1//===- MipsLegalizerInfo.cpp ------------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file implements the targeting of the Machinelegalizer class for Mips.
10/// \todo This should be generated by TableGen.
11//===----------------------------------------------------------------------===//
12
13#include "MipsLegalizerInfo.h"
14#include "MipsTargetMachine.h"
15#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
16#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
17#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
18#include "llvm/IR/IntrinsicsMips.h"
19
20using namespace llvm;
21
22struct TypesAndMemOps {
23 LLT ValTy;
24 LLT PtrTy;
25 unsigned MemSize;
26 bool SystemSupportsUnalignedAccess;
27};
28
29// Assumes power of 2 memory size. Subtargets that have only naturally-aligned
30// memory access need to perform additional legalization here.
31static bool isUnalignedMemmoryAccess(uint64_t MemSize, uint64_t AlignInBits) {
32 assert(isPowerOf2_64(MemSize) && "Expected power of 2 memory size");
33 assert(isPowerOf2_64(AlignInBits) && "Expected power of 2 align");
34 if (MemSize > AlignInBits)
35 return true;
36 return false;
37}
38
39static bool
40CheckTy0Ty1MemSizeAlign(const LegalityQuery &Query,
41 std::initializer_list<TypesAndMemOps> SupportedValues) {
42 unsigned QueryMemSize = Query.MMODescrs[0].MemoryTy.getSizeInBits();
43
44 // Non power of two memory access is never legal.
45 if (!isPowerOf2_64(Value: QueryMemSize))
46 return false;
47
48 for (auto &Val : SupportedValues) {
49 if (Val.ValTy != Query.Types[0])
50 continue;
51 if (Val.PtrTy != Query.Types[1])
52 continue;
53 if (Val.MemSize != QueryMemSize)
54 continue;
55 if (!Val.SystemSupportsUnalignedAccess &&
56 isUnalignedMemmoryAccess(MemSize: QueryMemSize, AlignInBits: Query.MMODescrs[0].AlignInBits))
57 return false;
58 return true;
59 }
60 return false;
61}
62
63static bool CheckTyN(unsigned N, const LegalityQuery &Query,
64 std::initializer_list<LLT> SupportedValues) {
65 return llvm::is_contained(Set: SupportedValues, Element: Query.Types[N]);
66}
67
68MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
69 using namespace TargetOpcode;
70
71 const LLT s1 = LLT::scalar(SizeInBits: 1);
72 const LLT s8 = LLT::scalar(SizeInBits: 8);
73 const LLT s16 = LLT::scalar(SizeInBits: 16);
74 const LLT s32 = LLT::scalar(SizeInBits: 32);
75 const LLT s64 = LLT::scalar(SizeInBits: 64);
76 const LLT v16s8 = LLT::fixed_vector(NumElements: 16, ScalarSizeInBits: 8);
77 const LLT v8s16 = LLT::fixed_vector(NumElements: 8, ScalarSizeInBits: 16);
78 const LLT v4s32 = LLT::fixed_vector(NumElements: 4, ScalarSizeInBits: 32);
79 const LLT v2s64 = LLT::fixed_vector(NumElements: 2, ScalarSizeInBits: 64);
80 const LLT p0 = LLT::pointer(AddressSpace: 0, SizeInBits: 32);
81
82 getActionDefinitionsBuilder(Opcodes: {G_ADD, G_SUB, G_MUL})
83 .legalIf(Predicate: [=, &ST](const LegalityQuery &Query) {
84 if (CheckTyN(N: 0, Query, SupportedValues: {s32}))
85 return true;
86 if (ST.hasMSA() && CheckTyN(N: 0, Query, SupportedValues: {v16s8, v8s16, v4s32, v2s64}))
87 return true;
88 return false;
89 })
90 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32);
91
92 getActionDefinitionsBuilder(Opcodes: {G_UADDO, G_UADDE, G_USUBO, G_USUBE, G_UMULO})
93 .lowerFor(Types: {{s32, s1}});
94
95 getActionDefinitionsBuilder(Opcode: G_UMULH)
96 .legalFor(Types: {s32})
97 .maxScalar(TypeIdx: 0, Ty: s32);
98
99 // MIPS32r6 does not have alignment restrictions for memory access.
100 // For MIPS32r5 and older memory access must be naturally-aligned i.e. aligned
101 // to at least a multiple of its own size. There is however a two instruction
102 // combination that performs 4 byte unaligned access (lwr/lwl and swl/swr)
103 // therefore 4 byte load and store are legal and will use NoAlignRequirements.
104 bool NoAlignRequirements = true;
105
106 getActionDefinitionsBuilder(Opcodes: {G_LOAD, G_STORE})
107 .legalIf(Predicate: [=, &ST](const LegalityQuery &Query) {
108 if (CheckTy0Ty1MemSizeAlign(
109 Query, SupportedValues: {{.ValTy: s32, .PtrTy: p0, .MemSize: 8, .SystemSupportsUnalignedAccess: NoAlignRequirements},
110 {.ValTy: s32, .PtrTy: p0, .MemSize: 16, .SystemSupportsUnalignedAccess: ST.systemSupportsUnalignedAccess()},
111 {.ValTy: s32, .PtrTy: p0, .MemSize: 32, .SystemSupportsUnalignedAccess: NoAlignRequirements},
112 {.ValTy: p0, .PtrTy: p0, .MemSize: 32, .SystemSupportsUnalignedAccess: NoAlignRequirements},
113 {.ValTy: s64, .PtrTy: p0, .MemSize: 64, .SystemSupportsUnalignedAccess: ST.systemSupportsUnalignedAccess()}}))
114 return true;
115 if (ST.hasMSA() && CheckTy0Ty1MemSizeAlign(
116 Query, SupportedValues: {{.ValTy: v16s8, .PtrTy: p0, .MemSize: 128, .SystemSupportsUnalignedAccess: NoAlignRequirements},
117 {.ValTy: v8s16, .PtrTy: p0, .MemSize: 128, .SystemSupportsUnalignedAccess: NoAlignRequirements},
118 {.ValTy: v4s32, .PtrTy: p0, .MemSize: 128, .SystemSupportsUnalignedAccess: NoAlignRequirements},
119 {.ValTy: v2s64, .PtrTy: p0, .MemSize: 128, .SystemSupportsUnalignedAccess: NoAlignRequirements}}))
120 return true;
121 return false;
122 })
123 // Custom lower scalar memory access, up to 8 bytes, for:
124 // - non-power-of-2 MemSizes
125 // - unaligned 2 or 8 byte MemSizes for MIPS32r5 and older
126 .customIf(Predicate: [=, &ST](const LegalityQuery &Query) {
127 if (!Query.Types[0].isScalar() || Query.Types[1] != p0 ||
128 Query.Types[0] == s1)
129 return false;
130
131 unsigned Size = Query.Types[0].getSizeInBits();
132 unsigned QueryMemSize = Query.MMODescrs[0].MemoryTy.getSizeInBits();
133 assert(QueryMemSize <= Size && "Scalar can't hold MemSize");
134
135 if (Size > 64 || QueryMemSize > 64)
136 return false;
137
138 if (!isPowerOf2_64(Value: Query.MMODescrs[0].MemoryTy.getSizeInBits()))
139 return true;
140
141 if (!ST.systemSupportsUnalignedAccess() &&
142 isUnalignedMemmoryAccess(MemSize: QueryMemSize,
143 AlignInBits: Query.MMODescrs[0].AlignInBits)) {
144 assert(QueryMemSize != 32 && "4 byte load and store are legal");
145 return true;
146 }
147
148 return false;
149 })
150 .minScalar(TypeIdx: 0, Ty: s32)
151 .lower();
152
153 getActionDefinitionsBuilder(Opcode: G_IMPLICIT_DEF)
154 .legalFor(Types: {s32, s64});
155
156 getActionDefinitionsBuilder(Opcode: G_UNMERGE_VALUES)
157 .legalFor(Types: {{s32, s64}});
158
159 getActionDefinitionsBuilder(Opcode: G_MERGE_VALUES)
160 .legalFor(Types: {{s64, s32}});
161
162 getActionDefinitionsBuilder(Opcodes: {G_ZEXTLOAD, G_SEXTLOAD})
163 .legalForTypesWithMemDesc(TypesAndMemDesc: {{.Type0: s32, .Type1: p0, .MemTy: s8, .Align: 8},
164 {.Type0: s32, .Type1: p0, .MemTy: s16, .Align: 8}})
165 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32);
166
167 getActionDefinitionsBuilder(Opcodes: {G_ZEXT, G_SEXT, G_ANYEXT})
168 .legalIf(Predicate: [](const LegalityQuery &Query) { return false; })
169 .maxScalar(TypeIdx: 0, Ty: s32);
170
171 getActionDefinitionsBuilder(Opcode: G_TRUNC)
172 .legalIf(Predicate: [](const LegalityQuery &Query) { return false; })
173 .maxScalar(TypeIdx: 1, Ty: s32);
174
175 getActionDefinitionsBuilder(Opcode: G_SELECT)
176 .legalForCartesianProduct(Types0: {p0, s32, s64}, Types1: {s32})
177 .minScalar(TypeIdx: 0, Ty: s32)
178 .minScalar(TypeIdx: 1, Ty: s32);
179
180 getActionDefinitionsBuilder(Opcode: G_BR).alwaysLegal();
181
182 getActionDefinitionsBuilder(Opcode: G_BRCOND)
183 .legalFor(Types: {s32})
184 .minScalar(TypeIdx: 0, Ty: s32);
185
186 getActionDefinitionsBuilder(Opcode: G_BRJT)
187 .legalFor(Types: {{p0, s32}});
188
189 getActionDefinitionsBuilder(Opcode: G_BRINDIRECT)
190 .legalFor(Types: {p0});
191
192 getActionDefinitionsBuilder(Opcode: G_PHI)
193 .legalFor(Types: {p0, s32, s64})
194 .minScalar(TypeIdx: 0, Ty: s32);
195
196 getActionDefinitionsBuilder(Opcodes: {G_AND, G_OR, G_XOR})
197 .legalFor(Types: {s32})
198 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32);
199
200 getActionDefinitionsBuilder(Opcodes: {G_SDIV, G_SREM, G_UDIV, G_UREM})
201 .legalIf(Predicate: [=, &ST](const LegalityQuery &Query) {
202 if (CheckTyN(N: 0, Query, SupportedValues: {s32}))
203 return true;
204 if (ST.hasMSA() && CheckTyN(N: 0, Query, SupportedValues: {v16s8, v8s16, v4s32, v2s64}))
205 return true;
206 return false;
207 })
208 .minScalar(TypeIdx: 0, Ty: s32)
209 .libcallFor(Types: {s64});
210
211 getActionDefinitionsBuilder(Opcodes: {G_SHL, G_ASHR, G_LSHR})
212 .legalFor(Types: {{s32, s32}})
213 .clampScalar(TypeIdx: 1, MinTy: s32, MaxTy: s32)
214 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32);
215
216 getActionDefinitionsBuilder(Opcode: G_ICMP)
217 .legalForCartesianProduct(Types0: {s32}, Types1: {s32, p0})
218 .clampScalar(TypeIdx: 1, MinTy: s32, MaxTy: s32)
219 .minScalar(TypeIdx: 0, Ty: s32);
220
221 getActionDefinitionsBuilder(Opcode: G_CONSTANT)
222 .legalFor(Types: {s32})
223 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32);
224
225 getActionDefinitionsBuilder(Opcodes: {G_PTR_ADD, G_INTTOPTR})
226 .legalFor(Types: {{p0, s32}});
227
228 getActionDefinitionsBuilder(Opcode: G_PTRTOINT)
229 .legalFor(Types: {{s32, p0}});
230
231 getActionDefinitionsBuilder(Opcode: G_FRAME_INDEX)
232 .legalFor(Types: {p0});
233
234 getActionDefinitionsBuilder(Opcodes: {G_GLOBAL_VALUE, G_JUMP_TABLE})
235 .legalFor(Types: {p0});
236
237 getActionDefinitionsBuilder(Opcode: G_DYN_STACKALLOC)
238 .lowerFor(Types: {{p0, s32}});
239
240 getActionDefinitionsBuilder(Opcode: G_VASTART)
241 .legalFor(Types: {p0});
242
243 getActionDefinitionsBuilder(Opcode: G_BSWAP)
244 .legalIf(Predicate: [=, &ST](const LegalityQuery &Query) {
245 if (ST.hasMips32r2() && CheckTyN(N: 0, Query, SupportedValues: {s32}))
246 return true;
247 return false;
248 })
249 .lowerIf(Predicate: [=, &ST](const LegalityQuery &Query) {
250 if (!ST.hasMips32r2() && CheckTyN(N: 0, Query, SupportedValues: {s32}))
251 return true;
252 return false;
253 })
254 .maxScalar(TypeIdx: 0, Ty: s32);
255
256 getActionDefinitionsBuilder(Opcode: G_BITREVERSE)
257 .lowerFor(Types: {s32})
258 .maxScalar(TypeIdx: 0, Ty: s32);
259
260 getActionDefinitionsBuilder(Opcode: G_CTLZ)
261 .legalFor(Types: {{s32, s32}})
262 .maxScalar(TypeIdx: 0, Ty: s32)
263 .maxScalar(TypeIdx: 1, Ty: s32);
264 getActionDefinitionsBuilder(Opcode: G_CTLZ_ZERO_POISON)
265 .lowerFor(Types: {{s32, s32}});
266
267 getActionDefinitionsBuilder(Opcode: G_CTTZ)
268 .lowerFor(Types: {{s32, s32}})
269 .maxScalar(TypeIdx: 0, Ty: s32)
270 .maxScalar(TypeIdx: 1, Ty: s32);
271 getActionDefinitionsBuilder(Opcode: G_CTTZ_ZERO_POISON)
272 .lowerFor(Types: {{s32, s32}, {s64, s64}});
273
274 getActionDefinitionsBuilder(Opcode: G_CTPOP)
275 .lowerFor(Types: {{s32, s32}})
276 .clampScalar(TypeIdx: 0, MinTy: s32, MaxTy: s32)
277 .clampScalar(TypeIdx: 1, MinTy: s32, MaxTy: s32);
278
279 // FP instructions
280 getActionDefinitionsBuilder(Opcode: G_FCONSTANT)
281 .legalFor(Types: {s32, s64});
282
283 getActionDefinitionsBuilder(Opcodes: {G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FABS, G_FSQRT})
284 .legalIf(Predicate: [=, &ST](const LegalityQuery &Query) {
285 if (CheckTyN(N: 0, Query, SupportedValues: {s32, s64}))
286 return true;
287 if (ST.hasMSA() && CheckTyN(N: 0, Query, SupportedValues: {v16s8, v8s16, v4s32, v2s64}))
288 return true;
289 return false;
290 });
291
292 getActionDefinitionsBuilder(Opcode: G_FCMP)
293 .legalFor(Types: {{s32, s32}, {s32, s64}})
294 .minScalar(TypeIdx: 0, Ty: s32);
295
296 getActionDefinitionsBuilder(Opcodes: {G_FCEIL, G_FFLOOR})
297 .libcallFor(Types: {s32, s64});
298
299 getActionDefinitionsBuilder(Opcode: G_FPEXT)
300 .legalFor(Types: {{s64, s32}});
301
302 getActionDefinitionsBuilder(Opcode: G_FPTRUNC)
303 .legalFor(Types: {{s32, s64}});
304
305 // FP to int conversion instructions
306 getActionDefinitionsBuilder(Opcode: G_FPTOSI)
307 .legalForCartesianProduct(Types0: {s32}, Types1: {s64, s32})
308 .libcallForCartesianProduct(Types0: {s64}, Types1: {s64, s32})
309 .minScalar(TypeIdx: 0, Ty: s32);
310
311 getActionDefinitionsBuilder(Opcode: G_FPTOUI)
312 .libcallForCartesianProduct(Types0: {s64}, Types1: {s64, s32})
313 .lowerForCartesianProduct(Types0: {s32}, Types1: {s64, s32})
314 .minScalar(TypeIdx: 0, Ty: s32);
315
316 // Int to FP conversion instructions
317 getActionDefinitionsBuilder(Opcode: G_SITOFP)
318 .legalForCartesianProduct(Types0: {s64, s32}, Types1: {s32})
319 .libcallForCartesianProduct(Types0: {s64, s32}, Types1: {s64})
320 .minScalar(TypeIdx: 1, Ty: s32);
321
322 getActionDefinitionsBuilder(Opcode: G_UITOFP)
323 .libcallForCartesianProduct(Types0: {s64, s32}, Types1: {s64})
324 .customForCartesianProduct(Types0: {s64, s32}, Types1: {s32})
325 .minScalar(TypeIdx: 1, Ty: s32);
326
327 getActionDefinitionsBuilder(Opcode: G_SEXT_INREG).lower();
328
329 getActionDefinitionsBuilder(Opcodes: {G_MEMCPY, G_MEMMOVE, G_MEMSET}).libcall();
330
331 getActionDefinitionsBuilder(Opcode: G_FENCE).alwaysLegal();
332 getActionDefinitionsBuilder(Opcodes: {G_TRAP, G_DEBUGTRAP, G_UBSANTRAP}).alwaysLegal();
333
334 verify(MII: *ST.getInstrInfo());
335}
336
337bool MipsLegalizerInfo::legalizeCustom(
338 LegalizerHelper &Helper, MachineInstr &MI,
339 LostDebugLocObserver &LocObserver) const {
340 using namespace TargetOpcode;
341
342 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
343 MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
344
345 const LLT s32 = LLT::scalar(SizeInBits: 32);
346 const LLT s64 = LLT::scalar(SizeInBits: 64);
347
348 switch (MI.getOpcode()) {
349 case G_LOAD:
350 case G_STORE: {
351 unsigned MemSize = (**MI.memoperands_begin()).getSize().getValue();
352 Register Val = MI.getOperand(i: 0).getReg();
353 unsigned Size = MRI.getType(Reg: Val).getSizeInBits();
354
355 MachineMemOperand *MMOBase = *MI.memoperands_begin();
356
357 assert(MemSize <= 8 && "MemSize is too large");
358 assert(Size <= 64 && "Scalar size is too large");
359
360 // Split MemSize into two, P2HalfMemSize is largest power of two smaller
361 // then MemSize. e.g. 8 = 4 + 4 , 6 = 4 + 2, 3 = 2 + 1.
362 unsigned P2HalfMemSize, RemMemSize;
363 if (isPowerOf2_64(Value: MemSize)) {
364 P2HalfMemSize = RemMemSize = MemSize / 2;
365 } else {
366 P2HalfMemSize = 1 << Log2_32(Value: MemSize);
367 RemMemSize = MemSize - P2HalfMemSize;
368 }
369
370 Register BaseAddr = MI.getOperand(i: 1).getReg();
371 LLT PtrTy = MRI.getType(Reg: BaseAddr);
372 MachineFunction &MF = MIRBuilder.getMF();
373 bool IsLittle = MF.getDataLayout().isLittleEndian();
374 unsigned FirstMemSize = IsLittle ? P2HalfMemSize : RemMemSize;
375
376 auto P2HalfMemOp = MF.getMachineMemOperand(
377 MMO: MMOBase, Offset: IsLittle ? 0 : RemMemSize, Size: P2HalfMemSize);
378 auto RemMemOp = MF.getMachineMemOperand(
379 MMO: MMOBase, Offset: IsLittle ? P2HalfMemSize : 0, Size: RemMemSize);
380
381 if (MI.getOpcode() == G_STORE) {
382 // Widen Val to s32 or s64 in order to create legal G_LSHR or G_UNMERGE.
383 if (Size < 32)
384 Val = MIRBuilder.buildAnyExt(Res: s32, Op: Val).getReg(Idx: 0);
385 if (Size > 32 && Size < 64)
386 Val = MIRBuilder.buildAnyExt(Res: s64, Op: Val).getReg(Idx: 0);
387
388 auto Offset = MIRBuilder.buildConstant(Res: s32, Val: FirstMemSize);
389 Register Addr = MIRBuilder.buildPtrAdd(Res: PtrTy, Op0: BaseAddr, Op1: Offset).getReg(Idx: 0);
390 Register LoAddr = IsLittle ? BaseAddr : Addr;
391 Register HiAddr = IsLittle ? Addr : BaseAddr;
392
393 if (MI.getOpcode() == G_STORE && MemSize <= 4) {
394 MIRBuilder.buildStore(Val, Addr: LoAddr, MMO&: *P2HalfMemOp);
395 auto C_P2Half_InBits = MIRBuilder.buildConstant(Res: s32, Val: P2HalfMemSize * 8);
396 auto Shift = MIRBuilder.buildLShr(Dst: s32, Src0: Val, Src1: C_P2Half_InBits);
397 MIRBuilder.buildStore(Val: Shift, Addr: HiAddr, MMO&: *RemMemOp);
398 } else {
399 auto Unmerge = MIRBuilder.buildUnmerge(Res: s32, Op: Val);
400 MIRBuilder.buildStore(Val: Unmerge.getReg(Idx: 0), Addr: LoAddr, MMO&: *P2HalfMemOp);
401 MIRBuilder.buildStore(Val: Unmerge.getReg(Idx: 1), Addr: HiAddr, MMO&: *RemMemOp);
402 }
403 }
404
405 if (MI.getOpcode() == G_LOAD) {
406
407 if (MemSize <= 4) {
408 // This is anyextending load, use 4 byte lwr/lwl.
409 auto *Load4MMO = MF.getMachineMemOperand(MMO: MMOBase, Offset: 0, Size: 4);
410
411 if (!IsLittle) {
412 auto Load = MIRBuilder.buildLoad(Res: s32, Addr: BaseAddr, MMO&: *Load4MMO);
413 auto ShiftAmt = MIRBuilder.buildConstant(Res: s32, Val: (4 - MemSize) * 8);
414 auto Shift = MIRBuilder.buildLShr(Dst: s32, Src0: Load, Src1: ShiftAmt);
415 MIRBuilder.buildAnyExtOrTrunc(Res: Val, Op: Shift);
416 } else if (Size == 32)
417 MIRBuilder.buildLoad(Res: Val, Addr: BaseAddr, MMO&: *Load4MMO);
418 else {
419 auto Load = MIRBuilder.buildLoad(Res: s32, Addr: BaseAddr, MMO&: *Load4MMO);
420 MIRBuilder.buildTrunc(Res: Val, Op: Load.getReg(Idx: 0));
421 }
422
423 } else {
424 auto Offset = MIRBuilder.buildConstant(Res: s32, Val: FirstMemSize);
425 Register Addr =
426 MIRBuilder.buildPtrAdd(Res: PtrTy, Op0: BaseAddr, Op1: Offset).getReg(Idx: 0);
427 Register LoAddr = IsLittle ? BaseAddr : Addr;
428 Register HiAddr = IsLittle ? Addr : BaseAddr;
429
430 auto Load_P2Half = MIRBuilder.buildLoad(Res: s32, Addr: LoAddr, MMO&: *P2HalfMemOp);
431 auto Load_Rem = MIRBuilder.buildLoad(Res: s32, Addr: HiAddr, MMO&: *RemMemOp);
432
433 if (Size == 64)
434 MIRBuilder.buildMergeLikeInstr(Res: Val, Ops: {Load_P2Half, Load_Rem});
435 else {
436 auto Merge =
437 MIRBuilder.buildMergeLikeInstr(Res: s64, Ops: {Load_P2Half, Load_Rem});
438 MIRBuilder.buildTrunc(Res: Val, Op: Merge);
439 }
440 }
441 }
442 MI.eraseFromParent();
443 break;
444 }
445 case G_UITOFP: {
446 Register Dst = MI.getOperand(i: 0).getReg();
447 Register Src = MI.getOperand(i: 1).getReg();
448 LLT DstTy = MRI.getType(Reg: Dst);
449 LLT SrcTy = MRI.getType(Reg: Src);
450
451 if (SrcTy != s32)
452 return false;
453 if (DstTy != s32 && DstTy != s64)
454 return false;
455
456 // Let 0xABCDEFGH be given unsigned in MI.getOperand(1). First let's convert
457 // unsigned to double. Mantissa has 52 bits so we use following trick:
458 // First make floating point bit mask 0x43300000ABCDEFGH.
459 // Mask represents 2^52 * 0x1.00000ABCDEFGH i.e. 0x100000ABCDEFGH.0 .
460 // Next, subtract 2^52 * 0x1.0000000000000 i.e. 0x10000000000000.0 from it.
461 // Done. Trunc double to float if needed.
462
463 auto C_HiMask = MIRBuilder.buildConstant(Res: s32, UINT32_C(0x43300000));
464 auto Bitcast =
465 MIRBuilder.buildMergeLikeInstr(Res: s64, Ops: {Src, C_HiMask.getReg(Idx: 0)});
466
467 MachineInstrBuilder TwoP52FP = MIRBuilder.buildFConstant(
468 Res: s64, Val: llvm::bit_cast<double>(UINT64_C(0x4330000000000000)));
469
470 if (DstTy == s64)
471 MIRBuilder.buildFSub(Dst, Src0: Bitcast, Src1: TwoP52FP);
472 else {
473 MachineInstrBuilder ResF64 = MIRBuilder.buildFSub(Dst: s64, Src0: Bitcast, Src1: TwoP52FP);
474 MIRBuilder.buildFPTrunc(Res: Dst, Op: ResF64);
475 }
476
477 MI.eraseFromParent();
478 break;
479 }
480 default:
481 return false;
482 }
483
484 return true;
485}
486
487static bool SelectMSA3OpIntrinsic(MachineInstr &MI, unsigned Opcode,
488 MachineIRBuilder &MIRBuilder,
489 const MipsSubtarget &ST) {
490 assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA.");
491 MIRBuilder.buildInstr(Opcode)
492 .add(MO: MI.getOperand(i: 0))
493 .add(MO: MI.getOperand(i: 2))
494 .add(MO: MI.getOperand(i: 3))
495 .constrainAllUses(TII: MIRBuilder.getTII(), TRI: *ST.getRegisterInfo(),
496 RBI: *ST.getRegBankInfo());
497 MI.eraseFromParent();
498 return true;
499}
500
501static bool MSA3OpIntrinsicToGeneric(MachineInstr &MI, unsigned Opcode,
502 MachineIRBuilder &MIRBuilder,
503 const MipsSubtarget &ST) {
504 assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA.");
505 MIRBuilder.buildInstr(Opcode)
506 .add(MO: MI.getOperand(i: 0))
507 .add(MO: MI.getOperand(i: 2))
508 .add(MO: MI.getOperand(i: 3));
509 MI.eraseFromParent();
510 return true;
511}
512
513static bool MSA2OpIntrinsicToGeneric(MachineInstr &MI, unsigned Opcode,
514 MachineIRBuilder &MIRBuilder,
515 const MipsSubtarget &ST) {
516 assert(ST.hasMSA() && "MSA intrinsic not supported on target without MSA.");
517 MIRBuilder.buildInstr(Opcode)
518 .add(MO: MI.getOperand(i: 0))
519 .add(MO: MI.getOperand(i: 2));
520 MI.eraseFromParent();
521 return true;
522}
523
524bool MipsLegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
525 MachineInstr &MI) const {
526 MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
527 const MipsSubtarget &ST = MI.getMF()->getSubtarget<MipsSubtarget>();
528
529 switch (cast<GIntrinsic>(Val&: MI).getIntrinsicID()) {
530 case Intrinsic::vacopy: {
531 MachinePointerInfo MPO;
532 LLT PtrTy = LLT::pointer(AddressSpace: 0, SizeInBits: 32);
533 auto Tmp =
534 MIRBuilder.buildLoad(Res: PtrTy, Addr: MI.getOperand(i: 2),
535 MMO&: *MI.getMF()->getMachineMemOperand(
536 PtrInfo: MPO, F: MachineMemOperand::MOLoad, MemTy: PtrTy, BaseAlignment: Align(4)));
537 MIRBuilder.buildStore(Val: Tmp, Addr: MI.getOperand(i: 1),
538 MMO&: *MI.getMF()->getMachineMemOperand(
539 PtrInfo: MPO, F: MachineMemOperand::MOStore, MemTy: PtrTy, BaseAlignment: Align(4)));
540 MI.eraseFromParent();
541 return true;
542 }
543 case Intrinsic::mips_addv_b:
544 case Intrinsic::mips_addv_h:
545 case Intrinsic::mips_addv_w:
546 case Intrinsic::mips_addv_d:
547 return MSA3OpIntrinsicToGeneric(MI, Opcode: TargetOpcode::G_ADD, MIRBuilder, ST);
548 case Intrinsic::mips_addvi_b:
549 return SelectMSA3OpIntrinsic(MI, Opcode: Mips::ADDVI_B, MIRBuilder, ST);
550 case Intrinsic::mips_addvi_h:
551 return SelectMSA3OpIntrinsic(MI, Opcode: Mips::ADDVI_H, MIRBuilder, ST);
552 case Intrinsic::mips_addvi_w:
553 return SelectMSA3OpIntrinsic(MI, Opcode: Mips::ADDVI_W, MIRBuilder, ST);
554 case Intrinsic::mips_addvi_d:
555 return SelectMSA3OpIntrinsic(MI, Opcode: Mips::ADDVI_D, MIRBuilder, ST);
556 case Intrinsic::mips_subv_b:
557 case Intrinsic::mips_subv_h:
558 case Intrinsic::mips_subv_w:
559 case Intrinsic::mips_subv_d:
560 return MSA3OpIntrinsicToGeneric(MI, Opcode: TargetOpcode::G_SUB, MIRBuilder, ST);
561 case Intrinsic::mips_subvi_b:
562 return SelectMSA3OpIntrinsic(MI, Opcode: Mips::SUBVI_B, MIRBuilder, ST);
563 case Intrinsic::mips_subvi_h:
564 return SelectMSA3OpIntrinsic(MI, Opcode: Mips::SUBVI_H, MIRBuilder, ST);
565 case Intrinsic::mips_subvi_w:
566 return SelectMSA3OpIntrinsic(MI, Opcode: Mips::SUBVI_W, MIRBuilder, ST);
567 case Intrinsic::mips_subvi_d:
568 return SelectMSA3OpIntrinsic(MI, Opcode: Mips::SUBVI_D, MIRBuilder, ST);
569 case Intrinsic::mips_mulv_b:
570 case Intrinsic::mips_mulv_h:
571 case Intrinsic::mips_mulv_w:
572 case Intrinsic::mips_mulv_d:
573 return MSA3OpIntrinsicToGeneric(MI, Opcode: TargetOpcode::G_MUL, MIRBuilder, ST);
574 case Intrinsic::mips_div_s_b:
575 case Intrinsic::mips_div_s_h:
576 case Intrinsic::mips_div_s_w:
577 case Intrinsic::mips_div_s_d:
578 return MSA3OpIntrinsicToGeneric(MI, Opcode: TargetOpcode::G_SDIV, MIRBuilder, ST);
579 case Intrinsic::mips_mod_s_b:
580 case Intrinsic::mips_mod_s_h:
581 case Intrinsic::mips_mod_s_w:
582 case Intrinsic::mips_mod_s_d:
583 return MSA3OpIntrinsicToGeneric(MI, Opcode: TargetOpcode::G_SREM, MIRBuilder, ST);
584 case Intrinsic::mips_div_u_b:
585 case Intrinsic::mips_div_u_h:
586 case Intrinsic::mips_div_u_w:
587 case Intrinsic::mips_div_u_d:
588 return MSA3OpIntrinsicToGeneric(MI, Opcode: TargetOpcode::G_UDIV, MIRBuilder, ST);
589 case Intrinsic::mips_mod_u_b:
590 case Intrinsic::mips_mod_u_h:
591 case Intrinsic::mips_mod_u_w:
592 case Intrinsic::mips_mod_u_d:
593 return MSA3OpIntrinsicToGeneric(MI, Opcode: TargetOpcode::G_UREM, MIRBuilder, ST);
594 case Intrinsic::mips_fadd_w:
595 case Intrinsic::mips_fadd_d:
596 return MSA3OpIntrinsicToGeneric(MI, Opcode: TargetOpcode::G_FADD, MIRBuilder, ST);
597 case Intrinsic::mips_fsub_w:
598 case Intrinsic::mips_fsub_d:
599 return MSA3OpIntrinsicToGeneric(MI, Opcode: TargetOpcode::G_FSUB, MIRBuilder, ST);
600 case Intrinsic::mips_fmul_w:
601 case Intrinsic::mips_fmul_d:
602 return MSA3OpIntrinsicToGeneric(MI, Opcode: TargetOpcode::G_FMUL, MIRBuilder, ST);
603 case Intrinsic::mips_fdiv_w:
604 case Intrinsic::mips_fdiv_d:
605 return MSA3OpIntrinsicToGeneric(MI, Opcode: TargetOpcode::G_FDIV, MIRBuilder, ST);
606 case Intrinsic::mips_fmax_a_w:
607 return SelectMSA3OpIntrinsic(MI, Opcode: Mips::FMAX_A_W, MIRBuilder, ST);
608 case Intrinsic::mips_fmax_a_d:
609 return SelectMSA3OpIntrinsic(MI, Opcode: Mips::FMAX_A_D, MIRBuilder, ST);
610 case Intrinsic::mips_fsqrt_w:
611 return MSA2OpIntrinsicToGeneric(MI, Opcode: TargetOpcode::G_FSQRT, MIRBuilder, ST);
612 case Intrinsic::mips_fsqrt_d:
613 return MSA2OpIntrinsicToGeneric(MI, Opcode: TargetOpcode::G_FSQRT, MIRBuilder, ST);
614 default:
615 break;
616 }
617 return true;
618}
619