1//===---- RISCVISelDAGToDAG.h - A dag to dag inst selector for RISC-V -----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines an instruction selector for the RISC-V target.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H
14#define LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H
15
16#include "RISCV.h"
17#include "RISCVTargetMachine.h"
18#include "llvm/CodeGen/SelectionDAGISel.h"
19#include "llvm/Support/KnownBits.h"
20
21// RISC-V specific code to select RISC-V machine instructions for
22// SelectionDAG operations.
23namespace llvm {
24class RISCVDAGToDAGISel : public SelectionDAGISel {
25 const RISCVSubtarget *Subtarget = nullptr;
26
27public:
28 RISCVDAGToDAGISel() = delete;
29
30 explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine,
31 CodeGenOptLevel OptLevel)
32 : SelectionDAGISel(TargetMachine, OptLevel) {}
33
34 bool runOnMachineFunction(MachineFunction &MF) override {
35 Subtarget = &MF.getSubtarget<RISCVSubtarget>();
36 return SelectionDAGISel::runOnMachineFunction(mf&: MF);
37 }
38
39 void PreprocessISelDAG() override;
40 void PostprocessISelDAG() override;
41
42 void Select(SDNode *Node) override;
43
44 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
45 InlineAsm::ConstraintCode ConstraintID,
46 std::vector<SDValue> &OutOps) override;
47
48 bool areOffsetsWithinAlignment(SDValue Addr, Align Alignment);
49
50 bool SelectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset);
51 bool SelectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset);
52 bool SelectAddrRegImm26(SDValue Addr, SDValue &Base, SDValue &Offset);
53 bool SelectAddrRegImm9(SDValue Addr, SDValue &Base, SDValue &Offset);
54 bool SelectAddrRegImmLsb00000(SDValue Addr, SDValue &Base, SDValue &Offset);
55
56 bool SelectAddrRegRegScale(SDValue Addr, unsigned MaxShiftAmount,
57 SDValue &Base, SDValue &Index, SDValue &Scale);
58
59 template <unsigned MaxShift>
60 bool SelectAddrRegRegScale(SDValue Addr, SDValue &Base, SDValue &Index,
61 SDValue &Scale) {
62 return SelectAddrRegRegScale(Addr, MaxShiftAmount: MaxShift, Base, Index, Scale);
63 }
64
65 bool SelectAddrRegZextRegScale(SDValue Addr, unsigned MaxShiftAmount,
66 unsigned Bits, SDValue &Base, SDValue &Index,
67 SDValue &Scale);
68
69 template <unsigned MaxShift, unsigned Bits>
70 bool SelectAddrRegZextRegScale(SDValue Addr, SDValue &Base, SDValue &Index,
71 SDValue &Scale) {
72 return SelectAddrRegZextRegScale(Addr, MaxShiftAmount: MaxShift, Bits, Base, Index, Scale);
73 }
74
75 bool SelectAddrRegReg(SDValue Addr, SDValue &Base, SDValue &Offset);
76
77 bool tryShrinkShlLogicImm(SDNode *Node);
78 bool trySignedBitfieldExtract(SDNode *Node);
79 bool trySignedBitfieldInsertInSign(SDNode *Node);
80 bool tryUnsignedBitfieldExtract(SDNode *Node, const SDLoc &DL, MVT VT,
81 SDValue X, unsigned Msb, unsigned Lsb);
82 bool tryUnsignedBitfieldInsertInZero(SDNode *Node, const SDLoc &DL, MVT VT,
83 SDValue X, unsigned Msb, unsigned Lsb);
84 bool tryIndexedLoad(SDNode *Node);
85 bool tryWideningMulAcc(SDNode *Node, const SDLoc &DL);
86
87 bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt);
88 bool selectShiftMaskXLen(SDValue N, SDValue &ShAmt) {
89 return selectShiftMask(N, ShiftWidth: Subtarget->getXLen(), ShAmt);
90 }
91 template <unsigned Size> bool selectShiftMask(SDValue N, SDValue &ShAmt) {
92 return selectShiftMask(N, ShiftWidth: Size, ShAmt);
93 }
94
95 bool selectSETCC(SDValue N, ISD::CondCode ExpectedCCVal, SDValue &Val);
96 bool selectSETNE(SDValue N, SDValue &Val) {
97 return selectSETCC(N, ExpectedCCVal: ISD::SETNE, Val);
98 }
99 bool selectSETEQ(SDValue N, SDValue &Val) {
100 return selectSETCC(N, ExpectedCCVal: ISD::SETEQ, Val);
101 }
102
103 bool selectSExtBits(SDValue N, unsigned Bits, SDValue &Val);
104 template <unsigned Bits> bool selectSExtBits(SDValue N, SDValue &Val) {
105 return selectSExtBits(N, Bits, Val);
106 }
107 bool selectZExtBits(SDValue N, unsigned Bits, SDValue &Val);
108 template <unsigned Bits> bool selectZExtBits(SDValue N, SDValue &Val) {
109 return selectZExtBits(N, Bits, Val);
110 }
111
112 bool selectSHXADDOp(SDValue N, unsigned ShAmt, SDValue &Val);
113 template <unsigned ShAmt> bool selectSHXADDOp(SDValue N, SDValue &Val) {
114 return selectSHXADDOp(N, ShAmt, Val);
115 }
116
117 bool selectSHXADD_UWOp(SDValue N, unsigned ShAmt, SDValue &Val);
118 template <unsigned ShAmt> bool selectSHXADD_UWOp(SDValue N, SDValue &Val) {
119 return selectSHXADD_UWOp(N, ShAmt, Val);
120 }
121
122 bool selectZExtImm32(SDValue N, SDValue &Val);
123 bool selectNegImm(SDValue N, SDValue &Val);
124 bool selectInvLogicImm(SDValue N, SDValue &Val);
125
126 bool orDisjoint(const SDNode *Node) const;
127 bool hasAllNBitUsers(SDNode *Node, unsigned Bits,
128 const unsigned Depth = 0) const;
129 bool hasAllBUsers(SDNode *Node) const { return hasAllNBitUsers(Node, Bits: 8); }
130 bool hasAllHUsers(SDNode *Node) const { return hasAllNBitUsers(Node, Bits: 16); }
131 bool hasAllWUsers(SDNode *Node) const { return hasAllNBitUsers(Node, Bits: 32); }
132
133 bool selectSimm5Shl2(SDValue N, SDValue &Simm5, SDValue &Shl2);
134
135 bool selectVLOp(SDValue N, SDValue &VL);
136
137 bool selectVSplat(SDValue N, SDValue &SplatVal);
138 bool selectVSplatSimm5(SDValue N, SDValue &SplatVal);
139 bool selectVSplatUimm(SDValue N, unsigned Bits, SDValue &SplatVal);
140 template <unsigned Bits> bool selectVSplatUimmBits(SDValue N, SDValue &Val) {
141 return selectVSplatUimm(N, Bits, SplatVal&: Val);
142 }
143 bool selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal);
144 bool selectVSplatSimm5Plus1NoDec(SDValue N, SDValue &SplatVal);
145 bool selectVSplatSimm5Plus1NonZero(SDValue N, SDValue &SplatVal);
146 bool selectVSplatImm64Neg(SDValue N, SDValue &SplatVal);
147 // Matches the splat of a value which can be extended or truncated, such that
148 // only the bottom 8 bits are preserved.
149 bool selectLow8BitsVSplat(SDValue N, SDValue &SplatVal);
150 bool selectScalarFPAsInt(SDValue N, SDValue &Imm);
151
152 bool selectRVVSimm5(SDValue N, unsigned Width, SDValue &Imm);
153 template <unsigned Width> bool selectRVVSimm5(SDValue N, SDValue &Imm) {
154 return selectRVVSimm5(N, Width, Imm);
155 }
156
157 bool selectVMNOTOp(SDValue N, SDValue &Res);
158 bool selectVMNOT_VLOp(SDNode *Parent, SDValue N, SDValue &Res);
159
160 void addVectorLoadStoreOperands(SDNode *Node, unsigned SEWImm,
161 const SDLoc &DL, unsigned CurOp,
162 bool IsMasked, bool IsStridedOrIndexed,
163 SmallVectorImpl<SDValue> &Operands,
164 bool IsLoad = false, MVT *IndexVT = nullptr);
165
166 void selectVLSEG(SDNode *Node, unsigned NF, bool IsMasked, bool IsStrided);
167 void selectVLSEGFF(SDNode *Node, unsigned NF, bool IsMasked);
168 void selectVLXSEG(SDNode *Node, unsigned NF, bool IsMasked, bool IsOrdered);
169 void selectVSSEG(SDNode *Node, unsigned NF, bool IsMasked, bool IsStrided);
170 void selectVSXSEG(SDNode *Node, unsigned NF, bool IsMasked, bool IsOrdered);
171
172 void selectVSETVLI(SDNode *Node);
173 void selectXSfmmVSET(SDNode *Node);
174
175 void selectSF_VC_X_SE(SDNode *Node);
176
177 // Return the RISC-V condition code that matches the given DAG integer
178 // condition code. The CondCode must be one of those supported by the RISC-V
179 // ISA (see translateSetCCForBranch).
180 static RISCVCC::CondCode getRISCVCCForIntCC(ISD::CondCode CC) {
181 switch (CC) {
182 default:
183 llvm_unreachable("Unsupported CondCode");
184 case ISD::SETEQ:
185 return RISCVCC::COND_EQ;
186 case ISD::SETNE:
187 return RISCVCC::COND_NE;
188 case ISD::SETLT:
189 return RISCVCC::COND_LT;
190 case ISD::SETGE:
191 return RISCVCC::COND_GE;
192 case ISD::SETULT:
193 return RISCVCC::COND_LTU;
194 case ISD::SETUGE:
195 return RISCVCC::COND_GEU;
196 }
197 }
198
199// Include the pieces autogenerated from the target description.
200#define GET_DAGISEL_DECL
201#include "RISCVGenDAGISel.inc"
202
203private:
204 bool doPeepholeSExtW(SDNode *Node);
205 bool doPeepholeMaskedRVV(MachineSDNode *Node);
206 bool doPeepholeNoRegPassThru();
207 bool performCombineVMergeAndVOps(SDNode *N);
208 bool selectImm64IfCheaper(int64_t Imm, int64_t OrigImm, SDValue N,
209 SDValue &Val);
210};
211
212class RISCVDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
213public:
214 static char ID;
215 explicit RISCVDAGToDAGISelLegacy(RISCVTargetMachine &TargetMachine,
216 CodeGenOptLevel OptLevel);
217};
218
219} // namespace llvm
220
221#endif
222