1//===---- RISCVISelDAGToDAG.h - A dag to dag inst selector for RISC-V -----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines an instruction selector for the RISC-V target.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H
14#define LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H
15
16#include "RISCV.h"
17#include "RISCVTargetMachine.h"
18#include "llvm/CodeGen/SelectionDAGISel.h"
19#include "llvm/Support/KnownBits.h"
20
21// RISC-V specific code to select RISC-V machine instructions for
22// SelectionDAG operations.
23namespace llvm {
24class RISCVDAGToDAGISel : public SelectionDAGISel {
25 const RISCVSubtarget *Subtarget = nullptr;
26
27public:
28 RISCVDAGToDAGISel() = delete;
29
30 explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine,
31 CodeGenOptLevel OptLevel)
32 : SelectionDAGISel(TargetMachine, OptLevel) {}
33
34 bool runOnMachineFunction(MachineFunction &MF) override {
35 Subtarget = &MF.getSubtarget<RISCVSubtarget>();
36 return SelectionDAGISel::runOnMachineFunction(mf&: MF);
37 }
38
39 void PreprocessISelDAG() override;
40 void PostprocessISelDAG() override;
41
42 void Select(SDNode *Node) override;
43
44 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
45 InlineAsm::ConstraintCode ConstraintID,
46 std::vector<SDValue> &OutOps) override;
47
48 bool areOffsetsWithinAlignment(SDValue Addr, Align Alignment);
49
50 bool SelectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset);
51 bool SelectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset);
52 bool SelectAddrRegImm26(SDValue Addr, SDValue &Base, SDValue &Offset);
53 bool SelectAddrRegImm9(SDValue Addr, SDValue &Base, SDValue &Offset);
54 bool SelectAddrRegImmLsb00000(SDValue Addr, SDValue &Base, SDValue &Offset);
55
56 bool SelectAddrRegRegScale(SDValue Addr, ArrayRef<unsigned> Amounts,
57 SDValue &Base, SDValue &Index, SDValue &Scale);
58
59 template <unsigned ShiftAmount>
60 bool SelectAddrRegRegFixedScale(SDValue Addr, SDValue &Base, SDValue &Index) {
61 SDValue Scale;
62 if (!SelectAddrRegRegScale(Addr, Amounts: ShiftAmount, Base, Index, Scale))
63 return false;
64 assert(Scale->getAsZExtVal() == ShiftAmount &&
65 "ShiftAmount doesn't match!");
66 return true;
67 }
68
69 template <unsigned MaxShift>
70 bool SelectAddrRegRegScale(SDValue Addr, SDValue &Base, SDValue &Index,
71 SDValue &Scale) {
72 std::array<unsigned, MaxShift + 1> Amounts;
73 std::iota(Amounts.begin(), Amounts.end(), 0);
74 return SelectAddrRegRegScale(Addr, Amounts, Base, Index, Scale);
75 }
76
77 bool SelectAddrRegZextRegScale(SDValue Addr, ArrayRef<unsigned> Amounts,
78 unsigned Bits, SDValue &Base, SDValue &Index,
79 SDValue &Scale);
80
81 template <unsigned ShiftAmount, unsigned Bits>
82 bool SelectAddrRegZextRegFixedScale(SDValue Addr, SDValue &Base,
83 SDValue &Index) {
84 SDValue Scale;
85 if (!SelectAddrRegZextRegScale(Addr, Amounts: ShiftAmount, Bits, Base, Index, Scale))
86 return false;
87 assert(Scale->getAsZExtVal() == ShiftAmount &&
88 "ShiftAmount doesn't match!");
89 return true;
90 }
91
92 template <unsigned MaxShift, unsigned Bits>
93 bool SelectAddrRegZextRegScale(SDValue Addr, SDValue &Base, SDValue &Index,
94 SDValue &Scale) {
95 std::array<unsigned, MaxShift + 1> Amounts;
96 std::iota(Amounts.begin(), Amounts.end(), 0);
97 return SelectAddrRegZextRegScale(Addr, Amounts, Bits, Base, Index, Scale);
98 }
99
100 bool SelectAddrRegReg(SDValue Addr, SDValue &Base, SDValue &Offset);
101
102 bool tryShrinkShlLogicImm(SDNode *Node);
103 bool trySignedBitfieldExtract(SDNode *Node);
104 bool trySignedBitfieldInsertInSign(SDNode *Node);
105 bool tryUnsignedBitfieldExtract(SDNode *Node, const SDLoc &DL, MVT VT,
106 SDValue X, unsigned Msb, unsigned Lsb);
107 bool tryUnsignedBitfieldInsertInZero(SDNode *Node, const SDLoc &DL, MVT VT,
108 SDValue X, unsigned Msb, unsigned Lsb);
109 bool tryIndexedLoad(SDNode *Node);
110 bool tryWideningMulAcc(SDNode *Node, const SDLoc &DL);
111
112 bool selectShiftMask(SDValue N, unsigned ShiftWidth, SDValue &ShAmt);
113 bool selectShiftMaskXLen(SDValue N, SDValue &ShAmt) {
114 return selectShiftMask(N, ShiftWidth: Subtarget->getXLen(), ShAmt);
115 }
116 template <unsigned Size> bool selectShiftMask(SDValue N, SDValue &ShAmt) {
117 return selectShiftMask(N, ShiftWidth: Size, ShAmt);
118 }
119
120 bool selectSETCC(SDValue N, ISD::CondCode ExpectedCCVal, SDValue &Val,
121 bool OneUse);
122 template <bool OneUse = false> bool selectSETNE(SDValue N, SDValue &Val) {
123 return selectSETCC(N, ExpectedCCVal: ISD::SETNE, Val, OneUse);
124 }
125 template <bool OneUse = false> bool selectSETEQ(SDValue N, SDValue &Val) {
126 return selectSETCC(N, ExpectedCCVal: ISD::SETEQ, Val, OneUse);
127 }
128
129 bool selectSExtBits(SDValue N, unsigned Bits, SDValue &Val);
130 template <unsigned Bits> bool selectSExtBits(SDValue N, SDValue &Val) {
131 return selectSExtBits(N, Bits, Val);
132 }
133 bool selectZExtBits(SDValue N, unsigned Bits, SDValue &Val);
134 template <unsigned Bits> bool selectZExtBits(SDValue N, SDValue &Val) {
135 return selectZExtBits(N, Bits, Val);
136 }
137
138 bool selectSHXADDOp(SDValue N, unsigned ShAmt, SDValue &Val);
139 template <unsigned ShAmt> bool selectSHXADDOp(SDValue N, SDValue &Val) {
140 return selectSHXADDOp(N, ShAmt, Val);
141 }
142
143 bool selectSHXADD_UWOp(SDValue N, unsigned ShAmt, SDValue &Val);
144 template <unsigned ShAmt> bool selectSHXADD_UWOp(SDValue N, SDValue &Val) {
145 return selectSHXADD_UWOp(N, ShAmt, Val);
146 }
147
148 bool selectZExtImm32(SDValue N, SDValue &Val);
149 bool selectNegImm(SDValue N, SDValue &Val);
150 bool selectInvLogicImm(SDValue N, SDValue &Val);
151
152 bool orDisjoint(const SDNode *Node) const;
153 bool hasAllNBitUsers(SDNode *Node, unsigned Bits,
154 const unsigned Depth = 0) const;
155 bool hasAllBUsers(SDNode *Node) const { return hasAllNBitUsers(Node, Bits: 8); }
156 bool hasAllHUsers(SDNode *Node) const { return hasAllNBitUsers(Node, Bits: 16); }
157 bool hasAllWUsers(SDNode *Node) const { return hasAllNBitUsers(Node, Bits: 32); }
158
159 bool selectSimm5Shl2(SDValue N, SDValue &Simm5, SDValue &Shl2);
160
161 bool selectVLOp(SDValue N, SDValue &VL);
162
163 bool selectVSplat(SDValue N, SDValue &SplatVal);
164 bool selectVSplatSimm5(SDValue N, SDValue &SplatVal);
165 bool selectVSplatUimm(SDValue N, unsigned Bits, SDValue &SplatVal);
166 template <unsigned Bits> bool selectVSplatUimmBits(SDValue N, SDValue &Val) {
167 return selectVSplatUimm(N, Bits, SplatVal&: Val);
168 }
169 bool selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal);
170 bool selectVSplatSimm5Plus1NoDec(SDValue N, SDValue &SplatVal);
171 bool selectVSplatSimm5Plus1NonZero(SDValue N, SDValue &SplatVal);
172 bool selectVSplatImm64Neg(SDValue N, SDValue &SplatVal);
173 // Matches the splat of a value which can be extended or truncated, such that
174 // only the bottom 8 bits are preserved.
175 bool selectLow8BitsVSplat(SDValue N, SDValue &SplatVal);
176 bool selectScalarFPAsInt(SDValue N, SDValue &Imm);
177
178 bool selectRVVSimm5(SDValue N, unsigned Width, SDValue &Imm);
179 template <unsigned Width> bool selectRVVSimm5(SDValue N, SDValue &Imm) {
180 return selectRVVSimm5(N, Width, Imm);
181 }
182
183 bool selectVMNOTOp(SDValue N, SDValue &Res);
184 bool selectVMNOT_VLOp(SDNode *Parent, SDValue N, SDValue &Res);
185
186 void addVectorLoadStoreOperands(SDNode *Node, unsigned SEWImm,
187 const SDLoc &DL, unsigned CurOp,
188 bool IsMasked, bool IsStridedOrIndexed,
189 SmallVectorImpl<SDValue> &Operands,
190 bool IsLoad = false, MVT *IndexVT = nullptr);
191
192 void selectVLSEG(SDNode *Node, unsigned NF, bool IsMasked, bool IsStrided);
193 void selectVLSEGFF(SDNode *Node, unsigned NF, bool IsMasked);
194 void selectVLXSEG(SDNode *Node, unsigned NF, bool IsMasked, bool IsOrdered);
195 void selectVSSEG(SDNode *Node, unsigned NF, bool IsMasked, bool IsStrided);
196 void selectVSXSEG(SDNode *Node, unsigned NF, bool IsMasked, bool IsOrdered);
197
198 void selectVSETVLI(SDNode *Node);
199 void selectXSfmmVSET(SDNode *Node);
200
201 void selectSF_VC_X_SE(SDNode *Node);
202
203 // Return the RISC-V condition code that matches the given DAG integer
204 // condition code. The CondCode must be one of those supported by the RISC-V
205 // ISA (see translateSetCCForBranch).
206 static RISCVCC::CondCode getRISCVCCForIntCC(ISD::CondCode CC) {
207 switch (CC) {
208 default:
209 llvm_unreachable("Unsupported CondCode");
210 case ISD::SETEQ:
211 return RISCVCC::COND_EQ;
212 case ISD::SETNE:
213 return RISCVCC::COND_NE;
214 case ISD::SETLT:
215 return RISCVCC::COND_LT;
216 case ISD::SETGE:
217 return RISCVCC::COND_GE;
218 case ISD::SETULT:
219 return RISCVCC::COND_LTU;
220 case ISD::SETUGE:
221 return RISCVCC::COND_GEU;
222 }
223 }
224
225// Include the pieces autogenerated from the target description.
226#define GET_DAGISEL_DECL
227#include "RISCVGenDAGISel.inc"
228
229private:
230 bool doPeepholeSExtW(SDNode *Node);
231 bool doPeepholeMaskedRVV(MachineSDNode *Node);
232 bool doPeepholeNoRegPassThru();
233 bool selectImm64IfCheaper(int64_t Imm, int64_t OrigImm, SDValue N,
234 SDValue &Val);
235};
236
237class RISCVDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
238public:
239 static char ID;
240 explicit RISCVDAGToDAGISelLegacy(RISCVTargetMachine &TargetMachine,
241 CodeGenOptLevel OptLevel);
242};
243
244} // namespace llvm
245
246#endif
247