1//===-- RISCVISelDAGToDAG.cpp - A dag to dag inst selector for RISC-V -----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines an instruction selector for the RISC-V target.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVISelDAGToDAG.h"
14#include "MCTargetDesc/RISCVBaseInfo.h"
15#include "MCTargetDesc/RISCVMCTargetDesc.h"
16#include "MCTargetDesc/RISCVMatInt.h"
17#include "RISCVISelLowering.h"
18#include "RISCVInstrInfo.h"
19#include "RISCVSelectionDAGInfo.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/SDPatternMatch.h"
22#include "llvm/IR/IntrinsicsRISCV.h"
23#include "llvm/Support/Alignment.h"
24#include "llvm/Support/Debug.h"
25#include "llvm/Support/MathExtras.h"
26#include "llvm/Support/raw_ostream.h"
27
28using namespace llvm;
29
30#define DEBUG_TYPE "riscv-isel"
31#define PASS_NAME "RISC-V DAG->DAG Pattern Instruction Selection"
32
33extern cl::opt<uint32_t> PreferredLandingPadLabel;
34
35static cl::opt<bool> UsePseudoMovImm(
36 "riscv-use-rematerializable-movimm", cl::Hidden,
37 cl::desc("Use a rematerializable pseudoinstruction for 2 instruction "
38 "constant materialization"),
39 cl::init(Val: false));
40
41#define GET_DAGISEL_BODY RISCVDAGToDAGISel
42#include "RISCVGenDAGISel.inc"
43
44void RISCVDAGToDAGISel::PreprocessISelDAG() {
45 SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_end();
46
47 bool MadeChange = false;
48 while (Position != CurDAG->allnodes_begin()) {
49 SDNode *N = &*--Position;
50 if (N->use_empty())
51 continue;
52
53 SDValue Result;
54 switch (N->getOpcode()) {
55 case ISD::SPLAT_VECTOR: {
56 if (Subtarget->hasStdExtP())
57 break;
58 // Convert integer SPLAT_VECTOR to VMV_V_X_VL and floating-point
59 // SPLAT_VECTOR to VFMV_V_F_VL to reduce isel burden.
60 MVT VT = N->getSimpleValueType(ResNo: 0);
61 unsigned Opc =
62 VT.isInteger() ? RISCVISD::VMV_V_X_VL : RISCVISD::VFMV_V_F_VL;
63 SDLoc DL(N);
64 SDValue VL = CurDAG->getRegister(Reg: RISCV::X0, VT: Subtarget->getXLenVT());
65 SDValue Src = N->getOperand(Num: 0);
66 if (VT.isInteger())
67 Src = CurDAG->getNode(Opcode: ISD::ANY_EXTEND, DL, VT: Subtarget->getXLenVT(),
68 Operand: N->getOperand(Num: 0));
69 Result = CurDAG->getNode(Opcode: Opc, DL, VT, N1: CurDAG->getUNDEF(VT), N2: Src, N3: VL);
70 break;
71 }
72 case RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL: {
73 // Lower SPLAT_VECTOR_SPLIT_I64 to two scalar stores and a stride 0 vector
74 // load. Done after lowering and combining so that we have a chance to
75 // optimize this to VMV_V_X_VL when the upper bits aren't needed.
76 assert(N->getNumOperands() == 4 && "Unexpected number of operands");
77 MVT VT = N->getSimpleValueType(ResNo: 0);
78 SDValue Passthru = N->getOperand(Num: 0);
79 SDValue Lo = N->getOperand(Num: 1);
80 SDValue Hi = N->getOperand(Num: 2);
81 SDValue VL = N->getOperand(Num: 3);
82 assert(VT.getVectorElementType() == MVT::i64 && VT.isScalableVector() &&
83 Lo.getValueType() == MVT::i32 && Hi.getValueType() == MVT::i32 &&
84 "Unexpected VTs!");
85 MachineFunction &MF = CurDAG->getMachineFunction();
86 SDLoc DL(N);
87
88 // Create temporary stack for each expanding node.
89 SDValue StackSlot =
90 CurDAG->CreateStackTemporary(Bytes: TypeSize::getFixed(ExactSize: 8), Alignment: Align(8));
91 int FI = cast<FrameIndexSDNode>(Val: StackSlot.getNode())->getIndex();
92 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(MF, FI);
93
94 SDValue Chain = CurDAG->getEntryNode();
95 Lo = CurDAG->getStore(Chain, dl: DL, Val: Lo, Ptr: StackSlot, PtrInfo: MPI, Alignment: Align(8));
96
97 SDValue OffsetSlot =
98 CurDAG->getMemBasePlusOffset(Base: StackSlot, Offset: TypeSize::getFixed(ExactSize: 4), DL);
99 Hi = CurDAG->getStore(Chain, dl: DL, Val: Hi, Ptr: OffsetSlot, PtrInfo: MPI.getWithOffset(O: 4),
100 Alignment: Align(8));
101
102 Chain = CurDAG->getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, N1: Lo, N2: Hi);
103
104 SDVTList VTs = CurDAG->getVTList(VTs: {VT, MVT::Other});
105 SDValue IntID =
106 CurDAG->getTargetConstant(Val: Intrinsic::riscv_vlse, DL, VT: MVT::i64);
107 SDValue Ops[] = {Chain,
108 IntID,
109 Passthru,
110 StackSlot,
111 CurDAG->getRegister(Reg: RISCV::X0, VT: MVT::i64),
112 VL};
113
114 Result = CurDAG->getMemIntrinsicNode(Opcode: ISD::INTRINSIC_W_CHAIN, dl: DL, VTList: VTs, Ops,
115 MemVT: MVT::i64, PtrInfo: MPI, Alignment: Align(8),
116 Flags: MachineMemOperand::MOLoad);
117 break;
118 }
119 case ISD::FP_EXTEND: {
120 // We only have vector patterns for riscv_fpextend_vl in isel.
121 SDLoc DL(N);
122 MVT VT = N->getSimpleValueType(ResNo: 0);
123 if (!VT.isVector())
124 break;
125 SDValue VLMAX = CurDAG->getRegister(Reg: RISCV::X0, VT: Subtarget->getXLenVT());
126 SDValue TrueMask = CurDAG->getNode(
127 Opcode: RISCVISD::VMSET_VL, DL, VT: VT.changeVectorElementType(EltVT: MVT::i1), Operand: VLMAX);
128 Result = CurDAG->getNode(Opcode: RISCVISD::FP_EXTEND_VL, DL, VT, N1: N->getOperand(Num: 0),
129 N2: TrueMask, N3: VLMAX);
130 break;
131 }
132 }
133
134 if (Result) {
135 LLVM_DEBUG(dbgs() << "RISC-V DAG preprocessing replacing:\nOld: ");
136 LLVM_DEBUG(N->dump(CurDAG));
137 LLVM_DEBUG(dbgs() << "\nNew: ");
138 LLVM_DEBUG(Result->dump(CurDAG));
139 LLVM_DEBUG(dbgs() << "\n");
140
141 CurDAG->ReplaceAllUsesOfValueWith(From: SDValue(N, 0), To: Result);
142 MadeChange = true;
143 }
144 }
145
146 if (MadeChange)
147 CurDAG->RemoveDeadNodes();
148}
149
150void RISCVDAGToDAGISel::PostprocessISelDAG() {
151 HandleSDNode Dummy(CurDAG->getRoot());
152 SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_end();
153
154 bool MadeChange = false;
155 while (Position != CurDAG->allnodes_begin()) {
156 SDNode *N = &*--Position;
157 // Skip dead nodes and any non-machine opcodes.
158 if (N->use_empty() || !N->isMachineOpcode())
159 continue;
160
161 MadeChange |= doPeepholeSExtW(Node: N);
162
163 // FIXME: This is here only because the VMerge transform doesn't
164 // know how to handle masked true inputs. Once that has been moved
165 // to post-ISEL, this can be deleted as well.
166 MadeChange |= doPeepholeMaskedRVV(Node: cast<MachineSDNode>(Val: N));
167 }
168
169 CurDAG->setRoot(Dummy.getValue());
170
171 // After we're done with everything else, convert IMPLICIT_DEF
172 // passthru operands to NoRegister. This is required to workaround
173 // an optimization deficiency in MachineCSE. This really should
174 // be merged back into each of the patterns (i.e. there's no good
175 // reason not to go directly to NoReg), but is being done this way
176 // to allow easy backporting.
177 MadeChange |= doPeepholeNoRegPassThru();
178
179 if (MadeChange)
180 CurDAG->RemoveDeadNodes();
181}
182
183static SDValue selectImmSeq(SelectionDAG *CurDAG, const SDLoc &DL, const MVT VT,
184 RISCVMatInt::InstSeq &Seq) {
185 SDValue SrcReg = CurDAG->getRegister(Reg: RISCV::X0, VT);
186 for (const RISCVMatInt::Inst &Inst : Seq) {
187 SDValue SDImm = CurDAG->getSignedTargetConstant(Val: Inst.getImm(), DL, VT);
188 SDNode *Result = nullptr;
189 switch (Inst.getOpndKind()) {
190 case RISCVMatInt::Imm:
191 Result = CurDAG->getMachineNode(Opcode: Inst.getOpcode(), dl: DL, VT, Op1: SDImm);
192 break;
193 case RISCVMatInt::RegX0:
194 Result = CurDAG->getMachineNode(Opcode: Inst.getOpcode(), dl: DL, VT, Op1: SrcReg,
195 Op2: CurDAG->getRegister(Reg: RISCV::X0, VT));
196 break;
197 case RISCVMatInt::RegReg:
198 Result = CurDAG->getMachineNode(Opcode: Inst.getOpcode(), dl: DL, VT, Op1: SrcReg, Op2: SrcReg);
199 break;
200 case RISCVMatInt::RegImm:
201 Result = CurDAG->getMachineNode(Opcode: Inst.getOpcode(), dl: DL, VT, Op1: SrcReg, Op2: SDImm);
202 break;
203 }
204
205 // Only the first instruction has X0 as its source.
206 SrcReg = SDValue(Result, 0);
207 }
208
209 return SrcReg;
210}
211
212static SDValue selectImm(SelectionDAG *CurDAG, const SDLoc &DL, const MVT VT,
213 int64_t Imm, const RISCVSubtarget &Subtarget) {
214 RISCVMatInt::InstSeq Seq = RISCVMatInt::generateInstSeq(Val: Imm, STI: Subtarget);
215
216 // Use a rematerializable pseudo instruction for short sequences if enabled.
217 if (Seq.size() == 2 && UsePseudoMovImm)
218 return SDValue(
219 CurDAG->getMachineNode(Opcode: RISCV::PseudoMovImm, dl: DL, VT,
220 Op1: CurDAG->getSignedTargetConstant(Val: Imm, DL, VT)),
221 0);
222
223 // See if we can create this constant as (ADD (SLLI X, C), X) where X is at
224 // worst an LUI+ADDIW. This will require an extra register, but avoids a
225 // constant pool.
226 // If we have Zba we can use (ADD_UW X, (SLLI X, 32)) to handle cases where
227 // low and high 32 bits are the same and bit 31 and 63 are set.
228 if (Seq.size() > 3) {
229 unsigned ShiftAmt, AddOpc;
230 RISCVMatInt::InstSeq SeqLo =
231 RISCVMatInt::generateTwoRegInstSeq(Val: Imm, STI: Subtarget, ShiftAmt, AddOpc);
232 if (!SeqLo.empty() && (SeqLo.size() + 2) < Seq.size()) {
233 SDValue Lo = selectImmSeq(CurDAG, DL, VT, Seq&: SeqLo);
234
235 SDValue SLLI = SDValue(
236 CurDAG->getMachineNode(Opcode: RISCV::SLLI, dl: DL, VT, Op1: Lo,
237 Op2: CurDAG->getTargetConstant(Val: ShiftAmt, DL, VT)),
238 0);
239 return SDValue(CurDAG->getMachineNode(Opcode: AddOpc, dl: DL, VT, Op1: Lo, Op2: SLLI), 0);
240 }
241 }
242
243 // Otherwise, use the original sequence.
244 return selectImmSeq(CurDAG, DL, VT, Seq);
245}
246
247void RISCVDAGToDAGISel::addVectorLoadStoreOperands(
248 SDNode *Node, unsigned Log2SEW, const SDLoc &DL, unsigned CurOp,
249 bool IsMasked, bool IsStridedOrIndexed, SmallVectorImpl<SDValue> &Operands,
250 bool IsLoad, MVT *IndexVT) {
251 SDValue Chain = Node->getOperand(Num: 0);
252
253 Operands.push_back(Elt: Node->getOperand(Num: CurOp++)); // Base pointer.
254
255 if (IsStridedOrIndexed) {
256 Operands.push_back(Elt: Node->getOperand(Num: CurOp++)); // Index.
257 if (IndexVT)
258 *IndexVT = Operands.back()->getSimpleValueType(ResNo: 0);
259 }
260
261 if (IsMasked) {
262 SDValue Mask = Node->getOperand(Num: CurOp++);
263 Operands.push_back(Elt: Mask);
264 }
265 SDValue VL;
266 selectVLOp(N: Node->getOperand(Num: CurOp++), VL);
267 Operands.push_back(Elt: VL);
268
269 MVT XLenVT = Subtarget->getXLenVT();
270 SDValue SEWOp = CurDAG->getTargetConstant(Val: Log2SEW, DL, VT: XLenVT);
271 Operands.push_back(Elt: SEWOp);
272
273 // At the IR layer, all the masked load intrinsics have policy operands,
274 // none of the others do. All have passthru operands. For our pseudos,
275 // all loads have policy operands.
276 if (IsLoad) {
277 uint64_t Policy = RISCVVType::MASK_AGNOSTIC;
278 if (IsMasked)
279 Policy = Node->getConstantOperandVal(Num: CurOp++);
280 SDValue PolicyOp = CurDAG->getTargetConstant(Val: Policy, DL, VT: XLenVT);
281 Operands.push_back(Elt: PolicyOp);
282 }
283
284 Operands.push_back(Elt: Chain); // Chain.
285}
286
287void RISCVDAGToDAGISel::selectVLSEG(SDNode *Node, unsigned NF, bool IsMasked,
288 bool IsStrided) {
289 SDLoc DL(Node);
290 MVT VT = Node->getSimpleValueType(ResNo: 0);
291 unsigned Log2SEW = Node->getConstantOperandVal(Num: Node->getNumOperands() - 1);
292 RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
293
294 unsigned CurOp = 2;
295 SmallVector<SDValue, 8> Operands;
296
297 Operands.push_back(Elt: Node->getOperand(Num: CurOp++));
298
299 addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked, IsStridedOrIndexed: IsStrided,
300 Operands, /*IsLoad=*/true);
301
302 const RISCV::VLSEGPseudo *P =
303 RISCV::getVLSEGPseudo(NF, Masked: IsMasked, Strided: IsStrided, /*FF*/ false, Log2SEW,
304 LMUL: static_cast<unsigned>(LMUL));
305 MachineSDNode *Load =
306 CurDAG->getMachineNode(Opcode: P->Pseudo, dl: DL, VT1: MVT::Untyped, VT2: MVT::Other, Ops: Operands);
307
308 CurDAG->setNodeMemRefs(N: Load, NewMemRefs: {cast<MemSDNode>(Val: Node)->getMemOperand()});
309
310 ReplaceUses(F: SDValue(Node, 0), T: SDValue(Load, 0));
311 ReplaceUses(F: SDValue(Node, 1), T: SDValue(Load, 1));
312 CurDAG->RemoveDeadNode(N: Node);
313}
314
315void RISCVDAGToDAGISel::selectVLSEGFF(SDNode *Node, unsigned NF,
316 bool IsMasked) {
317 SDLoc DL(Node);
318 MVT VT = Node->getSimpleValueType(ResNo: 0);
319 MVT XLenVT = Subtarget->getXLenVT();
320 unsigned Log2SEW = Node->getConstantOperandVal(Num: Node->getNumOperands() - 1);
321 RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
322
323 unsigned CurOp = 2;
324 SmallVector<SDValue, 7> Operands;
325
326 Operands.push_back(Elt: Node->getOperand(Num: CurOp++));
327
328 addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked,
329 /*IsStridedOrIndexed*/ false, Operands,
330 /*IsLoad=*/true);
331
332 const RISCV::VLSEGPseudo *P =
333 RISCV::getVLSEGPseudo(NF, Masked: IsMasked, /*Strided*/ false, /*FF*/ true,
334 Log2SEW, LMUL: static_cast<unsigned>(LMUL));
335 MachineSDNode *Load = CurDAG->getMachineNode(Opcode: P->Pseudo, dl: DL, VT1: MVT::Untyped,
336 VT2: XLenVT, VT3: MVT::Other, Ops: Operands);
337
338 CurDAG->setNodeMemRefs(N: Load, NewMemRefs: {cast<MemSDNode>(Val: Node)->getMemOperand()});
339
340 ReplaceUses(F: SDValue(Node, 0), T: SDValue(Load, 0)); // Result
341 ReplaceUses(F: SDValue(Node, 1), T: SDValue(Load, 1)); // VL
342 ReplaceUses(F: SDValue(Node, 2), T: SDValue(Load, 2)); // Chain
343 CurDAG->RemoveDeadNode(N: Node);
344}
345
346void RISCVDAGToDAGISel::selectVLXSEG(SDNode *Node, unsigned NF, bool IsMasked,
347 bool IsOrdered) {
348 SDLoc DL(Node);
349 MVT VT = Node->getSimpleValueType(ResNo: 0);
350 unsigned Log2SEW = Node->getConstantOperandVal(Num: Node->getNumOperands() - 1);
351 RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
352
353 unsigned CurOp = 2;
354 SmallVector<SDValue, 8> Operands;
355
356 Operands.push_back(Elt: Node->getOperand(Num: CurOp++));
357
358 MVT IndexVT;
359 addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked,
360 /*IsStridedOrIndexed*/ true, Operands,
361 /*IsLoad=*/true, IndexVT: &IndexVT);
362
363#ifndef NDEBUG
364 // Number of element = RVVBitsPerBlock * LMUL / SEW
365 unsigned ContainedTyNumElts = RISCV::RVVBitsPerBlock >> Log2SEW;
366 auto DecodedLMUL = RISCVVType::decodeVLMUL(LMUL);
367 if (DecodedLMUL.second)
368 ContainedTyNumElts /= DecodedLMUL.first;
369 else
370 ContainedTyNumElts *= DecodedLMUL.first;
371 assert(ContainedTyNumElts == IndexVT.getVectorMinNumElements() &&
372 "Element count mismatch");
373#endif
374
375 RISCVVType::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(VT: IndexVT);
376 unsigned IndexLog2EEW = Log2_32(Value: IndexVT.getScalarSizeInBits());
377 if (IndexLog2EEW == 6 && !Subtarget->is64Bit()) {
378 reportFatalUsageError(reason: "The V extension does not support EEW=64 for index "
379 "values when XLEN=32");
380 }
381 const RISCV::VLXSEGPseudo *P = RISCV::getVLXSEGPseudo(
382 NF, Masked: IsMasked, Ordered: IsOrdered, Log2SEW: IndexLog2EEW, LMUL: static_cast<unsigned>(LMUL),
383 IndexLMUL: static_cast<unsigned>(IndexLMUL));
384 MachineSDNode *Load =
385 CurDAG->getMachineNode(Opcode: P->Pseudo, dl: DL, VT1: MVT::Untyped, VT2: MVT::Other, Ops: Operands);
386
387 CurDAG->setNodeMemRefs(N: Load, NewMemRefs: {cast<MemSDNode>(Val: Node)->getMemOperand()});
388
389 ReplaceUses(F: SDValue(Node, 0), T: SDValue(Load, 0));
390 ReplaceUses(F: SDValue(Node, 1), T: SDValue(Load, 1));
391 CurDAG->RemoveDeadNode(N: Node);
392}
393
394void RISCVDAGToDAGISel::selectVSSEG(SDNode *Node, unsigned NF, bool IsMasked,
395 bool IsStrided) {
396 SDLoc DL(Node);
397 MVT VT = Node->getOperand(Num: 2)->getSimpleValueType(ResNo: 0);
398 unsigned Log2SEW = Node->getConstantOperandVal(Num: Node->getNumOperands() - 1);
399 RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
400
401 unsigned CurOp = 2;
402 SmallVector<SDValue, 8> Operands;
403
404 Operands.push_back(Elt: Node->getOperand(Num: CurOp++));
405
406 addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked, IsStridedOrIndexed: IsStrided,
407 Operands);
408
409 const RISCV::VSSEGPseudo *P = RISCV::getVSSEGPseudo(
410 NF, Masked: IsMasked, Strided: IsStrided, Log2SEW, LMUL: static_cast<unsigned>(LMUL));
411 MachineSDNode *Store =
412 CurDAG->getMachineNode(Opcode: P->Pseudo, dl: DL, VT: Node->getValueType(ResNo: 0), Ops: Operands);
413
414 CurDAG->setNodeMemRefs(N: Store, NewMemRefs: {cast<MemSDNode>(Val: Node)->getMemOperand()});
415
416 ReplaceNode(F: Node, T: Store);
417}
418
419void RISCVDAGToDAGISel::selectVSXSEG(SDNode *Node, unsigned NF, bool IsMasked,
420 bool IsOrdered) {
421 SDLoc DL(Node);
422 MVT VT = Node->getOperand(Num: 2)->getSimpleValueType(ResNo: 0);
423 unsigned Log2SEW = Node->getConstantOperandVal(Num: Node->getNumOperands() - 1);
424 RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
425
426 unsigned CurOp = 2;
427 SmallVector<SDValue, 8> Operands;
428
429 Operands.push_back(Elt: Node->getOperand(Num: CurOp++));
430
431 MVT IndexVT;
432 addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked,
433 /*IsStridedOrIndexed*/ true, Operands,
434 /*IsLoad=*/false, IndexVT: &IndexVT);
435
436#ifndef NDEBUG
437 // Number of element = RVVBitsPerBlock * LMUL / SEW
438 unsigned ContainedTyNumElts = RISCV::RVVBitsPerBlock >> Log2SEW;
439 auto DecodedLMUL = RISCVVType::decodeVLMUL(LMUL);
440 if (DecodedLMUL.second)
441 ContainedTyNumElts /= DecodedLMUL.first;
442 else
443 ContainedTyNumElts *= DecodedLMUL.first;
444 assert(ContainedTyNumElts == IndexVT.getVectorMinNumElements() &&
445 "Element count mismatch");
446#endif
447
448 RISCVVType::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(VT: IndexVT);
449 unsigned IndexLog2EEW = Log2_32(Value: IndexVT.getScalarSizeInBits());
450 if (IndexLog2EEW == 6 && !Subtarget->is64Bit()) {
451 reportFatalUsageError(reason: "The V extension does not support EEW=64 for index "
452 "values when XLEN=32");
453 }
454 const RISCV::VSXSEGPseudo *P = RISCV::getVSXSEGPseudo(
455 NF, Masked: IsMasked, Ordered: IsOrdered, Log2SEW: IndexLog2EEW, LMUL: static_cast<unsigned>(LMUL),
456 IndexLMUL: static_cast<unsigned>(IndexLMUL));
457 MachineSDNode *Store =
458 CurDAG->getMachineNode(Opcode: P->Pseudo, dl: DL, VT: Node->getValueType(ResNo: 0), Ops: Operands);
459
460 CurDAG->setNodeMemRefs(N: Store, NewMemRefs: {cast<MemSDNode>(Val: Node)->getMemOperand()});
461
462 ReplaceNode(F: Node, T: Store);
463}
464
465void RISCVDAGToDAGISel::selectVSETVLI(SDNode *Node) {
466 if (!Subtarget->hasVInstructions())
467 return;
468
469 assert(Node->getOpcode() == ISD::INTRINSIC_WO_CHAIN && "Unexpected opcode");
470
471 SDLoc DL(Node);
472 MVT XLenVT = Subtarget->getXLenVT();
473
474 unsigned IntNo = Node->getConstantOperandVal(Num: 0);
475
476 assert((IntNo == Intrinsic::riscv_vsetvli ||
477 IntNo == Intrinsic::riscv_vsetvlimax) &&
478 "Unexpected vsetvli intrinsic");
479
480 bool VLMax = IntNo == Intrinsic::riscv_vsetvlimax;
481 unsigned Offset = (VLMax ? 1 : 2);
482
483 assert(Node->getNumOperands() == Offset + 2 &&
484 "Unexpected number of operands");
485
486 unsigned SEW =
487 RISCVVType::decodeVSEW(VSEW: Node->getConstantOperandVal(Num: Offset) & 0x7);
488 RISCVVType::VLMUL VLMul = static_cast<RISCVVType::VLMUL>(
489 Node->getConstantOperandVal(Num: Offset + 1) & 0x7);
490
491 unsigned VTypeI = RISCVVType::encodeVTYPE(VLMUL: VLMul, SEW, /*TailAgnostic*/ true,
492 /*MaskAgnostic*/ true);
493 SDValue VTypeIOp = CurDAG->getTargetConstant(Val: VTypeI, DL, VT: XLenVT);
494
495 SDValue VLOperand;
496 unsigned Opcode = RISCV::PseudoVSETVLI;
497 if (auto *C = dyn_cast<ConstantSDNode>(Val: Node->getOperand(Num: 1))) {
498 if (auto VLEN = Subtarget->getRealVLen())
499 if (*VLEN / RISCVVType::getSEWLMULRatio(SEW, VLMul) == C->getZExtValue())
500 VLMax = true;
501 }
502 if (VLMax || isAllOnesConstant(V: Node->getOperand(Num: 1))) {
503 VLOperand = CurDAG->getRegister(Reg: RISCV::X0, VT: XLenVT);
504 Opcode = RISCV::PseudoVSETVLIX0;
505 } else {
506 VLOperand = Node->getOperand(Num: 1);
507
508 if (auto *C = dyn_cast<ConstantSDNode>(Val&: VLOperand)) {
509 uint64_t AVL = C->getZExtValue();
510 if (isUInt<5>(x: AVL)) {
511 SDValue VLImm = CurDAG->getTargetConstant(Val: AVL, DL, VT: XLenVT);
512 ReplaceNode(F: Node, T: CurDAG->getMachineNode(Opcode: RISCV::PseudoVSETIVLI, dl: DL,
513 VT: XLenVT, Op1: VLImm, Op2: VTypeIOp));
514 return;
515 }
516 }
517 }
518
519 ReplaceNode(F: Node,
520 T: CurDAG->getMachineNode(Opcode, dl: DL, VT: XLenVT, Op1: VLOperand, Op2: VTypeIOp));
521}
522
523void RISCVDAGToDAGISel::selectXSfmmVSET(SDNode *Node) {
524 if (!Subtarget->hasVendorXSfmmbase())
525 return;
526
527 assert(Node->getOpcode() == ISD::INTRINSIC_WO_CHAIN && "Unexpected opcode");
528
529 SDLoc DL(Node);
530 MVT XLenVT = Subtarget->getXLenVT();
531
532 unsigned IntNo = Node->getConstantOperandVal(Num: 0);
533
534 assert((IntNo == Intrinsic::riscv_sf_vsettnt ||
535 IntNo == Intrinsic::riscv_sf_vsettm ||
536 IntNo == Intrinsic::riscv_sf_vsettk) &&
537 "Unexpected XSfmm vset intrinsic");
538
539 unsigned SEW = RISCVVType::decodeVSEW(VSEW: Node->getConstantOperandVal(Num: 2));
540 unsigned Widen = RISCVVType::decodeTWiden(TWiden: Node->getConstantOperandVal(Num: 3));
541 unsigned PseudoOpCode =
542 IntNo == Intrinsic::riscv_sf_vsettnt ? RISCV::PseudoSF_VSETTNT
543 : IntNo == Intrinsic::riscv_sf_vsettm ? RISCV::PseudoSF_VSETTM
544 : RISCV::PseudoSF_VSETTK;
545
546 if (IntNo == Intrinsic::riscv_sf_vsettnt) {
547 unsigned VTypeI = RISCVVType::encodeXSfmmVType(SEW, Widen, AltFmt: 0);
548 SDValue VTypeIOp = CurDAG->getTargetConstant(Val: VTypeI, DL, VT: XLenVT);
549
550 ReplaceNode(F: Node, T: CurDAG->getMachineNode(Opcode: PseudoOpCode, dl: DL, VT: XLenVT,
551 Op1: Node->getOperand(Num: 1), Op2: VTypeIOp));
552 } else {
553 SDValue Log2SEW = CurDAG->getTargetConstant(Val: Log2_32(Value: SEW), DL, VT: XLenVT);
554 SDValue TWiden = CurDAG->getTargetConstant(Val: Widen, DL, VT: XLenVT);
555 ReplaceNode(F: Node,
556 T: CurDAG->getMachineNode(Opcode: PseudoOpCode, dl: DL, VT: XLenVT,
557 Op1: Node->getOperand(Num: 1), Op2: Log2SEW, Op3: TWiden));
558 }
559}
560
561bool RISCVDAGToDAGISel::tryShrinkShlLogicImm(SDNode *Node) {
562 MVT VT = Node->getSimpleValueType(ResNo: 0);
563 unsigned Opcode = Node->getOpcode();
564 assert((Opcode == ISD::AND || Opcode == ISD::OR || Opcode == ISD::XOR) &&
565 "Unexpected opcode");
566 SDLoc DL(Node);
567
568 // For operations of the form (x << C1) op C2, check if we can use
569 // ANDI/ORI/XORI by transforming it into (x op (C2>>C1)) << C1.
570 SDValue N0 = Node->getOperand(Num: 0);
571 SDValue N1 = Node->getOperand(Num: 1);
572
573 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Val&: N1);
574 if (!Cst)
575 return false;
576
577 int64_t Val = Cst->getSExtValue();
578
579 // Check if immediate can already use ANDI/ORI/XORI.
580 if (isInt<12>(x: Val))
581 return false;
582
583 SDValue Shift = N0;
584
585 // If Val is simm32 and we have a sext_inreg from i32, then the binop
586 // produces at least 33 sign bits. We can peek through the sext_inreg and use
587 // a SLLIW at the end.
588 bool SignExt = false;
589 if (isInt<32>(x: Val) && N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
590 N0.hasOneUse() && cast<VTSDNode>(Val: N0.getOperand(i: 1))->getVT() == MVT::i32) {
591 SignExt = true;
592 Shift = N0.getOperand(i: 0);
593 }
594
595 if (Shift.getOpcode() != ISD::SHL || !Shift.hasOneUse())
596 return false;
597
598 ConstantSDNode *ShlCst = dyn_cast<ConstantSDNode>(Val: Shift.getOperand(i: 1));
599 if (!ShlCst)
600 return false;
601
602 uint64_t ShAmt = ShlCst->getZExtValue();
603
604 // Make sure that we don't change the operation by removing bits.
605 // This only matters for OR and XOR, AND is unaffected.
606 uint64_t RemovedBitsMask = maskTrailingOnes<uint64_t>(N: ShAmt);
607 if (Opcode != ISD::AND && (Val & RemovedBitsMask) != 0)
608 return false;
609
610 int64_t ShiftedVal = Val >> ShAmt;
611 if (!isInt<12>(x: ShiftedVal))
612 return false;
613
614 // If we peeked through a sext_inreg, make sure the shift is valid for SLLIW.
615 if (SignExt && ShAmt >= 32)
616 return false;
617
618 // Ok, we can reorder to get a smaller immediate.
619 unsigned BinOpc;
620 switch (Opcode) {
621 default: llvm_unreachable("Unexpected opcode");
622 case ISD::AND: BinOpc = RISCV::ANDI; break;
623 case ISD::OR: BinOpc = RISCV::ORI; break;
624 case ISD::XOR: BinOpc = RISCV::XORI; break;
625 }
626
627 unsigned ShOpc = SignExt ? RISCV::SLLIW : RISCV::SLLI;
628
629 SDNode *BinOp = CurDAG->getMachineNode(
630 Opcode: BinOpc, dl: DL, VT, Op1: Shift.getOperand(i: 0),
631 Op2: CurDAG->getSignedTargetConstant(Val: ShiftedVal, DL, VT));
632 SDNode *SLLI =
633 CurDAG->getMachineNode(Opcode: ShOpc, dl: DL, VT, Op1: SDValue(BinOp, 0),
634 Op2: CurDAG->getTargetConstant(Val: ShAmt, DL, VT));
635 ReplaceNode(F: Node, T: SLLI);
636 return true;
637}
638
639bool RISCVDAGToDAGISel::trySignedBitfieldExtract(SDNode *Node) {
640 unsigned Opc;
641
642 if (Subtarget->hasVendorXTHeadBb())
643 Opc = RISCV::TH_EXT;
644 else if (Subtarget->hasVendorXAndesPerf())
645 Opc = RISCV::NDS_BFOS;
646 else if (Subtarget->hasVendorXqcibm())
647 Opc = RISCV::QC_EXT;
648 else
649 // Only supported with XTHeadBb/XAndesPerf/Xqcibm at the moment.
650 return false;
651
652 auto *N1C = dyn_cast<ConstantSDNode>(Val: Node->getOperand(Num: 1));
653 if (!N1C)
654 return false;
655
656 SDValue N0 = Node->getOperand(Num: 0);
657 if (!N0.hasOneUse())
658 return false;
659
660 auto BitfieldExtract = [&](SDValue N0, unsigned Msb, unsigned Lsb,
661 const SDLoc &DL, MVT VT) {
662 if (Opc == RISCV::QC_EXT) {
663 // QC.EXT X, width, shamt
664 // shamt is the same as Lsb
665 // width is the number of bits to extract from the Lsb
666 Msb = Msb - Lsb + 1;
667 }
668 return CurDAG->getMachineNode(Opcode: Opc, dl: DL, VT, Op1: N0.getOperand(i: 0),
669 Op2: CurDAG->getTargetConstant(Val: Msb, DL, VT),
670 Op3: CurDAG->getTargetConstant(Val: Lsb, DL, VT));
671 };
672
673 SDLoc DL(Node);
674 MVT VT = Node->getSimpleValueType(ResNo: 0);
675 const unsigned RightShAmt = N1C->getZExtValue();
676
677 // Transform (sra (shl X, C1) C2) with C1 < C2
678 // -> (SignedBitfieldExtract X, msb, lsb)
679 if (N0.getOpcode() == ISD::SHL) {
680 auto *N01C = dyn_cast<ConstantSDNode>(Val: N0.getOperand(i: 1));
681 if (!N01C)
682 return false;
683
684 const unsigned LeftShAmt = N01C->getZExtValue();
685 // Make sure that this is a bitfield extraction (i.e., the shift-right
686 // amount can not be less than the left-shift).
687 if (LeftShAmt > RightShAmt)
688 return false;
689
690 const unsigned MsbPlusOne = VT.getSizeInBits() - LeftShAmt;
691 const unsigned Msb = MsbPlusOne - 1;
692 const unsigned Lsb = RightShAmt - LeftShAmt;
693
694 SDNode *Sbe = BitfieldExtract(N0, Msb, Lsb, DL, VT);
695 ReplaceNode(F: Node, T: Sbe);
696 return true;
697 }
698
699 // Transform (sra (sext_inreg X, _), C) ->
700 // (SignedBitfieldExtract X, msb, lsb)
701 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
702 unsigned ExtSize =
703 cast<VTSDNode>(Val: N0.getOperand(i: 1))->getVT().getSizeInBits();
704
705 // ExtSize of 32 should use sraiw via tablegen pattern.
706 if (ExtSize == 32)
707 return false;
708
709 const unsigned Msb = ExtSize - 1;
710 // If the shift-right amount is greater than Msb, it means that extracts
711 // the X[Msb] bit and sign-extend it.
712 const unsigned Lsb = RightShAmt > Msb ? Msb : RightShAmt;
713
714 SDNode *Sbe = BitfieldExtract(N0, Msb, Lsb, DL, VT);
715 ReplaceNode(F: Node, T: Sbe);
716 return true;
717 }
718
719 return false;
720}
721
722bool RISCVDAGToDAGISel::trySignedBitfieldInsertInSign(SDNode *Node) {
723 // Only supported with XAndesPerf at the moment.
724 if (!Subtarget->hasVendorXAndesPerf())
725 return false;
726
727 auto *N1C = dyn_cast<ConstantSDNode>(Val: Node->getOperand(Num: 1));
728 if (!N1C)
729 return false;
730
731 SDValue N0 = Node->getOperand(Num: 0);
732 if (!N0.hasOneUse())
733 return false;
734
735 auto BitfieldInsert = [&](SDValue N0, unsigned Msb, unsigned Lsb,
736 const SDLoc &DL, MVT VT) {
737 unsigned Opc = RISCV::NDS_BFOS;
738 // If the Lsb is equal to the Msb, then the Lsb should be 0.
739 if (Lsb == Msb)
740 Lsb = 0;
741 return CurDAG->getMachineNode(Opcode: Opc, dl: DL, VT, Op1: N0.getOperand(i: 0),
742 Op2: CurDAG->getTargetConstant(Val: Lsb, DL, VT),
743 Op3: CurDAG->getTargetConstant(Val: Msb, DL, VT));
744 };
745
746 SDLoc DL(Node);
747 MVT VT = Node->getSimpleValueType(ResNo: 0);
748 const unsigned RightShAmt = N1C->getZExtValue();
749
750 // Transform (sra (shl X, C1) C2) with C1 > C2
751 // -> (NDS.BFOS X, lsb, msb)
752 if (N0.getOpcode() == ISD::SHL) {
753 auto *N01C = dyn_cast<ConstantSDNode>(Val: N0.getOperand(i: 1));
754 if (!N01C)
755 return false;
756
757 const unsigned LeftShAmt = N01C->getZExtValue();
758 // Make sure that this is a bitfield insertion (i.e., the shift-right
759 // amount should be less than the left-shift).
760 if (LeftShAmt <= RightShAmt)
761 return false;
762
763 const unsigned MsbPlusOne = VT.getSizeInBits() - RightShAmt;
764 const unsigned Msb = MsbPlusOne - 1;
765 const unsigned Lsb = LeftShAmt - RightShAmt;
766
767 SDNode *Sbi = BitfieldInsert(N0, Msb, Lsb, DL, VT);
768 ReplaceNode(F: Node, T: Sbi);
769 return true;
770 }
771
772 return false;
773}
774
775bool RISCVDAGToDAGISel::tryUnsignedBitfieldExtract(SDNode *Node,
776 const SDLoc &DL, MVT VT,
777 SDValue X, unsigned Msb,
778 unsigned Lsb) {
779 unsigned Opc;
780
781 if (Subtarget->hasVendorXTHeadBb()) {
782 Opc = RISCV::TH_EXTU;
783 } else if (Subtarget->hasVendorXAndesPerf()) {
784 Opc = RISCV::NDS_BFOZ;
785 } else if (Subtarget->hasVendorXqcibm()) {
786 Opc = RISCV::QC_EXTU;
787 // QC.EXTU X, width, shamt
788 // shamt is the same as Lsb
789 // width is the number of bits to extract from the Lsb
790 Msb = Msb - Lsb + 1;
791 } else {
792 // Only supported with XTHeadBb/XAndesPerf/Xqcibm at the moment.
793 return false;
794 }
795
796 SDNode *Ube = CurDAG->getMachineNode(Opcode: Opc, dl: DL, VT, Op1: X,
797 Op2: CurDAG->getTargetConstant(Val: Msb, DL, VT),
798 Op3: CurDAG->getTargetConstant(Val: Lsb, DL, VT));
799 ReplaceNode(F: Node, T: Ube);
800 return true;
801}
802
803bool RISCVDAGToDAGISel::tryUnsignedBitfieldInsertInZero(SDNode *Node,
804 const SDLoc &DL, MVT VT,
805 SDValue X, unsigned Msb,
806 unsigned Lsb) {
807 // Only supported with XAndesPerf at the moment.
808 if (!Subtarget->hasVendorXAndesPerf())
809 return false;
810
811 unsigned Opc = RISCV::NDS_BFOZ;
812
813 // If the Lsb is equal to the Msb, then the Lsb should be 0.
814 if (Lsb == Msb)
815 Lsb = 0;
816 SDNode *Ubi = CurDAG->getMachineNode(Opcode: Opc, dl: DL, VT, Op1: X,
817 Op2: CurDAG->getTargetConstant(Val: Lsb, DL, VT),
818 Op3: CurDAG->getTargetConstant(Val: Msb, DL, VT));
819 ReplaceNode(F: Node, T: Ubi);
820 return true;
821}
822
823bool RISCVDAGToDAGISel::tryIndexedLoad(SDNode *Node) {
824 // Target does not support indexed loads.
825 if (!Subtarget->hasVendorXTHeadMemIdx())
826 return false;
827
828 LoadSDNode *Ld = cast<LoadSDNode>(Val: Node);
829 ISD::MemIndexedMode AM = Ld->getAddressingMode();
830 if (AM == ISD::UNINDEXED)
831 return false;
832
833 const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val: Ld->getOffset());
834 if (!C)
835 return false;
836
837 EVT LoadVT = Ld->getMemoryVT();
838 assert((AM == ISD::PRE_INC || AM == ISD::POST_INC) &&
839 "Unexpected addressing mode");
840 bool IsPre = AM == ISD::PRE_INC;
841 bool IsPost = AM == ISD::POST_INC;
842 int64_t Offset = C->getSExtValue();
843
844 // The constants that can be encoded in the THeadMemIdx instructions
845 // are of the form (sign_extend(imm5) << imm2).
846 unsigned Shift;
847 for (Shift = 0; Shift < 4; Shift++)
848 if (isInt<5>(x: Offset >> Shift) && ((Offset % (1LL << Shift)) == 0))
849 break;
850
851 // Constant cannot be encoded.
852 if (Shift == 4)
853 return false;
854
855 bool IsZExt = (Ld->getExtensionType() == ISD::ZEXTLOAD);
856 unsigned Opcode;
857 if (LoadVT == MVT::i8 && IsPre)
858 Opcode = IsZExt ? RISCV::TH_LBUIB : RISCV::TH_LBIB;
859 else if (LoadVT == MVT::i8 && IsPost)
860 Opcode = IsZExt ? RISCV::TH_LBUIA : RISCV::TH_LBIA;
861 else if (LoadVT == MVT::i16 && IsPre)
862 Opcode = IsZExt ? RISCV::TH_LHUIB : RISCV::TH_LHIB;
863 else if (LoadVT == MVT::i16 && IsPost)
864 Opcode = IsZExt ? RISCV::TH_LHUIA : RISCV::TH_LHIA;
865 else if (LoadVT == MVT::i32 && IsPre)
866 Opcode = IsZExt ? RISCV::TH_LWUIB : RISCV::TH_LWIB;
867 else if (LoadVT == MVT::i32 && IsPost)
868 Opcode = IsZExt ? RISCV::TH_LWUIA : RISCV::TH_LWIA;
869 else if (LoadVT == MVT::i64 && IsPre)
870 Opcode = RISCV::TH_LDIB;
871 else if (LoadVT == MVT::i64 && IsPost)
872 Opcode = RISCV::TH_LDIA;
873 else
874 return false;
875
876 EVT Ty = Ld->getOffset().getValueType();
877 SDValue Ops[] = {
878 Ld->getBasePtr(),
879 CurDAG->getSignedTargetConstant(Val: Offset >> Shift, DL: SDLoc(Node), VT: Ty),
880 CurDAG->getTargetConstant(Val: Shift, DL: SDLoc(Node), VT: Ty), Ld->getChain()};
881 SDNode *New = CurDAG->getMachineNode(Opcode, dl: SDLoc(Node), VT1: Ld->getValueType(ResNo: 0),
882 VT2: Ld->getValueType(ResNo: 1), VT3: MVT::Other, Ops);
883
884 MachineMemOperand *MemOp = cast<MemSDNode>(Val: Node)->getMemOperand();
885 CurDAG->setNodeMemRefs(N: cast<MachineSDNode>(Val: New), NewMemRefs: {MemOp});
886
887 ReplaceNode(F: Node, T: New);
888
889 return true;
890}
891
892static SDValue buildGPRPair(SelectionDAG *CurDAG, const SDLoc &DL, MVT VT,
893 SDValue Lo, SDValue Hi) {
894 SDValue Ops[] = {
895 CurDAG->getTargetConstant(Val: RISCV::GPRPairRegClassID, DL, VT: MVT::i32), Lo,
896 CurDAG->getTargetConstant(Val: RISCV::sub_gpr_even, DL, VT: MVT::i32), Hi,
897 CurDAG->getTargetConstant(Val: RISCV::sub_gpr_odd, DL, VT: MVT::i32)};
898
899 return SDValue(
900 CurDAG->getMachineNode(Opcode: TargetOpcode::REG_SEQUENCE, dl: DL, VT, Ops), 0);
901}
902
903// Helper to extract Lo and Hi values from a GPR pair.
904static std::pair<SDValue, SDValue>
905extractGPRPair(SelectionDAG *CurDAG, const SDLoc &DL, SDValue Pair) {
906 SDValue Lo =
907 CurDAG->getTargetExtractSubreg(SRIdx: RISCV::sub_gpr_even, DL, VT: MVT::i32, Operand: Pair);
908 SDValue Hi =
909 CurDAG->getTargetExtractSubreg(SRIdx: RISCV::sub_gpr_odd, DL, VT: MVT::i32, Operand: Pair);
910 return {Lo, Hi};
911}
912
913// Try to match WMACC pattern: ADDD where one operand pair comes from a
914// widening multiply (both results of UMUL_LOHI, SMUL_LOHI, or WMULSU).
915bool RISCVDAGToDAGISel::tryWideningMulAcc(SDNode *Node, const SDLoc &DL) {
916 assert(Node->getOpcode() == RISCVISD::ADDD && "Expected ADDD");
917
918 SDValue Op0Lo = Node->getOperand(Num: 0);
919 SDValue Op0Hi = Node->getOperand(Num: 1);
920 SDValue Op1Lo = Node->getOperand(Num: 2);
921 SDValue Op1Hi = Node->getOperand(Num: 3);
922
923 auto IsSupportedMulWithOneUse = [](SDValue Lo, SDValue Hi) {
924 unsigned Opc = Lo.getOpcode();
925 if (Opc != ISD::UMUL_LOHI && Opc != ISD::SMUL_LOHI &&
926 Opc != RISCVISD::WMULSU)
927 return false;
928 return Lo.getNode() == Hi.getNode() && Lo.getResNo() == 0 &&
929 Hi.getResNo() == 1 && Lo.hasOneUse() && Hi.hasOneUse();
930 };
931
932 SDNode *MulNode = nullptr;
933 SDValue AddLo, AddHi;
934
935 // Check if first operand pair is a supported multiply with single use.
936 if (IsSupportedMulWithOneUse(Op0Lo, Op0Hi)) {
937 MulNode = Op0Lo.getNode();
938 AddLo = Op1Lo;
939 AddHi = Op1Hi;
940 }
941 // ADDD is commutative. Check if second operand pair is a supported multiply
942 // with single use.
943 else if (IsSupportedMulWithOneUse(Op1Lo, Op1Hi)) {
944 MulNode = Op1Lo.getNode();
945 AddLo = Op0Lo;
946 AddHi = Op0Hi;
947 } else {
948 return false;
949 }
950
951 unsigned Opc;
952 switch (MulNode->getOpcode()) {
953 default:
954 llvm_unreachable("Unexpected multiply opcode");
955 case ISD::UMUL_LOHI:
956 Opc = RISCV::WMACCU;
957 break;
958 case ISD::SMUL_LOHI:
959 Opc = RISCV::WMACC;
960 break;
961 case RISCVISD::WMULSU:
962 Opc = RISCV::WMACCSU;
963 break;
964 }
965
966 SDValue Acc = buildGPRPair(CurDAG, DL, VT: MVT::Untyped, Lo: AddLo, Hi: AddHi);
967
968 // WMACC instruction format: rd, rs1, rs2 (rd is accumulator).
969 SDValue M0 = MulNode->getOperand(Num: 0);
970 SDValue M1 = MulNode->getOperand(Num: 1);
971 MachineSDNode *New =
972 CurDAG->getMachineNode(Opcode: Opc, dl: DL, VT: MVT::Untyped, Op1: Acc, Op2: M0, Op3: M1);
973
974 auto [Lo, Hi] = extractGPRPair(CurDAG, DL, Pair: SDValue(New, 0));
975 ReplaceUses(F: SDValue(Node, 0), T: Lo);
976 ReplaceUses(F: SDValue(Node, 1), T: Hi);
977 CurDAG->RemoveDeadNode(N: Node);
978 return true;
979}
980
981static Register getTileReg(uint64_t TileNum) {
982 assert(TileNum <= 15 && "Invalid tile number");
983 return RISCV::T0 + TileNum;
984}
985
986void RISCVDAGToDAGISel::selectSF_VC_X_SE(SDNode *Node) {
987 if (!Subtarget->hasVInstructions())
988 return;
989
990 assert(Node->getOpcode() == ISD::INTRINSIC_VOID && "Unexpected opcode");
991
992 SDLoc DL(Node);
993 unsigned IntNo = Node->getConstantOperandVal(Num: 1);
994
995 assert((IntNo == Intrinsic::riscv_sf_vc_x_se ||
996 IntNo == Intrinsic::riscv_sf_vc_i_se) &&
997 "Unexpected vsetvli intrinsic");
998
999 // imm, imm, imm, simm5/scalar, sew, log2lmul, vl
1000 unsigned Log2SEW = Log2_32(Value: Node->getConstantOperandVal(Num: 6));
1001 SDValue SEWOp =
1002 CurDAG->getTargetConstant(Val: Log2SEW, DL, VT: Subtarget->getXLenVT());
1003 SmallVector<SDValue, 8> Operands = {Node->getOperand(Num: 2), Node->getOperand(Num: 3),
1004 Node->getOperand(Num: 4), Node->getOperand(Num: 5),
1005 Node->getOperand(Num: 8), SEWOp,
1006 Node->getOperand(Num: 0)};
1007
1008 unsigned Opcode;
1009 auto *LMulSDNode = cast<ConstantSDNode>(Val: Node->getOperand(Num: 7));
1010 switch (LMulSDNode->getSExtValue()) {
1011 case 5:
1012 Opcode = IntNo == Intrinsic::riscv_sf_vc_x_se ? RISCV::PseudoSF_VC_X_SE_MF8
1013 : RISCV::PseudoSF_VC_I_SE_MF8;
1014 break;
1015 case 6:
1016 Opcode = IntNo == Intrinsic::riscv_sf_vc_x_se ? RISCV::PseudoSF_VC_X_SE_MF4
1017 : RISCV::PseudoSF_VC_I_SE_MF4;
1018 break;
1019 case 7:
1020 Opcode = IntNo == Intrinsic::riscv_sf_vc_x_se ? RISCV::PseudoSF_VC_X_SE_MF2
1021 : RISCV::PseudoSF_VC_I_SE_MF2;
1022 break;
1023 case 0:
1024 Opcode = IntNo == Intrinsic::riscv_sf_vc_x_se ? RISCV::PseudoSF_VC_X_SE_M1
1025 : RISCV::PseudoSF_VC_I_SE_M1;
1026 break;
1027 case 1:
1028 Opcode = IntNo == Intrinsic::riscv_sf_vc_x_se ? RISCV::PseudoSF_VC_X_SE_M2
1029 : RISCV::PseudoSF_VC_I_SE_M2;
1030 break;
1031 case 2:
1032 Opcode = IntNo == Intrinsic::riscv_sf_vc_x_se ? RISCV::PseudoSF_VC_X_SE_M4
1033 : RISCV::PseudoSF_VC_I_SE_M4;
1034 break;
1035 case 3:
1036 Opcode = IntNo == Intrinsic::riscv_sf_vc_x_se ? RISCV::PseudoSF_VC_X_SE_M8
1037 : RISCV::PseudoSF_VC_I_SE_M8;
1038 break;
1039 }
1040
1041 ReplaceNode(F: Node, T: CurDAG->getMachineNode(
1042 Opcode, dl: DL, VT: Node->getSimpleValueType(ResNo: 0), Ops: Operands));
1043}
1044
1045static unsigned getSegInstNF(unsigned Intrinsic) {
1046#define INST_NF_CASE(NAME, NF) \
1047 case Intrinsic::riscv_##NAME##NF: \
1048 return NF;
1049#define INST_NF_CASE_MASK(NAME, NF) \
1050 case Intrinsic::riscv_##NAME##NF##_mask: \
1051 return NF;
1052#define INST_NF_CASE_FF(NAME, NF) \
1053 case Intrinsic::riscv_##NAME##NF##ff: \
1054 return NF;
1055#define INST_NF_CASE_FF_MASK(NAME, NF) \
1056 case Intrinsic::riscv_##NAME##NF##ff_mask: \
1057 return NF;
1058#define INST_ALL_NF_CASE_BASE(MACRO_NAME, NAME) \
1059 MACRO_NAME(NAME, 2) \
1060 MACRO_NAME(NAME, 3) \
1061 MACRO_NAME(NAME, 4) \
1062 MACRO_NAME(NAME, 5) \
1063 MACRO_NAME(NAME, 6) \
1064 MACRO_NAME(NAME, 7) \
1065 MACRO_NAME(NAME, 8)
1066#define INST_ALL_NF_CASE(NAME) \
1067 INST_ALL_NF_CASE_BASE(INST_NF_CASE, NAME) \
1068 INST_ALL_NF_CASE_BASE(INST_NF_CASE_MASK, NAME)
1069#define INST_ALL_NF_CASE_WITH_FF(NAME) \
1070 INST_ALL_NF_CASE(NAME) \
1071 INST_ALL_NF_CASE_BASE(INST_NF_CASE_FF, NAME) \
1072 INST_ALL_NF_CASE_BASE(INST_NF_CASE_FF_MASK, NAME)
1073 switch (Intrinsic) {
1074 default:
1075 llvm_unreachable("Unexpected segment load/store intrinsic");
1076 INST_ALL_NF_CASE_WITH_FF(vlseg)
1077 INST_ALL_NF_CASE(vlsseg)
1078 INST_ALL_NF_CASE(vloxseg)
1079 INST_ALL_NF_CASE(vluxseg)
1080 INST_ALL_NF_CASE(vsseg)
1081 INST_ALL_NF_CASE(vssseg)
1082 INST_ALL_NF_CASE(vsoxseg)
1083 INST_ALL_NF_CASE(vsuxseg)
1084 }
1085}
1086
1087static bool isApplicableToPLIOrPLUI(int Val) {
1088 // Check if the immediate is packed i8 or i10
1089 int16_t Bit31To16 = Val >> 16;
1090 int16_t Bit15To0 = Val;
1091 int8_t Bit15To8 = Bit15To0 >> 8;
1092 int8_t Bit7To0 = Val;
1093 if (Bit31To16 != Bit15To0)
1094 return false;
1095
1096 return isInt<10>(x: Bit15To0) || isShiftedInt<10, 6>(x: Bit15To0) ||
1097 Bit15To8 == Bit7To0;
1098}
1099
1100void RISCVDAGToDAGISel::Select(SDNode *Node) {
1101 // If we have a custom node, we have already selected.
1102 if (Node->isMachineOpcode()) {
1103 LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");
1104 Node->setNodeId(-1);
1105 return;
1106 }
1107
1108 // Instruction Selection not handled by the auto-generated tablegen selection
1109 // should be handled here.
1110 unsigned Opcode = Node->getOpcode();
1111 MVT XLenVT = Subtarget->getXLenVT();
1112 SDLoc DL(Node);
1113 MVT VT = Node->getSimpleValueType(ResNo: 0);
1114
1115 bool HasBitTest = Subtarget->hasBEXTILike();
1116
1117 switch (Opcode) {
1118 case ISD::Constant: {
1119 assert(VT == Subtarget->getXLenVT() && "Unexpected VT");
1120 auto *ConstNode = cast<ConstantSDNode>(Val: Node);
1121 if (ConstNode->isZero()) {
1122 SDValue New =
1123 CurDAG->getCopyFromReg(Chain: CurDAG->getEntryNode(), dl: DL, Reg: RISCV::X0, VT);
1124 ReplaceNode(F: Node, T: New.getNode());
1125 return;
1126 }
1127 int64_t Imm = ConstNode->getSExtValue();
1128 // If only the lower 8 bits are used, try to convert this to a simm6 by
1129 // sign-extending bit 7. This is neutral without the C extension, and
1130 // allows C.LI to be used if C is present.
1131 if (!isInt<8>(x: Imm) && isUInt<8>(x: Imm) && isInt<6>(x: SignExtend64<8>(x: Imm)) &&
1132 hasAllBUsers(Node))
1133 Imm = SignExtend64<8>(x: Imm);
1134 // If the upper XLen-16 bits are not used, try to convert this to a simm12
1135 // by sign extending bit 15.
1136 else if (!isInt<16>(x: Imm) && isUInt<16>(x: Imm) &&
1137 isInt<12>(x: SignExtend64<16>(x: Imm)) && hasAllHUsers(Node))
1138 Imm = SignExtend64<16>(x: Imm);
1139
1140 // If the upper XLen-16 bits are not used, the lower 2 bytes are the same,
1141 // and we can't use li, convert to an xlen splat so we can use pli.b.
1142 if (Subtarget->hasStdExtP() && !isInt<12>(x: Imm) &&
1143 (Imm & 0xff) == ((Imm >> 8) & 0xff) && hasAllHUsers(Node)) {
1144 // Splat the lower 16 bits to XLen. Sign extend for RV32.
1145 uint64_t Splat = Imm & 0xffff;
1146 Splat = (Splat << 16) | Splat;
1147 if (VT == MVT::i64)
1148 Imm = Splat << 32 | Splat;
1149 else
1150 Imm = SignExtend64<32>(x: Splat);
1151 } else {
1152 // If the upper 32-bits are not used try to convert this into a simm32 by
1153 // sign extending bit 32.
1154 if (!isInt<32>(x: Imm) && isUInt<32>(x: Imm) && hasAllWUsers(Node))
1155 Imm = SignExtend64<32>(x: Imm);
1156
1157 if (VT == MVT::i64 && !isInt<12>(x: Imm) && !isShiftedInt<20, 12>(x: Imm) &&
1158 Subtarget->hasStdExtP() && isApplicableToPLIOrPLUI(Val: Imm) &&
1159 hasAllWUsers(Node)) {
1160 // If it's 4 packed 8-bit integers or 2 packed signed 16-bit integers,
1161 // we can simply copy lower 32 bits to higher 32 bits to make it able to
1162 // rematerialize to PLI_B or PLI_H
1163 Imm = ((uint64_t)Imm << 32) | (Imm & 0xFFFFFFFF);
1164 }
1165 }
1166
1167 ReplaceNode(F: Node, T: selectImm(CurDAG, DL, VT, Imm, Subtarget: *Subtarget).getNode());
1168 return;
1169 }
1170 case ISD::ConstantFP: {
1171 const APFloat &APF = cast<ConstantFPSDNode>(Val: Node)->getValueAPF();
1172
1173 bool Is64Bit = Subtarget->is64Bit();
1174 bool HasZdinx = Subtarget->hasStdExtZdinx();
1175
1176 bool NegZeroF64 = APF.isNegZero() && VT == MVT::f64;
1177 SDValue Imm;
1178 // For +0.0 or f64 -0.0 we need to start from X0. For all others, we will
1179 // create an integer immediate.
1180 if (APF.isPosZero() || NegZeroF64) {
1181 if (VT == MVT::f64 && HasZdinx && !Is64Bit)
1182 Imm = CurDAG->getRegister(Reg: RISCV::X0_Pair, VT: MVT::f64);
1183 else
1184 Imm = CurDAG->getRegister(Reg: RISCV::X0, VT: XLenVT);
1185 } else {
1186 Imm = selectImm(CurDAG, DL, VT: XLenVT, Imm: APF.bitcastToAPInt().getSExtValue(),
1187 Subtarget: *Subtarget);
1188 }
1189
1190 unsigned Opc;
1191 switch (VT.SimpleTy) {
1192 default:
1193 llvm_unreachable("Unexpected size");
1194 case MVT::bf16:
1195 assert(Subtarget->hasStdExtZfbfmin());
1196 Opc = RISCV::FMV_H_X;
1197 break;
1198 case MVT::f16:
1199 Opc = Subtarget->hasStdExtZhinxmin() ? RISCV::COPY : RISCV::FMV_H_X;
1200 break;
1201 case MVT::f32:
1202 Opc = Subtarget->hasStdExtZfinx() ? RISCV::COPY : RISCV::FMV_W_X;
1203 break;
1204 case MVT::f64:
1205 // For RV32, we can't move from a GPR, we need to convert instead. This
1206 // should only happen for +0.0 and -0.0.
1207 assert((Subtarget->is64Bit() || APF.isZero()) && "Unexpected constant");
1208 if (HasZdinx)
1209 Opc = RISCV::COPY;
1210 else
1211 Opc = Is64Bit ? RISCV::FMV_D_X : RISCV::FCVT_D_W;
1212 break;
1213 }
1214
1215 SDNode *Res;
1216 if (VT.SimpleTy == MVT::f16 && Opc == RISCV::COPY) {
1217 Res =
1218 CurDAG->getTargetExtractSubreg(SRIdx: RISCV::sub_16, DL, VT, Operand: Imm).getNode();
1219 } else if (VT.SimpleTy == MVT::f32 && Opc == RISCV::COPY) {
1220 Res =
1221 CurDAG->getTargetExtractSubreg(SRIdx: RISCV::sub_32, DL, VT, Operand: Imm).getNode();
1222 } else if (Opc == RISCV::FCVT_D_W_IN32X || Opc == RISCV::FCVT_D_W)
1223 Res = CurDAG->getMachineNode(
1224 Opcode: Opc, dl: DL, VT, Op1: Imm,
1225 Op2: CurDAG->getTargetConstant(Val: RISCVFPRndMode::RNE, DL, VT: XLenVT));
1226 else
1227 Res = CurDAG->getMachineNode(Opcode: Opc, dl: DL, VT, Op1: Imm);
1228
1229 // For f64 -0.0, we need to insert a fneg.d idiom.
1230 if (NegZeroF64) {
1231 Opc = RISCV::FSGNJN_D;
1232 if (HasZdinx)
1233 Opc = Is64Bit ? RISCV::FSGNJN_D_INX : RISCV::FSGNJN_D_IN32X;
1234 Res =
1235 CurDAG->getMachineNode(Opcode: Opc, dl: DL, VT, Op1: SDValue(Res, 0), Op2: SDValue(Res, 0));
1236 }
1237
1238 ReplaceNode(F: Node, T: Res);
1239 return;
1240 }
1241 case RISCVISD::BuildGPRPair:
1242 case RISCVISD::BuildPairF64:
1243 case RISCVISD::BuildPairGPRVec: {
1244 if (Opcode == RISCVISD::BuildPairF64 && !Subtarget->hasStdExtZdinx())
1245 break;
1246
1247 assert((!Subtarget->is64Bit() || Opcode != RISCVISD::BuildPairF64) &&
1248 "BuildPairF64 only handled here on rv32i_zdinx");
1249
1250 SDValue N =
1251 buildGPRPair(CurDAG, DL, VT, Lo: Node->getOperand(Num: 0), Hi: Node->getOperand(Num: 1));
1252 ReplaceNode(F: Node, T: N.getNode());
1253 return;
1254 }
1255 case RISCVISD::SplitGPRPair:
1256 case RISCVISD::SplitF64:
1257 case RISCVISD::SplitGPRVec: {
1258 if (Subtarget->hasStdExtZdinx() || Opcode != RISCVISD::SplitF64) {
1259 assert((!Subtarget->is64Bit() || Opcode != RISCVISD::SplitF64) &&
1260 "SplitF64 only handled here on rv32i_zdinx");
1261
1262 if (!SDValue(Node, 0).use_empty()) {
1263 SDValue Lo = CurDAG->getTargetExtractSubreg(SRIdx: RISCV::sub_gpr_even, DL,
1264 VT: Node->getValueType(ResNo: 0),
1265 Operand: Node->getOperand(Num: 0));
1266 ReplaceUses(F: SDValue(Node, 0), T: Lo);
1267 }
1268
1269 if (!SDValue(Node, 1).use_empty()) {
1270 SDValue Hi = CurDAG->getTargetExtractSubreg(
1271 SRIdx: RISCV::sub_gpr_odd, DL, VT: Node->getValueType(ResNo: 1), Operand: Node->getOperand(Num: 0));
1272 ReplaceUses(F: SDValue(Node, 1), T: Hi);
1273 }
1274
1275 CurDAG->RemoveDeadNode(N: Node);
1276 return;
1277 }
1278
1279 if (!Subtarget->hasStdExtZfa())
1280 break;
1281 assert(Subtarget->hasStdExtD() && !Subtarget->is64Bit() &&
1282 "Unexpected subtarget");
1283
1284 // With Zfa, lower to fmv.x.w and fmvh.x.d.
1285 if (!SDValue(Node, 0).use_empty()) {
1286 SDNode *Lo = CurDAG->getMachineNode(Opcode: RISCV::FMV_X_W_FPR64, dl: DL, VT,
1287 Op1: Node->getOperand(Num: 0));
1288 ReplaceUses(F: SDValue(Node, 0), T: SDValue(Lo, 0));
1289 }
1290 if (!SDValue(Node, 1).use_empty()) {
1291 SDNode *Hi = CurDAG->getMachineNode(Opcode: RISCV::FMVH_X_D, dl: DL, VT,
1292 Op1: Node->getOperand(Num: 0));
1293 ReplaceUses(F: SDValue(Node, 1), T: SDValue(Hi, 0));
1294 }
1295
1296 CurDAG->RemoveDeadNode(N: Node);
1297 return;
1298 }
1299 case ISD::SHL: {
1300 auto *N1C = dyn_cast<ConstantSDNode>(Val: Node->getOperand(Num: 1));
1301 if (!N1C)
1302 break;
1303 SDValue N0 = Node->getOperand(Num: 0);
1304 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse() ||
1305 !isa<ConstantSDNode>(Val: N0.getOperand(i: 1)))
1306 break;
1307 unsigned ShAmt = N1C->getZExtValue();
1308 uint64_t Mask = N0.getConstantOperandVal(i: 1);
1309
1310 if (isShiftedMask_64(Value: Mask)) {
1311 unsigned XLen = Subtarget->getXLen();
1312 unsigned LeadingZeros = XLen - llvm::bit_width(Value: Mask);
1313 unsigned TrailingZeros = llvm::countr_zero(Val: Mask);
1314 if (ShAmt <= 32 && TrailingZeros > 0 && LeadingZeros == 32) {
1315 // Optimize (shl (and X, C2), C) -> (slli (srliw X, C3), C3+C)
1316 // where C2 has 32 leading zeros and C3 trailing zeros.
1317 SDNode *SRLIW = CurDAG->getMachineNode(
1318 Opcode: RISCV::SRLIW, dl: DL, VT, Op1: N0.getOperand(i: 0),
1319 Op2: CurDAG->getTargetConstant(Val: TrailingZeros, DL, VT));
1320 SDNode *SLLI = CurDAG->getMachineNode(
1321 Opcode: RISCV::SLLI, dl: DL, VT, Op1: SDValue(SRLIW, 0),
1322 Op2: CurDAG->getTargetConstant(Val: TrailingZeros + ShAmt, DL, VT));
1323 ReplaceNode(F: Node, T: SLLI);
1324 return;
1325 }
1326 if (TrailingZeros == 0 && LeadingZeros > ShAmt &&
1327 XLen - LeadingZeros > 11 && LeadingZeros != 32) {
1328 // Optimize (shl (and X, C2), C) -> (srli (slli X, C4), C4-C)
1329 // where C2 has C4 leading zeros and no trailing zeros.
1330 // This is profitable if the "and" was to be lowered to
1331 // (srli (slli X, C4), C4) and not (andi X, C2).
1332 // For "LeadingZeros == 32":
1333 // - with Zba it's just (slli.uw X, C)
1334 // - without Zba a tablegen pattern applies the very same
1335 // transform as we would have done here
1336 SDNode *SLLI = CurDAG->getMachineNode(
1337 Opcode: RISCV::SLLI, dl: DL, VT, Op1: N0.getOperand(i: 0),
1338 Op2: CurDAG->getTargetConstant(Val: LeadingZeros, DL, VT));
1339 SDNode *SRLI = CurDAG->getMachineNode(
1340 Opcode: RISCV::SRLI, dl: DL, VT, Op1: SDValue(SLLI, 0),
1341 Op2: CurDAG->getTargetConstant(Val: LeadingZeros - ShAmt, DL, VT));
1342 ReplaceNode(F: Node, T: SRLI);
1343 return;
1344 }
1345 }
1346 break;
1347 }
1348 case ISD::SRL: {
1349 auto *N1C = dyn_cast<ConstantSDNode>(Val: Node->getOperand(Num: 1));
1350 if (!N1C)
1351 break;
1352 SDValue N0 = Node->getOperand(Num: 0);
1353 if (N0.getOpcode() != ISD::AND || !isa<ConstantSDNode>(Val: N0.getOperand(i: 1)))
1354 break;
1355 unsigned ShAmt = N1C->getZExtValue();
1356 uint64_t Mask = N0.getConstantOperandVal(i: 1);
1357
1358 // Optimize (srl (and X, C2), C) -> (slli (srliw X, C3), C3-C) where C2 has
1359 // 32 leading zeros and C3 trailing zeros.
1360 if (isShiftedMask_64(Value: Mask) && N0.hasOneUse()) {
1361 unsigned XLen = Subtarget->getXLen();
1362 unsigned LeadingZeros = XLen - llvm::bit_width(Value: Mask);
1363 unsigned TrailingZeros = llvm::countr_zero(Val: Mask);
1364 if (LeadingZeros == 32 && TrailingZeros > ShAmt) {
1365 SDNode *SRLIW = CurDAG->getMachineNode(
1366 Opcode: RISCV::SRLIW, dl: DL, VT, Op1: N0.getOperand(i: 0),
1367 Op2: CurDAG->getTargetConstant(Val: TrailingZeros, DL, VT));
1368 SDNode *SLLI = CurDAG->getMachineNode(
1369 Opcode: RISCV::SLLI, dl: DL, VT, Op1: SDValue(SRLIW, 0),
1370 Op2: CurDAG->getTargetConstant(Val: TrailingZeros - ShAmt, DL, VT));
1371 ReplaceNode(F: Node, T: SLLI);
1372 return;
1373 }
1374 }
1375
1376 // Optimize (srl (and X, C2), C) ->
1377 // (srli (slli X, (XLen-C3), (XLen-C3) + C)
1378 // Where C2 is a mask with C3 trailing ones.
1379 // Taking into account that the C2 may have had lower bits unset by
1380 // SimplifyDemandedBits. This avoids materializing the C2 immediate.
1381 // This pattern occurs when type legalizing right shifts for types with
1382 // less than XLen bits.
1383 Mask |= maskTrailingOnes<uint64_t>(N: ShAmt);
1384 if (!isMask_64(Value: Mask))
1385 break;
1386 unsigned TrailingOnes = llvm::countr_one(Value: Mask);
1387 if (ShAmt >= TrailingOnes)
1388 break;
1389 // If the mask has 32 trailing ones, use SRLI on RV32 or SRLIW on RV64.
1390 if (TrailingOnes == 32) {
1391 SDNode *SRLI = CurDAG->getMachineNode(
1392 Opcode: Subtarget->is64Bit() ? RISCV::SRLIW : RISCV::SRLI, dl: DL, VT,
1393 Op1: N0.getOperand(i: 0), Op2: CurDAG->getTargetConstant(Val: ShAmt, DL, VT));
1394 ReplaceNode(F: Node, T: SRLI);
1395 return;
1396 }
1397
1398 // Only do the remaining transforms if the AND has one use.
1399 if (!N0.hasOneUse())
1400 break;
1401
1402 // If C2 is (1 << ShAmt) use bexti or th.tst if possible.
1403 if (HasBitTest && ShAmt + 1 == TrailingOnes) {
1404 SDNode *BEXTI = CurDAG->getMachineNode(
1405 Opcode: Subtarget->hasStdExtZbs() ? RISCV::BEXTI : RISCV::TH_TST, dl: DL, VT,
1406 Op1: N0.getOperand(i: 0), Op2: CurDAG->getTargetConstant(Val: ShAmt, DL, VT));
1407 ReplaceNode(F: Node, T: BEXTI);
1408 return;
1409 }
1410
1411 const unsigned Msb = TrailingOnes - 1;
1412 const unsigned Lsb = ShAmt;
1413 if (tryUnsignedBitfieldExtract(Node, DL, VT, X: N0.getOperand(i: 0), Msb, Lsb))
1414 return;
1415
1416 unsigned LShAmt = Subtarget->getXLen() - TrailingOnes;
1417 SDNode *SLLI =
1418 CurDAG->getMachineNode(Opcode: RISCV::SLLI, dl: DL, VT, Op1: N0.getOperand(i: 0),
1419 Op2: CurDAG->getTargetConstant(Val: LShAmt, DL, VT));
1420 SDNode *SRLI = CurDAG->getMachineNode(
1421 Opcode: RISCV::SRLI, dl: DL, VT, Op1: SDValue(SLLI, 0),
1422 Op2: CurDAG->getTargetConstant(Val: LShAmt + ShAmt, DL, VT));
1423 ReplaceNode(F: Node, T: SRLI);
1424 return;
1425 }
1426 case ISD::SRA: {
1427 if (trySignedBitfieldExtract(Node))
1428 return;
1429
1430 if (trySignedBitfieldInsertInSign(Node))
1431 return;
1432
1433 // Optimize (sra (sext_inreg X, i16), C) ->
1434 // (srai (slli X, (XLen-16), (XLen-16) + C)
1435 // And (sra (sext_inreg X, i8), C) ->
1436 // (srai (slli X, (XLen-8), (XLen-8) + C)
1437 // This can occur when Zbb is enabled, which makes sext_inreg i16/i8 legal.
1438 // This transform matches the code we get without Zbb. The shifts are more
1439 // compressible, and this can help expose CSE opportunities in the sdiv by
1440 // constant optimization.
1441 auto *N1C = dyn_cast<ConstantSDNode>(Val: Node->getOperand(Num: 1));
1442 if (!N1C)
1443 break;
1444 SDValue N0 = Node->getOperand(Num: 0);
1445 if (N0.getOpcode() != ISD::SIGN_EXTEND_INREG || !N0.hasOneUse())
1446 break;
1447 unsigned ShAmt = N1C->getZExtValue();
1448 unsigned ExtSize =
1449 cast<VTSDNode>(Val: N0.getOperand(i: 1))->getVT().getSizeInBits();
1450 // ExtSize of 32 should use sraiw via tablegen pattern.
1451 if (ExtSize >= 32 || ShAmt >= ExtSize)
1452 break;
1453 unsigned LShAmt = Subtarget->getXLen() - ExtSize;
1454 SDNode *SLLI =
1455 CurDAG->getMachineNode(Opcode: RISCV::SLLI, dl: DL, VT, Op1: N0.getOperand(i: 0),
1456 Op2: CurDAG->getTargetConstant(Val: LShAmt, DL, VT));
1457 SDNode *SRAI = CurDAG->getMachineNode(
1458 Opcode: RISCV::SRAI, dl: DL, VT, Op1: SDValue(SLLI, 0),
1459 Op2: CurDAG->getTargetConstant(Val: LShAmt + ShAmt, DL, VT));
1460 ReplaceNode(F: Node, T: SRAI);
1461 return;
1462 }
1463 case ISD::SIGN_EXTEND_INREG: {
1464 // Optimize (sext_inreg (srl X, C), i8/i16) ->
1465 // (srai (slli X, XLen-ExtSize-C), XLen-ExtSize)
1466 // This is a bitfield extract pattern where we're extracting a signed
1467 // 8-bit or 16-bit field from position C.
1468 SDValue N0 = Node->getOperand(Num: 0);
1469 if (N0.getOpcode() != ISD::SRL || !N0.hasOneUse())
1470 break;
1471
1472 auto *ShAmtC = dyn_cast<ConstantSDNode>(Val: N0.getOperand(i: 1));
1473 if (!ShAmtC)
1474 break;
1475
1476 unsigned ExtSize =
1477 cast<VTSDNode>(Val: Node->getOperand(Num: 1))->getVT().getSizeInBits();
1478 unsigned ShAmt = ShAmtC->getZExtValue();
1479 unsigned XLen = Subtarget->getXLen();
1480
1481 // Only handle types less than 32, and make sure the shift amount is valid.
1482 if (ExtSize >= 32 || ShAmt >= XLen - ExtSize)
1483 break;
1484
1485 unsigned LShAmt = XLen - ExtSize - ShAmt;
1486 SDNode *SLLI =
1487 CurDAG->getMachineNode(Opcode: RISCV::SLLI, dl: DL, VT, Op1: N0.getOperand(i: 0),
1488 Op2: CurDAG->getTargetConstant(Val: LShAmt, DL, VT));
1489 SDNode *SRAI = CurDAG->getMachineNode(
1490 Opcode: RISCV::SRAI, dl: DL, VT, Op1: SDValue(SLLI, 0),
1491 Op2: CurDAG->getTargetConstant(Val: XLen - ExtSize, DL, VT));
1492 ReplaceNode(F: Node, T: SRAI);
1493 return;
1494 }
1495 case ISD::OR: {
1496 if (tryShrinkShlLogicImm(Node))
1497 return;
1498
1499 break;
1500 }
1501 case ISD::XOR:
1502 if (tryShrinkShlLogicImm(Node))
1503 return;
1504
1505 break;
1506 case ISD::AND: {
1507 auto *N1C = dyn_cast<ConstantSDNode>(Val: Node->getOperand(Num: 1));
1508 if (!N1C)
1509 break;
1510
1511 SDValue N0 = Node->getOperand(Num: 0);
1512
1513 bool LeftShift = N0.getOpcode() == ISD::SHL;
1514 if (LeftShift || N0.getOpcode() == ISD::SRL) {
1515 auto *C = dyn_cast<ConstantSDNode>(Val: N0.getOperand(i: 1));
1516 if (!C)
1517 break;
1518 unsigned C2 = C->getZExtValue();
1519 unsigned XLen = Subtarget->getXLen();
1520 assert((C2 > 0 && C2 < XLen) && "Unexpected shift amount!");
1521
1522 // Keep track of whether this is a c.andi. If we can't use c.andi, the
1523 // shift pair might offer more compression opportunities.
1524 // TODO: We could check for C extension here, but we don't have many lit
1525 // tests with the C extension enabled so not checking gets better
1526 // coverage.
1527 // TODO: What if ANDI faster than shift?
1528 bool IsCANDI = isInt<6>(x: N1C->getSExtValue());
1529
1530 uint64_t C1 = N1C->getZExtValue();
1531
1532 // Clear irrelevant bits in the mask.
1533 if (LeftShift)
1534 C1 &= maskTrailingZeros<uint64_t>(N: C2);
1535 else
1536 C1 &= maskTrailingOnes<uint64_t>(N: XLen - C2);
1537
1538 // Some transforms should only be done if the shift has a single use or
1539 // the AND would become (srli (slli X, 32), 32)
1540 bool OneUseOrZExtW = N0.hasOneUse() || C1 == UINT64_C(0xFFFFFFFF);
1541
1542 SDValue X = N0.getOperand(i: 0);
1543
1544 // Turn (and (srl x, c2) c1) -> (srli (slli x, c3-c2), c3) if c1 is a mask
1545 // with c3 leading zeros.
1546 if (!LeftShift && isMask_64(Value: C1)) {
1547 unsigned Leading = XLen - llvm::bit_width(Value: C1);
1548 if (C2 < Leading) {
1549 // If the number of leading zeros is C2+32 this can be SRLIW.
1550 if (C2 + 32 == Leading) {
1551 SDNode *SRLIW = CurDAG->getMachineNode(
1552 Opcode: RISCV::SRLIW, dl: DL, VT, Op1: X, Op2: CurDAG->getTargetConstant(Val: C2, DL, VT));
1553 ReplaceNode(F: Node, T: SRLIW);
1554 return;
1555 }
1556
1557 // (and (srl (sexti32 Y), c2), c1) -> (srliw (sraiw Y, 31), c3 - 32)
1558 // if c1 is a mask with c3 leading zeros and c2 >= 32 and c3-c2==1.
1559 //
1560 // This pattern occurs when (i32 (srl (sra 31), c3 - 32)) is type
1561 // legalized and goes through DAG combine.
1562 if (C2 >= 32 && (Leading - C2) == 1 && N0.hasOneUse() &&
1563 X.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1564 cast<VTSDNode>(Val: X.getOperand(i: 1))->getVT() == MVT::i32) {
1565 SDNode *SRAIW =
1566 CurDAG->getMachineNode(Opcode: RISCV::SRAIW, dl: DL, VT, Op1: X.getOperand(i: 0),
1567 Op2: CurDAG->getTargetConstant(Val: 31, DL, VT));
1568 SDNode *SRLIW = CurDAG->getMachineNode(
1569 Opcode: RISCV::SRLIW, dl: DL, VT, Op1: SDValue(SRAIW, 0),
1570 Op2: CurDAG->getTargetConstant(Val: Leading - 32, DL, VT));
1571 ReplaceNode(F: Node, T: SRLIW);
1572 return;
1573 }
1574
1575 // Try to use an unsigned bitfield extract (e.g., th.extu) if
1576 // available.
1577 // Transform (and (srl x, C2), C1)
1578 // -> (<bfextract> x, msb, lsb)
1579 //
1580 // Make sure to keep this below the SRLIW cases, as we always want to
1581 // prefer the more common instruction.
1582 const unsigned Msb = llvm::bit_width(Value: C1) + C2 - 1;
1583 const unsigned Lsb = C2;
1584 if (tryUnsignedBitfieldExtract(Node, DL, VT, X, Msb, Lsb))
1585 return;
1586
1587 // (srli (slli x, c3-c2), c3).
1588 // Skip if we could use (zext.w (sraiw X, C2)).
1589 bool Skip = Subtarget->hasStdExtZba() && Leading == 32 &&
1590 X.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1591 cast<VTSDNode>(Val: X.getOperand(i: 1))->getVT() == MVT::i32;
1592 // Also Skip if we can use bexti or th.tst.
1593 Skip |= HasBitTest && Leading == XLen - 1;
1594 if (OneUseOrZExtW && !Skip) {
1595 SDNode *SLLI = CurDAG->getMachineNode(
1596 Opcode: RISCV::SLLI, dl: DL, VT, Op1: X,
1597 Op2: CurDAG->getTargetConstant(Val: Leading - C2, DL, VT));
1598 SDNode *SRLI = CurDAG->getMachineNode(
1599 Opcode: RISCV::SRLI, dl: DL, VT, Op1: SDValue(SLLI, 0),
1600 Op2: CurDAG->getTargetConstant(Val: Leading, DL, VT));
1601 ReplaceNode(F: Node, T: SRLI);
1602 return;
1603 }
1604 }
1605 }
1606
1607 // Turn (and (shl x, c2), c1) -> (srli (slli c2+c3), c3) if c1 is a mask
1608 // shifted by c2 bits with c3 leading zeros.
1609 if (LeftShift && isShiftedMask_64(Value: C1)) {
1610 unsigned Leading = XLen - llvm::bit_width(Value: C1);
1611
1612 if (C2 + Leading < XLen &&
1613 C1 == (maskTrailingOnes<uint64_t>(N: XLen - (C2 + Leading)) << C2)) {
1614 // Use slli.uw when possible.
1615 if ((XLen - (C2 + Leading)) == 32 && Subtarget->hasStdExtZba()) {
1616 SDNode *SLLI_UW =
1617 CurDAG->getMachineNode(Opcode: RISCV::SLLI_UW, dl: DL, VT, Op1: X,
1618 Op2: CurDAG->getTargetConstant(Val: C2, DL, VT));
1619 ReplaceNode(F: Node, T: SLLI_UW);
1620 return;
1621 }
1622
1623 // Try to use an unsigned bitfield insert (e.g., nds.bfoz) if
1624 // available.
1625 // Transform (and (shl x, c2), c1)
1626 // -> (<bfinsert> x, msb, lsb)
1627 // e.g.
1628 // (and (shl x, 12), 0x00fff000)
1629 // If XLen = 32 and C2 = 12, then
1630 // Msb = 32 - 8 - 1 = 23 and Lsb = 12
1631 const unsigned Msb = XLen - Leading - 1;
1632 const unsigned Lsb = C2;
1633 if (tryUnsignedBitfieldInsertInZero(Node, DL, VT, X, Msb, Lsb))
1634 return;
1635
1636 if (OneUseOrZExtW && !IsCANDI) {
1637 // (packh x0, X)
1638 if (Subtarget->hasStdExtZbkb() && C1 == 0xff00 && C2 == 8) {
1639 SDNode *PACKH = CurDAG->getMachineNode(
1640 Opcode: RISCV::PACKH, dl: DL, VT,
1641 Op1: CurDAG->getRegister(Reg: RISCV::X0, VT: Subtarget->getXLenVT()), Op2: X);
1642 ReplaceNode(F: Node, T: PACKH);
1643 return;
1644 }
1645 // (srli (slli c2+c3), c3)
1646 SDNode *SLLI = CurDAG->getMachineNode(
1647 Opcode: RISCV::SLLI, dl: DL, VT, Op1: X,
1648 Op2: CurDAG->getTargetConstant(Val: C2 + Leading, DL, VT));
1649 SDNode *SRLI = CurDAG->getMachineNode(
1650 Opcode: RISCV::SRLI, dl: DL, VT, Op1: SDValue(SLLI, 0),
1651 Op2: CurDAG->getTargetConstant(Val: Leading, DL, VT));
1652 ReplaceNode(F: Node, T: SRLI);
1653 return;
1654 }
1655 }
1656 }
1657
1658 // Turn (and (shr x, c2), c1) -> (slli (srli x, c2+c3), c3) if c1 is a
1659 // shifted mask with c2 leading zeros and c3 trailing zeros.
1660 if (!LeftShift && isShiftedMask_64(Value: C1)) {
1661 unsigned Leading = XLen - llvm::bit_width(Value: C1);
1662 unsigned Trailing = llvm::countr_zero(Val: C1);
1663 if (Leading == C2 && C2 + Trailing < XLen && OneUseOrZExtW &&
1664 !IsCANDI) {
1665 unsigned SrliOpc = RISCV::SRLI;
1666 // If the input is zexti32 we should use SRLIW.
1667 if (X.getOpcode() == ISD::AND &&
1668 isa<ConstantSDNode>(Val: X.getOperand(i: 1)) &&
1669 X.getConstantOperandVal(i: 1) == UINT64_C(0xFFFFFFFF)) {
1670 SrliOpc = RISCV::SRLIW;
1671 X = X.getOperand(i: 0);
1672 }
1673 SDNode *SRLI = CurDAG->getMachineNode(
1674 Opcode: SrliOpc, dl: DL, VT, Op1: X,
1675 Op2: CurDAG->getTargetConstant(Val: C2 + Trailing, DL, VT));
1676 SDNode *SLLI = CurDAG->getMachineNode(
1677 Opcode: RISCV::SLLI, dl: DL, VT, Op1: SDValue(SRLI, 0),
1678 Op2: CurDAG->getTargetConstant(Val: Trailing, DL, VT));
1679 ReplaceNode(F: Node, T: SLLI);
1680 return;
1681 }
1682 // If the leading zero count is C2+32, we can use SRLIW instead of SRLI.
1683 if (Leading > 32 && (Leading - 32) == C2 && C2 + Trailing < 32 &&
1684 OneUseOrZExtW && !IsCANDI) {
1685 SDNode *SRLIW = CurDAG->getMachineNode(
1686 Opcode: RISCV::SRLIW, dl: DL, VT, Op1: X,
1687 Op2: CurDAG->getTargetConstant(Val: C2 + Trailing, DL, VT));
1688 SDNode *SLLI = CurDAG->getMachineNode(
1689 Opcode: RISCV::SLLI, dl: DL, VT, Op1: SDValue(SRLIW, 0),
1690 Op2: CurDAG->getTargetConstant(Val: Trailing, DL, VT));
1691 ReplaceNode(F: Node, T: SLLI);
1692 return;
1693 }
1694 // If we have 32 bits in the mask, we can use SLLI_UW instead of SLLI.
1695 if (Trailing > 0 && Leading + Trailing == 32 && C2 + Trailing < XLen &&
1696 OneUseOrZExtW && Subtarget->hasStdExtZba()) {
1697 SDNode *SRLI = CurDAG->getMachineNode(
1698 Opcode: RISCV::SRLI, dl: DL, VT, Op1: X,
1699 Op2: CurDAG->getTargetConstant(Val: C2 + Trailing, DL, VT));
1700 SDNode *SLLI_UW = CurDAG->getMachineNode(
1701 Opcode: RISCV::SLLI_UW, dl: DL, VT, Op1: SDValue(SRLI, 0),
1702 Op2: CurDAG->getTargetConstant(Val: Trailing, DL, VT));
1703 ReplaceNode(F: Node, T: SLLI_UW);
1704 return;
1705 }
1706 }
1707
1708 // Turn (and (shl x, c2), c1) -> (slli (srli x, c3-c2), c3) if c1 is a
1709 // shifted mask with no leading zeros and c3 trailing zeros.
1710 if (LeftShift && isShiftedMask_64(Value: C1)) {
1711 unsigned Leading = XLen - llvm::bit_width(Value: C1);
1712 unsigned Trailing = llvm::countr_zero(Val: C1);
1713 if (Leading == 0 && C2 < Trailing && OneUseOrZExtW && !IsCANDI) {
1714 SDNode *SRLI = CurDAG->getMachineNode(
1715 Opcode: RISCV::SRLI, dl: DL, VT, Op1: X,
1716 Op2: CurDAG->getTargetConstant(Val: Trailing - C2, DL, VT));
1717 SDNode *SLLI = CurDAG->getMachineNode(
1718 Opcode: RISCV::SLLI, dl: DL, VT, Op1: SDValue(SRLI, 0),
1719 Op2: CurDAG->getTargetConstant(Val: Trailing, DL, VT));
1720 ReplaceNode(F: Node, T: SLLI);
1721 return;
1722 }
1723 // If we have (32-C2) leading zeros, we can use SRLIW instead of SRLI.
1724 if (C2 < Trailing && Leading + C2 == 32 && OneUseOrZExtW && !IsCANDI) {
1725 SDNode *SRLIW = CurDAG->getMachineNode(
1726 Opcode: RISCV::SRLIW, dl: DL, VT, Op1: X,
1727 Op2: CurDAG->getTargetConstant(Val: Trailing - C2, DL, VT));
1728 SDNode *SLLI = CurDAG->getMachineNode(
1729 Opcode: RISCV::SLLI, dl: DL, VT, Op1: SDValue(SRLIW, 0),
1730 Op2: CurDAG->getTargetConstant(Val: Trailing, DL, VT));
1731 ReplaceNode(F: Node, T: SLLI);
1732 return;
1733 }
1734
1735 // If we have 32 bits in the mask, we can use SLLI_UW instead of SLLI.
1736 if (C2 < Trailing && Leading + Trailing == 32 && OneUseOrZExtW &&
1737 Subtarget->hasStdExtZba()) {
1738 SDNode *SRLI = CurDAG->getMachineNode(
1739 Opcode: RISCV::SRLI, dl: DL, VT, Op1: X,
1740 Op2: CurDAG->getTargetConstant(Val: Trailing - C2, DL, VT));
1741 SDNode *SLLI_UW = CurDAG->getMachineNode(
1742 Opcode: RISCV::SLLI_UW, dl: DL, VT, Op1: SDValue(SRLI, 0),
1743 Op2: CurDAG->getTargetConstant(Val: Trailing, DL, VT));
1744 ReplaceNode(F: Node, T: SLLI_UW);
1745 return;
1746 }
1747 }
1748 }
1749
1750 const uint64_t C1 = N1C->getZExtValue();
1751
1752 if (N0.getOpcode() == ISD::SRA && isa<ConstantSDNode>(Val: N0.getOperand(i: 1)) &&
1753 N0.hasOneUse()) {
1754 unsigned C2 = N0.getConstantOperandVal(i: 1);
1755 unsigned XLen = Subtarget->getXLen();
1756 assert((C2 > 0 && C2 < XLen) && "Unexpected shift amount!");
1757
1758 SDValue X = N0.getOperand(i: 0);
1759
1760 // Prefer SRAIW + ANDI when possible.
1761 bool Skip = C2 > 32 && isInt<12>(x: N1C->getSExtValue()) &&
1762 X.getOpcode() == ISD::SHL &&
1763 isa<ConstantSDNode>(Val: X.getOperand(i: 1)) &&
1764 X.getConstantOperandVal(i: 1) == 32;
1765 // Turn (and (sra x, c2), c1) -> (srli (srai x, c2-c3), c3) if c1 is a
1766 // mask with c3 leading zeros and c2 is larger than c3.
1767 if (isMask_64(Value: C1) && !Skip) {
1768 unsigned Leading = XLen - llvm::bit_width(Value: C1);
1769 if (C2 > Leading) {
1770 SDNode *SRAI = CurDAG->getMachineNode(
1771 Opcode: RISCV::SRAI, dl: DL, VT, Op1: X,
1772 Op2: CurDAG->getTargetConstant(Val: C2 - Leading, DL, VT));
1773 SDNode *SRLI = CurDAG->getMachineNode(
1774 Opcode: RISCV::SRLI, dl: DL, VT, Op1: SDValue(SRAI, 0),
1775 Op2: CurDAG->getTargetConstant(Val: Leading, DL, VT));
1776 ReplaceNode(F: Node, T: SRLI);
1777 return;
1778 }
1779 }
1780
1781 // Look for (and (sra y, c2), c1) where c1 is a shifted mask with c3
1782 // leading zeros and c4 trailing zeros. If c2 is greater than c3, we can
1783 // use (slli (srli (srai y, c2 - c3), c3 + c4), c4).
1784 if (isShiftedMask_64(Value: C1) && !Skip) {
1785 unsigned Leading = XLen - llvm::bit_width(Value: C1);
1786 unsigned Trailing = llvm::countr_zero(Val: C1);
1787 if (C2 > Leading && Leading > 0 && Trailing > 0) {
1788 SDNode *SRAI = CurDAG->getMachineNode(
1789 Opcode: RISCV::SRAI, dl: DL, VT, Op1: N0.getOperand(i: 0),
1790 Op2: CurDAG->getTargetConstant(Val: C2 - Leading, DL, VT));
1791 SDNode *SRLI = CurDAG->getMachineNode(
1792 Opcode: RISCV::SRLI, dl: DL, VT, Op1: SDValue(SRAI, 0),
1793 Op2: CurDAG->getTargetConstant(Val: Leading + Trailing, DL, VT));
1794 SDNode *SLLI = CurDAG->getMachineNode(
1795 Opcode: RISCV::SLLI, dl: DL, VT, Op1: SDValue(SRLI, 0),
1796 Op2: CurDAG->getTargetConstant(Val: Trailing, DL, VT));
1797 ReplaceNode(F: Node, T: SLLI);
1798 return;
1799 }
1800 }
1801 }
1802
1803 // If C1 masks off the upper bits only (but can't be formed as an
1804 // ANDI), use an unsigned bitfield extract (e.g., th.extu), if
1805 // available.
1806 // Transform (and x, C1)
1807 // -> (<bfextract> x, msb, lsb)
1808 if (isMask_64(Value: C1) && !isInt<12>(x: N1C->getSExtValue()) &&
1809 !(C1 == 0xffff && Subtarget->hasStdExtZbb()) &&
1810 !(C1 == 0xffffffff && Subtarget->hasStdExtZba())) {
1811 const unsigned Msb = llvm::bit_width(Value: C1) - 1;
1812 if (tryUnsignedBitfieldExtract(Node, DL, VT, X: N0, Msb, Lsb: 0))
1813 return;
1814 }
1815
1816 if (tryShrinkShlLogicImm(Node))
1817 return;
1818
1819 break;
1820 }
1821 case ISD::MUL: {
1822 // Special case for calculating (mul (and X, C2), C1) where the full product
1823 // fits in XLen bits. We can shift X left by the number of leading zeros in
1824 // C2 and shift C1 left by XLen-lzcnt(C2). This will ensure the final
1825 // product has XLen trailing zeros, putting it in the output of MULHU. This
1826 // can avoid materializing a constant in a register for C2.
1827
1828 // RHS should be a constant.
1829 auto *N1C = dyn_cast<ConstantSDNode>(Val: Node->getOperand(Num: 1));
1830 if (!N1C || !N1C->hasOneUse())
1831 break;
1832
1833 // LHS should be an AND with constant.
1834 SDValue N0 = Node->getOperand(Num: 0);
1835 if (N0.getOpcode() != ISD::AND || !isa<ConstantSDNode>(Val: N0.getOperand(i: 1)))
1836 break;
1837
1838 uint64_t C2 = N0.getConstantOperandVal(i: 1);
1839
1840 // Constant should be a mask.
1841 if (!isMask_64(Value: C2))
1842 break;
1843
1844 // If this can be an ANDI or ZEXT.H, don't do this if the ANDI/ZEXT has
1845 // multiple users or the constant is a simm12. This prevents inserting a
1846 // shift and still have uses of the AND/ZEXT. Shifting a simm12 will likely
1847 // make it more costly to materialize. Otherwise, using a SLLI might allow
1848 // it to be compressed.
1849 bool IsANDIOrZExt =
1850 isInt<12>(x: C2) ||
1851 (C2 == UINT64_C(0xFFFF) && Subtarget->hasStdExtZbb());
1852 // With XTHeadBb, we can use TH.EXTU.
1853 IsANDIOrZExt |= C2 == UINT64_C(0xFFFF) && Subtarget->hasVendorXTHeadBb();
1854 if (IsANDIOrZExt && (isInt<12>(x: N1C->getSExtValue()) || !N0.hasOneUse()))
1855 break;
1856 // If this can be a ZEXT.w, don't do this if the ZEXT has multiple users or
1857 // the constant is a simm32.
1858 bool IsZExtW = C2 == UINT64_C(0xFFFFFFFF) && Subtarget->hasStdExtZba();
1859 // With XTHeadBb, we can use TH.EXTU.
1860 IsZExtW |= C2 == UINT64_C(0xFFFFFFFF) && Subtarget->hasVendorXTHeadBb();
1861 if (IsZExtW && (isInt<32>(x: N1C->getSExtValue()) || !N0.hasOneUse()))
1862 break;
1863
1864 // We need to shift left the AND input and C1 by a total of XLen bits.
1865
1866 // How far left do we need to shift the AND input?
1867 unsigned XLen = Subtarget->getXLen();
1868 unsigned LeadingZeros = XLen - llvm::bit_width(Value: C2);
1869
1870 // The constant gets shifted by the remaining amount unless that would
1871 // shift bits out.
1872 uint64_t C1 = N1C->getZExtValue();
1873 unsigned ConstantShift = XLen - LeadingZeros;
1874 if (ConstantShift > (XLen - llvm::bit_width(Value: C1)))
1875 break;
1876
1877 uint64_t ShiftedC1 = C1 << ConstantShift;
1878 // If this RV32, we need to sign extend the constant.
1879 if (XLen == 32)
1880 ShiftedC1 = SignExtend64<32>(x: ShiftedC1);
1881
1882 // Create (mulhu (slli X, lzcnt(C2)), C1 << (XLen - lzcnt(C2))).
1883 SDNode *Imm = selectImm(CurDAG, DL, VT, Imm: ShiftedC1, Subtarget: *Subtarget).getNode();
1884 SDNode *SLLI =
1885 CurDAG->getMachineNode(Opcode: RISCV::SLLI, dl: DL, VT, Op1: N0.getOperand(i: 0),
1886 Op2: CurDAG->getTargetConstant(Val: LeadingZeros, DL, VT));
1887 SDNode *MULHU = CurDAG->getMachineNode(Opcode: RISCV::MULHU, dl: DL, VT,
1888 Op1: SDValue(SLLI, 0), Op2: SDValue(Imm, 0));
1889 ReplaceNode(F: Node, T: MULHU);
1890 return;
1891 }
1892 case ISD::SMUL_LOHI:
1893 case ISD::UMUL_LOHI:
1894 case RISCVISD::WMULSU:
1895 case RISCVISD::WADDU:
1896 case RISCVISD::WSUBU: {
1897 assert(Subtarget->hasStdExtP() && !Subtarget->is64Bit() && VT == MVT::i32 &&
1898 "Unexpected opcode");
1899
1900 unsigned Opc;
1901 switch (Node->getOpcode()) {
1902 default:
1903 llvm_unreachable("Unexpected opcode");
1904 case ISD::SMUL_LOHI:
1905 Opc = RISCV::WMUL;
1906 break;
1907 case ISD::UMUL_LOHI:
1908 Opc = RISCV::WMULU;
1909 break;
1910 case RISCVISD::WMULSU:
1911 Opc = RISCV::WMULSU;
1912 break;
1913 case RISCVISD::WADDU:
1914 Opc = RISCV::WADDU;
1915 break;
1916 case RISCVISD::WSUBU:
1917 Opc = RISCV::WSUBU;
1918 break;
1919 }
1920
1921 SDNode *Result = CurDAG->getMachineNode(
1922 Opcode: Opc, dl: DL, VT: MVT::Untyped, Op1: Node->getOperand(Num: 0), Op2: Node->getOperand(Num: 1));
1923
1924 auto [Lo, Hi] = extractGPRPair(CurDAG, DL, Pair: SDValue(Result, 0));
1925 ReplaceUses(F: SDValue(Node, 0), T: Lo);
1926 ReplaceUses(F: SDValue(Node, 1), T: Hi);
1927 CurDAG->RemoveDeadNode(N: Node);
1928 return;
1929 }
1930 case RISCVISD::WSLL:
1931 case RISCVISD::WSLA: {
1932 // Custom select WSLL/WSLA for RV32P.
1933 assert(Subtarget->hasStdExtP() && !Subtarget->is64Bit() && VT == MVT::i32 &&
1934 "Unexpected opcode");
1935
1936 bool IsSigned = Node->getOpcode() == RISCVISD::WSLA;
1937
1938 SDValue ShAmt = Node->getOperand(Num: 1);
1939
1940 unsigned Opc;
1941
1942 auto *ShAmtC = dyn_cast<ConstantSDNode>(Val&: ShAmt);
1943 if (ShAmtC && ShAmtC->getZExtValue() < 64) {
1944 Opc = IsSigned ? RISCV::WSLAI : RISCV::WSLLI;
1945 ShAmt = CurDAG->getTargetConstant(Val: ShAmtC->getZExtValue(), DL, VT: XLenVT);
1946 } else {
1947 Opc = IsSigned ? RISCV::WSLA : RISCV::WSLL;
1948 }
1949
1950 SDNode *WShift = CurDAG->getMachineNode(Opcode: Opc, dl: DL, VT: MVT::Untyped,
1951 Op1: Node->getOperand(Num: 0), Op2: ShAmt);
1952
1953 auto [Lo, Hi] = extractGPRPair(CurDAG, DL, Pair: SDValue(WShift, 0));
1954 ReplaceUses(F: SDValue(Node, 0), T: Lo);
1955 ReplaceUses(F: SDValue(Node, 1), T: Hi);
1956 CurDAG->RemoveDeadNode(N: Node);
1957 return;
1958 }
1959 case ISD::LOAD: {
1960 if (tryIndexedLoad(Node))
1961 return;
1962
1963 if (Subtarget->hasVendorXCVmem() && !Subtarget->is64Bit()) {
1964 // We match post-incrementing load here
1965 LoadSDNode *Load = cast<LoadSDNode>(Val: Node);
1966 if (Load->getAddressingMode() != ISD::POST_INC)
1967 break;
1968
1969 SDValue Chain = Node->getOperand(Num: 0);
1970 SDValue Base = Node->getOperand(Num: 1);
1971 SDValue Offset = Node->getOperand(Num: 2);
1972
1973 bool Simm12 = false;
1974 bool SignExtend = Load->getExtensionType() == ISD::SEXTLOAD;
1975
1976 if (auto ConstantOffset = dyn_cast<ConstantSDNode>(Val&: Offset)) {
1977 int ConstantVal = ConstantOffset->getSExtValue();
1978 Simm12 = isInt<12>(x: ConstantVal);
1979 if (Simm12)
1980 Offset = CurDAG->getSignedTargetConstant(Val: ConstantVal, DL: SDLoc(Offset),
1981 VT: Offset.getValueType());
1982 }
1983
1984 unsigned Opcode = 0;
1985 switch (Load->getMemoryVT().getSimpleVT().SimpleTy) {
1986 case MVT::i8:
1987 if (Simm12 && SignExtend)
1988 Opcode = RISCV::CV_LB_ri_inc;
1989 else if (Simm12 && !SignExtend)
1990 Opcode = RISCV::CV_LBU_ri_inc;
1991 else if (!Simm12 && SignExtend)
1992 Opcode = RISCV::CV_LB_rr_inc;
1993 else
1994 Opcode = RISCV::CV_LBU_rr_inc;
1995 break;
1996 case MVT::i16:
1997 if (Simm12 && SignExtend)
1998 Opcode = RISCV::CV_LH_ri_inc;
1999 else if (Simm12 && !SignExtend)
2000 Opcode = RISCV::CV_LHU_ri_inc;
2001 else if (!Simm12 && SignExtend)
2002 Opcode = RISCV::CV_LH_rr_inc;
2003 else
2004 Opcode = RISCV::CV_LHU_rr_inc;
2005 break;
2006 case MVT::i32:
2007 if (Simm12)
2008 Opcode = RISCV::CV_LW_ri_inc;
2009 else
2010 Opcode = RISCV::CV_LW_rr_inc;
2011 break;
2012 default:
2013 break;
2014 }
2015 if (!Opcode)
2016 break;
2017
2018 ReplaceNode(F: Node, T: CurDAG->getMachineNode(Opcode, dl: DL, VT1: XLenVT, VT2: XLenVT,
2019 VT3: Chain.getSimpleValueType(), Op1: Base,
2020 Op2: Offset, Op3: Chain));
2021 return;
2022 }
2023 break;
2024 }
2025 case RISCVISD::LD_RV32: {
2026 assert(Subtarget->hasStdExtZilsd() && "LD_RV32 is only used with Zilsd");
2027
2028 SDValue Base, Offset;
2029 SDValue Chain = Node->getOperand(Num: 0);
2030 SDValue Addr = Node->getOperand(Num: 1);
2031 SelectAddrRegImm(Addr, Base, Offset);
2032
2033 SDValue Ops[] = {Base, Offset, Chain};
2034 MachineSDNode *New = CurDAG->getMachineNode(
2035 Opcode: RISCV::LD_RV32, dl: DL, ResultTys: {MVT::Untyped, MVT::Other}, Ops);
2036 auto [Lo, Hi] = extractGPRPair(CurDAG, DL, Pair: SDValue(New, 0));
2037 CurDAG->setNodeMemRefs(N: New, NewMemRefs: {cast<MemSDNode>(Val: Node)->getMemOperand()});
2038 ReplaceUses(F: SDValue(Node, 0), T: Lo);
2039 ReplaceUses(F: SDValue(Node, 1), T: Hi);
2040 ReplaceUses(F: SDValue(Node, 2), T: SDValue(New, 1));
2041 CurDAG->RemoveDeadNode(N: Node);
2042 return;
2043 }
2044 case RISCVISD::SD_RV32: {
2045 SDValue Base, Offset;
2046 SDValue Chain = Node->getOperand(Num: 0);
2047 SDValue Addr = Node->getOperand(Num: 3);
2048 SelectAddrRegImm(Addr, Base, Offset);
2049
2050 SDValue Lo = Node->getOperand(Num: 1);
2051 SDValue Hi = Node->getOperand(Num: 2);
2052
2053 SDValue RegPair;
2054 // Peephole to use X0_Pair for storing zero.
2055 if (isNullConstant(V: Lo) && isNullConstant(V: Hi)) {
2056 RegPair = CurDAG->getRegister(Reg: RISCV::X0_Pair, VT: MVT::Untyped);
2057 } else {
2058 RegPair = buildGPRPair(CurDAG, DL, VT: MVT::Untyped, Lo, Hi);
2059 }
2060
2061 MachineSDNode *New = CurDAG->getMachineNode(Opcode: RISCV::SD_RV32, dl: DL, VT: MVT::Other,
2062 Ops: {RegPair, Base, Offset, Chain});
2063 CurDAG->setNodeMemRefs(N: New, NewMemRefs: {cast<MemSDNode>(Val: Node)->getMemOperand()});
2064 ReplaceUses(F: SDValue(Node, 0), T: SDValue(New, 0));
2065 CurDAG->RemoveDeadNode(N: Node);
2066 return;
2067 }
2068 case RISCVISD::ADDD:
2069 // Try to match WMACC pattern: ADDD where one operand pair comes from a
2070 // widening multiply.
2071 if (tryWideningMulAcc(Node, DL))
2072 return;
2073
2074 // Fall through to regular ADDD selection.
2075 [[fallthrough]];
2076 case RISCVISD::SUBD:
2077 case RISCVISD::WADDAU:
2078 case RISCVISD::WSUBAU:
2079 case RISCVISD::WADDA:
2080 case RISCVISD::WSUBA: {
2081 assert(!Subtarget->is64Bit() && Subtarget->hasStdExtP() &&
2082 "Unexpected opcode");
2083
2084 SDValue Op0Lo = Node->getOperand(Num: 0);
2085 SDValue Op0Hi = Node->getOperand(Num: 1);
2086
2087 SDValue Op0;
2088 if (isNullConstant(V: Op0Lo) && isNullConstant(V: Op0Hi)) {
2089 Op0 = CurDAG->getRegister(Reg: RISCV::X0_Pair, VT: MVT::Untyped);
2090 } else {
2091 Op0 = buildGPRPair(CurDAG, DL, VT: MVT::Untyped, Lo: Op0Lo, Hi: Op0Hi);
2092 }
2093
2094 SDValue Op1Lo = Node->getOperand(Num: 2);
2095 SDValue Op1Hi = Node->getOperand(Num: 3);
2096
2097 MachineSDNode *New;
2098 if (Opcode == RISCVISD::WADDAU || Opcode == RISCVISD::WSUBAU ||
2099 Opcode == RISCVISD::WADDA || Opcode == RISCVISD::WSUBA) {
2100 // Widening accumulate: Op0 is the accumulator (GPRPair), Op1Lo and Op1Hi
2101 // are the two 32-bit values.
2102 unsigned Opc;
2103 switch (Opcode) {
2104 default:
2105 llvm_unreachable("Unexpected opcode");
2106 case RISCVISD::WADDAU:
2107 Opc = RISCV::WADDAU;
2108 break;
2109 case RISCVISD::WSUBAU:
2110 Opc = RISCV::WSUBAU;
2111 break;
2112 case RISCVISD::WADDA:
2113 Opc = RISCV::WADDA;
2114 break;
2115 case RISCVISD::WSUBA:
2116 Opc = RISCV::WSUBA;
2117 break;
2118 }
2119 New = CurDAG->getMachineNode(Opcode: Opc, dl: DL, VT: MVT::Untyped, Op1: Op0, Op2: Op1Lo, Op3: Op1Hi);
2120 } else {
2121 SDValue Op1 = buildGPRPair(CurDAG, DL, VT: MVT::Untyped, Lo: Op1Lo, Hi: Op1Hi);
2122
2123 unsigned Opc;
2124 switch (Opcode) {
2125 default:
2126 llvm_unreachable("Unexpected opcode");
2127 case RISCVISD::ADDD:
2128 Opc = RISCV::ADDD;
2129 break;
2130 case RISCVISD::SUBD:
2131 Opc = RISCV::SUBD;
2132 break;
2133 }
2134 New = CurDAG->getMachineNode(Opcode: Opc, dl: DL, VT: MVT::Untyped, Op1: Op0, Op2: Op1);
2135 }
2136
2137 auto [Lo, Hi] = extractGPRPair(CurDAG, DL, Pair: SDValue(New, 0));
2138 ReplaceUses(F: SDValue(Node, 0), T: Lo);
2139 ReplaceUses(F: SDValue(Node, 1), T: Hi);
2140 CurDAG->RemoveDeadNode(N: Node);
2141 return;
2142 }
2143 case ISD::INTRINSIC_WO_CHAIN: {
2144 unsigned IntNo = Node->getConstantOperandVal(Num: 0);
2145 switch (IntNo) {
2146 // By default we do not custom select any intrinsic.
2147 default:
2148 break;
2149 case Intrinsic::riscv_vmsgeu:
2150 case Intrinsic::riscv_vmsge: {
2151 SDValue Src1 = Node->getOperand(Num: 1);
2152 SDValue Src2 = Node->getOperand(Num: 2);
2153 bool IsUnsigned = IntNo == Intrinsic::riscv_vmsgeu;
2154 bool IsCmpConstant = false;
2155 bool IsCmpMinimum = false;
2156 // Only custom select scalar second operand.
2157 if (Src2.getValueType() != XLenVT)
2158 break;
2159 // Small constants are handled with patterns.
2160 int64_t CVal = 0;
2161 MVT Src1VT = Src1.getSimpleValueType();
2162 if (auto *C = dyn_cast<ConstantSDNode>(Val&: Src2)) {
2163 IsCmpConstant = true;
2164 CVal = C->getSExtValue();
2165 if (CVal >= -15 && CVal <= 16) {
2166 if (!IsUnsigned || CVal != 0)
2167 break;
2168 IsCmpMinimum = true;
2169 } else if (!IsUnsigned && CVal == APInt::getSignedMinValue(
2170 numBits: Src1VT.getScalarSizeInBits())
2171 .getSExtValue()) {
2172 IsCmpMinimum = true;
2173 }
2174 }
2175 unsigned VMSLTOpcode, VMNANDOpcode, VMSetOpcode, VMSGTOpcode;
2176 switch (RISCVTargetLowering::getLMUL(VT: Src1VT)) {
2177 default:
2178 llvm_unreachable("Unexpected LMUL!");
2179#define CASE_VMSLT_OPCODES(lmulenum, suffix) \
2180 case RISCVVType::lmulenum: \
2181 VMSLTOpcode = IsUnsigned ? RISCV::PseudoVMSLTU_VX_##suffix \
2182 : RISCV::PseudoVMSLT_VX_##suffix; \
2183 VMSGTOpcode = IsUnsigned ? RISCV::PseudoVMSGTU_VX_##suffix \
2184 : RISCV::PseudoVMSGT_VX_##suffix; \
2185 break;
2186 CASE_VMSLT_OPCODES(LMUL_F8, MF8)
2187 CASE_VMSLT_OPCODES(LMUL_F4, MF4)
2188 CASE_VMSLT_OPCODES(LMUL_F2, MF2)
2189 CASE_VMSLT_OPCODES(LMUL_1, M1)
2190 CASE_VMSLT_OPCODES(LMUL_2, M2)
2191 CASE_VMSLT_OPCODES(LMUL_4, M4)
2192 CASE_VMSLT_OPCODES(LMUL_8, M8)
2193#undef CASE_VMSLT_OPCODES
2194 }
2195 // Mask operations use the LMUL from the mask type.
2196 switch (RISCVTargetLowering::getLMUL(VT)) {
2197 default:
2198 llvm_unreachable("Unexpected LMUL!");
2199#define CASE_VMNAND_VMSET_OPCODES(lmulenum, suffix) \
2200 case RISCVVType::lmulenum: \
2201 VMNANDOpcode = RISCV::PseudoVMNAND_MM_##suffix; \
2202 VMSetOpcode = RISCV::PseudoVMSET_M_##suffix; \
2203 break;
2204 CASE_VMNAND_VMSET_OPCODES(LMUL_F8, B64)
2205 CASE_VMNAND_VMSET_OPCODES(LMUL_F4, B32)
2206 CASE_VMNAND_VMSET_OPCODES(LMUL_F2, B16)
2207 CASE_VMNAND_VMSET_OPCODES(LMUL_1, B8)
2208 CASE_VMNAND_VMSET_OPCODES(LMUL_2, B4)
2209 CASE_VMNAND_VMSET_OPCODES(LMUL_4, B2)
2210 CASE_VMNAND_VMSET_OPCODES(LMUL_8, B1)
2211#undef CASE_VMNAND_VMSET_OPCODES
2212 }
2213 SDValue SEW = CurDAG->getTargetConstant(
2214 Val: Log2_32(Value: Src1VT.getScalarSizeInBits()), DL, VT: XLenVT);
2215 SDValue MaskSEW = CurDAG->getTargetConstant(Val: 0, DL, VT: XLenVT);
2216 SDValue VL;
2217 selectVLOp(N: Node->getOperand(Num: 3), VL);
2218
2219 // If vmsge(u) with minimum value, expand it to vmset.
2220 if (IsCmpMinimum) {
2221 ReplaceNode(F: Node,
2222 T: CurDAG->getMachineNode(Opcode: VMSetOpcode, dl: DL, VT, Op1: VL, Op2: MaskSEW));
2223 return;
2224 }
2225
2226 if (IsCmpConstant) {
2227 SDValue Imm =
2228 selectImm(CurDAG, DL: SDLoc(Src2), VT: XLenVT, Imm: CVal - 1, Subtarget: *Subtarget);
2229
2230 ReplaceNode(F: Node, T: CurDAG->getMachineNode(Opcode: VMSGTOpcode, dl: DL, VT,
2231 Ops: {Src1, Imm, VL, SEW}));
2232 return;
2233 }
2234
2235 // Expand to
2236 // vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd
2237 SDValue Cmp = SDValue(
2238 CurDAG->getMachineNode(Opcode: VMSLTOpcode, dl: DL, VT, Ops: {Src1, Src2, VL, SEW}),
2239 0);
2240 ReplaceNode(F: Node, T: CurDAG->getMachineNode(Opcode: VMNANDOpcode, dl: DL, VT,
2241 Ops: {Cmp, Cmp, VL, MaskSEW}));
2242 return;
2243 }
2244 case Intrinsic::riscv_vmsgeu_mask:
2245 case Intrinsic::riscv_vmsge_mask: {
2246 SDValue Src1 = Node->getOperand(Num: 2);
2247 SDValue Src2 = Node->getOperand(Num: 3);
2248 bool IsUnsigned = IntNo == Intrinsic::riscv_vmsgeu_mask;
2249 bool IsCmpConstant = false;
2250 bool IsCmpMinimum = false;
2251 // Only custom select scalar second operand.
2252 if (Src2.getValueType() != XLenVT)
2253 break;
2254 // Small constants are handled with patterns.
2255 MVT Src1VT = Src1.getSimpleValueType();
2256 int64_t CVal = 0;
2257 if (auto *C = dyn_cast<ConstantSDNode>(Val&: Src2)) {
2258 IsCmpConstant = true;
2259 CVal = C->getSExtValue();
2260 if (CVal >= -15 && CVal <= 16) {
2261 if (!IsUnsigned || CVal != 0)
2262 break;
2263 IsCmpMinimum = true;
2264 } else if (!IsUnsigned && CVal == APInt::getSignedMinValue(
2265 numBits: Src1VT.getScalarSizeInBits())
2266 .getSExtValue()) {
2267 IsCmpMinimum = true;
2268 }
2269 }
2270 unsigned VMSLTOpcode, VMSLTMaskOpcode, VMXOROpcode, VMANDNOpcode,
2271 VMOROpcode, VMSGTMaskOpcode;
2272 switch (RISCVTargetLowering::getLMUL(VT: Src1VT)) {
2273 default:
2274 llvm_unreachable("Unexpected LMUL!");
2275#define CASE_VMSLT_OPCODES(lmulenum, suffix) \
2276 case RISCVVType::lmulenum: \
2277 VMSLTOpcode = IsUnsigned ? RISCV::PseudoVMSLTU_VX_##suffix \
2278 : RISCV::PseudoVMSLT_VX_##suffix; \
2279 VMSLTMaskOpcode = IsUnsigned ? RISCV::PseudoVMSLTU_VX_##suffix##_MASK \
2280 : RISCV::PseudoVMSLT_VX_##suffix##_MASK; \
2281 VMSGTMaskOpcode = IsUnsigned ? RISCV::PseudoVMSGTU_VX_##suffix##_MASK \
2282 : RISCV::PseudoVMSGT_VX_##suffix##_MASK; \
2283 break;
2284 CASE_VMSLT_OPCODES(LMUL_F8, MF8)
2285 CASE_VMSLT_OPCODES(LMUL_F4, MF4)
2286 CASE_VMSLT_OPCODES(LMUL_F2, MF2)
2287 CASE_VMSLT_OPCODES(LMUL_1, M1)
2288 CASE_VMSLT_OPCODES(LMUL_2, M2)
2289 CASE_VMSLT_OPCODES(LMUL_4, M4)
2290 CASE_VMSLT_OPCODES(LMUL_8, M8)
2291#undef CASE_VMSLT_OPCODES
2292 }
2293 // Mask operations use the LMUL from the mask type.
2294 switch (RISCVTargetLowering::getLMUL(VT)) {
2295 default:
2296 llvm_unreachable("Unexpected LMUL!");
2297#define CASE_VMXOR_VMANDN_VMOR_OPCODES(lmulenum, suffix) \
2298 case RISCVVType::lmulenum: \
2299 VMXOROpcode = RISCV::PseudoVMXOR_MM_##suffix; \
2300 VMANDNOpcode = RISCV::PseudoVMANDN_MM_##suffix; \
2301 VMOROpcode = RISCV::PseudoVMOR_MM_##suffix; \
2302 break;
2303 CASE_VMXOR_VMANDN_VMOR_OPCODES(LMUL_F8, B64)
2304 CASE_VMXOR_VMANDN_VMOR_OPCODES(LMUL_F4, B32)
2305 CASE_VMXOR_VMANDN_VMOR_OPCODES(LMUL_F2, B16)
2306 CASE_VMXOR_VMANDN_VMOR_OPCODES(LMUL_1, B8)
2307 CASE_VMXOR_VMANDN_VMOR_OPCODES(LMUL_2, B4)
2308 CASE_VMXOR_VMANDN_VMOR_OPCODES(LMUL_4, B2)
2309 CASE_VMXOR_VMANDN_VMOR_OPCODES(LMUL_8, B1)
2310#undef CASE_VMXOR_VMANDN_VMOR_OPCODES
2311 }
2312 SDValue SEW = CurDAG->getTargetConstant(
2313 Val: Log2_32(Value: Src1VT.getScalarSizeInBits()), DL, VT: XLenVT);
2314 SDValue MaskSEW = CurDAG->getTargetConstant(Val: 0, DL, VT: XLenVT);
2315 SDValue VL;
2316 selectVLOp(N: Node->getOperand(Num: 5), VL);
2317 SDValue MaskedOff = Node->getOperand(Num: 1);
2318 SDValue Mask = Node->getOperand(Num: 4);
2319
2320 // If vmsge(u) with minimum value, expand it to vmor mask, maskedoff.
2321 if (IsCmpMinimum) {
2322 // We don't need vmor if the MaskedOff and the Mask are the same
2323 // value.
2324 if (Mask == MaskedOff) {
2325 ReplaceUses(F: Node, T: Mask.getNode());
2326 return;
2327 }
2328 ReplaceNode(F: Node,
2329 T: CurDAG->getMachineNode(Opcode: VMOROpcode, dl: DL, VT,
2330 Ops: {Mask, MaskedOff, VL, MaskSEW}));
2331 return;
2332 }
2333
2334 // If the MaskedOff value and the Mask are the same value use
2335 // vmslt{u}.vx vt, va, x; vmandn.mm vd, vd, vt
2336 // This avoids needing to copy v0 to vd before starting the next sequence.
2337 if (Mask == MaskedOff) {
2338 SDValue Cmp = SDValue(
2339 CurDAG->getMachineNode(Opcode: VMSLTOpcode, dl: DL, VT, Ops: {Src1, Src2, VL, SEW}),
2340 0);
2341 ReplaceNode(F: Node, T: CurDAG->getMachineNode(Opcode: VMANDNOpcode, dl: DL, VT,
2342 Ops: {Mask, Cmp, VL, MaskSEW}));
2343 return;
2344 }
2345
2346 SDValue PolicyOp =
2347 CurDAG->getTargetConstant(Val: RISCVVType::TAIL_AGNOSTIC, DL, VT: XLenVT);
2348
2349 if (IsCmpConstant) {
2350 SDValue Imm =
2351 selectImm(CurDAG, DL: SDLoc(Src2), VT: XLenVT, Imm: CVal - 1, Subtarget: *Subtarget);
2352
2353 ReplaceNode(F: Node, T: CurDAG->getMachineNode(
2354 Opcode: VMSGTMaskOpcode, dl: DL, VT,
2355 Ops: {MaskedOff, Src1, Imm, Mask, VL, SEW, PolicyOp}));
2356 return;
2357 }
2358
2359 // Otherwise use
2360 // vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0
2361 // The result is mask undisturbed.
2362 // We use the same instructions to emulate mask agnostic behavior, because
2363 // the agnostic result can be either undisturbed or all 1.
2364 SDValue Cmp = SDValue(CurDAG->getMachineNode(Opcode: VMSLTMaskOpcode, dl: DL, VT,
2365 Ops: {MaskedOff, Src1, Src2, Mask,
2366 VL, SEW, PolicyOp}),
2367 0);
2368 // vmxor.mm vd, vd, v0 is used to update active value.
2369 ReplaceNode(F: Node, T: CurDAG->getMachineNode(Opcode: VMXOROpcode, dl: DL, VT,
2370 Ops: {Cmp, Mask, VL, MaskSEW}));
2371 return;
2372 }
2373 case Intrinsic::riscv_vsetvli:
2374 case Intrinsic::riscv_vsetvlimax:
2375 return selectVSETVLI(Node);
2376 case Intrinsic::riscv_sf_vsettnt:
2377 case Intrinsic::riscv_sf_vsettm:
2378 case Intrinsic::riscv_sf_vsettk:
2379 return selectXSfmmVSET(Node);
2380 }
2381 break;
2382 }
2383 case ISD::INTRINSIC_W_CHAIN: {
2384 unsigned IntNo = Node->getConstantOperandVal(Num: 1);
2385 switch (IntNo) {
2386 // By default we do not custom select any intrinsic.
2387 default:
2388 break;
2389 case Intrinsic::riscv_vlseg2:
2390 case Intrinsic::riscv_vlseg3:
2391 case Intrinsic::riscv_vlseg4:
2392 case Intrinsic::riscv_vlseg5:
2393 case Intrinsic::riscv_vlseg6:
2394 case Intrinsic::riscv_vlseg7:
2395 case Intrinsic::riscv_vlseg8: {
2396 selectVLSEG(Node, NF: getSegInstNF(Intrinsic: IntNo), /*IsMasked*/ false,
2397 /*IsStrided*/ false);
2398 return;
2399 }
2400 case Intrinsic::riscv_vlseg2_mask:
2401 case Intrinsic::riscv_vlseg3_mask:
2402 case Intrinsic::riscv_vlseg4_mask:
2403 case Intrinsic::riscv_vlseg5_mask:
2404 case Intrinsic::riscv_vlseg6_mask:
2405 case Intrinsic::riscv_vlseg7_mask:
2406 case Intrinsic::riscv_vlseg8_mask: {
2407 selectVLSEG(Node, NF: getSegInstNF(Intrinsic: IntNo), /*IsMasked*/ true,
2408 /*IsStrided*/ false);
2409 return;
2410 }
2411 case Intrinsic::riscv_vlsseg2:
2412 case Intrinsic::riscv_vlsseg3:
2413 case Intrinsic::riscv_vlsseg4:
2414 case Intrinsic::riscv_vlsseg5:
2415 case Intrinsic::riscv_vlsseg6:
2416 case Intrinsic::riscv_vlsseg7:
2417 case Intrinsic::riscv_vlsseg8: {
2418 selectVLSEG(Node, NF: getSegInstNF(Intrinsic: IntNo), /*IsMasked*/ false,
2419 /*IsStrided*/ true);
2420 return;
2421 }
2422 case Intrinsic::riscv_vlsseg2_mask:
2423 case Intrinsic::riscv_vlsseg3_mask:
2424 case Intrinsic::riscv_vlsseg4_mask:
2425 case Intrinsic::riscv_vlsseg5_mask:
2426 case Intrinsic::riscv_vlsseg6_mask:
2427 case Intrinsic::riscv_vlsseg7_mask:
2428 case Intrinsic::riscv_vlsseg8_mask: {
2429 selectVLSEG(Node, NF: getSegInstNF(Intrinsic: IntNo), /*IsMasked*/ true,
2430 /*IsStrided*/ true);
2431 return;
2432 }
2433 case Intrinsic::riscv_vloxseg2:
2434 case Intrinsic::riscv_vloxseg3:
2435 case Intrinsic::riscv_vloxseg4:
2436 case Intrinsic::riscv_vloxseg5:
2437 case Intrinsic::riscv_vloxseg6:
2438 case Intrinsic::riscv_vloxseg7:
2439 case Intrinsic::riscv_vloxseg8:
2440 selectVLXSEG(Node, NF: getSegInstNF(Intrinsic: IntNo), /*IsMasked*/ false,
2441 /*IsOrdered*/ true);
2442 return;
2443 case Intrinsic::riscv_vluxseg2:
2444 case Intrinsic::riscv_vluxseg3:
2445 case Intrinsic::riscv_vluxseg4:
2446 case Intrinsic::riscv_vluxseg5:
2447 case Intrinsic::riscv_vluxseg6:
2448 case Intrinsic::riscv_vluxseg7:
2449 case Intrinsic::riscv_vluxseg8:
2450 selectVLXSEG(Node, NF: getSegInstNF(Intrinsic: IntNo), /*IsMasked*/ false,
2451 /*IsOrdered*/ false);
2452 return;
2453 case Intrinsic::riscv_vloxseg2_mask:
2454 case Intrinsic::riscv_vloxseg3_mask:
2455 case Intrinsic::riscv_vloxseg4_mask:
2456 case Intrinsic::riscv_vloxseg5_mask:
2457 case Intrinsic::riscv_vloxseg6_mask:
2458 case Intrinsic::riscv_vloxseg7_mask:
2459 case Intrinsic::riscv_vloxseg8_mask:
2460 selectVLXSEG(Node, NF: getSegInstNF(Intrinsic: IntNo), /*IsMasked*/ true,
2461 /*IsOrdered*/ true);
2462 return;
2463 case Intrinsic::riscv_vluxseg2_mask:
2464 case Intrinsic::riscv_vluxseg3_mask:
2465 case Intrinsic::riscv_vluxseg4_mask:
2466 case Intrinsic::riscv_vluxseg5_mask:
2467 case Intrinsic::riscv_vluxseg6_mask:
2468 case Intrinsic::riscv_vluxseg7_mask:
2469 case Intrinsic::riscv_vluxseg8_mask:
2470 selectVLXSEG(Node, NF: getSegInstNF(Intrinsic: IntNo), /*IsMasked*/ true,
2471 /*IsOrdered*/ false);
2472 return;
2473 case Intrinsic::riscv_vlseg8ff:
2474 case Intrinsic::riscv_vlseg7ff:
2475 case Intrinsic::riscv_vlseg6ff:
2476 case Intrinsic::riscv_vlseg5ff:
2477 case Intrinsic::riscv_vlseg4ff:
2478 case Intrinsic::riscv_vlseg3ff:
2479 case Intrinsic::riscv_vlseg2ff: {
2480 selectVLSEGFF(Node, NF: getSegInstNF(Intrinsic: IntNo), /*IsMasked*/ false);
2481 return;
2482 }
2483 case Intrinsic::riscv_vlseg8ff_mask:
2484 case Intrinsic::riscv_vlseg7ff_mask:
2485 case Intrinsic::riscv_vlseg6ff_mask:
2486 case Intrinsic::riscv_vlseg5ff_mask:
2487 case Intrinsic::riscv_vlseg4ff_mask:
2488 case Intrinsic::riscv_vlseg3ff_mask:
2489 case Intrinsic::riscv_vlseg2ff_mask: {
2490 selectVLSEGFF(Node, NF: getSegInstNF(Intrinsic: IntNo), /*IsMasked*/ true);
2491 return;
2492 }
2493 case Intrinsic::riscv_vloxei:
2494 case Intrinsic::riscv_vloxei_mask:
2495 case Intrinsic::riscv_vluxei:
2496 case Intrinsic::riscv_vluxei_mask: {
2497 bool IsMasked = IntNo == Intrinsic::riscv_vloxei_mask ||
2498 IntNo == Intrinsic::riscv_vluxei_mask;
2499 bool IsOrdered = IntNo == Intrinsic::riscv_vloxei ||
2500 IntNo == Intrinsic::riscv_vloxei_mask;
2501
2502 MVT VT = Node->getSimpleValueType(ResNo: 0);
2503 unsigned Log2SEW = Log2_32(Value: VT.getScalarSizeInBits());
2504
2505 unsigned CurOp = 2;
2506 SmallVector<SDValue, 8> Operands;
2507 Operands.push_back(Elt: Node->getOperand(Num: CurOp++));
2508
2509 MVT IndexVT;
2510 addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked,
2511 /*IsStridedOrIndexed*/ true, Operands,
2512 /*IsLoad=*/true, IndexVT: &IndexVT);
2513
2514 assert(VT.getVectorElementCount() == IndexVT.getVectorElementCount() &&
2515 "Element count mismatch");
2516
2517 RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
2518 RISCVVType::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(VT: IndexVT);
2519 unsigned IndexLog2EEW = Log2_32(Value: IndexVT.getScalarSizeInBits());
2520 if (IndexLog2EEW == 6 && !Subtarget->is64Bit()) {
2521 reportFatalUsageError(reason: "The V extension does not support EEW=64 for "
2522 "index values when XLEN=32");
2523 }
2524 const RISCV::VLX_VSXPseudo *P = RISCV::getVLXPseudo(
2525 Masked: IsMasked, Ordered: IsOrdered, Log2SEW: IndexLog2EEW, LMUL: static_cast<unsigned>(LMUL),
2526 IndexLMUL: static_cast<unsigned>(IndexLMUL));
2527 MachineSDNode *Load =
2528 CurDAG->getMachineNode(Opcode: P->Pseudo, dl: DL, VTs: Node->getVTList(), Ops: Operands);
2529
2530 CurDAG->setNodeMemRefs(N: Load, NewMemRefs: {cast<MemSDNode>(Val: Node)->getMemOperand()});
2531
2532 ReplaceNode(F: Node, T: Load);
2533 return;
2534 }
2535 case Intrinsic::riscv_vlm:
2536 case Intrinsic::riscv_vle:
2537 case Intrinsic::riscv_vle_mask:
2538 case Intrinsic::riscv_vlse:
2539 case Intrinsic::riscv_vlse_mask: {
2540 bool IsMasked = IntNo == Intrinsic::riscv_vle_mask ||
2541 IntNo == Intrinsic::riscv_vlse_mask;
2542 bool IsStrided =
2543 IntNo == Intrinsic::riscv_vlse || IntNo == Intrinsic::riscv_vlse_mask;
2544
2545 MVT VT = Node->getSimpleValueType(ResNo: 0);
2546 unsigned Log2SEW = Log2_32(Value: VT.getScalarSizeInBits());
2547
2548 // The riscv_vlm intrinsic are always tail agnostic and no passthru
2549 // operand at the IR level. In pseudos, they have both policy and
2550 // passthru operand. The passthru operand is needed to track the
2551 // "tail undefined" state, and the policy is there just for
2552 // for consistency - it will always be "don't care" for the
2553 // unmasked form.
2554 bool HasPassthruOperand = IntNo != Intrinsic::riscv_vlm;
2555 unsigned CurOp = 2;
2556 SmallVector<SDValue, 8> Operands;
2557 if (HasPassthruOperand)
2558 Operands.push_back(Elt: Node->getOperand(Num: CurOp++));
2559 else {
2560 // We eagerly lower to implicit_def (instead of undef), as we
2561 // otherwise fail to select nodes such as: nxv1i1 = undef
2562 SDNode *Passthru =
2563 CurDAG->getMachineNode(Opcode: TargetOpcode::IMPLICIT_DEF, dl: DL, VT);
2564 Operands.push_back(Elt: SDValue(Passthru, 0));
2565 }
2566 addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked, IsStridedOrIndexed: IsStrided,
2567 Operands, /*IsLoad=*/true);
2568
2569 RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
2570 const RISCV::VLEPseudo *P =
2571 RISCV::getVLEPseudo(Masked: IsMasked, Strided: IsStrided, /*FF*/ false, Log2SEW,
2572 LMUL: static_cast<unsigned>(LMUL));
2573 MachineSDNode *Load =
2574 CurDAG->getMachineNode(Opcode: P->Pseudo, dl: DL, VTs: Node->getVTList(), Ops: Operands);
2575
2576 CurDAG->setNodeMemRefs(N: Load, NewMemRefs: {cast<MemSDNode>(Val: Node)->getMemOperand()});
2577
2578 ReplaceNode(F: Node, T: Load);
2579 return;
2580 }
2581 case Intrinsic::riscv_vleff:
2582 case Intrinsic::riscv_vleff_mask: {
2583 bool IsMasked = IntNo == Intrinsic::riscv_vleff_mask;
2584
2585 MVT VT = Node->getSimpleValueType(ResNo: 0);
2586 unsigned Log2SEW = Log2_32(Value: VT.getScalarSizeInBits());
2587
2588 unsigned CurOp = 2;
2589 SmallVector<SDValue, 7> Operands;
2590 Operands.push_back(Elt: Node->getOperand(Num: CurOp++));
2591 addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked,
2592 /*IsStridedOrIndexed*/ false, Operands,
2593 /*IsLoad=*/true);
2594
2595 RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
2596 const RISCV::VLEPseudo *P =
2597 RISCV::getVLEPseudo(Masked: IsMasked, /*Strided*/ false, /*FF*/ true,
2598 Log2SEW, LMUL: static_cast<unsigned>(LMUL));
2599 MachineSDNode *Load = CurDAG->getMachineNode(
2600 Opcode: P->Pseudo, dl: DL, VTs: Node->getVTList(), Ops: Operands);
2601 CurDAG->setNodeMemRefs(N: Load, NewMemRefs: {cast<MemSDNode>(Val: Node)->getMemOperand()});
2602
2603 ReplaceNode(F: Node, T: Load);
2604 return;
2605 }
2606 case Intrinsic::riscv_nds_vln:
2607 case Intrinsic::riscv_nds_vln_mask:
2608 case Intrinsic::riscv_nds_vlnu:
2609 case Intrinsic::riscv_nds_vlnu_mask: {
2610 bool IsMasked = IntNo == Intrinsic::riscv_nds_vln_mask ||
2611 IntNo == Intrinsic::riscv_nds_vlnu_mask;
2612 bool IsUnsigned = IntNo == Intrinsic::riscv_nds_vlnu ||
2613 IntNo == Intrinsic::riscv_nds_vlnu_mask;
2614
2615 MVT VT = Node->getSimpleValueType(ResNo: 0);
2616 unsigned Log2SEW = Log2_32(Value: VT.getScalarSizeInBits());
2617 unsigned CurOp = 2;
2618 SmallVector<SDValue, 8> Operands;
2619
2620 Operands.push_back(Elt: Node->getOperand(Num: CurOp++));
2621 addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked,
2622 /*IsStridedOrIndexed=*/false, Operands,
2623 /*IsLoad=*/true);
2624
2625 RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
2626 const RISCV::NDSVLNPseudo *P = RISCV::getNDSVLNPseudo(
2627 Masked: IsMasked, Unsigned: IsUnsigned, Log2SEW, LMUL: static_cast<unsigned>(LMUL));
2628 MachineSDNode *Load =
2629 CurDAG->getMachineNode(Opcode: P->Pseudo, dl: DL, VTs: Node->getVTList(), Ops: Operands);
2630
2631 if (auto *MemOp = dyn_cast<MemSDNode>(Val: Node))
2632 CurDAG->setNodeMemRefs(N: Load, NewMemRefs: {MemOp->getMemOperand()});
2633
2634 ReplaceNode(F: Node, T: Load);
2635 return;
2636 }
2637 }
2638 break;
2639 }
2640 case ISD::INTRINSIC_VOID: {
2641 unsigned IntNo = Node->getConstantOperandVal(Num: 1);
2642 switch (IntNo) {
2643 case Intrinsic::riscv_vsseg2:
2644 case Intrinsic::riscv_vsseg3:
2645 case Intrinsic::riscv_vsseg4:
2646 case Intrinsic::riscv_vsseg5:
2647 case Intrinsic::riscv_vsseg6:
2648 case Intrinsic::riscv_vsseg7:
2649 case Intrinsic::riscv_vsseg8: {
2650 selectVSSEG(Node, NF: getSegInstNF(Intrinsic: IntNo), /*IsMasked*/ false,
2651 /*IsStrided*/ false);
2652 return;
2653 }
2654 case Intrinsic::riscv_vsseg2_mask:
2655 case Intrinsic::riscv_vsseg3_mask:
2656 case Intrinsic::riscv_vsseg4_mask:
2657 case Intrinsic::riscv_vsseg5_mask:
2658 case Intrinsic::riscv_vsseg6_mask:
2659 case Intrinsic::riscv_vsseg7_mask:
2660 case Intrinsic::riscv_vsseg8_mask: {
2661 selectVSSEG(Node, NF: getSegInstNF(Intrinsic: IntNo), /*IsMasked*/ true,
2662 /*IsStrided*/ false);
2663 return;
2664 }
2665 case Intrinsic::riscv_vssseg2:
2666 case Intrinsic::riscv_vssseg3:
2667 case Intrinsic::riscv_vssseg4:
2668 case Intrinsic::riscv_vssseg5:
2669 case Intrinsic::riscv_vssseg6:
2670 case Intrinsic::riscv_vssseg7:
2671 case Intrinsic::riscv_vssseg8: {
2672 selectVSSEG(Node, NF: getSegInstNF(Intrinsic: IntNo), /*IsMasked*/ false,
2673 /*IsStrided*/ true);
2674 return;
2675 }
2676 case Intrinsic::riscv_vssseg2_mask:
2677 case Intrinsic::riscv_vssseg3_mask:
2678 case Intrinsic::riscv_vssseg4_mask:
2679 case Intrinsic::riscv_vssseg5_mask:
2680 case Intrinsic::riscv_vssseg6_mask:
2681 case Intrinsic::riscv_vssseg7_mask:
2682 case Intrinsic::riscv_vssseg8_mask: {
2683 selectVSSEG(Node, NF: getSegInstNF(Intrinsic: IntNo), /*IsMasked*/ true,
2684 /*IsStrided*/ true);
2685 return;
2686 }
2687 case Intrinsic::riscv_vsoxseg2:
2688 case Intrinsic::riscv_vsoxseg3:
2689 case Intrinsic::riscv_vsoxseg4:
2690 case Intrinsic::riscv_vsoxseg5:
2691 case Intrinsic::riscv_vsoxseg6:
2692 case Intrinsic::riscv_vsoxseg7:
2693 case Intrinsic::riscv_vsoxseg8:
2694 selectVSXSEG(Node, NF: getSegInstNF(Intrinsic: IntNo), /*IsMasked*/ false,
2695 /*IsOrdered*/ true);
2696 return;
2697 case Intrinsic::riscv_vsuxseg2:
2698 case Intrinsic::riscv_vsuxseg3:
2699 case Intrinsic::riscv_vsuxseg4:
2700 case Intrinsic::riscv_vsuxseg5:
2701 case Intrinsic::riscv_vsuxseg6:
2702 case Intrinsic::riscv_vsuxseg7:
2703 case Intrinsic::riscv_vsuxseg8:
2704 selectVSXSEG(Node, NF: getSegInstNF(Intrinsic: IntNo), /*IsMasked*/ false,
2705 /*IsOrdered*/ false);
2706 return;
2707 case Intrinsic::riscv_vsoxseg2_mask:
2708 case Intrinsic::riscv_vsoxseg3_mask:
2709 case Intrinsic::riscv_vsoxseg4_mask:
2710 case Intrinsic::riscv_vsoxseg5_mask:
2711 case Intrinsic::riscv_vsoxseg6_mask:
2712 case Intrinsic::riscv_vsoxseg7_mask:
2713 case Intrinsic::riscv_vsoxseg8_mask:
2714 selectVSXSEG(Node, NF: getSegInstNF(Intrinsic: IntNo), /*IsMasked*/ true,
2715 /*IsOrdered*/ true);
2716 return;
2717 case Intrinsic::riscv_vsuxseg2_mask:
2718 case Intrinsic::riscv_vsuxseg3_mask:
2719 case Intrinsic::riscv_vsuxseg4_mask:
2720 case Intrinsic::riscv_vsuxseg5_mask:
2721 case Intrinsic::riscv_vsuxseg6_mask:
2722 case Intrinsic::riscv_vsuxseg7_mask:
2723 case Intrinsic::riscv_vsuxseg8_mask:
2724 selectVSXSEG(Node, NF: getSegInstNF(Intrinsic: IntNo), /*IsMasked*/ true,
2725 /*IsOrdered*/ false);
2726 return;
2727 case Intrinsic::riscv_vsoxei:
2728 case Intrinsic::riscv_vsoxei_mask:
2729 case Intrinsic::riscv_vsuxei:
2730 case Intrinsic::riscv_vsuxei_mask: {
2731 bool IsMasked = IntNo == Intrinsic::riscv_vsoxei_mask ||
2732 IntNo == Intrinsic::riscv_vsuxei_mask;
2733 bool IsOrdered = IntNo == Intrinsic::riscv_vsoxei ||
2734 IntNo == Intrinsic::riscv_vsoxei_mask;
2735
2736 MVT VT = Node->getOperand(Num: 2)->getSimpleValueType(ResNo: 0);
2737 unsigned Log2SEW = Log2_32(Value: VT.getScalarSizeInBits());
2738
2739 unsigned CurOp = 2;
2740 SmallVector<SDValue, 8> Operands;
2741 Operands.push_back(Elt: Node->getOperand(Num: CurOp++)); // Store value.
2742
2743 MVT IndexVT;
2744 addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked,
2745 /*IsStridedOrIndexed*/ true, Operands,
2746 /*IsLoad=*/false, IndexVT: &IndexVT);
2747
2748 assert(VT.getVectorElementCount() == IndexVT.getVectorElementCount() &&
2749 "Element count mismatch");
2750
2751 RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
2752 RISCVVType::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(VT: IndexVT);
2753 unsigned IndexLog2EEW = Log2_32(Value: IndexVT.getScalarSizeInBits());
2754 if (IndexLog2EEW == 6 && !Subtarget->is64Bit()) {
2755 reportFatalUsageError(reason: "The V extension does not support EEW=64 for "
2756 "index values when XLEN=32");
2757 }
2758 const RISCV::VLX_VSXPseudo *P = RISCV::getVSXPseudo(
2759 Masked: IsMasked, Ordered: IsOrdered, Log2SEW: IndexLog2EEW,
2760 LMUL: static_cast<unsigned>(LMUL), IndexLMUL: static_cast<unsigned>(IndexLMUL));
2761 MachineSDNode *Store =
2762 CurDAG->getMachineNode(Opcode: P->Pseudo, dl: DL, VTs: Node->getVTList(), Ops: Operands);
2763
2764 CurDAG->setNodeMemRefs(N: Store, NewMemRefs: {cast<MemSDNode>(Val: Node)->getMemOperand()});
2765
2766 ReplaceNode(F: Node, T: Store);
2767 return;
2768 }
2769 case Intrinsic::riscv_vsm:
2770 case Intrinsic::riscv_vse:
2771 case Intrinsic::riscv_vse_mask:
2772 case Intrinsic::riscv_vsse:
2773 case Intrinsic::riscv_vsse_mask: {
2774 bool IsMasked = IntNo == Intrinsic::riscv_vse_mask ||
2775 IntNo == Intrinsic::riscv_vsse_mask;
2776 bool IsStrided =
2777 IntNo == Intrinsic::riscv_vsse || IntNo == Intrinsic::riscv_vsse_mask;
2778
2779 MVT VT = Node->getOperand(Num: 2)->getSimpleValueType(ResNo: 0);
2780 unsigned Log2SEW = Log2_32(Value: VT.getScalarSizeInBits());
2781
2782 unsigned CurOp = 2;
2783 SmallVector<SDValue, 8> Operands;
2784 Operands.push_back(Elt: Node->getOperand(Num: CurOp++)); // Store value.
2785
2786 addVectorLoadStoreOperands(Node, Log2SEW, DL, CurOp, IsMasked, IsStridedOrIndexed: IsStrided,
2787 Operands);
2788
2789 RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
2790 const RISCV::VSEPseudo *P = RISCV::getVSEPseudo(
2791 Masked: IsMasked, Strided: IsStrided, Log2SEW, LMUL: static_cast<unsigned>(LMUL));
2792 MachineSDNode *Store =
2793 CurDAG->getMachineNode(Opcode: P->Pseudo, dl: DL, VTs: Node->getVTList(), Ops: Operands);
2794 CurDAG->setNodeMemRefs(N: Store, NewMemRefs: {cast<MemSDNode>(Val: Node)->getMemOperand()});
2795
2796 ReplaceNode(F: Node, T: Store);
2797 return;
2798 }
2799 case Intrinsic::riscv_sf_vc_x_se:
2800 case Intrinsic::riscv_sf_vc_i_se:
2801 selectSF_VC_X_SE(Node);
2802 return;
2803 case Intrinsic::riscv_sf_vlte8:
2804 case Intrinsic::riscv_sf_vlte16:
2805 case Intrinsic::riscv_sf_vlte32:
2806 case Intrinsic::riscv_sf_vlte64: {
2807 unsigned Log2SEW;
2808 unsigned PseudoInst;
2809 switch (IntNo) {
2810 case Intrinsic::riscv_sf_vlte8:
2811 PseudoInst = RISCV::PseudoSF_VLTE8;
2812 Log2SEW = 3;
2813 break;
2814 case Intrinsic::riscv_sf_vlte16:
2815 PseudoInst = RISCV::PseudoSF_VLTE16;
2816 Log2SEW = 4;
2817 break;
2818 case Intrinsic::riscv_sf_vlte32:
2819 PseudoInst = RISCV::PseudoSF_VLTE32;
2820 Log2SEW = 5;
2821 break;
2822 case Intrinsic::riscv_sf_vlte64:
2823 PseudoInst = RISCV::PseudoSF_VLTE64;
2824 Log2SEW = 6;
2825 break;
2826 }
2827
2828 SDValue SEWOp = CurDAG->getTargetConstant(Val: Log2SEW, DL, VT: XLenVT);
2829 SDValue TWidenOp = CurDAG->getTargetConstant(Val: 1, DL, VT: XLenVT);
2830 SDValue Operands[] = {Node->getOperand(Num: 2),
2831 Node->getOperand(Num: 3),
2832 Node->getOperand(Num: 4),
2833 SEWOp,
2834 TWidenOp,
2835 Node->getOperand(Num: 0)};
2836
2837 MachineSDNode *TileLoad =
2838 CurDAG->getMachineNode(Opcode: PseudoInst, dl: DL, VTs: Node->getVTList(), Ops: Operands);
2839 CurDAG->setNodeMemRefs(N: TileLoad,
2840 NewMemRefs: {cast<MemSDNode>(Val: Node)->getMemOperand()});
2841
2842 ReplaceNode(F: Node, T: TileLoad);
2843 return;
2844 }
2845 case Intrinsic::riscv_sf_mm_s_s:
2846 case Intrinsic::riscv_sf_mm_s_u:
2847 case Intrinsic::riscv_sf_mm_u_s:
2848 case Intrinsic::riscv_sf_mm_u_u:
2849 case Intrinsic::riscv_sf_mm_e5m2_e5m2:
2850 case Intrinsic::riscv_sf_mm_e5m2_e4m3:
2851 case Intrinsic::riscv_sf_mm_e4m3_e5m2:
2852 case Intrinsic::riscv_sf_mm_e4m3_e4m3:
2853 case Intrinsic::riscv_sf_mm_f_f: {
2854 bool HasFRM = false;
2855 unsigned PseudoInst;
2856 switch (IntNo) {
2857 case Intrinsic::riscv_sf_mm_s_s:
2858 PseudoInst = RISCV::PseudoSF_MM_S_S;
2859 break;
2860 case Intrinsic::riscv_sf_mm_s_u:
2861 PseudoInst = RISCV::PseudoSF_MM_S_U;
2862 break;
2863 case Intrinsic::riscv_sf_mm_u_s:
2864 PseudoInst = RISCV::PseudoSF_MM_U_S;
2865 break;
2866 case Intrinsic::riscv_sf_mm_u_u:
2867 PseudoInst = RISCV::PseudoSF_MM_U_U;
2868 break;
2869 case Intrinsic::riscv_sf_mm_e5m2_e5m2:
2870 PseudoInst = RISCV::PseudoSF_MM_E5M2_E5M2;
2871 HasFRM = true;
2872 break;
2873 case Intrinsic::riscv_sf_mm_e5m2_e4m3:
2874 PseudoInst = RISCV::PseudoSF_MM_E5M2_E4M3;
2875 HasFRM = true;
2876 break;
2877 case Intrinsic::riscv_sf_mm_e4m3_e5m2:
2878 PseudoInst = RISCV::PseudoSF_MM_E4M3_E5M2;
2879 HasFRM = true;
2880 break;
2881 case Intrinsic::riscv_sf_mm_e4m3_e4m3:
2882 PseudoInst = RISCV::PseudoSF_MM_E4M3_E4M3;
2883 HasFRM = true;
2884 break;
2885 case Intrinsic::riscv_sf_mm_f_f:
2886 if (Node->getOperand(Num: 3).getValueType().getScalarType() == MVT::bf16)
2887 PseudoInst = RISCV::PseudoSF_MM_F_F_ALT;
2888 else
2889 PseudoInst = RISCV::PseudoSF_MM_F_F;
2890 HasFRM = true;
2891 break;
2892 }
2893 uint64_t TileNum = Node->getConstantOperandVal(Num: 2);
2894 SDValue Op1 = Node->getOperand(Num: 3);
2895 SDValue Op2 = Node->getOperand(Num: 4);
2896 MVT VT = Op1->getSimpleValueType(ResNo: 0);
2897 unsigned Log2SEW = Log2_32(Value: VT.getScalarSizeInBits());
2898 SDValue TmOp = Node->getOperand(Num: 5);
2899 SDValue TnOp = Node->getOperand(Num: 6);
2900 SDValue TkOp = Node->getOperand(Num: 7);
2901 SDValue TWidenOp = Node->getOperand(Num: 8);
2902 SDValue Chain = Node->getOperand(Num: 0);
2903
2904 // sf.mm.f.f with sew=32, twiden=2 is invalid
2905 if (IntNo == Intrinsic::riscv_sf_mm_f_f && Log2SEW == 5 &&
2906 TWidenOp->getAsZExtVal() == 2)
2907 reportFatalUsageError(reason: "sf.mm.f.f doesn't support (sew=32, twiden=2)");
2908
2909 SmallVector<SDValue, 10> Operands(
2910 {CurDAG->getRegister(Reg: getTileReg(TileNum), VT: XLenVT), Op1, Op2});
2911 if (HasFRM)
2912 Operands.push_back(
2913 Elt: CurDAG->getTargetConstant(Val: RISCVFPRndMode::DYN, DL, VT: XLenVT));
2914 Operands.append(IL: {TmOp, TnOp, TkOp,
2915 CurDAG->getTargetConstant(Val: Log2SEW, DL, VT: XLenVT), TWidenOp,
2916 Chain});
2917
2918 auto *NewNode =
2919 CurDAG->getMachineNode(Opcode: PseudoInst, dl: DL, VTs: Node->getVTList(), Ops: Operands);
2920
2921 ReplaceNode(F: Node, T: NewNode);
2922 return;
2923 }
2924 case Intrinsic::riscv_sf_vtzero_t: {
2925 uint64_t TileNum = Node->getConstantOperandVal(Num: 2);
2926 SDValue Tm = Node->getOperand(Num: 3);
2927 SDValue Tn = Node->getOperand(Num: 4);
2928 SDValue Log2SEW = Node->getOperand(Num: 5);
2929 SDValue TWiden = Node->getOperand(Num: 6);
2930 SDValue Chain = Node->getOperand(Num: 0);
2931 auto *NewNode = CurDAG->getMachineNode(
2932 Opcode: RISCV::PseudoSF_VTZERO_T, dl: DL, VTs: Node->getVTList(),
2933 Ops: {CurDAG->getRegister(Reg: getTileReg(TileNum), VT: XLenVT), Tm, Tn, Log2SEW,
2934 TWiden, Chain});
2935
2936 ReplaceNode(F: Node, T: NewNode);
2937 return;
2938 }
2939 }
2940 break;
2941 }
2942 case ISD::BITCAST: {
2943 MVT SrcVT = Node->getOperand(Num: 0).getSimpleValueType();
2944 // Just drop bitcasts between vectors if both are fixed or both are
2945 // scalable.
2946 if ((VT.isScalableVector() && SrcVT.isScalableVector()) ||
2947 (VT.isFixedLengthVector() && SrcVT.isFixedLengthVector())) {
2948 ReplaceUses(F: SDValue(Node, 0), T: Node->getOperand(Num: 0));
2949 CurDAG->RemoveDeadNode(N: Node);
2950 return;
2951 }
2952 if (Subtarget->hasStdExtP()) {
2953 bool Is32BitCast =
2954 (VT == MVT::i32 && (SrcVT == MVT::v4i8 || SrcVT == MVT::v2i16)) ||
2955 (SrcVT == MVT::i32 && (VT == MVT::v4i8 || VT == MVT::v2i16));
2956 bool Is64BitCast =
2957 (VT == MVT::i64 && (SrcVT == MVT::v8i8 || SrcVT == MVT::v4i16 ||
2958 SrcVT == MVT::v2i32)) ||
2959 (SrcVT == MVT::i64 &&
2960 (VT == MVT::v8i8 || VT == MVT::v4i16 || VT == MVT::v2i32));
2961 if (Is32BitCast || Is64BitCast) {
2962 ReplaceUses(F: SDValue(Node, 0), T: Node->getOperand(Num: 0));
2963 CurDAG->RemoveDeadNode(N: Node);
2964 return;
2965 }
2966 }
2967 break;
2968 }
2969 case ISD::SPLAT_VECTOR: {
2970 if (!Subtarget->hasStdExtP())
2971 break;
2972 if (auto *ConstNode = dyn_cast<ConstantSDNode>(Val: Node->getOperand(Num: 0))) {
2973 bool IsDoubleWide = Subtarget->isPExtPackedDoubleType(VT);
2974
2975 if (ConstNode->isZero()) {
2976 MCPhysReg X0Reg = IsDoubleWide ? RISCV::X0_Pair : RISCV::X0;
2977 SDValue New =
2978 CurDAG->getCopyFromReg(Chain: CurDAG->getEntryNode(), dl: DL, Reg: X0Reg, VT);
2979 ReplaceNode(F: Node, T: New.getNode());
2980 return;
2981 }
2982
2983 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
2984 APInt Val = ConstNode->getAPIntValue().trunc(width: EltSize);
2985
2986 // Use LI for all ones since it can be compressed to c.li.
2987 if (Val.isAllOnes() && !IsDoubleWide) {
2988 SDNode *NewNode = CurDAG->getMachineNode(
2989 Opcode: RISCV::ADDI, dl: DL, VT, Op1: CurDAG->getRegister(Reg: RISCV::X0, VT),
2990 Op2: CurDAG->getAllOnesConstant(DL, VT: XLenVT, /*IsTarget=*/true));
2991 ReplaceNode(F: Node, T: NewNode);
2992 return;
2993 }
2994
2995 // Find the smallest splat.
2996 if (Val.getBitWidth() > 16 && Val.isSplat(SplatSizeInBits: 16))
2997 Val = Val.trunc(width: 16);
2998 if (Val.getBitWidth() > 8 && Val.isSplat(SplatSizeInBits: 8))
2999 Val = Val.trunc(width: 8);
3000
3001 EltSize = Val.getBitWidth();
3002 int64_t Imm = Val.getSExtValue();
3003
3004 unsigned Opc = 0;
3005 if (EltSize == 8) {
3006 Opc = IsDoubleWide ? RISCV::PLI_DB : RISCV::PLI_B;
3007 } else if (EltSize == 16 && isInt<10>(x: Imm)) {
3008 Opc = IsDoubleWide ? RISCV::PLI_DH : RISCV::PLI_H;
3009 } else if (!IsDoubleWide && EltSize == 32 && isInt<10>(x: Imm)) {
3010 Opc = RISCV::PLI_W;
3011 } else if (EltSize == 16 && isShiftedInt<10, 6>(x: Imm)) {
3012 Opc = IsDoubleWide ? RISCV::PLUI_DH : RISCV::PLUI_H;
3013 Imm = Imm >> 6;
3014 } else if (!IsDoubleWide && EltSize == 32 && isShiftedInt<10, 22>(x: Imm)) {
3015 Opc = RISCV::PLUI_W;
3016 Imm = Imm >> 22;
3017 }
3018
3019 if (Opc) {
3020 SDNode *NewNode = CurDAG->getMachineNode(
3021 Opcode: Opc, dl: DL, VT, Op1: CurDAG->getSignedTargetConstant(Val: Imm, DL, VT: XLenVT));
3022 ReplaceNode(F: Node, T: NewNode);
3023 return;
3024 }
3025 }
3026
3027 break;
3028 }
3029 case ISD::SCALAR_TO_VECTOR:
3030 if (Subtarget->hasStdExtP()) {
3031 MVT SrcVT = Node->getOperand(Num: 0).getSimpleValueType();
3032 if ((VT == MVT::v2i32 && SrcVT == MVT::i64) ||
3033 (VT == MVT::v4i8 && SrcVT == MVT::i32)) {
3034 ReplaceUses(F: SDValue(Node, 0), T: Node->getOperand(Num: 0));
3035 CurDAG->RemoveDeadNode(N: Node);
3036 return;
3037 }
3038 }
3039 break;
3040 case ISD::INSERT_SUBVECTOR:
3041 case RISCVISD::TUPLE_INSERT: {
3042 SDValue V = Node->getOperand(Num: 0);
3043 SDValue SubV = Node->getOperand(Num: 1);
3044 SDLoc DL(SubV);
3045 auto Idx = Node->getConstantOperandVal(Num: 2);
3046 MVT SubVecVT = SubV.getSimpleValueType();
3047
3048 const RISCVTargetLowering &TLI = *Subtarget->getTargetLowering();
3049 MVT SubVecContainerVT = SubVecVT;
3050 // Establish the correct scalable-vector types for any fixed-length type.
3051 if (SubVecVT.isFixedLengthVector()) {
3052 SubVecContainerVT = TLI.getContainerForFixedLengthVector(VT: SubVecVT);
3053 TypeSize VecRegSize = TypeSize::getScalable(MinimumSize: RISCV::RVVBitsPerBlock);
3054 [[maybe_unused]] bool ExactlyVecRegSized =
3055 Subtarget->expandVScale(X: SubVecVT.getSizeInBits())
3056 .isKnownMultipleOf(RHS: Subtarget->expandVScale(X: VecRegSize));
3057 assert(isPowerOf2_64(Subtarget->expandVScale(SubVecVT.getSizeInBits())
3058 .getKnownMinValue()));
3059 assert(Idx == 0 && (ExactlyVecRegSized || V.isUndef()));
3060 }
3061 MVT ContainerVT = VT;
3062 if (VT.isFixedLengthVector())
3063 ContainerVT = TLI.getContainerForFixedLengthVector(VT);
3064
3065 const auto *TRI = Subtarget->getRegisterInfo();
3066 unsigned SubRegIdx;
3067 std::tie(args&: SubRegIdx, args&: Idx) =
3068 RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(
3069 VecVT: ContainerVT, SubVecVT: SubVecContainerVT, InsertExtractIdx: Idx, TRI);
3070
3071 // If the Idx hasn't been completely eliminated then this is a subvector
3072 // insert which doesn't naturally align to a vector register. These must
3073 // be handled using instructions to manipulate the vector registers.
3074 if (Idx != 0)
3075 break;
3076
3077 RISCVVType::VLMUL SubVecLMUL =
3078 RISCVTargetLowering::getLMUL(VT: SubVecContainerVT);
3079 [[maybe_unused]] bool IsSubVecPartReg =
3080 SubVecLMUL == RISCVVType::VLMUL::LMUL_F2 ||
3081 SubVecLMUL == RISCVVType::VLMUL::LMUL_F4 ||
3082 SubVecLMUL == RISCVVType::VLMUL::LMUL_F8;
3083 assert((V.getValueType().isRISCVVectorTuple() || !IsSubVecPartReg ||
3084 V.isUndef()) &&
3085 "Expecting lowering to have created legal INSERT_SUBVECTORs when "
3086 "the subvector is smaller than a full-sized register");
3087
3088 // If we haven't set a SubRegIdx, then we must be going between
3089 // equally-sized LMUL groups (e.g. VR -> VR). This can be done as a copy.
3090 if (SubRegIdx == RISCV::NoSubRegister) {
3091 unsigned InRegClassID =
3092 RISCVTargetLowering::getRegClassIDForVecVT(VT: ContainerVT);
3093 assert(RISCVTargetLowering::getRegClassIDForVecVT(SubVecContainerVT) ==
3094 InRegClassID &&
3095 "Unexpected subvector extraction");
3096 SDValue RC = CurDAG->getTargetConstant(Val: InRegClassID, DL, VT: XLenVT);
3097 SDNode *NewNode = CurDAG->getMachineNode(Opcode: TargetOpcode::COPY_TO_REGCLASS,
3098 dl: DL, VT, Op1: SubV, Op2: RC);
3099 ReplaceNode(F: Node, T: NewNode);
3100 return;
3101 }
3102
3103 SDValue Insert = CurDAG->getTargetInsertSubreg(SRIdx: SubRegIdx, DL, VT, Operand: V, Subreg: SubV);
3104 ReplaceNode(F: Node, T: Insert.getNode());
3105 return;
3106 }
3107 case ISD::EXTRACT_SUBVECTOR:
3108 case RISCVISD::TUPLE_EXTRACT: {
3109 if (Subtarget->hasStdExtP())
3110 break;
3111
3112 SDValue V = Node->getOperand(Num: 0);
3113 auto Idx = Node->getConstantOperandVal(Num: 1);
3114 MVT InVT = V.getSimpleValueType();
3115
3116 SDLoc DL(V);
3117
3118 const RISCVTargetLowering &TLI = *Subtarget->getTargetLowering();
3119 MVT SubVecContainerVT = VT;
3120 // Establish the correct scalable-vector types for any fixed-length type.
3121 if (VT.isFixedLengthVector()) {
3122 assert(Idx == 0);
3123 SubVecContainerVT = TLI.getContainerForFixedLengthVector(VT);
3124 }
3125 if (InVT.isFixedLengthVector())
3126 InVT = TLI.getContainerForFixedLengthVector(VT: InVT);
3127
3128 const auto *TRI = Subtarget->getRegisterInfo();
3129 unsigned SubRegIdx;
3130 std::tie(args&: SubRegIdx, args&: Idx) =
3131 RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(
3132 VecVT: InVT, SubVecVT: SubVecContainerVT, InsertExtractIdx: Idx, TRI);
3133
3134 // If the Idx hasn't been completely eliminated then this is a subvector
3135 // extract which doesn't naturally align to a vector register. These must
3136 // be handled using instructions to manipulate the vector registers.
3137 if (Idx != 0)
3138 break;
3139
3140 // If we haven't set a SubRegIdx, then we must be going between
3141 // equally-sized LMUL types (e.g. VR -> VR). This can be done as a copy.
3142 if (SubRegIdx == RISCV::NoSubRegister) {
3143 unsigned InRegClassID = RISCVTargetLowering::getRegClassIDForVecVT(VT: InVT);
3144 assert(RISCVTargetLowering::getRegClassIDForVecVT(SubVecContainerVT) ==
3145 InRegClassID &&
3146 "Unexpected subvector extraction");
3147 SDValue RC = CurDAG->getTargetConstant(Val: InRegClassID, DL, VT: XLenVT);
3148 SDNode *NewNode =
3149 CurDAG->getMachineNode(Opcode: TargetOpcode::COPY_TO_REGCLASS, dl: DL, VT, Op1: V, Op2: RC);
3150 ReplaceNode(F: Node, T: NewNode);
3151 return;
3152 }
3153
3154 SDValue Extract = CurDAG->getTargetExtractSubreg(SRIdx: SubRegIdx, DL, VT, Operand: V);
3155 ReplaceNode(F: Node, T: Extract.getNode());
3156 return;
3157 }
3158 case RISCVISD::VMV_S_X_VL:
3159 case RISCVISD::VFMV_S_F_VL:
3160 case RISCVISD::VMV_V_X_VL:
3161 case RISCVISD::VFMV_V_F_VL: {
3162 // Try to match splat of a scalar load to a strided load with stride of x0.
3163 bool IsScalarMove = Node->getOpcode() == RISCVISD::VMV_S_X_VL ||
3164 Node->getOpcode() == RISCVISD::VFMV_S_F_VL;
3165 if (!Node->getOperand(Num: 0).isUndef())
3166 break;
3167 SDValue Src = Node->getOperand(Num: 1);
3168 auto *Ld = dyn_cast<LoadSDNode>(Val&: Src);
3169 // Can't fold load update node because the second
3170 // output is used so that load update node can't be removed.
3171 if (!Ld || Ld->isIndexed())
3172 break;
3173 EVT MemVT = Ld->getMemoryVT();
3174 // The memory VT should be the same size as the element type.
3175 if (MemVT.getStoreSize() != VT.getVectorElementType().getStoreSize())
3176 break;
3177 if (!IsProfitableToFold(N: Src, U: Node, Root: Node) ||
3178 !IsLegalToFold(N: Src, U: Node, Root: Node, OptLevel: TM.getOptLevel()))
3179 break;
3180
3181 SDValue VL;
3182 if (IsScalarMove) {
3183 // We could deal with more VL if we update the VSETVLI insert pass to
3184 // avoid introducing more VSETVLI.
3185 if (!isOneConstant(V: Node->getOperand(Num: 2)))
3186 break;
3187 selectVLOp(N: Node->getOperand(Num: 2), VL);
3188 } else
3189 selectVLOp(N: Node->getOperand(Num: 2), VL);
3190
3191 unsigned Log2SEW = Log2_32(Value: VT.getScalarSizeInBits());
3192 SDValue SEW = CurDAG->getTargetConstant(Val: Log2SEW, DL, VT: XLenVT);
3193
3194 // If VL=1, then we don't need to do a strided load and can just do a
3195 // regular load.
3196 bool IsStrided = !isOneConstant(V: VL);
3197
3198 // Only do a strided load if we have optimized zero-stride vector load.
3199 if (IsStrided && !Subtarget->hasOptimizedZeroStrideLoad())
3200 break;
3201
3202 SmallVector<SDValue> Operands = {
3203 SDValue(CurDAG->getMachineNode(Opcode: TargetOpcode::IMPLICIT_DEF, dl: DL, VT), 0),
3204 Ld->getBasePtr()};
3205 if (IsStrided)
3206 Operands.push_back(Elt: CurDAG->getRegister(Reg: RISCV::X0, VT: XLenVT));
3207 uint64_t Policy = RISCVVType::MASK_AGNOSTIC | RISCVVType::TAIL_AGNOSTIC;
3208 SDValue PolicyOp = CurDAG->getTargetConstant(Val: Policy, DL, VT: XLenVT);
3209 Operands.append(IL: {VL, SEW, PolicyOp, Ld->getChain()});
3210
3211 RISCVVType::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
3212 const RISCV::VLEPseudo *P = RISCV::getVLEPseudo(
3213 /*IsMasked*/ Masked: false, Strided: IsStrided, /*FF*/ false,
3214 Log2SEW, LMUL: static_cast<unsigned>(LMUL));
3215 MachineSDNode *Load =
3216 CurDAG->getMachineNode(Opcode: P->Pseudo, dl: DL, ResultTys: {VT, MVT::Other}, Ops: Operands);
3217 // Update the chain.
3218 ReplaceUses(F: Src.getValue(R: 1), T: SDValue(Load, 1));
3219 // Record the mem-refs
3220 CurDAG->setNodeMemRefs(N: Load, NewMemRefs: {Ld->getMemOperand()});
3221 // Replace the splat with the vlse.
3222 ReplaceNode(F: Node, T: Load);
3223 return;
3224 }
3225 case RISCVISD::LPAD_CALL:
3226 case RISCVISD::LPAD_CALL_INDIRECT: {
3227 bool IsIndirect = Opcode == RISCVISD::LPAD_CALL_INDIRECT;
3228 unsigned PseudoOpc = IsIndirect ? RISCV::PseudoCALLIndirectLpadAlign
3229 : RISCV::PseudoCALLLpadAlign;
3230
3231 uint32_t LpadLabel = 0;
3232 if (PreferredLandingPadLabel.getNumOccurrences() > 0) {
3233 if (!isUInt<20>(x: PreferredLandingPadLabel))
3234 report_fatal_error(reason: "riscv-landing-pad-label=<val>, <val> needs to fit "
3235 "in unsigned 20-bits");
3236 LpadLabel = PreferredLandingPadLabel;
3237 }
3238
3239 SmallVector<SDValue, 4> Ops;
3240 Ops.push_back(Elt: Node->getOperand(Num: 1));
3241 Ops.push_back(Elt: CurDAG->getTargetConstant(Val: LpadLabel, DL, VT: XLenVT));
3242 Ops.push_back(Elt: Node->getOperand(Num: 0));
3243 if (Node->getGluedNode())
3244 Ops.push_back(Elt: Node->getOperand(Num: Node->getNumOperands() - 1));
3245
3246 ReplaceNode(F: Node,
3247 T: CurDAG->getMachineNode(Opcode: PseudoOpc, dl: DL, VTs: Node->getVTList(), Ops));
3248 return;
3249 }
3250 case ISD::PREFETCH:
3251 // MIPS's prefetch instruction already encodes the hint within the
3252 // instruction itself, so no extra NTL hint is needed.
3253 if (Subtarget->hasVendorXMIPSCBOP())
3254 break;
3255
3256 unsigned Locality = Node->getConstantOperandVal(Num: 3);
3257 if (Locality > 2)
3258 break;
3259
3260 auto *LoadStoreMem = cast<MemSDNode>(Val: Node);
3261 MachineMemOperand *MMO = LoadStoreMem->getMemOperand();
3262 MMO->setFlags(MachineMemOperand::MONonTemporal);
3263
3264 int NontemporalLevel = 0;
3265 switch (Locality) {
3266 case 0:
3267 NontemporalLevel = 3; // NTL.ALL
3268 break;
3269 case 1:
3270 NontemporalLevel = 1; // NTL.PALL
3271 break;
3272 case 2:
3273 NontemporalLevel = 0; // NTL.P1
3274 break;
3275 default:
3276 llvm_unreachable("unexpected locality value.");
3277 }
3278
3279 if (NontemporalLevel & 0b1)
3280 MMO->setFlags(MONontemporalBit0);
3281 if (NontemporalLevel & 0b10)
3282 MMO->setFlags(MONontemporalBit1);
3283 break;
3284 }
3285
3286 // Select the default instruction.
3287 SelectCode(N: Node);
3288}
3289
3290bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand(
3291 const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
3292 std::vector<SDValue> &OutOps) {
3293 // Always produce a register and immediate operand, as expected by
3294 // RISCVAsmPrinter::PrintAsmMemoryOperand.
3295 switch (ConstraintID) {
3296 case InlineAsm::ConstraintCode::o:
3297 case InlineAsm::ConstraintCode::m: {
3298 SDValue Op0, Op1;
3299 [[maybe_unused]] bool Found = SelectAddrRegImm(Addr: Op, Base&: Op0, Offset&: Op1);
3300 assert(Found && "SelectAddrRegImm should always succeed");
3301 OutOps.push_back(x: Op0);
3302 OutOps.push_back(x: Op1);
3303 return false;
3304 }
3305 case InlineAsm::ConstraintCode::A:
3306 OutOps.push_back(x: Op);
3307 OutOps.push_back(
3308 x: CurDAG->getTargetConstant(Val: 0, DL: SDLoc(Op), VT: Subtarget->getXLenVT()));
3309 return false;
3310 default:
3311 report_fatal_error(reason: "Unexpected asm memory constraint " +
3312 InlineAsm::getMemConstraintName(C: ConstraintID));
3313 }
3314
3315 return true;
3316}
3317
3318bool RISCVDAGToDAGISel::SelectAddrFrameIndex(SDValue Addr, SDValue &Base,
3319 SDValue &Offset) {
3320 if (auto *FIN = dyn_cast<FrameIndexSDNode>(Val&: Addr)) {
3321 Base = CurDAG->getTargetFrameIndex(FI: FIN->getIndex(), VT: Subtarget->getXLenVT());
3322 Offset = CurDAG->getTargetConstant(Val: 0, DL: SDLoc(Addr), VT: Subtarget->getXLenVT());
3323 return true;
3324 }
3325
3326 return false;
3327}
3328
3329// Fold constant addresses.
3330static bool selectConstantAddr(SelectionDAG *CurDAG, const SDLoc &DL,
3331 const MVT VT, const RISCVSubtarget *Subtarget,
3332 SDValue Addr, SDValue &Base, SDValue &Offset,
3333 bool IsPrefetch = false) {
3334 if (!isa<ConstantSDNode>(Val: Addr))
3335 return false;
3336
3337 int64_t CVal = cast<ConstantSDNode>(Val&: Addr)->getSExtValue();
3338
3339 // If the constant is a simm12, we can fold the whole constant and use X0 as
3340 // the base. If the constant can be materialized with LUI+simm12, use LUI as
3341 // the base. We can't use generateInstSeq because it favors LUI+ADDIW.
3342 int64_t Lo12 = SignExtend64<12>(x: CVal);
3343 int64_t Hi = (uint64_t)CVal - (uint64_t)Lo12;
3344 if (!Subtarget->is64Bit() || isInt<32>(x: Hi)) {
3345 if (IsPrefetch && (Lo12 & 0b11111) != 0)
3346 return false;
3347 if (Hi) {
3348 int64_t Hi20 = (Hi >> 12) & 0xfffff;
3349 Base = SDValue(
3350 CurDAG->getMachineNode(Opcode: RISCV::LUI, dl: DL, VT,
3351 Op1: CurDAG->getTargetConstant(Val: Hi20, DL, VT)),
3352 0);
3353 } else {
3354 Base = CurDAG->getRegister(Reg: RISCV::X0, VT);
3355 }
3356 Offset = CurDAG->getSignedTargetConstant(Val: Lo12, DL, VT);
3357 return true;
3358 }
3359
3360 // Ask how constant materialization would handle this constant.
3361 RISCVMatInt::InstSeq Seq = RISCVMatInt::generateInstSeq(Val: CVal, STI: *Subtarget);
3362
3363 // If the last instruction would be an ADDI, we can fold its immediate and
3364 // emit the rest of the sequence as the base.
3365 if (Seq.back().getOpcode() != RISCV::ADDI)
3366 return false;
3367 Lo12 = Seq.back().getImm();
3368 if (IsPrefetch && (Lo12 & 0b11111) != 0)
3369 return false;
3370
3371 // Drop the last instruction.
3372 Seq.pop_back();
3373 assert(!Seq.empty() && "Expected more instructions in sequence");
3374
3375 Base = selectImmSeq(CurDAG, DL, VT, Seq);
3376 Offset = CurDAG->getSignedTargetConstant(Val: Lo12, DL, VT);
3377 return true;
3378}
3379
3380// Is this ADD instruction only used as the base pointer of scalar loads and
3381// stores?
3382static bool isWorthFoldingAdd(SDValue Add) {
3383 for (auto *User : Add->users()) {
3384 if (User->getOpcode() != ISD::LOAD && User->getOpcode() != ISD::STORE &&
3385 User->getOpcode() != RISCVISD::LD_RV32 &&
3386 User->getOpcode() != RISCVISD::SD_RV32 &&
3387 User->getOpcode() != ISD::ATOMIC_LOAD &&
3388 User->getOpcode() != ISD::ATOMIC_STORE)
3389 return false;
3390 EVT VT = cast<MemSDNode>(Val: User)->getMemoryVT();
3391 if (!VT.isScalarInteger() && VT != MVT::f16 && VT != MVT::f32 &&
3392 VT != MVT::f64)
3393 return false;
3394 // Don't allow stores of the value. It must be used as the address.
3395 if (User->getOpcode() == ISD::STORE &&
3396 cast<StoreSDNode>(Val: User)->getValue() == Add)
3397 return false;
3398 if (User->getOpcode() == ISD::ATOMIC_STORE &&
3399 cast<AtomicSDNode>(Val: User)->getVal() == Add)
3400 return false;
3401 if (User->getOpcode() == RISCVISD::SD_RV32 &&
3402 (User->getOperand(Num: 0) == Add || User->getOperand(Num: 1) == Add))
3403 return false;
3404 if (isStrongerThanMonotonic(AO: cast<MemSDNode>(Val: User)->getSuccessOrdering()))
3405 return false;
3406 }
3407
3408 return true;
3409}
3410
3411bool isRegImmLoadOrStore(SDNode *User, SDValue Add) {
3412 switch (User->getOpcode()) {
3413 default:
3414 return false;
3415 case ISD::LOAD:
3416 case RISCVISD::LD_RV32:
3417 case ISD::ATOMIC_LOAD:
3418 break;
3419 case ISD::STORE:
3420 // Don't allow stores of Add. It must only be used as the address.
3421 if (cast<StoreSDNode>(Val: User)->getValue() == Add)
3422 return false;
3423 break;
3424 case RISCVISD::SD_RV32:
3425 // Don't allow stores of Add. It must only be used as the address.
3426 if (User->getOperand(Num: 0) == Add || User->getOperand(Num: 1) == Add)
3427 return false;
3428 break;
3429 case ISD::ATOMIC_STORE:
3430 // Don't allow stores of Add. It must only be used as the address.
3431 if (cast<AtomicSDNode>(Val: User)->getVal() == Add)
3432 return false;
3433 break;
3434 }
3435
3436 return true;
3437}
3438
3439// To prevent SelectAddrRegImm from folding offsets that conflict with the
3440// fusion of PseudoMovAddr, check if the offset of every use of a given address
3441// is within the alignment.
3442bool RISCVDAGToDAGISel::areOffsetsWithinAlignment(SDValue Addr,
3443 Align Alignment) {
3444 assert(Addr->getOpcode() == RISCVISD::ADD_LO);
3445 for (auto *User : Addr->users()) {
3446 // If the user is a load or store, then the offset is 0 which is always
3447 // within alignment.
3448 if (isRegImmLoadOrStore(User, Add: Addr))
3449 continue;
3450
3451 if (CurDAG->isBaseWithConstantOffset(Op: SDValue(User, 0))) {
3452 int64_t CVal = cast<ConstantSDNode>(Val: User->getOperand(Num: 1))->getSExtValue();
3453 if (!isInt<12>(x: CVal) || Alignment <= CVal)
3454 return false;
3455
3456 // Make sure all uses are foldable load/stores.
3457 for (auto *AddUser : User->users())
3458 if (!isRegImmLoadOrStore(User: AddUser, Add: SDValue(User, 0)))
3459 return false;
3460
3461 continue;
3462 }
3463
3464 return false;
3465 }
3466
3467 return true;
3468}
3469
3470bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
3471 SDValue &Offset) {
3472 if (SelectAddrFrameIndex(Addr, Base, Offset))
3473 return true;
3474
3475 SDLoc DL(Addr);
3476 MVT VT = Addr.getSimpleValueType();
3477
3478 if (Addr.getOpcode() == RISCVISD::ADD_LO) {
3479 bool CanFold = true;
3480 // Unconditionally fold if operand 1 is not a global address (e.g.
3481 // externsymbol)
3482 if (auto *GA = dyn_cast<GlobalAddressSDNode>(Val: Addr.getOperand(i: 1))) {
3483 const DataLayout &DL = CurDAG->getDataLayout();
3484 Align Alignment = commonAlignment(
3485 A: GA->getGlobal()->getPointerAlignment(DL), Offset: GA->getOffset());
3486 if (!areOffsetsWithinAlignment(Addr, Alignment))
3487 CanFold = false;
3488 }
3489 if (CanFold) {
3490 Base = Addr.getOperand(i: 0);
3491 Offset = Addr.getOperand(i: 1);
3492 return true;
3493 }
3494 }
3495
3496 if (CurDAG->isBaseWithConstantOffset(Op: Addr)) {
3497 int64_t CVal = cast<ConstantSDNode>(Val: Addr.getOperand(i: 1))->getSExtValue();
3498 if (isInt<12>(x: CVal)) {
3499 Base = Addr.getOperand(i: 0);
3500 if (Base.getOpcode() == RISCVISD::ADD_LO) {
3501 SDValue LoOperand = Base.getOperand(i: 1);
3502 if (auto *GA = dyn_cast<GlobalAddressSDNode>(Val&: LoOperand)) {
3503 // If the Lo in (ADD_LO hi, lo) is a global variable's address
3504 // (its low part, really), then we can rely on the alignment of that
3505 // variable to provide a margin of safety before low part can overflow
3506 // the 12 bits of the load/store offset. Check if CVal falls within
3507 // that margin; if so (low part + CVal) can't overflow.
3508 const DataLayout &DL = CurDAG->getDataLayout();
3509 Align Alignment = commonAlignment(
3510 A: GA->getGlobal()->getPointerAlignment(DL), Offset: GA->getOffset());
3511 if ((CVal == 0 || Alignment > CVal) &&
3512 areOffsetsWithinAlignment(Addr: Base, Alignment)) {
3513 int64_t CombinedOffset = CVal + GA->getOffset();
3514 Base = Base.getOperand(i: 0);
3515 Offset = CurDAG->getTargetGlobalAddress(
3516 GV: GA->getGlobal(), DL: SDLoc(LoOperand), VT: LoOperand.getValueType(),
3517 offset: CombinedOffset, TargetFlags: GA->getTargetFlags());
3518 return true;
3519 }
3520 }
3521 }
3522
3523 if (auto *FIN = dyn_cast<FrameIndexSDNode>(Val&: Base))
3524 Base = CurDAG->getTargetFrameIndex(FI: FIN->getIndex(), VT);
3525 Offset = CurDAG->getSignedTargetConstant(Val: CVal, DL, VT);
3526 return true;
3527 }
3528 }
3529
3530 // Handle ADD with large immediates.
3531 if (Addr.getOpcode() == ISD::ADD && isa<ConstantSDNode>(Val: Addr.getOperand(i: 1))) {
3532 int64_t CVal = cast<ConstantSDNode>(Val: Addr.getOperand(i: 1))->getSExtValue();
3533 assert(!isInt<12>(CVal) && "simm12 not already handled?");
3534
3535 // Handle immediates in the range [-4096,-2049] or [2048, 4094]. We can use
3536 // an ADDI for part of the offset and fold the rest into the load/store.
3537 // This mirrors the AddiPair PatFrag in RISCVInstrInfo.td.
3538 if (CVal >= -4096 && CVal <= 4094) {
3539 int64_t Adj = CVal < 0 ? -2048 : 2047;
3540 Base = SDValue(
3541 CurDAG->getMachineNode(Opcode: RISCV::ADDI, dl: DL, VT, Op1: Addr.getOperand(i: 0),
3542 Op2: CurDAG->getSignedTargetConstant(Val: Adj, DL, VT)),
3543 0);
3544 Offset = CurDAG->getSignedTargetConstant(Val: CVal - Adj, DL, VT);
3545 return true;
3546 }
3547
3548 // For larger immediates, we might be able to save one instruction from
3549 // constant materialization by folding the Lo12 bits of the immediate into
3550 // the address. We should only do this if the ADD is only used by loads and
3551 // stores that can fold the lo12 bits. Otherwise, the ADD will get iseled
3552 // separately with the full materialized immediate creating extra
3553 // instructions.
3554 if (isWorthFoldingAdd(Add: Addr) &&
3555 selectConstantAddr(CurDAG, DL, VT, Subtarget, Addr: Addr.getOperand(i: 1), Base,
3556 Offset, /*IsPrefetch=*/false)) {
3557 // Insert an ADD instruction with the materialized Hi52 bits.
3558 Base = SDValue(
3559 CurDAG->getMachineNode(Opcode: RISCV::ADD, dl: DL, VT, Op1: Addr.getOperand(i: 0), Op2: Base),
3560 0);
3561 return true;
3562 }
3563 }
3564
3565 if (selectConstantAddr(CurDAG, DL, VT, Subtarget, Addr, Base, Offset,
3566 /*IsPrefetch=*/false))
3567 return true;
3568
3569 Base = Addr;
3570 Offset = CurDAG->getTargetConstant(Val: 0, DL, VT);
3571 return true;
3572}
3573
3574/// Similar to SelectAddrRegImm, except that the offset is a 26-bit signed
3575/// immediate. This is used by the Qualcomm Xqcilo large offset load/store
3576/// instructions (qc.e.lw/qc.e.sw), whose offset field is 26 bits wide.
3577/// Only matches offsets that do not fit a 12-bit signed immediate, so that
3578/// offsets in the simm12 range keep using the shorter (and possibly
3579/// compressible) standard load/store instructions.
3580bool RISCVDAGToDAGISel::SelectAddrRegImm26(SDValue Addr, SDValue &Base,
3581 SDValue &Offset) {
3582
3583 if (SelectAddrFrameIndex(Addr, Base, Offset))
3584 return true;
3585
3586 SDLoc DL(Addr);
3587 MVT VT = Addr.getSimpleValueType();
3588
3589 if (CurDAG->isBaseWithConstantOffset(Op: Addr)) {
3590 int64_t CVal = cast<ConstantSDNode>(Val: Addr.getOperand(i: 1))->getSExtValue();
3591 // Fold a 26-bit (but not 12-bit) signed offset directly into the
3592 // load/store.
3593 if (isInt<26>(x: CVal) && !isInt<12>(x: CVal)) {
3594 Base = Addr.getOperand(i: 0);
3595 if (auto *FIN = dyn_cast<FrameIndexSDNode>(Val&: Base))
3596 Base = CurDAG->getTargetFrameIndex(FI: FIN->getIndex(), VT);
3597 Offset = CurDAG->getSignedTargetConstant(Val: CVal, DL, VT);
3598 return true;
3599 }
3600 }
3601
3602 // The offset is just outside the 26-bit range. Split off a small (simm12)
3603 // adjustment with a plain ADDI and fold the remaining 26-bit offset into the
3604 // load/store. A plain ADDI is used (rather than the wide
3605 // qc.e.addi/qc.e.addai) because the adjustment fits simm12: this keeps it a
3606 // short, compressible (c.addi) instruction and is available without Xqcilia.
3607 //
3608 // Skip the split if the address is used other than as a foldable load/store
3609 // base. `isWorthFoldingAdd()` returns true when every user of the add node is
3610 // a scalar load/store using it as an address operand. If it return false, it
3611 // means that some use consumes the add result as a value (e.g. it feeds
3612 // another add, is a stored value, is used in arithmetic) and that use forces
3613 // the add to be materialized into a register.
3614 if (Addr.getOpcode() == ISD::ADD && isa<ConstantSDNode>(Val: Addr.getOperand(i: 1)) &&
3615 isWorthFoldingAdd(Add: Addr)) {
3616 int64_t CVal = cast<ConstantSDNode>(Val: Addr.getOperand(i: 1))->getSExtValue();
3617 if (!isInt<26>(x: CVal)) {
3618 // check if lw in lui + add + lw combination can be compressed.
3619 // The check here purely based on the immediate value and hopes that
3620 // register allocator would assign a register from a GPRC set so that the
3621 // instruction can get compressed.
3622 bool IsLwCompressable = isShiftedUInt<5, 2>(x: CVal & ((1 << 12) - 1));
3623
3624 int64_t Imm26 = CVal < 0 ? minIntN(N: 26) : maxIntN(N: 26);
3625 int64_t Adj = CVal - Imm26;
3626 // If Adj fits within 6-bits, then both combinations will take 8 bytes
3627 // however c.addi + qc.e.lw/sw will take 1 less cycle. Also, if lw is not
3628 // compressable then both combination would take 10 bytes but again
3629 // addi + qc.e.lw/sw will take 1 less cycle.
3630 if (isInt<6>(x: Adj) || (isInt<12>(x: Adj) && !IsLwCompressable)) {
3631 Base = SDValue(CurDAG->getMachineNode(
3632 Opcode: RISCV::ADDI, dl: DL, VT, Op1: Addr.getOperand(i: 0),
3633 Op2: CurDAG->getSignedTargetConstant(Val: Adj, DL, VT)),
3634 0);
3635 Offset = CurDAG->getSignedTargetConstant(Val: Imm26, DL, VT);
3636 return true;
3637 }
3638 }
3639 }
3640
3641 // Don't match: let the standard addressing modes handle it.
3642 return false;
3643}
3644
3645/// Similar to SelectAddrRegImm, except that the offset is restricted to uimm9.
3646bool RISCVDAGToDAGISel::SelectAddrRegImm9(SDValue Addr, SDValue &Base,
3647 SDValue &Offset) {
3648 if (SelectAddrFrameIndex(Addr, Base, Offset))
3649 return true;
3650
3651 SDLoc DL(Addr);
3652 MVT VT = Addr.getSimpleValueType();
3653
3654 if (CurDAG->isBaseWithConstantOffset(Op: Addr)) {
3655 int64_t CVal = cast<ConstantSDNode>(Val: Addr.getOperand(i: 1))->getSExtValue();
3656 if (isUInt<9>(x: CVal)) {
3657 Base = Addr.getOperand(i: 0);
3658
3659 if (auto *FIN = dyn_cast<FrameIndexSDNode>(Val&: Base))
3660 Base = CurDAG->getTargetFrameIndex(FI: FIN->getIndex(), VT);
3661 Offset = CurDAG->getSignedTargetConstant(Val: CVal, DL, VT);
3662 return true;
3663 }
3664 }
3665
3666 Base = Addr;
3667 Offset = CurDAG->getTargetConstant(Val: 0, DL, VT);
3668 return true;
3669}
3670
3671/// Similar to SelectAddrRegImm, except that the least significant 5 bits of
3672/// Offset should be all zeros.
3673bool RISCVDAGToDAGISel::SelectAddrRegImmLsb00000(SDValue Addr, SDValue &Base,
3674 SDValue &Offset) {
3675 if (SelectAddrFrameIndex(Addr, Base, Offset))
3676 return true;
3677
3678 SDLoc DL(Addr);
3679 MVT VT = Addr.getSimpleValueType();
3680
3681 if (CurDAG->isBaseWithConstantOffset(Op: Addr)) {
3682 int64_t CVal = cast<ConstantSDNode>(Val: Addr.getOperand(i: 1))->getSExtValue();
3683 if (isInt<12>(x: CVal)) {
3684 Base = Addr.getOperand(i: 0);
3685
3686 // Early-out if not a valid offset.
3687 if ((CVal & 0b11111) != 0) {
3688 Base = Addr;
3689 Offset = CurDAG->getTargetConstant(Val: 0, DL, VT);
3690 return true;
3691 }
3692
3693 if (auto *FIN = dyn_cast<FrameIndexSDNode>(Val&: Base))
3694 Base = CurDAG->getTargetFrameIndex(FI: FIN->getIndex(), VT);
3695 Offset = CurDAG->getSignedTargetConstant(Val: CVal, DL, VT);
3696 return true;
3697 }
3698 }
3699
3700 // Handle ADD with large immediates.
3701 if (Addr.getOpcode() == ISD::ADD && isa<ConstantSDNode>(Val: Addr.getOperand(i: 1))) {
3702 int64_t CVal = cast<ConstantSDNode>(Val: Addr.getOperand(i: 1))->getSExtValue();
3703 assert(!isInt<12>(CVal) && "simm12 not already handled?");
3704
3705 // Handle immediates in the range [-4096,-2049] or [2017, 4065]. We can save
3706 // one instruction by folding adjustment (-2048 or 2016) into the address.
3707 if ((-2049 >= CVal && CVal >= -4096) || (4065 >= CVal && CVal >= 2017)) {
3708 int64_t Adj = CVal < 0 ? -2048 : 2016;
3709 int64_t AdjustedOffset = CVal - Adj;
3710 Base =
3711 SDValue(CurDAG->getMachineNode(
3712 Opcode: RISCV::ADDI, dl: DL, VT, Op1: Addr.getOperand(i: 0),
3713 Op2: CurDAG->getSignedTargetConstant(Val: AdjustedOffset, DL, VT)),
3714 0);
3715 Offset = CurDAG->getSignedTargetConstant(Val: Adj, DL, VT);
3716 return true;
3717 }
3718
3719 if (selectConstantAddr(CurDAG, DL, VT, Subtarget, Addr: Addr.getOperand(i: 1), Base,
3720 Offset, /*IsPrefetch=*/true)) {
3721 // Insert an ADD instruction with the materialized Hi52 bits.
3722 Base = SDValue(
3723 CurDAG->getMachineNode(Opcode: RISCV::ADD, dl: DL, VT, Op1: Addr.getOperand(i: 0), Op2: Base),
3724 0);
3725 return true;
3726 }
3727 }
3728
3729 if (selectConstantAddr(CurDAG, DL, VT, Subtarget, Addr, Base, Offset,
3730 /*IsPrefetch=*/true))
3731 return true;
3732
3733 Base = Addr;
3734 Offset = CurDAG->getTargetConstant(Val: 0, DL, VT);
3735 return true;
3736}
3737
3738/// Return true if this a load/store that we have a RegRegScale instruction for.
3739static bool isRegRegScaleLoadOrStore(SDNode *User, SDValue Add,
3740 const RISCVSubtarget &Subtarget) {
3741 if (User->getOpcode() != ISD::LOAD && User->getOpcode() != ISD::STORE)
3742 return false;
3743 EVT VT = cast<MemSDNode>(Val: User)->getMemoryVT();
3744 if (!(VT.isScalarInteger() &&
3745 (Subtarget.hasVendorXTHeadMemIdx() || Subtarget.hasVendorXqcisls())) &&
3746 !((VT == MVT::f32 || VT == MVT::f64) &&
3747 Subtarget.hasVendorXTHeadFMemIdx()))
3748 return false;
3749 // Don't allow stores of the value. It must be used as the address.
3750 if (User->getOpcode() == ISD::STORE &&
3751 cast<StoreSDNode>(Val: User)->getValue() == Add)
3752 return false;
3753
3754 return true;
3755}
3756
3757/// Is it profitable to fold this Add into RegRegScale load/store. If \p
3758/// Shift is non-null, then we have matched a shl+add. We allow reassociating
3759/// (add (add (shl A C2) B) C1) -> (add (add B C1) (shl A C2)) if there is a
3760/// single addi and we don't have a SHXADD instruction we could use.
3761/// FIXME: May still need to check how many and what kind of users the SHL has.
3762static bool isWorthFoldingIntoRegRegScale(const RISCVSubtarget &Subtarget,
3763 SDValue Add,
3764 SDValue Shift = SDValue()) {
3765 bool FoundADDI = false;
3766 for (auto *User : Add->users()) {
3767 if (isRegRegScaleLoadOrStore(User, Add, Subtarget))
3768 continue;
3769
3770 // Allow a single ADDI that is used by loads/stores if we matched a shift.
3771 if (!Shift || FoundADDI || User->getOpcode() != ISD::ADD ||
3772 !isa<ConstantSDNode>(Val: User->getOperand(Num: 1)) ||
3773 !isInt<12>(x: cast<ConstantSDNode>(Val: User->getOperand(Num: 1))->getSExtValue()))
3774 return false;
3775
3776 FoundADDI = true;
3777
3778 // If we have a SHXADD instruction, prefer that over reassociating an ADDI.
3779 assert(Shift.getOpcode() == ISD::SHL);
3780 unsigned ShiftAmt = Shift.getConstantOperandVal(i: 1);
3781 if (Subtarget.hasShlAdd(ShAmt: ShiftAmt))
3782 return false;
3783
3784 // All users of the ADDI should be load/store.
3785 for (auto *ADDIUser : User->users())
3786 if (!isRegRegScaleLoadOrStore(User: ADDIUser, Add: SDValue(User, 0), Subtarget))
3787 return false;
3788 }
3789
3790 return true;
3791}
3792
3793bool RISCVDAGToDAGISel::SelectAddrRegRegScale(SDValue Addr,
3794 unsigned MaxShiftAmount,
3795 SDValue &Base, SDValue &Index,
3796 SDValue &Scale) {
3797 if (Addr.getOpcode() != ISD::ADD)
3798 return false;
3799 SDValue LHS = Addr.getOperand(i: 0);
3800 SDValue RHS = Addr.getOperand(i: 1);
3801
3802 EVT VT = Addr.getSimpleValueType();
3803 auto SelectShl = [this, VT, MaxShiftAmount](SDValue N, SDValue &Index,
3804 SDValue &Shift) {
3805 if (N.getOpcode() != ISD::SHL || !isa<ConstantSDNode>(Val: N.getOperand(i: 1)))
3806 return false;
3807
3808 // Only match shifts by a value in range [0, MaxShiftAmount].
3809 unsigned ShiftAmt = N.getConstantOperandVal(i: 1);
3810 if (ShiftAmt > MaxShiftAmount)
3811 return false;
3812
3813 Index = N.getOperand(i: 0);
3814 Shift = CurDAG->getTargetConstant(Val: ShiftAmt, DL: SDLoc(N), VT);
3815 return true;
3816 };
3817
3818 if (auto *C1 = dyn_cast<ConstantSDNode>(Val&: RHS)) {
3819 // (add (add (shl A C2) B) C1) -> (add (add B C1) (shl A C2))
3820 if (LHS.getOpcode() == ISD::ADD &&
3821 !isa<ConstantSDNode>(Val: LHS.getOperand(i: 1)) &&
3822 isInt<12>(x: C1->getSExtValue())) {
3823 if (SelectShl(LHS.getOperand(i: 1), Index, Scale) &&
3824 isWorthFoldingIntoRegRegScale(Subtarget: *Subtarget, Add: LHS, Shift: LHS.getOperand(i: 1))) {
3825 SDValue C1Val = CurDAG->getTargetConstant(Val: *C1->getConstantIntValue(),
3826 DL: SDLoc(Addr), VT);
3827 Base = SDValue(CurDAG->getMachineNode(Opcode: RISCV::ADDI, dl: SDLoc(Addr), VT,
3828 Op1: LHS.getOperand(i: 0), Op2: C1Val),
3829 0);
3830 return true;
3831 }
3832
3833 // Add is commutative so we need to check both operands.
3834 if (SelectShl(LHS.getOperand(i: 0), Index, Scale) &&
3835 isWorthFoldingIntoRegRegScale(Subtarget: *Subtarget, Add: LHS, Shift: LHS.getOperand(i: 0))) {
3836 SDValue C1Val = CurDAG->getTargetConstant(Val: *C1->getConstantIntValue(),
3837 DL: SDLoc(Addr), VT);
3838 Base = SDValue(CurDAG->getMachineNode(Opcode: RISCV::ADDI, dl: SDLoc(Addr), VT,
3839 Op1: LHS.getOperand(i: 1), Op2: C1Val),
3840 0);
3841 return true;
3842 }
3843 }
3844
3845 // Don't match add with constants.
3846 // FIXME: Is this profitable for large constants that have 0s in the lower
3847 // 12 bits that we can materialize with LUI?
3848 return false;
3849 }
3850
3851 // Try to match a shift on the RHS.
3852 if (SelectShl(RHS, Index, Scale)) {
3853 if (!isWorthFoldingIntoRegRegScale(Subtarget: *Subtarget, Add: Addr, Shift: RHS))
3854 return false;
3855 Base = LHS;
3856 return true;
3857 }
3858
3859 // Try to match a shift on the LHS.
3860 if (SelectShl(LHS, Index, Scale)) {
3861 if (!isWorthFoldingIntoRegRegScale(Subtarget: *Subtarget, Add: Addr, Shift: LHS))
3862 return false;
3863 Base = RHS;
3864 return true;
3865 }
3866
3867 if (!isWorthFoldingIntoRegRegScale(Subtarget: *Subtarget, Add: Addr))
3868 return false;
3869
3870 Base = LHS;
3871 Index = RHS;
3872 Scale = CurDAG->getTargetConstant(Val: 0, DL: SDLoc(Addr), VT);
3873 return true;
3874}
3875
3876bool RISCVDAGToDAGISel::SelectAddrRegZextRegScale(SDValue Addr,
3877 unsigned MaxShiftAmount,
3878 unsigned Bits, SDValue &Base,
3879 SDValue &Index,
3880 SDValue &Scale) {
3881 if (!SelectAddrRegRegScale(Addr, MaxShiftAmount, Base, Index, Scale))
3882 return false;
3883
3884 if (Index.getOpcode() == ISD::AND) {
3885 auto *C = dyn_cast<ConstantSDNode>(Val: Index.getOperand(i: 1));
3886 if (C && C->getZExtValue() == maskTrailingOnes<uint64_t>(N: Bits)) {
3887 Index = Index.getOperand(i: 0);
3888 return true;
3889 }
3890 }
3891
3892 return false;
3893}
3894
3895bool RISCVDAGToDAGISel::SelectAddrRegReg(SDValue Addr, SDValue &Base,
3896 SDValue &Offset) {
3897 if (Addr.getOpcode() != ISD::ADD)
3898 return false;
3899
3900 if (isa<ConstantSDNode>(Val: Addr.getOperand(i: 1)))
3901 return false;
3902
3903 Base = Addr.getOperand(i: 0);
3904 Offset = Addr.getOperand(i: 1);
3905 return true;
3906}
3907
3908bool RISCVDAGToDAGISel::selectShiftMask(SDValue N, unsigned ShiftWidth,
3909 SDValue &ShAmt) {
3910 ShAmt = N;
3911
3912 // Peek through zext.
3913 if (ShAmt->getOpcode() == ISD::ZERO_EXTEND)
3914 ShAmt = ShAmt.getOperand(i: 0);
3915
3916 // Shift instructions on RISC-V only read the lower 5 or 6 bits of the shift
3917 // amount. If there is an AND on the shift amount, we can bypass it if it
3918 // doesn't affect any of those bits.
3919 if (ShAmt.getOpcode() == ISD::AND &&
3920 isa<ConstantSDNode>(Val: ShAmt.getOperand(i: 1))) {
3921 const APInt &AndMask = ShAmt.getConstantOperandAPInt(i: 1);
3922
3923 // Since the max shift amount is a power of 2 we can subtract 1 to make a
3924 // mask that covers the bits needed to represent all shift amounts.
3925 assert(isPowerOf2_32(ShiftWidth) && "Unexpected max shift amount!");
3926 APInt ShMask(AndMask.getBitWidth(), ShiftWidth - 1);
3927
3928 if (ShMask.isSubsetOf(RHS: AndMask)) {
3929 ShAmt = ShAmt.getOperand(i: 0);
3930 } else {
3931 // SimplifyDemandedBits may have optimized the mask so try restoring any
3932 // bits that are known zero.
3933 KnownBits Known = CurDAG->computeKnownBits(Op: ShAmt.getOperand(i: 0));
3934 if (!ShMask.isSubsetOf(RHS: AndMask | Known.Zero))
3935 return true;
3936 ShAmt = ShAmt.getOperand(i: 0);
3937 }
3938 }
3939
3940 if (ShAmt.getOpcode() == ISD::ADD &&
3941 isa<ConstantSDNode>(Val: ShAmt.getOperand(i: 1))) {
3942 uint64_t Imm = ShAmt.getConstantOperandVal(i: 1);
3943 // If we are shifting by X+N where N == 0 mod Size, then just shift by X
3944 // to avoid the ADD.
3945 if (Imm != 0 && Imm % ShiftWidth == 0) {
3946 ShAmt = ShAmt.getOperand(i: 0);
3947 return true;
3948 }
3949 } else if (ShAmt.getOpcode() == ISD::SUB &&
3950 isa<ConstantSDNode>(Val: ShAmt.getOperand(i: 0))) {
3951 uint64_t Imm = ShAmt.getConstantOperandVal(i: 0);
3952 // If we are shifting by N-X where N == 0 mod Size, then just shift by -X to
3953 // generate a NEG instead of a SUB of a constant.
3954 if (Imm != 0 && Imm % ShiftWidth == 0) {
3955 SDLoc DL(ShAmt);
3956 EVT VT = ShAmt.getValueType();
3957 SDValue Zero = CurDAG->getRegister(Reg: RISCV::X0, VT);
3958 unsigned NegOpc = VT == MVT::i64 ? RISCV::SUBW : RISCV::SUB;
3959 MachineSDNode *Neg = CurDAG->getMachineNode(Opcode: NegOpc, dl: DL, VT, Op1: Zero,
3960 Op2: ShAmt.getOperand(i: 1));
3961 ShAmt = SDValue(Neg, 0);
3962 return true;
3963 }
3964 // If we are shifting by N-X where N == -1 mod Size, then just shift by ~X
3965 // to generate a NOT instead of a SUB of a constant.
3966 if (Imm % ShiftWidth == ShiftWidth - 1) {
3967 SDLoc DL(ShAmt);
3968 EVT VT = ShAmt.getValueType();
3969 MachineSDNode *Not = CurDAG->getMachineNode(
3970 Opcode: RISCV::XORI, dl: DL, VT, Op1: ShAmt.getOperand(i: 1),
3971 Op2: CurDAG->getAllOnesConstant(DL, VT, /*isTarget=*/IsTarget: true));
3972 ShAmt = SDValue(Not, 0);
3973 return true;
3974 }
3975 }
3976
3977 return true;
3978}
3979
3980/// RISC-V doesn't have general instructions for integer setne/seteq, but we can
3981/// check for equality with 0. This function emits instructions that convert the
3982/// seteq/setne into something that can be compared with 0.
3983/// \p ExpectedCCVal indicates the condition code to attempt to match (e.g.
3984/// ISD::SETNE).
3985bool RISCVDAGToDAGISel::selectSETCC(SDValue N, ISD::CondCode ExpectedCCVal,
3986 SDValue &Val) {
3987 assert(ISD::isIntEqualitySetCC(ExpectedCCVal) &&
3988 "Unexpected condition code!");
3989
3990 // We're looking for a setcc.
3991 if (N->getOpcode() != ISD::SETCC)
3992 return false;
3993
3994 // Must be an equality comparison.
3995 ISD::CondCode CCVal = cast<CondCodeSDNode>(Val: N->getOperand(Num: 2))->get();
3996 if (CCVal != ExpectedCCVal)
3997 return false;
3998
3999 SDValue LHS = N->getOperand(Num: 0);
4000 SDValue RHS = N->getOperand(Num: 1);
4001
4002 if (!LHS.getValueType().isScalarInteger())
4003 return false;
4004
4005 // If the RHS side is 0, we don't need any extra instructions, return the LHS.
4006 if (isNullConstant(V: RHS)) {
4007 Val = LHS;
4008 return true;
4009 }
4010
4011 SDLoc DL(N);
4012
4013 if (auto *C = dyn_cast<ConstantSDNode>(Val&: RHS)) {
4014 int64_t CVal = C->getSExtValue();
4015 // If the RHS is -2048, we can use xori to produce 0 if the LHS is -2048 and
4016 // non-zero otherwise.
4017 if (CVal == -2048) {
4018 Val = SDValue(
4019 CurDAG->getMachineNode(
4020 Opcode: RISCV::XORI, dl: DL, VT: N->getValueType(ResNo: 0), Op1: LHS,
4021 Op2: CurDAG->getSignedTargetConstant(Val: CVal, DL, VT: N->getValueType(ResNo: 0))),
4022 0);
4023 return true;
4024 }
4025 // If the RHS is [-2047,2048], we can use addi/addiw with -RHS to produce 0
4026 // if the LHS is equal to the RHS and non-zero otherwise.
4027 if (isInt<12>(x: CVal) || CVal == 2048) {
4028 unsigned Opc = RISCV::ADDI;
4029 if (LHS.getOpcode() == ISD::SIGN_EXTEND_INREG &&
4030 cast<VTSDNode>(Val: LHS.getOperand(i: 1))->getVT() == MVT::i32) {
4031 Opc = RISCV::ADDIW;
4032 LHS = LHS.getOperand(i: 0);
4033 }
4034
4035 Val = SDValue(CurDAG->getMachineNode(Opcode: Opc, dl: DL, VT: N->getValueType(ResNo: 0), Op1: LHS,
4036 Op2: CurDAG->getSignedTargetConstant(
4037 Val: -CVal, DL, VT: N->getValueType(ResNo: 0))),
4038 0);
4039 return true;
4040 }
4041 if (isPowerOf2_64(Value: CVal) && Subtarget->hasStdExtZbs()) {
4042 Val = SDValue(
4043 CurDAG->getMachineNode(
4044 Opcode: RISCV::BINVI, dl: DL, VT: N->getValueType(ResNo: 0), Op1: LHS,
4045 Op2: CurDAG->getTargetConstant(Val: Log2_64(Value: CVal), DL, VT: N->getValueType(ResNo: 0))),
4046 0);
4047 return true;
4048 }
4049 // Same as the addi case above but for larger immediates (signed 26-bit) use
4050 // the QC_E_ADDI instruction from the Xqcilia extension, if available. Avoid
4051 // anything which can be done with a single lui as it might be compressible.
4052 if (Subtarget->hasVendorXqcilia() && isInt<26>(x: CVal) &&
4053 (CVal & 0xFFF) != 0) {
4054 Val = SDValue(
4055 CurDAG->getMachineNode(
4056 Opcode: RISCV::QC_E_ADDI, dl: DL, VT: N->getValueType(ResNo: 0), Op1: LHS,
4057 Op2: CurDAG->getSignedTargetConstant(Val: -CVal, DL, VT: N->getValueType(ResNo: 0))),
4058 0);
4059 return true;
4060 }
4061 }
4062
4063 // If nothing else we can XOR the LHS and RHS to produce zero if they are
4064 // equal and a non-zero value if they aren't.
4065 Val = SDValue(
4066 CurDAG->getMachineNode(Opcode: RISCV::XOR, dl: DL, VT: N->getValueType(ResNo: 0), Op1: LHS, Op2: RHS), 0);
4067 return true;
4068}
4069
4070bool RISCVDAGToDAGISel::selectSExtBits(SDValue N, unsigned Bits, SDValue &Val) {
4071 if (N.getOpcode() == ISD::SIGN_EXTEND_INREG &&
4072 cast<VTSDNode>(Val: N.getOperand(i: 1))->getVT().getSizeInBits() == Bits) {
4073 Val = N.getOperand(i: 0);
4074 return true;
4075 }
4076
4077 auto UnwrapShlSra = [](SDValue N, unsigned ShiftAmt) {
4078 if (N.getOpcode() != ISD::SRA || !isa<ConstantSDNode>(Val: N.getOperand(i: 1)))
4079 return N;
4080
4081 SDValue N0 = N.getOperand(i: 0);
4082 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(Val: N0.getOperand(i: 1)) &&
4083 N.getConstantOperandVal(i: 1) == ShiftAmt &&
4084 N0.getConstantOperandVal(i: 1) == ShiftAmt)
4085 return N0.getOperand(i: 0);
4086
4087 return N;
4088 };
4089
4090 MVT VT = N.getSimpleValueType();
4091 if (CurDAG->ComputeNumSignBits(Op: N) > (VT.getSizeInBits() - Bits)) {
4092 Val = UnwrapShlSra(N, VT.getSizeInBits() - Bits);
4093 return true;
4094 }
4095
4096 return false;
4097}
4098
4099bool RISCVDAGToDAGISel::selectZExtBits(SDValue N, unsigned Bits, SDValue &Val) {
4100 if (N.getOpcode() == ISD::AND) {
4101 auto *C = dyn_cast<ConstantSDNode>(Val: N.getOperand(i: 1));
4102 if (C && C->getZExtValue() == maskTrailingOnes<uint64_t>(N: Bits)) {
4103 Val = N.getOperand(i: 0);
4104 return true;
4105 }
4106 }
4107 MVT VT = N.getSimpleValueType();
4108 APInt Mask = APInt::getBitsSetFrom(numBits: VT.getSizeInBits(), loBit: Bits);
4109 if (CurDAG->MaskedValueIsZero(Op: N, Mask)) {
4110 Val = N;
4111 return true;
4112 }
4113
4114 return false;
4115}
4116
4117/// Look for various patterns that can be done with a SHL that can be folded
4118/// into a SHXADD. \p ShAmt contains 1, 2, or 3 and is set based on which
4119/// SHXADD we are trying to match.
4120bool RISCVDAGToDAGISel::selectSHXADDOp(SDValue N, unsigned ShAmt,
4121 SDValue &Val) {
4122 if (N.getOpcode() == ISD::AND && isa<ConstantSDNode>(Val: N.getOperand(i: 1))) {
4123 SDValue N0 = N.getOperand(i: 0);
4124
4125 if (bool LeftShift = N0.getOpcode() == ISD::SHL;
4126 (LeftShift || N0.getOpcode() == ISD::SRL) &&
4127 isa<ConstantSDNode>(Val: N0.getOperand(i: 1))) {
4128 uint64_t Mask = N.getConstantOperandVal(i: 1);
4129 unsigned C2 = N0.getConstantOperandVal(i: 1);
4130
4131 unsigned XLen = Subtarget->getXLen();
4132 if (LeftShift)
4133 Mask &= maskTrailingZeros<uint64_t>(N: C2);
4134 else
4135 Mask &= maskTrailingOnes<uint64_t>(N: XLen - C2);
4136
4137 if (isShiftedMask_64(Value: Mask)) {
4138 unsigned Leading = XLen - llvm::bit_width(Value: Mask);
4139 unsigned Trailing = llvm::countr_zero(Val: Mask);
4140 if (Trailing != ShAmt)
4141 return false;
4142
4143 unsigned Opcode;
4144 // Look for (and (shl y, c2), c1) where c1 is a shifted mask with no
4145 // leading zeros and c3 trailing zeros. We can use an SRLI by c3-c2
4146 // followed by a SHXADD with c3 for the X amount.
4147 if (LeftShift && Leading == 0 && C2 < Trailing)
4148 Opcode = RISCV::SRLI;
4149 // Look for (and (shl y, c2), c1) where c1 is a shifted mask with 32-c2
4150 // leading zeros and c3 trailing zeros. We can use an SRLIW by c3-c2
4151 // followed by a SHXADD with c3 for the X amount.
4152 else if (LeftShift && Leading == 32 - C2 && C2 < Trailing)
4153 Opcode = RISCV::SRLIW;
4154 // Look for (and (shr y, c2), c1) where c1 is a shifted mask with c2
4155 // leading zeros and c3 trailing zeros. We can use an SRLI by c2+c3
4156 // followed by a SHXADD using c3 for the X amount.
4157 else if (!LeftShift && Leading == C2)
4158 Opcode = RISCV::SRLI;
4159 // Look for (and (shr y, c2), c1) where c1 is a shifted mask with 32+c2
4160 // leading zeros and c3 trailing zeros. We can use an SRLIW by c2+c3
4161 // followed by a SHXADD using c3 for the X amount.
4162 else if (!LeftShift && Leading == 32 + C2)
4163 Opcode = RISCV::SRLIW;
4164 else
4165 return false;
4166
4167 SDLoc DL(N);
4168 EVT VT = N.getValueType();
4169 ShAmt = LeftShift ? Trailing - C2 : Trailing + C2;
4170 Val = SDValue(
4171 CurDAG->getMachineNode(Opcode, dl: DL, VT, Op1: N0.getOperand(i: 0),
4172 Op2: CurDAG->getTargetConstant(Val: ShAmt, DL, VT)),
4173 0);
4174 return true;
4175 }
4176 } else if (N0.getOpcode() == ISD::SRA && N0.hasOneUse() &&
4177 isa<ConstantSDNode>(Val: N0.getOperand(i: 1))) {
4178 uint64_t Mask = N.getConstantOperandVal(i: 1);
4179 unsigned C2 = N0.getConstantOperandVal(i: 1);
4180
4181 // Look for (and (sra y, c2), c1) where c1 is a shifted mask with c3
4182 // leading zeros and c4 trailing zeros. If c2 is greater than c3, we can
4183 // use (srli (srai y, c2 - c3), c3 + c4) followed by a SHXADD with c4 as
4184 // the X amount.
4185 if (isShiftedMask_64(Value: Mask)) {
4186 unsigned XLen = Subtarget->getXLen();
4187 unsigned Leading = XLen - llvm::bit_width(Value: Mask);
4188 unsigned Trailing = llvm::countr_zero(Val: Mask);
4189 if (C2 > Leading && Leading > 0 && Trailing == ShAmt) {
4190 SDLoc DL(N);
4191 EVT VT = N.getValueType();
4192 Val = SDValue(CurDAG->getMachineNode(
4193 Opcode: RISCV::SRAI, dl: DL, VT, Op1: N0.getOperand(i: 0),
4194 Op2: CurDAG->getTargetConstant(Val: C2 - Leading, DL, VT)),
4195 0);
4196 Val = SDValue(CurDAG->getMachineNode(
4197 Opcode: RISCV::SRLI, dl: DL, VT, Op1: Val,
4198 Op2: CurDAG->getTargetConstant(Val: Leading + ShAmt, DL, VT)),
4199 0);
4200 return true;
4201 }
4202 }
4203 }
4204 } else if (bool LeftShift = N.getOpcode() == ISD::SHL;
4205 (LeftShift || N.getOpcode() == ISD::SRL) &&
4206 isa<ConstantSDNode>(Val: N.getOperand(i: 1))) {
4207 SDValue N0 = N.getOperand(i: 0);
4208 if (N0.getOpcode() == ISD::AND && N0.hasOneUse() &&
4209 isa<ConstantSDNode>(Val: N0.getOperand(i: 1))) {
4210 uint64_t Mask = N0.getConstantOperandVal(i: 1);
4211 if (isShiftedMask_64(Value: Mask)) {
4212 unsigned C1 = N.getConstantOperandVal(i: 1);
4213 unsigned XLen = Subtarget->getXLen();
4214 unsigned Leading = XLen - llvm::bit_width(Value: Mask);
4215 unsigned Trailing = llvm::countr_zero(Val: Mask);
4216 // Look for (shl (and X, Mask), C1) where Mask has 32 leading zeros and
4217 // C3 trailing zeros. If C1+C3==ShAmt we can use SRLIW+SHXADD.
4218 if (LeftShift && Leading == 32 && Trailing > 0 &&
4219 (Trailing + C1) == ShAmt) {
4220 SDLoc DL(N);
4221 EVT VT = N.getValueType();
4222 Val = SDValue(CurDAG->getMachineNode(
4223 Opcode: RISCV::SRLIW, dl: DL, VT, Op1: N0.getOperand(i: 0),
4224 Op2: CurDAG->getTargetConstant(Val: Trailing, DL, VT)),
4225 0);
4226 return true;
4227 }
4228 // Look for (srl (and X, Mask), C1) where Mask has 32 leading zeros and
4229 // C3 trailing zeros. If C3-C1==ShAmt we can use SRLIW+SHXADD.
4230 if (!LeftShift && Leading == 32 && Trailing > C1 &&
4231 (Trailing - C1) == ShAmt) {
4232 SDLoc DL(N);
4233 EVT VT = N.getValueType();
4234 Val = SDValue(CurDAG->getMachineNode(
4235 Opcode: RISCV::SRLIW, dl: DL, VT, Op1: N0.getOperand(i: 0),
4236 Op2: CurDAG->getTargetConstant(Val: Trailing, DL, VT)),
4237 0);
4238 return true;
4239 }
4240 }
4241 }
4242 }
4243
4244 return false;
4245}
4246
4247/// Look for various patterns that can be done with a SHL that can be folded
4248/// into a SHXADD_UW. \p ShAmt contains 1, 2, or 3 and is set based on which
4249/// SHXADD_UW we are trying to match.
4250bool RISCVDAGToDAGISel::selectSHXADD_UWOp(SDValue N, unsigned ShAmt,
4251 SDValue &Val) {
4252 if (N.getOpcode() == ISD::AND && isa<ConstantSDNode>(Val: N.getOperand(i: 1)) &&
4253 N.hasOneUse()) {
4254 SDValue N0 = N.getOperand(i: 0);
4255 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(Val: N0.getOperand(i: 1)) &&
4256 N0.hasOneUse()) {
4257 uint64_t Mask = N.getConstantOperandVal(i: 1);
4258 unsigned C2 = N0.getConstantOperandVal(i: 1);
4259
4260 Mask &= maskTrailingZeros<uint64_t>(N: C2);
4261
4262 // Look for (and (shl y, c2), c1) where c1 is a shifted mask with
4263 // 32-ShAmt leading zeros and c2 trailing zeros. We can use SLLI by
4264 // c2-ShAmt followed by SHXADD_UW with ShAmt for the X amount.
4265 if (isShiftedMask_64(Value: Mask)) {
4266 unsigned Leading = llvm::countl_zero(Val: Mask);
4267 unsigned Trailing = llvm::countr_zero(Val: Mask);
4268 if (Leading == 32 - ShAmt && Trailing == C2 && Trailing > ShAmt) {
4269 SDLoc DL(N);
4270 EVT VT = N.getValueType();
4271 Val = SDValue(CurDAG->getMachineNode(
4272 Opcode: RISCV::SLLI, dl: DL, VT, Op1: N0.getOperand(i: 0),
4273 Op2: CurDAG->getTargetConstant(Val: C2 - ShAmt, DL, VT)),
4274 0);
4275 return true;
4276 }
4277 }
4278 }
4279 }
4280
4281 return false;
4282}
4283
4284bool RISCVDAGToDAGISel::orDisjoint(const SDNode *N) const {
4285 assert(N->getOpcode() == ISD::OR || N->getOpcode() == RISCVISD::OR_VL);
4286 if (N->getFlags().hasDisjoint())
4287 return true;
4288 return CurDAG->haveNoCommonBitsSet(A: N->getOperand(Num: 0), B: N->getOperand(Num: 1));
4289}
4290
4291bool RISCVDAGToDAGISel::selectImm64IfCheaper(int64_t Imm, int64_t OrigImm,
4292 SDValue N, SDValue &Val) {
4293 int OrigCost = RISCVMatInt::getIntMatCost(Val: APInt(64, OrigImm), Size: 64, STI: *Subtarget,
4294 /*CompressionCost=*/true);
4295 int Cost = RISCVMatInt::getIntMatCost(Val: APInt(64, Imm), Size: 64, STI: *Subtarget,
4296 /*CompressionCost=*/true);
4297 if (OrigCost <= Cost)
4298 return false;
4299
4300 Val = selectImm(CurDAG, DL: SDLoc(N), VT: N->getSimpleValueType(ResNo: 0), Imm, Subtarget: *Subtarget);
4301 return true;
4302}
4303
4304bool RISCVDAGToDAGISel::selectZExtImm32(SDValue N, SDValue &Val) {
4305 if (!isa<ConstantSDNode>(Val: N))
4306 return false;
4307 int64_t Imm = cast<ConstantSDNode>(Val&: N)->getSExtValue();
4308 if ((Imm >> 31) != 1)
4309 return false;
4310
4311 for (const SDNode *U : N->users()) {
4312 switch (U->getOpcode()) {
4313 case ISD::ADD:
4314 break;
4315 case ISD::OR:
4316 if (orDisjoint(N: U))
4317 break;
4318 return false;
4319 default:
4320 return false;
4321 }
4322 }
4323
4324 return selectImm64IfCheaper(Imm: 0xffffffff00000000 | Imm, OrigImm: Imm, N, Val);
4325}
4326
4327bool RISCVDAGToDAGISel::selectNegImm(SDValue N, SDValue &Val) {
4328 if (!isa<ConstantSDNode>(Val: N))
4329 return false;
4330 int64_t Imm = cast<ConstantSDNode>(Val&: N)->getSExtValue();
4331 if (isInt<32>(x: Imm))
4332 return false;
4333 if (Imm == INT64_MIN)
4334 return false;
4335
4336 for (const SDNode *U : N->users()) {
4337 switch (U->getOpcode()) {
4338 case ISD::ADD:
4339 break;
4340 case RISCVISD::VMV_V_X_VL:
4341 if (!all_of(Range: U->users(), P: [](const SDNode *V) {
4342 return V->getOpcode() == ISD::ADD ||
4343 V->getOpcode() == RISCVISD::ADD_VL;
4344 }))
4345 return false;
4346 break;
4347 default:
4348 return false;
4349 }
4350 }
4351
4352 return selectImm64IfCheaper(Imm: -Imm, OrigImm: Imm, N, Val);
4353}
4354
4355bool RISCVDAGToDAGISel::selectInvLogicImm(SDValue N, SDValue &Val) {
4356 if (!isa<ConstantSDNode>(Val: N))
4357 return false;
4358 int64_t Imm = cast<ConstantSDNode>(Val&: N)->getSExtValue();
4359
4360 // For 32-bit signed constants, we can only substitute LUI+ADDI with LUI.
4361 if (isInt<32>(x: Imm) && ((Imm & 0xfff) != 0xfff || Imm == -1))
4362 return false;
4363
4364 // Abandon this transform if the constant is needed elsewhere.
4365 for (const SDNode *U : N->users()) {
4366 switch (U->getOpcode()) {
4367 case ISD::AND:
4368 case ISD::OR:
4369 case ISD::XOR:
4370 if (!(Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbkb()))
4371 return false;
4372 break;
4373 case RISCVISD::VMV_V_X_VL:
4374 if (!Subtarget->hasStdExtZvkb())
4375 return false;
4376 if (!all_of(Range: U->users(), P: [](const SDNode *V) {
4377 return V->getOpcode() == ISD::AND ||
4378 V->getOpcode() == RISCVISD::AND_VL;
4379 }))
4380 return false;
4381 break;
4382 default:
4383 return false;
4384 }
4385 }
4386
4387 if (isInt<32>(x: Imm)) {
4388 Val =
4389 selectImm(CurDAG, DL: SDLoc(N), VT: N->getSimpleValueType(ResNo: 0), Imm: ~Imm, Subtarget: *Subtarget);
4390 return true;
4391 }
4392
4393 // For 64-bit constants, the instruction sequences get complex,
4394 // so we select inverted only if it's cheaper.
4395 return selectImm64IfCheaper(Imm: ~Imm, OrigImm: Imm, N, Val);
4396}
4397
4398static bool vectorPseudoHasAllNBitUsers(SDNode *User, unsigned UserOpNo,
4399 unsigned Bits,
4400 const TargetInstrInfo *TII) {
4401 unsigned MCOpcode = RISCV::getRVVMCOpcode(RVVPseudoOpcode: User->getMachineOpcode());
4402
4403 if (!MCOpcode)
4404 return false;
4405
4406 const MCInstrDesc &MCID = TII->get(Opcode: User->getMachineOpcode());
4407 const uint64_t TSFlags = MCID.TSFlags;
4408 if (!RISCVII::hasSEWOp(TSFlags))
4409 return false;
4410 assert(RISCVII::hasVLOp(TSFlags));
4411
4412 unsigned ChainOpIdx = User->getNumOperands() - 1;
4413 bool HasChainOp = User->getOperand(Num: ChainOpIdx).getValueType() == MVT::Other;
4414 bool HasVecPolicyOp = RISCVII::hasVecPolicyOp(TSFlags);
4415 unsigned VLIdx = User->getNumOperands() - HasVecPolicyOp - HasChainOp - 2;
4416 const unsigned Log2SEW = User->getConstantOperandVal(Num: VLIdx + 1);
4417
4418 if (UserOpNo == VLIdx)
4419 return false;
4420
4421 auto NumDemandedBits =
4422 RISCV::getVectorLowDemandedScalarBits(Opcode: MCOpcode, Log2SEW);
4423 return NumDemandedBits && Bits >= *NumDemandedBits;
4424}
4425
4426// Return true if all users of this SDNode* only consume the lower \p Bits.
4427// This can be used to form W instructions for add/sub/mul/shl even when the
4428// root isn't a sext_inreg. This can allow the ADDW/SUBW/MULW/SLLIW to CSE if
4429// SimplifyDemandedBits has made it so some users see a sext_inreg and some
4430// don't. The sext_inreg+add/sub/mul/shl will get selected, but still leave
4431// the add/sub/mul/shl to become non-W instructions. By checking the users we
4432// may be able to use a W instruction and CSE with the other instruction if
4433// this has happened. We could try to detect that the CSE opportunity exists
4434// before doing this, but that would be more complicated.
4435bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits,
4436 const unsigned Depth) const {
4437 assert((Node->getOpcode() == ISD::ADD || Node->getOpcode() == ISD::SUB ||
4438 Node->getOpcode() == ISD::MUL || Node->getOpcode() == ISD::SHL ||
4439 Node->getOpcode() == ISD::SRL || Node->getOpcode() == ISD::AND ||
4440 Node->getOpcode() == ISD::OR || Node->getOpcode() == ISD::XOR ||
4441 Node->getOpcode() == ISD::SIGN_EXTEND_INREG ||
4442 isa<ConstantSDNode>(Node) || Depth != 0) &&
4443 "Unexpected opcode");
4444
4445 if (Depth >= SelectionDAG::MaxRecursionDepth)
4446 return false;
4447
4448 // The PatFrags that call this may run before RISCVGenDAGISel.inc has checked
4449 // the VT. Ensure the type is scalar to avoid wasting time on vectors.
4450 if (Depth == 0 && !Node->getValueType(ResNo: 0).isScalarInteger())
4451 return false;
4452
4453 for (SDUse &Use : Node->uses()) {
4454 SDNode *User = Use.getUser();
4455 // Users of this node should have already been instruction selected
4456 if (!User->isMachineOpcode())
4457 return false;
4458
4459 // TODO: Add more opcodes?
4460 switch (User->getMachineOpcode()) {
4461 default:
4462 if (vectorPseudoHasAllNBitUsers(User, UserOpNo: Use.getOperandNo(), Bits, TII))
4463 break;
4464 return false;
4465 case RISCV::ADDW:
4466 case RISCV::ADDIW:
4467 case RISCV::SUBW:
4468 case RISCV::MULW:
4469 case RISCV::SLLW:
4470 case RISCV::SLLIW:
4471 case RISCV::SRAW:
4472 case RISCV::SRAIW:
4473 case RISCV::SRLW:
4474 case RISCV::SRLIW:
4475 case RISCV::DIVW:
4476 case RISCV::DIVUW:
4477 case RISCV::REMW:
4478 case RISCV::REMUW:
4479 case RISCV::ROLW:
4480 case RISCV::RORW:
4481 case RISCV::RORIW:
4482 case RISCV::CLSW:
4483 case RISCV::CLZW:
4484 case RISCV::CTZW:
4485 case RISCV::CPOPW:
4486 case RISCV::SLLI_UW:
4487 case RISCV::ABSW:
4488 case RISCV::FMV_W_X:
4489 case RISCV::FCVT_H_W:
4490 case RISCV::FCVT_H_W_INX:
4491 case RISCV::FCVT_H_WU:
4492 case RISCV::FCVT_H_WU_INX:
4493 case RISCV::FCVT_S_W:
4494 case RISCV::FCVT_S_W_INX:
4495 case RISCV::FCVT_S_WU:
4496 case RISCV::FCVT_S_WU_INX:
4497 case RISCV::FCVT_D_W:
4498 case RISCV::FCVT_D_W_INX:
4499 case RISCV::FCVT_D_WU:
4500 case RISCV::FCVT_D_WU_INX:
4501 case RISCV::TH_REVW:
4502 case RISCV::TH_SRRIW:
4503 if (Bits >= 32)
4504 break;
4505 return false;
4506 case RISCV::SLL:
4507 case RISCV::SRA:
4508 case RISCV::SRL:
4509 case RISCV::ROL:
4510 case RISCV::ROR:
4511 case RISCV::BSET:
4512 case RISCV::BCLR:
4513 case RISCV::BINV:
4514 // Shift amount operands only use log2(Xlen) bits.
4515 if (Use.getOperandNo() == 1 && Bits >= Log2_32(Value: Subtarget->getXLen()))
4516 break;
4517 return false;
4518 case RISCV::SLLI:
4519 // SLLI only uses the lower (XLen - ShAmt) bits.
4520 if (Bits >= Subtarget->getXLen() - User->getConstantOperandVal(Num: 1))
4521 break;
4522 return false;
4523 case RISCV::ANDI:
4524 if (Bits >= (unsigned)llvm::bit_width(Value: User->getConstantOperandVal(Num: 1)))
4525 break;
4526 goto RecCheck;
4527 case RISCV::ORI: {
4528 uint64_t Imm = cast<ConstantSDNode>(Val: User->getOperand(Num: 1))->getSExtValue();
4529 if (Bits >= (unsigned)llvm::bit_width<uint64_t>(Value: ~Imm))
4530 break;
4531 [[fallthrough]];
4532 }
4533 case RISCV::AND:
4534 case RISCV::OR:
4535 case RISCV::XOR:
4536 case RISCV::XORI:
4537 case RISCV::ANDN:
4538 case RISCV::ORN:
4539 case RISCV::XNOR:
4540 case RISCV::SH1ADD:
4541 case RISCV::SH2ADD:
4542 case RISCV::SH3ADD:
4543 RecCheck:
4544 if (hasAllNBitUsers(Node: User, Bits, Depth: Depth + 1))
4545 break;
4546 return false;
4547 case RISCV::SRLI: {
4548 unsigned ShAmt = User->getConstantOperandVal(Num: 1);
4549 // If we are shifting right by less than Bits, and users don't demand any
4550 // bits that were shifted into [Bits-1:0], then we can consider this as an
4551 // N-Bit user.
4552 if (Bits > ShAmt && hasAllNBitUsers(Node: User, Bits: Bits - ShAmt, Depth: Depth + 1))
4553 break;
4554 return false;
4555 }
4556 case RISCV::SEXT_B:
4557 case RISCV::PACKH:
4558 if (Bits >= 8)
4559 break;
4560 return false;
4561 case RISCV::SEXT_H:
4562 case RISCV::FMV_H_X:
4563 case RISCV::ZEXT_H_RV32:
4564 case RISCV::ZEXT_H_RV64:
4565 case RISCV::PACKW:
4566 if (Bits >= 16)
4567 break;
4568 return false;
4569 case RISCV::PACK:
4570 if (Bits >= (Subtarget->getXLen() / 2))
4571 break;
4572 return false;
4573 case RISCV::PPAIRE_H:
4574 // If only the lower 32-bits of the result are used, then only the
4575 // lower 16 bits of the inputs are used.
4576 if (Bits >= 16 && hasAllNBitUsers(Node: User, Bits: 32, Depth: Depth + 1))
4577 break;
4578 return false;
4579 case RISCV::ADD_UW:
4580 case RISCV::SH1ADD_UW:
4581 case RISCV::SH2ADD_UW:
4582 case RISCV::SH3ADD_UW:
4583 // The first operand to add.uw/shXadd.uw is implicitly zero extended from
4584 // 32 bits.
4585 if (Use.getOperandNo() == 0 && Bits >= 32)
4586 break;
4587 return false;
4588 case RISCV::SB:
4589 if (Use.getOperandNo() == 0 && Bits >= 8)
4590 break;
4591 return false;
4592 case RISCV::SH:
4593 if (Use.getOperandNo() == 0 && Bits >= 16)
4594 break;
4595 return false;
4596 case RISCV::SW:
4597 if (Use.getOperandNo() == 0 && Bits >= 32)
4598 break;
4599 return false;
4600 case RISCV::TH_EXT:
4601 case RISCV::TH_EXTU: {
4602 unsigned Msb = User->getConstantOperandVal(Num: 1);
4603 unsigned Lsb = User->getConstantOperandVal(Num: 2);
4604 // Behavior of Msb < Lsb is not well documented.
4605 if (Msb >= Lsb && Bits > Msb)
4606 break;
4607 return false;
4608 }
4609 }
4610 }
4611
4612 return true;
4613}
4614
4615// Select a constant that can be represented as (sign_extend(imm5) << imm2).
4616bool RISCVDAGToDAGISel::selectSimm5Shl2(SDValue N, SDValue &Simm5,
4617 SDValue &Shl2) {
4618 auto *C = dyn_cast<ConstantSDNode>(Val&: N);
4619 if (!C)
4620 return false;
4621
4622 int64_t Offset = C->getSExtValue();
4623 for (unsigned Shift = 0; Shift < 4; Shift++) {
4624 if (isInt<5>(x: Offset >> Shift) && ((Offset % (1LL << Shift)) == 0)) {
4625 EVT VT = N->getValueType(ResNo: 0);
4626 Simm5 = CurDAG->getSignedTargetConstant(Val: Offset >> Shift, DL: SDLoc(N), VT);
4627 Shl2 = CurDAG->getTargetConstant(Val: Shift, DL: SDLoc(N), VT);
4628 return true;
4629 }
4630 }
4631
4632 return false;
4633}
4634
4635// Select VL as a 5 bit immediate or a value that will become a register. This
4636// allows us to choose between VSETIVLI or VSETVLI later.
4637bool RISCVDAGToDAGISel::selectVLOp(SDValue N, SDValue &VL) {
4638 auto *C = dyn_cast<ConstantSDNode>(Val&: N);
4639 if (C && isUInt<5>(x: C->getZExtValue())) {
4640 VL = CurDAG->getTargetConstant(Val: C->getZExtValue(), DL: SDLoc(N),
4641 VT: N->getValueType(ResNo: 0));
4642 } else if (C && C->isAllOnes()) {
4643 // Treat all ones as VLMax.
4644 VL = CurDAG->getSignedTargetConstant(Val: RISCV::VLMaxSentinel, DL: SDLoc(N),
4645 VT: N->getValueType(ResNo: 0));
4646 } else if (isa<RegisterSDNode>(Val: N) &&
4647 cast<RegisterSDNode>(Val&: N)->getReg() == RISCV::X0) {
4648 // All our VL operands use an operand that allows GPRNoX0 or an immediate
4649 // as the register class. Convert X0 to a special immediate to pass the
4650 // MachineVerifier. This is recognized specially by the vsetvli insertion
4651 // pass.
4652 VL = CurDAG->getSignedTargetConstant(Val: RISCV::VLMaxSentinel, DL: SDLoc(N),
4653 VT: N->getValueType(ResNo: 0));
4654 } else {
4655 VL = N;
4656 }
4657
4658 return true;
4659}
4660
4661static SDValue findVSplat(SDValue N) {
4662 if (N.getOpcode() == ISD::INSERT_SUBVECTOR) {
4663 if (!N.getOperand(i: 0).isUndef())
4664 return SDValue();
4665 N = N.getOperand(i: 1);
4666 }
4667 SDValue Splat = N;
4668 if ((Splat.getOpcode() != RISCVISD::VMV_V_X_VL &&
4669 Splat.getOpcode() != RISCVISD::VMV_S_X_VL) ||
4670 !Splat.getOperand(i: 0).isUndef())
4671 return SDValue();
4672 assert(Splat.getNumOperands() == 3 && "Unexpected number of operands");
4673 return Splat;
4674}
4675
4676bool RISCVDAGToDAGISel::selectVSplat(SDValue N, SDValue &SplatVal) {
4677 SDValue Splat = findVSplat(N);
4678 if (!Splat)
4679 return false;
4680
4681 SplatVal = Splat.getOperand(i: 1);
4682 return true;
4683}
4684
4685static bool selectVSplatImmHelper(SDValue N, SDValue &SplatVal,
4686 SelectionDAG &DAG,
4687 const RISCVSubtarget &Subtarget,
4688 std::function<bool(int64_t)> ValidateImm,
4689 bool Decrement = false) {
4690 SDValue Splat = findVSplat(N);
4691 if (!Splat || !isa<ConstantSDNode>(Val: Splat.getOperand(i: 1)))
4692 return false;
4693
4694 const unsigned SplatEltSize = Splat.getScalarValueSizeInBits();
4695 assert(Subtarget.getXLenVT() == Splat.getOperand(1).getSimpleValueType() &&
4696 "Unexpected splat operand type");
4697
4698 // The semantics of RISCVISD::VMV_V_X_VL is that when the operand
4699 // type is wider than the resulting vector element type: an implicit
4700 // truncation first takes place. Therefore, perform a manual
4701 // truncation/sign-extension in order to ignore any truncated bits and catch
4702 // any zero-extended immediate.
4703 // For example, we wish to match (i8 -1) -> (XLenVT 255) as a simm5 by first
4704 // sign-extending to (XLenVT -1).
4705 APInt SplatConst = Splat.getConstantOperandAPInt(i: 1).sextOrTrunc(width: SplatEltSize);
4706
4707 int64_t SplatImm = SplatConst.getSExtValue();
4708
4709 if (!ValidateImm(SplatImm))
4710 return false;
4711
4712 if (Decrement)
4713 SplatImm -= 1;
4714
4715 SplatVal =
4716 DAG.getSignedTargetConstant(Val: SplatImm, DL: SDLoc(N), VT: Subtarget.getXLenVT());
4717 return true;
4718}
4719
4720bool RISCVDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &SplatVal) {
4721 return selectVSplatImmHelper(N, SplatVal, DAG&: *CurDAG, Subtarget: *Subtarget,
4722 ValidateImm: [](int64_t Imm) { return isInt<5>(x: Imm); });
4723}
4724
4725bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal) {
4726 return selectVSplatImmHelper(
4727 N, SplatVal, DAG&: *CurDAG, Subtarget: *Subtarget,
4728 ValidateImm: [](int64_t Imm) { return Imm >= -15 && Imm <= 16; },
4729 /*Decrement=*/true);
4730}
4731
4732bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1NoDec(SDValue N, SDValue &SplatVal) {
4733 return selectVSplatImmHelper(
4734 N, SplatVal, DAG&: *CurDAG, Subtarget: *Subtarget,
4735 ValidateImm: [](int64_t Imm) { return Imm >= -15 && Imm <= 16; },
4736 /*Decrement=*/false);
4737}
4738
4739bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1NonZero(SDValue N,
4740 SDValue &SplatVal) {
4741 return selectVSplatImmHelper(
4742 N, SplatVal, DAG&: *CurDAG, Subtarget: *Subtarget,
4743 ValidateImm: [](int64_t Imm) { return Imm != 0 && Imm >= -15 && Imm <= 16; },
4744 /*Decrement=*/true);
4745}
4746
4747bool RISCVDAGToDAGISel::selectVSplatUimm(SDValue N, unsigned Bits,
4748 SDValue &SplatVal) {
4749 return selectVSplatImmHelper(
4750 N, SplatVal, DAG&: *CurDAG, Subtarget: *Subtarget,
4751 ValidateImm: [Bits](int64_t Imm) { return isUIntN(N: Bits, x: Imm); });
4752}
4753
4754bool RISCVDAGToDAGISel::selectVSplatImm64Neg(SDValue N, SDValue &SplatVal) {
4755 SDValue Splat = findVSplat(N);
4756 return Splat && selectNegImm(N: Splat.getOperand(i: 1), Val&: SplatVal);
4757}
4758
4759bool RISCVDAGToDAGISel::selectLow8BitsVSplat(SDValue N, SDValue &SplatVal) {
4760 auto IsExtOrTrunc = [](SDValue N) {
4761 switch (N->getOpcode()) {
4762 case ISD::SIGN_EXTEND:
4763 case ISD::ZERO_EXTEND:
4764 // There's no passthru on these _VL nodes so any VL/mask is ok, since any
4765 // inactive elements will be undef.
4766 case RISCVISD::TRUNCATE_VECTOR_VL:
4767 case RISCVISD::VSEXT_VL:
4768 case RISCVISD::VZEXT_VL:
4769 return true;
4770 default:
4771 return false;
4772 }
4773 };
4774
4775 // We can have multiple nested nodes, so unravel them all if needed.
4776 while (IsExtOrTrunc(N)) {
4777 if (!N.hasOneUse() || N.getScalarValueSizeInBits() < 8)
4778 return false;
4779 N = N->getOperand(Num: 0);
4780 }
4781
4782 return selectVSplat(N, SplatVal);
4783}
4784
4785bool RISCVDAGToDAGISel::selectScalarFPAsInt(SDValue N, SDValue &Imm) {
4786 // Allow bitcasts from XLenVT -> FP.
4787 if (N.getOpcode() == ISD::BITCAST &&
4788 N.getOperand(i: 0).getValueType() == Subtarget->getXLenVT()) {
4789 Imm = N.getOperand(i: 0);
4790 return true;
4791 }
4792 // Allow moves from XLenVT to FP.
4793 if (N.getOpcode() == RISCVISD::FMV_H_X ||
4794 N.getOpcode() == RISCVISD::FMV_W_X_RV64) {
4795 Imm = N.getOperand(i: 0);
4796 return true;
4797 }
4798
4799 // Otherwise, look for FP constants that can materialized with scalar int.
4800 ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Val: N.getNode());
4801 if (!CFP)
4802 return false;
4803 const APFloat &APF = CFP->getValueAPF();
4804 // td can handle +0.0 already.
4805 if (APF.isPosZero())
4806 return false;
4807
4808 MVT VT = CFP->getSimpleValueType(ResNo: 0);
4809
4810 MVT XLenVT = Subtarget->getXLenVT();
4811 if (VT == MVT::f64 && !Subtarget->is64Bit()) {
4812 assert(APF.isNegZero() && "Unexpected constant.");
4813 return false;
4814 }
4815 SDLoc DL(N);
4816 Imm = selectImm(CurDAG, DL, VT: XLenVT, Imm: APF.bitcastToAPInt().getSExtValue(),
4817 Subtarget: *Subtarget);
4818 return true;
4819}
4820
4821bool RISCVDAGToDAGISel::selectRVVSimm5(SDValue N, unsigned Width,
4822 SDValue &Imm) {
4823 if (auto *C = dyn_cast<ConstantSDNode>(Val&: N)) {
4824 int64_t ImmVal = SignExtend64(X: C->getSExtValue(), B: Width);
4825
4826 if (!isInt<5>(x: ImmVal))
4827 return false;
4828
4829 Imm = CurDAG->getSignedTargetConstant(Val: ImmVal, DL: SDLoc(N),
4830 VT: Subtarget->getXLenVT());
4831 return true;
4832 }
4833
4834 return false;
4835}
4836
4837// Match XOR with a VMSET_VL operand. Return the other operand.
4838bool RISCVDAGToDAGISel::selectVMNOTOp(SDValue N, SDValue &Res) {
4839 if (N.getOpcode() != ISD::XOR)
4840 return false;
4841
4842 if (N.getOperand(i: 0).getOpcode() == RISCVISD::VMSET_VL) {
4843 Res = N.getOperand(i: 1);
4844 return true;
4845 }
4846
4847 if (N.getOperand(i: 1).getOpcode() == RISCVISD::VMSET_VL) {
4848 Res = N.getOperand(i: 0);
4849 return true;
4850 }
4851
4852 return false;
4853}
4854
4855// Match VMXOR_VL with a VMSET_VL operand. Making sure that that VL operand
4856// matches the parent's VL. Return the other operand of the VMXOR_VL.
4857bool RISCVDAGToDAGISel::selectVMNOT_VLOp(SDNode *Parent, SDValue N,
4858 SDValue &Res) {
4859 if (N.getOpcode() != RISCVISD::VMXOR_VL)
4860 return false;
4861
4862 assert(Parent &&
4863 (Parent->getOpcode() == RISCVISD::VMAND_VL ||
4864 Parent->getOpcode() == RISCVISD::VMOR_VL ||
4865 Parent->getOpcode() == RISCVISD::VMXOR_VL) &&
4866 "Unexpected parent");
4867
4868 // The VL should match the parent.
4869 if (Parent->getOperand(Num: 2) != N->getOperand(Num: 2))
4870 return false;
4871
4872 if (N.getOperand(i: 0).getOpcode() == RISCVISD::VMSET_VL) {
4873 Res = N.getOperand(i: 1);
4874 return true;
4875 }
4876
4877 if (N.getOperand(i: 1).getOpcode() == RISCVISD::VMSET_VL) {
4878 Res = N.getOperand(i: 0);
4879 return true;
4880 }
4881
4882 return false;
4883}
4884
4885// Try to remove sext.w if the input is a W instruction or can be made into
4886// a W instruction cheaply.
4887bool RISCVDAGToDAGISel::doPeepholeSExtW(SDNode *N) {
4888 // Look for the sext.w pattern, addiw rd, rs1, 0.
4889 if (N->getMachineOpcode() != RISCV::ADDIW ||
4890 !isNullConstant(V: N->getOperand(Num: 1)))
4891 return false;
4892
4893 SDValue N0 = N->getOperand(Num: 0);
4894 if (!N0.isMachineOpcode())
4895 return false;
4896
4897 switch (N0.getMachineOpcode()) {
4898 default:
4899 break;
4900 case RISCV::ADD:
4901 case RISCV::ADDI:
4902 case RISCV::SUB:
4903 case RISCV::MUL:
4904 case RISCV::SLLI: {
4905 // Convert sext.w+add/sub/mul to their W instructions. This will create
4906 // a new independent instruction. This improves latency.
4907 unsigned Opc;
4908 switch (N0.getMachineOpcode()) {
4909 default:
4910 llvm_unreachable("Unexpected opcode!");
4911 case RISCV::ADD: Opc = RISCV::ADDW; break;
4912 case RISCV::ADDI: Opc = RISCV::ADDIW; break;
4913 case RISCV::SUB: Opc = RISCV::SUBW; break;
4914 case RISCV::MUL: Opc = RISCV::MULW; break;
4915 case RISCV::SLLI: Opc = RISCV::SLLIW; break;
4916 }
4917
4918 SDValue N00 = N0.getOperand(i: 0);
4919 SDValue N01 = N0.getOperand(i: 1);
4920
4921 // Shift amount needs to be uimm5.
4922 if (N0.getMachineOpcode() == RISCV::SLLI &&
4923 !isUInt<5>(x: cast<ConstantSDNode>(Val&: N01)->getSExtValue()))
4924 break;
4925
4926 SDNode *Result =
4927 CurDAG->getMachineNode(Opcode: Opc, dl: SDLoc(N), VT: N->getValueType(ResNo: 0),
4928 Op1: N00, Op2: N01);
4929 ReplaceUses(F: N, T: Result);
4930 return true;
4931 }
4932 case RISCV::ADDW:
4933 case RISCV::ADDIW:
4934 case RISCV::SUBW:
4935 case RISCV::MULW:
4936 case RISCV::SLLIW:
4937 case RISCV::PACKW:
4938 case RISCV::TH_MULAW:
4939 case RISCV::TH_MULAH:
4940 case RISCV::TH_MULSW:
4941 case RISCV::TH_MULSH:
4942 if (N0.getValueType() == MVT::i32)
4943 break;
4944
4945 // Result is already sign extended just remove the sext.w.
4946 // NOTE: We only handle the nodes that are selected with hasAllWUsers.
4947 ReplaceUses(F: N, T: N0.getNode());
4948 return true;
4949 }
4950
4951 return false;
4952}
4953
4954static bool usesAllOnesMask(SDValue MaskOp) {
4955 const auto IsVMSet = [](unsigned Opc) {
4956 return Opc == RISCV::PseudoVMSET_M_B1 || Opc == RISCV::PseudoVMSET_M_B16 ||
4957 Opc == RISCV::PseudoVMSET_M_B2 || Opc == RISCV::PseudoVMSET_M_B32 ||
4958 Opc == RISCV::PseudoVMSET_M_B4 || Opc == RISCV::PseudoVMSET_M_B64 ||
4959 Opc == RISCV::PseudoVMSET_M_B8;
4960 };
4961
4962 // TODO: Check that the VMSET is the expected bitwidth? The pseudo has
4963 // undefined behaviour if it's the wrong bitwidth, so we could choose to
4964 // assume that it's all-ones? Same applies to its VL.
4965 return MaskOp->isMachineOpcode() && IsVMSet(MaskOp.getMachineOpcode());
4966}
4967
4968static bool isImplicitDef(SDValue V) {
4969 if (!V.isMachineOpcode())
4970 return false;
4971 if (V.getMachineOpcode() == TargetOpcode::REG_SEQUENCE) {
4972 for (unsigned I = 1; I < V.getNumOperands(); I += 2)
4973 if (!isImplicitDef(V: V.getOperand(i: I)))
4974 return false;
4975 return true;
4976 }
4977 return V.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF;
4978}
4979
4980// Optimize masked RVV pseudo instructions with a known all-ones mask to their
4981// corresponding "unmasked" pseudo versions.
4982bool RISCVDAGToDAGISel::doPeepholeMaskedRVV(MachineSDNode *N) {
4983 const RISCV::RISCVMaskedPseudoInfo *I =
4984 RISCV::getMaskedPseudoInfo(MaskedPseudo: N->getMachineOpcode());
4985 if (!I)
4986 return false;
4987
4988 unsigned MaskOpIdx = I->MaskOpIdx;
4989 if (!usesAllOnesMask(MaskOp: N->getOperand(Num: MaskOpIdx)))
4990 return false;
4991
4992 // There are two classes of pseudos in the table - compares and
4993 // everything else. See the comment on RISCVMaskedPseudo for details.
4994 const unsigned Opc = I->UnmaskedPseudo;
4995 const MCInstrDesc &MCID = TII->get(Opcode: Opc);
4996 const bool HasPassthru = RISCVII::isFirstDefTiedToFirstUse(Desc: MCID);
4997
4998 const MCInstrDesc &MaskedMCID = TII->get(Opcode: N->getMachineOpcode());
4999 const bool MaskedHasPassthru = RISCVII::isFirstDefTiedToFirstUse(Desc: MaskedMCID);
5000
5001 assert((RISCVII::hasVecPolicyOp(MaskedMCID.TSFlags) ||
5002 !RISCVII::hasVecPolicyOp(MCID.TSFlags)) &&
5003 "Unmasked pseudo has policy but masked pseudo doesn't?");
5004 assert(RISCVII::hasVecPolicyOp(MCID.TSFlags) == HasPassthru &&
5005 "Unexpected pseudo structure");
5006 assert(!(HasPassthru && !MaskedHasPassthru) &&
5007 "Unmasked pseudo has passthru but masked pseudo doesn't?");
5008
5009 SmallVector<SDValue, 8> Ops;
5010 // Skip the passthru operand at index 0 if the unmasked don't have one.
5011 bool ShouldSkip = !HasPassthru && MaskedHasPassthru;
5012 bool DropPolicy = !RISCVII::hasVecPolicyOp(TSFlags: MCID.TSFlags) &&
5013 RISCVII::hasVecPolicyOp(TSFlags: MaskedMCID.TSFlags);
5014 bool HasChainOp =
5015 N->getOperand(Num: N->getNumOperands() - 1).getValueType() == MVT::Other;
5016 unsigned LastOpNum = N->getNumOperands() - 1 - HasChainOp;
5017 for (unsigned I = ShouldSkip, E = N->getNumOperands(); I != E; I++) {
5018 // Skip the mask
5019 SDValue Op = N->getOperand(Num: I);
5020 if (I == MaskOpIdx)
5021 continue;
5022 if (DropPolicy && I == LastOpNum)
5023 continue;
5024 Ops.push_back(Elt: Op);
5025 }
5026
5027 MachineSDNode *Result =
5028 CurDAG->getMachineNode(Opcode: Opc, dl: SDLoc(N), VTs: N->getVTList(), Ops);
5029
5030 if (!N->memoperands_empty())
5031 CurDAG->setNodeMemRefs(N: Result, NewMemRefs: N->memoperands());
5032
5033 Result->setFlags(N->getFlags());
5034 ReplaceUses(F: N, T: Result);
5035
5036 return true;
5037}
5038
5039/// If our passthru is an implicit_def, use noreg instead. This side
5040/// steps issues with MachineCSE not being able to CSE expressions with
5041/// IMPLICIT_DEF operands while preserving the semantic intent. See
5042/// pr64282 for context. Note that this transform is the last one
5043/// performed at ISEL DAG to DAG.
5044bool RISCVDAGToDAGISel::doPeepholeNoRegPassThru() {
5045 bool MadeChange = false;
5046 SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_end();
5047
5048 while (Position != CurDAG->allnodes_begin()) {
5049 SDNode *N = &*--Position;
5050 if (N->use_empty() || !N->isMachineOpcode())
5051 continue;
5052
5053 const unsigned Opc = N->getMachineOpcode();
5054 if (!RISCVVPseudosTable::getPseudoInfo(Pseudo: Opc) ||
5055 !RISCVII::isFirstDefTiedToFirstUse(Desc: TII->get(Opcode: Opc)) ||
5056 !isImplicitDef(V: N->getOperand(Num: 0)))
5057 continue;
5058
5059 SmallVector<SDValue> Ops;
5060 Ops.push_back(Elt: CurDAG->getRegister(Reg: RISCV::NoRegister, VT: N->getValueType(ResNo: 0)));
5061 for (unsigned I = 1, E = N->getNumOperands(); I != E; I++) {
5062 SDValue Op = N->getOperand(Num: I);
5063 Ops.push_back(Elt: Op);
5064 }
5065
5066 MachineSDNode *Result =
5067 CurDAG->getMachineNode(Opcode: Opc, dl: SDLoc(N), VTs: N->getVTList(), Ops);
5068 Result->setFlags(N->getFlags());
5069 CurDAG->setNodeMemRefs(N: Result, NewMemRefs: cast<MachineSDNode>(Val: N)->memoperands());
5070 ReplaceUses(F: N, T: Result);
5071 MadeChange = true;
5072 }
5073 return MadeChange;
5074}
5075
5076
5077// This pass converts a legalized DAG into a RISCV-specific DAG, ready
5078// for instruction scheduling.
5079FunctionPass *llvm::createRISCVISelDag(RISCVTargetMachine &TM,
5080 CodeGenOptLevel OptLevel) {
5081 return new RISCVDAGToDAGISelLegacy(TM, OptLevel);
5082}
5083
5084char RISCVDAGToDAGISelLegacy::ID = 0;
5085
5086RISCVDAGToDAGISelLegacy::RISCVDAGToDAGISelLegacy(RISCVTargetMachine &TM,
5087 CodeGenOptLevel OptLevel)
5088 : SelectionDAGISelLegacy(
5089 ID, std::make_unique<RISCVDAGToDAGISel>(args&: TM, args&: OptLevel)) {}
5090
5091INITIALIZE_PASS(RISCVDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false)
5092