1//===-- RISCVRegisterInfo.cpp - RISC-V Register Information -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the RISC-V implementation of the TargetRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVRegisterInfo.h"
14#include "RISCV.h"
15#include "RISCVSubtarget.h"
16#include "llvm/ADT/SmallSet.h"
17#include "llvm/BinaryFormat/Dwarf.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/RegisterScavenging.h"
22#include "llvm/CodeGen/TargetFrameLowering.h"
23#include "llvm/CodeGen/TargetInstrInfo.h"
24#include "llvm/IR/DebugInfoMetadata.h"
25#include "llvm/Support/ErrorHandling.h"
26
27#define GET_REGINFO_TARGET_DESC
28#include "RISCVGenRegisterInfo.inc"
29
30using namespace llvm;
31
32static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");
33static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive");
34static_assert(RISCV::F1_H == RISCV::F0_H + 1, "Register list not consecutive");
35static_assert(RISCV::F31_H == RISCV::F0_H + 31,
36 "Register list not consecutive");
37static_assert(RISCV::F1_F == RISCV::F0_F + 1, "Register list not consecutive");
38static_assert(RISCV::F31_F == RISCV::F0_F + 31,
39 "Register list not consecutive");
40static_assert(RISCV::F1_D == RISCV::F0_D + 1, "Register list not consecutive");
41static_assert(RISCV::F31_D == RISCV::F0_D + 31,
42 "Register list not consecutive");
43static_assert(RISCV::F1_Q == RISCV::F0_Q + 1, "Register list not consecutive");
44static_assert(RISCV::F31_Q == RISCV::F0_Q + 31,
45 "Register list not consecutive");
46static_assert(RISCV::V1 == RISCV::V0 + 1, "Register list not consecutive");
47static_assert(RISCV::V31 == RISCV::V0 + 31, "Register list not consecutive");
48
49RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode)
50 : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
51 /*PC*/0, HwMode) {}
52
53const MCPhysReg *
54RISCVRegisterInfo::getIPRACSRegs(const MachineFunction *MF) const {
55 return CSR_IPRA_SaveList;
56}
57
58const MCPhysReg *
59RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
60 auto &Subtarget = MF->getSubtarget<RISCVSubtarget>();
61 if (MF->getFunction().getCallingConv() == CallingConv::GHC)
62 return CSR_NoRegs_SaveList;
63 if (MF->getFunction().getCallingConv() == CallingConv::PreserveMost)
64 return Subtarget.hasStdExtE() ? CSR_RT_MostRegs_RVE_SaveList
65 : CSR_RT_MostRegs_SaveList;
66 if (MF->getFunction().hasFnAttribute(Kind: "interrupt")) {
67 if (Subtarget.hasVInstructions()) {
68 if (Subtarget.hasStdExtD())
69 return Subtarget.hasStdExtE() ? CSR_XLEN_F64_V_Interrupt_RVE_SaveList
70 : CSR_XLEN_F64_V_Interrupt_SaveList;
71 if (Subtarget.hasStdExtF())
72 return Subtarget.hasStdExtE() ? CSR_XLEN_F32_V_Interrupt_RVE_SaveList
73 : CSR_XLEN_F32_V_Interrupt_SaveList;
74 return Subtarget.hasStdExtE() ? CSR_XLEN_V_Interrupt_RVE_SaveList
75 : CSR_XLEN_V_Interrupt_SaveList;
76 }
77 if (Subtarget.hasStdExtD())
78 return Subtarget.hasStdExtE() ? CSR_XLEN_F64_Interrupt_RVE_SaveList
79 : CSR_XLEN_F64_Interrupt_SaveList;
80 if (Subtarget.hasStdExtF())
81 return Subtarget.hasStdExtE() ? CSR_XLEN_F32_Interrupt_RVE_SaveList
82 : CSR_XLEN_F32_Interrupt_SaveList;
83 return Subtarget.hasStdExtE() ? CSR_Interrupt_RVE_SaveList
84 : CSR_Interrupt_SaveList;
85 }
86
87 bool HasVectorCSR =
88 MF->getFunction().getCallingConv() == CallingConv::RISCV_VectorCall &&
89 Subtarget.hasVInstructions();
90
91 switch (Subtarget.getTargetABI()) {
92 default:
93 llvm_unreachable("Unrecognized ABI");
94 case RISCVABI::ABI_ILP32E:
95 case RISCVABI::ABI_LP64E:
96 return CSR_ILP32E_LP64E_SaveList;
97 case RISCVABI::ABI_ILP32:
98 case RISCVABI::ABI_LP64:
99 if (HasVectorCSR)
100 return CSR_ILP32_LP64_V_SaveList;
101 return CSR_ILP32_LP64_SaveList;
102 case RISCVABI::ABI_ILP32F:
103 case RISCVABI::ABI_LP64F:
104 if (HasVectorCSR)
105 return CSR_ILP32F_LP64F_V_SaveList;
106 return CSR_ILP32F_LP64F_SaveList;
107 case RISCVABI::ABI_ILP32D:
108 case RISCVABI::ABI_LP64D:
109 if (HasVectorCSR)
110 return CSR_ILP32D_LP64D_V_SaveList;
111 return CSR_ILP32D_LP64D_SaveList;
112 }
113}
114
115const TargetRegisterClass *RISCVRegisterInfo::getConstrainedRegClassForReg(
116 Register Reg, const MachineRegisterInfo &MRI) const {
117 const RISCVSubtarget &STI = MRI.getMF().getSubtarget<RISCVSubtarget>();
118
119 const RegClassOrRegBank &RCOrRB = MRI.getRegClassOrRegBank(Reg);
120 if (const RegisterBank *RB = dyn_cast<const RegisterBank *>(Val: RCOrRB))
121 return getRegClassForTypeOnBank(Ty: MRI.getType(Reg), RB: *RB, Is64Bit: STI.is64Bit());
122
123 if (const auto *RC = dyn_cast<const TargetRegisterClass *>(Val: RCOrRB)) {
124 return getAllocatableClass(RC);
125 }
126
127 return nullptr;
128}
129
130const TargetRegisterClass *
131RISCVRegisterInfo::getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB,
132 bool Is64Bit) const {
133 if (RB.getID() == RISCV::GPRBRegBankID) {
134 if (Ty.getSizeInBits() <= 32 || (Is64Bit && Ty.getSizeInBits() == 64))
135 return &RISCV::GPRRegClass;
136 }
137
138 if (RB.getID() == RISCV::FPRBRegBankID) {
139 if (Ty.getSizeInBits() == 16)
140 return &RISCV::FPR16RegClass;
141 if (Ty.getSizeInBits() == 32)
142 return &RISCV::FPR32RegClass;
143 if (Ty.getSizeInBits() == 64)
144 return &RISCV::FPR64RegClass;
145 }
146
147 if (RB.getID() == RISCV::VRBRegBankID) {
148 if (Ty.getSizeInBits().getKnownMinValue() <= 64)
149 return &RISCV::VRRegClass;
150
151 if (Ty.getSizeInBits().getKnownMinValue() == 128)
152 return &RISCV::VRM2RegClass;
153
154 if (Ty.getSizeInBits().getKnownMinValue() == 256)
155 return &RISCV::VRM4RegClass;
156
157 if (Ty.getSizeInBits().getKnownMinValue() == 512)
158 return &RISCV::VRM8RegClass;
159 }
160
161 return nullptr;
162}
163
164BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
165 const RISCVFrameLowering *TFI = getFrameLowering(MF);
166 BitVector Reserved(getNumRegs());
167 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
168
169 for (size_t Reg = 0; Reg < getNumRegs(); Reg++) {
170 // Mark any GPRs requested to be reserved as such
171 if (Subtarget.isRegisterReservedByUser(i: Reg)) {
172 for (MCPhysReg Sub : subregs_inclusive(Reg))
173 markSuperRegs(RegisterSet&: Reserved, Reg: Sub);
174 }
175
176 // Mark all the registers defined as constant in TableGen as reserved.
177 if (isConstantPhysReg(PhysReg: Reg)) {
178 for (MCPhysReg Sub : subregs_inclusive(Reg))
179 markSuperRegs(RegisterSet&: Reserved, Reg: Sub);
180 }
181 }
182
183 // Use markSuperRegs to ensure any register aliases are also reserved
184 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::X2_H); // sp
185 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::X3_H); // gp
186 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::X4_H); // tp
187 if (TFI->hasFP(MF))
188 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::X8_H); // fp
189 // Reserve the base register if we need to realign the stack and allocate
190 // variable-sized objects at runtime.
191 if (TFI->hasBP(MF))
192 markSuperRegs(RegisterSet&: Reserved, Reg: RISCVABI::getBPReg()); // bp
193
194 // There are only 16 GPRs for RVE.
195 if (Subtarget.hasStdExtE())
196 for (MCPhysReg Reg = RISCV::X16_H; Reg <= RISCV::X31_H; Reg++)
197 markSuperRegs(RegisterSet&: Reserved, Reg);
198
199 // V registers for code generation. We handle them manually.
200 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::VL);
201 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::VTYPE);
202 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::VXSAT);
203 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::VXRM);
204
205 // Floating point environment registers.
206 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::FRM);
207 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::FFLAGS);
208
209 // SiFive VCIX state registers.
210 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::SF_VCIX_STATE);
211
212 if (MF.getFunction().getCallingConv() == CallingConv::GRAAL) {
213 if (Subtarget.hasStdExtE())
214 reportFatalUsageError(reason: "Graal reserved registers do not exist in RVE");
215 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::X23_H);
216 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::X27_H);
217 }
218
219 // Shadow stack pointer.
220 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::SSP);
221
222 // XSfmmbase
223 for (MCPhysReg Reg = RISCV::T0; Reg <= RISCV::T15; Reg++)
224 markSuperRegs(RegisterSet&: Reserved, Reg);
225
226 assert(checkAllSuperRegsMarked(Reserved));
227 return Reserved;
228}
229
230bool RISCVRegisterInfo::isAsmClobberable(const MachineFunction &MF,
231 MCRegister PhysReg) const {
232 return !MF.getSubtarget().isRegisterReservedByUser(R: PhysReg);
233}
234
235const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const {
236 return CSR_NoRegs_RegMask;
237}
238
239void RISCVRegisterInfo::adjustReg(MachineBasicBlock &MBB,
240 MachineBasicBlock::iterator II,
241 const DebugLoc &DL, Register DestReg,
242 Register SrcReg, StackOffset Offset,
243 MachineInstr::MIFlag Flag,
244 MaybeAlign RequiredAlign) const {
245
246 if (DestReg == SrcReg && !Offset.getFixed() && !Offset.getScalable())
247 return;
248
249 MachineFunction &MF = *MBB.getParent();
250 MachineRegisterInfo &MRI = MF.getRegInfo();
251 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
252 const RISCVInstrInfo *TII = ST.getInstrInfo();
253
254 // Optimize compile time offset case
255 if (Offset.getScalable()) {
256 if (auto VLEN = ST.getRealVLen()) {
257 // 1. Multiply the number of v-slots by the (constant) length of register
258 const int64_t VLENB = *VLEN / 8;
259 assert(Offset.getScalable() % RISCV::RVVBytesPerBlock == 0 &&
260 "Reserve the stack by the multiple of one vector size.");
261 const int64_t NumOfVReg = Offset.getScalable() / 8;
262 const int64_t FixedOffset = NumOfVReg * VLENB;
263 if (!isInt<32>(x: FixedOffset)) {
264 // This check might also need to be updated to 64bit.
265 // However mulImm() still assumes 32bit. For now only support fixed
266 // 64bit frame offsets, since scalable offsets would require the number
267 // of spilled registers to exceed 2^31, which is unlikely.
268 reportFatalUsageError(reason: "Scalable frame size outside of the signed "
269 "32-bit range not supported");
270 }
271 Offset = StackOffset::getFixed(Fixed: FixedOffset + Offset.getFixed());
272 }
273 }
274
275 bool KillSrcReg = false;
276
277 if (Offset.getScalable()) {
278 unsigned ScalableAdjOpc = RISCV::ADD;
279 int64_t ScalableValue = Offset.getScalable();
280 if (ScalableValue < 0) {
281 ScalableValue = -ScalableValue;
282 ScalableAdjOpc = RISCV::SUB;
283 }
284 // Get vlenb and multiply vlen with the number of vector registers.
285 Register ScratchReg = DestReg;
286 if (DestReg == SrcReg)
287 ScratchReg = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
288
289 assert(ScalableValue > 0 && "There is no need to get VLEN scaled value.");
290 assert(ScalableValue % RISCV::RVVBytesPerBlock == 0 &&
291 "Reserve the stack by the multiple of one vector size.");
292 assert(isInt<32>(ScalableValue / RISCV::RVVBytesPerBlock) &&
293 "Expect the number of vector registers within 32-bits.");
294 uint32_t NumOfVReg = ScalableValue / RISCV::RVVBytesPerBlock;
295 // Only use vsetvli rather than vlenb if adjusting in the prologue or
296 // epilogue, otherwise it may disturb the VTYPE and VL status.
297 bool IsPrologueOrEpilogue =
298 Flag == MachineInstr::FrameSetup || Flag == MachineInstr::FrameDestroy;
299 bool UseVsetvliRatherThanVlenb =
300 IsPrologueOrEpilogue && ST.preferVsetvliOverReadVLENB();
301 if (UseVsetvliRatherThanVlenb && (NumOfVReg == 1 || NumOfVReg == 2 ||
302 NumOfVReg == 4 || NumOfVReg == 8)) {
303 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::PseudoReadVLENBViaVSETVLIX0),
304 DestReg: ScratchReg)
305 .addImm(Val: NumOfVReg)
306 .setMIFlag(Flag);
307 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: ScalableAdjOpc), DestReg)
308 .addReg(RegNo: SrcReg)
309 .addReg(RegNo: ScratchReg, Flags: RegState::Kill)
310 .setMIFlag(Flag);
311 } else {
312 if (UseVsetvliRatherThanVlenb)
313 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::PseudoReadVLENBViaVSETVLIX0),
314 DestReg: ScratchReg)
315 .addImm(Val: 1)
316 .setMIFlag(Flag);
317 else
318 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::PseudoReadVLENB), DestReg: ScratchReg)
319 .setMIFlag(Flag);
320
321 if (ScalableAdjOpc == RISCV::ADD && ST.hasStdExtZba() &&
322 (NumOfVReg == 2 || NumOfVReg == 4 || NumOfVReg == 8)) {
323 unsigned Opc = NumOfVReg == 2
324 ? RISCV::SH1ADD
325 : (NumOfVReg == 4 ? RISCV::SH2ADD : RISCV::SH3ADD);
326 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: Opc), DestReg)
327 .addReg(RegNo: ScratchReg, Flags: RegState::Kill)
328 .addReg(RegNo: SrcReg)
329 .setMIFlag(Flag);
330 } else {
331 TII->mulImm(MF, MBB, II, DL, DestReg: ScratchReg, Amt: NumOfVReg, Flag);
332 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: ScalableAdjOpc), DestReg)
333 .addReg(RegNo: SrcReg)
334 .addReg(RegNo: ScratchReg, Flags: RegState::Kill)
335 .setMIFlag(Flag);
336 }
337 }
338 SrcReg = DestReg;
339 KillSrcReg = true;
340 }
341
342 int64_t Val = Offset.getFixed();
343 if (DestReg == SrcReg && Val == 0)
344 return;
345
346 const uint64_t Align = RequiredAlign.valueOrOne().value();
347
348 if (isInt<12>(x: Val)) {
349 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::ADDI), DestReg)
350 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrcReg))
351 .addImm(Val)
352 .setMIFlag(Flag);
353 return;
354 }
355
356 // Use the QC_E_ADDI instruction from the Xqcilia extension that can take a
357 // signed 26-bit immediate.
358 if (ST.hasVendorXqcilia() && isInt<26>(x: Val)) {
359 // The one case where using this instruction is sub-optimal is if Val can be
360 // materialized with a single compressible LUI and following add/sub is also
361 // compressible. Avoid doing this if that is the case.
362 int Hi20 = (Val & 0xFFFFF000) >> 12;
363 bool IsCompressLUI =
364 ((Val & 0xFFF) == 0) && (Hi20 != 0) &&
365 (isUInt<5>(x: Hi20) || (Hi20 >= 0xfffe0 && Hi20 <= 0xfffff));
366 bool IsCompressAddSub =
367 (SrcReg == DestReg) &&
368 ((Val > 0 && RISCV::GPRNoX0RegClass.contains(Reg: SrcReg)) ||
369 (Val < 0 && RISCV::GPRCRegClass.contains(Reg: SrcReg)));
370
371 if (!(IsCompressLUI && IsCompressAddSub)) {
372 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::QC_E_ADDI), DestReg)
373 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrcReg))
374 .addImm(Val)
375 .setMIFlag(Flag);
376 return;
377 }
378 }
379
380 // Try to split the offset across two ADDIs. We need to keep the intermediate
381 // result aligned after each ADDI. We need to determine the maximum value we
382 // can put in each ADDI. In the negative direction, we can use -2048 which is
383 // always sufficiently aligned. In the positive direction, we need to find the
384 // largest 12-bit immediate that is aligned. Exclude -4096 since it can be
385 // created with LUI.
386 assert(Align < 2048 && "Required alignment too large");
387 int64_t MaxPosAdjStep = 2048 - Align;
388 if (Val > -4096 && Val <= (2 * MaxPosAdjStep)) {
389 int64_t FirstAdj = Val < 0 ? -2048 : MaxPosAdjStep;
390 Val -= FirstAdj;
391 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::ADDI), DestReg)
392 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrcReg))
393 .addImm(Val: FirstAdj)
394 .setMIFlag(Flag);
395 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::ADDI), DestReg)
396 .addReg(RegNo: DestReg, Flags: RegState::Kill)
397 .addImm(Val)
398 .setMIFlag(Flag);
399 return;
400 }
401
402 // Use shNadd if doing so lets us materialize a 12 bit immediate with a single
403 // instruction. This saves 1 instruction over the full lui/addi+add fallback
404 // path. We avoid anything which can be done with a single lui as it might
405 // be compressible. Note that the sh1add case is fully covered by the 2x addi
406 // case just above and is thus omitted.
407 if (ST.hasStdExtZba() && (Val & 0xFFF) != 0) {
408 unsigned Opc = 0;
409 if (isShiftedInt<12, 3>(x: Val)) {
410 Opc = RISCV::SH3ADD;
411 Val = Val >> 3;
412 } else if (isShiftedInt<12, 2>(x: Val)) {
413 Opc = RISCV::SH2ADD;
414 Val = Val >> 2;
415 }
416 if (Opc) {
417 Register ScratchReg = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
418 TII->movImm(MBB, MBBI: II, DL, DstReg: ScratchReg, Val, Flag);
419 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: Opc), DestReg)
420 .addReg(RegNo: ScratchReg, Flags: RegState::Kill)
421 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrcReg))
422 .setMIFlag(Flag);
423 return;
424 }
425 }
426
427 // Emit a PseudoAddUpperImm instead of LUI+ADD when the offset is a multiple
428 // of 4096 and the source is the frame register. The frame register is
429 // invariant after PEI, so MachineLateInstrsCleanup can CSE identical pseudos.
430 // The pseudo is later expanded back to LUI+ADD.
431 if (Flag == MachineInstr::NoFlags && !KillSrcReg && DestReg != SrcReg &&
432 SrcReg == getFrameRegister(MF) && isShiftedInt<20, 12>(x: Val)) {
433 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::PseudoAddUpperImm), DestReg)
434 .addReg(RegNo: SrcReg)
435 .addImm(Val: static_cast<uint32_t>(Val) >> 12);
436 return;
437 }
438
439 unsigned Opc = RISCV::ADD;
440 if (Val < 0) {
441 Val = -Val;
442 Opc = RISCV::SUB;
443 }
444
445 Register ScratchReg = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
446 TII->movImm(MBB, MBBI: II, DL, DstReg: ScratchReg, Val, Flag);
447 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: Opc), DestReg)
448 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrcReg))
449 .addReg(RegNo: ScratchReg, Flags: RegState::Kill)
450 .setMIFlag(Flag);
451}
452
453static std::tuple<RISCVVType::VLMUL, const TargetRegisterClass &, unsigned>
454getSpillReloadInfo(unsigned NumRemaining, uint16_t RegEncoding, bool IsSpill) {
455 if (NumRemaining >= 8 && RegEncoding % 8 == 0)
456 return {RISCVVType::LMUL_8, RISCV::VRM8RegClass,
457 IsSpill ? RISCV::VS8R_V : RISCV::VL8RE8_V};
458 if (NumRemaining >= 4 && RegEncoding % 4 == 0)
459 return {RISCVVType::LMUL_4, RISCV::VRM4RegClass,
460 IsSpill ? RISCV::VS4R_V : RISCV::VL4RE8_V};
461 if (NumRemaining >= 2 && RegEncoding % 2 == 0)
462 return {RISCVVType::LMUL_2, RISCV::VRM2RegClass,
463 IsSpill ? RISCV::VS2R_V : RISCV::VL2RE8_V};
464 return {RISCVVType::LMUL_1, RISCV::VRRegClass,
465 IsSpill ? RISCV::VS1R_V : RISCV::VL1RE8_V};
466}
467
468// Split a VSPILLx_Mx/VSPILLx_Mx pseudo into multiple whole register stores
469// separated by LMUL*VLENB bytes.
470void RISCVRegisterInfo::lowerSegmentSpillReload(MachineBasicBlock::iterator II,
471 bool IsSpill) const {
472 DebugLoc DL = II->getDebugLoc();
473 MachineBasicBlock &MBB = *II->getParent();
474 MachineFunction &MF = *MBB.getParent();
475 MachineRegisterInfo &MRI = MF.getRegInfo();
476 const RISCVSubtarget &STI = MF.getSubtarget<RISCVSubtarget>();
477 const TargetInstrInfo *TII = STI.getInstrInfo();
478 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
479
480 auto ZvlssegInfo = RISCV::isRVVSpillForZvlsseg(Opcode: II->getOpcode());
481 unsigned NF = ZvlssegInfo->first;
482 unsigned LMUL = ZvlssegInfo->second;
483 unsigned NumRegs = NF * LMUL;
484 assert(NumRegs <= 8 && "Invalid NF/LMUL combinations.");
485
486 Register Reg = II->getOperand(i: 0).getReg();
487 uint16_t RegEncoding = TRI->getEncodingValue(Reg);
488 Register Base = II->getOperand(i: 1).getReg();
489 bool IsBaseKill = II->getOperand(i: 1).isKill();
490 Register NewBase = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
491
492 auto *OldMMO = *(II->memoperands_begin());
493 LocationSize OldLoc = OldMMO->getSize();
494 assert(OldLoc.isPrecise() && OldLoc.getValue().isKnownMultipleOf(NF));
495 TypeSize VRegSize = OldLoc.getValue().divideCoefficientBy(RHS: NumRegs);
496
497 Register VLENB = 0;
498 unsigned VLENBShift = 0;
499 unsigned PrevHandledNum = 0;
500 unsigned I = 0;
501 while (I != NumRegs) {
502 auto [LMulHandled, RegClass, Opcode] =
503 getSpillReloadInfo(NumRemaining: NumRegs - I, RegEncoding, IsSpill);
504 auto [RegNumHandled, _] = RISCVVType::decodeVLMUL(VLMul: LMulHandled);
505 bool IsLast = I + RegNumHandled == NumRegs;
506 if (PrevHandledNum) {
507 Register Step;
508 // Optimize for constant VLEN.
509 if (auto VLEN = STI.getRealVLen()) {
510 int64_t Offset = *VLEN / 8 * PrevHandledNum;
511 Step = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
512 STI.getInstrInfo()->movImm(MBB, MBBI: II, DL, DstReg: Step, Val: Offset);
513 } else {
514 if (!VLENB) {
515 VLENB = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
516 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::PseudoReadVLENB), DestReg: VLENB);
517 }
518 uint32_t ShiftAmount = Log2_32(Value: PrevHandledNum);
519 // To avoid using an extra register, we shift the VLENB register and
520 // remember how much it has been shifted. We can then use relative
521 // shifts to adjust to the desired shift amount.
522 if (VLENBShift > ShiftAmount) {
523 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::SRLI), DestReg: VLENB)
524 .addReg(RegNo: VLENB, Flags: RegState::Kill)
525 .addImm(Val: VLENBShift - ShiftAmount);
526 } else if (VLENBShift < ShiftAmount) {
527 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::SLLI), DestReg: VLENB)
528 .addReg(RegNo: VLENB, Flags: RegState::Kill)
529 .addImm(Val: ShiftAmount - VLENBShift);
530 }
531 VLENBShift = ShiftAmount;
532 Step = VLENB;
533 }
534
535 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::ADD), DestReg: NewBase)
536 .addReg(RegNo: Base, Flags: getKillRegState(B: I != 0 || IsBaseKill))
537 .addReg(RegNo: Step, Flags: getKillRegState(B: Step != VLENB || IsLast));
538 Base = NewBase;
539 }
540
541 MCRegister ActualReg = findVRegWithEncoding(RegClass, Encoding: RegEncoding);
542 MachineInstrBuilder MIB =
543 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode))
544 .addReg(RegNo: ActualReg, Flags: getDefRegState(B: !IsSpill))
545 .addReg(RegNo: Base, Flags: getKillRegState(B: IsLast))
546 .addMemOperand(MMO: MF.getMachineMemOperand(MMO: OldMMO, Offset: OldMMO->getOffset(),
547 Size: VRegSize * RegNumHandled));
548
549 // Adding implicit-use of super register to describe we are using part of
550 // super register, that prevents machine verifier complaining when part of
551 // subreg is undef, see comment in MachineVerifier::checkLiveness for more
552 // detail.
553 if (IsSpill)
554 MIB.addReg(RegNo: Reg, Flags: RegState::Implicit);
555
556 PrevHandledNum = RegNumHandled;
557 RegEncoding += RegNumHandled;
558 I += RegNumHandled;
559 }
560 II->eraseFromParent();
561}
562
563static unsigned getXqciloWideOpcode(unsigned Opc) {
564 switch (Opc) {
565 case RISCV::LW:
566 return RISCV::QC_E_LW;
567 case RISCV::SW:
568 return RISCV::QC_E_SW;
569 case RISCV::LB:
570 return RISCV::QC_E_LB;
571 case RISCV::LBU:
572 return RISCV::QC_E_LBU;
573 case RISCV::LH:
574 return RISCV::QC_E_LH;
575 case RISCV::LHU:
576 return RISCV::QC_E_LHU;
577 case RISCV::SB:
578 return RISCV::QC_E_SB;
579 case RISCV::SH:
580 return RISCV::QC_E_SH;
581 default:
582 return 0;
583 }
584}
585
586bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
587 int SPAdj, unsigned FIOperandNum,
588 RegScavenger *RS) const {
589 assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
590
591 MachineInstr &MI = *II;
592 MachineFunction &MF = *MI.getParent()->getParent();
593 MachineRegisterInfo &MRI = MF.getRegInfo();
594 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
595 const RISCVInstrInfo *TII = ST.getInstrInfo();
596 bool Is64Bit = ST.is64Bit();
597 DebugLoc DL = MI.getDebugLoc();
598
599 int FrameIndex = MI.getOperand(i: FIOperandNum).getIndex();
600 Register FrameReg;
601 StackOffset Offset =
602 getFrameLowering(MF)->getFrameIndexReference(MF, FI: FrameIndex, FrameReg);
603 bool IsRVVSpill = RISCV::isRVVSpill(MI);
604 if (!IsRVVSpill)
605 Offset += StackOffset::getFixed(Fixed: MI.getOperand(i: FIOperandNum + 1).getImm());
606
607 if (!Is64Bit && !isInt<32>(x: Offset.getFixed())) {
608 reportFatalUsageError(reason: "Frame offsets outside of the signed 32-bit range "
609 "not supported on RV32");
610 }
611
612 if (!IsRVVSpill) {
613 int64_t Val = Offset.getFixed();
614 int64_t Lo12 = SignExtend64<12>(x: Val);
615 int64_t Lo26 = SignExtend64<26>(x: Val);
616 unsigned Opc = MI.getOpcode();
617
618 if (Opc == RISCV::ADDI && !isInt<12>(x: Val)) {
619 // We chose to emit the canonical immediate sequence rather than folding
620 // the offset into the using add under the theory that doing so doesn't
621 // save dynamic instruction count and some target may fuse the canonical
622 // 32 bit immediate sequence. We still need to clear the portion of the
623 // offset encoded in the immediate.
624 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: 0);
625 } else if ((Opc == RISCV::PREFETCH_I || Opc == RISCV::PREFETCH_R ||
626 Opc == RISCV::PREFETCH_W) &&
627 (Lo12 & 0b11111) != 0) {
628 // Prefetch instructions require the offset to be 32 byte aligned.
629 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: 0);
630 } else if (Opc == RISCV::MIPS_PREF && !isUInt<9>(x: Val)) {
631 // MIPS Prefetch instructions require the offset to be 9 bits encoded.
632 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: 0);
633 } else if ((Opc == RISCV::PseudoRV32ZdinxLD ||
634 Opc == RISCV::PseudoRV32ZdinxSD ||
635 Opc == RISCV::PseudoLD_RV32_OPT ||
636 Opc == RISCV::PseudoSD_RV32_OPT) &&
637 Lo12 >= 2044) {
638 // This instruction will/might be split into 2 instructions. The second
639 // instruction will add 4 to the immediate. If that would overflow 12
640 // bits, we can't fold the offset.
641 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: 0);
642 } else if (unsigned WideOpc = getXqciloWideOpcode(Opc);
643 !isInt<12>(x: Val) && ST.hasVendorXqcilo() && WideOpc) {
644 // The resolved frame offset exceeds simm12 but the instruction is a
645 // standard load/store (LW/SW/etc). Promote to the wide Xqcilo equivalent
646 // so the full 26-bit offset folds directly, avoiding a separate
647 // base-adjust instruction. This runs post-RA and does not affect
648 // register allocation decisions.
649 MI.setDesc(TII->get(Opcode: WideOpc));
650 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: Lo26);
651 Offset = StackOffset::get(Fixed: (uint64_t)Val - (uint64_t)Lo26,
652 Scalable: Offset.getScalable());
653 } else if (Opc == RISCV::QC_E_ADDI || RISCVInstrInfo::isBaseQCLoad(MI) ||
654 RISCVInstrInfo::isBaseQCStore(MI)) {
655 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: Lo26);
656 Offset = StackOffset::get(Fixed: (uint64_t)Val - (uint64_t)Lo26,
657 Scalable: Offset.getScalable());
658 } else {
659 // We can encode an add with 12 bit signed immediate in the immediate
660 // operand of our user instruction. As a result, the remaining
661 // offset can by construction, at worst, a LUI and a ADD.
662 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: Lo12);
663 Offset = StackOffset::get(Fixed: (uint64_t)Val - (uint64_t)Lo12,
664 Scalable: Offset.getScalable());
665 }
666 }
667
668 if (Offset.getScalable() || Offset.getFixed()) {
669 Register DestReg;
670 if (MI.getOpcode() == RISCV::ADDI)
671 DestReg = MI.getOperand(i: 0).getReg();
672 else
673 DestReg = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
674 adjustReg(MBB&: *II->getParent(), II, DL, DestReg, SrcReg: FrameReg, Offset,
675 Flag: MachineInstr::NoFlags, RequiredAlign: std::nullopt);
676 MI.getOperand(i: FIOperandNum).ChangeToRegister(Reg: DestReg, /*IsDef*/isDef: false,
677 /*IsImp*/isImp: false,
678 /*IsKill*/isKill: true);
679 } else {
680 MI.getOperand(i: FIOperandNum).ChangeToRegister(Reg: FrameReg, /*IsDef*/isDef: false,
681 /*IsImp*/isImp: false,
682 /*IsKill*/isKill: false);
683 }
684
685 // If after materializing the adjustment, we have a pointless ADDI, remove it
686 if (MI.getOpcode() == RISCV::ADDI &&
687 MI.getOperand(i: 0).getReg() == MI.getOperand(i: 1).getReg() &&
688 MI.getOperand(i: 2).getImm() == 0) {
689 MI.eraseFromParent();
690 return true;
691 }
692
693 // Handle spill/fill of synthetic register classes for segment operations to
694 // ensure correctness in the edge case one gets spilled.
695 switch (MI.getOpcode()) {
696 case RISCV::PseudoVSPILL2_M1:
697 case RISCV::PseudoVSPILL2_M2:
698 case RISCV::PseudoVSPILL2_M4:
699 case RISCV::PseudoVSPILL3_M1:
700 case RISCV::PseudoVSPILL3_M2:
701 case RISCV::PseudoVSPILL4_M1:
702 case RISCV::PseudoVSPILL4_M2:
703 case RISCV::PseudoVSPILL5_M1:
704 case RISCV::PseudoVSPILL6_M1:
705 case RISCV::PseudoVSPILL7_M1:
706 case RISCV::PseudoVSPILL8_M1:
707 lowerSegmentSpillReload(II, /*IsSpill=*/true);
708 return true;
709 case RISCV::PseudoVRELOAD2_M1:
710 case RISCV::PseudoVRELOAD2_M2:
711 case RISCV::PseudoVRELOAD2_M4:
712 case RISCV::PseudoVRELOAD3_M1:
713 case RISCV::PseudoVRELOAD3_M2:
714 case RISCV::PseudoVRELOAD4_M1:
715 case RISCV::PseudoVRELOAD4_M2:
716 case RISCV::PseudoVRELOAD5_M1:
717 case RISCV::PseudoVRELOAD6_M1:
718 case RISCV::PseudoVRELOAD7_M1:
719 case RISCV::PseudoVRELOAD8_M1:
720 lowerSegmentSpillReload(II, /*IsSpill=*/false);
721 return true;
722 }
723
724 return false;
725}
726
727bool RISCVRegisterInfo::requiresVirtualBaseRegisters(
728 const MachineFunction &MF) const {
729 return true;
730}
731
732// Returns true if the instruction's frame index reference would be better
733// served by a base register other than FP or SP.
734// Used by LocalStackSlotAllocation pass to determine which frame index
735// references it should create new base registers for.
736bool RISCVRegisterInfo::needsFrameBaseReg(MachineInstr *MI,
737 int64_t Offset) const {
738 unsigned FIOperandNum = 0;
739 for (; !MI->getOperand(i: FIOperandNum).isFI(); FIOperandNum++)
740 assert(FIOperandNum < MI->getNumOperands() &&
741 "Instr doesn't have FrameIndex operand");
742
743 // For RISC-V, The machine instructions that include a FrameIndex operand
744 // are load/store, ADDI instructions.
745 unsigned MIFrm = RISCVII::getFormat(TSFlags: MI->getDesc().TSFlags);
746 if (MIFrm != RISCVII::InstFormatI && MIFrm != RISCVII::InstFormatS)
747 return false;
748 // We only generate virtual base registers for loads and stores, so
749 // return false for everything else.
750 if (!MI->mayLoad() && !MI->mayStore())
751 return false;
752
753 const MachineFunction &MF = *MI->getMF();
754 const MachineFrameInfo &MFI = MF.getFrameInfo();
755 const RISCVFrameLowering *TFI = getFrameLowering(MF);
756 const MachineRegisterInfo &MRI = MF.getRegInfo();
757
758 if (TFI->hasFP(MF) && !shouldRealignStack(MF)) {
759 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
760 // Estimate the stack size used to store callee saved registers(
761 // excludes reserved registers).
762 unsigned CalleeSavedSize = 0;
763 for (const MCPhysReg *R = MRI.getCalleeSavedRegs(); MCPhysReg Reg = *R;
764 ++R) {
765 if (Subtarget.isRegisterReservedByUser(i: Reg))
766 continue;
767
768 if (RISCV::GPRRegClass.contains(Reg))
769 CalleeSavedSize += getSpillSize(RC: RISCV::GPRRegClass);
770 else if (RISCV::FPR64RegClass.contains(Reg))
771 CalleeSavedSize += getSpillSize(RC: RISCV::FPR64RegClass);
772 else if (RISCV::FPR32RegClass.contains(Reg))
773 CalleeSavedSize += getSpillSize(RC: RISCV::FPR32RegClass);
774 // Ignore vector registers.
775 }
776
777 int64_t MaxFPOffset = Offset - CalleeSavedSize;
778 if (isFrameOffsetLegal(MI, BaseReg: RISCV::X8, Offset: MaxFPOffset))
779 return false;
780
781 // If the FP-relative offset doesn't fit, fall through to check the
782 // SP-relative offset. getFrameIndexReference may select SP over FP when
783 // the SP offset fits in the compressed instruction immediate range, so a
784 // base register might not be needed.
785 }
786
787 // Assume 128 bytes spill slots size to estimate the maximum possible
788 // offset relative to the stack pointer.
789 // FIXME: The 128 is copied from ARM. We should run some statistics and pick a
790 // real one for RISC-V.
791 int64_t MaxSPOffset = Offset + 128;
792 MaxSPOffset += MFI.getLocalFrameSize();
793 return !isFrameOffsetLegal(MI, BaseReg: RISCV::X2, Offset: MaxSPOffset);
794}
795
796// Determine whether a given base register plus offset immediate is
797// encodable to resolve a frame index.
798bool RISCVRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
799 Register BaseReg,
800 int64_t Offset) const {
801 unsigned FIOperandNum = 0;
802 while (!MI->getOperand(i: FIOperandNum).isFI()) {
803 FIOperandNum++;
804 assert(FIOperandNum < MI->getNumOperands() &&
805 "Instr does not have a FrameIndex operand!");
806 }
807
808 Offset += getFrameIndexInstrOffset(MI, Idx: FIOperandNum);
809 return isInt<12>(x: Offset);
810}
811
812// Insert defining instruction(s) for a pointer to FrameIdx before
813// insertion point I.
814// Return materialized frame pointer.
815Register RISCVRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
816 int FrameIdx,
817 int64_t Offset) const {
818 MachineBasicBlock::iterator MBBI = MBB->begin();
819 DebugLoc DL;
820 if (MBBI != MBB->end())
821 DL = MBBI->getDebugLoc();
822 MachineFunction *MF = MBB->getParent();
823 MachineRegisterInfo &MFI = MF->getRegInfo();
824 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
825
826 Register BaseReg = MFI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
827 BuildMI(BB&: *MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: RISCV::ADDI), DestReg: BaseReg)
828 .addFrameIndex(Idx: FrameIdx)
829 .addImm(Val: Offset);
830 return BaseReg;
831}
832
833// Resolve a frame index operand of an instruction to reference the
834// indicated base register plus offset instead.
835void RISCVRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg,
836 int64_t Offset) const {
837 unsigned FIOperandNum = 0;
838 while (!MI.getOperand(i: FIOperandNum).isFI()) {
839 FIOperandNum++;
840 assert(FIOperandNum < MI.getNumOperands() &&
841 "Instr does not have a FrameIndex operand!");
842 }
843
844 Offset += getFrameIndexInstrOffset(MI: &MI, Idx: FIOperandNum);
845 // FrameIndex Operands are always represented as a
846 // register followed by an immediate.
847 MI.getOperand(i: FIOperandNum).ChangeToRegister(Reg: BaseReg, isDef: false);
848 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: Offset);
849}
850
851// Get the offset from the referenced frame index in the instruction,
852// if there is one.
853int64_t RISCVRegisterInfo::getFrameIndexInstrOffset(const MachineInstr *MI,
854 int Idx) const {
855 assert((RISCVII::getFormat(MI->getDesc().TSFlags) == RISCVII::InstFormatI ||
856 RISCVII::getFormat(MI->getDesc().TSFlags) == RISCVII::InstFormatS) &&
857 "The MI must be I or S format.");
858 assert(MI->getOperand(Idx).isFI() && "The Idx'th operand of MI is not a "
859 "FrameIndex operand");
860 return MI->getOperand(i: Idx + 1).getImm();
861}
862
863Register RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
864 const TargetFrameLowering *TFI = getFrameLowering(MF);
865 return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
866}
867
868bool RISCVRegisterInfo::isArgumentRegister(const MachineFunction &MF,
869 MCRegister Reg) const {
870 auto const &STI = MF.getSubtarget<RISCVSubtarget>();
871 const RISCVRegisterInfo *TRI = STI.getRegisterInfo();
872
873 if (TRI->isGeneralPurposeRegister(MF, PhysReg: Reg))
874 return llvm::is_contained(Range: RISCV::getArgGPRs(STI), Element: Reg);
875
876 if (TRI->isFPRegister(Reg))
877 return llvm::is_contained(Range: RISCV::getArgFPRs(STI), Element: Reg);
878
879 if (RISCV::VRRegClass.contains(Reg))
880 return llvm::is_contained(Range: RISCV::getArgVRs(STI), Element: Reg);
881
882 return false;
883}
884
885StringRef RISCVRegisterInfo::getRegAsmName(MCRegister Reg) const {
886 if (Reg == RISCV::SF_VCIX_STATE)
887 return "sf.vcix_state";
888 return TargetRegisterInfo::getRegAsmName(Reg);
889}
890
891const uint32_t *
892RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF,
893 CallingConv::ID CC) const {
894 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
895
896 if (CC == CallingConv::GHC)
897 return CSR_NoRegs_RegMask;
898 RISCVABI::ABI ABI = Subtarget.getTargetABI();
899 if (CC == CallingConv::PreserveMost) {
900 if (ABI == RISCVABI::ABI_ILP32E || ABI == RISCVABI::ABI_LP64E)
901 return CSR_RT_MostRegs_RVE_RegMask;
902 return CSR_RT_MostRegs_RegMask;
903 }
904 switch (ABI) {
905 default:
906 llvm_unreachable("Unrecognized ABI");
907 case RISCVABI::ABI_ILP32E:
908 case RISCVABI::ABI_LP64E:
909 return CSR_ILP32E_LP64E_RegMask;
910 case RISCVABI::ABI_ILP32:
911 case RISCVABI::ABI_LP64:
912 if (CC == CallingConv::RISCV_VectorCall)
913 return CSR_ILP32_LP64_V_RegMask;
914 return CSR_ILP32_LP64_RegMask;
915 case RISCVABI::ABI_ILP32F:
916 case RISCVABI::ABI_LP64F:
917 if (CC == CallingConv::RISCV_VectorCall)
918 return CSR_ILP32F_LP64F_V_RegMask;
919 return CSR_ILP32F_LP64F_RegMask;
920 case RISCVABI::ABI_ILP32D:
921 case RISCVABI::ABI_LP64D:
922 if (CC == CallingConv::RISCV_VectorCall)
923 return CSR_ILP32D_LP64D_V_RegMask;
924 return CSR_ILP32D_LP64D_RegMask;
925 }
926}
927
928const TargetRegisterClass *
929RISCVRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
930 const MachineFunction &) const {
931 if (RC == &RISCV::VMV0RegClass)
932 return &RISCV::VRRegClass;
933 if (RC == &RISCV::VRNoV0RegClass)
934 return &RISCV::VRRegClass;
935 if (RC == &RISCV::VRM2NoV0RegClass)
936 return &RISCV::VRM2RegClass;
937 if (RC == &RISCV::VRM4NoV0RegClass)
938 return &RISCV::VRM4RegClass;
939 if (RC == &RISCV::VRM8NoV0RegClass)
940 return &RISCV::VRM8RegClass;
941 return RC;
942}
943
944void RISCVRegisterInfo::getOffsetOpcodes(const StackOffset &Offset,
945 SmallVectorImpl<uint64_t> &Ops) const {
946 // VLENB is the length of a vector register in bytes. We use <vscale x 8 x i8>
947 // to represent one vector register. The dwarf offset is
948 // VLENB * scalable_offset / 8.
949 assert(Offset.getScalable() % 8 == 0 && "Invalid frame offset");
950
951 // Add fixed-sized offset using existing DIExpression interface.
952 DIExpression::appendOffset(Ops, Offset: Offset.getFixed());
953
954 unsigned VLENB = getDwarfRegNum(Reg: RISCV::VLENB, isEH: true);
955 int64_t VLENBSized = Offset.getScalable() / 8;
956 if (VLENBSized > 0) {
957 Ops.push_back(Elt: dwarf::DW_OP_constu);
958 Ops.push_back(Elt: VLENBSized);
959 Ops.append(IL: {dwarf::DW_OP_bregx, VLENB, 0ULL});
960 Ops.push_back(Elt: dwarf::DW_OP_mul);
961 Ops.push_back(Elt: dwarf::DW_OP_plus);
962 } else if (VLENBSized < 0) {
963 Ops.push_back(Elt: dwarf::DW_OP_constu);
964 Ops.push_back(Elt: -VLENBSized);
965 Ops.append(IL: {dwarf::DW_OP_bregx, VLENB, 0ULL});
966 Ops.push_back(Elt: dwarf::DW_OP_mul);
967 Ops.push_back(Elt: dwarf::DW_OP_minus);
968 }
969}
970
971std::pair<Register, Register>
972RISCVRegisterInfo::getGPRPairSubRegs(MCRegister Pair) const {
973 if (Pair == RISCV::X0_Pair)
974 return {RISCV::X0, RISCV::X0};
975 return {getSubReg(Reg: Pair, Idx: RISCV::sub_gpr_even),
976 getSubReg(Reg: Pair, Idx: RISCV::sub_gpr_odd)};
977}
978
979unsigned
980RISCVRegisterInfo::getRegisterCostTableIndex(const MachineFunction &MF) const {
981 // Set CostPerUse to 1 only when optimizing for size and RVC exists.
982 const auto &ST = MF.getSubtarget<RISCVSubtarget>();
983 return MF.getFunction().hasOptSize() && ST.hasStdExtZca() &&
984 ST.getCLOpts().cost_per_use
985 ? 1
986 : 0;
987}
988
989float RISCVRegisterInfo::getSpillWeightScaleFactor(
990 const TargetRegisterClass *RC) const {
991 return getRegClassWeight(RC).RegWeight;
992}
993
994// Add two address hints to improve chances of being able to use a compressed
995// instruction.
996bool RISCVRegisterInfo::getRegAllocationHints(
997 Register VirtReg, ArrayRef<MCPhysReg> Order,
998 SmallSetVector<MCPhysReg, 16> &Hints, const MachineFunction &MF,
999 const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
1000 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1001 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
1002
1003 // Handle RegPairEven/RegPairOdd hints for Zilsd register pairs
1004 std::pair<unsigned, Register> Hint = MRI->getRegAllocationHint(VReg: VirtReg);
1005 unsigned HintType = Hint.first;
1006 Register Partner = Hint.second;
1007
1008 MCRegister TargetReg;
1009 if (HintType == RISCVRI::RegPairEven || HintType == RISCVRI::RegPairOdd) {
1010 // Check if we want the even or odd register of a consecutive pair
1011 bool WantOdd = (HintType == RISCVRI::RegPairOdd);
1012
1013 // First priority: Check if partner is already allocated
1014 if (Partner.isVirtual() && VRM && VRM->hasPhys(virtReg: Partner)) {
1015 MCRegister PartnerPhys = VRM->getPhys(virtReg: Partner);
1016 // Calculate the exact register we need for consecutive pairing
1017 TargetReg = PartnerPhys.id() + (WantOdd ? 1 : -1);
1018
1019 // Verify it's valid and available
1020 if (RISCV::GPRRegClass.contains(Reg: TargetReg) &&
1021 is_contained(Range&: Order, Element: TargetReg))
1022 Hints.insert(X: TargetReg.id());
1023 }
1024
1025 // Second priority: Try to find consecutive register pairs in the allocation
1026 // order
1027 for (MCPhysReg PhysReg : Order) {
1028 // Don't add the hint if we already added above.
1029 if (TargetReg == PhysReg)
1030 continue;
1031
1032 unsigned RegNum = getEncodingValue(Reg: PhysReg);
1033 // Check if this register matches the even/odd requirement
1034 bool IsOdd = (RegNum % 2 != 0);
1035
1036 // Don't provide hints that are paired to a reserved register.
1037 MCRegister Paired = PhysReg + (IsOdd ? -1 : 1);
1038 if (WantOdd == IsOdd && !MRI->isReserved(PhysReg: Paired))
1039 Hints.insert(X: PhysReg);
1040 }
1041 }
1042
1043 bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
1044 VirtReg, Order, Hints, MF, VRM, Matrix);
1045
1046 if (!VRM || !MF.getSubtarget<RISCVSubtarget>().getCLOpts().regalloc_hints)
1047 return BaseImplRetVal;
1048
1049 // Add any two address hints after any copy hints.
1050 SmallSet<Register, 4> TwoAddrHints;
1051
1052 auto tryAddHint = [&](const MachineOperand &VRRegMO, const MachineOperand &MO,
1053 bool NeedGPRC) -> void {
1054 Register Reg = MO.getReg();
1055 Register PhysReg = Reg.isPhysical() ? Reg : Register(VRM->getPhys(virtReg: Reg));
1056 // TODO: Support GPRPair subregisters? Need to be careful with even/odd
1057 // registers. If the virtual register is an odd register of a pair and the
1058 // physical register is even (or vice versa), we should not add the hint.
1059 if (PhysReg && (!NeedGPRC || RISCV::GPRCRegClass.contains(Reg: PhysReg)) &&
1060 !MO.getSubReg() && !VRRegMO.getSubReg()) {
1061 if (!MRI->isReserved(PhysReg) && !Hints.contains(key: PhysReg))
1062 TwoAddrHints.insert(V: PhysReg);
1063 }
1064 };
1065
1066 // This is all of the compressible binary instructions. If an instruction
1067 // needs GPRC register class operands \p NeedGPRC will be set to true.
1068 auto isCompressible = [&Subtarget](const MachineInstr &MI, bool &NeedGPRC) {
1069 NeedGPRC = false;
1070 switch (MI.getOpcode()) {
1071 default:
1072 return false;
1073 case RISCV::AND:
1074 case RISCV::OR:
1075 case RISCV::XOR:
1076 case RISCV::SUB:
1077 case RISCV::ADDW:
1078 case RISCV::SUBW:
1079 NeedGPRC = true;
1080 return true;
1081 case RISCV::ANDI: {
1082 NeedGPRC = true;
1083 if (!MI.getOperand(i: 2).isImm())
1084 return false;
1085 int64_t Imm = MI.getOperand(i: 2).getImm();
1086 if (isInt<6>(x: Imm))
1087 return true;
1088 // c.zext.b
1089 return Subtarget.hasStdExtZcb() && Imm == 255;
1090 }
1091 case RISCV::SRAI:
1092 case RISCV::SRLI:
1093 NeedGPRC = true;
1094 return true;
1095 case RISCV::ADD:
1096 case RISCV::SLLI:
1097 return true;
1098 case RISCV::ADDI:
1099 case RISCV::ADDIW:
1100 return MI.getOperand(i: 2).isImm() && isInt<6>(x: MI.getOperand(i: 2).getImm());
1101 case RISCV::MUL:
1102 // c.mul
1103 NeedGPRC = true;
1104 return Subtarget.hasStdExtZcb();
1105 case RISCV::SEXT_B:
1106 case RISCV::SEXT_H:
1107 case RISCV::ZEXT_H_RV32:
1108 case RISCV::ZEXT_H_RV64:
1109 // c.sext.b, c.sext.h, c.zext.h
1110 NeedGPRC = true;
1111 return Subtarget.hasStdExtZcb() && Subtarget.hasStdExtZbb();
1112 case RISCV::ADD_UW:
1113 // c.zext.w
1114 NeedGPRC = true;
1115 return Subtarget.hasStdExtZcb() && MI.getOperand(i: 2).isReg() &&
1116 MI.getOperand(i: 2).getReg() == RISCV::X0;
1117 case RISCV::XORI:
1118 // c.not
1119 NeedGPRC = true;
1120 return Subtarget.hasStdExtZcb() && MI.getOperand(i: 2).isImm() &&
1121 MI.getOperand(i: 2).getImm() == -1;
1122 case RISCV::QC_EXTU:
1123 return MI.getOperand(i: 2).getImm() >= 6 && MI.getOperand(i: 3).getImm() == 0;
1124 case RISCV::BSETI:
1125 case RISCV::BEXTI:
1126 // qc.c.bseti, qc.c.bexti
1127 NeedGPRC = true;
1128 return Subtarget.hasVendorXqcibm() && MI.getOperand(i: 2).getImm() != 0;
1129 }
1130 };
1131
1132 // Returns true if this operand is compressible. For non-registers it always
1133 // returns true. Immediate range was already checked in isCompressible.
1134 // For registers, it checks if the register is a GPRC register. reg-reg
1135 // instructions that require GPRC need all register operands to be GPRC.
1136 auto isCompressibleOpnd = [&](const MachineOperand &MO) {
1137 if (!MO.isReg())
1138 return true;
1139 Register Reg = MO.getReg();
1140 Register PhysReg = Reg.isPhysical() ? Reg : Register(VRM->getPhys(virtReg: Reg));
1141 return PhysReg && RISCV::GPRCRegClass.contains(Reg: PhysReg);
1142 };
1143
1144 for (auto &MO : MRI->reg_nodbg_operands(Reg: VirtReg)) {
1145 const MachineInstr &MI = *MO.getParent();
1146 unsigned OpIdx = MO.getOperandNo();
1147 bool NeedGPRC;
1148 if (isCompressible(MI, NeedGPRC)) {
1149 if (OpIdx == 0 && MI.getOperand(i: 1).isReg()) {
1150 if (!NeedGPRC || MI.getNumExplicitOperands() < 3 ||
1151 MI.getOpcode() == RISCV::ADD_UW ||
1152 isCompressibleOpnd(MI.getOperand(i: 2)))
1153 tryAddHint(MO, MI.getOperand(i: 1), NeedGPRC);
1154 if (MI.isCommutable() && MI.getOperand(i: 2).isReg() &&
1155 (!NeedGPRC || isCompressibleOpnd(MI.getOperand(i: 1))))
1156 tryAddHint(MO, MI.getOperand(i: 2), NeedGPRC);
1157 } else if (OpIdx == 1 && (!NeedGPRC || MI.getNumExplicitOperands() < 3 ||
1158 isCompressibleOpnd(MI.getOperand(i: 2)))) {
1159 tryAddHint(MO, MI.getOperand(i: 0), NeedGPRC);
1160 } else if (MI.isCommutable() && OpIdx == 2 &&
1161 (!NeedGPRC || isCompressibleOpnd(MI.getOperand(i: 1)))) {
1162 tryAddHint(MO, MI.getOperand(i: 0), NeedGPRC);
1163 }
1164 }
1165
1166 // Add a hint if it would allow auipc/lui+addi(w) fusion. We do this even
1167 // without the fusions explicitly enabled as the impact is rarely negative
1168 // and some cores do implement this fusion.
1169 if ((MI.getOpcode() == RISCV::ADDIW || MI.getOpcode() == RISCV::ADDI) &&
1170 MI.getOperand(i: 1).isReg()) {
1171 const MachineBasicBlock &MBB = *MI.getParent();
1172 MachineBasicBlock::const_iterator I = MI.getIterator();
1173 // Is the previous instruction a LUI or AUIPC that can be fused?
1174 if (I != MBB.begin()) {
1175 I = skipDebugInstructionsBackward(It: std::prev(x: I), Begin: MBB.begin());
1176 if ((I->getOpcode() == RISCV::LUI || I->getOpcode() == RISCV::AUIPC) &&
1177 I->getOperand(i: 0).getReg() == MI.getOperand(i: 1).getReg()) {
1178 if (OpIdx == 0)
1179 tryAddHint(MO, MI.getOperand(i: 1), /*NeedGPRC=*/false);
1180 else
1181 tryAddHint(MO, MI.getOperand(i: 0), /*NeedGPRC=*/false);
1182 }
1183 }
1184 }
1185 }
1186
1187 for (MCPhysReg OrderReg : Order)
1188 if (TwoAddrHints.count(V: OrderReg))
1189 Hints.insert(X: OrderReg);
1190
1191 return BaseImplRetVal;
1192}
1193
1194void RISCVRegisterInfo::updateRegAllocHint(Register Reg, Register NewReg,
1195 MachineFunction &MF) const {
1196 MachineRegisterInfo *MRI = &MF.getRegInfo();
1197 std::pair<unsigned, Register> Hint = MRI->getRegAllocationHint(VReg: Reg);
1198
1199 // Handle RegPairEven/RegPairOdd hints for Zilsd register pairs
1200 if ((Hint.first == RISCVRI::RegPairOdd ||
1201 Hint.first == RISCVRI::RegPairEven) &&
1202 Hint.second.isVirtual()) {
1203 // If 'Reg' is one of the even/odd register pair and it's now changed
1204 // (e.g. coalesced) into a different register, the other register of the
1205 // pair allocation hint must be updated to reflect the relationship change.
1206 Register Partner = Hint.second;
1207 std::pair<unsigned, Register> PartnerHint =
1208 MRI->getRegAllocationHint(VReg: Partner);
1209
1210 // Make sure partner still points to us
1211 if (PartnerHint.second == Reg) {
1212 // Update partner to point to NewReg instead of Reg
1213 MRI->setRegAllocationHint(VReg: Partner, Type: PartnerHint.first, PrefReg: NewReg);
1214
1215 // If NewReg is virtual, set up the reciprocal hint
1216 // NewReg takes over Reg's role, so it gets the SAME hint type as Reg
1217 if (NewReg.isVirtual())
1218 MRI->setRegAllocationHint(VReg: NewReg, Type: Hint.first, PrefReg: Partner);
1219 }
1220 }
1221}
1222
1223Register
1224RISCVRegisterInfo::findVRegWithEncoding(const TargetRegisterClass &RegClass,
1225 uint16_t Encoding) const {
1226 MCRegister Reg = RISCV::V0 + Encoding;
1227 if (RISCVRI::getLMul(TSFlags: RegClass.TSFlags) == RISCVVType::LMUL_1)
1228 return Reg;
1229 return getMatchingSuperReg(Reg, SubIdx: RISCV::sub_vrm1_0, RC: &RegClass);
1230}
1231