1//===-- RISCVRegisterInfo.cpp - RISC-V Register Information -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the RISC-V implementation of the TargetRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVRegisterInfo.h"
14#include "RISCV.h"
15#include "RISCVSubtarget.h"
16#include "llvm/ADT/SmallSet.h"
17#include "llvm/BinaryFormat/Dwarf.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/RegisterScavenging.h"
22#include "llvm/CodeGen/TargetFrameLowering.h"
23#include "llvm/CodeGen/TargetInstrInfo.h"
24#include "llvm/IR/DebugInfoMetadata.h"
25#include "llvm/Support/ErrorHandling.h"
26
27#define GET_REGINFO_TARGET_DESC
28#include "RISCVGenRegisterInfo.inc"
29
30using namespace llvm;
31
32static cl::opt<bool> DisableCostPerUse("riscv-disable-cost-per-use",
33 cl::init(Val: false), cl::Hidden);
34static cl::opt<bool>
35 DisableRegAllocHints("riscv-disable-regalloc-hints", cl::Hidden,
36 cl::init(Val: false),
37 cl::desc("Disable two address hints for register "
38 "allocation"));
39
40static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");
41static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive");
42static_assert(RISCV::F1_H == RISCV::F0_H + 1, "Register list not consecutive");
43static_assert(RISCV::F31_H == RISCV::F0_H + 31,
44 "Register list not consecutive");
45static_assert(RISCV::F1_F == RISCV::F0_F + 1, "Register list not consecutive");
46static_assert(RISCV::F31_F == RISCV::F0_F + 31,
47 "Register list not consecutive");
48static_assert(RISCV::F1_D == RISCV::F0_D + 1, "Register list not consecutive");
49static_assert(RISCV::F31_D == RISCV::F0_D + 31,
50 "Register list not consecutive");
51static_assert(RISCV::F1_Q == RISCV::F0_Q + 1, "Register list not consecutive");
52static_assert(RISCV::F31_Q == RISCV::F0_Q + 31,
53 "Register list not consecutive");
54static_assert(RISCV::V1 == RISCV::V0 + 1, "Register list not consecutive");
55static_assert(RISCV::V31 == RISCV::V0 + 31, "Register list not consecutive");
56
57RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode)
58 : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
59 /*PC*/0, HwMode) {}
60
61const MCPhysReg *
62RISCVRegisterInfo::getIPRACSRegs(const MachineFunction *MF) const {
63 return CSR_IPRA_SaveList;
64}
65
66const MCPhysReg *
67RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
68 auto &Subtarget = MF->getSubtarget<RISCVSubtarget>();
69 if (MF->getFunction().getCallingConv() == CallingConv::GHC)
70 return CSR_NoRegs_SaveList;
71 if (MF->getFunction().getCallingConv() == CallingConv::PreserveMost)
72 return Subtarget.hasStdExtE() ? CSR_RT_MostRegs_RVE_SaveList
73 : CSR_RT_MostRegs_SaveList;
74 if (MF->getFunction().hasFnAttribute(Kind: "interrupt")) {
75 if (Subtarget.hasVInstructions()) {
76 if (Subtarget.hasStdExtD())
77 return Subtarget.hasStdExtE() ? CSR_XLEN_F64_V_Interrupt_RVE_SaveList
78 : CSR_XLEN_F64_V_Interrupt_SaveList;
79 if (Subtarget.hasStdExtF())
80 return Subtarget.hasStdExtE() ? CSR_XLEN_F32_V_Interrupt_RVE_SaveList
81 : CSR_XLEN_F32_V_Interrupt_SaveList;
82 return Subtarget.hasStdExtE() ? CSR_XLEN_V_Interrupt_RVE_SaveList
83 : CSR_XLEN_V_Interrupt_SaveList;
84 }
85 if (Subtarget.hasStdExtD())
86 return Subtarget.hasStdExtE() ? CSR_XLEN_F64_Interrupt_RVE_SaveList
87 : CSR_XLEN_F64_Interrupt_SaveList;
88 if (Subtarget.hasStdExtF())
89 return Subtarget.hasStdExtE() ? CSR_XLEN_F32_Interrupt_RVE_SaveList
90 : CSR_XLEN_F32_Interrupt_SaveList;
91 return Subtarget.hasStdExtE() ? CSR_Interrupt_RVE_SaveList
92 : CSR_Interrupt_SaveList;
93 }
94
95 bool HasVectorCSR =
96 MF->getFunction().getCallingConv() == CallingConv::RISCV_VectorCall &&
97 Subtarget.hasVInstructions();
98
99 switch (Subtarget.getTargetABI()) {
100 default:
101 llvm_unreachable("Unrecognized ABI");
102 case RISCVABI::ABI_ILP32E:
103 case RISCVABI::ABI_LP64E:
104 return CSR_ILP32E_LP64E_SaveList;
105 case RISCVABI::ABI_ILP32:
106 case RISCVABI::ABI_LP64:
107 if (HasVectorCSR)
108 return CSR_ILP32_LP64_V_SaveList;
109 return CSR_ILP32_LP64_SaveList;
110 case RISCVABI::ABI_ILP32F:
111 case RISCVABI::ABI_LP64F:
112 if (HasVectorCSR)
113 return CSR_ILP32F_LP64F_V_SaveList;
114 return CSR_ILP32F_LP64F_SaveList;
115 case RISCVABI::ABI_ILP32D:
116 case RISCVABI::ABI_LP64D:
117 if (HasVectorCSR)
118 return CSR_ILP32D_LP64D_V_SaveList;
119 return CSR_ILP32D_LP64D_SaveList;
120 }
121}
122
123const TargetRegisterClass *RISCVRegisterInfo::getConstrainedRegClassForOperand(
124 const MachineOperand &MO, const MachineRegisterInfo &MRI) const {
125 const RISCVSubtarget &STI = MRI.getMF().getSubtarget<RISCVSubtarget>();
126
127 const RegClassOrRegBank &RCOrRB = MRI.getRegClassOrRegBank(Reg: MO.getReg());
128 if (const RegisterBank *RB = dyn_cast<const RegisterBank *>(Val: RCOrRB))
129 return getRegClassForTypeOnBank(Ty: MRI.getType(Reg: MO.getReg()), RB: *RB,
130 Is64Bit: STI.is64Bit());
131
132 if (const auto *RC = dyn_cast<const TargetRegisterClass *>(Val: RCOrRB)) {
133 return getAllocatableClass(RC);
134 }
135
136 return nullptr;
137}
138
139const TargetRegisterClass *
140RISCVRegisterInfo::getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB,
141 bool Is64Bit) const {
142 if (RB.getID() == RISCV::GPRBRegBankID) {
143 if (Ty.getSizeInBits() <= 32 || (Is64Bit && Ty.getSizeInBits() == 64))
144 return &RISCV::GPRRegClass;
145 }
146
147 if (RB.getID() == RISCV::FPRBRegBankID) {
148 if (Ty.getSizeInBits() == 16)
149 return &RISCV::FPR16RegClass;
150 if (Ty.getSizeInBits() == 32)
151 return &RISCV::FPR32RegClass;
152 if (Ty.getSizeInBits() == 64)
153 return &RISCV::FPR64RegClass;
154 }
155
156 if (RB.getID() == RISCV::VRBRegBankID) {
157 if (Ty.getSizeInBits().getKnownMinValue() <= 64)
158 return &RISCV::VRRegClass;
159
160 if (Ty.getSizeInBits().getKnownMinValue() == 128)
161 return &RISCV::VRM2RegClass;
162
163 if (Ty.getSizeInBits().getKnownMinValue() == 256)
164 return &RISCV::VRM4RegClass;
165
166 if (Ty.getSizeInBits().getKnownMinValue() == 512)
167 return &RISCV::VRM8RegClass;
168 }
169
170 return nullptr;
171}
172
173BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
174 const RISCVFrameLowering *TFI = getFrameLowering(MF);
175 BitVector Reserved(getNumRegs());
176 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
177
178 for (size_t Reg = 0; Reg < getNumRegs(); Reg++) {
179 // Mark any GPRs requested to be reserved as such
180 if (Subtarget.isRegisterReservedByUser(i: Reg)) {
181 for (MCPhysReg Sub : subregs_inclusive(Reg))
182 markSuperRegs(RegisterSet&: Reserved, Reg: Sub);
183 }
184
185 // Mark all the registers defined as constant in TableGen as reserved.
186 if (isConstantPhysReg(PhysReg: Reg)) {
187 for (MCPhysReg Sub : subregs_inclusive(Reg))
188 markSuperRegs(RegisterSet&: Reserved, Reg: Sub);
189 }
190 }
191
192 // Use markSuperRegs to ensure any register aliases are also reserved
193 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::X2_H); // sp
194 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::X3_H); // gp
195 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::X4_H); // tp
196 if (TFI->hasFP(MF))
197 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::X8_H); // fp
198 // Reserve the base register if we need to realign the stack and allocate
199 // variable-sized objects at runtime.
200 if (TFI->hasBP(MF))
201 markSuperRegs(RegisterSet&: Reserved, Reg: RISCVABI::getBPReg()); // bp
202
203 // Additionally reserve dummy register used to form the register pair
204 // beginning with 'x0' for instructions that take register pairs.
205 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::DUMMY_REG_PAIR_WITH_X0);
206
207 // There are only 16 GPRs for RVE.
208 if (Subtarget.hasStdExtE())
209 for (MCPhysReg Reg = RISCV::X16_H; Reg <= RISCV::X31_H; Reg++)
210 markSuperRegs(RegisterSet&: Reserved, Reg);
211
212 // V registers for code generation. We handle them manually.
213 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::VL);
214 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::VTYPE);
215 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::VXSAT);
216 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::VXRM);
217
218 // Floating point environment registers.
219 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::FRM);
220 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::FFLAGS);
221
222 // SiFive VCIX state registers.
223 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::SF_VCIX_STATE);
224
225 if (MF.getFunction().getCallingConv() == CallingConv::GRAAL) {
226 if (Subtarget.hasStdExtE())
227 reportFatalUsageError(reason: "Graal reserved registers do not exist in RVE");
228 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::X23_H);
229 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::X27_H);
230 }
231
232 // Shadow stack pointer.
233 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::SSP);
234
235 // XSfmmbase
236 for (MCPhysReg Reg = RISCV::T0; Reg <= RISCV::T15; Reg++)
237 markSuperRegs(RegisterSet&: Reserved, Reg);
238
239 assert(checkAllSuperRegsMarked(Reserved));
240 return Reserved;
241}
242
243bool RISCVRegisterInfo::isAsmClobberable(const MachineFunction &MF,
244 MCRegister PhysReg) const {
245 return !MF.getSubtarget().isRegisterReservedByUser(R: PhysReg);
246}
247
248const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const {
249 return CSR_NoRegs_RegMask;
250}
251
252void RISCVRegisterInfo::adjustReg(MachineBasicBlock &MBB,
253 MachineBasicBlock::iterator II,
254 const DebugLoc &DL, Register DestReg,
255 Register SrcReg, StackOffset Offset,
256 MachineInstr::MIFlag Flag,
257 MaybeAlign RequiredAlign) const {
258
259 if (DestReg == SrcReg && !Offset.getFixed() && !Offset.getScalable())
260 return;
261
262 MachineFunction &MF = *MBB.getParent();
263 MachineRegisterInfo &MRI = MF.getRegInfo();
264 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
265 const RISCVInstrInfo *TII = ST.getInstrInfo();
266
267 // Optimize compile time offset case
268 if (Offset.getScalable()) {
269 if (auto VLEN = ST.getRealVLen()) {
270 // 1. Multiply the number of v-slots by the (constant) length of register
271 const int64_t VLENB = *VLEN / 8;
272 assert(Offset.getScalable() % RISCV::RVVBytesPerBlock == 0 &&
273 "Reserve the stack by the multiple of one vector size.");
274 const int64_t NumOfVReg = Offset.getScalable() / 8;
275 const int64_t FixedOffset = NumOfVReg * VLENB;
276 if (!isInt<32>(x: FixedOffset)) {
277 // This check might also need to be updated to 64bit.
278 // However mulImm() still assumes 32bit. For now only support fixed
279 // 64bit frame offsets, since scalable offsets would require the number
280 // of spilled registers to exceed 2^31, which is unlikely.
281 reportFatalUsageError(reason: "Scalable frame size outside of the signed "
282 "32-bit range not supported");
283 }
284 Offset = StackOffset::getFixed(Fixed: FixedOffset + Offset.getFixed());
285 }
286 }
287
288 bool KillSrcReg = false;
289
290 if (Offset.getScalable()) {
291 unsigned ScalableAdjOpc = RISCV::ADD;
292 int64_t ScalableValue = Offset.getScalable();
293 if (ScalableValue < 0) {
294 ScalableValue = -ScalableValue;
295 ScalableAdjOpc = RISCV::SUB;
296 }
297 // Get vlenb and multiply vlen with the number of vector registers.
298 Register ScratchReg = DestReg;
299 if (DestReg == SrcReg)
300 ScratchReg = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
301
302 assert(ScalableValue > 0 && "There is no need to get VLEN scaled value.");
303 assert(ScalableValue % RISCV::RVVBytesPerBlock == 0 &&
304 "Reserve the stack by the multiple of one vector size.");
305 assert(isInt<32>(ScalableValue / RISCV::RVVBytesPerBlock) &&
306 "Expect the number of vector registers within 32-bits.");
307 uint32_t NumOfVReg = ScalableValue / RISCV::RVVBytesPerBlock;
308 // Only use vsetvli rather than vlenb if adjusting in the prologue or
309 // epilogue, otherwise it may disturb the VTYPE and VL status.
310 bool IsPrologueOrEpilogue =
311 Flag == MachineInstr::FrameSetup || Flag == MachineInstr::FrameDestroy;
312 bool UseVsetvliRatherThanVlenb =
313 IsPrologueOrEpilogue && ST.preferVsetvliOverReadVLENB();
314 if (UseVsetvliRatherThanVlenb && (NumOfVReg == 1 || NumOfVReg == 2 ||
315 NumOfVReg == 4 || NumOfVReg == 8)) {
316 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::PseudoReadVLENBViaVSETVLIX0),
317 DestReg: ScratchReg)
318 .addImm(Val: NumOfVReg)
319 .setMIFlag(Flag);
320 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: ScalableAdjOpc), DestReg)
321 .addReg(RegNo: SrcReg)
322 .addReg(RegNo: ScratchReg, Flags: RegState::Kill)
323 .setMIFlag(Flag);
324 } else {
325 if (UseVsetvliRatherThanVlenb)
326 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::PseudoReadVLENBViaVSETVLIX0),
327 DestReg: ScratchReg)
328 .addImm(Val: 1)
329 .setMIFlag(Flag);
330 else
331 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::PseudoReadVLENB), DestReg: ScratchReg)
332 .setMIFlag(Flag);
333
334 if (ScalableAdjOpc == RISCV::ADD && ST.hasStdExtZba() &&
335 (NumOfVReg == 2 || NumOfVReg == 4 || NumOfVReg == 8)) {
336 unsigned Opc = NumOfVReg == 2
337 ? RISCV::SH1ADD
338 : (NumOfVReg == 4 ? RISCV::SH2ADD : RISCV::SH3ADD);
339 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: Opc), DestReg)
340 .addReg(RegNo: ScratchReg, Flags: RegState::Kill)
341 .addReg(RegNo: SrcReg)
342 .setMIFlag(Flag);
343 } else {
344 TII->mulImm(MF, MBB, II, DL, DestReg: ScratchReg, Amt: NumOfVReg, Flag);
345 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: ScalableAdjOpc), DestReg)
346 .addReg(RegNo: SrcReg)
347 .addReg(RegNo: ScratchReg, Flags: RegState::Kill)
348 .setMIFlag(Flag);
349 }
350 }
351 SrcReg = DestReg;
352 KillSrcReg = true;
353 }
354
355 int64_t Val = Offset.getFixed();
356 if (DestReg == SrcReg && Val == 0)
357 return;
358
359 const uint64_t Align = RequiredAlign.valueOrOne().value();
360
361 if (isInt<12>(x: Val)) {
362 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::ADDI), DestReg)
363 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrcReg))
364 .addImm(Val)
365 .setMIFlag(Flag);
366 return;
367 }
368
369 // Use the QC_E_ADDI instruction from the Xqcilia extension that can take a
370 // signed 26-bit immediate.
371 if (ST.hasVendorXqcilia() && isInt<26>(x: Val)) {
372 // The one case where using this instruction is sub-optimal is if Val can be
373 // materialized with a single compressible LUI and following add/sub is also
374 // compressible. Avoid doing this if that is the case.
375 int Hi20 = (Val & 0xFFFFF000) >> 12;
376 bool IsCompressLUI =
377 ((Val & 0xFFF) == 0) && (Hi20 != 0) &&
378 (isUInt<5>(x: Hi20) || (Hi20 >= 0xfffe0 && Hi20 <= 0xfffff));
379 bool IsCompressAddSub =
380 (SrcReg == DestReg) &&
381 ((Val > 0 && RISCV::GPRNoX0RegClass.contains(Reg: SrcReg)) ||
382 (Val < 0 && RISCV::GPRCRegClass.contains(Reg: SrcReg)));
383
384 if (!(IsCompressLUI && IsCompressAddSub)) {
385 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::QC_E_ADDI), DestReg)
386 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrcReg))
387 .addImm(Val)
388 .setMIFlag(Flag);
389 return;
390 }
391 }
392
393 // Try to split the offset across two ADDIs. We need to keep the intermediate
394 // result aligned after each ADDI. We need to determine the maximum value we
395 // can put in each ADDI. In the negative direction, we can use -2048 which is
396 // always sufficiently aligned. In the positive direction, we need to find the
397 // largest 12-bit immediate that is aligned. Exclude -4096 since it can be
398 // created with LUI.
399 assert(Align < 2048 && "Required alignment too large");
400 int64_t MaxPosAdjStep = 2048 - Align;
401 if (Val > -4096 && Val <= (2 * MaxPosAdjStep)) {
402 int64_t FirstAdj = Val < 0 ? -2048 : MaxPosAdjStep;
403 Val -= FirstAdj;
404 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::ADDI), DestReg)
405 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrcReg))
406 .addImm(Val: FirstAdj)
407 .setMIFlag(Flag);
408 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::ADDI), DestReg)
409 .addReg(RegNo: DestReg, Flags: RegState::Kill)
410 .addImm(Val)
411 .setMIFlag(Flag);
412 return;
413 }
414
415 // Use shNadd if doing so lets us materialize a 12 bit immediate with a single
416 // instruction. This saves 1 instruction over the full lui/addi+add fallback
417 // path. We avoid anything which can be done with a single lui as it might
418 // be compressible. Note that the sh1add case is fully covered by the 2x addi
419 // case just above and is thus omitted.
420 if (ST.hasStdExtZba() && (Val & 0xFFF) != 0) {
421 unsigned Opc = 0;
422 if (isShiftedInt<12, 3>(x: Val)) {
423 Opc = RISCV::SH3ADD;
424 Val = Val >> 3;
425 } else if (isShiftedInt<12, 2>(x: Val)) {
426 Opc = RISCV::SH2ADD;
427 Val = Val >> 2;
428 }
429 if (Opc) {
430 Register ScratchReg = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
431 TII->movImm(MBB, MBBI: II, DL, DstReg: ScratchReg, Val, Flag);
432 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: Opc), DestReg)
433 .addReg(RegNo: ScratchReg, Flags: RegState::Kill)
434 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrcReg))
435 .setMIFlag(Flag);
436 return;
437 }
438 }
439
440 unsigned Opc = RISCV::ADD;
441 if (Val < 0) {
442 Val = -Val;
443 Opc = RISCV::SUB;
444 }
445
446 Register ScratchReg = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
447 TII->movImm(MBB, MBBI: II, DL, DstReg: ScratchReg, Val, Flag);
448 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: Opc), DestReg)
449 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrcReg))
450 .addReg(RegNo: ScratchReg, Flags: RegState::Kill)
451 .setMIFlag(Flag);
452}
453
454static std::tuple<RISCVVType::VLMUL, const TargetRegisterClass &, unsigned>
455getSpillReloadInfo(unsigned NumRemaining, uint16_t RegEncoding, bool IsSpill) {
456 if (NumRemaining >= 8 && RegEncoding % 8 == 0)
457 return {RISCVVType::LMUL_8, RISCV::VRM8RegClass,
458 IsSpill ? RISCV::VS8R_V : RISCV::VL8RE8_V};
459 if (NumRemaining >= 4 && RegEncoding % 4 == 0)
460 return {RISCVVType::LMUL_4, RISCV::VRM4RegClass,
461 IsSpill ? RISCV::VS4R_V : RISCV::VL4RE8_V};
462 if (NumRemaining >= 2 && RegEncoding % 2 == 0)
463 return {RISCVVType::LMUL_2, RISCV::VRM2RegClass,
464 IsSpill ? RISCV::VS2R_V : RISCV::VL2RE8_V};
465 return {RISCVVType::LMUL_1, RISCV::VRRegClass,
466 IsSpill ? RISCV::VS1R_V : RISCV::VL1RE8_V};
467}
468
469// Split a VSPILLx_Mx/VSPILLx_Mx pseudo into multiple whole register stores
470// separated by LMUL*VLENB bytes.
471void RISCVRegisterInfo::lowerSegmentSpillReload(MachineBasicBlock::iterator II,
472 bool IsSpill) const {
473 DebugLoc DL = II->getDebugLoc();
474 MachineBasicBlock &MBB = *II->getParent();
475 MachineFunction &MF = *MBB.getParent();
476 MachineRegisterInfo &MRI = MF.getRegInfo();
477 const RISCVSubtarget &STI = MF.getSubtarget<RISCVSubtarget>();
478 const TargetInstrInfo *TII = STI.getInstrInfo();
479 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
480
481 auto ZvlssegInfo = RISCV::isRVVSpillForZvlsseg(Opcode: II->getOpcode());
482 unsigned NF = ZvlssegInfo->first;
483 unsigned LMUL = ZvlssegInfo->second;
484 unsigned NumRegs = NF * LMUL;
485 assert(NumRegs <= 8 && "Invalid NF/LMUL combinations.");
486
487 Register Reg = II->getOperand(i: 0).getReg();
488 uint16_t RegEncoding = TRI->getEncodingValue(Reg);
489 Register Base = II->getOperand(i: 1).getReg();
490 bool IsBaseKill = II->getOperand(i: 1).isKill();
491 Register NewBase = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
492
493 auto *OldMMO = *(II->memoperands_begin());
494 LocationSize OldLoc = OldMMO->getSize();
495 assert(OldLoc.isPrecise() && OldLoc.getValue().isKnownMultipleOf(NF));
496 TypeSize VRegSize = OldLoc.getValue().divideCoefficientBy(RHS: NumRegs);
497
498 Register VLENB = 0;
499 unsigned VLENBShift = 0;
500 unsigned PrevHandledNum = 0;
501 unsigned I = 0;
502 while (I != NumRegs) {
503 auto [LMulHandled, RegClass, Opcode] =
504 getSpillReloadInfo(NumRemaining: NumRegs - I, RegEncoding, IsSpill);
505 auto [RegNumHandled, _] = RISCVVType::decodeVLMUL(VLMul: LMulHandled);
506 bool IsLast = I + RegNumHandled == NumRegs;
507 if (PrevHandledNum) {
508 Register Step;
509 // Optimize for constant VLEN.
510 if (auto VLEN = STI.getRealVLen()) {
511 int64_t Offset = *VLEN / 8 * PrevHandledNum;
512 Step = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
513 STI.getInstrInfo()->movImm(MBB, MBBI: II, DL, DstReg: Step, Val: Offset);
514 } else {
515 if (!VLENB) {
516 VLENB = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
517 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::PseudoReadVLENB), DestReg: VLENB);
518 }
519 uint32_t ShiftAmount = Log2_32(Value: PrevHandledNum);
520 // To avoid using an extra register, we shift the VLENB register and
521 // remember how much it has been shifted. We can then use relative
522 // shifts to adjust to the desired shift amount.
523 if (VLENBShift > ShiftAmount) {
524 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::SRLI), DestReg: VLENB)
525 .addReg(RegNo: VLENB, Flags: RegState::Kill)
526 .addImm(Val: VLENBShift - ShiftAmount);
527 } else if (VLENBShift < ShiftAmount) {
528 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::SLLI), DestReg: VLENB)
529 .addReg(RegNo: VLENB, Flags: RegState::Kill)
530 .addImm(Val: ShiftAmount - VLENBShift);
531 }
532 VLENBShift = ShiftAmount;
533 Step = VLENB;
534 }
535
536 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::ADD), DestReg: NewBase)
537 .addReg(RegNo: Base, Flags: getKillRegState(B: I != 0 || IsBaseKill))
538 .addReg(RegNo: Step, Flags: getKillRegState(B: Step != VLENB || IsLast));
539 Base = NewBase;
540 }
541
542 MCRegister ActualReg = findVRegWithEncoding(RegClass, Encoding: RegEncoding);
543 MachineInstrBuilder MIB =
544 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode))
545 .addReg(RegNo: ActualReg, Flags: getDefRegState(B: !IsSpill))
546 .addReg(RegNo: Base, Flags: getKillRegState(B: IsLast))
547 .addMemOperand(MMO: MF.getMachineMemOperand(MMO: OldMMO, Offset: OldMMO->getOffset(),
548 Size: VRegSize * RegNumHandled));
549
550 // Adding implicit-use of super register to describe we are using part of
551 // super register, that prevents machine verifier complaining when part of
552 // subreg is undef, see comment in MachineVerifier::checkLiveness for more
553 // detail.
554 if (IsSpill)
555 MIB.addReg(RegNo: Reg, Flags: RegState::Implicit);
556
557 PrevHandledNum = RegNumHandled;
558 RegEncoding += RegNumHandled;
559 I += RegNumHandled;
560 }
561 II->eraseFromParent();
562}
563
564bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
565 int SPAdj, unsigned FIOperandNum,
566 RegScavenger *RS) const {
567 assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
568
569 MachineInstr &MI = *II;
570 MachineFunction &MF = *MI.getParent()->getParent();
571 MachineRegisterInfo &MRI = MF.getRegInfo();
572 bool Is64Bit = MF.getSubtarget<RISCVSubtarget>().is64Bit();
573 DebugLoc DL = MI.getDebugLoc();
574
575 int FrameIndex = MI.getOperand(i: FIOperandNum).getIndex();
576 Register FrameReg;
577 StackOffset Offset =
578 getFrameLowering(MF)->getFrameIndexReference(MF, FI: FrameIndex, FrameReg);
579 bool IsRVVSpill = RISCV::isRVVSpill(MI);
580 if (!IsRVVSpill)
581 Offset += StackOffset::getFixed(Fixed: MI.getOperand(i: FIOperandNum + 1).getImm());
582
583 if (!Is64Bit && !isInt<32>(x: Offset.getFixed())) {
584 reportFatalUsageError(reason: "Frame offsets outside of the signed 32-bit range "
585 "not supported on RV32");
586 }
587
588 if (!IsRVVSpill) {
589 int64_t Val = Offset.getFixed();
590 int64_t Lo12 = SignExtend64<12>(x: Val);
591 int64_t Lo26 = SignExtend64<26>(x: Val);
592 unsigned Opc = MI.getOpcode();
593
594 if (Opc == RISCV::ADDI && !isInt<12>(x: Val)) {
595 // We chose to emit the canonical immediate sequence rather than folding
596 // the offset into the using add under the theory that doing so doesn't
597 // save dynamic instruction count and some target may fuse the canonical
598 // 32 bit immediate sequence. We still need to clear the portion of the
599 // offset encoded in the immediate.
600 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: 0);
601 } else if ((Opc == RISCV::PREFETCH_I || Opc == RISCV::PREFETCH_R ||
602 Opc == RISCV::PREFETCH_W) &&
603 (Lo12 & 0b11111) != 0) {
604 // Prefetch instructions require the offset to be 32 byte aligned.
605 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: 0);
606 } else if (Opc == RISCV::MIPS_PREF && !isUInt<9>(x: Val)) {
607 // MIPS Prefetch instructions require the offset to be 9 bits encoded.
608 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: 0);
609 } else if ((Opc == RISCV::PseudoRV32ZdinxLD ||
610 Opc == RISCV::PseudoRV32ZdinxSD ||
611 Opc == RISCV::PseudoLD_RV32_OPT ||
612 Opc == RISCV::PseudoSD_RV32_OPT) &&
613 Lo12 >= 2044) {
614 // This instruction will/might be split into 2 instructions. The second
615 // instruction will add 4 to the immediate. If that would overflow 12
616 // bits, we can't fold the offset.
617 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: 0);
618 } else if (Opc == RISCV::QC_E_ADDI || RISCVInstrInfo::isBaseQCLoad(MI) ||
619 RISCVInstrInfo::isBaseQCStore(MI)) {
620 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: Lo26);
621 Offset = StackOffset::get(Fixed: (uint64_t)Val - (uint64_t)Lo26,
622 Scalable: Offset.getScalable());
623 } else {
624 // We can encode an add with 12 bit signed immediate in the immediate
625 // operand of our user instruction. As a result, the remaining
626 // offset can by construction, at worst, a LUI and a ADD.
627 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: Lo12);
628 Offset = StackOffset::get(Fixed: (uint64_t)Val - (uint64_t)Lo12,
629 Scalable: Offset.getScalable());
630 }
631 }
632
633 if (Offset.getScalable() || Offset.getFixed()) {
634 Register DestReg;
635 if (MI.getOpcode() == RISCV::ADDI)
636 DestReg = MI.getOperand(i: 0).getReg();
637 else
638 DestReg = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
639 adjustReg(MBB&: *II->getParent(), II, DL, DestReg, SrcReg: FrameReg, Offset,
640 Flag: MachineInstr::NoFlags, RequiredAlign: std::nullopt);
641 MI.getOperand(i: FIOperandNum).ChangeToRegister(Reg: DestReg, /*IsDef*/isDef: false,
642 /*IsImp*/isImp: false,
643 /*IsKill*/isKill: true);
644 } else {
645 MI.getOperand(i: FIOperandNum).ChangeToRegister(Reg: FrameReg, /*IsDef*/isDef: false,
646 /*IsImp*/isImp: false,
647 /*IsKill*/isKill: false);
648 }
649
650 // If after materializing the adjustment, we have a pointless ADDI, remove it
651 if (MI.getOpcode() == RISCV::ADDI &&
652 MI.getOperand(i: 0).getReg() == MI.getOperand(i: 1).getReg() &&
653 MI.getOperand(i: 2).getImm() == 0) {
654 MI.eraseFromParent();
655 return true;
656 }
657
658 // Handle spill/fill of synthetic register classes for segment operations to
659 // ensure correctness in the edge case one gets spilled.
660 switch (MI.getOpcode()) {
661 case RISCV::PseudoVSPILL2_M1:
662 case RISCV::PseudoVSPILL2_M2:
663 case RISCV::PseudoVSPILL2_M4:
664 case RISCV::PseudoVSPILL3_M1:
665 case RISCV::PseudoVSPILL3_M2:
666 case RISCV::PseudoVSPILL4_M1:
667 case RISCV::PseudoVSPILL4_M2:
668 case RISCV::PseudoVSPILL5_M1:
669 case RISCV::PseudoVSPILL6_M1:
670 case RISCV::PseudoVSPILL7_M1:
671 case RISCV::PseudoVSPILL8_M1:
672 lowerSegmentSpillReload(II, /*IsSpill=*/true);
673 return true;
674 case RISCV::PseudoVRELOAD2_M1:
675 case RISCV::PseudoVRELOAD2_M2:
676 case RISCV::PseudoVRELOAD2_M4:
677 case RISCV::PseudoVRELOAD3_M1:
678 case RISCV::PseudoVRELOAD3_M2:
679 case RISCV::PseudoVRELOAD4_M1:
680 case RISCV::PseudoVRELOAD4_M2:
681 case RISCV::PseudoVRELOAD5_M1:
682 case RISCV::PseudoVRELOAD6_M1:
683 case RISCV::PseudoVRELOAD7_M1:
684 case RISCV::PseudoVRELOAD8_M1:
685 lowerSegmentSpillReload(II, /*IsSpill=*/false);
686 return true;
687 }
688
689 return false;
690}
691
692bool RISCVRegisterInfo::requiresVirtualBaseRegisters(
693 const MachineFunction &MF) const {
694 return true;
695}
696
697// Returns true if the instruction's frame index reference would be better
698// served by a base register other than FP or SP.
699// Used by LocalStackSlotAllocation pass to determine which frame index
700// references it should create new base registers for.
701bool RISCVRegisterInfo::needsFrameBaseReg(MachineInstr *MI,
702 int64_t Offset) const {
703 unsigned FIOperandNum = 0;
704 for (; !MI->getOperand(i: FIOperandNum).isFI(); FIOperandNum++)
705 assert(FIOperandNum < MI->getNumOperands() &&
706 "Instr doesn't have FrameIndex operand");
707
708 // For RISC-V, The machine instructions that include a FrameIndex operand
709 // are load/store, ADDI instructions.
710 unsigned MIFrm = RISCVII::getFormat(TSFlags: MI->getDesc().TSFlags);
711 if (MIFrm != RISCVII::InstFormatI && MIFrm != RISCVII::InstFormatS)
712 return false;
713 // We only generate virtual base registers for loads and stores, so
714 // return false for everything else.
715 if (!MI->mayLoad() && !MI->mayStore())
716 return false;
717
718 const MachineFunction &MF = *MI->getMF();
719 const MachineFrameInfo &MFI = MF.getFrameInfo();
720 const RISCVFrameLowering *TFI = getFrameLowering(MF);
721 const MachineRegisterInfo &MRI = MF.getRegInfo();
722
723 if (TFI->hasFP(MF) && !shouldRealignStack(MF)) {
724 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
725 // Estimate the stack size used to store callee saved registers(
726 // excludes reserved registers).
727 unsigned CalleeSavedSize = 0;
728 for (const MCPhysReg *R = MRI.getCalleeSavedRegs(); MCPhysReg Reg = *R;
729 ++R) {
730 if (Subtarget.isRegisterReservedByUser(i: Reg))
731 continue;
732
733 if (RISCV::GPRRegClass.contains(Reg))
734 CalleeSavedSize += getSpillSize(RC: RISCV::GPRRegClass);
735 else if (RISCV::FPR64RegClass.contains(Reg))
736 CalleeSavedSize += getSpillSize(RC: RISCV::FPR64RegClass);
737 else if (RISCV::FPR32RegClass.contains(Reg))
738 CalleeSavedSize += getSpillSize(RC: RISCV::FPR32RegClass);
739 // Ignore vector registers.
740 }
741
742 int64_t MaxFPOffset = Offset - CalleeSavedSize;
743 if (isFrameOffsetLegal(MI, BaseReg: RISCV::X8, Offset: MaxFPOffset))
744 return false;
745
746 // If the FP-relative offset doesn't fit, fall through to check the
747 // SP-relative offset. getFrameIndexReference may select SP over FP when
748 // the SP offset fits in the compressed instruction immediate range, so a
749 // base register might not be needed.
750 }
751
752 // Assume 128 bytes spill slots size to estimate the maximum possible
753 // offset relative to the stack pointer.
754 // FIXME: The 128 is copied from ARM. We should run some statistics and pick a
755 // real one for RISC-V.
756 int64_t MaxSPOffset = Offset + 128;
757 MaxSPOffset += MFI.getLocalFrameSize();
758 return !isFrameOffsetLegal(MI, BaseReg: RISCV::X2, Offset: MaxSPOffset);
759}
760
761// Determine whether a given base register plus offset immediate is
762// encodable to resolve a frame index.
763bool RISCVRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
764 Register BaseReg,
765 int64_t Offset) const {
766 unsigned FIOperandNum = 0;
767 while (!MI->getOperand(i: FIOperandNum).isFI()) {
768 FIOperandNum++;
769 assert(FIOperandNum < MI->getNumOperands() &&
770 "Instr does not have a FrameIndex operand!");
771 }
772
773 Offset += getFrameIndexInstrOffset(MI, Idx: FIOperandNum);
774 return isInt<12>(x: Offset);
775}
776
777// Insert defining instruction(s) for a pointer to FrameIdx before
778// insertion point I.
779// Return materialized frame pointer.
780Register RISCVRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
781 int FrameIdx,
782 int64_t Offset) const {
783 MachineBasicBlock::iterator MBBI = MBB->begin();
784 DebugLoc DL;
785 if (MBBI != MBB->end())
786 DL = MBBI->getDebugLoc();
787 MachineFunction *MF = MBB->getParent();
788 MachineRegisterInfo &MFI = MF->getRegInfo();
789 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
790
791 Register BaseReg = MFI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
792 BuildMI(BB&: *MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: RISCV::ADDI), DestReg: BaseReg)
793 .addFrameIndex(Idx: FrameIdx)
794 .addImm(Val: Offset);
795 return BaseReg;
796}
797
798// Resolve a frame index operand of an instruction to reference the
799// indicated base register plus offset instead.
800void RISCVRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg,
801 int64_t Offset) const {
802 unsigned FIOperandNum = 0;
803 while (!MI.getOperand(i: FIOperandNum).isFI()) {
804 FIOperandNum++;
805 assert(FIOperandNum < MI.getNumOperands() &&
806 "Instr does not have a FrameIndex operand!");
807 }
808
809 Offset += getFrameIndexInstrOffset(MI: &MI, Idx: FIOperandNum);
810 // FrameIndex Operands are always represented as a
811 // register followed by an immediate.
812 MI.getOperand(i: FIOperandNum).ChangeToRegister(Reg: BaseReg, isDef: false);
813 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: Offset);
814}
815
816// Get the offset from the referenced frame index in the instruction,
817// if there is one.
818int64_t RISCVRegisterInfo::getFrameIndexInstrOffset(const MachineInstr *MI,
819 int Idx) const {
820 assert((RISCVII::getFormat(MI->getDesc().TSFlags) == RISCVII::InstFormatI ||
821 RISCVII::getFormat(MI->getDesc().TSFlags) == RISCVII::InstFormatS) &&
822 "The MI must be I or S format.");
823 assert(MI->getOperand(Idx).isFI() && "The Idx'th operand of MI is not a "
824 "FrameIndex operand");
825 return MI->getOperand(i: Idx + 1).getImm();
826}
827
828Register RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
829 const TargetFrameLowering *TFI = getFrameLowering(MF);
830 return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
831}
832
833bool RISCVRegisterInfo::isArgumentRegister(const MachineFunction &MF,
834 MCRegister Reg) const {
835 auto const &STI = MF.getSubtarget<RISCVSubtarget>();
836 const RISCVRegisterInfo *TRI = STI.getRegisterInfo();
837
838 if (TRI->isGeneralPurposeRegister(MF, PhysReg: Reg))
839 return llvm::is_contained(Range: RISCV::getArgGPRs(STI), Element: Reg);
840
841 if (TRI->isFPRegister(Reg))
842 return llvm::is_contained(Range: RISCV::getArgFPRs(STI), Element: Reg);
843
844 return false;
845}
846
847StringRef RISCVRegisterInfo::getRegAsmName(MCRegister Reg) const {
848 if (Reg == RISCV::SF_VCIX_STATE)
849 return "sf.vcix_state";
850 return TargetRegisterInfo::getRegAsmName(Reg);
851}
852
853const uint32_t *
854RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF,
855 CallingConv::ID CC) const {
856 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
857
858 if (CC == CallingConv::GHC)
859 return CSR_NoRegs_RegMask;
860 RISCVABI::ABI ABI = Subtarget.getTargetABI();
861 if (CC == CallingConv::PreserveMost) {
862 if (ABI == RISCVABI::ABI_ILP32E || ABI == RISCVABI::ABI_LP64E)
863 return CSR_RT_MostRegs_RVE_RegMask;
864 return CSR_RT_MostRegs_RegMask;
865 }
866 switch (ABI) {
867 default:
868 llvm_unreachable("Unrecognized ABI");
869 case RISCVABI::ABI_ILP32E:
870 case RISCVABI::ABI_LP64E:
871 return CSR_ILP32E_LP64E_RegMask;
872 case RISCVABI::ABI_ILP32:
873 case RISCVABI::ABI_LP64:
874 if (CC == CallingConv::RISCV_VectorCall)
875 return CSR_ILP32_LP64_V_RegMask;
876 return CSR_ILP32_LP64_RegMask;
877 case RISCVABI::ABI_ILP32F:
878 case RISCVABI::ABI_LP64F:
879 if (CC == CallingConv::RISCV_VectorCall)
880 return CSR_ILP32F_LP64F_V_RegMask;
881 return CSR_ILP32F_LP64F_RegMask;
882 case RISCVABI::ABI_ILP32D:
883 case RISCVABI::ABI_LP64D:
884 if (CC == CallingConv::RISCV_VectorCall)
885 return CSR_ILP32D_LP64D_V_RegMask;
886 return CSR_ILP32D_LP64D_RegMask;
887 }
888}
889
890const TargetRegisterClass *
891RISCVRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
892 const MachineFunction &) const {
893 if (RC == &RISCV::VMV0RegClass)
894 return &RISCV::VRRegClass;
895 if (RC == &RISCV::VRNoV0RegClass)
896 return &RISCV::VRRegClass;
897 if (RC == &RISCV::VRM2NoV0RegClass)
898 return &RISCV::VRM2RegClass;
899 if (RC == &RISCV::VRM4NoV0RegClass)
900 return &RISCV::VRM4RegClass;
901 if (RC == &RISCV::VRM8NoV0RegClass)
902 return &RISCV::VRM8RegClass;
903 return RC;
904}
905
906void RISCVRegisterInfo::getOffsetOpcodes(const StackOffset &Offset,
907 SmallVectorImpl<uint64_t> &Ops) const {
908 // VLENB is the length of a vector register in bytes. We use <vscale x 8 x i8>
909 // to represent one vector register. The dwarf offset is
910 // VLENB * scalable_offset / 8.
911 assert(Offset.getScalable() % 8 == 0 && "Invalid frame offset");
912
913 // Add fixed-sized offset using existing DIExpression interface.
914 DIExpression::appendOffset(Ops, Offset: Offset.getFixed());
915
916 unsigned VLENB = getDwarfRegNum(Reg: RISCV::VLENB, isEH: true);
917 int64_t VLENBSized = Offset.getScalable() / 8;
918 if (VLENBSized > 0) {
919 Ops.push_back(Elt: dwarf::DW_OP_constu);
920 Ops.push_back(Elt: VLENBSized);
921 Ops.append(IL: {dwarf::DW_OP_bregx, VLENB, 0ULL});
922 Ops.push_back(Elt: dwarf::DW_OP_mul);
923 Ops.push_back(Elt: dwarf::DW_OP_plus);
924 } else if (VLENBSized < 0) {
925 Ops.push_back(Elt: dwarf::DW_OP_constu);
926 Ops.push_back(Elt: -VLENBSized);
927 Ops.append(IL: {dwarf::DW_OP_bregx, VLENB, 0ULL});
928 Ops.push_back(Elt: dwarf::DW_OP_mul);
929 Ops.push_back(Elt: dwarf::DW_OP_minus);
930 }
931}
932
933unsigned
934RISCVRegisterInfo::getRegisterCostTableIndex(const MachineFunction &MF) const {
935 // Set CostPerUse to 1 only when optimizing for size and RVC exists.
936 return MF.getFunction().hasOptSize() &&
937 MF.getSubtarget<RISCVSubtarget>().hasStdExtZca() &&
938 !DisableCostPerUse
939 ? 1
940 : 0;
941}
942
943float RISCVRegisterInfo::getSpillWeightScaleFactor(
944 const TargetRegisterClass *RC) const {
945 return getRegClassWeight(RC).RegWeight;
946}
947
948// Add two address hints to improve chances of being able to use a compressed
949// instruction.
950bool RISCVRegisterInfo::getRegAllocationHints(
951 Register VirtReg, ArrayRef<MCPhysReg> Order,
952 SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF,
953 const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
954 const MachineRegisterInfo *MRI = &MF.getRegInfo();
955 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
956
957 // Handle RegPairEven/RegPairOdd hints for Zilsd register pairs
958 std::pair<unsigned, Register> Hint = MRI->getRegAllocationHint(VReg: VirtReg);
959 unsigned HintType = Hint.first;
960 Register Partner = Hint.second;
961
962 MCRegister TargetReg;
963 if (HintType == RISCVRI::RegPairEven || HintType == RISCVRI::RegPairOdd) {
964 // Check if we want the even or odd register of a consecutive pair
965 bool WantOdd = (HintType == RISCVRI::RegPairOdd);
966
967 // First priority: Check if partner is already allocated
968 if (Partner.isVirtual() && VRM && VRM->hasPhys(virtReg: Partner)) {
969 MCRegister PartnerPhys = VRM->getPhys(virtReg: Partner);
970 // Calculate the exact register we need for consecutive pairing
971 TargetReg = PartnerPhys.id() + (WantOdd ? 1 : -1);
972
973 // Verify it's valid and available
974 if (RISCV::GPRRegClass.contains(Reg: TargetReg) &&
975 is_contained(Range&: Order, Element: TargetReg))
976 Hints.push_back(Elt: TargetReg.id());
977 }
978
979 // Second priority: Try to find consecutive register pairs in the allocation
980 // order
981 for (MCPhysReg PhysReg : Order) {
982 // Don't add the hint if we already added above.
983 if (TargetReg == PhysReg)
984 continue;
985
986 unsigned RegNum = getEncodingValue(Reg: PhysReg);
987 // Check if this register matches the even/odd requirement
988 bool IsOdd = (RegNum % 2 != 0);
989
990 // Don't provide hints that are paired to a reserved register.
991 MCRegister Paired = PhysReg + (IsOdd ? -1 : 1);
992 if (WantOdd == IsOdd && !MRI->isReserved(PhysReg: Paired))
993 Hints.push_back(Elt: PhysReg);
994 }
995 }
996
997 bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
998 VirtReg, Order, Hints, MF, VRM, Matrix);
999
1000 if (!VRM || DisableRegAllocHints)
1001 return BaseImplRetVal;
1002
1003 // Add any two address hints after any copy hints.
1004 SmallSet<Register, 4> TwoAddrHints;
1005
1006 auto tryAddHint = [&](const MachineOperand &VRRegMO, const MachineOperand &MO,
1007 bool NeedGPRC) -> void {
1008 Register Reg = MO.getReg();
1009 Register PhysReg = Reg.isPhysical() ? Reg : Register(VRM->getPhys(virtReg: Reg));
1010 // TODO: Support GPRPair subregisters? Need to be careful with even/odd
1011 // registers. If the virtual register is an odd register of a pair and the
1012 // physical register is even (or vice versa), we should not add the hint.
1013 if (PhysReg && (!NeedGPRC || RISCV::GPRCRegClass.contains(Reg: PhysReg)) &&
1014 !MO.getSubReg() && !VRRegMO.getSubReg()) {
1015 if (!MRI->isReserved(PhysReg) && !is_contained(Range&: Hints, Element: PhysReg))
1016 TwoAddrHints.insert(V: PhysReg);
1017 }
1018 };
1019
1020 // This is all of the compressible binary instructions. If an instruction
1021 // needs GPRC register class operands \p NeedGPRC will be set to true.
1022 auto isCompressible = [&Subtarget](const MachineInstr &MI, bool &NeedGPRC) {
1023 NeedGPRC = false;
1024 switch (MI.getOpcode()) {
1025 default:
1026 return false;
1027 case RISCV::AND:
1028 case RISCV::OR:
1029 case RISCV::XOR:
1030 case RISCV::SUB:
1031 case RISCV::ADDW:
1032 case RISCV::SUBW:
1033 NeedGPRC = true;
1034 return true;
1035 case RISCV::ANDI: {
1036 NeedGPRC = true;
1037 if (!MI.getOperand(i: 2).isImm())
1038 return false;
1039 int64_t Imm = MI.getOperand(i: 2).getImm();
1040 if (isInt<6>(x: Imm))
1041 return true;
1042 // c.zext.b
1043 return Subtarget.hasStdExtZcb() && Imm == 255;
1044 }
1045 case RISCV::SRAI:
1046 case RISCV::SRLI:
1047 NeedGPRC = true;
1048 return true;
1049 case RISCV::ADD:
1050 case RISCV::SLLI:
1051 return true;
1052 case RISCV::ADDI:
1053 case RISCV::ADDIW:
1054 return MI.getOperand(i: 2).isImm() && isInt<6>(x: MI.getOperand(i: 2).getImm());
1055 case RISCV::MUL:
1056 // c.mul
1057 NeedGPRC = true;
1058 return Subtarget.hasStdExtZcb();
1059 case RISCV::SEXT_B:
1060 case RISCV::SEXT_H:
1061 case RISCV::ZEXT_H_RV32:
1062 case RISCV::ZEXT_H_RV64:
1063 // c.sext.b, c.sext.h, c.zext.h
1064 NeedGPRC = true;
1065 return Subtarget.hasStdExtZcb() && Subtarget.hasStdExtZbb();
1066 case RISCV::ADD_UW:
1067 // c.zext.w
1068 NeedGPRC = true;
1069 return Subtarget.hasStdExtZcb() && MI.getOperand(i: 2).isReg() &&
1070 MI.getOperand(i: 2).getReg() == RISCV::X0;
1071 case RISCV::XORI:
1072 // c.not
1073 NeedGPRC = true;
1074 return Subtarget.hasStdExtZcb() && MI.getOperand(i: 2).isImm() &&
1075 MI.getOperand(i: 2).getImm() == -1;
1076 case RISCV::QC_EXTU:
1077 return MI.getOperand(i: 2).getImm() >= 6 && MI.getOperand(i: 3).getImm() == 0;
1078 case RISCV::BSETI:
1079 case RISCV::BEXTI:
1080 // qc.c.bseti, qc.c.bexti
1081 NeedGPRC = true;
1082 return Subtarget.hasVendorXqcibm() && MI.getOperand(i: 2).getImm() != 0;
1083 }
1084 };
1085
1086 // Returns true if this operand is compressible. For non-registers it always
1087 // returns true. Immediate range was already checked in isCompressible.
1088 // For registers, it checks if the register is a GPRC register. reg-reg
1089 // instructions that require GPRC need all register operands to be GPRC.
1090 auto isCompressibleOpnd = [&](const MachineOperand &MO) {
1091 if (!MO.isReg())
1092 return true;
1093 Register Reg = MO.getReg();
1094 Register PhysReg = Reg.isPhysical() ? Reg : Register(VRM->getPhys(virtReg: Reg));
1095 return PhysReg && RISCV::GPRCRegClass.contains(Reg: PhysReg);
1096 };
1097
1098 for (auto &MO : MRI->reg_nodbg_operands(Reg: VirtReg)) {
1099 const MachineInstr &MI = *MO.getParent();
1100 unsigned OpIdx = MO.getOperandNo();
1101 bool NeedGPRC;
1102 if (isCompressible(MI, NeedGPRC)) {
1103 if (OpIdx == 0 && MI.getOperand(i: 1).isReg()) {
1104 if (!NeedGPRC || MI.getNumExplicitOperands() < 3 ||
1105 MI.getOpcode() == RISCV::ADD_UW ||
1106 isCompressibleOpnd(MI.getOperand(i: 2)))
1107 tryAddHint(MO, MI.getOperand(i: 1), NeedGPRC);
1108 if (MI.isCommutable() && MI.getOperand(i: 2).isReg() &&
1109 (!NeedGPRC || isCompressibleOpnd(MI.getOperand(i: 1))))
1110 tryAddHint(MO, MI.getOperand(i: 2), NeedGPRC);
1111 } else if (OpIdx == 1 && (!NeedGPRC || MI.getNumExplicitOperands() < 3 ||
1112 isCompressibleOpnd(MI.getOperand(i: 2)))) {
1113 tryAddHint(MO, MI.getOperand(i: 0), NeedGPRC);
1114 } else if (MI.isCommutable() && OpIdx == 2 &&
1115 (!NeedGPRC || isCompressibleOpnd(MI.getOperand(i: 1)))) {
1116 tryAddHint(MO, MI.getOperand(i: 0), NeedGPRC);
1117 }
1118 }
1119
1120 // Add a hint if it would allow auipc/lui+addi(w) fusion. We do this even
1121 // without the fusions explicitly enabled as the impact is rarely negative
1122 // and some cores do implement this fusion.
1123 if ((MI.getOpcode() == RISCV::ADDIW || MI.getOpcode() == RISCV::ADDI) &&
1124 MI.getOperand(i: 1).isReg()) {
1125 const MachineBasicBlock &MBB = *MI.getParent();
1126 MachineBasicBlock::const_iterator I = MI.getIterator();
1127 // Is the previous instruction a LUI or AUIPC that can be fused?
1128 if (I != MBB.begin()) {
1129 I = skipDebugInstructionsBackward(It: std::prev(x: I), Begin: MBB.begin());
1130 if ((I->getOpcode() == RISCV::LUI || I->getOpcode() == RISCV::AUIPC) &&
1131 I->getOperand(i: 0).getReg() == MI.getOperand(i: 1).getReg()) {
1132 if (OpIdx == 0)
1133 tryAddHint(MO, MI.getOperand(i: 1), /*NeedGPRC=*/false);
1134 else
1135 tryAddHint(MO, MI.getOperand(i: 0), /*NeedGPRC=*/false);
1136 }
1137 }
1138 }
1139 }
1140
1141 for (MCPhysReg OrderReg : Order)
1142 if (TwoAddrHints.count(V: OrderReg))
1143 Hints.push_back(Elt: OrderReg);
1144
1145 return BaseImplRetVal;
1146}
1147
1148void RISCVRegisterInfo::updateRegAllocHint(Register Reg, Register NewReg,
1149 MachineFunction &MF) const {
1150 MachineRegisterInfo *MRI = &MF.getRegInfo();
1151 std::pair<unsigned, Register> Hint = MRI->getRegAllocationHint(VReg: Reg);
1152
1153 // Handle RegPairEven/RegPairOdd hints for Zilsd register pairs
1154 if ((Hint.first == RISCVRI::RegPairOdd ||
1155 Hint.first == RISCVRI::RegPairEven) &&
1156 Hint.second.isVirtual()) {
1157 // If 'Reg' is one of the even/odd register pair and it's now changed
1158 // (e.g. coalesced) into a different register, the other register of the
1159 // pair allocation hint must be updated to reflect the relationship change.
1160 Register Partner = Hint.second;
1161 std::pair<unsigned, Register> PartnerHint =
1162 MRI->getRegAllocationHint(VReg: Partner);
1163
1164 // Make sure partner still points to us
1165 if (PartnerHint.second == Reg) {
1166 // Update partner to point to NewReg instead of Reg
1167 MRI->setRegAllocationHint(VReg: Partner, Type: PartnerHint.first, PrefReg: NewReg);
1168
1169 // If NewReg is virtual, set up the reciprocal hint
1170 // NewReg takes over Reg's role, so it gets the SAME hint type as Reg
1171 if (NewReg.isVirtual())
1172 MRI->setRegAllocationHint(VReg: NewReg, Type: Hint.first, PrefReg: Partner);
1173 }
1174 }
1175}
1176
1177Register
1178RISCVRegisterInfo::findVRegWithEncoding(const TargetRegisterClass &RegClass,
1179 uint16_t Encoding) const {
1180 MCRegister Reg = RISCV::V0 + Encoding;
1181 if (RISCVRI::getLMul(TSFlags: RegClass.TSFlags) == RISCVVType::LMUL_1)
1182 return Reg;
1183 return getMatchingSuperReg(Reg, SubIdx: RISCV::sub_vrm1_0, RC: &RegClass);
1184}
1185