1//===-- RISCVRegisterInfo.cpp - RISC-V Register Information -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the RISC-V implementation of the TargetRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVRegisterInfo.h"
14#include "RISCV.h"
15#include "RISCVSubtarget.h"
16#include "llvm/ADT/SmallSet.h"
17#include "llvm/BinaryFormat/Dwarf.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/RegisterScavenging.h"
22#include "llvm/CodeGen/TargetFrameLowering.h"
23#include "llvm/CodeGen/TargetInstrInfo.h"
24#include "llvm/IR/DebugInfoMetadata.h"
25#include "llvm/Support/ErrorHandling.h"
26
27#define GET_REGINFO_TARGET_DESC
28#include "RISCVGenRegisterInfo.inc"
29
30using namespace llvm;
31
32static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");
33static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive");
34static_assert(RISCV::F1_H == RISCV::F0_H + 1, "Register list not consecutive");
35static_assert(RISCV::F31_H == RISCV::F0_H + 31,
36 "Register list not consecutive");
37static_assert(RISCV::F1_F == RISCV::F0_F + 1, "Register list not consecutive");
38static_assert(RISCV::F31_F == RISCV::F0_F + 31,
39 "Register list not consecutive");
40static_assert(RISCV::F1_D == RISCV::F0_D + 1, "Register list not consecutive");
41static_assert(RISCV::F31_D == RISCV::F0_D + 31,
42 "Register list not consecutive");
43static_assert(RISCV::F1_Q == RISCV::F0_Q + 1, "Register list not consecutive");
44static_assert(RISCV::F31_Q == RISCV::F0_Q + 31,
45 "Register list not consecutive");
46static_assert(RISCV::V1 == RISCV::V0 + 1, "Register list not consecutive");
47static_assert(RISCV::V31 == RISCV::V0 + 31, "Register list not consecutive");
48
49RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode)
50 : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
51 /*PC*/0, HwMode) {}
52
53const MCPhysReg *
54RISCVRegisterInfo::getIPRACSRegs(const MachineFunction *MF) const {
55 return CSR_IPRA_SaveList;
56}
57
58const MCPhysReg *
59RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
60 auto &Subtarget = MF->getSubtarget<RISCVSubtarget>();
61 if (MF->getFunction().getCallingConv() == CallingConv::GHC)
62 return CSR_NoRegs_SaveList;
63 if (MF->getFunction().getCallingConv() == CallingConv::PreserveMost)
64 return Subtarget.hasStdExtE() ? CSR_RT_MostRegs_RVE_SaveList
65 : CSR_RT_MostRegs_SaveList;
66 if (MF->getFunction().hasFnAttribute(Kind: "interrupt")) {
67 if (Subtarget.hasVInstructions()) {
68 if (Subtarget.hasStdExtD())
69 return Subtarget.hasStdExtE() ? CSR_XLEN_F64_V_Interrupt_RVE_SaveList
70 : CSR_XLEN_F64_V_Interrupt_SaveList;
71 if (Subtarget.hasStdExtF())
72 return Subtarget.hasStdExtE() ? CSR_XLEN_F32_V_Interrupt_RVE_SaveList
73 : CSR_XLEN_F32_V_Interrupt_SaveList;
74 return Subtarget.hasStdExtE() ? CSR_XLEN_V_Interrupt_RVE_SaveList
75 : CSR_XLEN_V_Interrupt_SaveList;
76 }
77 if (Subtarget.hasStdExtD())
78 return Subtarget.hasStdExtE() ? CSR_XLEN_F64_Interrupt_RVE_SaveList
79 : CSR_XLEN_F64_Interrupt_SaveList;
80 if (Subtarget.hasStdExtF())
81 return Subtarget.hasStdExtE() ? CSR_XLEN_F32_Interrupt_RVE_SaveList
82 : CSR_XLEN_F32_Interrupt_SaveList;
83 return Subtarget.hasStdExtE() ? CSR_Interrupt_RVE_SaveList
84 : CSR_Interrupt_SaveList;
85 }
86
87 bool HasVectorCSR =
88 MF->getFunction().getCallingConv() == CallingConv::RISCV_VectorCall &&
89 Subtarget.hasVInstructions();
90
91 switch (Subtarget.getTargetABI()) {
92 default:
93 llvm_unreachable("Unrecognized ABI");
94 case RISCVABI::ABI_ILP32E:
95 case RISCVABI::ABI_LP64E:
96 return CSR_ILP32E_LP64E_SaveList;
97 case RISCVABI::ABI_ILP32:
98 case RISCVABI::ABI_LP64:
99 if (HasVectorCSR)
100 return CSR_ILP32_LP64_V_SaveList;
101 return CSR_ILP32_LP64_SaveList;
102 case RISCVABI::ABI_ILP32F:
103 case RISCVABI::ABI_LP64F:
104 if (HasVectorCSR)
105 return CSR_ILP32F_LP64F_V_SaveList;
106 return CSR_ILP32F_LP64F_SaveList;
107 case RISCVABI::ABI_ILP32D:
108 case RISCVABI::ABI_LP64D:
109 if (HasVectorCSR)
110 return CSR_ILP32D_LP64D_V_SaveList;
111 return CSR_ILP32D_LP64D_SaveList;
112 }
113}
114
115const TargetRegisterClass *RISCVRegisterInfo::getConstrainedRegClassForReg(
116 Register Reg, const MachineRegisterInfo &MRI) const {
117 const RISCVSubtarget &STI = MRI.getMF().getSubtarget<RISCVSubtarget>();
118
119 const RegClassOrRegBank &RCOrRB = MRI.getRegClassOrRegBank(Reg);
120 if (const RegisterBank *RB = dyn_cast<const RegisterBank *>(Val: RCOrRB))
121 return getRegClassForTypeOnBank(Ty: MRI.getType(Reg), RB: *RB, Is64Bit: STI.is64Bit());
122
123 if (const auto *RC = dyn_cast<const TargetRegisterClass *>(Val: RCOrRB)) {
124 return getAllocatableClass(RC);
125 }
126
127 return nullptr;
128}
129
130const TargetRegisterClass *
131RISCVRegisterInfo::getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB,
132 bool Is64Bit) const {
133 if (RB.getID() == RISCV::GPRBRegBankID) {
134 if (Ty.getSizeInBits() <= 32 || (Is64Bit && Ty.getSizeInBits() == 64))
135 return &RISCV::GPRRegClass;
136 }
137
138 if (RB.getID() == RISCV::FPRBRegBankID) {
139 if (Ty.getSizeInBits() == 16)
140 return &RISCV::FPR16RegClass;
141 if (Ty.getSizeInBits() == 32)
142 return &RISCV::FPR32RegClass;
143 if (Ty.getSizeInBits() == 64)
144 return &RISCV::FPR64RegClass;
145 }
146
147 if (RB.getID() == RISCV::VRBRegBankID) {
148 if (Ty.getSizeInBits().getKnownMinValue() <= 64)
149 return &RISCV::VRRegClass;
150
151 if (Ty.getSizeInBits().getKnownMinValue() == 128)
152 return &RISCV::VRM2RegClass;
153
154 if (Ty.getSizeInBits().getKnownMinValue() == 256)
155 return &RISCV::VRM4RegClass;
156
157 if (Ty.getSizeInBits().getKnownMinValue() == 512)
158 return &RISCV::VRM8RegClass;
159 }
160
161 return nullptr;
162}
163
164BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
165 const RISCVFrameLowering *TFI = getFrameLowering(MF);
166 BitVector Reserved(getNumRegs());
167 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
168
169 for (size_t Reg = 0; Reg < getNumRegs(); Reg++) {
170 // Mark any GPRs requested to be reserved as such
171 if (Subtarget.isRegisterReservedByUser(i: Reg)) {
172 for (MCPhysReg Sub : subregs_inclusive(Reg))
173 markSuperRegs(RegisterSet&: Reserved, Reg: Sub);
174 }
175
176 // Mark all the registers defined as constant in TableGen as reserved.
177 if (isConstantPhysReg(PhysReg: Reg)) {
178 for (MCPhysReg Sub : subregs_inclusive(Reg))
179 markSuperRegs(RegisterSet&: Reserved, Reg: Sub);
180 }
181 }
182
183 // Use markSuperRegs to ensure any register aliases are also reserved
184 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::X2_H); // sp
185 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::X3_H); // gp
186 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::X4_H); // tp
187 if (TFI->hasFP(MF))
188 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::X8_H); // fp
189 // Reserve the base register if we need to realign the stack and allocate
190 // variable-sized objects at runtime.
191 if (TFI->hasBP(MF))
192 markSuperRegs(RegisterSet&: Reserved, Reg: RISCVABI::getBPReg()); // bp
193
194 // Additionally reserve dummy register used to form the register pair
195 // beginning with 'x0' for instructions that take register pairs.
196 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::DUMMY_REG_PAIR_WITH_X0);
197
198 // There are only 16 GPRs for RVE.
199 if (Subtarget.hasStdExtE())
200 for (MCPhysReg Reg = RISCV::X16_H; Reg <= RISCV::X31_H; Reg++)
201 markSuperRegs(RegisterSet&: Reserved, Reg);
202
203 // V registers for code generation. We handle them manually.
204 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::VL);
205 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::VTYPE);
206 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::VXSAT);
207 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::VXRM);
208
209 // Floating point environment registers.
210 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::FRM);
211 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::FFLAGS);
212
213 // SiFive VCIX state registers.
214 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::SF_VCIX_STATE);
215
216 if (MF.getFunction().getCallingConv() == CallingConv::GRAAL) {
217 if (Subtarget.hasStdExtE())
218 reportFatalUsageError(reason: "Graal reserved registers do not exist in RVE");
219 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::X23_H);
220 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::X27_H);
221 }
222
223 // Shadow stack pointer.
224 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::SSP);
225
226 // XSfmmbase
227 for (MCPhysReg Reg = RISCV::T0; Reg <= RISCV::T15; Reg++)
228 markSuperRegs(RegisterSet&: Reserved, Reg);
229
230 assert(checkAllSuperRegsMarked(Reserved));
231 return Reserved;
232}
233
234bool RISCVRegisterInfo::isAsmClobberable(const MachineFunction &MF,
235 MCRegister PhysReg) const {
236 return !MF.getSubtarget().isRegisterReservedByUser(R: PhysReg);
237}
238
239const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const {
240 return CSR_NoRegs_RegMask;
241}
242
243void RISCVRegisterInfo::adjustReg(MachineBasicBlock &MBB,
244 MachineBasicBlock::iterator II,
245 const DebugLoc &DL, Register DestReg,
246 Register SrcReg, StackOffset Offset,
247 MachineInstr::MIFlag Flag,
248 MaybeAlign RequiredAlign) const {
249
250 if (DestReg == SrcReg && !Offset.getFixed() && !Offset.getScalable())
251 return;
252
253 MachineFunction &MF = *MBB.getParent();
254 MachineRegisterInfo &MRI = MF.getRegInfo();
255 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
256 const RISCVInstrInfo *TII = ST.getInstrInfo();
257
258 // Optimize compile time offset case
259 if (Offset.getScalable()) {
260 if (auto VLEN = ST.getRealVLen()) {
261 // 1. Multiply the number of v-slots by the (constant) length of register
262 const int64_t VLENB = *VLEN / 8;
263 assert(Offset.getScalable() % RISCV::RVVBytesPerBlock == 0 &&
264 "Reserve the stack by the multiple of one vector size.");
265 const int64_t NumOfVReg = Offset.getScalable() / 8;
266 const int64_t FixedOffset = NumOfVReg * VLENB;
267 if (!isInt<32>(x: FixedOffset)) {
268 // This check might also need to be updated to 64bit.
269 // However mulImm() still assumes 32bit. For now only support fixed
270 // 64bit frame offsets, since scalable offsets would require the number
271 // of spilled registers to exceed 2^31, which is unlikely.
272 reportFatalUsageError(reason: "Scalable frame size outside of the signed "
273 "32-bit range not supported");
274 }
275 Offset = StackOffset::getFixed(Fixed: FixedOffset + Offset.getFixed());
276 }
277 }
278
279 bool KillSrcReg = false;
280
281 if (Offset.getScalable()) {
282 unsigned ScalableAdjOpc = RISCV::ADD;
283 int64_t ScalableValue = Offset.getScalable();
284 if (ScalableValue < 0) {
285 ScalableValue = -ScalableValue;
286 ScalableAdjOpc = RISCV::SUB;
287 }
288 // Get vlenb and multiply vlen with the number of vector registers.
289 Register ScratchReg = DestReg;
290 if (DestReg == SrcReg)
291 ScratchReg = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
292
293 assert(ScalableValue > 0 && "There is no need to get VLEN scaled value.");
294 assert(ScalableValue % RISCV::RVVBytesPerBlock == 0 &&
295 "Reserve the stack by the multiple of one vector size.");
296 assert(isInt<32>(ScalableValue / RISCV::RVVBytesPerBlock) &&
297 "Expect the number of vector registers within 32-bits.");
298 uint32_t NumOfVReg = ScalableValue / RISCV::RVVBytesPerBlock;
299 // Only use vsetvli rather than vlenb if adjusting in the prologue or
300 // epilogue, otherwise it may disturb the VTYPE and VL status.
301 bool IsPrologueOrEpilogue =
302 Flag == MachineInstr::FrameSetup || Flag == MachineInstr::FrameDestroy;
303 bool UseVsetvliRatherThanVlenb =
304 IsPrologueOrEpilogue && ST.preferVsetvliOverReadVLENB();
305 if (UseVsetvliRatherThanVlenb && (NumOfVReg == 1 || NumOfVReg == 2 ||
306 NumOfVReg == 4 || NumOfVReg == 8)) {
307 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::PseudoReadVLENBViaVSETVLIX0),
308 DestReg: ScratchReg)
309 .addImm(Val: NumOfVReg)
310 .setMIFlag(Flag);
311 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: ScalableAdjOpc), DestReg)
312 .addReg(RegNo: SrcReg)
313 .addReg(RegNo: ScratchReg, Flags: RegState::Kill)
314 .setMIFlag(Flag);
315 } else {
316 if (UseVsetvliRatherThanVlenb)
317 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::PseudoReadVLENBViaVSETVLIX0),
318 DestReg: ScratchReg)
319 .addImm(Val: 1)
320 .setMIFlag(Flag);
321 else
322 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::PseudoReadVLENB), DestReg: ScratchReg)
323 .setMIFlag(Flag);
324
325 if (ScalableAdjOpc == RISCV::ADD && ST.hasStdExtZba() &&
326 (NumOfVReg == 2 || NumOfVReg == 4 || NumOfVReg == 8)) {
327 unsigned Opc = NumOfVReg == 2
328 ? RISCV::SH1ADD
329 : (NumOfVReg == 4 ? RISCV::SH2ADD : RISCV::SH3ADD);
330 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: Opc), DestReg)
331 .addReg(RegNo: ScratchReg, Flags: RegState::Kill)
332 .addReg(RegNo: SrcReg)
333 .setMIFlag(Flag);
334 } else {
335 TII->mulImm(MF, MBB, II, DL, DestReg: ScratchReg, Amt: NumOfVReg, Flag);
336 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: ScalableAdjOpc), DestReg)
337 .addReg(RegNo: SrcReg)
338 .addReg(RegNo: ScratchReg, Flags: RegState::Kill)
339 .setMIFlag(Flag);
340 }
341 }
342 SrcReg = DestReg;
343 KillSrcReg = true;
344 }
345
346 int64_t Val = Offset.getFixed();
347 if (DestReg == SrcReg && Val == 0)
348 return;
349
350 const uint64_t Align = RequiredAlign.valueOrOne().value();
351
352 if (isInt<12>(x: Val)) {
353 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::ADDI), DestReg)
354 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrcReg))
355 .addImm(Val)
356 .setMIFlag(Flag);
357 return;
358 }
359
360 // Use the QC_E_ADDI instruction from the Xqcilia extension that can take a
361 // signed 26-bit immediate.
362 if (ST.hasVendorXqcilia() && isInt<26>(x: Val)) {
363 // The one case where using this instruction is sub-optimal is if Val can be
364 // materialized with a single compressible LUI and following add/sub is also
365 // compressible. Avoid doing this if that is the case.
366 int Hi20 = (Val & 0xFFFFF000) >> 12;
367 bool IsCompressLUI =
368 ((Val & 0xFFF) == 0) && (Hi20 != 0) &&
369 (isUInt<5>(x: Hi20) || (Hi20 >= 0xfffe0 && Hi20 <= 0xfffff));
370 bool IsCompressAddSub =
371 (SrcReg == DestReg) &&
372 ((Val > 0 && RISCV::GPRNoX0RegClass.contains(Reg: SrcReg)) ||
373 (Val < 0 && RISCV::GPRCRegClass.contains(Reg: SrcReg)));
374
375 if (!(IsCompressLUI && IsCompressAddSub)) {
376 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::QC_E_ADDI), DestReg)
377 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrcReg))
378 .addImm(Val)
379 .setMIFlag(Flag);
380 return;
381 }
382 }
383
384 // Try to split the offset across two ADDIs. We need to keep the intermediate
385 // result aligned after each ADDI. We need to determine the maximum value we
386 // can put in each ADDI. In the negative direction, we can use -2048 which is
387 // always sufficiently aligned. In the positive direction, we need to find the
388 // largest 12-bit immediate that is aligned. Exclude -4096 since it can be
389 // created with LUI.
390 assert(Align < 2048 && "Required alignment too large");
391 int64_t MaxPosAdjStep = 2048 - Align;
392 if (Val > -4096 && Val <= (2 * MaxPosAdjStep)) {
393 int64_t FirstAdj = Val < 0 ? -2048 : MaxPosAdjStep;
394 Val -= FirstAdj;
395 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::ADDI), DestReg)
396 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrcReg))
397 .addImm(Val: FirstAdj)
398 .setMIFlag(Flag);
399 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::ADDI), DestReg)
400 .addReg(RegNo: DestReg, Flags: RegState::Kill)
401 .addImm(Val)
402 .setMIFlag(Flag);
403 return;
404 }
405
406 // Use shNadd if doing so lets us materialize a 12 bit immediate with a single
407 // instruction. This saves 1 instruction over the full lui/addi+add fallback
408 // path. We avoid anything which can be done with a single lui as it might
409 // be compressible. Note that the sh1add case is fully covered by the 2x addi
410 // case just above and is thus omitted.
411 if (ST.hasStdExtZba() && (Val & 0xFFF) != 0) {
412 unsigned Opc = 0;
413 if (isShiftedInt<12, 3>(x: Val)) {
414 Opc = RISCV::SH3ADD;
415 Val = Val >> 3;
416 } else if (isShiftedInt<12, 2>(x: Val)) {
417 Opc = RISCV::SH2ADD;
418 Val = Val >> 2;
419 }
420 if (Opc) {
421 Register ScratchReg = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
422 TII->movImm(MBB, MBBI: II, DL, DstReg: ScratchReg, Val, Flag);
423 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: Opc), DestReg)
424 .addReg(RegNo: ScratchReg, Flags: RegState::Kill)
425 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrcReg))
426 .setMIFlag(Flag);
427 return;
428 }
429 }
430
431 // Emit a PseudoAddUpperImm instead of LUI+ADD when the offset is a multiple
432 // of 4096 and the source is the frame register. The frame register is
433 // invariant after PEI, so MachineLateInstrsCleanup can CSE identical pseudos.
434 // The pseudo is later expanded back to LUI+ADD.
435 if (Flag == MachineInstr::NoFlags && !KillSrcReg && DestReg != SrcReg &&
436 SrcReg == getFrameRegister(MF) && isShiftedInt<20, 12>(x: Val)) {
437 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::PseudoAddUpperImm), DestReg)
438 .addReg(RegNo: SrcReg)
439 .addImm(Val: static_cast<uint32_t>(Val) >> 12);
440 return;
441 }
442
443 unsigned Opc = RISCV::ADD;
444 if (Val < 0) {
445 Val = -Val;
446 Opc = RISCV::SUB;
447 }
448
449 Register ScratchReg = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
450 TII->movImm(MBB, MBBI: II, DL, DstReg: ScratchReg, Val, Flag);
451 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: Opc), DestReg)
452 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrcReg))
453 .addReg(RegNo: ScratchReg, Flags: RegState::Kill)
454 .setMIFlag(Flag);
455}
456
457static std::tuple<RISCVVType::VLMUL, const TargetRegisterClass &, unsigned>
458getSpillReloadInfo(unsigned NumRemaining, uint16_t RegEncoding, bool IsSpill) {
459 if (NumRemaining >= 8 && RegEncoding % 8 == 0)
460 return {RISCVVType::LMUL_8, RISCV::VRM8RegClass,
461 IsSpill ? RISCV::VS8R_V : RISCV::VL8RE8_V};
462 if (NumRemaining >= 4 && RegEncoding % 4 == 0)
463 return {RISCVVType::LMUL_4, RISCV::VRM4RegClass,
464 IsSpill ? RISCV::VS4R_V : RISCV::VL4RE8_V};
465 if (NumRemaining >= 2 && RegEncoding % 2 == 0)
466 return {RISCVVType::LMUL_2, RISCV::VRM2RegClass,
467 IsSpill ? RISCV::VS2R_V : RISCV::VL2RE8_V};
468 return {RISCVVType::LMUL_1, RISCV::VRRegClass,
469 IsSpill ? RISCV::VS1R_V : RISCV::VL1RE8_V};
470}
471
472// Split a VSPILLx_Mx/VSPILLx_Mx pseudo into multiple whole register stores
473// separated by LMUL*VLENB bytes.
474void RISCVRegisterInfo::lowerSegmentSpillReload(MachineBasicBlock::iterator II,
475 bool IsSpill) const {
476 DebugLoc DL = II->getDebugLoc();
477 MachineBasicBlock &MBB = *II->getParent();
478 MachineFunction &MF = *MBB.getParent();
479 MachineRegisterInfo &MRI = MF.getRegInfo();
480 const RISCVSubtarget &STI = MF.getSubtarget<RISCVSubtarget>();
481 const TargetInstrInfo *TII = STI.getInstrInfo();
482 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
483
484 auto ZvlssegInfo = RISCV::isRVVSpillForZvlsseg(Opcode: II->getOpcode());
485 unsigned NF = ZvlssegInfo->first;
486 unsigned LMUL = ZvlssegInfo->second;
487 unsigned NumRegs = NF * LMUL;
488 assert(NumRegs <= 8 && "Invalid NF/LMUL combinations.");
489
490 Register Reg = II->getOperand(i: 0).getReg();
491 uint16_t RegEncoding = TRI->getEncodingValue(Reg);
492 Register Base = II->getOperand(i: 1).getReg();
493 bool IsBaseKill = II->getOperand(i: 1).isKill();
494 Register NewBase = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
495
496 auto *OldMMO = *(II->memoperands_begin());
497 LocationSize OldLoc = OldMMO->getSize();
498 assert(OldLoc.isPrecise() && OldLoc.getValue().isKnownMultipleOf(NF));
499 TypeSize VRegSize = OldLoc.getValue().divideCoefficientBy(RHS: NumRegs);
500
501 Register VLENB = 0;
502 unsigned VLENBShift = 0;
503 unsigned PrevHandledNum = 0;
504 unsigned I = 0;
505 while (I != NumRegs) {
506 auto [LMulHandled, RegClass, Opcode] =
507 getSpillReloadInfo(NumRemaining: NumRegs - I, RegEncoding, IsSpill);
508 auto [RegNumHandled, _] = RISCVVType::decodeVLMUL(VLMul: LMulHandled);
509 bool IsLast = I + RegNumHandled == NumRegs;
510 if (PrevHandledNum) {
511 Register Step;
512 // Optimize for constant VLEN.
513 if (auto VLEN = STI.getRealVLen()) {
514 int64_t Offset = *VLEN / 8 * PrevHandledNum;
515 Step = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
516 STI.getInstrInfo()->movImm(MBB, MBBI: II, DL, DstReg: Step, Val: Offset);
517 } else {
518 if (!VLENB) {
519 VLENB = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
520 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::PseudoReadVLENB), DestReg: VLENB);
521 }
522 uint32_t ShiftAmount = Log2_32(Value: PrevHandledNum);
523 // To avoid using an extra register, we shift the VLENB register and
524 // remember how much it has been shifted. We can then use relative
525 // shifts to adjust to the desired shift amount.
526 if (VLENBShift > ShiftAmount) {
527 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::SRLI), DestReg: VLENB)
528 .addReg(RegNo: VLENB, Flags: RegState::Kill)
529 .addImm(Val: VLENBShift - ShiftAmount);
530 } else if (VLENBShift < ShiftAmount) {
531 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::SLLI), DestReg: VLENB)
532 .addReg(RegNo: VLENB, Flags: RegState::Kill)
533 .addImm(Val: ShiftAmount - VLENBShift);
534 }
535 VLENBShift = ShiftAmount;
536 Step = VLENB;
537 }
538
539 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::ADD), DestReg: NewBase)
540 .addReg(RegNo: Base, Flags: getKillRegState(B: I != 0 || IsBaseKill))
541 .addReg(RegNo: Step, Flags: getKillRegState(B: Step != VLENB || IsLast));
542 Base = NewBase;
543 }
544
545 MCRegister ActualReg = findVRegWithEncoding(RegClass, Encoding: RegEncoding);
546 MachineInstrBuilder MIB =
547 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode))
548 .addReg(RegNo: ActualReg, Flags: getDefRegState(B: !IsSpill))
549 .addReg(RegNo: Base, Flags: getKillRegState(B: IsLast))
550 .addMemOperand(MMO: MF.getMachineMemOperand(MMO: OldMMO, Offset: OldMMO->getOffset(),
551 Size: VRegSize * RegNumHandled));
552
553 // Adding implicit-use of super register to describe we are using part of
554 // super register, that prevents machine verifier complaining when part of
555 // subreg is undef, see comment in MachineVerifier::checkLiveness for more
556 // detail.
557 if (IsSpill)
558 MIB.addReg(RegNo: Reg, Flags: RegState::Implicit);
559
560 PrevHandledNum = RegNumHandled;
561 RegEncoding += RegNumHandled;
562 I += RegNumHandled;
563 }
564 II->eraseFromParent();
565}
566
567static unsigned getXqciloWideOpcode(unsigned Opc) {
568 switch (Opc) {
569 case RISCV::LW:
570 return RISCV::QC_E_LW;
571 case RISCV::SW:
572 return RISCV::QC_E_SW;
573 case RISCV::LB:
574 return RISCV::QC_E_LB;
575 case RISCV::LBU:
576 return RISCV::QC_E_LBU;
577 case RISCV::LH:
578 return RISCV::QC_E_LH;
579 case RISCV::LHU:
580 return RISCV::QC_E_LHU;
581 case RISCV::SB:
582 return RISCV::QC_E_SB;
583 case RISCV::SH:
584 return RISCV::QC_E_SH;
585 default:
586 return 0;
587 }
588}
589
590bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
591 int SPAdj, unsigned FIOperandNum,
592 RegScavenger *RS) const {
593 assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
594
595 MachineInstr &MI = *II;
596 MachineFunction &MF = *MI.getParent()->getParent();
597 MachineRegisterInfo &MRI = MF.getRegInfo();
598 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
599 const RISCVInstrInfo *TII = ST.getInstrInfo();
600 bool Is64Bit = ST.is64Bit();
601 DebugLoc DL = MI.getDebugLoc();
602
603 int FrameIndex = MI.getOperand(i: FIOperandNum).getIndex();
604 Register FrameReg;
605 StackOffset Offset =
606 getFrameLowering(MF)->getFrameIndexReference(MF, FI: FrameIndex, FrameReg);
607 bool IsRVVSpill = RISCV::isRVVSpill(MI);
608 if (!IsRVVSpill)
609 Offset += StackOffset::getFixed(Fixed: MI.getOperand(i: FIOperandNum + 1).getImm());
610
611 if (!Is64Bit && !isInt<32>(x: Offset.getFixed())) {
612 reportFatalUsageError(reason: "Frame offsets outside of the signed 32-bit range "
613 "not supported on RV32");
614 }
615
616 if (!IsRVVSpill) {
617 int64_t Val = Offset.getFixed();
618 int64_t Lo12 = SignExtend64<12>(x: Val);
619 int64_t Lo26 = SignExtend64<26>(x: Val);
620 unsigned Opc = MI.getOpcode();
621
622 if (Opc == RISCV::ADDI && !isInt<12>(x: Val)) {
623 // We chose to emit the canonical immediate sequence rather than folding
624 // the offset into the using add under the theory that doing so doesn't
625 // save dynamic instruction count and some target may fuse the canonical
626 // 32 bit immediate sequence. We still need to clear the portion of the
627 // offset encoded in the immediate.
628 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: 0);
629 } else if ((Opc == RISCV::PREFETCH_I || Opc == RISCV::PREFETCH_R ||
630 Opc == RISCV::PREFETCH_W) &&
631 (Lo12 & 0b11111) != 0) {
632 // Prefetch instructions require the offset to be 32 byte aligned.
633 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: 0);
634 } else if (Opc == RISCV::MIPS_PREF && !isUInt<9>(x: Val)) {
635 // MIPS Prefetch instructions require the offset to be 9 bits encoded.
636 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: 0);
637 } else if ((Opc == RISCV::PseudoRV32ZdinxLD ||
638 Opc == RISCV::PseudoRV32ZdinxSD ||
639 Opc == RISCV::PseudoLD_RV32_OPT ||
640 Opc == RISCV::PseudoSD_RV32_OPT) &&
641 Lo12 >= 2044) {
642 // This instruction will/might be split into 2 instructions. The second
643 // instruction will add 4 to the immediate. If that would overflow 12
644 // bits, we can't fold the offset.
645 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: 0);
646 } else if (unsigned WideOpc = getXqciloWideOpcode(Opc);
647 !isInt<12>(x: Val) && ST.hasVendorXqcilo() && WideOpc) {
648 // The resolved frame offset exceeds simm12 but the instruction is a
649 // standard load/store (LW/SW/etc). Promote to the wide Xqcilo equivalent
650 // so the full 26-bit offset folds directly, avoiding a separate
651 // base-adjust instruction. This runs post-RA and does not affect
652 // register allocation decisions.
653 MI.setDesc(TII->get(Opcode: WideOpc));
654 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: Lo26);
655 Offset = StackOffset::get(Fixed: (uint64_t)Val - (uint64_t)Lo26,
656 Scalable: Offset.getScalable());
657 } else if (Opc == RISCV::QC_E_ADDI || RISCVInstrInfo::isBaseQCLoad(MI) ||
658 RISCVInstrInfo::isBaseQCStore(MI)) {
659 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: Lo26);
660 Offset = StackOffset::get(Fixed: (uint64_t)Val - (uint64_t)Lo26,
661 Scalable: Offset.getScalable());
662 } else {
663 // We can encode an add with 12 bit signed immediate in the immediate
664 // operand of our user instruction. As a result, the remaining
665 // offset can by construction, at worst, a LUI and a ADD.
666 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: Lo12);
667 Offset = StackOffset::get(Fixed: (uint64_t)Val - (uint64_t)Lo12,
668 Scalable: Offset.getScalable());
669 }
670 }
671
672 if (Offset.getScalable() || Offset.getFixed()) {
673 Register DestReg;
674 if (MI.getOpcode() == RISCV::ADDI)
675 DestReg = MI.getOperand(i: 0).getReg();
676 else
677 DestReg = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
678 adjustReg(MBB&: *II->getParent(), II, DL, DestReg, SrcReg: FrameReg, Offset,
679 Flag: MachineInstr::NoFlags, RequiredAlign: std::nullopt);
680 MI.getOperand(i: FIOperandNum).ChangeToRegister(Reg: DestReg, /*IsDef*/isDef: false,
681 /*IsImp*/isImp: false,
682 /*IsKill*/isKill: true);
683 } else {
684 MI.getOperand(i: FIOperandNum).ChangeToRegister(Reg: FrameReg, /*IsDef*/isDef: false,
685 /*IsImp*/isImp: false,
686 /*IsKill*/isKill: false);
687 }
688
689 // If after materializing the adjustment, we have a pointless ADDI, remove it
690 if (MI.getOpcode() == RISCV::ADDI &&
691 MI.getOperand(i: 0).getReg() == MI.getOperand(i: 1).getReg() &&
692 MI.getOperand(i: 2).getImm() == 0) {
693 MI.eraseFromParent();
694 return true;
695 }
696
697 // Handle spill/fill of synthetic register classes for segment operations to
698 // ensure correctness in the edge case one gets spilled.
699 switch (MI.getOpcode()) {
700 case RISCV::PseudoVSPILL2_M1:
701 case RISCV::PseudoVSPILL2_M2:
702 case RISCV::PseudoVSPILL2_M4:
703 case RISCV::PseudoVSPILL3_M1:
704 case RISCV::PseudoVSPILL3_M2:
705 case RISCV::PseudoVSPILL4_M1:
706 case RISCV::PseudoVSPILL4_M2:
707 case RISCV::PseudoVSPILL5_M1:
708 case RISCV::PseudoVSPILL6_M1:
709 case RISCV::PseudoVSPILL7_M1:
710 case RISCV::PseudoVSPILL8_M1:
711 lowerSegmentSpillReload(II, /*IsSpill=*/true);
712 return true;
713 case RISCV::PseudoVRELOAD2_M1:
714 case RISCV::PseudoVRELOAD2_M2:
715 case RISCV::PseudoVRELOAD2_M4:
716 case RISCV::PseudoVRELOAD3_M1:
717 case RISCV::PseudoVRELOAD3_M2:
718 case RISCV::PseudoVRELOAD4_M1:
719 case RISCV::PseudoVRELOAD4_M2:
720 case RISCV::PseudoVRELOAD5_M1:
721 case RISCV::PseudoVRELOAD6_M1:
722 case RISCV::PseudoVRELOAD7_M1:
723 case RISCV::PseudoVRELOAD8_M1:
724 lowerSegmentSpillReload(II, /*IsSpill=*/false);
725 return true;
726 }
727
728 return false;
729}
730
731bool RISCVRegisterInfo::requiresVirtualBaseRegisters(
732 const MachineFunction &MF) const {
733 return true;
734}
735
736// Returns true if the instruction's frame index reference would be better
737// served by a base register other than FP or SP.
738// Used by LocalStackSlotAllocation pass to determine which frame index
739// references it should create new base registers for.
740bool RISCVRegisterInfo::needsFrameBaseReg(MachineInstr *MI,
741 int64_t Offset) const {
742 unsigned FIOperandNum = 0;
743 for (; !MI->getOperand(i: FIOperandNum).isFI(); FIOperandNum++)
744 assert(FIOperandNum < MI->getNumOperands() &&
745 "Instr doesn't have FrameIndex operand");
746
747 // For RISC-V, The machine instructions that include a FrameIndex operand
748 // are load/store, ADDI instructions.
749 unsigned MIFrm = RISCVII::getFormat(TSFlags: MI->getDesc().TSFlags);
750 if (MIFrm != RISCVII::InstFormatI && MIFrm != RISCVII::InstFormatS)
751 return false;
752 // We only generate virtual base registers for loads and stores, so
753 // return false for everything else.
754 if (!MI->mayLoad() && !MI->mayStore())
755 return false;
756
757 const MachineFunction &MF = *MI->getMF();
758 const MachineFrameInfo &MFI = MF.getFrameInfo();
759 const RISCVFrameLowering *TFI = getFrameLowering(MF);
760 const MachineRegisterInfo &MRI = MF.getRegInfo();
761
762 if (TFI->hasFP(MF) && !shouldRealignStack(MF)) {
763 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
764 // Estimate the stack size used to store callee saved registers(
765 // excludes reserved registers).
766 unsigned CalleeSavedSize = 0;
767 for (const MCPhysReg *R = MRI.getCalleeSavedRegs(); MCPhysReg Reg = *R;
768 ++R) {
769 if (Subtarget.isRegisterReservedByUser(i: Reg))
770 continue;
771
772 if (RISCV::GPRRegClass.contains(Reg))
773 CalleeSavedSize += getSpillSize(RC: RISCV::GPRRegClass);
774 else if (RISCV::FPR64RegClass.contains(Reg))
775 CalleeSavedSize += getSpillSize(RC: RISCV::FPR64RegClass);
776 else if (RISCV::FPR32RegClass.contains(Reg))
777 CalleeSavedSize += getSpillSize(RC: RISCV::FPR32RegClass);
778 // Ignore vector registers.
779 }
780
781 int64_t MaxFPOffset = Offset - CalleeSavedSize;
782 if (isFrameOffsetLegal(MI, BaseReg: RISCV::X8, Offset: MaxFPOffset))
783 return false;
784
785 // If the FP-relative offset doesn't fit, fall through to check the
786 // SP-relative offset. getFrameIndexReference may select SP over FP when
787 // the SP offset fits in the compressed instruction immediate range, so a
788 // base register might not be needed.
789 }
790
791 // Assume 128 bytes spill slots size to estimate the maximum possible
792 // offset relative to the stack pointer.
793 // FIXME: The 128 is copied from ARM. We should run some statistics and pick a
794 // real one for RISC-V.
795 int64_t MaxSPOffset = Offset + 128;
796 MaxSPOffset += MFI.getLocalFrameSize();
797 return !isFrameOffsetLegal(MI, BaseReg: RISCV::X2, Offset: MaxSPOffset);
798}
799
800// Determine whether a given base register plus offset immediate is
801// encodable to resolve a frame index.
802bool RISCVRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
803 Register BaseReg,
804 int64_t Offset) const {
805 unsigned FIOperandNum = 0;
806 while (!MI->getOperand(i: FIOperandNum).isFI()) {
807 FIOperandNum++;
808 assert(FIOperandNum < MI->getNumOperands() &&
809 "Instr does not have a FrameIndex operand!");
810 }
811
812 Offset += getFrameIndexInstrOffset(MI, Idx: FIOperandNum);
813 return isInt<12>(x: Offset);
814}
815
816// Insert defining instruction(s) for a pointer to FrameIdx before
817// insertion point I.
818// Return materialized frame pointer.
819Register RISCVRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
820 int FrameIdx,
821 int64_t Offset) const {
822 MachineBasicBlock::iterator MBBI = MBB->begin();
823 DebugLoc DL;
824 if (MBBI != MBB->end())
825 DL = MBBI->getDebugLoc();
826 MachineFunction *MF = MBB->getParent();
827 MachineRegisterInfo &MFI = MF->getRegInfo();
828 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
829
830 Register BaseReg = MFI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
831 BuildMI(BB&: *MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: RISCV::ADDI), DestReg: BaseReg)
832 .addFrameIndex(Idx: FrameIdx)
833 .addImm(Val: Offset);
834 return BaseReg;
835}
836
837// Resolve a frame index operand of an instruction to reference the
838// indicated base register plus offset instead.
839void RISCVRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg,
840 int64_t Offset) const {
841 unsigned FIOperandNum = 0;
842 while (!MI.getOperand(i: FIOperandNum).isFI()) {
843 FIOperandNum++;
844 assert(FIOperandNum < MI.getNumOperands() &&
845 "Instr does not have a FrameIndex operand!");
846 }
847
848 Offset += getFrameIndexInstrOffset(MI: &MI, Idx: FIOperandNum);
849 // FrameIndex Operands are always represented as a
850 // register followed by an immediate.
851 MI.getOperand(i: FIOperandNum).ChangeToRegister(Reg: BaseReg, isDef: false);
852 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: Offset);
853}
854
855// Get the offset from the referenced frame index in the instruction,
856// if there is one.
857int64_t RISCVRegisterInfo::getFrameIndexInstrOffset(const MachineInstr *MI,
858 int Idx) const {
859 assert((RISCVII::getFormat(MI->getDesc().TSFlags) == RISCVII::InstFormatI ||
860 RISCVII::getFormat(MI->getDesc().TSFlags) == RISCVII::InstFormatS) &&
861 "The MI must be I or S format.");
862 assert(MI->getOperand(Idx).isFI() && "The Idx'th operand of MI is not a "
863 "FrameIndex operand");
864 return MI->getOperand(i: Idx + 1).getImm();
865}
866
867Register RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
868 const TargetFrameLowering *TFI = getFrameLowering(MF);
869 return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
870}
871
872bool RISCVRegisterInfo::isArgumentRegister(const MachineFunction &MF,
873 MCRegister Reg) const {
874 auto const &STI = MF.getSubtarget<RISCVSubtarget>();
875 const RISCVRegisterInfo *TRI = STI.getRegisterInfo();
876
877 if (TRI->isGeneralPurposeRegister(MF, PhysReg: Reg))
878 return llvm::is_contained(Range: RISCV::getArgGPRs(STI), Element: Reg);
879
880 if (TRI->isFPRegister(Reg))
881 return llvm::is_contained(Range: RISCV::getArgFPRs(STI), Element: Reg);
882
883 if (RISCV::VRRegClass.contains(Reg))
884 return llvm::is_contained(Range: RISCV::getArgVRs(STI), Element: Reg);
885
886 return false;
887}
888
889StringRef RISCVRegisterInfo::getRegAsmName(MCRegister Reg) const {
890 if (Reg == RISCV::SF_VCIX_STATE)
891 return "sf.vcix_state";
892 return TargetRegisterInfo::getRegAsmName(Reg);
893}
894
895const uint32_t *
896RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF,
897 CallingConv::ID CC) const {
898 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
899
900 if (CC == CallingConv::GHC)
901 return CSR_NoRegs_RegMask;
902 RISCVABI::ABI ABI = Subtarget.getTargetABI();
903 if (CC == CallingConv::PreserveMost) {
904 if (ABI == RISCVABI::ABI_ILP32E || ABI == RISCVABI::ABI_LP64E)
905 return CSR_RT_MostRegs_RVE_RegMask;
906 return CSR_RT_MostRegs_RegMask;
907 }
908 switch (ABI) {
909 default:
910 llvm_unreachable("Unrecognized ABI");
911 case RISCVABI::ABI_ILP32E:
912 case RISCVABI::ABI_LP64E:
913 return CSR_ILP32E_LP64E_RegMask;
914 case RISCVABI::ABI_ILP32:
915 case RISCVABI::ABI_LP64:
916 if (CC == CallingConv::RISCV_VectorCall)
917 return CSR_ILP32_LP64_V_RegMask;
918 return CSR_ILP32_LP64_RegMask;
919 case RISCVABI::ABI_ILP32F:
920 case RISCVABI::ABI_LP64F:
921 if (CC == CallingConv::RISCV_VectorCall)
922 return CSR_ILP32F_LP64F_V_RegMask;
923 return CSR_ILP32F_LP64F_RegMask;
924 case RISCVABI::ABI_ILP32D:
925 case RISCVABI::ABI_LP64D:
926 if (CC == CallingConv::RISCV_VectorCall)
927 return CSR_ILP32D_LP64D_V_RegMask;
928 return CSR_ILP32D_LP64D_RegMask;
929 }
930}
931
932const TargetRegisterClass *
933RISCVRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
934 const MachineFunction &) const {
935 if (RC == &RISCV::VMV0RegClass)
936 return &RISCV::VRRegClass;
937 if (RC == &RISCV::VRNoV0RegClass)
938 return &RISCV::VRRegClass;
939 if (RC == &RISCV::VRM2NoV0RegClass)
940 return &RISCV::VRM2RegClass;
941 if (RC == &RISCV::VRM4NoV0RegClass)
942 return &RISCV::VRM4RegClass;
943 if (RC == &RISCV::VRM8NoV0RegClass)
944 return &RISCV::VRM8RegClass;
945 return RC;
946}
947
948void RISCVRegisterInfo::getOffsetOpcodes(const StackOffset &Offset,
949 SmallVectorImpl<uint64_t> &Ops) const {
950 // VLENB is the length of a vector register in bytes. We use <vscale x 8 x i8>
951 // to represent one vector register. The dwarf offset is
952 // VLENB * scalable_offset / 8.
953 assert(Offset.getScalable() % 8 == 0 && "Invalid frame offset");
954
955 // Add fixed-sized offset using existing DIExpression interface.
956 DIExpression::appendOffset(Ops, Offset: Offset.getFixed());
957
958 unsigned VLENB = getDwarfRegNum(Reg: RISCV::VLENB, isEH: true);
959 int64_t VLENBSized = Offset.getScalable() / 8;
960 if (VLENBSized > 0) {
961 Ops.push_back(Elt: dwarf::DW_OP_constu);
962 Ops.push_back(Elt: VLENBSized);
963 Ops.append(IL: {dwarf::DW_OP_bregx, VLENB, 0ULL});
964 Ops.push_back(Elt: dwarf::DW_OP_mul);
965 Ops.push_back(Elt: dwarf::DW_OP_plus);
966 } else if (VLENBSized < 0) {
967 Ops.push_back(Elt: dwarf::DW_OP_constu);
968 Ops.push_back(Elt: -VLENBSized);
969 Ops.append(IL: {dwarf::DW_OP_bregx, VLENB, 0ULL});
970 Ops.push_back(Elt: dwarf::DW_OP_mul);
971 Ops.push_back(Elt: dwarf::DW_OP_minus);
972 }
973}
974
975unsigned
976RISCVRegisterInfo::getRegisterCostTableIndex(const MachineFunction &MF) const {
977 // Set CostPerUse to 1 only when optimizing for size and RVC exists.
978 const auto &ST = MF.getSubtarget<RISCVSubtarget>();
979 return MF.getFunction().hasOptSize() && ST.hasStdExtZca() &&
980 ST.getCLOpts().cost_per_use
981 ? 1
982 : 0;
983}
984
985float RISCVRegisterInfo::getSpillWeightScaleFactor(
986 const TargetRegisterClass *RC) const {
987 return getRegClassWeight(RC).RegWeight;
988}
989
990// Add two address hints to improve chances of being able to use a compressed
991// instruction.
992bool RISCVRegisterInfo::getRegAllocationHints(
993 Register VirtReg, ArrayRef<MCPhysReg> Order,
994 SmallSetVector<MCPhysReg, 16> &Hints, const MachineFunction &MF,
995 const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
996 const MachineRegisterInfo *MRI = &MF.getRegInfo();
997 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
998
999 // Handle RegPairEven/RegPairOdd hints for Zilsd register pairs
1000 std::pair<unsigned, Register> Hint = MRI->getRegAllocationHint(VReg: VirtReg);
1001 unsigned HintType = Hint.first;
1002 Register Partner = Hint.second;
1003
1004 MCRegister TargetReg;
1005 if (HintType == RISCVRI::RegPairEven || HintType == RISCVRI::RegPairOdd) {
1006 // Check if we want the even or odd register of a consecutive pair
1007 bool WantOdd = (HintType == RISCVRI::RegPairOdd);
1008
1009 // First priority: Check if partner is already allocated
1010 if (Partner.isVirtual() && VRM && VRM->hasPhys(virtReg: Partner)) {
1011 MCRegister PartnerPhys = VRM->getPhys(virtReg: Partner);
1012 // Calculate the exact register we need for consecutive pairing
1013 TargetReg = PartnerPhys.id() + (WantOdd ? 1 : -1);
1014
1015 // Verify it's valid and available
1016 if (RISCV::GPRRegClass.contains(Reg: TargetReg) &&
1017 is_contained(Range&: Order, Element: TargetReg))
1018 Hints.insert(X: TargetReg.id());
1019 }
1020
1021 // Second priority: Try to find consecutive register pairs in the allocation
1022 // order
1023 for (MCPhysReg PhysReg : Order) {
1024 // Don't add the hint if we already added above.
1025 if (TargetReg == PhysReg)
1026 continue;
1027
1028 unsigned RegNum = getEncodingValue(Reg: PhysReg);
1029 // Check if this register matches the even/odd requirement
1030 bool IsOdd = (RegNum % 2 != 0);
1031
1032 // Don't provide hints that are paired to a reserved register.
1033 MCRegister Paired = PhysReg + (IsOdd ? -1 : 1);
1034 if (WantOdd == IsOdd && !MRI->isReserved(PhysReg: Paired))
1035 Hints.insert(X: PhysReg);
1036 }
1037 }
1038
1039 bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
1040 VirtReg, Order, Hints, MF, VRM, Matrix);
1041
1042 if (!VRM || !MF.getSubtarget<RISCVSubtarget>().getCLOpts().regalloc_hints)
1043 return BaseImplRetVal;
1044
1045 // Add any two address hints after any copy hints.
1046 SmallSet<Register, 4> TwoAddrHints;
1047
1048 auto tryAddHint = [&](const MachineOperand &VRRegMO, const MachineOperand &MO,
1049 bool NeedGPRC) -> void {
1050 Register Reg = MO.getReg();
1051 Register PhysReg = Reg.isPhysical() ? Reg : Register(VRM->getPhys(virtReg: Reg));
1052 // TODO: Support GPRPair subregisters? Need to be careful with even/odd
1053 // registers. If the virtual register is an odd register of a pair and the
1054 // physical register is even (or vice versa), we should not add the hint.
1055 if (PhysReg && (!NeedGPRC || RISCV::GPRCRegClass.contains(Reg: PhysReg)) &&
1056 !MO.getSubReg() && !VRRegMO.getSubReg()) {
1057 if (!MRI->isReserved(PhysReg) && !Hints.contains(key: PhysReg))
1058 TwoAddrHints.insert(V: PhysReg);
1059 }
1060 };
1061
1062 // This is all of the compressible binary instructions. If an instruction
1063 // needs GPRC register class operands \p NeedGPRC will be set to true.
1064 auto isCompressible = [&Subtarget](const MachineInstr &MI, bool &NeedGPRC) {
1065 NeedGPRC = false;
1066 switch (MI.getOpcode()) {
1067 default:
1068 return false;
1069 case RISCV::AND:
1070 case RISCV::OR:
1071 case RISCV::XOR:
1072 case RISCV::SUB:
1073 case RISCV::ADDW:
1074 case RISCV::SUBW:
1075 NeedGPRC = true;
1076 return true;
1077 case RISCV::ANDI: {
1078 NeedGPRC = true;
1079 if (!MI.getOperand(i: 2).isImm())
1080 return false;
1081 int64_t Imm = MI.getOperand(i: 2).getImm();
1082 if (isInt<6>(x: Imm))
1083 return true;
1084 // c.zext.b
1085 return Subtarget.hasStdExtZcb() && Imm == 255;
1086 }
1087 case RISCV::SRAI:
1088 case RISCV::SRLI:
1089 NeedGPRC = true;
1090 return true;
1091 case RISCV::ADD:
1092 case RISCV::SLLI:
1093 return true;
1094 case RISCV::ADDI:
1095 case RISCV::ADDIW:
1096 return MI.getOperand(i: 2).isImm() && isInt<6>(x: MI.getOperand(i: 2).getImm());
1097 case RISCV::MUL:
1098 // c.mul
1099 NeedGPRC = true;
1100 return Subtarget.hasStdExtZcb();
1101 case RISCV::SEXT_B:
1102 case RISCV::SEXT_H:
1103 case RISCV::ZEXT_H_RV32:
1104 case RISCV::ZEXT_H_RV64:
1105 // c.sext.b, c.sext.h, c.zext.h
1106 NeedGPRC = true;
1107 return Subtarget.hasStdExtZcb() && Subtarget.hasStdExtZbb();
1108 case RISCV::ADD_UW:
1109 // c.zext.w
1110 NeedGPRC = true;
1111 return Subtarget.hasStdExtZcb() && MI.getOperand(i: 2).isReg() &&
1112 MI.getOperand(i: 2).getReg() == RISCV::X0;
1113 case RISCV::XORI:
1114 // c.not
1115 NeedGPRC = true;
1116 return Subtarget.hasStdExtZcb() && MI.getOperand(i: 2).isImm() &&
1117 MI.getOperand(i: 2).getImm() == -1;
1118 case RISCV::QC_EXTU:
1119 return MI.getOperand(i: 2).getImm() >= 6 && MI.getOperand(i: 3).getImm() == 0;
1120 case RISCV::BSETI:
1121 case RISCV::BEXTI:
1122 // qc.c.bseti, qc.c.bexti
1123 NeedGPRC = true;
1124 return Subtarget.hasVendorXqcibm() && MI.getOperand(i: 2).getImm() != 0;
1125 }
1126 };
1127
1128 // Returns true if this operand is compressible. For non-registers it always
1129 // returns true. Immediate range was already checked in isCompressible.
1130 // For registers, it checks if the register is a GPRC register. reg-reg
1131 // instructions that require GPRC need all register operands to be GPRC.
1132 auto isCompressibleOpnd = [&](const MachineOperand &MO) {
1133 if (!MO.isReg())
1134 return true;
1135 Register Reg = MO.getReg();
1136 Register PhysReg = Reg.isPhysical() ? Reg : Register(VRM->getPhys(virtReg: Reg));
1137 return PhysReg && RISCV::GPRCRegClass.contains(Reg: PhysReg);
1138 };
1139
1140 for (auto &MO : MRI->reg_nodbg_operands(Reg: VirtReg)) {
1141 const MachineInstr &MI = *MO.getParent();
1142 unsigned OpIdx = MO.getOperandNo();
1143 bool NeedGPRC;
1144 if (isCompressible(MI, NeedGPRC)) {
1145 if (OpIdx == 0 && MI.getOperand(i: 1).isReg()) {
1146 if (!NeedGPRC || MI.getNumExplicitOperands() < 3 ||
1147 MI.getOpcode() == RISCV::ADD_UW ||
1148 isCompressibleOpnd(MI.getOperand(i: 2)))
1149 tryAddHint(MO, MI.getOperand(i: 1), NeedGPRC);
1150 if (MI.isCommutable() && MI.getOperand(i: 2).isReg() &&
1151 (!NeedGPRC || isCompressibleOpnd(MI.getOperand(i: 1))))
1152 tryAddHint(MO, MI.getOperand(i: 2), NeedGPRC);
1153 } else if (OpIdx == 1 && (!NeedGPRC || MI.getNumExplicitOperands() < 3 ||
1154 isCompressibleOpnd(MI.getOperand(i: 2)))) {
1155 tryAddHint(MO, MI.getOperand(i: 0), NeedGPRC);
1156 } else if (MI.isCommutable() && OpIdx == 2 &&
1157 (!NeedGPRC || isCompressibleOpnd(MI.getOperand(i: 1)))) {
1158 tryAddHint(MO, MI.getOperand(i: 0), NeedGPRC);
1159 }
1160 }
1161
1162 // Add a hint if it would allow auipc/lui+addi(w) fusion. We do this even
1163 // without the fusions explicitly enabled as the impact is rarely negative
1164 // and some cores do implement this fusion.
1165 if ((MI.getOpcode() == RISCV::ADDIW || MI.getOpcode() == RISCV::ADDI) &&
1166 MI.getOperand(i: 1).isReg()) {
1167 const MachineBasicBlock &MBB = *MI.getParent();
1168 MachineBasicBlock::const_iterator I = MI.getIterator();
1169 // Is the previous instruction a LUI or AUIPC that can be fused?
1170 if (I != MBB.begin()) {
1171 I = skipDebugInstructionsBackward(It: std::prev(x: I), Begin: MBB.begin());
1172 if ((I->getOpcode() == RISCV::LUI || I->getOpcode() == RISCV::AUIPC) &&
1173 I->getOperand(i: 0).getReg() == MI.getOperand(i: 1).getReg()) {
1174 if (OpIdx == 0)
1175 tryAddHint(MO, MI.getOperand(i: 1), /*NeedGPRC=*/false);
1176 else
1177 tryAddHint(MO, MI.getOperand(i: 0), /*NeedGPRC=*/false);
1178 }
1179 }
1180 }
1181 }
1182
1183 for (MCPhysReg OrderReg : Order)
1184 if (TwoAddrHints.count(V: OrderReg))
1185 Hints.insert(X: OrderReg);
1186
1187 return BaseImplRetVal;
1188}
1189
1190void RISCVRegisterInfo::updateRegAllocHint(Register Reg, Register NewReg,
1191 MachineFunction &MF) const {
1192 MachineRegisterInfo *MRI = &MF.getRegInfo();
1193 std::pair<unsigned, Register> Hint = MRI->getRegAllocationHint(VReg: Reg);
1194
1195 // Handle RegPairEven/RegPairOdd hints for Zilsd register pairs
1196 if ((Hint.first == RISCVRI::RegPairOdd ||
1197 Hint.first == RISCVRI::RegPairEven) &&
1198 Hint.second.isVirtual()) {
1199 // If 'Reg' is one of the even/odd register pair and it's now changed
1200 // (e.g. coalesced) into a different register, the other register of the
1201 // pair allocation hint must be updated to reflect the relationship change.
1202 Register Partner = Hint.second;
1203 std::pair<unsigned, Register> PartnerHint =
1204 MRI->getRegAllocationHint(VReg: Partner);
1205
1206 // Make sure partner still points to us
1207 if (PartnerHint.second == Reg) {
1208 // Update partner to point to NewReg instead of Reg
1209 MRI->setRegAllocationHint(VReg: Partner, Type: PartnerHint.first, PrefReg: NewReg);
1210
1211 // If NewReg is virtual, set up the reciprocal hint
1212 // NewReg takes over Reg's role, so it gets the SAME hint type as Reg
1213 if (NewReg.isVirtual())
1214 MRI->setRegAllocationHint(VReg: NewReg, Type: Hint.first, PrefReg: Partner);
1215 }
1216 }
1217}
1218
1219Register
1220RISCVRegisterInfo::findVRegWithEncoding(const TargetRegisterClass &RegClass,
1221 uint16_t Encoding) const {
1222 MCRegister Reg = RISCV::V0 + Encoding;
1223 if (RISCVRI::getLMul(TSFlags: RegClass.TSFlags) == RISCVVType::LMUL_1)
1224 return Reg;
1225 return getMatchingSuperReg(Reg, SubIdx: RISCV::sub_vrm1_0, RC: &RegClass);
1226}
1227