1//===-- RISCVRegisterInfo.cpp - RISC-V Register Information -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the RISC-V implementation of the TargetRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVRegisterInfo.h"
14#include "RISCV.h"
15#include "RISCVSubtarget.h"
16#include "llvm/ADT/SmallSet.h"
17#include "llvm/BinaryFormat/Dwarf.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/RegisterScavenging.h"
22#include "llvm/CodeGen/TargetFrameLowering.h"
23#include "llvm/CodeGen/TargetInstrInfo.h"
24#include "llvm/IR/DebugInfoMetadata.h"
25#include "llvm/Support/ErrorHandling.h"
26
27#define GET_REGINFO_TARGET_DESC
28#include "RISCVGenRegisterInfo.inc"
29
30using namespace llvm;
31
32static cl::opt<bool> DisableCostPerUse("riscv-disable-cost-per-use",
33 cl::init(Val: false), cl::Hidden);
34static cl::opt<bool>
35 DisableRegAllocHints("riscv-disable-regalloc-hints", cl::Hidden,
36 cl::init(Val: false),
37 cl::desc("Disable two address hints for register "
38 "allocation"));
39
40static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");
41static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive");
42static_assert(RISCV::F1_H == RISCV::F0_H + 1, "Register list not consecutive");
43static_assert(RISCV::F31_H == RISCV::F0_H + 31,
44 "Register list not consecutive");
45static_assert(RISCV::F1_F == RISCV::F0_F + 1, "Register list not consecutive");
46static_assert(RISCV::F31_F == RISCV::F0_F + 31,
47 "Register list not consecutive");
48static_assert(RISCV::F1_D == RISCV::F0_D + 1, "Register list not consecutive");
49static_assert(RISCV::F31_D == RISCV::F0_D + 31,
50 "Register list not consecutive");
51static_assert(RISCV::F1_Q == RISCV::F0_Q + 1, "Register list not consecutive");
52static_assert(RISCV::F31_Q == RISCV::F0_Q + 31,
53 "Register list not consecutive");
54static_assert(RISCV::V1 == RISCV::V0 + 1, "Register list not consecutive");
55static_assert(RISCV::V31 == RISCV::V0 + 31, "Register list not consecutive");
56
57RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode)
58 : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
59 /*PC*/0, HwMode) {}
60
61const MCPhysReg *
62RISCVRegisterInfo::getIPRACSRegs(const MachineFunction *MF) const {
63 return CSR_IPRA_SaveList;
64}
65
66const MCPhysReg *
67RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
68 auto &Subtarget = MF->getSubtarget<RISCVSubtarget>();
69 if (MF->getFunction().getCallingConv() == CallingConv::GHC)
70 return CSR_NoRegs_SaveList;
71 if (MF->getFunction().getCallingConv() == CallingConv::PreserveMost)
72 return Subtarget.hasStdExtE() ? CSR_RT_MostRegs_RVE_SaveList
73 : CSR_RT_MostRegs_SaveList;
74 if (MF->getFunction().hasFnAttribute(Kind: "interrupt")) {
75 if (Subtarget.hasVInstructions()) {
76 if (Subtarget.hasStdExtD())
77 return Subtarget.hasStdExtE() ? CSR_XLEN_F64_V_Interrupt_RVE_SaveList
78 : CSR_XLEN_F64_V_Interrupt_SaveList;
79 if (Subtarget.hasStdExtF())
80 return Subtarget.hasStdExtE() ? CSR_XLEN_F32_V_Interrupt_RVE_SaveList
81 : CSR_XLEN_F32_V_Interrupt_SaveList;
82 return Subtarget.hasStdExtE() ? CSR_XLEN_V_Interrupt_RVE_SaveList
83 : CSR_XLEN_V_Interrupt_SaveList;
84 }
85 if (Subtarget.hasStdExtD())
86 return Subtarget.hasStdExtE() ? CSR_XLEN_F64_Interrupt_RVE_SaveList
87 : CSR_XLEN_F64_Interrupt_SaveList;
88 if (Subtarget.hasStdExtF())
89 return Subtarget.hasStdExtE() ? CSR_XLEN_F32_Interrupt_RVE_SaveList
90 : CSR_XLEN_F32_Interrupt_SaveList;
91 return Subtarget.hasStdExtE() ? CSR_Interrupt_RVE_SaveList
92 : CSR_Interrupt_SaveList;
93 }
94
95 bool HasVectorCSR =
96 MF->getFunction().getCallingConv() == CallingConv::RISCV_VectorCall &&
97 Subtarget.hasVInstructions();
98
99 switch (Subtarget.getTargetABI()) {
100 default:
101 llvm_unreachable("Unrecognized ABI");
102 case RISCVABI::ABI_ILP32E:
103 case RISCVABI::ABI_LP64E:
104 return CSR_ILP32E_LP64E_SaveList;
105 case RISCVABI::ABI_ILP32:
106 case RISCVABI::ABI_LP64:
107 if (HasVectorCSR)
108 return CSR_ILP32_LP64_V_SaveList;
109 return CSR_ILP32_LP64_SaveList;
110 case RISCVABI::ABI_ILP32F:
111 case RISCVABI::ABI_LP64F:
112 if (HasVectorCSR)
113 return CSR_ILP32F_LP64F_V_SaveList;
114 return CSR_ILP32F_LP64F_SaveList;
115 case RISCVABI::ABI_ILP32D:
116 case RISCVABI::ABI_LP64D:
117 if (HasVectorCSR)
118 return CSR_ILP32D_LP64D_V_SaveList;
119 return CSR_ILP32D_LP64D_SaveList;
120 }
121}
122
123BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
124 const RISCVFrameLowering *TFI = getFrameLowering(MF);
125 BitVector Reserved(getNumRegs());
126 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
127
128 for (size_t Reg = 0; Reg < getNumRegs(); Reg++) {
129 // Mark any GPRs requested to be reserved as such
130 if (Subtarget.isRegisterReservedByUser(i: Reg))
131 markSuperRegs(RegisterSet&: Reserved, Reg);
132
133 // Mark all the registers defined as constant in TableGen as reserved.
134 if (isConstantPhysReg(PhysReg: Reg))
135 markSuperRegs(RegisterSet&: Reserved, Reg);
136 }
137
138 // Use markSuperRegs to ensure any register aliases are also reserved
139 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::X2_H); // sp
140 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::X3_H); // gp
141 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::X4_H); // tp
142 if (TFI->hasFP(MF))
143 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::X8_H); // fp
144 // Reserve the base register if we need to realign the stack and allocate
145 // variable-sized objects at runtime.
146 if (TFI->hasBP(MF))
147 markSuperRegs(RegisterSet&: Reserved, Reg: RISCVABI::getBPReg()); // bp
148
149 // Additionally reserve dummy register used to form the register pair
150 // beginning with 'x0' for instructions that take register pairs.
151 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::DUMMY_REG_PAIR_WITH_X0);
152
153 // There are only 16 GPRs for RVE.
154 if (Subtarget.hasStdExtE())
155 for (MCPhysReg Reg = RISCV::X16_H; Reg <= RISCV::X31_H; Reg++)
156 markSuperRegs(RegisterSet&: Reserved, Reg);
157
158 // V registers for code generation. We handle them manually.
159 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::VL);
160 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::VTYPE);
161 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::VXSAT);
162 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::VXRM);
163
164 // Floating point environment registers.
165 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::FRM);
166 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::FFLAGS);
167
168 // SiFive VCIX state registers.
169 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::SF_VCIX_STATE);
170
171 if (MF.getFunction().getCallingConv() == CallingConv::GRAAL) {
172 if (Subtarget.hasStdExtE())
173 reportFatalUsageError(reason: "Graal reserved registers do not exist in RVE");
174 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::X23_H);
175 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::X27_H);
176 }
177
178 // Shadow stack pointer.
179 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::SSP);
180
181 // XSfmmbase
182 for (MCPhysReg Reg = RISCV::T0; Reg <= RISCV::T15; Reg++)
183 markSuperRegs(RegisterSet&: Reserved, Reg);
184
185 assert(checkAllSuperRegsMarked(Reserved));
186 return Reserved;
187}
188
189bool RISCVRegisterInfo::isAsmClobberable(const MachineFunction &MF,
190 MCRegister PhysReg) const {
191 return !MF.getSubtarget().isRegisterReservedByUser(R: PhysReg);
192}
193
194const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const {
195 return CSR_NoRegs_RegMask;
196}
197
198void RISCVRegisterInfo::adjustReg(MachineBasicBlock &MBB,
199 MachineBasicBlock::iterator II,
200 const DebugLoc &DL, Register DestReg,
201 Register SrcReg, StackOffset Offset,
202 MachineInstr::MIFlag Flag,
203 MaybeAlign RequiredAlign) const {
204
205 if (DestReg == SrcReg && !Offset.getFixed() && !Offset.getScalable())
206 return;
207
208 MachineFunction &MF = *MBB.getParent();
209 MachineRegisterInfo &MRI = MF.getRegInfo();
210 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
211 const RISCVInstrInfo *TII = ST.getInstrInfo();
212
213 // Optimize compile time offset case
214 if (Offset.getScalable()) {
215 if (auto VLEN = ST.getRealVLen()) {
216 // 1. Multiply the number of v-slots by the (constant) length of register
217 const int64_t VLENB = *VLEN / 8;
218 assert(Offset.getScalable() % RISCV::RVVBytesPerBlock == 0 &&
219 "Reserve the stack by the multiple of one vector size.");
220 const int64_t NumOfVReg = Offset.getScalable() / 8;
221 const int64_t FixedOffset = NumOfVReg * VLENB;
222 if (!isInt<32>(x: FixedOffset)) {
223 reportFatalUsageError(
224 reason: "Frame size outside of the signed 32-bit range not supported");
225 }
226 Offset = StackOffset::getFixed(Fixed: FixedOffset + Offset.getFixed());
227 }
228 }
229
230 bool KillSrcReg = false;
231
232 if (Offset.getScalable()) {
233 unsigned ScalableAdjOpc = RISCV::ADD;
234 int64_t ScalableValue = Offset.getScalable();
235 if (ScalableValue < 0) {
236 ScalableValue = -ScalableValue;
237 ScalableAdjOpc = RISCV::SUB;
238 }
239 // Get vlenb and multiply vlen with the number of vector registers.
240 Register ScratchReg = DestReg;
241 if (DestReg == SrcReg)
242 ScratchReg = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
243
244 assert(ScalableValue > 0 && "There is no need to get VLEN scaled value.");
245 assert(ScalableValue % RISCV::RVVBytesPerBlock == 0 &&
246 "Reserve the stack by the multiple of one vector size.");
247 assert(isInt<32>(ScalableValue / RISCV::RVVBytesPerBlock) &&
248 "Expect the number of vector registers within 32-bits.");
249 uint32_t NumOfVReg = ScalableValue / RISCV::RVVBytesPerBlock;
250 // Only use vsetvli rather than vlenb if adjusting in the prologue or
251 // epilogue, otherwise it may disturb the VTYPE and VL status.
252 bool IsPrologueOrEpilogue =
253 Flag == MachineInstr::FrameSetup || Flag == MachineInstr::FrameDestroy;
254 bool UseVsetvliRatherThanVlenb =
255 IsPrologueOrEpilogue && ST.preferVsetvliOverReadVLENB();
256 if (UseVsetvliRatherThanVlenb && (NumOfVReg == 1 || NumOfVReg == 2 ||
257 NumOfVReg == 4 || NumOfVReg == 8)) {
258 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::PseudoReadVLENBViaVSETVLIX0),
259 DestReg: ScratchReg)
260 .addImm(Val: NumOfVReg)
261 .setMIFlag(Flag);
262 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: ScalableAdjOpc), DestReg)
263 .addReg(RegNo: SrcReg)
264 .addReg(RegNo: ScratchReg, Flags: RegState::Kill)
265 .setMIFlag(Flag);
266 } else {
267 if (UseVsetvliRatherThanVlenb)
268 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::PseudoReadVLENBViaVSETVLIX0),
269 DestReg: ScratchReg)
270 .addImm(Val: 1)
271 .setMIFlag(Flag);
272 else
273 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::PseudoReadVLENB), DestReg: ScratchReg)
274 .setMIFlag(Flag);
275
276 if (ScalableAdjOpc == RISCV::ADD && ST.hasStdExtZba() &&
277 (NumOfVReg == 2 || NumOfVReg == 4 || NumOfVReg == 8)) {
278 unsigned Opc = NumOfVReg == 2
279 ? RISCV::SH1ADD
280 : (NumOfVReg == 4 ? RISCV::SH2ADD : RISCV::SH3ADD);
281 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: Opc), DestReg)
282 .addReg(RegNo: ScratchReg, Flags: RegState::Kill)
283 .addReg(RegNo: SrcReg)
284 .setMIFlag(Flag);
285 } else {
286 TII->mulImm(MF, MBB, II, DL, DestReg: ScratchReg, Amt: NumOfVReg, Flag);
287 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: ScalableAdjOpc), DestReg)
288 .addReg(RegNo: SrcReg)
289 .addReg(RegNo: ScratchReg, Flags: RegState::Kill)
290 .setMIFlag(Flag);
291 }
292 }
293 SrcReg = DestReg;
294 KillSrcReg = true;
295 }
296
297 int64_t Val = Offset.getFixed();
298 if (DestReg == SrcReg && Val == 0)
299 return;
300
301 const uint64_t Align = RequiredAlign.valueOrOne().value();
302
303 if (isInt<12>(x: Val)) {
304 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::ADDI), DestReg)
305 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrcReg))
306 .addImm(Val)
307 .setMIFlag(Flag);
308 return;
309 }
310
311 // Use the QC_E_ADDI instruction from the Xqcilia extension that can take a
312 // signed 26-bit immediate.
313 if (ST.hasVendorXqcilia() && isInt<26>(x: Val)) {
314 // The one case where using this instruction is sub-optimal is if Val can be
315 // materialized with a single compressible LUI and following add/sub is also
316 // compressible. Avoid doing this if that is the case.
317 int Hi20 = (Val & 0xFFFFF000) >> 12;
318 bool IsCompressLUI =
319 ((Val & 0xFFF) == 0) && (Hi20 != 0) &&
320 (isUInt<5>(x: Hi20) || (Hi20 >= 0xfffe0 && Hi20 <= 0xfffff));
321 bool IsCompressAddSub =
322 (SrcReg == DestReg) &&
323 ((Val > 0 && RISCV::GPRNoX0RegClass.contains(Reg: SrcReg)) ||
324 (Val < 0 && RISCV::GPRCRegClass.contains(Reg: SrcReg)));
325
326 if (!(IsCompressLUI && IsCompressAddSub)) {
327 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::QC_E_ADDI), DestReg)
328 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrcReg))
329 .addImm(Val)
330 .setMIFlag(Flag);
331 return;
332 }
333 }
334
335 // Try to split the offset across two ADDIs. We need to keep the intermediate
336 // result aligned after each ADDI. We need to determine the maximum value we
337 // can put in each ADDI. In the negative direction, we can use -2048 which is
338 // always sufficiently aligned. In the positive direction, we need to find the
339 // largest 12-bit immediate that is aligned. Exclude -4096 since it can be
340 // created with LUI.
341 assert(Align < 2048 && "Required alignment too large");
342 int64_t MaxPosAdjStep = 2048 - Align;
343 if (Val > -4096 && Val <= (2 * MaxPosAdjStep)) {
344 int64_t FirstAdj = Val < 0 ? -2048 : MaxPosAdjStep;
345 Val -= FirstAdj;
346 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::ADDI), DestReg)
347 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrcReg))
348 .addImm(Val: FirstAdj)
349 .setMIFlag(Flag);
350 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::ADDI), DestReg)
351 .addReg(RegNo: DestReg, Flags: RegState::Kill)
352 .addImm(Val)
353 .setMIFlag(Flag);
354 return;
355 }
356
357 // Use shNadd if doing so lets us materialize a 12 bit immediate with a single
358 // instruction. This saves 1 instruction over the full lui/addi+add fallback
359 // path. We avoid anything which can be done with a single lui as it might
360 // be compressible. Note that the sh1add case is fully covered by the 2x addi
361 // case just above and is thus omitted.
362 if (ST.hasStdExtZba() && (Val & 0xFFF) != 0) {
363 unsigned Opc = 0;
364 if (isShiftedInt<12, 3>(x: Val)) {
365 Opc = RISCV::SH3ADD;
366 Val = Val >> 3;
367 } else if (isShiftedInt<12, 2>(x: Val)) {
368 Opc = RISCV::SH2ADD;
369 Val = Val >> 2;
370 }
371 if (Opc) {
372 Register ScratchReg = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
373 TII->movImm(MBB, MBBI: II, DL, DstReg: ScratchReg, Val, Flag);
374 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: Opc), DestReg)
375 .addReg(RegNo: ScratchReg, Flags: RegState::Kill)
376 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrcReg))
377 .setMIFlag(Flag);
378 return;
379 }
380 }
381
382 unsigned Opc = RISCV::ADD;
383 if (Val < 0) {
384 Val = -Val;
385 Opc = RISCV::SUB;
386 }
387
388 Register ScratchReg = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
389 TII->movImm(MBB, MBBI: II, DL, DstReg: ScratchReg, Val, Flag);
390 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: Opc), DestReg)
391 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrcReg))
392 .addReg(RegNo: ScratchReg, Flags: RegState::Kill)
393 .setMIFlag(Flag);
394}
395
396static std::tuple<RISCVVType::VLMUL, const TargetRegisterClass &, unsigned>
397getSpillReloadInfo(unsigned NumRemaining, uint16_t RegEncoding, bool IsSpill) {
398 if (NumRemaining >= 8 && RegEncoding % 8 == 0)
399 return {RISCVVType::LMUL_8, RISCV::VRM8RegClass,
400 IsSpill ? RISCV::VS8R_V : RISCV::VL8RE8_V};
401 if (NumRemaining >= 4 && RegEncoding % 4 == 0)
402 return {RISCVVType::LMUL_4, RISCV::VRM4RegClass,
403 IsSpill ? RISCV::VS4R_V : RISCV::VL4RE8_V};
404 if (NumRemaining >= 2 && RegEncoding % 2 == 0)
405 return {RISCVVType::LMUL_2, RISCV::VRM2RegClass,
406 IsSpill ? RISCV::VS2R_V : RISCV::VL2RE8_V};
407 return {RISCVVType::LMUL_1, RISCV::VRRegClass,
408 IsSpill ? RISCV::VS1R_V : RISCV::VL1RE8_V};
409}
410
411// Split a VSPILLx_Mx/VSPILLx_Mx pseudo into multiple whole register stores
412// separated by LMUL*VLENB bytes.
413void RISCVRegisterInfo::lowerSegmentSpillReload(MachineBasicBlock::iterator II,
414 bool IsSpill) const {
415 DebugLoc DL = II->getDebugLoc();
416 MachineBasicBlock &MBB = *II->getParent();
417 MachineFunction &MF = *MBB.getParent();
418 MachineRegisterInfo &MRI = MF.getRegInfo();
419 const RISCVSubtarget &STI = MF.getSubtarget<RISCVSubtarget>();
420 const TargetInstrInfo *TII = STI.getInstrInfo();
421 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
422
423 auto ZvlssegInfo = RISCV::isRVVSpillForZvlsseg(Opcode: II->getOpcode());
424 unsigned NF = ZvlssegInfo->first;
425 unsigned LMUL = ZvlssegInfo->second;
426 unsigned NumRegs = NF * LMUL;
427 assert(NumRegs <= 8 && "Invalid NF/LMUL combinations.");
428
429 Register Reg = II->getOperand(i: 0).getReg();
430 uint16_t RegEncoding = TRI->getEncodingValue(Reg);
431 Register Base = II->getOperand(i: 1).getReg();
432 bool IsBaseKill = II->getOperand(i: 1).isKill();
433 Register NewBase = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
434
435 auto *OldMMO = *(II->memoperands_begin());
436 LocationSize OldLoc = OldMMO->getSize();
437 assert(OldLoc.isPrecise() && OldLoc.getValue().isKnownMultipleOf(NF));
438 TypeSize VRegSize = OldLoc.getValue().divideCoefficientBy(RHS: NumRegs);
439
440 Register VLENB = 0;
441 unsigned VLENBShift = 0;
442 unsigned PrevHandledNum = 0;
443 unsigned I = 0;
444 while (I != NumRegs) {
445 auto [LMulHandled, RegClass, Opcode] =
446 getSpillReloadInfo(NumRemaining: NumRegs - I, RegEncoding, IsSpill);
447 auto [RegNumHandled, _] = RISCVVType::decodeVLMUL(VLMul: LMulHandled);
448 bool IsLast = I + RegNumHandled == NumRegs;
449 if (PrevHandledNum) {
450 Register Step;
451 // Optimize for constant VLEN.
452 if (auto VLEN = STI.getRealVLen()) {
453 int64_t Offset = *VLEN / 8 * PrevHandledNum;
454 Step = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
455 STI.getInstrInfo()->movImm(MBB, MBBI: II, DL, DstReg: Step, Val: Offset);
456 } else {
457 if (!VLENB) {
458 VLENB = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
459 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::PseudoReadVLENB), DestReg: VLENB);
460 }
461 uint32_t ShiftAmount = Log2_32(Value: PrevHandledNum);
462 // To avoid using an extra register, we shift the VLENB register and
463 // remember how much it has been shifted. We can then use relative
464 // shifts to adjust to the desired shift amount.
465 if (VLENBShift > ShiftAmount) {
466 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::SRLI), DestReg: VLENB)
467 .addReg(RegNo: VLENB, Flags: RegState::Kill)
468 .addImm(Val: VLENBShift - ShiftAmount);
469 } else if (VLENBShift < ShiftAmount) {
470 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::SLLI), DestReg: VLENB)
471 .addReg(RegNo: VLENB, Flags: RegState::Kill)
472 .addImm(Val: ShiftAmount - VLENBShift);
473 }
474 VLENBShift = ShiftAmount;
475 Step = VLENB;
476 }
477
478 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::ADD), DestReg: NewBase)
479 .addReg(RegNo: Base, Flags: getKillRegState(B: I != 0 || IsBaseKill))
480 .addReg(RegNo: Step, Flags: getKillRegState(B: Step != VLENB || IsLast));
481 Base = NewBase;
482 }
483
484 MCRegister ActualReg = findVRegWithEncoding(RegClass, Encoding: RegEncoding);
485 MachineInstrBuilder MIB =
486 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode))
487 .addReg(RegNo: ActualReg, Flags: getDefRegState(B: !IsSpill))
488 .addReg(RegNo: Base, Flags: getKillRegState(B: IsLast))
489 .addMemOperand(MMO: MF.getMachineMemOperand(MMO: OldMMO, Offset: OldMMO->getOffset(),
490 Size: VRegSize * RegNumHandled));
491
492 // Adding implicit-use of super register to describe we are using part of
493 // super register, that prevents machine verifier complaining when part of
494 // subreg is undef, see comment in MachineVerifier::checkLiveness for more
495 // detail.
496 if (IsSpill)
497 MIB.addReg(RegNo: Reg, Flags: RegState::Implicit);
498
499 PrevHandledNum = RegNumHandled;
500 RegEncoding += RegNumHandled;
501 I += RegNumHandled;
502 }
503 II->eraseFromParent();
504}
505
506bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
507 int SPAdj, unsigned FIOperandNum,
508 RegScavenger *RS) const {
509 assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
510
511 MachineInstr &MI = *II;
512 MachineFunction &MF = *MI.getParent()->getParent();
513 MachineRegisterInfo &MRI = MF.getRegInfo();
514 DebugLoc DL = MI.getDebugLoc();
515
516 int FrameIndex = MI.getOperand(i: FIOperandNum).getIndex();
517 Register FrameReg;
518 StackOffset Offset =
519 getFrameLowering(MF)->getFrameIndexReference(MF, FI: FrameIndex, FrameReg);
520 bool IsRVVSpill = RISCV::isRVVSpill(MI);
521 if (!IsRVVSpill)
522 Offset += StackOffset::getFixed(Fixed: MI.getOperand(i: FIOperandNum + 1).getImm());
523
524 if (!isInt<32>(x: Offset.getFixed())) {
525 reportFatalUsageError(
526 reason: "Frame offsets outside of the signed 32-bit range not supported");
527 }
528
529 if (!IsRVVSpill) {
530 int64_t Val = Offset.getFixed();
531 int64_t Lo12 = SignExtend64<12>(x: Val);
532 unsigned Opc = MI.getOpcode();
533
534 if (Opc == RISCV::ADDI && !isInt<12>(x: Val)) {
535 // We chose to emit the canonical immediate sequence rather than folding
536 // the offset into the using add under the theory that doing so doesn't
537 // save dynamic instruction count and some target may fuse the canonical
538 // 32 bit immediate sequence. We still need to clear the portion of the
539 // offset encoded in the immediate.
540 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: 0);
541 } else if ((Opc == RISCV::PREFETCH_I || Opc == RISCV::PREFETCH_R ||
542 Opc == RISCV::PREFETCH_W) &&
543 (Lo12 & 0b11111) != 0) {
544 // Prefetch instructions require the offset to be 32 byte aligned.
545 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: 0);
546 } else if (Opc == RISCV::MIPS_PREF && !isUInt<9>(x: Val)) {
547 // MIPS Prefetch instructions require the offset to be 9 bits encoded.
548 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: 0);
549 } else if ((Opc == RISCV::PseudoRV32ZdinxLD ||
550 Opc == RISCV::PseudoRV32ZdinxSD ||
551 Opc == RISCV::PseudoLD_RV32_OPT ||
552 Opc == RISCV::PseudoSD_RV32_OPT) &&
553 Lo12 >= 2044) {
554 // This instruction will/might be split into 2 instructions. The second
555 // instruction will add 4 to the immediate. If that would overflow 12
556 // bits, we can't fold the offset.
557 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: 0);
558 } else {
559 // We can encode an add with 12 bit signed immediate in the immediate
560 // operand of our user instruction. As a result, the remaining
561 // offset can by construction, at worst, a LUI and a ADD.
562 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: Lo12);
563 Offset = StackOffset::get(Fixed: (uint64_t)Val - (uint64_t)Lo12,
564 Scalable: Offset.getScalable());
565 }
566 }
567
568 if (Offset.getScalable() || Offset.getFixed()) {
569 Register DestReg;
570 if (MI.getOpcode() == RISCV::ADDI)
571 DestReg = MI.getOperand(i: 0).getReg();
572 else
573 DestReg = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
574 adjustReg(MBB&: *II->getParent(), II, DL, DestReg, SrcReg: FrameReg, Offset,
575 Flag: MachineInstr::NoFlags, RequiredAlign: std::nullopt);
576 MI.getOperand(i: FIOperandNum).ChangeToRegister(Reg: DestReg, /*IsDef*/isDef: false,
577 /*IsImp*/isImp: false,
578 /*IsKill*/isKill: true);
579 } else {
580 MI.getOperand(i: FIOperandNum).ChangeToRegister(Reg: FrameReg, /*IsDef*/isDef: false,
581 /*IsImp*/isImp: false,
582 /*IsKill*/isKill: false);
583 }
584
585 // If after materializing the adjustment, we have a pointless ADDI, remove it
586 if (MI.getOpcode() == RISCV::ADDI &&
587 MI.getOperand(i: 0).getReg() == MI.getOperand(i: 1).getReg() &&
588 MI.getOperand(i: 2).getImm() == 0) {
589 MI.eraseFromParent();
590 return true;
591 }
592
593 // Handle spill/fill of synthetic register classes for segment operations to
594 // ensure correctness in the edge case one gets spilled.
595 switch (MI.getOpcode()) {
596 case RISCV::PseudoVSPILL2_M1:
597 case RISCV::PseudoVSPILL2_M2:
598 case RISCV::PseudoVSPILL2_M4:
599 case RISCV::PseudoVSPILL3_M1:
600 case RISCV::PseudoVSPILL3_M2:
601 case RISCV::PseudoVSPILL4_M1:
602 case RISCV::PseudoVSPILL4_M2:
603 case RISCV::PseudoVSPILL5_M1:
604 case RISCV::PseudoVSPILL6_M1:
605 case RISCV::PseudoVSPILL7_M1:
606 case RISCV::PseudoVSPILL8_M1:
607 lowerSegmentSpillReload(II, /*IsSpill=*/true);
608 return true;
609 case RISCV::PseudoVRELOAD2_M1:
610 case RISCV::PseudoVRELOAD2_M2:
611 case RISCV::PseudoVRELOAD2_M4:
612 case RISCV::PseudoVRELOAD3_M1:
613 case RISCV::PseudoVRELOAD3_M2:
614 case RISCV::PseudoVRELOAD4_M1:
615 case RISCV::PseudoVRELOAD4_M2:
616 case RISCV::PseudoVRELOAD5_M1:
617 case RISCV::PseudoVRELOAD6_M1:
618 case RISCV::PseudoVRELOAD7_M1:
619 case RISCV::PseudoVRELOAD8_M1:
620 lowerSegmentSpillReload(II, /*IsSpill=*/false);
621 return true;
622 }
623
624 return false;
625}
626
627bool RISCVRegisterInfo::requiresVirtualBaseRegisters(
628 const MachineFunction &MF) const {
629 return true;
630}
631
632// Returns true if the instruction's frame index reference would be better
633// served by a base register other than FP or SP.
634// Used by LocalStackSlotAllocation pass to determine which frame index
635// references it should create new base registers for.
636bool RISCVRegisterInfo::needsFrameBaseReg(MachineInstr *MI,
637 int64_t Offset) const {
638 unsigned FIOperandNum = 0;
639 for (; !MI->getOperand(i: FIOperandNum).isFI(); FIOperandNum++)
640 assert(FIOperandNum < MI->getNumOperands() &&
641 "Instr doesn't have FrameIndex operand");
642
643 // For RISC-V, The machine instructions that include a FrameIndex operand
644 // are load/store, ADDI instructions.
645 unsigned MIFrm = RISCVII::getFormat(TSFlags: MI->getDesc().TSFlags);
646 if (MIFrm != RISCVII::InstFormatI && MIFrm != RISCVII::InstFormatS)
647 return false;
648 // We only generate virtual base registers for loads and stores, so
649 // return false for everything else.
650 if (!MI->mayLoad() && !MI->mayStore())
651 return false;
652
653 const MachineFunction &MF = *MI->getMF();
654 const MachineFrameInfo &MFI = MF.getFrameInfo();
655 const RISCVFrameLowering *TFI = getFrameLowering(MF);
656 const MachineRegisterInfo &MRI = MF.getRegInfo();
657
658 if (TFI->hasFP(MF) && !shouldRealignStack(MF)) {
659 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
660 // Estimate the stack size used to store callee saved registers(
661 // excludes reserved registers).
662 unsigned CalleeSavedSize = 0;
663 for (const MCPhysReg *R = MRI.getCalleeSavedRegs(); MCPhysReg Reg = *R;
664 ++R) {
665 if (Subtarget.isRegisterReservedByUser(i: Reg))
666 continue;
667
668 if (RISCV::GPRRegClass.contains(Reg))
669 CalleeSavedSize += getSpillSize(RC: RISCV::GPRRegClass);
670 else if (RISCV::FPR64RegClass.contains(Reg))
671 CalleeSavedSize += getSpillSize(RC: RISCV::FPR64RegClass);
672 else if (RISCV::FPR32RegClass.contains(Reg))
673 CalleeSavedSize += getSpillSize(RC: RISCV::FPR32RegClass);
674 // Ignore vector registers.
675 }
676
677 int64_t MaxFPOffset = Offset - CalleeSavedSize;
678 return !isFrameOffsetLegal(MI, BaseReg: RISCV::X8, Offset: MaxFPOffset);
679 }
680
681 // Assume 128 bytes spill slots size to estimate the maximum possible
682 // offset relative to the stack pointer.
683 // FIXME: The 128 is copied from ARM. We should run some statistics and pick a
684 // real one for RISC-V.
685 int64_t MaxSPOffset = Offset + 128;
686 MaxSPOffset += MFI.getLocalFrameSize();
687 return !isFrameOffsetLegal(MI, BaseReg: RISCV::X2, Offset: MaxSPOffset);
688}
689
690// Determine whether a given base register plus offset immediate is
691// encodable to resolve a frame index.
692bool RISCVRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
693 Register BaseReg,
694 int64_t Offset) const {
695 unsigned FIOperandNum = 0;
696 while (!MI->getOperand(i: FIOperandNum).isFI()) {
697 FIOperandNum++;
698 assert(FIOperandNum < MI->getNumOperands() &&
699 "Instr does not have a FrameIndex operand!");
700 }
701
702 Offset += getFrameIndexInstrOffset(MI, Idx: FIOperandNum);
703 return isInt<12>(x: Offset);
704}
705
706// Insert defining instruction(s) for a pointer to FrameIdx before
707// insertion point I.
708// Return materialized frame pointer.
709Register RISCVRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
710 int FrameIdx,
711 int64_t Offset) const {
712 MachineBasicBlock::iterator MBBI = MBB->begin();
713 DebugLoc DL;
714 if (MBBI != MBB->end())
715 DL = MBBI->getDebugLoc();
716 MachineFunction *MF = MBB->getParent();
717 MachineRegisterInfo &MFI = MF->getRegInfo();
718 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
719
720 Register BaseReg = MFI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
721 BuildMI(BB&: *MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: RISCV::ADDI), DestReg: BaseReg)
722 .addFrameIndex(Idx: FrameIdx)
723 .addImm(Val: Offset);
724 return BaseReg;
725}
726
727// Resolve a frame index operand of an instruction to reference the
728// indicated base register plus offset instead.
729void RISCVRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg,
730 int64_t Offset) const {
731 unsigned FIOperandNum = 0;
732 while (!MI.getOperand(i: FIOperandNum).isFI()) {
733 FIOperandNum++;
734 assert(FIOperandNum < MI.getNumOperands() &&
735 "Instr does not have a FrameIndex operand!");
736 }
737
738 Offset += getFrameIndexInstrOffset(MI: &MI, Idx: FIOperandNum);
739 // FrameIndex Operands are always represented as a
740 // register followed by an immediate.
741 MI.getOperand(i: FIOperandNum).ChangeToRegister(Reg: BaseReg, isDef: false);
742 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: Offset);
743}
744
745// Get the offset from the referenced frame index in the instruction,
746// if there is one.
747int64_t RISCVRegisterInfo::getFrameIndexInstrOffset(const MachineInstr *MI,
748 int Idx) const {
749 assert((RISCVII::getFormat(MI->getDesc().TSFlags) == RISCVII::InstFormatI ||
750 RISCVII::getFormat(MI->getDesc().TSFlags) == RISCVII::InstFormatS) &&
751 "The MI must be I or S format.");
752 assert(MI->getOperand(Idx).isFI() && "The Idx'th operand of MI is not a "
753 "FrameIndex operand");
754 return MI->getOperand(i: Idx + 1).getImm();
755}
756
757Register RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
758 const TargetFrameLowering *TFI = getFrameLowering(MF);
759 return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
760}
761
762StringRef RISCVRegisterInfo::getRegAsmName(MCRegister Reg) const {
763 if (Reg == RISCV::SF_VCIX_STATE)
764 return "sf.vcix_state";
765 return TargetRegisterInfo::getRegAsmName(Reg);
766}
767
768const uint32_t *
769RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF,
770 CallingConv::ID CC) const {
771 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
772
773 if (CC == CallingConv::GHC)
774 return CSR_NoRegs_RegMask;
775 RISCVABI::ABI ABI = Subtarget.getTargetABI();
776 if (CC == CallingConv::PreserveMost) {
777 if (ABI == RISCVABI::ABI_ILP32E || ABI == RISCVABI::ABI_LP64E)
778 return CSR_RT_MostRegs_RVE_RegMask;
779 return CSR_RT_MostRegs_RegMask;
780 }
781 switch (ABI) {
782 default:
783 llvm_unreachable("Unrecognized ABI");
784 case RISCVABI::ABI_ILP32E:
785 case RISCVABI::ABI_LP64E:
786 return CSR_ILP32E_LP64E_RegMask;
787 case RISCVABI::ABI_ILP32:
788 case RISCVABI::ABI_LP64:
789 if (CC == CallingConv::RISCV_VectorCall)
790 return CSR_ILP32_LP64_V_RegMask;
791 return CSR_ILP32_LP64_RegMask;
792 case RISCVABI::ABI_ILP32F:
793 case RISCVABI::ABI_LP64F:
794 if (CC == CallingConv::RISCV_VectorCall)
795 return CSR_ILP32F_LP64F_V_RegMask;
796 return CSR_ILP32F_LP64F_RegMask;
797 case RISCVABI::ABI_ILP32D:
798 case RISCVABI::ABI_LP64D:
799 if (CC == CallingConv::RISCV_VectorCall)
800 return CSR_ILP32D_LP64D_V_RegMask;
801 return CSR_ILP32D_LP64D_RegMask;
802 }
803}
804
805const TargetRegisterClass *
806RISCVRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
807 const MachineFunction &) const {
808 if (RC == &RISCV::VMV0RegClass)
809 return &RISCV::VRRegClass;
810 if (RC == &RISCV::VRNoV0RegClass)
811 return &RISCV::VRRegClass;
812 if (RC == &RISCV::VRM2NoV0RegClass)
813 return &RISCV::VRM2RegClass;
814 if (RC == &RISCV::VRM4NoV0RegClass)
815 return &RISCV::VRM4RegClass;
816 if (RC == &RISCV::VRM8NoV0RegClass)
817 return &RISCV::VRM8RegClass;
818 return RC;
819}
820
821void RISCVRegisterInfo::getOffsetOpcodes(const StackOffset &Offset,
822 SmallVectorImpl<uint64_t> &Ops) const {
823 // VLENB is the length of a vector register in bytes. We use <vscale x 8 x i8>
824 // to represent one vector register. The dwarf offset is
825 // VLENB * scalable_offset / 8.
826 assert(Offset.getScalable() % 8 == 0 && "Invalid frame offset");
827
828 // Add fixed-sized offset using existing DIExpression interface.
829 DIExpression::appendOffset(Ops, Offset: Offset.getFixed());
830
831 unsigned VLENB = getDwarfRegNum(Reg: RISCV::VLENB, isEH: true);
832 int64_t VLENBSized = Offset.getScalable() / 8;
833 if (VLENBSized > 0) {
834 Ops.push_back(Elt: dwarf::DW_OP_constu);
835 Ops.push_back(Elt: VLENBSized);
836 Ops.append(IL: {dwarf::DW_OP_bregx, VLENB, 0ULL});
837 Ops.push_back(Elt: dwarf::DW_OP_mul);
838 Ops.push_back(Elt: dwarf::DW_OP_plus);
839 } else if (VLENBSized < 0) {
840 Ops.push_back(Elt: dwarf::DW_OP_constu);
841 Ops.push_back(Elt: -VLENBSized);
842 Ops.append(IL: {dwarf::DW_OP_bregx, VLENB, 0ULL});
843 Ops.push_back(Elt: dwarf::DW_OP_mul);
844 Ops.push_back(Elt: dwarf::DW_OP_minus);
845 }
846}
847
848unsigned
849RISCVRegisterInfo::getRegisterCostTableIndex(const MachineFunction &MF) const {
850 return MF.getSubtarget<RISCVSubtarget>().hasStdExtZca() && !DisableCostPerUse
851 ? 1
852 : 0;
853}
854
855float RISCVRegisterInfo::getSpillWeightScaleFactor(
856 const TargetRegisterClass *RC) const {
857 return getRegClassWeight(RC).RegWeight;
858}
859
860// Add two address hints to improve chances of being able to use a compressed
861// instruction.
862bool RISCVRegisterInfo::getRegAllocationHints(
863 Register VirtReg, ArrayRef<MCPhysReg> Order,
864 SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF,
865 const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
866 const MachineRegisterInfo *MRI = &MF.getRegInfo();
867 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
868
869 // Handle RegPairEven/RegPairOdd hints for Zilsd register pairs
870 std::pair<unsigned, Register> Hint = MRI->getRegAllocationHint(VReg: VirtReg);
871 unsigned HintType = Hint.first;
872 Register Partner = Hint.second;
873
874 MCRegister TargetReg;
875 if (HintType == RISCVRI::RegPairEven || HintType == RISCVRI::RegPairOdd) {
876 // Check if we want the even or odd register of a consecutive pair
877 bool WantOdd = (HintType == RISCVRI::RegPairOdd);
878
879 // First priority: Check if partner is already allocated
880 if (Partner.isVirtual() && VRM && VRM->hasPhys(virtReg: Partner)) {
881 MCRegister PartnerPhys = VRM->getPhys(virtReg: Partner);
882 // Calculate the exact register we need for consecutive pairing
883 TargetReg = PartnerPhys.id() + (WantOdd ? 1 : -1);
884
885 // Verify it's valid and available
886 if (RISCV::GPRRegClass.contains(Reg: TargetReg) &&
887 is_contained(Range&: Order, Element: TargetReg))
888 Hints.push_back(Elt: TargetReg.id());
889 }
890
891 // Second priority: Try to find consecutive register pairs in the allocation
892 // order
893 for (MCPhysReg PhysReg : Order) {
894 // Don't add the hint if we already added above.
895 if (TargetReg == PhysReg)
896 continue;
897
898 unsigned RegNum = getEncodingValue(Reg: PhysReg);
899 // Check if this register matches the even/odd requirement
900 bool IsOdd = (RegNum % 2 != 0);
901
902 // Don't provide hints that are paired to a reserved register.
903 MCRegister Paired = PhysReg + (IsOdd ? -1 : 1);
904 if (WantOdd == IsOdd && !MRI->isReserved(PhysReg: Paired))
905 Hints.push_back(Elt: PhysReg);
906 }
907 }
908
909 bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
910 VirtReg, Order, Hints, MF, VRM, Matrix);
911
912 if (!VRM || DisableRegAllocHints)
913 return BaseImplRetVal;
914
915 // Add any two address hints after any copy hints.
916 SmallSet<Register, 4> TwoAddrHints;
917
918 auto tryAddHint = [&](const MachineOperand &VRRegMO, const MachineOperand &MO,
919 bool NeedGPRC) -> void {
920 Register Reg = MO.getReg();
921 Register PhysReg = Reg.isPhysical() ? Reg : Register(VRM->getPhys(virtReg: Reg));
922 // TODO: Support GPRPair subregisters? Need to be careful with even/odd
923 // registers. If the virtual register is an odd register of a pair and the
924 // physical register is even (or vice versa), we should not add the hint.
925 if (PhysReg && (!NeedGPRC || RISCV::GPRCRegClass.contains(Reg: PhysReg)) &&
926 !MO.getSubReg() && !VRRegMO.getSubReg()) {
927 if (!MRI->isReserved(PhysReg) && !is_contained(Range&: Hints, Element: PhysReg))
928 TwoAddrHints.insert(V: PhysReg);
929 }
930 };
931
932 // This is all of the compressible binary instructions. If an instruction
933 // needs GPRC register class operands \p NeedGPRC will be set to true.
934 auto isCompressible = [&Subtarget](const MachineInstr &MI, bool &NeedGPRC) {
935 NeedGPRC = false;
936 switch (MI.getOpcode()) {
937 default:
938 return false;
939 case RISCV::AND:
940 case RISCV::OR:
941 case RISCV::XOR:
942 case RISCV::SUB:
943 case RISCV::ADDW:
944 case RISCV::SUBW:
945 NeedGPRC = true;
946 return true;
947 case RISCV::ANDI: {
948 NeedGPRC = true;
949 if (!MI.getOperand(i: 2).isImm())
950 return false;
951 int64_t Imm = MI.getOperand(i: 2).getImm();
952 if (isInt<6>(x: Imm))
953 return true;
954 // c.zext.b
955 return Subtarget.hasStdExtZcb() && Imm == 255;
956 }
957 case RISCV::SRAI:
958 case RISCV::SRLI:
959 NeedGPRC = true;
960 return true;
961 case RISCV::ADD:
962 case RISCV::SLLI:
963 return true;
964 case RISCV::ADDI:
965 case RISCV::ADDIW:
966 return MI.getOperand(i: 2).isImm() && isInt<6>(x: MI.getOperand(i: 2).getImm());
967 case RISCV::MUL:
968 case RISCV::SEXT_B:
969 case RISCV::SEXT_H:
970 case RISCV::ZEXT_H_RV32:
971 case RISCV::ZEXT_H_RV64:
972 // c.mul, c.sext.b, c.sext.h, c.zext.h
973 NeedGPRC = true;
974 return Subtarget.hasStdExtZcb();
975 case RISCV::ADD_UW:
976 // c.zext.w
977 NeedGPRC = true;
978 return Subtarget.hasStdExtZcb() && MI.getOperand(i: 2).isReg() &&
979 MI.getOperand(i: 2).getReg() == RISCV::X0;
980 case RISCV::XORI:
981 // c.not
982 NeedGPRC = true;
983 return Subtarget.hasStdExtZcb() && MI.getOperand(i: 2).isImm() &&
984 MI.getOperand(i: 2).getImm() == -1;
985 case RISCV::QC_EXTU:
986 return MI.getOperand(i: 2).getImm() >= 6 && MI.getOperand(i: 3).getImm() == 0;
987 case RISCV::BSETI:
988 case RISCV::BEXTI:
989 // qc.c.bseti, qc.c.bexti
990 NeedGPRC = true;
991 return Subtarget.hasVendorXqcibm() && MI.getOperand(i: 2).getImm() != 0;
992 }
993 };
994
995 // Returns true if this operand is compressible. For non-registers it always
996 // returns true. Immediate range was already checked in isCompressible.
997 // For registers, it checks if the register is a GPRC register. reg-reg
998 // instructions that require GPRC need all register operands to be GPRC.
999 auto isCompressibleOpnd = [&](const MachineOperand &MO) {
1000 if (!MO.isReg())
1001 return true;
1002 Register Reg = MO.getReg();
1003 Register PhysReg = Reg.isPhysical() ? Reg : Register(VRM->getPhys(virtReg: Reg));
1004 return PhysReg && RISCV::GPRCRegClass.contains(Reg: PhysReg);
1005 };
1006
1007 for (auto &MO : MRI->reg_nodbg_operands(Reg: VirtReg)) {
1008 const MachineInstr &MI = *MO.getParent();
1009 unsigned OpIdx = MO.getOperandNo();
1010 bool NeedGPRC;
1011 if (isCompressible(MI, NeedGPRC)) {
1012 if (OpIdx == 0 && MI.getOperand(i: 1).isReg()) {
1013 if (!NeedGPRC || MI.getNumExplicitOperands() < 3 ||
1014 MI.getOpcode() == RISCV::ADD_UW ||
1015 isCompressibleOpnd(MI.getOperand(i: 2)))
1016 tryAddHint(MO, MI.getOperand(i: 1), NeedGPRC);
1017 if (MI.isCommutable() && MI.getOperand(i: 2).isReg() &&
1018 (!NeedGPRC || isCompressibleOpnd(MI.getOperand(i: 1))))
1019 tryAddHint(MO, MI.getOperand(i: 2), NeedGPRC);
1020 } else if (OpIdx == 1 && (!NeedGPRC || MI.getNumExplicitOperands() < 3 ||
1021 isCompressibleOpnd(MI.getOperand(i: 2)))) {
1022 tryAddHint(MO, MI.getOperand(i: 0), NeedGPRC);
1023 } else if (MI.isCommutable() && OpIdx == 2 &&
1024 (!NeedGPRC || isCompressibleOpnd(MI.getOperand(i: 1)))) {
1025 tryAddHint(MO, MI.getOperand(i: 0), NeedGPRC);
1026 }
1027 }
1028
1029 // Add a hint if it would allow auipc/lui+addi(w) fusion. We do this even
1030 // without the fusions explicitly enabled as the impact is rarely negative
1031 // and some cores do implement this fusion.
1032 if ((MI.getOpcode() == RISCV::ADDIW || MI.getOpcode() == RISCV::ADDI) &&
1033 MI.getOperand(i: 1).isReg()) {
1034 const MachineBasicBlock &MBB = *MI.getParent();
1035 MachineBasicBlock::const_iterator I = MI.getIterator();
1036 // Is the previous instruction a LUI or AUIPC that can be fused?
1037 if (I != MBB.begin()) {
1038 I = skipDebugInstructionsBackward(It: std::prev(x: I), Begin: MBB.begin());
1039 if ((I->getOpcode() == RISCV::LUI || I->getOpcode() == RISCV::AUIPC) &&
1040 I->getOperand(i: 0).getReg() == MI.getOperand(i: 1).getReg()) {
1041 if (OpIdx == 0)
1042 tryAddHint(MO, MI.getOperand(i: 1), /*NeedGPRC=*/false);
1043 else
1044 tryAddHint(MO, MI.getOperand(i: 0), /*NeedGPRC=*/false);
1045 }
1046 }
1047 }
1048 }
1049
1050 for (MCPhysReg OrderReg : Order)
1051 if (TwoAddrHints.count(V: OrderReg))
1052 Hints.push_back(Elt: OrderReg);
1053
1054 return BaseImplRetVal;
1055}
1056
1057void RISCVRegisterInfo::updateRegAllocHint(Register Reg, Register NewReg,
1058 MachineFunction &MF) const {
1059 MachineRegisterInfo *MRI = &MF.getRegInfo();
1060 std::pair<unsigned, Register> Hint = MRI->getRegAllocationHint(VReg: Reg);
1061
1062 // Handle RegPairEven/RegPairOdd hints for Zilsd register pairs
1063 if ((Hint.first == RISCVRI::RegPairOdd ||
1064 Hint.first == RISCVRI::RegPairEven) &&
1065 Hint.second.isVirtual()) {
1066 // If 'Reg' is one of the even/odd register pair and it's now changed
1067 // (e.g. coalesced) into a different register, the other register of the
1068 // pair allocation hint must be updated to reflect the relationship change.
1069 Register Partner = Hint.second;
1070 std::pair<unsigned, Register> PartnerHint =
1071 MRI->getRegAllocationHint(VReg: Partner);
1072
1073 // Make sure partner still points to us
1074 if (PartnerHint.second == Reg) {
1075 // Update partner to point to NewReg instead of Reg
1076 MRI->setRegAllocationHint(VReg: Partner, Type: PartnerHint.first, PrefReg: NewReg);
1077
1078 // If NewReg is virtual, set up the reciprocal hint
1079 // NewReg takes over Reg's role, so it gets the SAME hint type as Reg
1080 if (NewReg.isVirtual())
1081 MRI->setRegAllocationHint(VReg: NewReg, Type: Hint.first, PrefReg: Partner);
1082 }
1083 }
1084}
1085
1086Register
1087RISCVRegisterInfo::findVRegWithEncoding(const TargetRegisterClass &RegClass,
1088 uint16_t Encoding) const {
1089 MCRegister Reg = RISCV::V0 + Encoding;
1090 if (RISCVRI::getLMul(TSFlags: RegClass.TSFlags) == RISCVVType::LMUL_1)
1091 return Reg;
1092 return getMatchingSuperReg(Reg, SubIdx: RISCV::sub_vrm1_0, RC: &RegClass);
1093}
1094