1//===-- RISCVRegisterInfo.cpp - RISC-V Register Information -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the RISC-V implementation of the TargetRegisterInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVRegisterInfo.h"
14#include "RISCV.h"
15#include "RISCVSubtarget.h"
16#include "llvm/ADT/SmallSet.h"
17#include "llvm/BinaryFormat/Dwarf.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/RegisterScavenging.h"
22#include "llvm/CodeGen/TargetFrameLowering.h"
23#include "llvm/CodeGen/TargetInstrInfo.h"
24#include "llvm/IR/DebugInfoMetadata.h"
25#include "llvm/Support/ErrorHandling.h"
26
27#define GET_REGINFO_TARGET_DESC
28#include "RISCVGenRegisterInfo.inc"
29
30using namespace llvm;
31
32static cl::opt<bool> DisableCostPerUse("riscv-disable-cost-per-use",
33 cl::init(Val: false), cl::Hidden);
34static cl::opt<bool>
35 DisableRegAllocHints("riscv-disable-regalloc-hints", cl::Hidden,
36 cl::init(Val: false),
37 cl::desc("Disable two address hints for register "
38 "allocation"));
39
40static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");
41static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive");
42static_assert(RISCV::F1_H == RISCV::F0_H + 1, "Register list not consecutive");
43static_assert(RISCV::F31_H == RISCV::F0_H + 31,
44 "Register list not consecutive");
45static_assert(RISCV::F1_F == RISCV::F0_F + 1, "Register list not consecutive");
46static_assert(RISCV::F31_F == RISCV::F0_F + 31,
47 "Register list not consecutive");
48static_assert(RISCV::F1_D == RISCV::F0_D + 1, "Register list not consecutive");
49static_assert(RISCV::F31_D == RISCV::F0_D + 31,
50 "Register list not consecutive");
51static_assert(RISCV::F1_Q == RISCV::F0_Q + 1, "Register list not consecutive");
52static_assert(RISCV::F31_Q == RISCV::F0_Q + 31,
53 "Register list not consecutive");
54static_assert(RISCV::V1 == RISCV::V0 + 1, "Register list not consecutive");
55static_assert(RISCV::V31 == RISCV::V0 + 31, "Register list not consecutive");
56
57RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode)
58 : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
59 /*PC*/0, HwMode) {}
60
61const MCPhysReg *
62RISCVRegisterInfo::getIPRACSRegs(const MachineFunction *MF) const {
63 return CSR_IPRA_SaveList;
64}
65
66const MCPhysReg *
67RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
68 auto &Subtarget = MF->getSubtarget<RISCVSubtarget>();
69 if (MF->getFunction().getCallingConv() == CallingConv::GHC)
70 return CSR_NoRegs_SaveList;
71 if (MF->getFunction().getCallingConv() == CallingConv::PreserveMost)
72 return Subtarget.hasStdExtE() ? CSR_RT_MostRegs_RVE_SaveList
73 : CSR_RT_MostRegs_SaveList;
74 if (MF->getFunction().hasFnAttribute(Kind: "interrupt")) {
75 if (Subtarget.hasVInstructions()) {
76 if (Subtarget.hasStdExtD())
77 return Subtarget.hasStdExtE() ? CSR_XLEN_F64_V_Interrupt_RVE_SaveList
78 : CSR_XLEN_F64_V_Interrupt_SaveList;
79 if (Subtarget.hasStdExtF())
80 return Subtarget.hasStdExtE() ? CSR_XLEN_F32_V_Interrupt_RVE_SaveList
81 : CSR_XLEN_F32_V_Interrupt_SaveList;
82 return Subtarget.hasStdExtE() ? CSR_XLEN_V_Interrupt_RVE_SaveList
83 : CSR_XLEN_V_Interrupt_SaveList;
84 }
85 if (Subtarget.hasStdExtD())
86 return Subtarget.hasStdExtE() ? CSR_XLEN_F64_Interrupt_RVE_SaveList
87 : CSR_XLEN_F64_Interrupt_SaveList;
88 if (Subtarget.hasStdExtF())
89 return Subtarget.hasStdExtE() ? CSR_XLEN_F32_Interrupt_RVE_SaveList
90 : CSR_XLEN_F32_Interrupt_SaveList;
91 return Subtarget.hasStdExtE() ? CSR_Interrupt_RVE_SaveList
92 : CSR_Interrupt_SaveList;
93 }
94
95 bool HasVectorCSR =
96 MF->getFunction().getCallingConv() == CallingConv::RISCV_VectorCall &&
97 Subtarget.hasVInstructions();
98
99 switch (Subtarget.getTargetABI()) {
100 default:
101 llvm_unreachable("Unrecognized ABI");
102 case RISCVABI::ABI_ILP32E:
103 case RISCVABI::ABI_LP64E:
104 return CSR_ILP32E_LP64E_SaveList;
105 case RISCVABI::ABI_ILP32:
106 case RISCVABI::ABI_LP64:
107 if (HasVectorCSR)
108 return CSR_ILP32_LP64_V_SaveList;
109 return CSR_ILP32_LP64_SaveList;
110 case RISCVABI::ABI_ILP32F:
111 case RISCVABI::ABI_LP64F:
112 if (HasVectorCSR)
113 return CSR_ILP32F_LP64F_V_SaveList;
114 return CSR_ILP32F_LP64F_SaveList;
115 case RISCVABI::ABI_ILP32D:
116 case RISCVABI::ABI_LP64D:
117 if (HasVectorCSR)
118 return CSR_ILP32D_LP64D_V_SaveList;
119 return CSR_ILP32D_LP64D_SaveList;
120 }
121}
122
123const TargetRegisterClass *RISCVRegisterInfo::getConstrainedRegClassForReg(
124 Register Reg, const MachineRegisterInfo &MRI) const {
125 const RISCVSubtarget &STI = MRI.getMF().getSubtarget<RISCVSubtarget>();
126
127 const RegClassOrRegBank &RCOrRB = MRI.getRegClassOrRegBank(Reg);
128 if (const RegisterBank *RB = dyn_cast<const RegisterBank *>(Val: RCOrRB))
129 return getRegClassForTypeOnBank(Ty: MRI.getType(Reg), RB: *RB, Is64Bit: STI.is64Bit());
130
131 if (const auto *RC = dyn_cast<const TargetRegisterClass *>(Val: RCOrRB)) {
132 return getAllocatableClass(RC);
133 }
134
135 return nullptr;
136}
137
138const TargetRegisterClass *
139RISCVRegisterInfo::getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB,
140 bool Is64Bit) const {
141 if (RB.getID() == RISCV::GPRBRegBankID) {
142 if (Ty.getSizeInBits() <= 32 || (Is64Bit && Ty.getSizeInBits() == 64))
143 return &RISCV::GPRRegClass;
144 }
145
146 if (RB.getID() == RISCV::FPRBRegBankID) {
147 if (Ty.getSizeInBits() == 16)
148 return &RISCV::FPR16RegClass;
149 if (Ty.getSizeInBits() == 32)
150 return &RISCV::FPR32RegClass;
151 if (Ty.getSizeInBits() == 64)
152 return &RISCV::FPR64RegClass;
153 }
154
155 if (RB.getID() == RISCV::VRBRegBankID) {
156 if (Ty.getSizeInBits().getKnownMinValue() <= 64)
157 return &RISCV::VRRegClass;
158
159 if (Ty.getSizeInBits().getKnownMinValue() == 128)
160 return &RISCV::VRM2RegClass;
161
162 if (Ty.getSizeInBits().getKnownMinValue() == 256)
163 return &RISCV::VRM4RegClass;
164
165 if (Ty.getSizeInBits().getKnownMinValue() == 512)
166 return &RISCV::VRM8RegClass;
167 }
168
169 return nullptr;
170}
171
172BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
173 const RISCVFrameLowering *TFI = getFrameLowering(MF);
174 BitVector Reserved(getNumRegs());
175 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
176
177 for (size_t Reg = 0; Reg < getNumRegs(); Reg++) {
178 // Mark any GPRs requested to be reserved as such
179 if (Subtarget.isRegisterReservedByUser(i: Reg)) {
180 for (MCPhysReg Sub : subregs_inclusive(Reg))
181 markSuperRegs(RegisterSet&: Reserved, Reg: Sub);
182 }
183
184 // Mark all the registers defined as constant in TableGen as reserved.
185 if (isConstantPhysReg(PhysReg: Reg)) {
186 for (MCPhysReg Sub : subregs_inclusive(Reg))
187 markSuperRegs(RegisterSet&: Reserved, Reg: Sub);
188 }
189 }
190
191 // Use markSuperRegs to ensure any register aliases are also reserved
192 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::X2_H); // sp
193 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::X3_H); // gp
194 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::X4_H); // tp
195 if (TFI->hasFP(MF))
196 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::X8_H); // fp
197 // Reserve the base register if we need to realign the stack and allocate
198 // variable-sized objects at runtime.
199 if (TFI->hasBP(MF))
200 markSuperRegs(RegisterSet&: Reserved, Reg: RISCVABI::getBPReg()); // bp
201
202 // Additionally reserve dummy register used to form the register pair
203 // beginning with 'x0' for instructions that take register pairs.
204 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::DUMMY_REG_PAIR_WITH_X0);
205
206 // There are only 16 GPRs for RVE.
207 if (Subtarget.hasStdExtE())
208 for (MCPhysReg Reg = RISCV::X16_H; Reg <= RISCV::X31_H; Reg++)
209 markSuperRegs(RegisterSet&: Reserved, Reg);
210
211 // V registers for code generation. We handle them manually.
212 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::VL);
213 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::VTYPE);
214 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::VXSAT);
215 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::VXRM);
216
217 // Floating point environment registers.
218 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::FRM);
219 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::FFLAGS);
220
221 // SiFive VCIX state registers.
222 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::SF_VCIX_STATE);
223
224 if (MF.getFunction().getCallingConv() == CallingConv::GRAAL) {
225 if (Subtarget.hasStdExtE())
226 reportFatalUsageError(reason: "Graal reserved registers do not exist in RVE");
227 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::X23_H);
228 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::X27_H);
229 }
230
231 // Shadow stack pointer.
232 markSuperRegs(RegisterSet&: Reserved, Reg: RISCV::SSP);
233
234 // XSfmmbase
235 for (MCPhysReg Reg = RISCV::T0; Reg <= RISCV::T15; Reg++)
236 markSuperRegs(RegisterSet&: Reserved, Reg);
237
238 assert(checkAllSuperRegsMarked(Reserved));
239 return Reserved;
240}
241
242bool RISCVRegisterInfo::isAsmClobberable(const MachineFunction &MF,
243 MCRegister PhysReg) const {
244 return !MF.getSubtarget().isRegisterReservedByUser(R: PhysReg);
245}
246
247const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const {
248 return CSR_NoRegs_RegMask;
249}
250
251void RISCVRegisterInfo::adjustReg(MachineBasicBlock &MBB,
252 MachineBasicBlock::iterator II,
253 const DebugLoc &DL, Register DestReg,
254 Register SrcReg, StackOffset Offset,
255 MachineInstr::MIFlag Flag,
256 MaybeAlign RequiredAlign) const {
257
258 if (DestReg == SrcReg && !Offset.getFixed() && !Offset.getScalable())
259 return;
260
261 MachineFunction &MF = *MBB.getParent();
262 MachineRegisterInfo &MRI = MF.getRegInfo();
263 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
264 const RISCVInstrInfo *TII = ST.getInstrInfo();
265
266 // Optimize compile time offset case
267 if (Offset.getScalable()) {
268 if (auto VLEN = ST.getRealVLen()) {
269 // 1. Multiply the number of v-slots by the (constant) length of register
270 const int64_t VLENB = *VLEN / 8;
271 assert(Offset.getScalable() % RISCV::RVVBytesPerBlock == 0 &&
272 "Reserve the stack by the multiple of one vector size.");
273 const int64_t NumOfVReg = Offset.getScalable() / 8;
274 const int64_t FixedOffset = NumOfVReg * VLENB;
275 if (!isInt<32>(x: FixedOffset)) {
276 // This check might also need to be updated to 64bit.
277 // However mulImm() still assumes 32bit. For now only support fixed
278 // 64bit frame offsets, since scalable offsets would require the number
279 // of spilled registers to exceed 2^31, which is unlikely.
280 reportFatalUsageError(reason: "Scalable frame size outside of the signed "
281 "32-bit range not supported");
282 }
283 Offset = StackOffset::getFixed(Fixed: FixedOffset + Offset.getFixed());
284 }
285 }
286
287 bool KillSrcReg = false;
288
289 if (Offset.getScalable()) {
290 unsigned ScalableAdjOpc = RISCV::ADD;
291 int64_t ScalableValue = Offset.getScalable();
292 if (ScalableValue < 0) {
293 ScalableValue = -ScalableValue;
294 ScalableAdjOpc = RISCV::SUB;
295 }
296 // Get vlenb and multiply vlen with the number of vector registers.
297 Register ScratchReg = DestReg;
298 if (DestReg == SrcReg)
299 ScratchReg = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
300
301 assert(ScalableValue > 0 && "There is no need to get VLEN scaled value.");
302 assert(ScalableValue % RISCV::RVVBytesPerBlock == 0 &&
303 "Reserve the stack by the multiple of one vector size.");
304 assert(isInt<32>(ScalableValue / RISCV::RVVBytesPerBlock) &&
305 "Expect the number of vector registers within 32-bits.");
306 uint32_t NumOfVReg = ScalableValue / RISCV::RVVBytesPerBlock;
307 // Only use vsetvli rather than vlenb if adjusting in the prologue or
308 // epilogue, otherwise it may disturb the VTYPE and VL status.
309 bool IsPrologueOrEpilogue =
310 Flag == MachineInstr::FrameSetup || Flag == MachineInstr::FrameDestroy;
311 bool UseVsetvliRatherThanVlenb =
312 IsPrologueOrEpilogue && ST.preferVsetvliOverReadVLENB();
313 if (UseVsetvliRatherThanVlenb && (NumOfVReg == 1 || NumOfVReg == 2 ||
314 NumOfVReg == 4 || NumOfVReg == 8)) {
315 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::PseudoReadVLENBViaVSETVLIX0),
316 DestReg: ScratchReg)
317 .addImm(Val: NumOfVReg)
318 .setMIFlag(Flag);
319 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: ScalableAdjOpc), DestReg)
320 .addReg(RegNo: SrcReg)
321 .addReg(RegNo: ScratchReg, Flags: RegState::Kill)
322 .setMIFlag(Flag);
323 } else {
324 if (UseVsetvliRatherThanVlenb)
325 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::PseudoReadVLENBViaVSETVLIX0),
326 DestReg: ScratchReg)
327 .addImm(Val: 1)
328 .setMIFlag(Flag);
329 else
330 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::PseudoReadVLENB), DestReg: ScratchReg)
331 .setMIFlag(Flag);
332
333 if (ScalableAdjOpc == RISCV::ADD && ST.hasStdExtZba() &&
334 (NumOfVReg == 2 || NumOfVReg == 4 || NumOfVReg == 8)) {
335 unsigned Opc = NumOfVReg == 2
336 ? RISCV::SH1ADD
337 : (NumOfVReg == 4 ? RISCV::SH2ADD : RISCV::SH3ADD);
338 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: Opc), DestReg)
339 .addReg(RegNo: ScratchReg, Flags: RegState::Kill)
340 .addReg(RegNo: SrcReg)
341 .setMIFlag(Flag);
342 } else {
343 TII->mulImm(MF, MBB, II, DL, DestReg: ScratchReg, Amt: NumOfVReg, Flag);
344 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: ScalableAdjOpc), DestReg)
345 .addReg(RegNo: SrcReg)
346 .addReg(RegNo: ScratchReg, Flags: RegState::Kill)
347 .setMIFlag(Flag);
348 }
349 }
350 SrcReg = DestReg;
351 KillSrcReg = true;
352 }
353
354 int64_t Val = Offset.getFixed();
355 if (DestReg == SrcReg && Val == 0)
356 return;
357
358 const uint64_t Align = RequiredAlign.valueOrOne().value();
359
360 if (isInt<12>(x: Val)) {
361 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::ADDI), DestReg)
362 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrcReg))
363 .addImm(Val)
364 .setMIFlag(Flag);
365 return;
366 }
367
368 // Use the QC_E_ADDI instruction from the Xqcilia extension that can take a
369 // signed 26-bit immediate.
370 if (ST.hasVendorXqcilia() && isInt<26>(x: Val)) {
371 // The one case where using this instruction is sub-optimal is if Val can be
372 // materialized with a single compressible LUI and following add/sub is also
373 // compressible. Avoid doing this if that is the case.
374 int Hi20 = (Val & 0xFFFFF000) >> 12;
375 bool IsCompressLUI =
376 ((Val & 0xFFF) == 0) && (Hi20 != 0) &&
377 (isUInt<5>(x: Hi20) || (Hi20 >= 0xfffe0 && Hi20 <= 0xfffff));
378 bool IsCompressAddSub =
379 (SrcReg == DestReg) &&
380 ((Val > 0 && RISCV::GPRNoX0RegClass.contains(Reg: SrcReg)) ||
381 (Val < 0 && RISCV::GPRCRegClass.contains(Reg: SrcReg)));
382
383 if (!(IsCompressLUI && IsCompressAddSub)) {
384 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::QC_E_ADDI), DestReg)
385 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrcReg))
386 .addImm(Val)
387 .setMIFlag(Flag);
388 return;
389 }
390 }
391
392 // Try to split the offset across two ADDIs. We need to keep the intermediate
393 // result aligned after each ADDI. We need to determine the maximum value we
394 // can put in each ADDI. In the negative direction, we can use -2048 which is
395 // always sufficiently aligned. In the positive direction, we need to find the
396 // largest 12-bit immediate that is aligned. Exclude -4096 since it can be
397 // created with LUI.
398 assert(Align < 2048 && "Required alignment too large");
399 int64_t MaxPosAdjStep = 2048 - Align;
400 if (Val > -4096 && Val <= (2 * MaxPosAdjStep)) {
401 int64_t FirstAdj = Val < 0 ? -2048 : MaxPosAdjStep;
402 Val -= FirstAdj;
403 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::ADDI), DestReg)
404 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrcReg))
405 .addImm(Val: FirstAdj)
406 .setMIFlag(Flag);
407 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::ADDI), DestReg)
408 .addReg(RegNo: DestReg, Flags: RegState::Kill)
409 .addImm(Val)
410 .setMIFlag(Flag);
411 return;
412 }
413
414 // Use shNadd if doing so lets us materialize a 12 bit immediate with a single
415 // instruction. This saves 1 instruction over the full lui/addi+add fallback
416 // path. We avoid anything which can be done with a single lui as it might
417 // be compressible. Note that the sh1add case is fully covered by the 2x addi
418 // case just above and is thus omitted.
419 if (ST.hasStdExtZba() && (Val & 0xFFF) != 0) {
420 unsigned Opc = 0;
421 if (isShiftedInt<12, 3>(x: Val)) {
422 Opc = RISCV::SH3ADD;
423 Val = Val >> 3;
424 } else if (isShiftedInt<12, 2>(x: Val)) {
425 Opc = RISCV::SH2ADD;
426 Val = Val >> 2;
427 }
428 if (Opc) {
429 Register ScratchReg = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
430 TII->movImm(MBB, MBBI: II, DL, DstReg: ScratchReg, Val, Flag);
431 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: Opc), DestReg)
432 .addReg(RegNo: ScratchReg, Flags: RegState::Kill)
433 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrcReg))
434 .setMIFlag(Flag);
435 return;
436 }
437 }
438
439 // Emit a PseudoAddUpperImm instead of LUI+ADD when the offset is a multiple
440 // of 4096 and the source is the frame register. The frame register is
441 // invariant after PEI, so MachineLateInstrsCleanup can CSE identical pseudos.
442 // The pseudo is later expanded back to LUI+ADD.
443 if (Flag == MachineInstr::NoFlags && !KillSrcReg && DestReg != SrcReg &&
444 SrcReg == getFrameRegister(MF) && isShiftedInt<20, 12>(x: Val)) {
445 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::PseudoAddUpperImm), DestReg)
446 .addReg(RegNo: SrcReg)
447 .addImm(Val: static_cast<uint32_t>(Val) >> 12);
448 return;
449 }
450
451 unsigned Opc = RISCV::ADD;
452 if (Val < 0) {
453 Val = -Val;
454 Opc = RISCV::SUB;
455 }
456
457 Register ScratchReg = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
458 TII->movImm(MBB, MBBI: II, DL, DstReg: ScratchReg, Val, Flag);
459 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: Opc), DestReg)
460 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrcReg))
461 .addReg(RegNo: ScratchReg, Flags: RegState::Kill)
462 .setMIFlag(Flag);
463}
464
465static std::tuple<RISCVVType::VLMUL, const TargetRegisterClass &, unsigned>
466getSpillReloadInfo(unsigned NumRemaining, uint16_t RegEncoding, bool IsSpill) {
467 if (NumRemaining >= 8 && RegEncoding % 8 == 0)
468 return {RISCVVType::LMUL_8, RISCV::VRM8RegClass,
469 IsSpill ? RISCV::VS8R_V : RISCV::VL8RE8_V};
470 if (NumRemaining >= 4 && RegEncoding % 4 == 0)
471 return {RISCVVType::LMUL_4, RISCV::VRM4RegClass,
472 IsSpill ? RISCV::VS4R_V : RISCV::VL4RE8_V};
473 if (NumRemaining >= 2 && RegEncoding % 2 == 0)
474 return {RISCVVType::LMUL_2, RISCV::VRM2RegClass,
475 IsSpill ? RISCV::VS2R_V : RISCV::VL2RE8_V};
476 return {RISCVVType::LMUL_1, RISCV::VRRegClass,
477 IsSpill ? RISCV::VS1R_V : RISCV::VL1RE8_V};
478}
479
480// Split a VSPILLx_Mx/VSPILLx_Mx pseudo into multiple whole register stores
481// separated by LMUL*VLENB bytes.
482void RISCVRegisterInfo::lowerSegmentSpillReload(MachineBasicBlock::iterator II,
483 bool IsSpill) const {
484 DebugLoc DL = II->getDebugLoc();
485 MachineBasicBlock &MBB = *II->getParent();
486 MachineFunction &MF = *MBB.getParent();
487 MachineRegisterInfo &MRI = MF.getRegInfo();
488 const RISCVSubtarget &STI = MF.getSubtarget<RISCVSubtarget>();
489 const TargetInstrInfo *TII = STI.getInstrInfo();
490 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
491
492 auto ZvlssegInfo = RISCV::isRVVSpillForZvlsseg(Opcode: II->getOpcode());
493 unsigned NF = ZvlssegInfo->first;
494 unsigned LMUL = ZvlssegInfo->second;
495 unsigned NumRegs = NF * LMUL;
496 assert(NumRegs <= 8 && "Invalid NF/LMUL combinations.");
497
498 Register Reg = II->getOperand(i: 0).getReg();
499 uint16_t RegEncoding = TRI->getEncodingValue(Reg);
500 Register Base = II->getOperand(i: 1).getReg();
501 bool IsBaseKill = II->getOperand(i: 1).isKill();
502 Register NewBase = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
503
504 auto *OldMMO = *(II->memoperands_begin());
505 LocationSize OldLoc = OldMMO->getSize();
506 assert(OldLoc.isPrecise() && OldLoc.getValue().isKnownMultipleOf(NF));
507 TypeSize VRegSize = OldLoc.getValue().divideCoefficientBy(RHS: NumRegs);
508
509 Register VLENB = 0;
510 unsigned VLENBShift = 0;
511 unsigned PrevHandledNum = 0;
512 unsigned I = 0;
513 while (I != NumRegs) {
514 auto [LMulHandled, RegClass, Opcode] =
515 getSpillReloadInfo(NumRemaining: NumRegs - I, RegEncoding, IsSpill);
516 auto [RegNumHandled, _] = RISCVVType::decodeVLMUL(VLMul: LMulHandled);
517 bool IsLast = I + RegNumHandled == NumRegs;
518 if (PrevHandledNum) {
519 Register Step;
520 // Optimize for constant VLEN.
521 if (auto VLEN = STI.getRealVLen()) {
522 int64_t Offset = *VLEN / 8 * PrevHandledNum;
523 Step = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
524 STI.getInstrInfo()->movImm(MBB, MBBI: II, DL, DstReg: Step, Val: Offset);
525 } else {
526 if (!VLENB) {
527 VLENB = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
528 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::PseudoReadVLENB), DestReg: VLENB);
529 }
530 uint32_t ShiftAmount = Log2_32(Value: PrevHandledNum);
531 // To avoid using an extra register, we shift the VLENB register and
532 // remember how much it has been shifted. We can then use relative
533 // shifts to adjust to the desired shift amount.
534 if (VLENBShift > ShiftAmount) {
535 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::SRLI), DestReg: VLENB)
536 .addReg(RegNo: VLENB, Flags: RegState::Kill)
537 .addImm(Val: VLENBShift - ShiftAmount);
538 } else if (VLENBShift < ShiftAmount) {
539 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::SLLI), DestReg: VLENB)
540 .addReg(RegNo: VLENB, Flags: RegState::Kill)
541 .addImm(Val: ShiftAmount - VLENBShift);
542 }
543 VLENBShift = ShiftAmount;
544 Step = VLENB;
545 }
546
547 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode: RISCV::ADD), DestReg: NewBase)
548 .addReg(RegNo: Base, Flags: getKillRegState(B: I != 0 || IsBaseKill))
549 .addReg(RegNo: Step, Flags: getKillRegState(B: Step != VLENB || IsLast));
550 Base = NewBase;
551 }
552
553 MCRegister ActualReg = findVRegWithEncoding(RegClass, Encoding: RegEncoding);
554 MachineInstrBuilder MIB =
555 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII->get(Opcode))
556 .addReg(RegNo: ActualReg, Flags: getDefRegState(B: !IsSpill))
557 .addReg(RegNo: Base, Flags: getKillRegState(B: IsLast))
558 .addMemOperand(MMO: MF.getMachineMemOperand(MMO: OldMMO, Offset: OldMMO->getOffset(),
559 Size: VRegSize * RegNumHandled));
560
561 // Adding implicit-use of super register to describe we are using part of
562 // super register, that prevents machine verifier complaining when part of
563 // subreg is undef, see comment in MachineVerifier::checkLiveness for more
564 // detail.
565 if (IsSpill)
566 MIB.addReg(RegNo: Reg, Flags: RegState::Implicit);
567
568 PrevHandledNum = RegNumHandled;
569 RegEncoding += RegNumHandled;
570 I += RegNumHandled;
571 }
572 II->eraseFromParent();
573}
574
575static unsigned getXqciloWideOpcode(unsigned Opc) {
576 switch (Opc) {
577 case RISCV::LW:
578 return RISCV::QC_E_LW;
579 case RISCV::SW:
580 return RISCV::QC_E_SW;
581 case RISCV::LB:
582 return RISCV::QC_E_LB;
583 case RISCV::LBU:
584 return RISCV::QC_E_LBU;
585 case RISCV::LH:
586 return RISCV::QC_E_LH;
587 case RISCV::LHU:
588 return RISCV::QC_E_LHU;
589 case RISCV::SB:
590 return RISCV::QC_E_SB;
591 case RISCV::SH:
592 return RISCV::QC_E_SH;
593 default:
594 return 0;
595 }
596}
597
598bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
599 int SPAdj, unsigned FIOperandNum,
600 RegScavenger *RS) const {
601 assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
602
603 MachineInstr &MI = *II;
604 MachineFunction &MF = *MI.getParent()->getParent();
605 MachineRegisterInfo &MRI = MF.getRegInfo();
606 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
607 const RISCVInstrInfo *TII = ST.getInstrInfo();
608 bool Is64Bit = ST.is64Bit();
609 DebugLoc DL = MI.getDebugLoc();
610
611 int FrameIndex = MI.getOperand(i: FIOperandNum).getIndex();
612 Register FrameReg;
613 StackOffset Offset =
614 getFrameLowering(MF)->getFrameIndexReference(MF, FI: FrameIndex, FrameReg);
615 bool IsRVVSpill = RISCV::isRVVSpill(MI);
616 if (!IsRVVSpill)
617 Offset += StackOffset::getFixed(Fixed: MI.getOperand(i: FIOperandNum + 1).getImm());
618
619 if (!Is64Bit && !isInt<32>(x: Offset.getFixed())) {
620 reportFatalUsageError(reason: "Frame offsets outside of the signed 32-bit range "
621 "not supported on RV32");
622 }
623
624 if (!IsRVVSpill) {
625 int64_t Val = Offset.getFixed();
626 int64_t Lo12 = SignExtend64<12>(x: Val);
627 int64_t Lo26 = SignExtend64<26>(x: Val);
628 unsigned Opc = MI.getOpcode();
629
630 if (Opc == RISCV::ADDI && !isInt<12>(x: Val)) {
631 // We chose to emit the canonical immediate sequence rather than folding
632 // the offset into the using add under the theory that doing so doesn't
633 // save dynamic instruction count and some target may fuse the canonical
634 // 32 bit immediate sequence. We still need to clear the portion of the
635 // offset encoded in the immediate.
636 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: 0);
637 } else if ((Opc == RISCV::PREFETCH_I || Opc == RISCV::PREFETCH_R ||
638 Opc == RISCV::PREFETCH_W) &&
639 (Lo12 & 0b11111) != 0) {
640 // Prefetch instructions require the offset to be 32 byte aligned.
641 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: 0);
642 } else if (Opc == RISCV::MIPS_PREF && !isUInt<9>(x: Val)) {
643 // MIPS Prefetch instructions require the offset to be 9 bits encoded.
644 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: 0);
645 } else if ((Opc == RISCV::PseudoRV32ZdinxLD ||
646 Opc == RISCV::PseudoRV32ZdinxSD ||
647 Opc == RISCV::PseudoLD_RV32_OPT ||
648 Opc == RISCV::PseudoSD_RV32_OPT) &&
649 Lo12 >= 2044) {
650 // This instruction will/might be split into 2 instructions. The second
651 // instruction will add 4 to the immediate. If that would overflow 12
652 // bits, we can't fold the offset.
653 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: 0);
654 } else if (unsigned WideOpc = getXqciloWideOpcode(Opc);
655 !isInt<12>(x: Val) && ST.hasVendorXqcilo() && WideOpc) {
656 // The resolved frame offset exceeds simm12 but the instruction is a
657 // standard load/store (LW/SW/etc). Promote to the wide Xqcilo equivalent
658 // so the full 26-bit offset folds directly, avoiding a separate
659 // base-adjust instruction. This runs post-RA and does not affect
660 // register allocation decisions.
661 MI.setDesc(TII->get(Opcode: WideOpc));
662 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: Lo26);
663 Offset = StackOffset::get(Fixed: (uint64_t)Val - (uint64_t)Lo26,
664 Scalable: Offset.getScalable());
665 } else if (Opc == RISCV::QC_E_ADDI || RISCVInstrInfo::isBaseQCLoad(MI) ||
666 RISCVInstrInfo::isBaseQCStore(MI)) {
667 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: Lo26);
668 Offset = StackOffset::get(Fixed: (uint64_t)Val - (uint64_t)Lo26,
669 Scalable: Offset.getScalable());
670 } else {
671 // We can encode an add with 12 bit signed immediate in the immediate
672 // operand of our user instruction. As a result, the remaining
673 // offset can by construction, at worst, a LUI and a ADD.
674 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: Lo12);
675 Offset = StackOffset::get(Fixed: (uint64_t)Val - (uint64_t)Lo12,
676 Scalable: Offset.getScalable());
677 }
678 }
679
680 if (Offset.getScalable() || Offset.getFixed()) {
681 Register DestReg;
682 if (MI.getOpcode() == RISCV::ADDI)
683 DestReg = MI.getOperand(i: 0).getReg();
684 else
685 DestReg = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
686 adjustReg(MBB&: *II->getParent(), II, DL, DestReg, SrcReg: FrameReg, Offset,
687 Flag: MachineInstr::NoFlags, RequiredAlign: std::nullopt);
688 MI.getOperand(i: FIOperandNum).ChangeToRegister(Reg: DestReg, /*IsDef*/isDef: false,
689 /*IsImp*/isImp: false,
690 /*IsKill*/isKill: true);
691 } else {
692 MI.getOperand(i: FIOperandNum).ChangeToRegister(Reg: FrameReg, /*IsDef*/isDef: false,
693 /*IsImp*/isImp: false,
694 /*IsKill*/isKill: false);
695 }
696
697 // If after materializing the adjustment, we have a pointless ADDI, remove it
698 if (MI.getOpcode() == RISCV::ADDI &&
699 MI.getOperand(i: 0).getReg() == MI.getOperand(i: 1).getReg() &&
700 MI.getOperand(i: 2).getImm() == 0) {
701 MI.eraseFromParent();
702 return true;
703 }
704
705 // Handle spill/fill of synthetic register classes for segment operations to
706 // ensure correctness in the edge case one gets spilled.
707 switch (MI.getOpcode()) {
708 case RISCV::PseudoVSPILL2_M1:
709 case RISCV::PseudoVSPILL2_M2:
710 case RISCV::PseudoVSPILL2_M4:
711 case RISCV::PseudoVSPILL3_M1:
712 case RISCV::PseudoVSPILL3_M2:
713 case RISCV::PseudoVSPILL4_M1:
714 case RISCV::PseudoVSPILL4_M2:
715 case RISCV::PseudoVSPILL5_M1:
716 case RISCV::PseudoVSPILL6_M1:
717 case RISCV::PseudoVSPILL7_M1:
718 case RISCV::PseudoVSPILL8_M1:
719 lowerSegmentSpillReload(II, /*IsSpill=*/true);
720 return true;
721 case RISCV::PseudoVRELOAD2_M1:
722 case RISCV::PseudoVRELOAD2_M2:
723 case RISCV::PseudoVRELOAD2_M4:
724 case RISCV::PseudoVRELOAD3_M1:
725 case RISCV::PseudoVRELOAD3_M2:
726 case RISCV::PseudoVRELOAD4_M1:
727 case RISCV::PseudoVRELOAD4_M2:
728 case RISCV::PseudoVRELOAD5_M1:
729 case RISCV::PseudoVRELOAD6_M1:
730 case RISCV::PseudoVRELOAD7_M1:
731 case RISCV::PseudoVRELOAD8_M1:
732 lowerSegmentSpillReload(II, /*IsSpill=*/false);
733 return true;
734 }
735
736 return false;
737}
738
739bool RISCVRegisterInfo::requiresVirtualBaseRegisters(
740 const MachineFunction &MF) const {
741 return true;
742}
743
744// Returns true if the instruction's frame index reference would be better
745// served by a base register other than FP or SP.
746// Used by LocalStackSlotAllocation pass to determine which frame index
747// references it should create new base registers for.
748bool RISCVRegisterInfo::needsFrameBaseReg(MachineInstr *MI,
749 int64_t Offset) const {
750 unsigned FIOperandNum = 0;
751 for (; !MI->getOperand(i: FIOperandNum).isFI(); FIOperandNum++)
752 assert(FIOperandNum < MI->getNumOperands() &&
753 "Instr doesn't have FrameIndex operand");
754
755 // For RISC-V, The machine instructions that include a FrameIndex operand
756 // are load/store, ADDI instructions.
757 unsigned MIFrm = RISCVII::getFormat(TSFlags: MI->getDesc().TSFlags);
758 if (MIFrm != RISCVII::InstFormatI && MIFrm != RISCVII::InstFormatS)
759 return false;
760 // We only generate virtual base registers for loads and stores, so
761 // return false for everything else.
762 if (!MI->mayLoad() && !MI->mayStore())
763 return false;
764
765 const MachineFunction &MF = *MI->getMF();
766 const MachineFrameInfo &MFI = MF.getFrameInfo();
767 const RISCVFrameLowering *TFI = getFrameLowering(MF);
768 const MachineRegisterInfo &MRI = MF.getRegInfo();
769
770 if (TFI->hasFP(MF) && !shouldRealignStack(MF)) {
771 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
772 // Estimate the stack size used to store callee saved registers(
773 // excludes reserved registers).
774 unsigned CalleeSavedSize = 0;
775 for (const MCPhysReg *R = MRI.getCalleeSavedRegs(); MCPhysReg Reg = *R;
776 ++R) {
777 if (Subtarget.isRegisterReservedByUser(i: Reg))
778 continue;
779
780 if (RISCV::GPRRegClass.contains(Reg))
781 CalleeSavedSize += getSpillSize(RC: RISCV::GPRRegClass);
782 else if (RISCV::FPR64RegClass.contains(Reg))
783 CalleeSavedSize += getSpillSize(RC: RISCV::FPR64RegClass);
784 else if (RISCV::FPR32RegClass.contains(Reg))
785 CalleeSavedSize += getSpillSize(RC: RISCV::FPR32RegClass);
786 // Ignore vector registers.
787 }
788
789 int64_t MaxFPOffset = Offset - CalleeSavedSize;
790 if (isFrameOffsetLegal(MI, BaseReg: RISCV::X8, Offset: MaxFPOffset))
791 return false;
792
793 // If the FP-relative offset doesn't fit, fall through to check the
794 // SP-relative offset. getFrameIndexReference may select SP over FP when
795 // the SP offset fits in the compressed instruction immediate range, so a
796 // base register might not be needed.
797 }
798
799 // Assume 128 bytes spill slots size to estimate the maximum possible
800 // offset relative to the stack pointer.
801 // FIXME: The 128 is copied from ARM. We should run some statistics and pick a
802 // real one for RISC-V.
803 int64_t MaxSPOffset = Offset + 128;
804 MaxSPOffset += MFI.getLocalFrameSize();
805 return !isFrameOffsetLegal(MI, BaseReg: RISCV::X2, Offset: MaxSPOffset);
806}
807
808// Determine whether a given base register plus offset immediate is
809// encodable to resolve a frame index.
810bool RISCVRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
811 Register BaseReg,
812 int64_t Offset) const {
813 unsigned FIOperandNum = 0;
814 while (!MI->getOperand(i: FIOperandNum).isFI()) {
815 FIOperandNum++;
816 assert(FIOperandNum < MI->getNumOperands() &&
817 "Instr does not have a FrameIndex operand!");
818 }
819
820 Offset += getFrameIndexInstrOffset(MI, Idx: FIOperandNum);
821 return isInt<12>(x: Offset);
822}
823
824// Insert defining instruction(s) for a pointer to FrameIdx before
825// insertion point I.
826// Return materialized frame pointer.
827Register RISCVRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
828 int FrameIdx,
829 int64_t Offset) const {
830 MachineBasicBlock::iterator MBBI = MBB->begin();
831 DebugLoc DL;
832 if (MBBI != MBB->end())
833 DL = MBBI->getDebugLoc();
834 MachineFunction *MF = MBB->getParent();
835 MachineRegisterInfo &MFI = MF->getRegInfo();
836 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
837
838 Register BaseReg = MFI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
839 BuildMI(BB&: *MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: RISCV::ADDI), DestReg: BaseReg)
840 .addFrameIndex(Idx: FrameIdx)
841 .addImm(Val: Offset);
842 return BaseReg;
843}
844
845// Resolve a frame index operand of an instruction to reference the
846// indicated base register plus offset instead.
847void RISCVRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg,
848 int64_t Offset) const {
849 unsigned FIOperandNum = 0;
850 while (!MI.getOperand(i: FIOperandNum).isFI()) {
851 FIOperandNum++;
852 assert(FIOperandNum < MI.getNumOperands() &&
853 "Instr does not have a FrameIndex operand!");
854 }
855
856 Offset += getFrameIndexInstrOffset(MI: &MI, Idx: FIOperandNum);
857 // FrameIndex Operands are always represented as a
858 // register followed by an immediate.
859 MI.getOperand(i: FIOperandNum).ChangeToRegister(Reg: BaseReg, isDef: false);
860 MI.getOperand(i: FIOperandNum + 1).ChangeToImmediate(ImmVal: Offset);
861}
862
863// Get the offset from the referenced frame index in the instruction,
864// if there is one.
865int64_t RISCVRegisterInfo::getFrameIndexInstrOffset(const MachineInstr *MI,
866 int Idx) const {
867 assert((RISCVII::getFormat(MI->getDesc().TSFlags) == RISCVII::InstFormatI ||
868 RISCVII::getFormat(MI->getDesc().TSFlags) == RISCVII::InstFormatS) &&
869 "The MI must be I or S format.");
870 assert(MI->getOperand(Idx).isFI() && "The Idx'th operand of MI is not a "
871 "FrameIndex operand");
872 return MI->getOperand(i: Idx + 1).getImm();
873}
874
875Register RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
876 const TargetFrameLowering *TFI = getFrameLowering(MF);
877 return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
878}
879
880bool RISCVRegisterInfo::isArgumentRegister(const MachineFunction &MF,
881 MCRegister Reg) const {
882 auto const &STI = MF.getSubtarget<RISCVSubtarget>();
883 const RISCVRegisterInfo *TRI = STI.getRegisterInfo();
884
885 if (TRI->isGeneralPurposeRegister(MF, PhysReg: Reg))
886 return llvm::is_contained(Range: RISCV::getArgGPRs(STI), Element: Reg);
887
888 if (TRI->isFPRegister(Reg))
889 return llvm::is_contained(Range: RISCV::getArgFPRs(STI), Element: Reg);
890
891 if (RISCV::VRRegClass.contains(Reg))
892 return llvm::is_contained(Range: RISCV::getArgVRs(STI), Element: Reg);
893
894 return false;
895}
896
897StringRef RISCVRegisterInfo::getRegAsmName(MCRegister Reg) const {
898 if (Reg == RISCV::SF_VCIX_STATE)
899 return "sf.vcix_state";
900 return TargetRegisterInfo::getRegAsmName(Reg);
901}
902
903const uint32_t *
904RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF,
905 CallingConv::ID CC) const {
906 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
907
908 if (CC == CallingConv::GHC)
909 return CSR_NoRegs_RegMask;
910 RISCVABI::ABI ABI = Subtarget.getTargetABI();
911 if (CC == CallingConv::PreserveMost) {
912 if (ABI == RISCVABI::ABI_ILP32E || ABI == RISCVABI::ABI_LP64E)
913 return CSR_RT_MostRegs_RVE_RegMask;
914 return CSR_RT_MostRegs_RegMask;
915 }
916 switch (ABI) {
917 default:
918 llvm_unreachable("Unrecognized ABI");
919 case RISCVABI::ABI_ILP32E:
920 case RISCVABI::ABI_LP64E:
921 return CSR_ILP32E_LP64E_RegMask;
922 case RISCVABI::ABI_ILP32:
923 case RISCVABI::ABI_LP64:
924 if (CC == CallingConv::RISCV_VectorCall)
925 return CSR_ILP32_LP64_V_RegMask;
926 return CSR_ILP32_LP64_RegMask;
927 case RISCVABI::ABI_ILP32F:
928 case RISCVABI::ABI_LP64F:
929 if (CC == CallingConv::RISCV_VectorCall)
930 return CSR_ILP32F_LP64F_V_RegMask;
931 return CSR_ILP32F_LP64F_RegMask;
932 case RISCVABI::ABI_ILP32D:
933 case RISCVABI::ABI_LP64D:
934 if (CC == CallingConv::RISCV_VectorCall)
935 return CSR_ILP32D_LP64D_V_RegMask;
936 return CSR_ILP32D_LP64D_RegMask;
937 }
938}
939
940const TargetRegisterClass *
941RISCVRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
942 const MachineFunction &) const {
943 if (RC == &RISCV::VMV0RegClass)
944 return &RISCV::VRRegClass;
945 if (RC == &RISCV::VRNoV0RegClass)
946 return &RISCV::VRRegClass;
947 if (RC == &RISCV::VRM2NoV0RegClass)
948 return &RISCV::VRM2RegClass;
949 if (RC == &RISCV::VRM4NoV0RegClass)
950 return &RISCV::VRM4RegClass;
951 if (RC == &RISCV::VRM8NoV0RegClass)
952 return &RISCV::VRM8RegClass;
953 return RC;
954}
955
956void RISCVRegisterInfo::getOffsetOpcodes(const StackOffset &Offset,
957 SmallVectorImpl<uint64_t> &Ops) const {
958 // VLENB is the length of a vector register in bytes. We use <vscale x 8 x i8>
959 // to represent one vector register. The dwarf offset is
960 // VLENB * scalable_offset / 8.
961 assert(Offset.getScalable() % 8 == 0 && "Invalid frame offset");
962
963 // Add fixed-sized offset using existing DIExpression interface.
964 DIExpression::appendOffset(Ops, Offset: Offset.getFixed());
965
966 unsigned VLENB = getDwarfRegNum(Reg: RISCV::VLENB, isEH: true);
967 int64_t VLENBSized = Offset.getScalable() / 8;
968 if (VLENBSized > 0) {
969 Ops.push_back(Elt: dwarf::DW_OP_constu);
970 Ops.push_back(Elt: VLENBSized);
971 Ops.append(IL: {dwarf::DW_OP_bregx, VLENB, 0ULL});
972 Ops.push_back(Elt: dwarf::DW_OP_mul);
973 Ops.push_back(Elt: dwarf::DW_OP_plus);
974 } else if (VLENBSized < 0) {
975 Ops.push_back(Elt: dwarf::DW_OP_constu);
976 Ops.push_back(Elt: -VLENBSized);
977 Ops.append(IL: {dwarf::DW_OP_bregx, VLENB, 0ULL});
978 Ops.push_back(Elt: dwarf::DW_OP_mul);
979 Ops.push_back(Elt: dwarf::DW_OP_minus);
980 }
981}
982
983unsigned
984RISCVRegisterInfo::getRegisterCostTableIndex(const MachineFunction &MF) const {
985 // Set CostPerUse to 1 only when optimizing for size and RVC exists.
986 return MF.getFunction().hasOptSize() &&
987 MF.getSubtarget<RISCVSubtarget>().hasStdExtZca() &&
988 !DisableCostPerUse
989 ? 1
990 : 0;
991}
992
993float RISCVRegisterInfo::getSpillWeightScaleFactor(
994 const TargetRegisterClass *RC) const {
995 return getRegClassWeight(RC).RegWeight;
996}
997
998// Add two address hints to improve chances of being able to use a compressed
999// instruction.
1000bool RISCVRegisterInfo::getRegAllocationHints(
1001 Register VirtReg, ArrayRef<MCPhysReg> Order,
1002 SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF,
1003 const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
1004 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1005 auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
1006
1007 // Handle RegPairEven/RegPairOdd hints for Zilsd register pairs
1008 std::pair<unsigned, Register> Hint = MRI->getRegAllocationHint(VReg: VirtReg);
1009 unsigned HintType = Hint.first;
1010 Register Partner = Hint.second;
1011
1012 MCRegister TargetReg;
1013 if (HintType == RISCVRI::RegPairEven || HintType == RISCVRI::RegPairOdd) {
1014 // Check if we want the even or odd register of a consecutive pair
1015 bool WantOdd = (HintType == RISCVRI::RegPairOdd);
1016
1017 // First priority: Check if partner is already allocated
1018 if (Partner.isVirtual() && VRM && VRM->hasPhys(virtReg: Partner)) {
1019 MCRegister PartnerPhys = VRM->getPhys(virtReg: Partner);
1020 // Calculate the exact register we need for consecutive pairing
1021 TargetReg = PartnerPhys.id() + (WantOdd ? 1 : -1);
1022
1023 // Verify it's valid and available
1024 if (RISCV::GPRRegClass.contains(Reg: TargetReg) &&
1025 is_contained(Range&: Order, Element: TargetReg))
1026 Hints.push_back(Elt: TargetReg.id());
1027 }
1028
1029 // Second priority: Try to find consecutive register pairs in the allocation
1030 // order
1031 for (MCPhysReg PhysReg : Order) {
1032 // Don't add the hint if we already added above.
1033 if (TargetReg == PhysReg)
1034 continue;
1035
1036 unsigned RegNum = getEncodingValue(Reg: PhysReg);
1037 // Check if this register matches the even/odd requirement
1038 bool IsOdd = (RegNum % 2 != 0);
1039
1040 // Don't provide hints that are paired to a reserved register.
1041 MCRegister Paired = PhysReg + (IsOdd ? -1 : 1);
1042 if (WantOdd == IsOdd && !MRI->isReserved(PhysReg: Paired))
1043 Hints.push_back(Elt: PhysReg);
1044 }
1045 }
1046
1047 bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
1048 VirtReg, Order, Hints, MF, VRM, Matrix);
1049
1050 if (!VRM || DisableRegAllocHints)
1051 return BaseImplRetVal;
1052
1053 // Add any two address hints after any copy hints.
1054 SmallSet<Register, 4> TwoAddrHints;
1055
1056 auto tryAddHint = [&](const MachineOperand &VRRegMO, const MachineOperand &MO,
1057 bool NeedGPRC) -> void {
1058 Register Reg = MO.getReg();
1059 Register PhysReg = Reg.isPhysical() ? Reg : Register(VRM->getPhys(virtReg: Reg));
1060 // TODO: Support GPRPair subregisters? Need to be careful with even/odd
1061 // registers. If the virtual register is an odd register of a pair and the
1062 // physical register is even (or vice versa), we should not add the hint.
1063 if (PhysReg && (!NeedGPRC || RISCV::GPRCRegClass.contains(Reg: PhysReg)) &&
1064 !MO.getSubReg() && !VRRegMO.getSubReg()) {
1065 if (!MRI->isReserved(PhysReg) && !is_contained(Range&: Hints, Element: PhysReg))
1066 TwoAddrHints.insert(V: PhysReg);
1067 }
1068 };
1069
1070 // This is all of the compressible binary instructions. If an instruction
1071 // needs GPRC register class operands \p NeedGPRC will be set to true.
1072 auto isCompressible = [&Subtarget](const MachineInstr &MI, bool &NeedGPRC) {
1073 NeedGPRC = false;
1074 switch (MI.getOpcode()) {
1075 default:
1076 return false;
1077 case RISCV::AND:
1078 case RISCV::OR:
1079 case RISCV::XOR:
1080 case RISCV::SUB:
1081 case RISCV::ADDW:
1082 case RISCV::SUBW:
1083 NeedGPRC = true;
1084 return true;
1085 case RISCV::ANDI: {
1086 NeedGPRC = true;
1087 if (!MI.getOperand(i: 2).isImm())
1088 return false;
1089 int64_t Imm = MI.getOperand(i: 2).getImm();
1090 if (isInt<6>(x: Imm))
1091 return true;
1092 // c.zext.b
1093 return Subtarget.hasStdExtZcb() && Imm == 255;
1094 }
1095 case RISCV::SRAI:
1096 case RISCV::SRLI:
1097 NeedGPRC = true;
1098 return true;
1099 case RISCV::ADD:
1100 case RISCV::SLLI:
1101 return true;
1102 case RISCV::ADDI:
1103 case RISCV::ADDIW:
1104 return MI.getOperand(i: 2).isImm() && isInt<6>(x: MI.getOperand(i: 2).getImm());
1105 case RISCV::MUL:
1106 // c.mul
1107 NeedGPRC = true;
1108 return Subtarget.hasStdExtZcb();
1109 case RISCV::SEXT_B:
1110 case RISCV::SEXT_H:
1111 case RISCV::ZEXT_H_RV32:
1112 case RISCV::ZEXT_H_RV64:
1113 // c.sext.b, c.sext.h, c.zext.h
1114 NeedGPRC = true;
1115 return Subtarget.hasStdExtZcb() && Subtarget.hasStdExtZbb();
1116 case RISCV::ADD_UW:
1117 // c.zext.w
1118 NeedGPRC = true;
1119 return Subtarget.hasStdExtZcb() && MI.getOperand(i: 2).isReg() &&
1120 MI.getOperand(i: 2).getReg() == RISCV::X0;
1121 case RISCV::XORI:
1122 // c.not
1123 NeedGPRC = true;
1124 return Subtarget.hasStdExtZcb() && MI.getOperand(i: 2).isImm() &&
1125 MI.getOperand(i: 2).getImm() == -1;
1126 case RISCV::QC_EXTU:
1127 return MI.getOperand(i: 2).getImm() >= 6 && MI.getOperand(i: 3).getImm() == 0;
1128 case RISCV::BSETI:
1129 case RISCV::BEXTI:
1130 // qc.c.bseti, qc.c.bexti
1131 NeedGPRC = true;
1132 return Subtarget.hasVendorXqcibm() && MI.getOperand(i: 2).getImm() != 0;
1133 }
1134 };
1135
1136 // Returns true if this operand is compressible. For non-registers it always
1137 // returns true. Immediate range was already checked in isCompressible.
1138 // For registers, it checks if the register is a GPRC register. reg-reg
1139 // instructions that require GPRC need all register operands to be GPRC.
1140 auto isCompressibleOpnd = [&](const MachineOperand &MO) {
1141 if (!MO.isReg())
1142 return true;
1143 Register Reg = MO.getReg();
1144 Register PhysReg = Reg.isPhysical() ? Reg : Register(VRM->getPhys(virtReg: Reg));
1145 return PhysReg && RISCV::GPRCRegClass.contains(Reg: PhysReg);
1146 };
1147
1148 for (auto &MO : MRI->reg_nodbg_operands(Reg: VirtReg)) {
1149 const MachineInstr &MI = *MO.getParent();
1150 unsigned OpIdx = MO.getOperandNo();
1151 bool NeedGPRC;
1152 if (isCompressible(MI, NeedGPRC)) {
1153 if (OpIdx == 0 && MI.getOperand(i: 1).isReg()) {
1154 if (!NeedGPRC || MI.getNumExplicitOperands() < 3 ||
1155 MI.getOpcode() == RISCV::ADD_UW ||
1156 isCompressibleOpnd(MI.getOperand(i: 2)))
1157 tryAddHint(MO, MI.getOperand(i: 1), NeedGPRC);
1158 if (MI.isCommutable() && MI.getOperand(i: 2).isReg() &&
1159 (!NeedGPRC || isCompressibleOpnd(MI.getOperand(i: 1))))
1160 tryAddHint(MO, MI.getOperand(i: 2), NeedGPRC);
1161 } else if (OpIdx == 1 && (!NeedGPRC || MI.getNumExplicitOperands() < 3 ||
1162 isCompressibleOpnd(MI.getOperand(i: 2)))) {
1163 tryAddHint(MO, MI.getOperand(i: 0), NeedGPRC);
1164 } else if (MI.isCommutable() && OpIdx == 2 &&
1165 (!NeedGPRC || isCompressibleOpnd(MI.getOperand(i: 1)))) {
1166 tryAddHint(MO, MI.getOperand(i: 0), NeedGPRC);
1167 }
1168 }
1169
1170 // Add a hint if it would allow auipc/lui+addi(w) fusion. We do this even
1171 // without the fusions explicitly enabled as the impact is rarely negative
1172 // and some cores do implement this fusion.
1173 if ((MI.getOpcode() == RISCV::ADDIW || MI.getOpcode() == RISCV::ADDI) &&
1174 MI.getOperand(i: 1).isReg()) {
1175 const MachineBasicBlock &MBB = *MI.getParent();
1176 MachineBasicBlock::const_iterator I = MI.getIterator();
1177 // Is the previous instruction a LUI or AUIPC that can be fused?
1178 if (I != MBB.begin()) {
1179 I = skipDebugInstructionsBackward(It: std::prev(x: I), Begin: MBB.begin());
1180 if ((I->getOpcode() == RISCV::LUI || I->getOpcode() == RISCV::AUIPC) &&
1181 I->getOperand(i: 0).getReg() == MI.getOperand(i: 1).getReg()) {
1182 if (OpIdx == 0)
1183 tryAddHint(MO, MI.getOperand(i: 1), /*NeedGPRC=*/false);
1184 else
1185 tryAddHint(MO, MI.getOperand(i: 0), /*NeedGPRC=*/false);
1186 }
1187 }
1188 }
1189 }
1190
1191 for (MCPhysReg OrderReg : Order)
1192 if (TwoAddrHints.count(V: OrderReg))
1193 Hints.push_back(Elt: OrderReg);
1194
1195 return BaseImplRetVal;
1196}
1197
1198void RISCVRegisterInfo::updateRegAllocHint(Register Reg, Register NewReg,
1199 MachineFunction &MF) const {
1200 MachineRegisterInfo *MRI = &MF.getRegInfo();
1201 std::pair<unsigned, Register> Hint = MRI->getRegAllocationHint(VReg: Reg);
1202
1203 // Handle RegPairEven/RegPairOdd hints for Zilsd register pairs
1204 if ((Hint.first == RISCVRI::RegPairOdd ||
1205 Hint.first == RISCVRI::RegPairEven) &&
1206 Hint.second.isVirtual()) {
1207 // If 'Reg' is one of the even/odd register pair and it's now changed
1208 // (e.g. coalesced) into a different register, the other register of the
1209 // pair allocation hint must be updated to reflect the relationship change.
1210 Register Partner = Hint.second;
1211 std::pair<unsigned, Register> PartnerHint =
1212 MRI->getRegAllocationHint(VReg: Partner);
1213
1214 // Make sure partner still points to us
1215 if (PartnerHint.second == Reg) {
1216 // Update partner to point to NewReg instead of Reg
1217 MRI->setRegAllocationHint(VReg: Partner, Type: PartnerHint.first, PrefReg: NewReg);
1218
1219 // If NewReg is virtual, set up the reciprocal hint
1220 // NewReg takes over Reg's role, so it gets the SAME hint type as Reg
1221 if (NewReg.isVirtual())
1222 MRI->setRegAllocationHint(VReg: NewReg, Type: Hint.first, PrefReg: Partner);
1223 }
1224 }
1225}
1226
1227Register
1228RISCVRegisterInfo::findVRegWithEncoding(const TargetRegisterClass &RegClass,
1229 uint16_t Encoding) const {
1230 MCRegister Reg = RISCV::V0 + Encoding;
1231 if (RISCVRI::getLMul(TSFlags: RegClass.TSFlags) == RISCVVType::LMUL_1)
1232 return Reg;
1233 return getMatchingSuperReg(Reg, SubIdx: RISCV::sub_vrm1_0, RC: &RegClass);
1234}
1235