1//===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the SystemZTargetLowering class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "SystemZISelLowering.h"
14#include "SystemZCallingConv.h"
15#include "SystemZConstantPoolValue.h"
16#include "SystemZMachineFunctionInfo.h"
17#include "llvm/ADT/SmallSet.h"
18#include "llvm/CodeGen/CallingConvLower.h"
19#include "llvm/CodeGen/ISDOpcodes.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
22#include "llvm/IR/GlobalAlias.h"
23#include "llvm/IR/IntrinsicInst.h"
24#include "llvm/IR/Intrinsics.h"
25#include "llvm/IR/IntrinsicsS390.h"
26#include "llvm/IR/Module.h"
27#include "llvm/IR/PatternMatch.h"
28#include "llvm/Support/CommandLine.h"
29#include "llvm/Support/ErrorHandling.h"
30#include "llvm/Support/KnownBits.h"
31#include "llvm/Target/TargetMachine.h"
32#include <cctype>
33#include <optional>
34
35using namespace llvm;
36
37#define DEBUG_TYPE "systemz-lower"
38
39// Temporarily let this be disabled by default until all known problems
40// related to argument extensions are fixed.
41static cl::opt<bool> EnableIntArgExtCheck(
42 "argext-abi-check", cl::init(Val: false),
43 cl::desc("Verify that narrow int args are properly extended per the "
44 "SystemZ ABI."));
45
46namespace {
47// Represents information about a comparison.
48struct Comparison {
49 Comparison(SDValue Op0In, SDValue Op1In, SDValue ChainIn)
50 : Op0(Op0In), Op1(Op1In), Chain(ChainIn),
51 Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {}
52
53 // The operands to the comparison.
54 SDValue Op0, Op1;
55
56 // Chain if this is a strict floating-point comparison.
57 SDValue Chain;
58
59 // The opcode that should be used to compare Op0 and Op1.
60 unsigned Opcode;
61
62 // A SystemZICMP value. Only used for integer comparisons.
63 unsigned ICmpType;
64
65 // The mask of CC values that Opcode can produce.
66 unsigned CCValid;
67
68 // The mask of CC values for which the original condition is true.
69 unsigned CCMask;
70};
71} // end anonymous namespace
72
73// Classify VT as either 32 or 64 bit.
74static bool is32Bit(EVT VT) {
75 switch (VT.getSimpleVT().SimpleTy) {
76 case MVT::i32:
77 return true;
78 case MVT::i64:
79 return false;
80 default:
81 llvm_unreachable("Unsupported type");
82 }
83}
84
85// Return a version of MachineOperand that can be safely used before the
86// final use.
87static MachineOperand earlyUseOperand(MachineOperand Op) {
88 if (Op.isReg())
89 Op.setIsKill(false);
90 return Op;
91}
92
93SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
94 const SystemZSubtarget &STI)
95 : TargetLowering(TM, STI), Subtarget(STI) {
96 MVT PtrVT = MVT::getIntegerVT(BitWidth: TM.getPointerSizeInBits(AS: 0));
97
98 auto *Regs = STI.getSpecialRegisters();
99
100 // Set up the register classes.
101 if (Subtarget.hasHighWord())
102 addRegisterClass(VT: MVT::i32, RC: &SystemZ::GRX32BitRegClass);
103 else
104 addRegisterClass(VT: MVT::i32, RC: &SystemZ::GR32BitRegClass);
105 addRegisterClass(VT: MVT::i64, RC: &SystemZ::GR64BitRegClass);
106 if (!useSoftFloat()) {
107 if (Subtarget.hasVector()) {
108 addRegisterClass(VT: MVT::f16, RC: &SystemZ::VR16BitRegClass);
109 addRegisterClass(VT: MVT::f32, RC: &SystemZ::VR32BitRegClass);
110 addRegisterClass(VT: MVT::f64, RC: &SystemZ::VR64BitRegClass);
111 } else {
112 addRegisterClass(VT: MVT::f16, RC: &SystemZ::FP16BitRegClass);
113 addRegisterClass(VT: MVT::f32, RC: &SystemZ::FP32BitRegClass);
114 addRegisterClass(VT: MVT::f64, RC: &SystemZ::FP64BitRegClass);
115 }
116 if (Subtarget.hasVectorEnhancements1())
117 addRegisterClass(VT: MVT::f128, RC: &SystemZ::VR128BitRegClass);
118 else
119 addRegisterClass(VT: MVT::f128, RC: &SystemZ::FP128BitRegClass);
120
121 if (Subtarget.hasVector()) {
122 addRegisterClass(VT: MVT::v16i8, RC: &SystemZ::VR128BitRegClass);
123 addRegisterClass(VT: MVT::v8i16, RC: &SystemZ::VR128BitRegClass);
124 addRegisterClass(VT: MVT::v4i32, RC: &SystemZ::VR128BitRegClass);
125 addRegisterClass(VT: MVT::v2i64, RC: &SystemZ::VR128BitRegClass);
126 addRegisterClass(VT: MVT::v8f16, RC: &SystemZ::VR128BitRegClass);
127 addRegisterClass(VT: MVT::v4f32, RC: &SystemZ::VR128BitRegClass);
128 addRegisterClass(VT: MVT::v2f64, RC: &SystemZ::VR128BitRegClass);
129 }
130
131 if (Subtarget.hasVector())
132 addRegisterClass(VT: MVT::i128, RC: &SystemZ::VR128BitRegClass);
133 }
134
135 // Compute derived properties from the register classes
136 computeRegisterProperties(TRI: Subtarget.getRegisterInfo());
137
138 // Set up special registers.
139 setStackPointerRegisterToSaveRestore(Regs->getStackPointerRegister());
140
141 // TODO: It may be better to default to latency-oriented scheduling, however
142 // LLVM's current latency-oriented scheduler can't handle physreg definitions
143 // such as SystemZ has with CC, so set this to the register-pressure
144 // scheduler, because it can.
145 setSchedulingPreference(Sched::RegPressure);
146
147 setBooleanContents(ZeroOrOneBooleanContent);
148 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
149
150 setMaxAtomicSizeInBitsSupported(128);
151
152 // Instructions are strings of 2-byte aligned 2-byte values.
153 setMinFunctionAlignment(Align(2));
154 // For performance reasons we prefer 16-byte alignment.
155 setPrefFunctionAlignment(Align(16));
156
157 // Handle operations that are handled in a similar way for all types.
158 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
159 I <= MVT::LAST_FP_VALUETYPE;
160 ++I) {
161 MVT VT = MVT::SimpleValueType(I);
162 if (isTypeLegal(VT)) {
163 // Lower SET_CC into an IPM-based sequence.
164 setOperationAction(Op: ISD::SETCC, VT, Action: Custom);
165 setOperationAction(Op: ISD::STRICT_FSETCC, VT, Action: Custom);
166 setOperationAction(Op: ISD::STRICT_FSETCCS, VT, Action: Custom);
167
168 // Expand SELECT(C, A, B) into SELECT_CC(X, 0, A, B, NE).
169 setOperationAction(Op: ISD::SELECT, VT, Action: Expand);
170
171 // Lower SELECT_CC and BR_CC into separate comparisons and branches.
172 setOperationAction(Op: ISD::SELECT_CC, VT, Action: Custom);
173 setOperationAction(Op: ISD::BR_CC, VT, Action: Custom);
174 }
175 }
176
177 // Expand jump table branches as address arithmetic followed by an
178 // indirect jump.
179 setOperationAction(Op: ISD::BR_JT, VT: MVT::Other, Action: Expand);
180
181 // Expand BRCOND into a BR_CC (see above).
182 setOperationAction(Op: ISD::BRCOND, VT: MVT::Other, Action: Expand);
183
184 // Handle integer types except i128.
185 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
186 I <= MVT::LAST_INTEGER_VALUETYPE;
187 ++I) {
188 MVT VT = MVT::SimpleValueType(I);
189 if (isTypeLegal(VT) && VT != MVT::i128) {
190 setOperationAction(Op: ISD::ABS, VT, Action: Legal);
191
192 // Expand individual DIV and REMs into DIVREMs.
193 setOperationAction(Op: ISD::SDIV, VT, Action: Expand);
194 setOperationAction(Op: ISD::UDIV, VT, Action: Expand);
195 setOperationAction(Op: ISD::SREM, VT, Action: Expand);
196 setOperationAction(Op: ISD::UREM, VT, Action: Expand);
197 setOperationAction(Op: ISD::SDIVREM, VT, Action: Custom);
198 setOperationAction(Op: ISD::UDIVREM, VT, Action: Custom);
199
200 // Support addition/subtraction with overflow.
201 setOperationAction(Op: ISD::SADDO, VT, Action: Custom);
202 setOperationAction(Op: ISD::SSUBO, VT, Action: Custom);
203
204 // Support addition/subtraction with carry.
205 setOperationAction(Op: ISD::UADDO, VT, Action: Custom);
206 setOperationAction(Op: ISD::USUBO, VT, Action: Custom);
207
208 // Support carry in as value rather than glue.
209 setOperationAction(Op: ISD::UADDO_CARRY, VT, Action: Custom);
210 setOperationAction(Op: ISD::USUBO_CARRY, VT, Action: Custom);
211
212 // Lower ATOMIC_LOAD_SUB into ATOMIC_LOAD_ADD if LAA and LAAG are
213 // available, or if the operand is constant.
214 setOperationAction(Op: ISD::ATOMIC_LOAD_SUB, VT, Action: Custom);
215
216 // Use POPCNT on z196 and above.
217 if (Subtarget.hasPopulationCount())
218 setOperationAction(Op: ISD::CTPOP, VT, Action: Custom);
219 else
220 setOperationAction(Op: ISD::CTPOP, VT, Action: Expand);
221
222 // No special instructions for these.
223 setOperationAction(Op: ISD::CTTZ, VT, Action: Expand);
224 setOperationAction(Op: ISD::ROTR, VT, Action: Expand);
225
226 // Use *MUL_LOHI where possible instead of MULH*.
227 setOperationAction(Op: ISD::MULHS, VT, Action: Expand);
228 setOperationAction(Op: ISD::MULHU, VT, Action: Expand);
229 setOperationAction(Op: ISD::SMUL_LOHI, VT, Action: Custom);
230 setOperationAction(Op: ISD::UMUL_LOHI, VT, Action: Custom);
231
232 // The fp<=>i32/i64 conversions are all Legal except for f16 and for
233 // unsigned on z10 (only z196 and above have native support for
234 // unsigned conversions).
235 for (auto Op : {ISD::FP_TO_SINT, ISD::STRICT_FP_TO_SINT,
236 ISD::SINT_TO_FP, ISD::STRICT_SINT_TO_FP})
237 setOperationAction(Op, VT, Action: Custom);
238 for (auto Op : {ISD::FP_TO_UINT, ISD::STRICT_FP_TO_UINT})
239 setOperationAction(Op, VT, Action: Custom);
240 for (auto Op : {ISD::UINT_TO_FP, ISD::STRICT_UINT_TO_FP}) {
241 // Handle unsigned 32-bit input types as signed 64-bit types on z10.
242 auto OpAction =
243 (!Subtarget.hasFPExtension() && VT == MVT::i32) ? Promote : Custom;
244 setOperationAction(Op, VT, Action: OpAction);
245 }
246 }
247 }
248
249 // Handle i128 if legal.
250 if (isTypeLegal(VT: MVT::i128)) {
251 // No special instructions for these.
252 setOperationAction(Op: ISD::SDIVREM, VT: MVT::i128, Action: Expand);
253 setOperationAction(Op: ISD::UDIVREM, VT: MVT::i128, Action: Expand);
254 setOperationAction(Op: ISD::SMUL_LOHI, VT: MVT::i128, Action: Expand);
255 setOperationAction(Op: ISD::UMUL_LOHI, VT: MVT::i128, Action: Expand);
256 setOperationAction(Op: ISD::ROTR, VT: MVT::i128, Action: Expand);
257 setOperationAction(Op: ISD::ROTL, VT: MVT::i128, Action: Expand);
258
259 // We may be able to use VSLDB/VSLD/VSRD for these.
260 setOperationAction(Op: ISD::FSHL, VT: MVT::i128, Action: Custom);
261 setOperationAction(Op: ISD::FSHR, VT: MVT::i128, Action: Custom);
262
263 // No special instructions for these before z17.
264 if (!Subtarget.hasVectorEnhancements3()) {
265 setOperationAction(Op: ISD::MUL, VT: MVT::i128, Action: Expand);
266 setOperationAction(Op: ISD::MULHS, VT: MVT::i128, Action: Expand);
267 setOperationAction(Op: ISD::MULHU, VT: MVT::i128, Action: Expand);
268 setOperationAction(Op: ISD::SDIV, VT: MVT::i128, Action: Expand);
269 setOperationAction(Op: ISD::UDIV, VT: MVT::i128, Action: Expand);
270 setOperationAction(Op: ISD::SREM, VT: MVT::i128, Action: Expand);
271 setOperationAction(Op: ISD::UREM, VT: MVT::i128, Action: Expand);
272 setOperationAction(Op: ISD::CTLZ, VT: MVT::i128, Action: Expand);
273 setOperationAction(Op: ISD::CTTZ, VT: MVT::i128, Action: Expand);
274 } else {
275 // Even if we do have a legal 128-bit multiply, we do not
276 // want 64-bit multiply-high operations to use it.
277 setOperationAction(Op: ISD::MULHS, VT: MVT::i64, Action: Custom);
278 setOperationAction(Op: ISD::MULHU, VT: MVT::i64, Action: Custom);
279 }
280
281 // Support addition/subtraction with carry.
282 setOperationAction(Op: ISD::UADDO, VT: MVT::i128, Action: Custom);
283 setOperationAction(Op: ISD::USUBO, VT: MVT::i128, Action: Custom);
284 setOperationAction(Op: ISD::UADDO_CARRY, VT: MVT::i128, Action: Custom);
285 setOperationAction(Op: ISD::USUBO_CARRY, VT: MVT::i128, Action: Custom);
286
287 // Use VPOPCT and add up partial results.
288 setOperationAction(Op: ISD::CTPOP, VT: MVT::i128, Action: Custom);
289
290 // Additional instructions available with z17.
291 if (Subtarget.hasVectorEnhancements3()) {
292 setOperationAction(Op: ISD::ABS, VT: MVT::i128, Action: Legal);
293
294 setOperationAction(Ops: {ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX},
295 VT: MVT::i128, Action: Legal);
296 }
297 }
298
299 // These need custom handling in order to handle the f16 conversions.
300 setOperationAction(Op: ISD::FP_TO_UINT, VT: MVT::i128, Action: Custom);
301 setOperationAction(Op: ISD::FP_TO_SINT, VT: MVT::i128, Action: Custom);
302 setOperationAction(Op: ISD::UINT_TO_FP, VT: MVT::i128, Action: Custom);
303 setOperationAction(Op: ISD::SINT_TO_FP, VT: MVT::i128, Action: Custom);
304 setOperationAction(Op: ISD::STRICT_FP_TO_UINT, VT: MVT::i128, Action: Custom);
305 setOperationAction(Op: ISD::STRICT_FP_TO_SINT, VT: MVT::i128, Action: Custom);
306 setOperationAction(Op: ISD::STRICT_UINT_TO_FP, VT: MVT::i128, Action: Custom);
307 setOperationAction(Op: ISD::STRICT_SINT_TO_FP, VT: MVT::i128, Action: Custom);
308
309 // Type legalization will convert 8- and 16-bit atomic operations into
310 // forms that operate on i32s (but still keeping the original memory VT).
311 // Lower them into full i32 operations.
312 setOperationAction(Op: ISD::ATOMIC_SWAP, VT: MVT::i32, Action: Custom);
313 setOperationAction(Op: ISD::ATOMIC_LOAD_ADD, VT: MVT::i32, Action: Custom);
314 setOperationAction(Op: ISD::ATOMIC_LOAD_SUB, VT: MVT::i32, Action: Custom);
315 setOperationAction(Op: ISD::ATOMIC_LOAD_AND, VT: MVT::i32, Action: Custom);
316 setOperationAction(Op: ISD::ATOMIC_LOAD_OR, VT: MVT::i32, Action: Custom);
317 setOperationAction(Op: ISD::ATOMIC_LOAD_XOR, VT: MVT::i32, Action: Custom);
318 setOperationAction(Op: ISD::ATOMIC_LOAD_NAND, VT: MVT::i32, Action: Custom);
319 setOperationAction(Op: ISD::ATOMIC_LOAD_MIN, VT: MVT::i32, Action: Custom);
320 setOperationAction(Op: ISD::ATOMIC_LOAD_MAX, VT: MVT::i32, Action: Custom);
321 setOperationAction(Op: ISD::ATOMIC_LOAD_UMIN, VT: MVT::i32, Action: Custom);
322 setOperationAction(Op: ISD::ATOMIC_LOAD_UMAX, VT: MVT::i32, Action: Custom);
323
324 // Whether or not i128 is not a legal type, we need to custom lower
325 // the atomic operations in order to exploit SystemZ instructions.
326 setOperationAction(Op: ISD::ATOMIC_LOAD, VT: MVT::i128, Action: Custom);
327 setOperationAction(Op: ISD::ATOMIC_STORE, VT: MVT::i128, Action: Custom);
328 setOperationAction(Op: ISD::ATOMIC_LOAD, VT: MVT::f128, Action: Custom);
329 setOperationAction(Op: ISD::ATOMIC_STORE, VT: MVT::f128, Action: Custom);
330
331 // Mark sign/zero extending atomic loads as legal, which will make
332 // DAGCombiner fold extensions into atomic loads if possible.
333 setAtomicLoadExtAction(ExtTypes: {ISD::SEXTLOAD, ISD::ZEXTLOAD}, ValVT: MVT::i64,
334 MemVTs: {MVT::i8, MVT::i16, MVT::i32}, Action: Legal);
335 setAtomicLoadExtAction(ExtTypes: {ISD::SEXTLOAD, ISD::ZEXTLOAD}, ValVT: MVT::i32,
336 MemVTs: {MVT::i8, MVT::i16}, Action: Legal);
337 setAtomicLoadExtAction(ExtTypes: {ISD::SEXTLOAD, ISD::ZEXTLOAD}, ValVT: MVT::i16,
338 MemVT: MVT::i8, Action: Legal);
339
340 // We can use the CC result of compare-and-swap to implement
341 // the "success" result of ATOMIC_CMP_SWAP_WITH_SUCCESS.
342 setOperationAction(Op: ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT: MVT::i32, Action: Custom);
343 setOperationAction(Op: ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT: MVT::i64, Action: Custom);
344 setOperationAction(Op: ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT: MVT::i128, Action: Custom);
345
346 setOperationAction(Op: ISD::ATOMIC_FENCE, VT: MVT::Other, Action: Custom);
347
348 // Traps are legal, as we will convert them to "j .+2".
349 setOperationAction(Op: ISD::TRAP, VT: MVT::Other, Action: Legal);
350
351 // We have native support for a 64-bit CTLZ, via FLOGR.
352 setOperationAction(Op: ISD::CTLZ, VT: MVT::i32, Action: Promote);
353 setOperationAction(Op: ISD::CTLZ_ZERO_POISON, VT: MVT::i32, Action: Promote);
354 setOperationAction(Op: ISD::CTLZ, VT: MVT::i64, Action: Legal);
355
356 // On z17 we have native support for a 64-bit CTTZ.
357 if (Subtarget.hasMiscellaneousExtensions4()) {
358 setOperationAction(Op: ISD::CTTZ, VT: MVT::i32, Action: Promote);
359 setOperationAction(Op: ISD::CTTZ_ZERO_POISON, VT: MVT::i32, Action: Promote);
360 setOperationAction(Op: ISD::CTTZ, VT: MVT::i64, Action: Legal);
361 }
362
363 // On z15 we have native support for a 64-bit CTPOP.
364 if (Subtarget.hasMiscellaneousExtensions3()) {
365 setOperationAction(Op: ISD::CTPOP, VT: MVT::i32, Action: Promote);
366 setOperationAction(Op: ISD::CTPOP, VT: MVT::i64, Action: Legal);
367 }
368
369 // Give LowerOperation the chance to replace 64-bit ORs with subregs.
370 setOperationAction(Op: ISD::OR, VT: MVT::i64, Action: Custom);
371
372 // Expand 128 bit shifts without using a libcall.
373 setOperationAction(Op: ISD::SRL_PARTS, VT: MVT::i64, Action: Expand);
374 setOperationAction(Op: ISD::SHL_PARTS, VT: MVT::i64, Action: Expand);
375 setOperationAction(Op: ISD::SRA_PARTS, VT: MVT::i64, Action: Expand);
376
377 // Also expand 256 bit shifts if i128 is a legal type.
378 if (isTypeLegal(VT: MVT::i128)) {
379 setOperationAction(Op: ISD::SRL_PARTS, VT: MVT::i128, Action: Expand);
380 setOperationAction(Op: ISD::SHL_PARTS, VT: MVT::i128, Action: Expand);
381 setOperationAction(Op: ISD::SRA_PARTS, VT: MVT::i128, Action: Expand);
382 }
383
384 // Handle bitcast from fp128 to i128.
385 if (!isTypeLegal(VT: MVT::i128))
386 setOperationAction(Op: ISD::BITCAST, VT: MVT::i128, Action: Custom);
387
388 // We have native instructions for i8, i16 and i32 extensions, but not i1.
389 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: MVT::i1, Action: Expand);
390 for (MVT VT : MVT::integer_valuetypes()) {
391 setLoadExtAction(ExtType: ISD::SEXTLOAD, ValVT: VT, MemVT: MVT::i1, Action: Promote);
392 setLoadExtAction(ExtType: ISD::ZEXTLOAD, ValVT: VT, MemVT: MVT::i1, Action: Promote);
393 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: VT, MemVT: MVT::i1, Action: Promote);
394 }
395
396 // Handle the various types of symbolic address.
397 setOperationAction(Op: ISD::ConstantPool, VT: PtrVT, Action: Custom);
398 setOperationAction(Op: ISD::GlobalAddress, VT: PtrVT, Action: Custom);
399 setOperationAction(Op: ISD::GlobalTLSAddress, VT: PtrVT, Action: Custom);
400 setOperationAction(Op: ISD::BlockAddress, VT: PtrVT, Action: Custom);
401 setOperationAction(Op: ISD::JumpTable, VT: PtrVT, Action: Custom);
402
403 // We need to handle dynamic allocations specially because of the
404 // 160-byte area at the bottom of the stack.
405 setOperationAction(Op: ISD::DYNAMIC_STACKALLOC, VT: PtrVT, Action: Custom);
406 setOperationAction(Op: ISD::GET_DYNAMIC_AREA_OFFSET, VT: PtrVT, Action: Custom);
407
408 setOperationAction(Op: ISD::STACKSAVE, VT: MVT::Other, Action: Custom);
409 setOperationAction(Op: ISD::STACKRESTORE, VT: MVT::Other, Action: Custom);
410
411 // Handle prefetches with PFD or PFDRL.
412 setOperationAction(Op: ISD::PREFETCH, VT: MVT::Other, Action: Custom);
413
414 // Handle readcyclecounter with STCKF.
415 setOperationAction(Op: ISD::READCYCLECOUNTER, VT: MVT::i64, Action: Custom);
416
417 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
418 // Assume by default that all vector operations need to be expanded.
419 for (unsigned Opcode = 0; Opcode < ISD::BUILTIN_OP_END; ++Opcode)
420 if (getOperationAction(Op: Opcode, VT) == Legal)
421 setOperationAction(Op: Opcode, VT, Action: Expand);
422
423 // Likewise all truncating stores and extending loads.
424 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
425 setTruncStoreAction(ValVT: VT, MemVT: InnerVT, Action: Expand);
426 setLoadExtAction(ExtType: ISD::SEXTLOAD, ValVT: VT, MemVT: InnerVT, Action: Expand);
427 setLoadExtAction(ExtType: ISD::ZEXTLOAD, ValVT: VT, MemVT: InnerVT, Action: Expand);
428 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: VT, MemVT: InnerVT, Action: Expand);
429 }
430
431 if (isTypeLegal(VT)) {
432 // These operations are legal for anything that can be stored in a
433 // vector register, even if there is no native support for the format
434 // as such. In particular, we can do these for v4f32 even though there
435 // are no specific instructions for that format.
436 setOperationAction(Op: ISD::LOAD, VT, Action: Legal);
437 setOperationAction(Op: ISD::STORE, VT, Action: Legal);
438 setOperationAction(Op: ISD::VSELECT, VT, Action: Legal);
439 setOperationAction(Op: ISD::BITCAST, VT, Action: Legal);
440 setOperationAction(Ops: {ISD::UNDEF, ISD::POISON}, VT, Action: Legal);
441
442 // Likewise, except that we need to replace the nodes with something
443 // more specific.
444 setOperationAction(Op: ISD::BUILD_VECTOR, VT, Action: Custom);
445 setOperationAction(Op: ISD::VECTOR_SHUFFLE, VT, Action: Custom);
446 }
447 }
448
449 // Handle integer vector types.
450 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) {
451 if (isTypeLegal(VT)) {
452 // These operations have direct equivalents.
453 setOperationAction(Op: ISD::EXTRACT_VECTOR_ELT, VT, Action: Legal);
454 setOperationAction(Op: ISD::INSERT_VECTOR_ELT, VT, Action: Legal);
455 setOperationAction(Op: ISD::ADD, VT, Action: Legal);
456 setOperationAction(Op: ISD::SUB, VT, Action: Legal);
457 if (VT != MVT::v2i64 || Subtarget.hasVectorEnhancements3()) {
458 setOperationAction(Op: ISD::MUL, VT, Action: Legal);
459 setOperationAction(Op: ISD::MULHS, VT, Action: Legal);
460 setOperationAction(Op: ISD::MULHU, VT, Action: Legal);
461 }
462 if (Subtarget.hasVectorEnhancements3() &&
463 VT != MVT::v16i8 && VT != MVT::v8i16) {
464 setOperationAction(Op: ISD::SDIV, VT, Action: Legal);
465 setOperationAction(Op: ISD::UDIV, VT, Action: Legal);
466 setOperationAction(Op: ISD::SREM, VT, Action: Legal);
467 setOperationAction(Op: ISD::UREM, VT, Action: Legal);
468 }
469 setOperationAction(Op: ISD::ABS, VT, Action: Legal);
470 setOperationAction(Op: ISD::AND, VT, Action: Legal);
471 setOperationAction(Op: ISD::OR, VT, Action: Legal);
472 setOperationAction(Op: ISD::XOR, VT, Action: Legal);
473 if (Subtarget.hasVectorEnhancements1())
474 setOperationAction(Op: ISD::CTPOP, VT, Action: Legal);
475 else
476 setOperationAction(Op: ISD::CTPOP, VT, Action: Custom);
477 setOperationAction(Op: ISD::CTTZ, VT, Action: Legal);
478 setOperationAction(Op: ISD::CTLZ, VT, Action: Legal);
479
480 // Convert a GPR scalar to a vector by inserting it into element 0.
481 setOperationAction(Op: ISD::SCALAR_TO_VECTOR, VT, Action: Custom);
482
483 // Use a series of unpacks for extensions.
484 setOperationAction(Op: ISD::SIGN_EXTEND_VECTOR_INREG, VT, Action: Custom);
485 setOperationAction(Op: ISD::ZERO_EXTEND_VECTOR_INREG, VT, Action: Custom);
486
487 // Detect shifts/rotates by a scalar amount and convert them into
488 // V*_BY_SCALAR.
489 setOperationAction(Op: ISD::SHL, VT, Action: Custom);
490 setOperationAction(Op: ISD::SRA, VT, Action: Custom);
491 setOperationAction(Op: ISD::SRL, VT, Action: Custom);
492 setOperationAction(Op: ISD::ROTL, VT, Action: Custom);
493
494 // Add ISD::VECREDUCE_ADD as custom in order to implement
495 // it with VZERO+VSUM
496 setOperationAction(Op: ISD::VECREDUCE_ADD, VT, Action: Custom);
497
498 // Map SETCCs onto one of VCE, VCH or VCHL, swapping the operands
499 // and inverting the result as necessary.
500 setOperationAction(Op: ISD::SETCC, VT, Action: Custom);
501
502 setOperationAction(Ops: {ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX}, VT,
503 Action: Legal);
504 }
505 }
506
507 if (Subtarget.hasVector()) {
508 // There should be no need to check for float types other than v2f64
509 // since <2 x f32> isn't a legal type.
510 setOperationAction(Op: ISD::FP_TO_SINT, VT: MVT::v2i64, Action: Legal);
511 setOperationAction(Op: ISD::FP_TO_SINT, VT: MVT::v2f64, Action: Legal);
512 setOperationAction(Op: ISD::FP_TO_UINT, VT: MVT::v2i64, Action: Legal);
513 setOperationAction(Op: ISD::FP_TO_UINT, VT: MVT::v2f64, Action: Legal);
514 setOperationAction(Op: ISD::SINT_TO_FP, VT: MVT::v2i64, Action: Legal);
515 setOperationAction(Op: ISD::SINT_TO_FP, VT: MVT::v2f64, Action: Legal);
516 setOperationAction(Op: ISD::UINT_TO_FP, VT: MVT::v2i64, Action: Legal);
517 setOperationAction(Op: ISD::UINT_TO_FP, VT: MVT::v2f64, Action: Legal);
518
519 setOperationAction(Op: ISD::STRICT_FP_TO_SINT, VT: MVT::v2i64, Action: Legal);
520 setOperationAction(Op: ISD::STRICT_FP_TO_SINT, VT: MVT::v2f64, Action: Legal);
521 setOperationAction(Op: ISD::STRICT_FP_TO_UINT, VT: MVT::v2i64, Action: Legal);
522 setOperationAction(Op: ISD::STRICT_FP_TO_UINT, VT: MVT::v2f64, Action: Legal);
523 setOperationAction(Op: ISD::STRICT_SINT_TO_FP, VT: MVT::v2i64, Action: Legal);
524 setOperationAction(Op: ISD::STRICT_SINT_TO_FP, VT: MVT::v2f64, Action: Legal);
525 setOperationAction(Op: ISD::STRICT_UINT_TO_FP, VT: MVT::v2i64, Action: Legal);
526 setOperationAction(Op: ISD::STRICT_UINT_TO_FP, VT: MVT::v2f64, Action: Legal);
527 }
528
529 if (Subtarget.hasVectorEnhancements2()) {
530 setOperationAction(Op: ISD::FP_TO_SINT, VT: MVT::v4i32, Action: Legal);
531 setOperationAction(Op: ISD::FP_TO_SINT, VT: MVT::v4f32, Action: Legal);
532 setOperationAction(Op: ISD::FP_TO_UINT, VT: MVT::v4i32, Action: Legal);
533 setOperationAction(Op: ISD::FP_TO_UINT, VT: MVT::v4f32, Action: Legal);
534 setOperationAction(Op: ISD::SINT_TO_FP, VT: MVT::v4i32, Action: Legal);
535 setOperationAction(Op: ISD::SINT_TO_FP, VT: MVT::v4f32, Action: Legal);
536 setOperationAction(Op: ISD::UINT_TO_FP, VT: MVT::v4i32, Action: Legal);
537 setOperationAction(Op: ISD::UINT_TO_FP, VT: MVT::v4f32, Action: Legal);
538
539 setOperationAction(Op: ISD::STRICT_FP_TO_SINT, VT: MVT::v4i32, Action: Legal);
540 setOperationAction(Op: ISD::STRICT_FP_TO_SINT, VT: MVT::v4f32, Action: Legal);
541 setOperationAction(Op: ISD::STRICT_FP_TO_UINT, VT: MVT::v4i32, Action: Legal);
542 setOperationAction(Op: ISD::STRICT_FP_TO_UINT, VT: MVT::v4f32, Action: Legal);
543 setOperationAction(Op: ISD::STRICT_SINT_TO_FP, VT: MVT::v4i32, Action: Legal);
544 setOperationAction(Op: ISD::STRICT_SINT_TO_FP, VT: MVT::v4f32, Action: Legal);
545 setOperationAction(Op: ISD::STRICT_UINT_TO_FP, VT: MVT::v4i32, Action: Legal);
546 setOperationAction(Op: ISD::STRICT_UINT_TO_FP, VT: MVT::v4f32, Action: Legal);
547 }
548
549 // Handle floating-point types.
550 if (!useSoftFloat()) {
551 // Promote all f16 operations to float, with some exceptions below.
552 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
553 setOperationAction(Op: Opc, VT: MVT::f16, Action: Promote);
554 setOperationAction(Op: ISD::ConstantFP, VT: MVT::f16, Action: Expand);
555 for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) {
556 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: VT, MemVT: MVT::f16, Action: Expand);
557 setTruncStoreAction(ValVT: VT, MemVT: MVT::f16, Action: Expand);
558 }
559 for (auto Op : {ISD::LOAD, ISD::ATOMIC_LOAD, ISD::STORE, ISD::ATOMIC_STORE})
560 setOperationAction(Op, VT: MVT::f16, Action: Subtarget.hasVector() ? Legal : Custom);
561 setOperationAction(Op: ISD::FP_ROUND, VT: MVT::f16, Action: LibCall);
562 setOperationAction(Op: ISD::STRICT_FP_ROUND, VT: MVT::f16, Action: LibCall);
563 setOperationAction(Op: ISD::BITCAST, VT: MVT::i16, Action: Custom);
564
565 for (auto Op : {ISD::FNEG, ISD::FABS, ISD::FCOPYSIGN})
566 setOperationAction(Op, VT: MVT::f16, Action: Legal);
567 }
568
569 for (unsigned I = MVT::FIRST_FP_VALUETYPE;
570 I <= MVT::LAST_FP_VALUETYPE;
571 ++I) {
572 MVT VT = MVT::SimpleValueType(I);
573 if (isTypeLegal(VT) && VT != MVT::f16) {
574 // We can use FI for FRINT.
575 setOperationAction(Op: ISD::FRINT, VT, Action: Legal);
576
577 // We can use the extended form of FI for other rounding operations.
578 if (Subtarget.hasFPExtension()) {
579 setOperationAction(Op: ISD::FNEARBYINT, VT, Action: Legal);
580 setOperationAction(Op: ISD::FFLOOR, VT, Action: Legal);
581 setOperationAction(Op: ISD::FCEIL, VT, Action: Legal);
582 setOperationAction(Op: ISD::FTRUNC, VT, Action: Legal);
583 setOperationAction(Op: ISD::FROUND, VT, Action: Legal);
584 setOperationAction(Op: ISD::FROUNDEVEN, VT, Action: Legal);
585 }
586
587 // No special instructions for these.
588 setOperationAction(Op: ISD::FSIN, VT, Action: Expand);
589 setOperationAction(Op: ISD::FCOS, VT, Action: Expand);
590 setOperationAction(Op: ISD::FSINCOS, VT, Action: Expand);
591 setOperationAction(Op: ISD::FREM, VT, Action: LibCall);
592 setOperationAction(Op: ISD::FPOW, VT, Action: Expand);
593
594 // Special treatment.
595 setOperationAction(Op: ISD::IS_FPCLASS, VT, Action: Custom);
596
597 // Handle constrained floating-point operations.
598 setOperationAction(Op: ISD::STRICT_FADD, VT, Action: Legal);
599 setOperationAction(Op: ISD::STRICT_FSUB, VT, Action: Legal);
600 setOperationAction(Op: ISD::STRICT_FMUL, VT, Action: Legal);
601 setOperationAction(Op: ISD::STRICT_FDIV, VT, Action: Legal);
602 setOperationAction(Op: ISD::STRICT_FMA, VT, Action: Legal);
603 setOperationAction(Op: ISD::STRICT_FSQRT, VT, Action: Legal);
604 setOperationAction(Op: ISD::STRICT_FRINT, VT, Action: Legal);
605 setOperationAction(Op: ISD::STRICT_FP_ROUND, VT, Action: Legal);
606 if (Subtarget.hasFPExtension()) {
607 setOperationAction(Op: ISD::STRICT_FNEARBYINT, VT, Action: Legal);
608 setOperationAction(Op: ISD::STRICT_FFLOOR, VT, Action: Legal);
609 setOperationAction(Op: ISD::STRICT_FCEIL, VT, Action: Legal);
610 setOperationAction(Op: ISD::STRICT_FTRUNC, VT, Action: Legal);
611 setOperationAction(Op: ISD::STRICT_FROUND, VT, Action: Legal);
612 setOperationAction(Op: ISD::STRICT_FROUNDEVEN, VT, Action: Legal);
613 }
614
615 // Extension from f16 needs libcall.
616 setOperationAction(Op: ISD::FP_EXTEND, VT, Action: Custom);
617 setOperationAction(Op: ISD::STRICT_FP_EXTEND, VT, Action: Custom);
618 }
619 }
620
621 // Handle floating-point vector types.
622 if (Subtarget.hasVector()) {
623 // Scalar-to-vector conversion is just a subreg.
624 setOperationAction(Op: ISD::SCALAR_TO_VECTOR, VT: MVT::v8f16, Action: Legal);
625 setOperationAction(Op: ISD::SCALAR_TO_VECTOR, VT: MVT::v4f32, Action: Legal);
626 setOperationAction(Op: ISD::SCALAR_TO_VECTOR, VT: MVT::v2f64, Action: Legal);
627
628 // Some insertions and extractions can be done directly but others
629 // need to go via integers.
630 setOperationAction(Op: ISD::INSERT_VECTOR_ELT, VT: MVT::v8f16, Action: Custom);
631 setOperationAction(Op: ISD::INSERT_VECTOR_ELT, VT: MVT::v4f32, Action: Custom);
632 setOperationAction(Op: ISD::INSERT_VECTOR_ELT, VT: MVT::v2f64, Action: Custom);
633 setOperationAction(Op: ISD::EXTRACT_VECTOR_ELT, VT: MVT::v8f16, Action: Custom);
634 setOperationAction(Op: ISD::EXTRACT_VECTOR_ELT, VT: MVT::v4f32, Action: Custom);
635 setOperationAction(Op: ISD::EXTRACT_VECTOR_ELT, VT: MVT::v2f64, Action: Custom);
636
637 // These operations have direct equivalents.
638 setOperationAction(Op: ISD::FADD, VT: MVT::v2f64, Action: Legal);
639 setOperationAction(Op: ISD::FNEG, VT: MVT::v2f64, Action: Legal);
640 setOperationAction(Op: ISD::FSUB, VT: MVT::v2f64, Action: Legal);
641 setOperationAction(Op: ISD::FMUL, VT: MVT::v2f64, Action: Legal);
642 setOperationAction(Op: ISD::FMA, VT: MVT::v2f64, Action: Legal);
643 setOperationAction(Op: ISD::FDIV, VT: MVT::v2f64, Action: Legal);
644 setOperationAction(Op: ISD::FABS, VT: MVT::v2f64, Action: Legal);
645 setOperationAction(Op: ISD::FSQRT, VT: MVT::v2f64, Action: Legal);
646 setOperationAction(Op: ISD::FRINT, VT: MVT::v2f64, Action: Legal);
647 setOperationAction(Op: ISD::FNEARBYINT, VT: MVT::v2f64, Action: Legal);
648 setOperationAction(Op: ISD::FFLOOR, VT: MVT::v2f64, Action: Legal);
649 setOperationAction(Op: ISD::FCEIL, VT: MVT::v2f64, Action: Legal);
650 setOperationAction(Op: ISD::FTRUNC, VT: MVT::v2f64, Action: Legal);
651 setOperationAction(Op: ISD::FROUND, VT: MVT::v2f64, Action: Legal);
652 setOperationAction(Op: ISD::FROUNDEVEN, VT: MVT::v2f64, Action: Legal);
653
654 // Handle constrained floating-point operations.
655 setOperationAction(Op: ISD::STRICT_FADD, VT: MVT::v2f64, Action: Legal);
656 setOperationAction(Op: ISD::STRICT_FSUB, VT: MVT::v2f64, Action: Legal);
657 setOperationAction(Op: ISD::STRICT_FMUL, VT: MVT::v2f64, Action: Legal);
658 setOperationAction(Op: ISD::STRICT_FMA, VT: MVT::v2f64, Action: Legal);
659 setOperationAction(Op: ISD::STRICT_FDIV, VT: MVT::v2f64, Action: Legal);
660 setOperationAction(Op: ISD::STRICT_FSQRT, VT: MVT::v2f64, Action: Legal);
661 setOperationAction(Op: ISD::STRICT_FRINT, VT: MVT::v2f64, Action: Legal);
662 setOperationAction(Op: ISD::STRICT_FNEARBYINT, VT: MVT::v2f64, Action: Legal);
663 setOperationAction(Op: ISD::STRICT_FFLOOR, VT: MVT::v2f64, Action: Legal);
664 setOperationAction(Op: ISD::STRICT_FCEIL, VT: MVT::v2f64, Action: Legal);
665 setOperationAction(Op: ISD::STRICT_FTRUNC, VT: MVT::v2f64, Action: Legal);
666 setOperationAction(Op: ISD::STRICT_FROUND, VT: MVT::v2f64, Action: Legal);
667 setOperationAction(Op: ISD::STRICT_FROUNDEVEN, VT: MVT::v2f64, Action: Legal);
668
669 setOperationAction(Op: ISD::SETCC, VT: MVT::v2f64, Action: Custom);
670 setOperationAction(Op: ISD::SETCC, VT: MVT::v4f32, Action: Custom);
671 setOperationAction(Op: ISD::STRICT_FSETCC, VT: MVT::v2f64, Action: Custom);
672 setOperationAction(Op: ISD::STRICT_FSETCC, VT: MVT::v4f32, Action: Custom);
673 if (Subtarget.hasVectorEnhancements1()) {
674 setOperationAction(Op: ISD::STRICT_FSETCCS, VT: MVT::v2f64, Action: Custom);
675 setOperationAction(Op: ISD::STRICT_FSETCCS, VT: MVT::v4f32, Action: Custom);
676 }
677 }
678
679 // The vector enhancements facility 1 has instructions for these.
680 if (Subtarget.hasVectorEnhancements1()) {
681 setOperationAction(Op: ISD::FADD, VT: MVT::v4f32, Action: Legal);
682 setOperationAction(Op: ISD::FNEG, VT: MVT::v4f32, Action: Legal);
683 setOperationAction(Op: ISD::FSUB, VT: MVT::v4f32, Action: Legal);
684 setOperationAction(Op: ISD::FMUL, VT: MVT::v4f32, Action: Legal);
685 setOperationAction(Op: ISD::FMA, VT: MVT::v4f32, Action: Legal);
686 setOperationAction(Op: ISD::FDIV, VT: MVT::v4f32, Action: Legal);
687 setOperationAction(Op: ISD::FABS, VT: MVT::v4f32, Action: Legal);
688 setOperationAction(Op: ISD::FSQRT, VT: MVT::v4f32, Action: Legal);
689 setOperationAction(Op: ISD::FRINT, VT: MVT::v4f32, Action: Legal);
690 setOperationAction(Op: ISD::FNEARBYINT, VT: MVT::v4f32, Action: Legal);
691 setOperationAction(Op: ISD::FFLOOR, VT: MVT::v4f32, Action: Legal);
692 setOperationAction(Op: ISD::FCEIL, VT: MVT::v4f32, Action: Legal);
693 setOperationAction(Op: ISD::FTRUNC, VT: MVT::v4f32, Action: Legal);
694 setOperationAction(Op: ISD::FROUND, VT: MVT::v4f32, Action: Legal);
695 setOperationAction(Op: ISD::FROUNDEVEN, VT: MVT::v4f32, Action: Legal);
696
697 for (MVT Type : {MVT::f64, MVT::v2f64, MVT::f32, MVT::v4f32, MVT::f128}) {
698 setOperationAction(Op: ISD::FMAXNUM, VT: Type, Action: Legal);
699 setOperationAction(Op: ISD::FMAXIMUM, VT: Type, Action: Legal);
700 setOperationAction(Op: ISD::FMAXIMUMNUM, VT: Type, Action: Legal);
701 setOperationAction(Op: ISD::PSEUDO_FMAX, VT: Type, Action: Legal);
702 setOperationAction(Op: ISD::FMINNUM, VT: Type, Action: Legal);
703 setOperationAction(Op: ISD::FMINIMUM, VT: Type, Action: Legal);
704 setOperationAction(Op: ISD::FMINIMUMNUM, VT: Type, Action: Legal);
705 setOperationAction(Op: ISD::PSEUDO_FMIN, VT: Type, Action: Legal);
706 }
707
708 // Handle constrained floating-point operations.
709 setOperationAction(Op: ISD::STRICT_FADD, VT: MVT::v4f32, Action: Legal);
710 setOperationAction(Op: ISD::STRICT_FSUB, VT: MVT::v4f32, Action: Legal);
711 setOperationAction(Op: ISD::STRICT_FMUL, VT: MVT::v4f32, Action: Legal);
712 setOperationAction(Op: ISD::STRICT_FMA, VT: MVT::v4f32, Action: Legal);
713 setOperationAction(Op: ISD::STRICT_FDIV, VT: MVT::v4f32, Action: Legal);
714 setOperationAction(Op: ISD::STRICT_FSQRT, VT: MVT::v4f32, Action: Legal);
715 setOperationAction(Op: ISD::STRICT_FRINT, VT: MVT::v4f32, Action: Legal);
716 setOperationAction(Op: ISD::STRICT_FNEARBYINT, VT: MVT::v4f32, Action: Legal);
717 setOperationAction(Op: ISD::STRICT_FFLOOR, VT: MVT::v4f32, Action: Legal);
718 setOperationAction(Op: ISD::STRICT_FCEIL, VT: MVT::v4f32, Action: Legal);
719 setOperationAction(Op: ISD::STRICT_FTRUNC, VT: MVT::v4f32, Action: Legal);
720 setOperationAction(Op: ISD::STRICT_FROUND, VT: MVT::v4f32, Action: Legal);
721 setOperationAction(Op: ISD::STRICT_FROUNDEVEN, VT: MVT::v4f32, Action: Legal);
722 for (auto VT : { MVT::f32, MVT::f64, MVT::f128,
723 MVT::v4f32, MVT::v2f64 }) {
724 setOperationAction(Op: ISD::STRICT_FMAXNUM, VT, Action: Legal);
725 setOperationAction(Op: ISD::STRICT_FMINNUM, VT, Action: Legal);
726 setOperationAction(Op: ISD::STRICT_FMAXIMUM, VT, Action: Legal);
727 setOperationAction(Op: ISD::STRICT_FMINIMUM, VT, Action: Legal);
728 setOperationAction(Op: ISD::STRICT_PSEUDO_FMAX, VT, Action: Legal);
729 setOperationAction(Op: ISD::STRICT_PSEUDO_FMIN, VT, Action: Legal);
730 }
731 }
732
733 // We only have fused f128 multiply-addition on vector registers.
734 if (!Subtarget.hasVectorEnhancements1()) {
735 setOperationAction(Op: ISD::FMA, VT: MVT::f128, Action: Expand);
736 setOperationAction(Op: ISD::STRICT_FMA, VT: MVT::f128, Action: Expand);
737 }
738
739 // We don't have a copysign instruction on vector registers.
740 if (Subtarget.hasVectorEnhancements1())
741 setOperationAction(Op: ISD::FCOPYSIGN, VT: MVT::f128, Action: Expand);
742
743 // Needed so that we don't try to implement f128 constant loads using
744 // a load-and-extend of a f80 constant (in cases where the constant
745 // would fit in an f80).
746 for (MVT VT : MVT::fp_valuetypes())
747 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: VT, MemVT: MVT::f80, Action: Expand);
748
749 // We don't have extending load instruction on vector registers.
750 if (Subtarget.hasVectorEnhancements1()) {
751 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: MVT::f128, MemVT: MVT::f32, Action: Expand);
752 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: MVT::f128, MemVT: MVT::f64, Action: Expand);
753 }
754
755 // Floating-point truncation and stores need to be done separately.
756 setTruncStoreAction(ValVT: MVT::f64, MemVT: MVT::f32, Action: Expand);
757 setTruncStoreAction(ValVT: MVT::f128, MemVT: MVT::f32, Action: Expand);
758 setTruncStoreAction(ValVT: MVT::f128, MemVT: MVT::f64, Action: Expand);
759
760 // We have 64-bit FPR<->GPR moves, but need special handling for
761 // 32-bit forms.
762 if (!Subtarget.hasVector()) {
763 setOperationAction(Op: ISD::BITCAST, VT: MVT::i32, Action: Custom);
764 setOperationAction(Op: ISD::BITCAST, VT: MVT::f32, Action: Custom);
765 }
766
767 // VASTART and VACOPY need to deal with the SystemZ-specific varargs
768 // structure, but VAEND is a no-op.
769 setOperationAction(Op: ISD::VASTART, VT: MVT::Other, Action: Custom);
770 setOperationAction(Op: ISD::VACOPY, VT: MVT::Other, Action: Custom);
771 setOperationAction(Op: ISD::VAEND, VT: MVT::Other, Action: Expand);
772
773 if (Subtarget.isTargetzOS()) {
774 // Handle address space casts between mixed sized pointers.
775 setOperationAction(Op: ISD::ADDRSPACECAST, VT: MVT::i32, Action: Custom);
776 setOperationAction(Op: ISD::ADDRSPACECAST, VT: MVT::i64, Action: Custom);
777 }
778
779 setOperationAction(Op: ISD::GET_ROUNDING, VT: MVT::i32, Action: Custom);
780
781 // Codes for which we want to perform some z-specific combinations.
782 setTargetDAGCombine({ISD::ZERO_EXTEND,
783 ISD::SIGN_EXTEND,
784 ISD::SIGN_EXTEND_INREG,
785 ISD::LOAD,
786 ISD::STORE,
787 ISD::VECTOR_SHUFFLE,
788 ISD::EXTRACT_VECTOR_ELT,
789 ISD::FP_ROUND,
790 ISD::STRICT_FP_ROUND,
791 ISD::FP_EXTEND,
792 ISD::SINT_TO_FP,
793 ISD::UINT_TO_FP,
794 ISD::STRICT_FP_EXTEND,
795 ISD::FCOPYSIGN,
796 ISD::BSWAP,
797 ISD::SETCC,
798 ISD::SRL,
799 ISD::SRA,
800 ISD::MUL,
801 ISD::SDIV,
802 ISD::UDIV,
803 ISD::SREM,
804 ISD::UREM,
805 ISD::INTRINSIC_VOID,
806 ISD::INTRINSIC_W_CHAIN});
807
808 // Handle intrinsics.
809 setOperationAction(Op: ISD::INTRINSIC_W_CHAIN, VT: MVT::Other, Action: Custom);
810 setOperationAction(Op: ISD::INTRINSIC_WO_CHAIN, VT: MVT::Other, Action: Custom);
811
812 // We're not using SJLJ for exception handling, but they're implemented
813 // solely to support use of __builtin_setjmp / __builtin_longjmp.
814 setOperationAction(Op: ISD::EH_SJLJ_SETJMP, VT: MVT::i32, Action: Custom);
815 setOperationAction(Op: ISD::EH_SJLJ_LONGJMP, VT: MVT::Other, Action: Custom);
816
817 // We want to use MVC in preference to even a single load/store pair.
818 MaxStoresPerMemcpy = Subtarget.hasVector() ? 2 : 0;
819 MaxStoresPerMemcpyOptSize = 0;
820
821 // Same with memmove.
822 MaxStoresPerMemmove = Subtarget.hasVector() ? 2 : 0;
823 MaxStoresPerMemmoveOptSize = 0;
824
825 // The main memset sequence is a byte store followed by an MVC.
826 // Two STC or MV..I stores win over that, but the kind of fused stores
827 // generated by target-independent code don't when the byte value is
828 // variable. E.g. "STC <reg>;MHI <reg>,257;STH <reg>" is not better
829 // than "STC;MVC". Handle the choice in target-specific code instead.
830 MaxStoresPerMemset = Subtarget.hasVector() ? 2 : 0;
831 MaxStoresPerMemsetOptSize = 0;
832
833 // Default to having -disable-strictnode-mutation on
834 IsStrictFPEnabled = true;
835}
836
837bool SystemZTargetLowering::useSoftFloat() const {
838 return Subtarget.hasSoftFloat();
839}
840
841unsigned SystemZTargetLowering::getVectorTypeBreakdownForCallingConv(
842 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
843 unsigned &NumIntermediates, MVT &RegisterVT) const {
844 // Pass fp16 vectors in VR(s).
845 if (Subtarget.hasVector() && VT.isVectorOf(EltVT: MVT::f16)) {
846 IntermediateVT = RegisterVT = MVT::v8f16;
847 return NumIntermediates =
848 divideCeil(Numerator: VT.getVectorNumElements(), Denominator: SystemZ::VectorBytes / 2);
849 }
850 return TargetLowering::getVectorTypeBreakdownForCallingConv(
851 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT);
852}
853
854MVT SystemZTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
855 CallingConv::ID CC,
856 EVT VT) const {
857 // 128-bit single-element vector types are passed like other vectors,
858 // not like their element type.
859 if (Subtarget.hasVector() && VT.isVector() && VT.getSizeInBits() == 128 &&
860 VT.getVectorNumElements() == 1)
861 return MVT::v16i8;
862 // Pass fp16 vectors in VR(s).
863 if (Subtarget.hasVector() && VT.isVectorOf(EltVT: MVT::f16))
864 return MVT::v8f16;
865 return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
866}
867
868unsigned SystemZTargetLowering::getNumRegistersForCallingConv(
869 LLVMContext &Context, CallingConv::ID CC, EVT VT) const {
870 // Pass fp16 vectors in VR(s).
871 if (Subtarget.hasVector() && VT.isVectorOf(EltVT: MVT::f16))
872 return divideCeil(Numerator: VT.getVectorNumElements(), Denominator: SystemZ::VectorBytes / 2);
873 return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
874}
875
876EVT SystemZTargetLowering::getSetCCResultType(const DataLayout &DL,
877 LLVMContext &, EVT VT) const {
878 if (!VT.isVector())
879 return MVT::i32;
880 return VT.changeVectorElementTypeToInteger();
881}
882
883bool SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(
884 const MachineFunction &MF, EVT VT) const {
885 if (useSoftFloat())
886 return false;
887
888 VT = VT.getScalarType();
889
890 if (!VT.isSimple())
891 return false;
892
893 switch (VT.getSimpleVT().SimpleTy) {
894 case MVT::f32:
895 case MVT::f64:
896 return true;
897 case MVT::f128:
898 return Subtarget.hasVectorEnhancements1();
899 default:
900 break;
901 }
902
903 return false;
904}
905
906// Return true if the constant can be generated with a vector instruction,
907// such as VGM, VGMB or VREPI.
908bool SystemZVectorConstantInfo::isVectorConstantLegal(
909 const SystemZSubtarget &Subtarget) {
910 const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
911 if (!Subtarget.hasVector() ||
912 (isFP128 && !Subtarget.hasVectorEnhancements1()))
913 return false;
914
915 // Try using VECTOR GENERATE BYTE MASK. This is the architecturally-
916 // preferred way of creating all-zero and all-one vectors so give it
917 // priority over other methods below.
918 unsigned Mask = 0;
919 unsigned I = 0;
920 for (; I < SystemZ::VectorBytes; ++I) {
921 uint64_t Byte = IntBits.lshr(shiftAmt: I * 8).trunc(width: 8).getZExtValue();
922 if (Byte == 0xff)
923 Mask |= 1ULL << I;
924 else if (Byte != 0)
925 break;
926 }
927 if (I == SystemZ::VectorBytes) {
928 Opcode = SystemZISD::BYTE_MASK;
929 OpVals.push_back(Elt: Mask);
930 VecVT = MVT::getVectorVT(VT: MVT::getIntegerVT(BitWidth: 8), NumElements: 16);
931 return true;
932 }
933
934 if (SplatBitSize > 64)
935 return false;
936
937 auto TryValue = [&](uint64_t Value) -> bool {
938 // Try VECTOR REPLICATE IMMEDIATE
939 int64_t SignedValue = SignExtend64(X: Value, B: SplatBitSize);
940 if (isInt<16>(x: SignedValue)) {
941 OpVals.push_back(Elt: ((unsigned) SignedValue));
942 Opcode = SystemZISD::REPLICATE;
943 VecVT = MVT::getVectorVT(VT: MVT::getIntegerVT(BitWidth: SplatBitSize),
944 NumElements: SystemZ::VectorBits / SplatBitSize);
945 return true;
946 }
947 // Try VECTOR GENERATE MASK
948 unsigned Start, End;
949 if (TII->isRxSBGMask(Mask: Value, BitSize: SplatBitSize, Start, End)) {
950 // isRxSBGMask returns the bit numbers for a full 64-bit value, with 0
951 // denoting 1 << 63 and 63 denoting 1. Convert them to bit numbers for
952 // an SplatBitSize value, so that 0 denotes 1 << (SplatBitSize-1).
953 OpVals.push_back(Elt: Start - (64 - SplatBitSize));
954 OpVals.push_back(Elt: End - (64 - SplatBitSize));
955 Opcode = SystemZISD::ROTATE_MASK;
956 VecVT = MVT::getVectorVT(VT: MVT::getIntegerVT(BitWidth: SplatBitSize),
957 NumElements: SystemZ::VectorBits / SplatBitSize);
958 return true;
959 }
960 return false;
961 };
962
963 // First try assuming that any undefined bits above the highest set bit
964 // and below the lowest set bit are 1s. This increases the likelihood of
965 // being able to use a sign-extended element value in VECTOR REPLICATE
966 // IMMEDIATE or a wraparound mask in VECTOR GENERATE MASK.
967 uint64_t SplatBitsZ = SplatBits.getZExtValue();
968 uint64_t SplatUndefZ = SplatUndef.getZExtValue();
969 unsigned LowerBits = llvm::countr_zero(Val: SplatBitsZ);
970 unsigned UpperBits = llvm::countl_zero(Val: SplatBitsZ);
971 uint64_t Lower = SplatUndefZ & maskTrailingOnes<uint64_t>(N: LowerBits);
972 uint64_t Upper = SplatUndefZ & maskLeadingOnes<uint64_t>(N: UpperBits);
973 if (TryValue(SplatBitsZ | Upper | Lower))
974 return true;
975
976 // Now try assuming that any undefined bits between the first and
977 // last defined set bits are set. This increases the chances of
978 // using a non-wraparound mask.
979 uint64_t Middle = SplatUndefZ & ~Upper & ~Lower;
980 return TryValue(SplatBitsZ | Middle);
981}
982
983SystemZVectorConstantInfo::SystemZVectorConstantInfo(APInt IntImm) {
984 if (IntImm.isSingleWord()) {
985 IntBits = APInt(128, IntImm.getZExtValue());
986 IntBits <<= (SystemZ::VectorBits - IntImm.getBitWidth());
987 } else
988 IntBits = IntImm;
989 assert(IntBits.getBitWidth() == 128 && "Unsupported APInt.");
990
991 // Find the smallest splat.
992 SplatBits = IntImm;
993 unsigned Width = SplatBits.getBitWidth();
994 while (Width > 8) {
995 unsigned HalfSize = Width / 2;
996 APInt HighValue = SplatBits.lshr(shiftAmt: HalfSize).trunc(width: HalfSize);
997 APInt LowValue = SplatBits.trunc(width: HalfSize);
998
999 // If the two halves do not match, stop here.
1000 if (HighValue != LowValue || 8 > HalfSize)
1001 break;
1002
1003 SplatBits = HighValue;
1004 Width = HalfSize;
1005 }
1006 SplatUndef = 0;
1007 SplatBitSize = Width;
1008}
1009
1010SystemZVectorConstantInfo::SystemZVectorConstantInfo(BuildVectorSDNode *BVN) {
1011 assert(BVN->isConstant() && "Expected a constant BUILD_VECTOR");
1012 bool HasAnyUndefs;
1013
1014 // Get IntBits by finding the 128 bit splat.
1015 BVN->isConstantSplat(SplatValue&: IntBits, SplatUndef, SplatBitSize, HasAnyUndefs, MinSplatBits: 128,
1016 isBigEndian: true);
1017
1018 // Get SplatBits by finding the 8 bit or greater splat.
1019 BVN->isConstantSplat(SplatValue&: SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs, MinSplatBits: 8,
1020 isBigEndian: true);
1021}
1022
1023bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
1024 bool ForCodeSize) const {
1025 // We can load zero using LZ?R and negative zero using LZ?R;LC?BR.
1026 if (Imm.isZero() || Imm.isNegZero())
1027 return true;
1028
1029 return SystemZVectorConstantInfo(Imm).isVectorConstantLegal(Subtarget);
1030}
1031
1032MachineBasicBlock *
1033SystemZTargetLowering::emitEHSjLjSetJmp(MachineInstr &MI,
1034 MachineBasicBlock *MBB) const {
1035 DebugLoc DL = MI.getDebugLoc();
1036 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1037 const SystemZRegisterInfo *TRI = Subtarget.getRegisterInfo();
1038
1039 MachineFunction *MF = MBB->getParent();
1040 MachineRegisterInfo &MRI = MF->getRegInfo();
1041
1042 const BasicBlock *BB = MBB->getBasicBlock();
1043 MachineFunction::iterator I = ++MBB->getIterator();
1044
1045 Register DstReg = MI.getOperand(i: 0).getReg();
1046 const TargetRegisterClass *RC = MRI.getRegClass(Reg: DstReg);
1047 assert(TRI->isTypeLegalForClass(*RC, MVT::i32) && "Invalid destination!");
1048 (void)TRI;
1049 Register MainDstReg = MRI.createVirtualRegister(RegClass: RC);
1050 Register RestoreDstReg = MRI.createVirtualRegister(RegClass: RC);
1051
1052 MVT PVT = getPointerTy(DL: MF->getDataLayout());
1053 assert((PVT == MVT::i64 || PVT == MVT::i32) && "Invalid Pointer Size!");
1054 // For v = setjmp(buf), we generate.
1055 // Algorithm:
1056 //
1057 // ---------
1058 // | thisMBB |
1059 // ---------
1060 // |
1061 // ------------------------
1062 // | |
1063 // ---------- ---------------
1064 // | mainMBB | | restoreMBB |
1065 // | v = 0 | | v = 1 |
1066 // ---------- ---------------
1067 // | |
1068 // -------------------------
1069 // |
1070 // -----------------------------
1071 // | sinkMBB |
1072 // | phi(v_mainMBB,v_restoreMBB) |
1073 // -----------------------------
1074 // thisMBB:
1075 // buf[FPOffset] = Frame Pointer if hasFP.
1076 // buf[LabelOffset] = restoreMBB <-- takes address of restoreMBB.
1077 // buf[BCOffset] = Backchain value if building with -mbackchain.
1078 // buf[SPOffset] = Stack Pointer.
1079 // buf[LPOffset] = We never write this slot with R13, gcc stores R13 always.
1080 // SjLjSetup restoreMBB
1081 // mainMBB:
1082 // v_main = 0
1083 // sinkMBB:
1084 // v = phi(v_main, v_restore)
1085 // restoreMBB:
1086 // v_restore = 1
1087
1088 MachineBasicBlock *ThisMBB = MBB;
1089 MachineBasicBlock *MainMBB = MF->CreateMachineBasicBlock(BB);
1090 MachineBasicBlock *SinkMBB = MF->CreateMachineBasicBlock(BB);
1091 MachineBasicBlock *RestoreMBB = MF->CreateMachineBasicBlock(BB);
1092
1093 MF->insert(MBBI: I, MBB: MainMBB);
1094 MF->insert(MBBI: I, MBB: SinkMBB);
1095 MF->push_back(MBB: RestoreMBB);
1096 RestoreMBB->setMachineBlockAddressTaken();
1097
1098 MachineInstrBuilder MIB;
1099
1100 // Transfer the remainder of BB and its successor edges to sinkMBB.
1101 SinkMBB->splice(Where: SinkMBB->begin(), Other: MBB,
1102 From: std::next(x: MachineBasicBlock::iterator(MI)), To: MBB->end());
1103 SinkMBB->transferSuccessorsAndUpdatePHIs(FromMBB: MBB);
1104
1105 // thisMBB:
1106 const int64_t FPOffset = 0; // Slot 1.
1107 const int64_t LabelOffset = 1 * PVT.getStoreSize(); // Slot 2.
1108 const int64_t BCOffset = 2 * PVT.getStoreSize(); // Slot 3.
1109 const int64_t SPOffset = 3 * PVT.getStoreSize(); // Slot 4.
1110
1111 // Buf address.
1112 Register BufReg = MI.getOperand(i: 1).getReg();
1113
1114 const TargetRegisterClass *PtrRC = getRegClassFor(VT: PVT);
1115 Register LabelReg = MRI.createVirtualRegister(RegClass: PtrRC);
1116
1117 // Prepare IP for longjmp.
1118 BuildMI(BB&: *ThisMBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: SystemZ::LARL), DestReg: LabelReg)
1119 .addMBB(MBB: RestoreMBB);
1120 // Store IP for return from jmp, slot 2, offset = 1.
1121 BuildMI(BB&: *ThisMBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: SystemZ::STG))
1122 .addReg(RegNo: LabelReg)
1123 .addReg(RegNo: BufReg)
1124 .addImm(Val: LabelOffset)
1125 .addReg(RegNo: 0);
1126
1127 auto *SpecialRegs = Subtarget.getSpecialRegisters();
1128 bool HasFP = Subtarget.getFrameLowering()->hasFP(MF: *MF);
1129 if (HasFP) {
1130 BuildMI(BB&: *ThisMBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: SystemZ::STG))
1131 .addReg(RegNo: SpecialRegs->getFramePointerRegister())
1132 .addReg(RegNo: BufReg)
1133 .addImm(Val: FPOffset)
1134 .addReg(RegNo: 0);
1135 }
1136
1137 // Store SP.
1138 BuildMI(BB&: *ThisMBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: SystemZ::STG))
1139 .addReg(RegNo: SpecialRegs->getStackPointerRegister())
1140 .addReg(RegNo: BufReg)
1141 .addImm(Val: SPOffset)
1142 .addReg(RegNo: 0);
1143
1144 // Slot 3(Offset = 2) Backchain value (if building with -mbackchain).
1145 bool BackChain = MF->getSubtarget<SystemZSubtarget>().hasBackChain();
1146 if (BackChain) {
1147 Register BCReg = MRI.createVirtualRegister(RegClass: PtrRC);
1148 auto *TFL = Subtarget.getFrameLowering<SystemZFrameLowering>();
1149 MIB = BuildMI(BB&: *ThisMBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: SystemZ::LG), DestReg: BCReg)
1150 .addReg(RegNo: SpecialRegs->getStackPointerRegister())
1151 .addImm(Val: TFL->getBackchainOffset(MF&: *MF))
1152 .addReg(RegNo: 0);
1153
1154 BuildMI(BB&: *ThisMBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: SystemZ::STG))
1155 .addReg(RegNo: BCReg)
1156 .addReg(RegNo: BufReg)
1157 .addImm(Val: BCOffset)
1158 .addReg(RegNo: 0);
1159 }
1160
1161 // Setup.
1162 MIB = BuildMI(BB&: *ThisMBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: SystemZ::EH_SjLj_Setup))
1163 .addMBB(MBB: RestoreMBB);
1164
1165 const SystemZRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
1166 MIB.addRegMask(Mask: RegInfo->getNoPreservedMask());
1167
1168 ThisMBB->addSuccessor(Succ: MainMBB);
1169 ThisMBB->addSuccessor(Succ: RestoreMBB);
1170
1171 // mainMBB:
1172 BuildMI(BB: MainMBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::LHI), DestReg: MainDstReg).addImm(Val: 0);
1173 MainMBB->addSuccessor(Succ: SinkMBB);
1174
1175 // sinkMBB:
1176 BuildMI(BB&: *SinkMBB, I: SinkMBB->begin(), MIMD: DL, MCID: TII->get(Opcode: SystemZ::PHI), DestReg: DstReg)
1177 .addReg(RegNo: MainDstReg)
1178 .addMBB(MBB: MainMBB)
1179 .addReg(RegNo: RestoreDstReg)
1180 .addMBB(MBB: RestoreMBB);
1181
1182 // restoreMBB.
1183 BuildMI(BB: RestoreMBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::LHI), DestReg: RestoreDstReg).addImm(Val: 1);
1184 BuildMI(BB: RestoreMBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::J)).addMBB(MBB: SinkMBB);
1185 RestoreMBB->addSuccessor(Succ: SinkMBB);
1186
1187 MI.eraseFromParent();
1188
1189 return SinkMBB;
1190}
1191
1192MachineBasicBlock *
1193SystemZTargetLowering::emitEHSjLjLongJmp(MachineInstr &MI,
1194 MachineBasicBlock *MBB) const {
1195
1196 DebugLoc DL = MI.getDebugLoc();
1197 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1198
1199 MachineFunction *MF = MBB->getParent();
1200 MachineRegisterInfo &MRI = MF->getRegInfo();
1201
1202 MVT PVT = getPointerTy(DL: MF->getDataLayout());
1203 assert((PVT == MVT::i64 || PVT == MVT::i32) && "Invalid Pointer Size!");
1204 Register BufReg = MI.getOperand(i: 0).getReg();
1205 const TargetRegisterClass *RC = MRI.getRegClass(Reg: BufReg);
1206 auto *SpecialRegs = Subtarget.getSpecialRegisters();
1207
1208 Register Tmp = MRI.createVirtualRegister(RegClass: RC);
1209 Register BCReg = MRI.createVirtualRegister(RegClass: RC);
1210
1211 MachineInstrBuilder MIB;
1212
1213 const int64_t FPOffset = 0;
1214 const int64_t LabelOffset = 1 * PVT.getStoreSize();
1215 const int64_t BCOffset = 2 * PVT.getStoreSize();
1216 const int64_t SPOffset = 3 * PVT.getStoreSize();
1217 const int64_t LPOffset = 4 * PVT.getStoreSize();
1218
1219 MIB = BuildMI(BB&: *MBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: SystemZ::LG), DestReg: Tmp)
1220 .addReg(RegNo: BufReg)
1221 .addImm(Val: LabelOffset)
1222 .addReg(RegNo: 0);
1223
1224 MIB = BuildMI(BB&: *MBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: SystemZ::LG),
1225 DestReg: SpecialRegs->getFramePointerRegister())
1226 .addReg(RegNo: BufReg)
1227 .addImm(Val: FPOffset)
1228 .addReg(RegNo: 0);
1229
1230 // We are restoring R13 even though we never stored in setjmp from llvm,
1231 // as gcc always stores R13 in builtin_setjmp. We could have mixed code
1232 // gcc setjmp and llvm longjmp.
1233 MIB = BuildMI(BB&: *MBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: SystemZ::LG), DestReg: SystemZ::R13D)
1234 .addReg(RegNo: BufReg)
1235 .addImm(Val: LPOffset)
1236 .addReg(RegNo: 0);
1237
1238 bool BackChain = MF->getSubtarget<SystemZSubtarget>().hasBackChain();
1239 if (BackChain) {
1240 MIB = BuildMI(BB&: *MBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: SystemZ::LG), DestReg: BCReg)
1241 .addReg(RegNo: BufReg)
1242 .addImm(Val: BCOffset)
1243 .addReg(RegNo: 0);
1244 }
1245
1246 MIB = BuildMI(BB&: *MBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: SystemZ::LG),
1247 DestReg: SpecialRegs->getStackPointerRegister())
1248 .addReg(RegNo: BufReg)
1249 .addImm(Val: SPOffset)
1250 .addReg(RegNo: 0);
1251
1252 if (BackChain) {
1253 auto *TFL = Subtarget.getFrameLowering<SystemZFrameLowering>();
1254 BuildMI(BB&: *MBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: SystemZ::STG))
1255 .addReg(RegNo: BCReg)
1256 .addReg(RegNo: SpecialRegs->getStackPointerRegister())
1257 .addImm(Val: TFL->getBackchainOffset(MF&: *MF))
1258 .addReg(RegNo: 0);
1259 }
1260
1261 MIB = BuildMI(BB&: *MBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: SystemZ::BR)).addReg(RegNo: Tmp);
1262
1263 MI.eraseFromParent();
1264 return MBB;
1265}
1266
1267/// Returns true if stack probing through inline assembly is requested.
1268bool SystemZTargetLowering::hasInlineStackProbe(const MachineFunction &MF) const {
1269 // If the function specifically requests inline stack probes, emit them.
1270 if (MF.getFunction().hasFnAttribute(Kind: "probe-stack"))
1271 return MF.getFunction().getFnAttribute(Kind: "probe-stack").getValueAsString() ==
1272 "inline-asm";
1273 return false;
1274}
1275
1276TargetLowering::AtomicExpansionKind
1277SystemZTargetLowering::shouldCastAtomicLoadInIR(LoadInst *LI) const {
1278 return AtomicExpansionKind::None;
1279}
1280
1281TargetLowering::AtomicExpansionKind
1282SystemZTargetLowering::shouldCastAtomicStoreInIR(StoreInst *SI) const {
1283 return AtomicExpansionKind::None;
1284}
1285
1286TargetLowering::AtomicExpansionKind
1287SystemZTargetLowering::shouldExpandAtomicRMWInIR(
1288 const AtomicRMWInst *RMW) const {
1289 // Don't expand subword operations as they require special treatment.
1290 if (RMW->getType()->isIntegerTy(BitWidth: 8) || RMW->getType()->isIntegerTy(BitWidth: 16))
1291 return AtomicExpansionKind::None;
1292
1293 // Don't expand if there is a target instruction available.
1294 if (Subtarget.hasInterlockedAccess1() &&
1295 (RMW->getType()->isIntegerTy(BitWidth: 32) || RMW->getType()->isIntegerTy(BitWidth: 64)) &&
1296 (RMW->getOperation() == AtomicRMWInst::BinOp::Add ||
1297 RMW->getOperation() == AtomicRMWInst::BinOp::Sub ||
1298 RMW->getOperation() == AtomicRMWInst::BinOp::And ||
1299 RMW->getOperation() == AtomicRMWInst::BinOp::Or ||
1300 RMW->getOperation() == AtomicRMWInst::BinOp::Xor))
1301 return AtomicExpansionKind::None;
1302
1303 return AtomicExpansionKind::CmpXChg;
1304}
1305
1306bool SystemZTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
1307 // We can use CGFI or CLGFI.
1308 return isInt<32>(x: Imm) || isUInt<32>(x: Imm);
1309}
1310
1311bool SystemZTargetLowering::isLegalAddImmediate(int64_t Imm) const {
1312 // We can use ALGFI or SLGFI.
1313 return isUInt<32>(x: Imm) || isUInt<32>(x: -Imm);
1314}
1315
1316bool SystemZTargetLowering::allowsMisalignedMemoryAccesses(
1317 EVT VT, unsigned, Align, MachineMemOperand::Flags, unsigned *Fast) const {
1318 // Unaligned accesses should never be slower than the expanded version.
1319 // We check specifically for aligned accesses in the few cases where
1320 // they are required.
1321 if (Fast)
1322 *Fast = 1;
1323 return true;
1324}
1325
1326bool SystemZTargetLowering::hasAndNot(SDValue Y) const {
1327 EVT VT = Y.getValueType();
1328
1329 // We can use NC(G)RK for types in GPRs ...
1330 if (VT == MVT::i32 || VT == MVT::i64)
1331 return Subtarget.hasMiscellaneousExtensions3();
1332
1333 // ... or VNC for types in VRs.
1334 if (VT.isVector() || VT == MVT::i128)
1335 return Subtarget.hasVector();
1336
1337 return false;
1338}
1339
1340// Information about the addressing mode for a memory access.
1341struct AddressingMode {
1342 // True if a long displacement is supported.
1343 bool LongDisplacement;
1344
1345 // True if use of index register is supported.
1346 bool IndexReg;
1347
1348 AddressingMode(bool LongDispl, bool IdxReg) :
1349 LongDisplacement(LongDispl), IndexReg(IdxReg) {}
1350};
1351
1352// Return the desired addressing mode for a Load which has only one use (in
1353// the same block) which is a Store.
1354static AddressingMode getLoadStoreAddrMode(bool HasVector,
1355 Type *Ty) {
1356 // With vector support a Load->Store combination may be combined to either
1357 // an MVC or vector operations and it seems to work best to allow the
1358 // vector addressing mode.
1359 if (HasVector)
1360 return AddressingMode(false/*LongDispl*/, true/*IdxReg*/);
1361
1362 // Otherwise only the MVC case is special.
1363 bool MVC = Ty->isIntegerTy(BitWidth: 8);
1364 return AddressingMode(!MVC/*LongDispl*/, !MVC/*IdxReg*/);
1365}
1366
1367// Return the addressing mode which seems most desirable given an LLVM
1368// Instruction pointer.
1369static AddressingMode
1370supportedAddressingMode(Instruction *I, bool HasVector) {
1371 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(Val: I)) {
1372 switch (II->getIntrinsicID()) {
1373 default: break;
1374 case Intrinsic::memset:
1375 case Intrinsic::memmove:
1376 case Intrinsic::memcpy:
1377 return AddressingMode(false/*LongDispl*/, false/*IdxReg*/);
1378 }
1379 }
1380
1381 if (isa<LoadInst>(Val: I) && I->hasOneUse()) {
1382 auto *SingleUser = cast<Instruction>(Val: *I->user_begin());
1383 if (SingleUser->getParent() == I->getParent()) {
1384 if (isa<ICmpInst>(Val: SingleUser)) {
1385 if (auto *C = dyn_cast<ConstantInt>(Val: SingleUser->getOperand(i: 1)))
1386 if (C->getBitWidth() <= 64 &&
1387 (isInt<16>(x: C->getSExtValue()) || isUInt<16>(x: C->getZExtValue())))
1388 // Comparison of memory with 16 bit signed / unsigned immediate
1389 return AddressingMode(false/*LongDispl*/, false/*IdxReg*/);
1390 } else if (isa<StoreInst>(Val: SingleUser))
1391 // Load->Store
1392 return getLoadStoreAddrMode(HasVector, Ty: I->getType());
1393 }
1394 } else if (auto *StoreI = dyn_cast<StoreInst>(Val: I)) {
1395 if (auto *LoadI = dyn_cast<LoadInst>(Val: StoreI->getValueOperand()))
1396 if (LoadI->hasOneUse() && LoadI->getParent() == I->getParent())
1397 // Load->Store
1398 return getLoadStoreAddrMode(HasVector, Ty: LoadI->getType());
1399 }
1400
1401 if (HasVector && (isa<LoadInst>(Val: I) || isa<StoreInst>(Val: I))) {
1402
1403 // * Use LDE instead of LE/LEY for z13 to avoid partial register
1404 // dependencies (LDE only supports small offsets).
1405 // * Utilize the vector registers to hold floating point
1406 // values (vector load / store instructions only support small
1407 // offsets).
1408
1409 Type *MemAccessTy = (isa<LoadInst>(Val: I) ? I->getType() :
1410 I->getOperand(i: 0)->getType());
1411 bool IsFPAccess = MemAccessTy->isFloatingPointTy();
1412 bool IsVectorAccess = MemAccessTy->isVectorTy();
1413
1414 // A store of an extracted vector element will be combined into a VSTE type
1415 // instruction.
1416 if (!IsVectorAccess && isa<StoreInst>(Val: I)) {
1417 Value *DataOp = I->getOperand(i: 0);
1418 if (isa<ExtractElementInst>(Val: DataOp))
1419 IsVectorAccess = true;
1420 }
1421
1422 // A load which gets inserted into a vector element will be combined into a
1423 // VLE type instruction.
1424 if (!IsVectorAccess && isa<LoadInst>(Val: I) && I->hasOneUse()) {
1425 User *LoadUser = *I->user_begin();
1426 if (isa<InsertElementInst>(Val: LoadUser))
1427 IsVectorAccess = true;
1428 }
1429
1430 if (IsFPAccess || IsVectorAccess)
1431 return AddressingMode(false/*LongDispl*/, true/*IdxReg*/);
1432 }
1433
1434 return AddressingMode(true/*LongDispl*/, true/*IdxReg*/);
1435}
1436
1437bool SystemZTargetLowering::isLegalAddressingMode(const DataLayout &DL,
1438 const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I) const {
1439 // Punt on globals for now, although they can be used in limited
1440 // RELATIVE LONG cases.
1441 if (AM.BaseGV)
1442 return false;
1443
1444 // Require a 20-bit signed offset.
1445 if (!isInt<20>(x: AM.BaseOffs))
1446 return false;
1447
1448 bool RequireD12 =
1449 Subtarget.hasVector() && (Ty->isVectorTy() || Ty->isIntegerTy(BitWidth: 128));
1450 AddressingMode SupportedAM(!RequireD12, true);
1451 if (I != nullptr)
1452 SupportedAM = supportedAddressingMode(I, HasVector: Subtarget.hasVector());
1453
1454 if (!SupportedAM.LongDisplacement && !isUInt<12>(x: AM.BaseOffs))
1455 return false;
1456
1457 if (!SupportedAM.IndexReg)
1458 // No indexing allowed.
1459 return AM.Scale == 0;
1460 else
1461 // Indexing is OK but no scale factor can be applied.
1462 return AM.Scale == 0 || AM.Scale == 1;
1463}
1464
1465bool SystemZTargetLowering::findOptimalMemOpLowering(
1466 LLVMContext &Context, std::vector<EVT> &MemOps, unsigned Limit,
1467 const MemOp &Op, unsigned DstAS, unsigned SrcAS,
1468 const AttributeList &FuncAttributes, EVT *LargestVT) const {
1469
1470 assert(Limit != ~0U &&
1471 "Expected EmitTargetCodeForMemXXX() to handle AlwaysInline cases.");
1472
1473 if (Op.isZeroMemset())
1474 return false; // Memset zero: Use XC.
1475
1476 const int MVCFastLen = 16;
1477 // Use MVC up to 16 bytes for memcpy. Small memset uses STC/MVI for first
1478 // byte.
1479 if (Op.isMemcpy() && Op.size() <= MVCFastLen)
1480 return false;
1481 if (Op.isMemset() && Op.size() - 1 <= MVCFastLen)
1482 return false;
1483
1484 // Avoid unaligned VL/VST:s.
1485 if ((Op.size() >= 16 && !Op.isAligned(AlignCheck: Align(8))) ||
1486 (Op.size() >= 25 && Op.size() <= 31))
1487 return false;
1488
1489 return TargetLowering::findOptimalMemOpLowering(
1490 Context, MemOps, Limit, Op, DstAS, SrcAS, FuncAttributes, LargestVT);
1491}
1492
1493EVT SystemZTargetLowering::getOptimalMemOpType(
1494 LLVMContext &Context, const MemOp &Op,
1495 const AttributeList &FuncAttributes) const {
1496 return Subtarget.hasVector() ? MVT::v2i64 : MVT::Other;
1497}
1498
1499bool SystemZTargetLowering::isTruncateFree(Type *FromType, Type *ToType) const {
1500 if (!FromType->isIntegerTy() || !ToType->isIntegerTy())
1501 return false;
1502 unsigned FromBits = FromType->getPrimitiveSizeInBits().getFixedValue();
1503 unsigned ToBits = ToType->getPrimitiveSizeInBits().getFixedValue();
1504 return FromBits > ToBits;
1505}
1506
1507bool SystemZTargetLowering::isTruncateFree(EVT FromVT, EVT ToVT) const {
1508 if (!FromVT.isInteger() || !ToVT.isInteger())
1509 return false;
1510 unsigned FromBits = FromVT.getFixedSizeInBits();
1511 unsigned ToBits = ToVT.getFixedSizeInBits();
1512 return FromBits > ToBits;
1513}
1514
1515//===----------------------------------------------------------------------===//
1516// Inline asm support
1517//===----------------------------------------------------------------------===//
1518
1519TargetLowering::ConstraintType
1520SystemZTargetLowering::getConstraintType(StringRef Constraint) const {
1521 if (Constraint.size() == 1) {
1522 switch (Constraint[0]) {
1523 case 'a': // Address register
1524 case 'd': // Data register (equivalent to 'r')
1525 case 'f': // Floating-point register
1526 case 'h': // High-part register
1527 case 'r': // General-purpose register
1528 case 'v': // Vector register
1529 return C_RegisterClass;
1530
1531 case 'Q': // Memory with base and unsigned 12-bit displacement
1532 case 'R': // Likewise, plus an index
1533 case 'S': // Memory with base and signed 20-bit displacement
1534 case 'T': // Likewise, plus an index
1535 case 'm': // Equivalent to 'T'.
1536 return C_Memory;
1537
1538 case 'I': // Unsigned 8-bit constant
1539 case 'J': // Unsigned 12-bit constant
1540 case 'K': // Signed 16-bit constant
1541 case 'L': // Signed 20-bit displacement (on all targets we support)
1542 case 'M': // 0x7fffffff
1543 return C_Immediate;
1544
1545 default:
1546 break;
1547 }
1548 } else if (Constraint.size() == 2 && Constraint[0] == 'Z') {
1549 switch (Constraint[1]) {
1550 case 'Q': // Address with base and unsigned 12-bit displacement
1551 case 'R': // Likewise, plus an index
1552 case 'S': // Address with base and signed 20-bit displacement
1553 case 'T': // Likewise, plus an index
1554 return C_Address;
1555
1556 default:
1557 break;
1558 }
1559 } else if (Constraint.size() == 5 && Constraint.starts_with(Prefix: "{")) {
1560 if (StringRef("{@cc}").compare(RHS: Constraint) == 0)
1561 return C_Other;
1562 }
1563 return TargetLowering::getConstraintType(Constraint);
1564}
1565
1566TargetLowering::ConstraintWeight
1567SystemZTargetLowering::getSingleConstraintMatchWeight(
1568 AsmOperandInfo &Info, const char *Constraint) const {
1569 ConstraintWeight Weight = CW_Invalid;
1570 Value *CallOperandVal = Info.CallOperandVal;
1571 // If we don't have a value, we can't do a match,
1572 // but allow it at the lowest weight.
1573 if (!CallOperandVal)
1574 return CW_Default;
1575 Type *type = CallOperandVal->getType();
1576 // Look at the constraint type.
1577 switch (*Constraint) {
1578 default:
1579 Weight = TargetLowering::getSingleConstraintMatchWeight(info&: Info, constraint: Constraint);
1580 break;
1581
1582 case 'a': // Address register
1583 case 'd': // Data register (equivalent to 'r')
1584 case 'h': // High-part register
1585 case 'r': // General-purpose register
1586 Weight =
1587 CallOperandVal->getType()->isIntegerTy() ? CW_Register : CW_Default;
1588 break;
1589
1590 case 'f': // Floating-point register
1591 if (!useSoftFloat())
1592 Weight = type->isFloatingPointTy() ? CW_Register : CW_Default;
1593 break;
1594
1595 case 'v': // Vector register
1596 if (Subtarget.hasVector())
1597 Weight = (type->isVectorTy() || type->isFloatingPointTy()) ? CW_Register
1598 : CW_Default;
1599 break;
1600
1601 case 'I': // Unsigned 8-bit constant
1602 if (auto *C = dyn_cast<ConstantInt>(Val: CallOperandVal))
1603 if (isUInt<8>(x: C->getZExtValue()))
1604 Weight = CW_Constant;
1605 break;
1606
1607 case 'J': // Unsigned 12-bit constant
1608 if (auto *C = dyn_cast<ConstantInt>(Val: CallOperandVal))
1609 if (isUInt<12>(x: C->getZExtValue()))
1610 Weight = CW_Constant;
1611 break;
1612
1613 case 'K': // Signed 16-bit constant
1614 if (auto *C = dyn_cast<ConstantInt>(Val: CallOperandVal))
1615 if (isInt<16>(x: C->getSExtValue()))
1616 Weight = CW_Constant;
1617 break;
1618
1619 case 'L': // Signed 20-bit displacement (on all targets we support)
1620 if (auto *C = dyn_cast<ConstantInt>(Val: CallOperandVal))
1621 if (isInt<20>(x: C->getSExtValue()))
1622 Weight = CW_Constant;
1623 break;
1624
1625 case 'M': // 0x7fffffff
1626 if (auto *C = dyn_cast<ConstantInt>(Val: CallOperandVal))
1627 if (C->getZExtValue() == 0x7fffffff)
1628 Weight = CW_Constant;
1629 break;
1630 }
1631 return Weight;
1632}
1633
1634// Parse a "{tNNN}" register constraint for which the register type "t"
1635// has already been verified. MC is the class associated with "t" and
1636// Map maps 0-based register numbers to LLVM register numbers.
1637static std::pair<unsigned, const TargetRegisterClass *>
1638parseRegisterNumber(StringRef Constraint, const TargetRegisterClass *RC,
1639 const unsigned *Map, unsigned Size) {
1640 assert(*(Constraint.end()-1) == '}' && "Missing '}'");
1641 if (isdigit(Constraint[2])) {
1642 unsigned Index;
1643 bool Failed =
1644 Constraint.slice(Start: 2, End: Constraint.size() - 1).getAsInteger(Radix: 10, Result&: Index);
1645 if (!Failed && Index < Size && Map[Index])
1646 return std::make_pair(x: Map[Index], y&: RC);
1647 }
1648 return std::make_pair(x: 0U, y: nullptr);
1649}
1650
1651std::pair<unsigned, const TargetRegisterClass *>
1652SystemZTargetLowering::getRegForInlineAsmConstraint(
1653 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
1654 if (Constraint.size() == 1) {
1655 // GCC Constraint Letters
1656 switch (Constraint[0]) {
1657 default: break;
1658 case 'd': // Data register (equivalent to 'r')
1659 case 'r': // General-purpose register
1660 if (VT.getSizeInBits() == 64)
1661 return std::make_pair(x: 0U, y: &SystemZ::GR64BitRegClass);
1662 else if (VT.getSizeInBits() == 128)
1663 return std::make_pair(x: 0U, y: &SystemZ::GR128BitRegClass);
1664 return std::make_pair(x: 0U, y: &SystemZ::GR32BitRegClass);
1665
1666 case 'a': // Address register
1667 if (VT == MVT::i64)
1668 return std::make_pair(x: 0U, y: &SystemZ::ADDR64BitRegClass);
1669 else if (VT == MVT::i128)
1670 return std::make_pair(x: 0U, y: &SystemZ::ADDR128BitRegClass);
1671 return std::make_pair(x: 0U, y: &SystemZ::ADDR32BitRegClass);
1672
1673 case 'h': // High-part register (an LLVM extension)
1674 return std::make_pair(x: 0U, y: &SystemZ::GRH32BitRegClass);
1675
1676 case 'f': // Floating-point register
1677 if (!useSoftFloat()) {
1678 if (VT.getSizeInBits() == 16)
1679 return std::make_pair(x: 0U, y: &SystemZ::FP16BitRegClass);
1680 else if (VT.getSizeInBits() == 64)
1681 return std::make_pair(x: 0U, y: &SystemZ::FP64BitRegClass);
1682 else if (VT.getSizeInBits() == 128)
1683 return std::make_pair(x: 0U, y: &SystemZ::FP128BitRegClass);
1684 return std::make_pair(x: 0U, y: &SystemZ::FP32BitRegClass);
1685 }
1686 break;
1687
1688 case 'v': // Vector register
1689 if (Subtarget.hasVector()) {
1690 if (VT.getSizeInBits() == 16)
1691 return std::make_pair(x: 0U, y: &SystemZ::VR16BitRegClass);
1692 if (VT.getSizeInBits() == 32)
1693 return std::make_pair(x: 0U, y: &SystemZ::VR32BitRegClass);
1694 if (VT.getSizeInBits() == 64)
1695 return std::make_pair(x: 0U, y: &SystemZ::VR64BitRegClass);
1696 return std::make_pair(x: 0U, y: &SystemZ::VR128BitRegClass);
1697 }
1698 break;
1699 }
1700 }
1701 if (Constraint.starts_with(Prefix: "{")) {
1702
1703 // A clobber constraint (e.g. ~{f0}) will have MVT::Other which is illegal
1704 // to check the size on.
1705 auto getVTSizeInBits = [&VT]() {
1706 return VT == MVT::Other ? 0 : VT.getSizeInBits();
1707 };
1708
1709 // We need to override the default register parsing for GPRs and FPRs
1710 // because the interpretation depends on VT. The internal names of
1711 // the registers are also different from the external names
1712 // (F0D and F0S instead of F0, etc.).
1713 if (Constraint[1] == 'r') {
1714 if (getVTSizeInBits() == 32)
1715 return parseRegisterNumber(Constraint, RC: &SystemZ::GR32BitRegClass,
1716 Map: SystemZMC::GR32Regs, Size: 16);
1717 if (getVTSizeInBits() == 128)
1718 return parseRegisterNumber(Constraint, RC: &SystemZ::GR128BitRegClass,
1719 Map: SystemZMC::GR128Regs, Size: 16);
1720 return parseRegisterNumber(Constraint, RC: &SystemZ::GR64BitRegClass,
1721 Map: SystemZMC::GR64Regs, Size: 16);
1722 }
1723 if (Constraint[1] == 'f') {
1724 if (useSoftFloat())
1725 return std::make_pair(
1726 x: 0u, y: static_cast<const TargetRegisterClass *>(nullptr));
1727 if (getVTSizeInBits() == 16)
1728 return parseRegisterNumber(Constraint, RC: &SystemZ::FP16BitRegClass,
1729 Map: SystemZMC::FP16Regs, Size: 16);
1730 if (getVTSizeInBits() == 32)
1731 return parseRegisterNumber(Constraint, RC: &SystemZ::FP32BitRegClass,
1732 Map: SystemZMC::FP32Regs, Size: 16);
1733 if (getVTSizeInBits() == 128)
1734 return parseRegisterNumber(Constraint, RC: &SystemZ::FP128BitRegClass,
1735 Map: SystemZMC::FP128Regs, Size: 16);
1736 return parseRegisterNumber(Constraint, RC: &SystemZ::FP64BitRegClass,
1737 Map: SystemZMC::FP64Regs, Size: 16);
1738 }
1739 if (Constraint[1] == 'v') {
1740 if (!Subtarget.hasVector())
1741 return std::make_pair(
1742 x: 0u, y: static_cast<const TargetRegisterClass *>(nullptr));
1743 if (getVTSizeInBits() == 16)
1744 return parseRegisterNumber(Constraint, RC: &SystemZ::VR16BitRegClass,
1745 Map: SystemZMC::VR16Regs, Size: 32);
1746 if (getVTSizeInBits() == 32)
1747 return parseRegisterNumber(Constraint, RC: &SystemZ::VR32BitRegClass,
1748 Map: SystemZMC::VR32Regs, Size: 32);
1749 if (getVTSizeInBits() == 64)
1750 return parseRegisterNumber(Constraint, RC: &SystemZ::VR64BitRegClass,
1751 Map: SystemZMC::VR64Regs, Size: 32);
1752 return parseRegisterNumber(Constraint, RC: &SystemZ::VR128BitRegClass,
1753 Map: SystemZMC::VR128Regs, Size: 32);
1754 }
1755 if (Constraint[1] == '@') {
1756 if (StringRef("{@cc}").compare(RHS: Constraint) == 0)
1757 return std::make_pair(x: SystemZ::CC, y: &SystemZ::CCRRegClass);
1758 }
1759 }
1760 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
1761}
1762
1763// FIXME? Maybe this could be a TableGen attribute on some registers and
1764// this table could be generated automatically from RegInfo.
1765Register
1766SystemZTargetLowering::getRegisterByName(const char *RegName, LLT VT,
1767 const MachineFunction &MF) const {
1768 Register Reg =
1769 StringSwitch<Register>(RegName)
1770 .Case(S: "r4", Value: Subtarget.isTargetXPLINK64() ? SystemZ::R4D
1771 : SystemZ::NoRegister)
1772 .Case(S: "r15",
1773 Value: Subtarget.isTargetELF() ? SystemZ::R15D : SystemZ::NoRegister)
1774 .Default(Value: Register());
1775
1776 return Reg;
1777}
1778
1779Register SystemZTargetLowering::getExceptionPointerRegister(
1780 ExceptionHandling EH, const Constant *PersonalityFn) const {
1781 return Subtarget.isTargetXPLINK64() ? SystemZ::R1D : SystemZ::R6D;
1782}
1783
1784Register SystemZTargetLowering::getExceptionSelectorRegister(
1785 ExceptionHandling EH, const Constant *PersonalityFn) const {
1786 return Subtarget.isTargetXPLINK64() ? SystemZ::R2D : SystemZ::R7D;
1787}
1788
1789// Convert condition code in CCReg to an i32 value.
1790static SDValue getCCResult(SelectionDAG &DAG, SDValue CCReg) {
1791 SDLoc DL(CCReg);
1792 SDValue IPM = DAG.getNode(Opcode: SystemZISD::IPM, DL, VT: MVT::i32, Operand: CCReg);
1793 return DAG.getNode(Opcode: ISD::SRL, DL, VT: MVT::i32, N1: IPM,
1794 N2: DAG.getConstant(Val: SystemZ::IPM_CC, DL, VT: MVT::i32));
1795}
1796
1797// Lower @cc targets via setcc.
1798SDValue SystemZTargetLowering::LowerAsmOutputForConstraint(
1799 SDValue &Chain, SDValue &Glue, const SDLoc &DL,
1800 const AsmOperandInfo &OpInfo, SelectionDAG &DAG) const {
1801 if (StringRef("{@cc}").compare(RHS: OpInfo.ConstraintCode) != 0)
1802 return SDValue();
1803
1804 // Check that return type is valid.
1805 if (OpInfo.ConstraintVT.isVector() || !OpInfo.ConstraintVT.isInteger() ||
1806 OpInfo.ConstraintVT.getSizeInBits() < 8)
1807 report_fatal_error(reason: "Glue output operand is of invalid type");
1808
1809 if (Glue.getNode()) {
1810 Glue = DAG.getCopyFromReg(Chain, dl: DL, Reg: SystemZ::CC, VT: MVT::i32, Glue);
1811 Chain = Glue.getValue(R: 1);
1812 } else
1813 Glue = DAG.getCopyFromReg(Chain, dl: DL, Reg: SystemZ::CC, VT: MVT::i32);
1814 return getCCResult(DAG, CCReg: Glue);
1815}
1816
1817void SystemZTargetLowering::LowerAsmOperandForConstraint(
1818 SDValue Op, StringRef Constraint, std::vector<SDValue> &Ops,
1819 SelectionDAG &DAG) const {
1820 // Only support length 1 constraints for now.
1821 if (Constraint.size() == 1) {
1822 switch (Constraint[0]) {
1823 case 'I': // Unsigned 8-bit constant
1824 if (auto *C = dyn_cast<ConstantSDNode>(Val&: Op))
1825 if (isUInt<8>(x: C->getZExtValue()))
1826 Ops.push_back(x: DAG.getTargetConstant(Val: C->getZExtValue(), DL: SDLoc(Op),
1827 VT: Op.getValueType()));
1828 return;
1829
1830 case 'J': // Unsigned 12-bit constant
1831 if (auto *C = dyn_cast<ConstantSDNode>(Val&: Op))
1832 if (isUInt<12>(x: C->getZExtValue()))
1833 Ops.push_back(x: DAG.getTargetConstant(Val: C->getZExtValue(), DL: SDLoc(Op),
1834 VT: Op.getValueType()));
1835 return;
1836
1837 case 'K': // Signed 16-bit constant
1838 if (auto *C = dyn_cast<ConstantSDNode>(Val&: Op))
1839 if (isInt<16>(x: C->getSExtValue()))
1840 Ops.push_back(x: DAG.getSignedTargetConstant(
1841 Val: C->getSExtValue(), DL: SDLoc(Op), VT: Op.getValueType()));
1842 return;
1843
1844 case 'L': // Signed 20-bit displacement (on all targets we support)
1845 if (auto *C = dyn_cast<ConstantSDNode>(Val&: Op))
1846 if (isInt<20>(x: C->getSExtValue()))
1847 Ops.push_back(x: DAG.getSignedTargetConstant(
1848 Val: C->getSExtValue(), DL: SDLoc(Op), VT: Op.getValueType()));
1849 return;
1850
1851 case 'M': // 0x7fffffff
1852 if (auto *C = dyn_cast<ConstantSDNode>(Val&: Op))
1853 if (C->getZExtValue() == 0x7fffffff)
1854 Ops.push_back(x: DAG.getTargetConstant(Val: C->getZExtValue(), DL: SDLoc(Op),
1855 VT: Op.getValueType()));
1856 return;
1857 }
1858 }
1859 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
1860}
1861
1862//===----------------------------------------------------------------------===//
1863// Calling conventions
1864//===----------------------------------------------------------------------===//
1865
1866#define GET_CALLING_CONV_IMPL
1867#include "SystemZGenCallingConv.inc"
1868
1869const MCPhysReg *SystemZTargetLowering::getScratchRegisters(
1870 CallingConv::ID) const {
1871 static const MCPhysReg ScratchRegs[] = { SystemZ::R0D, SystemZ::R1D,
1872 SystemZ::R14D, 0 };
1873 return ScratchRegs;
1874}
1875
1876bool SystemZTargetLowering::allowTruncateForTailCall(Type *FromType,
1877 Type *ToType) const {
1878 return isTruncateFree(FromType, ToType);
1879}
1880
1881bool SystemZTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
1882 return CI->isTailCall();
1883}
1884
1885// Value is a value that has been passed to us in the location described by VA
1886// (and so has type VA.getLocVT()). Convert Value to VA.getValVT(), chaining
1887// any loads onto Chain.
1888static SDValue convertLocVTToValVT(SelectionDAG &DAG, const SDLoc &DL,
1889 CCValAssign &VA, SDValue Chain,
1890 SDValue Value) {
1891 // If the argument has been promoted from a smaller type, insert an
1892 // assertion to capture this.
1893 if (VA.getLocInfo() == CCValAssign::SExt)
1894 Value = DAG.getNode(Opcode: ISD::AssertSext, DL, VT: VA.getLocVT(), N1: Value,
1895 N2: DAG.getValueType(VA.getValVT()));
1896 else if (VA.getLocInfo() == CCValAssign::ZExt)
1897 Value = DAG.getNode(Opcode: ISD::AssertZext, DL, VT: VA.getLocVT(), N1: Value,
1898 N2: DAG.getValueType(VA.getValVT()));
1899
1900 if (VA.isExtInLoc())
1901 Value = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: VA.getValVT(), Operand: Value);
1902 else if (VA.getLocInfo() == CCValAssign::BCvt) {
1903 // If this is a short vector argument loaded from the stack,
1904 // extend from i64 to full vector size and then bitcast.
1905 assert(VA.getLocVT() == MVT::i64);
1906 assert(VA.getValVT().isVector());
1907 Value = DAG.getBuildVector(VT: MVT::v2i64, DL, Ops: {Value, DAG.getUNDEF(VT: MVT::i64)});
1908 Value = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: VA.getValVT(), Operand: Value);
1909 } else
1910 assert(VA.getLocInfo() == CCValAssign::Full && "Unsupported getLocInfo");
1911 return Value;
1912}
1913
1914// Value is a value of type VA.getValVT() that we need to copy into
1915// the location described by VA. Return a copy of Value converted to
1916// VA.getValVT(). The caller is responsible for handling indirect values.
1917static SDValue convertValVTToLocVT(SelectionDAG &DAG, const SDLoc &DL,
1918 CCValAssign &VA, SDValue Value) {
1919 switch (VA.getLocInfo()) {
1920 case CCValAssign::SExt:
1921 return DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL, VT: VA.getLocVT(), Operand: Value);
1922 case CCValAssign::ZExt:
1923 return DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: VA.getLocVT(), Operand: Value);
1924 case CCValAssign::AExt:
1925 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: VA.getLocVT(), Operand: Value);
1926 case CCValAssign::BCvt: {
1927 assert(VA.getLocVT() == MVT::i64 || VA.getLocVT() == MVT::i128);
1928 assert(VA.getValVT().isVector() || VA.getValVT() == MVT::f32 ||
1929 VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::f128);
1930 // For an f32 vararg we need to first promote it to an f64 and then
1931 // bitcast it to an i64.
1932 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i64)
1933 Value = DAG.getNode(Opcode: ISD::FP_EXTEND, DL, VT: MVT::f64, Operand: Value);
1934 MVT BitCastToType = VA.getValVT().isVector() && VA.getLocVT() == MVT::i64
1935 ? MVT::v2i64
1936 : VA.getLocVT();
1937 Value = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: BitCastToType, Operand: Value);
1938 // For ELF, this is a short vector argument to be stored to the stack,
1939 // bitcast to v2i64 and then extract first element.
1940 if (BitCastToType == MVT::v2i64)
1941 return DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: VA.getLocVT(), N1: Value,
1942 N2: DAG.getConstant(Val: 0, DL, VT: MVT::i32));
1943 return Value;
1944 }
1945 case CCValAssign::Full:
1946 return Value;
1947 default:
1948 llvm_unreachable("Unhandled getLocInfo()");
1949 }
1950}
1951
1952static SDValue lowerI128ToGR128(SelectionDAG &DAG, SDValue In) {
1953 SDLoc DL(In);
1954 SDValue Lo, Hi;
1955 if (DAG.getTargetLoweringInfo().isTypeLegal(VT: MVT::i128)) {
1956 Lo = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: MVT::i64, Operand: In);
1957 Hi = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: MVT::i64,
1958 Operand: DAG.getNode(Opcode: ISD::SRL, DL, VT: MVT::i128, N1: In,
1959 N2: DAG.getConstant(Val: 64, DL, VT: MVT::i32)));
1960 } else {
1961 std::tie(args&: Lo, args&: Hi) = DAG.SplitScalar(N: In, DL, LoVT: MVT::i64, HiVT: MVT::i64);
1962 }
1963
1964 // FIXME: If v2i64 were a legal type, we could use it instead of
1965 // Untyped here. This might enable improved folding.
1966 SDNode *Pair = DAG.getMachineNode(Opcode: SystemZ::PAIR128, dl: DL,
1967 VT: MVT::Untyped, Op1: Hi, Op2: Lo);
1968 return SDValue(Pair, 0);
1969}
1970
1971static SDValue lowerGR128ToI128(SelectionDAG &DAG, SDValue In) {
1972 SDLoc DL(In);
1973 SDValue Hi = DAG.getTargetExtractSubreg(SRIdx: SystemZ::subreg_h64,
1974 DL, VT: MVT::i64, Operand: In);
1975 SDValue Lo = DAG.getTargetExtractSubreg(SRIdx: SystemZ::subreg_l64,
1976 DL, VT: MVT::i64, Operand: In);
1977
1978 if (DAG.getTargetLoweringInfo().isTypeLegal(VT: MVT::i128)) {
1979 Lo = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: MVT::i128, Operand: Lo);
1980 Hi = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: MVT::i128, Operand: Hi);
1981 Hi = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i128, N1: Hi,
1982 N2: DAG.getConstant(Val: 64, DL, VT: MVT::i32));
1983 return DAG.getNode(Opcode: ISD::OR, DL, VT: MVT::i128, N1: Lo, N2: Hi);
1984 } else {
1985 return DAG.getNode(Opcode: ISD::BUILD_PAIR, DL, VT: MVT::i128, N1: Lo, N2: Hi);
1986 }
1987}
1988
1989bool SystemZTargetLowering::splitValueIntoRegisterParts(
1990 SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
1991 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const {
1992 EVT ValueVT = Val.getValueType();
1993 if (ValueVT.getSizeInBits() == 128 && NumParts == 1 && PartVT == MVT::Untyped) {
1994 // Inline assembly operand.
1995 Parts[0] = lowerI128ToGR128(DAG, In: DAG.getBitcast(VT: MVT::i128, V: Val));
1996 return true;
1997 }
1998
1999 return false;
2000}
2001
2002SDValue SystemZTargetLowering::joinRegisterPartsIntoValue(
2003 SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts,
2004 MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const {
2005 if (ValueVT.getSizeInBits() == 128 && NumParts == 1 && PartVT == MVT::Untyped) {
2006 // Inline assembly operand.
2007 SDValue Res = lowerGR128ToI128(DAG, In: Parts[0]);
2008 return DAG.getBitcast(VT: ValueVT, V: Res);
2009 }
2010
2011 return SDValue();
2012}
2013
2014// The first part of a split stack argument is at index I in Args (and
2015// ArgLocs). Return the type of a part and the number of them by reference.
2016template <class ArgTy>
2017static bool analyzeArgSplit(const SmallVectorImpl<ArgTy> &Args,
2018 SmallVector<CCValAssign, 16> &ArgLocs, unsigned I,
2019 MVT &PartVT, unsigned &NumParts) {
2020 if (!Args[I].Flags.isSplit())
2021 return false;
2022 assert(I < ArgLocs.size() && ArgLocs.size() == Args.size() &&
2023 "ArgLocs havoc.");
2024 PartVT = ArgLocs[I].getValVT();
2025 NumParts = 1;
2026 for (unsigned PartIdx = I + 1;; ++PartIdx) {
2027 assert(PartIdx != ArgLocs.size() && "SplitEnd not found.");
2028 assert(ArgLocs[PartIdx].getValVT() == PartVT && "Unsupported split.");
2029 ++NumParts;
2030 if (Args[PartIdx].Flags.isSplitEnd())
2031 break;
2032 }
2033 return true;
2034}
2035
2036SDValue SystemZTargetLowering::LowerFormalArguments(
2037 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
2038 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
2039 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
2040 MachineFunction &MF = DAG.getMachineFunction();
2041 MachineFrameInfo &MFI = MF.getFrameInfo();
2042 MachineRegisterInfo &MRI = MF.getRegInfo();
2043 SystemZMachineFunctionInfo *FuncInfo =
2044 MF.getInfo<SystemZMachineFunctionInfo>();
2045 auto *TFL = Subtarget.getFrameLowering<SystemZELFFrameLowering>();
2046 EVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
2047
2048 // Assign locations to all of the incoming arguments.
2049 SmallVector<CCValAssign, 16> ArgLocs;
2050 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
2051 CCInfo.AnalyzeFormalArguments(Ins, Fn: CC_SystemZ);
2052 FuncInfo->setSizeOfFnParams(CCInfo.getStackSize());
2053
2054 unsigned NumFixedGPRs = 0;
2055 unsigned NumFixedFPRs = 0;
2056 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
2057 SDValue ArgValue;
2058 CCValAssign &VA = ArgLocs[I];
2059 EVT LocVT = VA.getLocVT();
2060 if (VA.isRegLoc()) {
2061 // Arguments passed in registers
2062 const TargetRegisterClass *RC;
2063 switch (LocVT.getSimpleVT().SimpleTy) {
2064 default:
2065 // Integers smaller than i64 should be promoted to i64.
2066 llvm_unreachable("Unexpected argument type");
2067 case MVT::i32:
2068 NumFixedGPRs += 1;
2069 RC = &SystemZ::GR32BitRegClass;
2070 break;
2071 case MVT::i64:
2072 NumFixedGPRs += 1;
2073 RC = &SystemZ::GR64BitRegClass;
2074 break;
2075 case MVT::f16:
2076 NumFixedFPRs += 1;
2077 RC = &SystemZ::FP16BitRegClass;
2078 break;
2079 case MVT::f32:
2080 NumFixedFPRs += 1;
2081 RC = &SystemZ::FP32BitRegClass;
2082 break;
2083 case MVT::f64:
2084 NumFixedFPRs += 1;
2085 RC = &SystemZ::FP64BitRegClass;
2086 break;
2087 case MVT::f128:
2088 NumFixedFPRs += 2;
2089 RC = &SystemZ::FP128BitRegClass;
2090 break;
2091 case MVT::v16i8:
2092 case MVT::v8i16:
2093 case MVT::v4i32:
2094 case MVT::v2i64:
2095 case MVT::v8f16:
2096 case MVT::v4f32:
2097 case MVT::v2f64:
2098 RC = &SystemZ::VR128BitRegClass;
2099 break;
2100 }
2101
2102 Register VReg = MRI.createVirtualRegister(RegClass: RC);
2103 MRI.addLiveIn(Reg: VA.getLocReg(), vreg: VReg);
2104 ArgValue = DAG.getCopyFromReg(Chain, dl: DL, Reg: VReg, VT: LocVT);
2105 } else {
2106 assert(VA.isMemLoc() && "Argument not register or memory");
2107
2108 // Create the frame index object for this incoming parameter.
2109 // FIXME: Pre-include call frame size in the offset, should not
2110 // need to manually add it here.
2111 int64_t ArgSPOffset = VA.getLocMemOffset();
2112 if (Subtarget.isTargetXPLINK64()) {
2113 auto &XPRegs =
2114 Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>();
2115 ArgSPOffset += XPRegs.getCallFrameSize();
2116 }
2117 int FI =
2118 MFI.CreateFixedObject(Size: LocVT.getSizeInBits() / 8, SPOffset: ArgSPOffset, IsImmutable: true);
2119
2120 // Create the SelectionDAG nodes corresponding to a load
2121 // from this parameter. Unpromoted ints and floats are
2122 // passed as right-justified 8-byte values.
2123 SDValue FIN = DAG.getFrameIndex(FI, VT: PtrVT);
2124 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32 ||
2125 VA.getLocVT() == MVT::f16) {
2126 unsigned SlotOffs = VA.getLocVT() == MVT::f16 ? 6 : 4;
2127 FIN = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: FIN,
2128 N2: DAG.getIntPtrConstant(Val: SlotOffs, DL));
2129 }
2130 ArgValue = DAG.getLoad(VT: LocVT, dl: DL, Chain, Ptr: FIN,
2131 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI));
2132 }
2133
2134 // Convert the value of the argument register into the value that's
2135 // being passed.
2136 if (VA.getLocInfo() == CCValAssign::Indirect) {
2137 InVals.push_back(Elt: DAG.getLoad(VT: VA.getValVT(), dl: DL, Chain, Ptr: ArgValue,
2138 PtrInfo: MachinePointerInfo()));
2139 // If the original argument was split (e.g. i128), we need
2140 // to load all parts of it here (using the same address).
2141 MVT PartVT;
2142 unsigned NumParts;
2143 if (analyzeArgSplit(Args: Ins, ArgLocs, I, PartVT, NumParts)) {
2144 for (unsigned PartIdx = 1; PartIdx < NumParts; ++PartIdx) {
2145 ++I;
2146 CCValAssign &PartVA = ArgLocs[I];
2147 unsigned PartOffset = Ins[I].PartOffset;
2148 SDValue Address = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: ArgValue,
2149 N2: DAG.getIntPtrConstant(Val: PartOffset, DL));
2150 InVals.push_back(Elt: DAG.getLoad(VT: PartVA.getValVT(), dl: DL, Chain, Ptr: Address,
2151 PtrInfo: MachinePointerInfo()));
2152 assert(PartOffset && "Offset should be non-zero.");
2153 }
2154 }
2155 } else if (Subtarget.isTargetXPLINK64() &&
2156 (VA.getLocInfo() == CCValAssign::SExt ||
2157 VA.getLocInfo() == CCValAssign::ZExt) &&
2158 Ins[I].ArgVT.isSimple()) {
2159 // Some prior z/OS compilers do not always perform the extension of
2160 // short integer arguments or pointers. To accommodate those, do not
2161 // rely on that extension by avoiding any AssertSext/AssertZext nodes by
2162 // directly truncating ArgValue to the original argument type.
2163 MVT OrigVT = Ins[I].ArgVT.getSimpleVT();
2164 InVals.push_back(Elt: DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: OrigVT, Operand: ArgValue));
2165 } else
2166 InVals.push_back(Elt: convertLocVTToValVT(DAG, DL, VA, Chain, Value: ArgValue));
2167 }
2168
2169 if (IsVarArg && Subtarget.isTargetXPLINK64()) {
2170 // Save the number of non-varargs registers for later use by va_start, etc.
2171 FuncInfo->setVarArgsFirstGPR(NumFixedGPRs);
2172 FuncInfo->setVarArgsFirstFPR(NumFixedFPRs);
2173
2174 auto *Regs = static_cast<SystemZXPLINK64Registers *>(
2175 Subtarget.getSpecialRegisters());
2176
2177 // Likewise the address (in the form of a frame index) of where the
2178 // first stack vararg would be. The 1-byte size here is arbitrary.
2179 // FIXME: Pre-include call frame size in the offset, should not
2180 // need to manually add it here.
2181 int64_t VarArgOffset = CCInfo.getStackSize() + Regs->getCallFrameSize();
2182 int FI = MFI.CreateFixedObject(Size: 1, SPOffset: VarArgOffset, IsImmutable: true);
2183 FuncInfo->setVarArgsFrameIndex(FI);
2184 }
2185
2186 if (IsVarArg && Subtarget.isTargetELF()) {
2187 // Save the number of non-varargs registers for later use by va_start, etc.
2188 FuncInfo->setVarArgsFirstGPR(NumFixedGPRs);
2189 FuncInfo->setVarArgsFirstFPR(NumFixedFPRs);
2190
2191 // Likewise the address (in the form of a frame index) of where the
2192 // first stack vararg would be. The 1-byte size here is arbitrary.
2193 int64_t VarArgsOffset = CCInfo.getStackSize();
2194 FuncInfo->setVarArgsFrameIndex(
2195 MFI.CreateFixedObject(Size: 1, SPOffset: VarArgsOffset, IsImmutable: true));
2196
2197 // ...and a similar frame index for the caller-allocated save area
2198 // that will be used to store the incoming registers.
2199 int64_t RegSaveOffset =
2200 -SystemZMC::ELFCallFrameSize + TFL->getRegSpillOffset(MF, Reg: SystemZ::R2D) - 16;
2201 unsigned RegSaveIndex = MFI.CreateFixedObject(Size: 1, SPOffset: RegSaveOffset, IsImmutable: true);
2202 FuncInfo->setRegSaveFrameIndex(RegSaveIndex);
2203
2204 // Store the FPR varargs in the reserved frame slots. (We store the
2205 // GPRs as part of the prologue.)
2206 if (NumFixedFPRs < SystemZ::ELFNumArgFPRs && !useSoftFloat()) {
2207 SDValue MemOps[SystemZ::ELFNumArgFPRs];
2208 for (unsigned I = NumFixedFPRs; I < SystemZ::ELFNumArgFPRs; ++I) {
2209 unsigned Offset = TFL->getRegSpillOffset(MF, Reg: SystemZ::ELFArgFPRs[I]);
2210 int FI =
2211 MFI.CreateFixedObject(Size: 8, SPOffset: -SystemZMC::ELFCallFrameSize + Offset, IsImmutable: true);
2212 SDValue FIN = DAG.getFrameIndex(FI, VT: getPointerTy(DL: DAG.getDataLayout()));
2213 Register VReg = MF.addLiveIn(PReg: SystemZ::ELFArgFPRs[I],
2214 RC: &SystemZ::FP64BitRegClass);
2215 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl: DL, Reg: VReg, VT: MVT::f64);
2216 MemOps[I] = DAG.getStore(Chain: ArgValue.getValue(R: 1), dl: DL, Val: ArgValue, Ptr: FIN,
2217 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI));
2218 }
2219 // Join the stores, which are independent of one another.
2220 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other,
2221 Ops: ArrayRef(&MemOps[NumFixedFPRs],
2222 SystemZ::ELFNumArgFPRs - NumFixedFPRs));
2223 }
2224 }
2225
2226 if (Subtarget.isTargetXPLINK64()) {
2227 // Create virual register for handling incoming "ADA" special register (R5)
2228 const TargetRegisterClass *RC = &SystemZ::ADDR64BitRegClass;
2229 Register ADAvReg = MRI.createVirtualRegister(RegClass: RC);
2230 auto *Regs = static_cast<SystemZXPLINK64Registers *>(
2231 Subtarget.getSpecialRegisters());
2232 MRI.addLiveIn(Reg: Regs->getADARegister(), vreg: ADAvReg);
2233 FuncInfo->setADAVirtualRegister(ADAvReg);
2234 }
2235 return Chain;
2236}
2237
2238static bool canUseSiblingCall(const CCState &ArgCCInfo,
2239 SmallVectorImpl<CCValAssign> &ArgLocs,
2240 SmallVectorImpl<ISD::OutputArg> &Outs) {
2241 // Punt if there are any indirect or stack arguments, or if the call
2242 // needs the callee-saved argument register R6, or if the call uses
2243 // the callee-saved register arguments SwiftSelf and SwiftError.
2244 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
2245 CCValAssign &VA = ArgLocs[I];
2246 if (VA.getLocInfo() == CCValAssign::Indirect)
2247 return false;
2248 if (!VA.isRegLoc())
2249 return false;
2250 Register Reg = VA.getLocReg();
2251 if (Reg == SystemZ::R6H || Reg == SystemZ::R6L || Reg == SystemZ::R6D)
2252 return false;
2253 if (Outs[I].Flags.isSwiftSelf() || Outs[I].Flags.isSwiftError())
2254 return false;
2255 }
2256 return true;
2257}
2258
2259static SDValue getADAEntry(SelectionDAG &DAG, SDValue Val, SDLoc DL,
2260 unsigned Offset, bool LoadAdr = false) {
2261 MachineFunction &MF = DAG.getMachineFunction();
2262 SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>();
2263 Register ADAvReg = MFI->getADAVirtualRegister();
2264 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DL: DAG.getDataLayout());
2265
2266 SDValue Reg = DAG.getRegister(Reg: ADAvReg, VT: PtrVT);
2267 SDValue Ofs = DAG.getTargetConstant(Val: Offset, DL, VT: PtrVT);
2268
2269 SDValue Result = DAG.getNode(Opcode: SystemZISD::ADA_ENTRY, DL, VT: PtrVT, N1: Val, N2: Reg, N3: Ofs);
2270 if (!LoadAdr)
2271 Result = DAG.getLoad(
2272 VT: PtrVT, dl: DL, Chain: DAG.getEntryNode(), Ptr: Result, PtrInfo: MachinePointerInfo(), Alignment: Align(8),
2273 MMOFlags: MachineMemOperand::MODereferenceable | MachineMemOperand::MOInvariant);
2274
2275 return Result;
2276}
2277
2278// ADA access using Global value
2279// Note: for functions, address of descriptor is returned
2280static SDValue getADAEntry(SelectionDAG &DAG, const GlobalValue *GV, SDLoc DL,
2281 EVT PtrVT) {
2282 unsigned ADAtype;
2283 bool LoadAddr = false;
2284 const GlobalAlias *GA = dyn_cast<GlobalAlias>(Val: GV);
2285 bool IsFunction =
2286 (isa<Function>(Val: GV)) || (GA && isa<Function>(Val: GA->getAliaseeObject()));
2287 bool IsInternal = (GV->hasInternalLinkage() || GV->hasPrivateLinkage());
2288
2289 if (IsFunction) {
2290 if (IsInternal) {
2291 ADAtype = SystemZII::MO_ADA_DIRECT_FUNC_DESC;
2292 LoadAddr = true;
2293 } else
2294 ADAtype = SystemZII::MO_ADA_INDIRECT_FUNC_DESC;
2295 } else {
2296 ADAtype = SystemZII::MO_ADA_DATA_SYMBOL_ADDR;
2297 }
2298 SDValue Val = DAG.getTargetGlobalAddress(GV, DL, VT: PtrVT, offset: 0, TargetFlags: ADAtype);
2299
2300 return getADAEntry(DAG, Val, DL, Offset: 0, LoadAdr: LoadAddr);
2301}
2302
2303static bool getzOSCalleeAndADA(SelectionDAG &DAG, SDValue &Callee, SDValue &ADA,
2304 SDLoc &DL, SDValue &Chain) {
2305 unsigned ADADelta = 0; // ADA offset in desc.
2306 unsigned EPADelta = 8; // EPA offset in desc.
2307 MachineFunction &MF = DAG.getMachineFunction();
2308 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DL: DAG.getDataLayout());
2309
2310 // XPLink calling convention.
2311 if (auto *G = dyn_cast<GlobalAddressSDNode>(Val&: Callee)) {
2312 bool IsInternal = (G->getGlobal()->hasInternalLinkage() ||
2313 G->getGlobal()->hasPrivateLinkage());
2314 if (IsInternal) {
2315 SystemZMachineFunctionInfo *MFI =
2316 MF.getInfo<SystemZMachineFunctionInfo>();
2317 Register ADAvReg = MFI->getADAVirtualRegister();
2318 ADA = DAG.getCopyFromReg(Chain, dl: DL, Reg: ADAvReg, VT: PtrVT);
2319 Callee = DAG.getTargetGlobalAddress(GV: G->getGlobal(), DL, VT: PtrVT);
2320 Callee = DAG.getNode(Opcode: SystemZISD::PCREL_WRAPPER, DL, VT: PtrVT, Operand: Callee);
2321 return true;
2322 } else {
2323 SDValue GA = DAG.getTargetGlobalAddress(
2324 GV: G->getGlobal(), DL, VT: PtrVT, offset: 0, TargetFlags: SystemZII::MO_ADA_DIRECT_FUNC_DESC);
2325 ADA = getADAEntry(DAG, Val: GA, DL, Offset: ADADelta);
2326 Callee = getADAEntry(DAG, Val: GA, DL, Offset: EPADelta);
2327 }
2328 } else if (auto *E = dyn_cast<ExternalSymbolSDNode>(Val&: Callee)) {
2329 SDValue ES = DAG.getTargetExternalSymbol(
2330 Sym: E->getSymbol(), VT: PtrVT, TargetFlags: SystemZII::MO_ADA_DIRECT_FUNC_DESC);
2331 ADA = getADAEntry(DAG, Val: ES, DL, Offset: ADADelta);
2332 Callee = getADAEntry(DAG, Val: ES, DL, Offset: EPADelta);
2333 } else {
2334 // Function pointer case
2335 ADA = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: Callee,
2336 N2: DAG.getConstant(Val: ADADelta, DL, VT: PtrVT));
2337 ADA = DAG.getLoad(VT: PtrVT, dl: DL, Chain: DAG.getEntryNode(), Ptr: ADA,
2338 PtrInfo: MachinePointerInfo::getGOT(MF&: DAG.getMachineFunction()));
2339 Callee = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: Callee,
2340 N2: DAG.getConstant(Val: EPADelta, DL, VT: PtrVT));
2341 Callee = DAG.getLoad(VT: PtrVT, dl: DL, Chain: DAG.getEntryNode(), Ptr: Callee,
2342 PtrInfo: MachinePointerInfo::getGOT(MF&: DAG.getMachineFunction()));
2343 }
2344 return false;
2345}
2346
2347SDValue
2348SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
2349 SmallVectorImpl<SDValue> &InVals) const {
2350 SelectionDAG &DAG = CLI.DAG;
2351 SDLoc &DL = CLI.DL;
2352 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2353 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2354 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2355 SDValue Chain = CLI.Chain;
2356 SDValue Callee = CLI.Callee;
2357 bool &IsTailCall = CLI.IsTailCall;
2358 CallingConv::ID CallConv = CLI.CallConv;
2359 bool IsVarArg = CLI.IsVarArg;
2360 MachineFunction &MF = DAG.getMachineFunction();
2361 EVT PtrVT = getPointerTy(DL: MF.getDataLayout());
2362 LLVMContext &Ctx = *DAG.getContext();
2363 SystemZCallingConventionRegisters *Regs = Subtarget.getSpecialRegisters();
2364
2365 // FIXME: z/OS support to be added in later.
2366 if (Subtarget.isTargetXPLINK64())
2367 IsTailCall = false;
2368
2369 // Integer args <=32 bits should have an extension attribute.
2370 verifyNarrowIntegerArgs_Call(Outs, F: &MF.getFunction(), Callee);
2371
2372 // Analyze the operands of the call, assigning locations to each operand.
2373 SmallVector<CCValAssign, 16> ArgLocs;
2374 CCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, Ctx);
2375 ArgCCInfo.AnalyzeCallOperands(Outs, Fn: CC_SystemZ);
2376
2377 // We don't support GuaranteedTailCallOpt, only automatically-detected
2378 // sibling calls.
2379 if (IsTailCall && !canUseSiblingCall(ArgCCInfo, ArgLocs, Outs))
2380 IsTailCall = false;
2381
2382 // Get a count of how many bytes are to be pushed on the stack.
2383 unsigned NumBytes = ArgCCInfo.getStackSize();
2384
2385 // Mark the start of the call.
2386 if (!IsTailCall)
2387 Chain = DAG.getCALLSEQ_START(Chain, InSize: NumBytes, OutSize: 0, DL);
2388
2389 // Copy argument values to their designated locations.
2390 SmallVector<std::pair<unsigned, SDValue>, 9> RegsToPass;
2391 SmallVector<SDValue, 8> MemOpChains;
2392 SDValue StackPtr;
2393 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
2394 CCValAssign &VA = ArgLocs[I];
2395 SDValue ArgValue = OutVals[I];
2396
2397 if (VA.getLocInfo() == CCValAssign::Indirect) {
2398 // Store the argument in a stack slot and pass its address.
2399 EVT SlotVT;
2400 MVT PartVT;
2401 unsigned NumParts = 1;
2402 if (analyzeArgSplit(Args: Outs, ArgLocs, I, PartVT, NumParts))
2403 SlotVT = EVT::getIntegerVT(Context&: Ctx, BitWidth: PartVT.getSizeInBits() * NumParts);
2404 else
2405 SlotVT = Outs[I].VT;
2406 SDValue SpillSlot = DAG.CreateStackTemporary(VT: SlotVT);
2407 int FI = cast<FrameIndexSDNode>(Val&: SpillSlot)->getIndex();
2408
2409 MachinePointerInfo StackPtrInfo =
2410 MachinePointerInfo::getFixedStack(MF, FI);
2411 MemOpChains.push_back(
2412 Elt: DAG.getStore(Chain, dl: DL, Val: ArgValue, Ptr: SpillSlot, PtrInfo: StackPtrInfo));
2413 // If the original argument was split (e.g. i128), we need
2414 // to store all parts of it here (and pass just one address).
2415 assert(Outs[I].PartOffset == 0);
2416 for (unsigned PartIdx = 1; PartIdx < NumParts; ++PartIdx) {
2417 ++I;
2418 SDValue PartValue = OutVals[I];
2419 unsigned PartOffset = Outs[I].PartOffset;
2420 SDValue Address = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: SpillSlot,
2421 N2: DAG.getIntPtrConstant(Val: PartOffset, DL));
2422 MemOpChains.push_back(
2423 Elt: DAG.getStore(Chain, dl: DL, Val: PartValue, Ptr: Address,
2424 PtrInfo: StackPtrInfo.getWithOffset(O: PartOffset)));
2425 assert(PartOffset && "Offset should be non-zero.");
2426 assert((PartOffset + PartValue.getValueType().getStoreSize() <=
2427 SlotVT.getStoreSize()) && "Not enough space for argument part!");
2428 }
2429 ArgValue = SpillSlot;
2430 } else
2431 ArgValue = convertValVTToLocVT(DAG, DL, VA, Value: ArgValue);
2432
2433 if (VA.isRegLoc()) {
2434 // In XPLINK64, for the 128-bit vararg case, ArgValue is bitcasted to a
2435 // MVT::i128 type. We decompose the 128-bit type to a pair of its high
2436 // and low values.
2437 if (VA.getLocVT() == MVT::i128)
2438 ArgValue = lowerI128ToGR128(DAG, In: ArgValue);
2439 // Queue up the argument copies and emit them at the end.
2440 RegsToPass.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: ArgValue));
2441 } else {
2442 assert(VA.isMemLoc() && "Argument not register or memory");
2443
2444 // Work out the address of the stack slot. Unpromoted ints and
2445 // floats are passed as right-justified 8-byte values.
2446 if (!StackPtr.getNode())
2447 StackPtr = DAG.getCopyFromReg(Chain, dl: DL,
2448 Reg: Regs->getStackPointerRegister(), VT: PtrVT);
2449 unsigned Offset = Regs->getStackPointerBias() + Regs->getCallFrameSize() +
2450 VA.getLocMemOffset();
2451 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
2452 Offset += 4;
2453 else if (VA.getLocVT() == MVT::f16)
2454 Offset += 6;
2455 SDValue Address = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: StackPtr,
2456 N2: DAG.getIntPtrConstant(Val: Offset, DL));
2457
2458 // Emit the store.
2459 MemOpChains.push_back(
2460 Elt: DAG.getStore(Chain, dl: DL, Val: ArgValue, Ptr: Address, PtrInfo: MachinePointerInfo()));
2461
2462 // Although long doubles or vectors are passed through the stack when
2463 // they are vararg (non-fixed arguments), if a long double or vector
2464 // occupies the third and fourth slot of the argument list GPR3 should
2465 // still shadow the third slot of the argument list.
2466 if (Subtarget.isTargetXPLINK64() && VA.needsCustom()) {
2467 SDValue ShadowArgValue =
2468 DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i64, N1: ArgValue,
2469 N2: DAG.getIntPtrConstant(Val: 1, DL));
2470 RegsToPass.push_back(Elt: std::make_pair(x: SystemZ::R3D, y&: ShadowArgValue));
2471 }
2472 }
2473 }
2474
2475 // Join the stores, which are independent of one another.
2476 if (!MemOpChains.empty())
2477 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, Ops: MemOpChains);
2478
2479 // Accept direct calls by converting symbolic call addresses to the
2480 // associated Target* opcodes. Force %r1 to be used for indirect
2481 // tail calls.
2482 SDValue Glue;
2483
2484 if (Subtarget.isTargetXPLINK64()) {
2485 SDValue ADA;
2486 bool IsBRASL = getzOSCalleeAndADA(DAG, Callee, ADA, DL, Chain);
2487 if (!IsBRASL) {
2488 unsigned CalleeReg = static_cast<SystemZXPLINK64Registers *>(Regs)
2489 ->getAddressOfCalleeRegister();
2490 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: CalleeReg, N: Callee, Glue);
2491 Glue = Chain.getValue(R: 1);
2492 Callee = DAG.getRegister(Reg: CalleeReg, VT: Callee.getValueType());
2493 }
2494 RegsToPass.push_back(Elt: std::make_pair(
2495 x: static_cast<SystemZXPLINK64Registers *>(Regs)->getADARegister(), y&: ADA));
2496 } else {
2497 if (auto *G = dyn_cast<GlobalAddressSDNode>(Val&: Callee)) {
2498 Callee = DAG.getTargetGlobalAddress(GV: G->getGlobal(), DL, VT: PtrVT);
2499 Callee = DAG.getNode(Opcode: SystemZISD::PCREL_WRAPPER, DL, VT: PtrVT, Operand: Callee);
2500 } else if (auto *E = dyn_cast<ExternalSymbolSDNode>(Val&: Callee)) {
2501 Callee = DAG.getTargetExternalSymbol(Sym: E->getSymbol(), VT: PtrVT);
2502 Callee = DAG.getNode(Opcode: SystemZISD::PCREL_WRAPPER, DL, VT: PtrVT, Operand: Callee);
2503 } else if (IsTailCall) {
2504 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: SystemZ::R1D, N: Callee, Glue);
2505 Glue = Chain.getValue(R: 1);
2506 Callee = DAG.getRegister(Reg: SystemZ::R1D, VT: Callee.getValueType());
2507 }
2508 }
2509
2510 // Build a sequence of copy-to-reg nodes, chained and glued together.
2511 for (const auto &[Reg, N] : RegsToPass) {
2512 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg, N, Glue);
2513 Glue = Chain.getValue(R: 1);
2514 }
2515
2516 // The first call operand is the chain and the second is the target address.
2517 SmallVector<SDValue, 8> Ops;
2518 Ops.push_back(Elt: Chain);
2519 Ops.push_back(Elt: Callee);
2520
2521 // Add argument registers to the end of the list so that they are
2522 // known live into the call.
2523 for (const auto &[Reg, N] : RegsToPass)
2524 Ops.push_back(Elt: DAG.getRegister(Reg, VT: N.getValueType()));
2525
2526 // Add a register mask operand representing the call-preserved registers.
2527 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2528 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
2529 assert(Mask && "Missing call preserved mask for calling convention");
2530 Ops.push_back(Elt: DAG.getRegisterMask(RegMask: Mask));
2531
2532 // Glue the call to the argument copies, if any.
2533 if (Glue.getNode())
2534 Ops.push_back(Elt: Glue);
2535
2536 // Emit the call.
2537 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
2538 if (IsTailCall) {
2539 SDValue Ret = DAG.getNode(Opcode: SystemZISD::SIBCALL, DL, VTList: NodeTys, Ops);
2540 DAG.addNoMergeSiteInfo(Node: Ret.getNode(), NoMerge: CLI.NoMerge);
2541 return Ret;
2542 }
2543 Chain = DAG.getNode(Opcode: SystemZISD::CALL, DL, VTList: NodeTys, Ops);
2544 DAG.addNoMergeSiteInfo(Node: Chain.getNode(), NoMerge: CLI.NoMerge);
2545 Glue = Chain.getValue(R: 1);
2546
2547 // Mark the end of the call, which is glued to the call itself.
2548 Chain = DAG.getCALLSEQ_END(Chain, Size1: NumBytes, Size2: 0, Glue, DL);
2549 Glue = Chain.getValue(R: 1);
2550
2551 // Assign locations to each value returned by this call.
2552 SmallVector<CCValAssign, 16> RetLocs;
2553 CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, Ctx);
2554 RetCCInfo.AnalyzeCallResult(Ins, Fn: RetCC_SystemZ);
2555
2556 // Copy all of the result registers out of their specified physreg.
2557 for (CCValAssign &VA : RetLocs) {
2558 // Copy the value out, gluing the copy to the end of the call sequence.
2559 SDValue RetValue = DAG.getCopyFromReg(Chain, dl: DL, Reg: VA.getLocReg(),
2560 VT: VA.getLocVT(), Glue);
2561 Chain = RetValue.getValue(R: 1);
2562 Glue = RetValue.getValue(R: 2);
2563
2564 // Convert the value of the return register into the value that's
2565 // being returned.
2566 InVals.push_back(Elt: convertLocVTToValVT(DAG, DL, VA, Chain, Value: RetValue));
2567 }
2568
2569 return Chain;
2570}
2571
2572// Generate a call taking the given operands as arguments and returning a
2573// result of type RetVT.
2574std::pair<SDValue, SDValue> SystemZTargetLowering::makeExternalCall(
2575 SDValue Chain, SelectionDAG &DAG, const char *CalleeName, EVT RetVT,
2576 ArrayRef<SDValue> Ops, CallingConv::ID CallConv, bool IsSigned, SDLoc DL,
2577 bool DoesNotReturn, bool IsReturnValueUsed) const {
2578 TargetLowering::ArgListTy Args;
2579 Args.reserve(n: Ops.size());
2580
2581 for (SDValue Op : Ops) {
2582 TargetLowering::ArgListEntry Entry(
2583 Op, Op.getValueType().getTypeForEVT(Context&: *DAG.getContext()));
2584 Entry.IsSExt = shouldSignExtendTypeInLibCall(Ty: Entry.Ty, IsSigned);
2585 Entry.IsZExt = !Entry.IsSExt;
2586 Args.push_back(x: Entry);
2587 }
2588
2589 SDValue Callee =
2590 DAG.getExternalSymbol(Sym: CalleeName, VT: getPointerTy(DL: DAG.getDataLayout()));
2591
2592 Type *RetTy = RetVT.getTypeForEVT(Context&: *DAG.getContext());
2593 TargetLowering::CallLoweringInfo CLI(DAG);
2594 bool SignExtend = shouldSignExtendTypeInLibCall(Ty: RetTy, IsSigned);
2595 CLI.setDebugLoc(DL)
2596 .setChain(Chain)
2597 .setCallee(CC: CallConv, ResultType: RetTy, Target: Callee, ArgsList: std::move(Args))
2598 .setNoReturn(DoesNotReturn)
2599 .setDiscardResult(!IsReturnValueUsed)
2600 .setSExtResult(SignExtend)
2601 .setZExtResult(!SignExtend);
2602 return LowerCallTo(CLI);
2603}
2604
2605bool SystemZTargetLowering::CanLowerReturn(
2606 CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
2607 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
2608 const Type *RetTy) const {
2609 // Special case that we cannot easily detect in RetCC_SystemZ since
2610 // i128 may not be a legal type.
2611 for (auto &Out : Outs)
2612 if (Out.ArgVT.isScalarInteger() && Out.ArgVT.getSizeInBits() > 64)
2613 return false;
2614
2615 SmallVector<CCValAssign, 16> RetLocs;
2616 CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, Context);
2617 return RetCCInfo.CheckReturn(Outs, Fn: RetCC_SystemZ);
2618}
2619
2620SDValue
2621SystemZTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2622 bool IsVarArg,
2623 const SmallVectorImpl<ISD::OutputArg> &Outs,
2624 const SmallVectorImpl<SDValue> &OutVals,
2625 const SDLoc &DL, SelectionDAG &DAG) const {
2626 MachineFunction &MF = DAG.getMachineFunction();
2627
2628 // Integer args <=32 bits should have an extension attribute.
2629 verifyNarrowIntegerArgs_Ret(Outs, F: &MF.getFunction());
2630
2631 // Assign locations to each returned value.
2632 SmallVector<CCValAssign, 16> RetLocs;
2633 CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext());
2634 RetCCInfo.AnalyzeReturn(Outs, Fn: RetCC_SystemZ);
2635
2636 // Quick exit for void returns
2637 if (RetLocs.empty())
2638 return DAG.getNode(Opcode: SystemZISD::RET_GLUE, DL, VT: MVT::Other, Operand: Chain);
2639
2640 if (CallConv == CallingConv::GHC)
2641 report_fatal_error(reason: "GHC functions return void only");
2642
2643 // Copy the result values into the output registers.
2644 SDValue Glue;
2645 SmallVector<SDValue, 4> RetOps;
2646 RetOps.push_back(Elt: Chain);
2647 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
2648 CCValAssign &VA = RetLocs[I];
2649 SDValue RetValue = OutVals[I];
2650
2651 // Make the return register live on exit.
2652 assert(VA.isRegLoc() && "Can only return in registers!");
2653
2654 // Promote the value as required.
2655 RetValue = convertValVTToLocVT(DAG, DL, VA, Value: RetValue);
2656
2657 // Chain and glue the copies together.
2658 Register Reg = VA.getLocReg();
2659 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg, N: RetValue, Glue);
2660 Glue = Chain.getValue(R: 1);
2661 RetOps.push_back(Elt: DAG.getRegister(Reg, VT: VA.getLocVT()));
2662 }
2663
2664 // Update chain and glue.
2665 RetOps[0] = Chain;
2666 if (Glue.getNode())
2667 RetOps.push_back(Elt: Glue);
2668
2669 return DAG.getNode(Opcode: SystemZISD::RET_GLUE, DL, VT: MVT::Other, Ops: RetOps);
2670}
2671
2672// Return true if Op is an intrinsic node with chain that returns the CC value
2673// as its only (other) argument. Provide the associated SystemZISD opcode and
2674// the mask of valid CC values if so.
2675static bool isIntrinsicWithCCAndChain(SDValue Op, unsigned &Opcode,
2676 unsigned &CCValid) {
2677 unsigned Id = Op.getConstantOperandVal(i: 1);
2678 switch (Id) {
2679 case Intrinsic::s390_tbegin:
2680 Opcode = SystemZISD::TBEGIN;
2681 CCValid = SystemZ::CCMASK_TBEGIN;
2682 return true;
2683
2684 case Intrinsic::s390_tbegin_nofloat:
2685 Opcode = SystemZISD::TBEGIN_NOFLOAT;
2686 CCValid = SystemZ::CCMASK_TBEGIN;
2687 return true;
2688
2689 case Intrinsic::s390_tend:
2690 Opcode = SystemZISD::TEND;
2691 CCValid = SystemZ::CCMASK_TEND;
2692 return true;
2693
2694 default:
2695 return false;
2696 }
2697}
2698
2699// Return true if Op is an intrinsic node without chain that returns the
2700// CC value as its final argument. Provide the associated SystemZISD
2701// opcode and the mask of valid CC values if so.
2702static bool isIntrinsicWithCC(SDValue Op, unsigned &Opcode, unsigned &CCValid) {
2703 unsigned Id = Op.getConstantOperandVal(i: 0);
2704 switch (Id) {
2705 case Intrinsic::s390_vpkshs:
2706 case Intrinsic::s390_vpksfs:
2707 case Intrinsic::s390_vpksgs:
2708 Opcode = SystemZISD::PACKS_CC;
2709 CCValid = SystemZ::CCMASK_VCMP;
2710 return true;
2711
2712 case Intrinsic::s390_vpklshs:
2713 case Intrinsic::s390_vpklsfs:
2714 case Intrinsic::s390_vpklsgs:
2715 Opcode = SystemZISD::PACKLS_CC;
2716 CCValid = SystemZ::CCMASK_VCMP;
2717 return true;
2718
2719 case Intrinsic::s390_vceqbs:
2720 case Intrinsic::s390_vceqhs:
2721 case Intrinsic::s390_vceqfs:
2722 case Intrinsic::s390_vceqgs:
2723 case Intrinsic::s390_vceqqs:
2724 Opcode = SystemZISD::VICMPES;
2725 CCValid = SystemZ::CCMASK_VCMP;
2726 return true;
2727
2728 case Intrinsic::s390_vchbs:
2729 case Intrinsic::s390_vchhs:
2730 case Intrinsic::s390_vchfs:
2731 case Intrinsic::s390_vchgs:
2732 case Intrinsic::s390_vchqs:
2733 Opcode = SystemZISD::VICMPHS;
2734 CCValid = SystemZ::CCMASK_VCMP;
2735 return true;
2736
2737 case Intrinsic::s390_vchlbs:
2738 case Intrinsic::s390_vchlhs:
2739 case Intrinsic::s390_vchlfs:
2740 case Intrinsic::s390_vchlgs:
2741 case Intrinsic::s390_vchlqs:
2742 Opcode = SystemZISD::VICMPHLS;
2743 CCValid = SystemZ::CCMASK_VCMP;
2744 return true;
2745
2746 case Intrinsic::s390_vtm:
2747 Opcode = SystemZISD::VTM;
2748 CCValid = SystemZ::CCMASK_VCMP;
2749 return true;
2750
2751 case Intrinsic::s390_vfaebs:
2752 case Intrinsic::s390_vfaehs:
2753 case Intrinsic::s390_vfaefs:
2754 Opcode = SystemZISD::VFAE_CC;
2755 CCValid = SystemZ::CCMASK_ANY;
2756 return true;
2757
2758 case Intrinsic::s390_vfaezbs:
2759 case Intrinsic::s390_vfaezhs:
2760 case Intrinsic::s390_vfaezfs:
2761 Opcode = SystemZISD::VFAEZ_CC;
2762 CCValid = SystemZ::CCMASK_ANY;
2763 return true;
2764
2765 case Intrinsic::s390_vfeebs:
2766 case Intrinsic::s390_vfeehs:
2767 case Intrinsic::s390_vfeefs:
2768 Opcode = SystemZISD::VFEE_CC;
2769 CCValid = SystemZ::CCMASK_ANY;
2770 return true;
2771
2772 case Intrinsic::s390_vfeezbs:
2773 case Intrinsic::s390_vfeezhs:
2774 case Intrinsic::s390_vfeezfs:
2775 Opcode = SystemZISD::VFEEZ_CC;
2776 CCValid = SystemZ::CCMASK_ANY;
2777 return true;
2778
2779 case Intrinsic::s390_vfenebs:
2780 case Intrinsic::s390_vfenehs:
2781 case Intrinsic::s390_vfenefs:
2782 Opcode = SystemZISD::VFENE_CC;
2783 CCValid = SystemZ::CCMASK_ANY;
2784 return true;
2785
2786 case Intrinsic::s390_vfenezbs:
2787 case Intrinsic::s390_vfenezhs:
2788 case Intrinsic::s390_vfenezfs:
2789 Opcode = SystemZISD::VFENEZ_CC;
2790 CCValid = SystemZ::CCMASK_ANY;
2791 return true;
2792
2793 case Intrinsic::s390_vistrbs:
2794 case Intrinsic::s390_vistrhs:
2795 case Intrinsic::s390_vistrfs:
2796 Opcode = SystemZISD::VISTR_CC;
2797 CCValid = SystemZ::CCMASK_0 | SystemZ::CCMASK_3;
2798 return true;
2799
2800 case Intrinsic::s390_vstrcbs:
2801 case Intrinsic::s390_vstrchs:
2802 case Intrinsic::s390_vstrcfs:
2803 Opcode = SystemZISD::VSTRC_CC;
2804 CCValid = SystemZ::CCMASK_ANY;
2805 return true;
2806
2807 case Intrinsic::s390_vstrczbs:
2808 case Intrinsic::s390_vstrczhs:
2809 case Intrinsic::s390_vstrczfs:
2810 Opcode = SystemZISD::VSTRCZ_CC;
2811 CCValid = SystemZ::CCMASK_ANY;
2812 return true;
2813
2814 case Intrinsic::s390_vstrsb:
2815 case Intrinsic::s390_vstrsh:
2816 case Intrinsic::s390_vstrsf:
2817 Opcode = SystemZISD::VSTRS_CC;
2818 CCValid = SystemZ::CCMASK_ANY;
2819 return true;
2820
2821 case Intrinsic::s390_vstrszb:
2822 case Intrinsic::s390_vstrszh:
2823 case Intrinsic::s390_vstrszf:
2824 Opcode = SystemZISD::VSTRSZ_CC;
2825 CCValid = SystemZ::CCMASK_ANY;
2826 return true;
2827
2828 case Intrinsic::s390_vfcedbs:
2829 case Intrinsic::s390_vfcesbs:
2830 Opcode = SystemZISD::VFCMPES;
2831 CCValid = SystemZ::CCMASK_VCMP;
2832 return true;
2833
2834 case Intrinsic::s390_vfchdbs:
2835 case Intrinsic::s390_vfchsbs:
2836 Opcode = SystemZISD::VFCMPHS;
2837 CCValid = SystemZ::CCMASK_VCMP;
2838 return true;
2839
2840 case Intrinsic::s390_vfchedbs:
2841 case Intrinsic::s390_vfchesbs:
2842 Opcode = SystemZISD::VFCMPHES;
2843 CCValid = SystemZ::CCMASK_VCMP;
2844 return true;
2845
2846 case Intrinsic::s390_vftcidb:
2847 case Intrinsic::s390_vftcisb:
2848 Opcode = SystemZISD::VFTCI;
2849 CCValid = SystemZ::CCMASK_VCMP;
2850 return true;
2851
2852 case Intrinsic::s390_tdc:
2853 Opcode = SystemZISD::TDC;
2854 CCValid = SystemZ::CCMASK_TDC;
2855 return true;
2856
2857 default:
2858 return false;
2859 }
2860}
2861
2862// Emit an intrinsic with chain and an explicit CC register result.
2863static SDNode *emitIntrinsicWithCCAndChain(SelectionDAG &DAG, SDValue Op,
2864 unsigned Opcode) {
2865 // Copy all operands except the intrinsic ID.
2866 unsigned NumOps = Op.getNumOperands();
2867 SmallVector<SDValue, 6> Ops;
2868 Ops.reserve(N: NumOps - 1);
2869 Ops.push_back(Elt: Op.getOperand(i: 0));
2870 for (unsigned I = 2; I < NumOps; ++I)
2871 Ops.push_back(Elt: Op.getOperand(i: I));
2872
2873 assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
2874 SDVTList RawVTs = DAG.getVTList(VT1: MVT::i32, VT2: MVT::Other);
2875 SDValue Intr = DAG.getNode(Opcode, DL: SDLoc(Op), VTList: RawVTs, Ops);
2876 SDValue OldChain = SDValue(Op.getNode(), 1);
2877 SDValue NewChain = SDValue(Intr.getNode(), 1);
2878 DAG.ReplaceAllUsesOfValueWith(From: OldChain, To: NewChain);
2879 return Intr.getNode();
2880}
2881
2882// Emit an intrinsic with an explicit CC register result.
2883static SDNode *emitIntrinsicWithCC(SelectionDAG &DAG, SDValue Op,
2884 unsigned Opcode) {
2885 // Copy all operands except the intrinsic ID.
2886 SDLoc DL(Op);
2887 unsigned NumOps = Op.getNumOperands();
2888 SmallVector<SDValue, 6> Ops;
2889 Ops.reserve(N: NumOps - 1);
2890 for (unsigned I = 1; I < NumOps; ++I) {
2891 SDValue CurrOper = Op.getOperand(i: I);
2892 if (CurrOper.getValueType() == MVT::f16) {
2893 assert((Op.getConstantOperandVal(0) == Intrinsic::s390_tdc && I == 1) &&
2894 "Unhandled intrinsic with f16 operand.");
2895 CurrOper = DAG.getFPExtendOrRound(Op: CurrOper, DL, VT: MVT::f32);
2896 }
2897 Ops.push_back(Elt: CurrOper);
2898 }
2899
2900 SDValue Intr = DAG.getNode(Opcode, DL, VTList: Op->getVTList(), Ops);
2901 return Intr.getNode();
2902}
2903
2904// CC is a comparison that will be implemented using an integer or
2905// floating-point comparison. Return the condition code mask for
2906// a branch on true. In the integer case, CCMASK_CMP_UO is set for
2907// unsigned comparisons and clear for signed ones. In the floating-point
2908// case, CCMASK_CMP_UO has its normal mask meaning (unordered).
2909static unsigned CCMaskForCondCode(ISD::CondCode CC) {
2910#define CONV(X) \
2911 case ISD::SET##X: return SystemZ::CCMASK_CMP_##X; \
2912 case ISD::SETO##X: return SystemZ::CCMASK_CMP_##X; \
2913 case ISD::SETU##X: return SystemZ::CCMASK_CMP_UO | SystemZ::CCMASK_CMP_##X
2914
2915 switch (CC) {
2916 default:
2917 llvm_unreachable("Invalid integer condition!");
2918
2919 CONV(EQ);
2920 CONV(NE);
2921 CONV(GT);
2922 CONV(GE);
2923 CONV(LT);
2924 CONV(LE);
2925
2926 case ISD::SETO: return SystemZ::CCMASK_CMP_O;
2927 case ISD::SETUO: return SystemZ::CCMASK_CMP_UO;
2928 }
2929#undef CONV
2930}
2931
2932// If C can be converted to a comparison against zero, adjust the operands
2933// as necessary.
2934static void adjustZeroCmp(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) {
2935 if (C.ICmpType == SystemZICMP::UnsignedOnly)
2936 return;
2937
2938 auto *ConstOp1 = dyn_cast<ConstantSDNode>(Val: C.Op1.getNode());
2939 if (!ConstOp1 || ConstOp1->getValueSizeInBits(ResNo: 0) > 64)
2940 return;
2941
2942 int64_t Value = ConstOp1->getSExtValue();
2943 if ((Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_GT) ||
2944 (Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_LE) ||
2945 (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_LT) ||
2946 (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_GE)) {
2947 C.CCMask ^= SystemZ::CCMASK_CMP_EQ;
2948 C.Op1 = DAG.getConstant(Val: 0, DL, VT: C.Op1.getValueType());
2949 }
2950}
2951
2952// If a comparison described by C is suitable for CLI(Y), CHHSI or CLHHSI,
2953// adjust the operands as necessary.
2954static void adjustSubwordCmp(SelectionDAG &DAG, const SDLoc &DL,
2955 Comparison &C) {
2956 // For us to make any changes, it must a comparison between a single-use
2957 // load and a constant.
2958 if (!C.Op0.hasOneUse() ||
2959 C.Op0.getOpcode() != ISD::LOAD ||
2960 C.Op1.getOpcode() != ISD::Constant)
2961 return;
2962
2963 // We must have an 8- or 16-bit load.
2964 auto *Load = cast<LoadSDNode>(Val&: C.Op0);
2965 unsigned NumBits = Load->getMemoryVT().getSizeInBits();
2966 if ((NumBits != 8 && NumBits != 16) ||
2967 NumBits != Load->getMemoryVT().getStoreSizeInBits())
2968 return;
2969
2970 // The load must be an extending one and the constant must be within the
2971 // range of the unextended value.
2972 auto *ConstOp1 = cast<ConstantSDNode>(Val&: C.Op1);
2973 if (!ConstOp1 || ConstOp1->getValueSizeInBits(ResNo: 0) > 64)
2974 return;
2975 uint64_t Value = ConstOp1->getZExtValue();
2976 uint64_t Mask = (1 << NumBits) - 1;
2977 if (Load->getExtensionType() == ISD::SEXTLOAD) {
2978 // Make sure that ConstOp1 is in range of C.Op0.
2979 int64_t SignedValue = ConstOp1->getSExtValue();
2980 if (uint64_t(SignedValue) + (uint64_t(1) << (NumBits - 1)) > Mask)
2981 return;
2982 if (C.ICmpType != SystemZICMP::SignedOnly) {
2983 // Unsigned comparison between two sign-extended values is equivalent
2984 // to unsigned comparison between two zero-extended values.
2985 Value &= Mask;
2986 } else if (NumBits == 8) {
2987 // Try to treat the comparison as unsigned, so that we can use CLI.
2988 // Adjust CCMask and Value as necessary.
2989 if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_LT)
2990 // Test whether the high bit of the byte is set.
2991 Value = 127, C.CCMask = SystemZ::CCMASK_CMP_GT;
2992 else if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_GE)
2993 // Test whether the high bit of the byte is clear.
2994 Value = 128, C.CCMask = SystemZ::CCMASK_CMP_LT;
2995 else
2996 // No instruction exists for this combination.
2997 return;
2998 C.ICmpType = SystemZICMP::UnsignedOnly;
2999 }
3000 } else if (Load->getExtensionType() == ISD::ZEXTLOAD) {
3001 if (Value > Mask)
3002 return;
3003 // If the constant is in range, we can use any comparison.
3004 C.ICmpType = SystemZICMP::Any;
3005 } else
3006 return;
3007
3008 // Make sure that the first operand is an i32 of the right extension type.
3009 ISD::LoadExtType ExtType = (C.ICmpType == SystemZICMP::SignedOnly ?
3010 ISD::SEXTLOAD :
3011 ISD::ZEXTLOAD);
3012 if (C.Op0.getValueType() != MVT::i32 ||
3013 Load->getExtensionType() != ExtType) {
3014 C.Op0 = DAG.getExtLoad(ExtType, dl: SDLoc(Load), VT: MVT::i32, Chain: Load->getChain(),
3015 Ptr: Load->getBasePtr(), PtrInfo: Load->getPointerInfo(),
3016 MemVT: Load->getMemoryVT(), Alignment: Load->getAlign(),
3017 MMOFlags: Load->getMemOperand()->getFlags());
3018 // Update the chain uses.
3019 DAG.ReplaceAllUsesOfValueWith(From: SDValue(Load, 1), To: C.Op0.getValue(R: 1));
3020 }
3021
3022 // Make sure that the second operand is an i32 with the right value.
3023 if (C.Op1.getValueType() != MVT::i32 ||
3024 Value != ConstOp1->getZExtValue())
3025 C.Op1 = DAG.getConstant(Val: (uint32_t)Value, DL, VT: MVT::i32);
3026}
3027
3028// Return true if Op is either an unextended load, or a load suitable
3029// for integer register-memory comparisons of type ICmpType.
3030static bool isNaturalMemoryOperand(SDValue Op, unsigned ICmpType) {
3031 auto *Load = dyn_cast<LoadSDNode>(Val: Op.getNode());
3032 if (Load) {
3033 // There are no instructions to compare a register with a memory byte.
3034 if (Load->getMemoryVT() == MVT::i8)
3035 return false;
3036 // Otherwise decide on extension type.
3037 switch (Load->getExtensionType()) {
3038 case ISD::NON_EXTLOAD:
3039 return true;
3040 case ISD::SEXTLOAD:
3041 return ICmpType != SystemZICMP::UnsignedOnly;
3042 case ISD::ZEXTLOAD:
3043 return ICmpType != SystemZICMP::SignedOnly;
3044 default:
3045 break;
3046 }
3047 }
3048 return false;
3049}
3050
3051// Return true if it is better to swap the operands of C.
3052static bool shouldSwapCmpOperands(const Comparison &C) {
3053 // If one side of the compare is a load of the stackguard reference value,
3054 // then that load should be Op1.
3055 if (C.Op0.isMachineOpcode() &&
3056 (C.Op0.getMachineOpcode() == SystemZ::LOAD_STACK_GUARD))
3057 return true;
3058
3059 // Leave i128 and f128 comparisons alone, since they have no memory forms.
3060 if (C.Op0.getValueType() == MVT::i128)
3061 return false;
3062 if (C.Op0.getValueType() == MVT::f128)
3063 return false;
3064
3065 // Always keep a floating-point constant second, since comparisons with
3066 // zero can use LOAD TEST and comparisons with other constants make a
3067 // natural memory operand.
3068 if (isa<ConstantFPSDNode>(Val: C.Op1))
3069 return false;
3070
3071 // Never swap comparisons with zero since there are many ways to optimize
3072 // those later.
3073 auto *ConstOp1 = dyn_cast<ConstantSDNode>(Val: C.Op1);
3074 if (ConstOp1 && ConstOp1->getZExtValue() == 0)
3075 return false;
3076
3077 // Also keep natural memory operands second if the loaded value is
3078 // only used here. Several comparisons have memory forms.
3079 if (isNaturalMemoryOperand(Op: C.Op1, ICmpType: C.ICmpType) && C.Op1.hasOneUse())
3080 return false;
3081
3082 // Look for cases where Cmp0 is a single-use load and Cmp1 isn't.
3083 // In that case we generally prefer the memory to be second.
3084 if (isNaturalMemoryOperand(Op: C.Op0, ICmpType: C.ICmpType) && C.Op0.hasOneUse()) {
3085 // The only exceptions are when the second operand is a constant and
3086 // we can use things like CHHSI.
3087 if (!ConstOp1)
3088 return true;
3089 // The unsigned memory-immediate instructions can handle 16-bit
3090 // unsigned integers.
3091 if (C.ICmpType != SystemZICMP::SignedOnly &&
3092 isUInt<16>(x: ConstOp1->getZExtValue()))
3093 return false;
3094 // The signed memory-immediate instructions can handle 16-bit
3095 // signed integers.
3096 if (C.ICmpType != SystemZICMP::UnsignedOnly &&
3097 isInt<16>(x: ConstOp1->getSExtValue()))
3098 return false;
3099 return true;
3100 }
3101
3102 // Try to promote the use of CGFR and CLGFR.
3103 unsigned Opcode0 = C.Op0.getOpcode();
3104 if (C.ICmpType != SystemZICMP::UnsignedOnly && Opcode0 == ISD::SIGN_EXTEND)
3105 return true;
3106 if (C.ICmpType != SystemZICMP::SignedOnly && Opcode0 == ISD::ZERO_EXTEND)
3107 return true;
3108 if (C.ICmpType != SystemZICMP::SignedOnly && Opcode0 == ISD::AND &&
3109 C.Op0.getOperand(i: 1).getOpcode() == ISD::Constant &&
3110 C.Op0.getConstantOperandVal(i: 1) == 0xffffffff)
3111 return true;
3112
3113 return false;
3114}
3115
3116// Check whether C tests for equality between X and Y and whether X - Y
3117// or Y - X is also computed. In that case it's better to compare the
3118// result of the subtraction against zero.
3119static void adjustForSubtraction(SelectionDAG &DAG, const SDLoc &DL,
3120 Comparison &C) {
3121 if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
3122 C.CCMask == SystemZ::CCMASK_CMP_NE) {
3123 for (SDNode *N : C.Op0->users()) {
3124 if (N->getOpcode() == ISD::SUB &&
3125 ((N->getOperand(Num: 0) == C.Op0 && N->getOperand(Num: 1) == C.Op1) ||
3126 (N->getOperand(Num: 0) == C.Op1 && N->getOperand(Num: 1) == C.Op0))) {
3127 // Disable the nsw and nuw flags: the backend needs to handle
3128 // overflow as well during comparison elimination.
3129 N->dropFlags(Mask: SDNodeFlags::NoWrap);
3130 C.Op0 = SDValue(N, 0);
3131 C.Op1 = DAG.getConstant(Val: 0, DL, VT: N->getValueType(ResNo: 0));
3132 return;
3133 }
3134 }
3135 }
3136}
3137
3138// Check whether C compares a floating-point value with zero and if that
3139// floating-point value is also negated. In this case we can use the
3140// negation to set CC, so avoiding separate LOAD AND TEST and
3141// LOAD (NEGATIVE/COMPLEMENT) instructions.
3142static void adjustForFNeg(Comparison &C) {
3143 // This optimization is invalid for strict comparisons, since FNEG
3144 // does not raise any exceptions.
3145 if (C.Chain)
3146 return;
3147 auto *C1 = dyn_cast<ConstantFPSDNode>(Val&: C.Op1);
3148 if (C1 && C1->isZero()) {
3149 for (SDNode *N : C.Op0->users()) {
3150 if (N->getOpcode() == ISD::FNEG) {
3151 C.Op0 = SDValue(N, 0);
3152 C.CCMask = SystemZ::reverseCCMask(CCMask: C.CCMask);
3153 return;
3154 }
3155 }
3156 }
3157}
3158
3159// Check whether C compares (shl X, 32) with 0 and whether X is
3160// also sign-extended. In that case it is better to test the result
3161// of the sign extension using LTGFR.
3162//
3163// This case is important because InstCombine transforms a comparison
3164// with (sext (trunc X)) into a comparison with (shl X, 32).
3165static void adjustForLTGFR(Comparison &C) {
3166 // Check for a comparison between (shl X, 32) and 0.
3167 if (C.Op0.getOpcode() == ISD::SHL && C.Op0.getValueType() == MVT::i64 &&
3168 C.Op1.getOpcode() == ISD::Constant && C.Op1->getAsZExtVal() == 0) {
3169 auto *C1 = dyn_cast<ConstantSDNode>(Val: C.Op0.getOperand(i: 1));
3170 if (C1 && C1->getZExtValue() == 32) {
3171 SDValue ShlOp0 = C.Op0.getOperand(i: 0);
3172 // See whether X has any SIGN_EXTEND_INREG uses.
3173 for (SDNode *N : ShlOp0->users()) {
3174 if (N->getOpcode() == ISD::SIGN_EXTEND_INREG &&
3175 cast<VTSDNode>(Val: N->getOperand(Num: 1))->getVT() == MVT::i32) {
3176 C.Op0 = SDValue(N, 0);
3177 return;
3178 }
3179 }
3180 }
3181 }
3182}
3183
3184// If C compares the truncation of an extending load, try to compare
3185// the untruncated value instead. This exposes more opportunities to
3186// reuse CC.
3187static void adjustICmpTruncate(SelectionDAG &DAG, const SDLoc &DL,
3188 Comparison &C) {
3189 if (C.Op0.getOpcode() == ISD::TRUNCATE &&
3190 C.Op0.getOperand(i: 0).getOpcode() == ISD::LOAD &&
3191 C.Op1.getOpcode() == ISD::Constant &&
3192 cast<ConstantSDNode>(Val&: C.Op1)->getValueSizeInBits(ResNo: 0) <= 64 &&
3193 C.Op1->getAsZExtVal() == 0) {
3194 auto *L = cast<LoadSDNode>(Val: C.Op0.getOperand(i: 0));
3195 if (L->getMemoryVT().getStoreSizeInBits().getFixedValue() <=
3196 C.Op0.getValueSizeInBits().getFixedValue()) {
3197 unsigned Type = L->getExtensionType();
3198 if ((Type == ISD::ZEXTLOAD && C.ICmpType != SystemZICMP::SignedOnly) ||
3199 (Type == ISD::SEXTLOAD && C.ICmpType != SystemZICMP::UnsignedOnly)) {
3200 C.Op0 = C.Op0.getOperand(i: 0);
3201 C.Op1 = DAG.getConstant(Val: 0, DL, VT: C.Op0.getValueType());
3202 }
3203 }
3204 }
3205}
3206
3207// Adjust if a given Compare is a check of the stack guard against a stack
3208// guard instance on the stack. Specifically, this checks if:
3209// - The operands are a load of the stack guard, and a load from a stack slot
3210// - The original opcode is ICMP
3211// - ICMPType is compatible with unsigned comparison.
3212static void adjustForStackGuardCompare(SelectionDAG &DAG, const SDLoc &DL,
3213 Comparison &C) {
3214
3215 // Opcode must be ICMP.
3216 if (C.Opcode != SystemZISD::ICMP)
3217 return;
3218 // ICmpType must be Unsigned or Any.
3219 if (C.ICmpType == SystemZICMP::SignedOnly)
3220 return;
3221 // Op0 must be FrameIndex Load.
3222 if (!(ISD::isNormalLoad(N: C.Op0.getNode()) &&
3223 dyn_cast<FrameIndexSDNode>(Val: C.Op0.getOperand(i: 1))))
3224 return;
3225 // Op1 must be LOAD_STACK_GUARD.
3226 if (!C.Op1.isMachineOpcode() ||
3227 C.Op1.getMachineOpcode() != SystemZ::LOAD_STACK_GUARD)
3228 return;
3229
3230 // At this point we are sure that this is a proper CMP_STACKGUARD
3231 // case, update the opcode to reflect this.
3232 C.Opcode = SystemZISD::CMP_STACKGUARD;
3233 C.Op1 = SDValue();
3234}
3235
3236// Return true if shift operation N has an in-range constant shift value.
3237// Store it in ShiftVal if so.
3238static bool isSimpleShift(SDValue N, unsigned &ShiftVal) {
3239 auto *Shift = dyn_cast<ConstantSDNode>(Val: N.getOperand(i: 1));
3240 if (!Shift)
3241 return false;
3242
3243 uint64_t Amount = Shift->getZExtValue();
3244 if (Amount >= N.getValueSizeInBits())
3245 return false;
3246
3247 ShiftVal = Amount;
3248 return true;
3249}
3250
3251// Check whether an AND with Mask is suitable for a TEST UNDER MASK
3252// instruction and whether the CC value is descriptive enough to handle
3253// a comparison of type Opcode between the AND result and CmpVal.
3254// CCMask says which comparison result is being tested and BitSize is
3255// the number of bits in the operands. If TEST UNDER MASK can be used,
3256// return the corresponding CC mask, otherwise return 0.
3257static unsigned getTestUnderMaskCond(unsigned BitSize, unsigned CCMask,
3258 uint64_t Mask, uint64_t CmpVal,
3259 unsigned ICmpType) {
3260 assert(Mask != 0 && "ANDs with zero should have been removed by now");
3261
3262 // Check whether the mask is suitable for TMHH, TMHL, TMLH or TMLL.
3263 if (!SystemZ::isImmLL(Val: Mask) && !SystemZ::isImmLH(Val: Mask) &&
3264 !SystemZ::isImmHL(Val: Mask) && !SystemZ::isImmHH(Val: Mask))
3265 return 0;
3266
3267 // Work out the masks for the lowest and highest bits.
3268 uint64_t High = llvm::bit_floor(Value: Mask);
3269 uint64_t Low = uint64_t(1) << llvm::countr_zero(Val: Mask);
3270
3271 // Signed ordered comparisons are effectively unsigned if the sign
3272 // bit is dropped.
3273 bool EffectivelyUnsigned = (ICmpType != SystemZICMP::SignedOnly);
3274
3275 // Check for equality comparisons with 0, or the equivalent.
3276 if (CmpVal == 0) {
3277 if (CCMask == SystemZ::CCMASK_CMP_EQ)
3278 return SystemZ::CCMASK_TM_ALL_0;
3279 if (CCMask == SystemZ::CCMASK_CMP_NE)
3280 return SystemZ::CCMASK_TM_SOME_1;
3281 }
3282 if (EffectivelyUnsigned && CmpVal > 0 && CmpVal <= Low) {
3283 if (CCMask == SystemZ::CCMASK_CMP_LT)
3284 return SystemZ::CCMASK_TM_ALL_0;
3285 if (CCMask == SystemZ::CCMASK_CMP_GE)
3286 return SystemZ::CCMASK_TM_SOME_1;
3287 }
3288 if (EffectivelyUnsigned && CmpVal < Low) {
3289 if (CCMask == SystemZ::CCMASK_CMP_LE)
3290 return SystemZ::CCMASK_TM_ALL_0;
3291 if (CCMask == SystemZ::CCMASK_CMP_GT)
3292 return SystemZ::CCMASK_TM_SOME_1;
3293 }
3294
3295 // Check for equality comparisons with the mask, or the equivalent.
3296 if (CmpVal == Mask) {
3297 if (CCMask == SystemZ::CCMASK_CMP_EQ)
3298 return SystemZ::CCMASK_TM_ALL_1;
3299 if (CCMask == SystemZ::CCMASK_CMP_NE)
3300 return SystemZ::CCMASK_TM_SOME_0;
3301 }
3302 if (EffectivelyUnsigned && CmpVal >= Mask - Low && CmpVal < Mask) {
3303 if (CCMask == SystemZ::CCMASK_CMP_GT)
3304 return SystemZ::CCMASK_TM_ALL_1;
3305 if (CCMask == SystemZ::CCMASK_CMP_LE)
3306 return SystemZ::CCMASK_TM_SOME_0;
3307 }
3308 if (EffectivelyUnsigned && CmpVal > Mask - Low && CmpVal <= Mask) {
3309 if (CCMask == SystemZ::CCMASK_CMP_GE)
3310 return SystemZ::CCMASK_TM_ALL_1;
3311 if (CCMask == SystemZ::CCMASK_CMP_LT)
3312 return SystemZ::CCMASK_TM_SOME_0;
3313 }
3314
3315 // Check for ordered comparisons with the top bit.
3316 if (EffectivelyUnsigned && CmpVal >= Mask - High && CmpVal < High) {
3317 if (CCMask == SystemZ::CCMASK_CMP_LE)
3318 return SystemZ::CCMASK_TM_MSB_0;
3319 if (CCMask == SystemZ::CCMASK_CMP_GT)
3320 return SystemZ::CCMASK_TM_MSB_1;
3321 }
3322 if (EffectivelyUnsigned && CmpVal > Mask - High && CmpVal <= High) {
3323 if (CCMask == SystemZ::CCMASK_CMP_LT)
3324 return SystemZ::CCMASK_TM_MSB_0;
3325 if (CCMask == SystemZ::CCMASK_CMP_GE)
3326 return SystemZ::CCMASK_TM_MSB_1;
3327 }
3328
3329 // If there are just two bits, we can do equality checks for Low and High
3330 // as well.
3331 if (Mask == Low + High) {
3332 if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == Low)
3333 return SystemZ::CCMASK_TM_MIXED_MSB_0;
3334 if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == Low)
3335 return SystemZ::CCMASK_TM_MIXED_MSB_0 ^ SystemZ::CCMASK_ANY;
3336 if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == High)
3337 return SystemZ::CCMASK_TM_MIXED_MSB_1;
3338 if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == High)
3339 return SystemZ::CCMASK_TM_MIXED_MSB_1 ^ SystemZ::CCMASK_ANY;
3340 }
3341
3342 // Looks like we've exhausted our options.
3343 return 0;
3344}
3345
3346// See whether C can be implemented as a TEST UNDER MASK instruction.
3347// Update the arguments with the TM version if so.
3348static void adjustForTestUnderMask(SelectionDAG &DAG, const SDLoc &DL,
3349 Comparison &C) {
3350 // Use VECTOR TEST UNDER MASK for i128 operations.
3351 if (C.Op0.getValueType() == MVT::i128) {
3352 // We can use VTM for EQ/NE comparisons of x & y against 0.
3353 if (C.Op0.getOpcode() == ISD::AND &&
3354 (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
3355 C.CCMask == SystemZ::CCMASK_CMP_NE)) {
3356 auto *Mask = dyn_cast<ConstantSDNode>(Val&: C.Op1);
3357 if (Mask && Mask->getAPIntValue() == 0) {
3358 C.Opcode = SystemZISD::VTM;
3359 C.Op1 = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: MVT::v16i8, Operand: C.Op0.getOperand(i: 1));
3360 C.Op0 = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: MVT::v16i8, Operand: C.Op0.getOperand(i: 0));
3361 C.CCValid = SystemZ::CCMASK_VCMP;
3362 if (C.CCMask == SystemZ::CCMASK_CMP_EQ)
3363 C.CCMask = SystemZ::CCMASK_VCMP_ALL;
3364 else
3365 C.CCMask = SystemZ::CCMASK_VCMP_ALL ^ C.CCValid;
3366 }
3367 }
3368 return;
3369 }
3370
3371 // Check that we have a comparison with a constant.
3372 auto *ConstOp1 = dyn_cast<ConstantSDNode>(Val&: C.Op1);
3373 if (!ConstOp1)
3374 return;
3375 uint64_t CmpVal = ConstOp1->getZExtValue();
3376
3377 // Check whether the nonconstant input is an AND with a constant mask.
3378 Comparison NewC(C);
3379 uint64_t MaskVal;
3380 ConstantSDNode *Mask = nullptr;
3381 if (C.Op0.getOpcode() == ISD::AND) {
3382 NewC.Op0 = C.Op0.getOperand(i: 0);
3383 NewC.Op1 = C.Op0.getOperand(i: 1);
3384 Mask = dyn_cast<ConstantSDNode>(Val&: NewC.Op1);
3385 if (!Mask)
3386 return;
3387 MaskVal = Mask->getZExtValue();
3388 } else {
3389 // There is no instruction to compare with a 64-bit immediate
3390 // so use TMHH instead if possible. We need an unsigned ordered
3391 // comparison with an i64 immediate.
3392 if (NewC.Op0.getValueType() != MVT::i64 ||
3393 NewC.CCMask == SystemZ::CCMASK_CMP_EQ ||
3394 NewC.CCMask == SystemZ::CCMASK_CMP_NE ||
3395 NewC.ICmpType == SystemZICMP::SignedOnly)
3396 return;
3397 // Convert LE and GT comparisons into LT and GE.
3398 if (NewC.CCMask == SystemZ::CCMASK_CMP_LE ||
3399 NewC.CCMask == SystemZ::CCMASK_CMP_GT) {
3400 if (CmpVal == uint64_t(-1))
3401 return;
3402 CmpVal += 1;
3403 NewC.CCMask ^= SystemZ::CCMASK_CMP_EQ;
3404 }
3405 // If the low N bits of Op1 are zero than the low N bits of Op0 can
3406 // be masked off without changing the result.
3407 MaskVal = -(CmpVal & -CmpVal);
3408 NewC.ICmpType = SystemZICMP::UnsignedOnly;
3409 }
3410 if (!MaskVal)
3411 return;
3412
3413 // Check whether the combination of mask, comparison value and comparison
3414 // type are suitable.
3415 unsigned BitSize = NewC.Op0.getValueSizeInBits();
3416 unsigned NewCCMask, ShiftVal;
3417 if (NewC.ICmpType != SystemZICMP::SignedOnly &&
3418 NewC.Op0.getOpcode() == ISD::SHL &&
3419 isSimpleShift(N: NewC.Op0, ShiftVal) &&
3420 (MaskVal >> ShiftVal != 0) &&
3421 ((CmpVal >> ShiftVal) << ShiftVal) == CmpVal &&
3422 (NewCCMask = getTestUnderMaskCond(BitSize, CCMask: NewC.CCMask,
3423 Mask: MaskVal >> ShiftVal,
3424 CmpVal: CmpVal >> ShiftVal,
3425 ICmpType: SystemZICMP::Any))) {
3426 NewC.Op0 = NewC.Op0.getOperand(i: 0);
3427 MaskVal >>= ShiftVal;
3428 } else if (NewC.ICmpType != SystemZICMP::SignedOnly &&
3429 NewC.Op0.getOpcode() == ISD::SRL &&
3430 isSimpleShift(N: NewC.Op0, ShiftVal) &&
3431 (MaskVal << ShiftVal != 0) &&
3432 ((CmpVal << ShiftVal) >> ShiftVal) == CmpVal &&
3433 (NewCCMask = getTestUnderMaskCond(BitSize, CCMask: NewC.CCMask,
3434 Mask: MaskVal << ShiftVal,
3435 CmpVal: CmpVal << ShiftVal,
3436 ICmpType: SystemZICMP::UnsignedOnly))) {
3437 NewC.Op0 = NewC.Op0.getOperand(i: 0);
3438 MaskVal <<= ShiftVal;
3439 } else {
3440 NewCCMask = getTestUnderMaskCond(BitSize, CCMask: NewC.CCMask, Mask: MaskVal, CmpVal,
3441 ICmpType: NewC.ICmpType);
3442 if (!NewCCMask)
3443 return;
3444 }
3445
3446 // Go ahead and make the change.
3447 C.Opcode = SystemZISD::TM;
3448 C.Op0 = NewC.Op0;
3449 if (Mask && Mask->getZExtValue() == MaskVal)
3450 C.Op1 = SDValue(Mask, 0);
3451 else
3452 C.Op1 = DAG.getConstant(Val: MaskVal, DL, VT: C.Op0.getValueType());
3453 C.CCValid = SystemZ::CCMASK_TM;
3454 C.CCMask = NewCCMask;
3455}
3456
3457// Implement i128 comparison in vector registers.
3458static void adjustICmp128(SelectionDAG &DAG, const SDLoc &DL,
3459 Comparison &C) {
3460 if (C.Opcode != SystemZISD::ICMP)
3461 return;
3462 if (C.Op0.getValueType() != MVT::i128)
3463 return;
3464
3465 // Recognize vector comparison reductions.
3466 if ((C.CCMask == SystemZ::CCMASK_CMP_EQ ||
3467 C.CCMask == SystemZ::CCMASK_CMP_NE) &&
3468 (isNullConstant(V: C.Op1) || isAllOnesConstant(V: C.Op1))) {
3469 bool CmpEq = C.CCMask == SystemZ::CCMASK_CMP_EQ;
3470 bool CmpNull = isNullConstant(V: C.Op1);
3471 SDValue Src = peekThroughBitcasts(V: C.Op0);
3472 if (Src.hasOneUse() && isBitwiseNot(V: Src)) {
3473 Src = Src.getOperand(i: 0);
3474 CmpNull = !CmpNull;
3475 }
3476 unsigned Opcode = 0;
3477 if (Src.hasOneUse()) {
3478 switch (Src.getOpcode()) {
3479 case SystemZISD::VICMPE: Opcode = SystemZISD::VICMPES; break;
3480 case SystemZISD::VICMPH: Opcode = SystemZISD::VICMPHS; break;
3481 case SystemZISD::VICMPHL: Opcode = SystemZISD::VICMPHLS; break;
3482 case SystemZISD::VFCMPE: Opcode = SystemZISD::VFCMPES; break;
3483 case SystemZISD::VFCMPH: Opcode = SystemZISD::VFCMPHS; break;
3484 case SystemZISD::VFCMPHE: Opcode = SystemZISD::VFCMPHES; break;
3485 default: break;
3486 }
3487 }
3488 if (Opcode) {
3489 C.Opcode = Opcode;
3490 C.Op0 = Src->getOperand(Num: 0);
3491 C.Op1 = Src->getOperand(Num: 1);
3492 C.CCValid = SystemZ::CCMASK_VCMP;
3493 C.CCMask = CmpNull ? SystemZ::CCMASK_VCMP_NONE : SystemZ::CCMASK_VCMP_ALL;
3494 if (!CmpEq)
3495 C.CCMask ^= C.CCValid;
3496 return;
3497 }
3498 }
3499
3500 // Everything below here is not useful if we have native i128 compares.
3501 if (DAG.getSubtarget<SystemZSubtarget>().hasVectorEnhancements3())
3502 return;
3503
3504 // (In-)Equality comparisons can be implemented via VCEQGS.
3505 if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
3506 C.CCMask == SystemZ::CCMASK_CMP_NE) {
3507 C.Opcode = SystemZISD::VICMPES;
3508 C.Op0 = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: MVT::v2i64, Operand: C.Op0);
3509 C.Op1 = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: MVT::v2i64, Operand: C.Op1);
3510 C.CCValid = SystemZ::CCMASK_VCMP;
3511 if (C.CCMask == SystemZ::CCMASK_CMP_EQ)
3512 C.CCMask = SystemZ::CCMASK_VCMP_ALL;
3513 else
3514 C.CCMask = SystemZ::CCMASK_VCMP_ALL ^ C.CCValid;
3515 return;
3516 }
3517
3518 // Normalize other comparisons to GT.
3519 bool Swap = false, Invert = false;
3520 switch (C.CCMask) {
3521 case SystemZ::CCMASK_CMP_GT: break;
3522 case SystemZ::CCMASK_CMP_LT: Swap = true; break;
3523 case SystemZ::CCMASK_CMP_LE: Invert = true; break;
3524 case SystemZ::CCMASK_CMP_GE: Swap = Invert = true; break;
3525 default: llvm_unreachable("Invalid integer condition!");
3526 }
3527 if (Swap)
3528 std::swap(a&: C.Op0, b&: C.Op1);
3529
3530 if (C.ICmpType == SystemZICMP::UnsignedOnly)
3531 C.Opcode = SystemZISD::UCMP128HI;
3532 else
3533 C.Opcode = SystemZISD::SCMP128HI;
3534 C.CCValid = SystemZ::CCMASK_ANY;
3535 C.CCMask = SystemZ::CCMASK_1;
3536
3537 if (Invert)
3538 C.CCMask ^= C.CCValid;
3539}
3540
3541// See whether the comparison argument contains a redundant AND
3542// and remove it if so. This sometimes happens due to the generic
3543// BRCOND expansion.
3544static void adjustForRedundantAnd(SelectionDAG &DAG, const SDLoc &DL,
3545 Comparison &C) {
3546 if (C.Op0.getOpcode() != ISD::AND)
3547 return;
3548 auto *Mask = dyn_cast<ConstantSDNode>(Val: C.Op0.getOperand(i: 1));
3549 if (!Mask || Mask->getValueSizeInBits(ResNo: 0) > 64)
3550 return;
3551 KnownBits Known = DAG.computeKnownBits(Op: C.Op0.getOperand(i: 0));
3552 if ((~Known.Zero).getZExtValue() & ~Mask->getZExtValue())
3553 return;
3554
3555 C.Op0 = C.Op0.getOperand(i: 0);
3556}
3557
3558// Return a Comparison that tests the condition-code result of intrinsic
3559// node Call against constant integer CC using comparison code Cond.
3560// Opcode is the opcode of the SystemZISD operation for the intrinsic
3561// and CCValid is the set of possible condition-code results.
3562static Comparison getIntrinsicCmp(SelectionDAG &DAG, unsigned Opcode,
3563 SDValue Call, unsigned CCValid, uint64_t CC,
3564 ISD::CondCode Cond) {
3565 Comparison C(Call, SDValue(), SDValue());
3566 C.Opcode = Opcode;
3567 C.CCValid = CCValid;
3568 if (Cond == ISD::SETEQ)
3569 // bit 3 for CC==0, bit 0 for CC==3, always false for CC>3.
3570 C.CCMask = CC < 4 ? 1 << (3 - CC) : 0;
3571 else if (Cond == ISD::SETNE)
3572 // ...and the inverse of that.
3573 C.CCMask = CC < 4 ? ~(1 << (3 - CC)) : -1;
3574 else if (Cond == ISD::SETLT || Cond == ISD::SETULT)
3575 // bits above bit 3 for CC==0 (always false), bits above bit 0 for CC==3,
3576 // always true for CC>3.
3577 C.CCMask = CC < 4 ? ~0U << (4 - CC) : -1;
3578 else if (Cond == ISD::SETGE || Cond == ISD::SETUGE)
3579 // ...and the inverse of that.
3580 C.CCMask = CC < 4 ? ~(~0U << (4 - CC)) : 0;
3581 else if (Cond == ISD::SETLE || Cond == ISD::SETULE)
3582 // bit 3 and above for CC==0, bit 0 and above for CC==3 (always true),
3583 // always true for CC>3.
3584 C.CCMask = CC < 4 ? ~0U << (3 - CC) : -1;
3585 else if (Cond == ISD::SETGT || Cond == ISD::SETUGT)
3586 // ...and the inverse of that.
3587 C.CCMask = CC < 4 ? ~(~0U << (3 - CC)) : 0;
3588 else
3589 llvm_unreachable("Unexpected integer comparison type");
3590 C.CCMask &= CCValid;
3591 return C;
3592}
3593
3594// Decide how to implement a comparison of type Cond between CmpOp0 with CmpOp1.
3595static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
3596 ISD::CondCode Cond, const SDLoc &DL,
3597 SDValue Chain = SDValue(),
3598 bool IsSignaling = false) {
3599 if (CmpOp1.getOpcode() == ISD::Constant) {
3600 assert(!Chain);
3601 unsigned Opcode, CCValid;
3602 if (CmpOp0.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
3603 CmpOp0.getResNo() == 0 && CmpOp0->hasNUsesOfValue(NUses: 1, Value: 0) &&
3604 isIntrinsicWithCCAndChain(Op: CmpOp0, Opcode, CCValid))
3605 return getIntrinsicCmp(DAG, Opcode, Call: CmpOp0, CCValid,
3606 CC: CmpOp1->getAsZExtVal(), Cond);
3607 if (CmpOp0.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
3608 CmpOp0.getResNo() == CmpOp0->getNumValues() - 1 &&
3609 isIntrinsicWithCC(Op: CmpOp0, Opcode, CCValid))
3610 return getIntrinsicCmp(DAG, Opcode, Call: CmpOp0, CCValid,
3611 CC: CmpOp1->getAsZExtVal(), Cond);
3612 }
3613 Comparison C(CmpOp0, CmpOp1, Chain);
3614 C.CCMask = CCMaskForCondCode(CC: Cond);
3615 if (C.Op0.getValueType().isFloatingPoint()) {
3616 C.CCValid = SystemZ::CCMASK_FCMP;
3617 if (!C.Chain)
3618 C.Opcode = SystemZISD::FCMP;
3619 else if (!IsSignaling)
3620 C.Opcode = SystemZISD::STRICT_FCMP;
3621 else
3622 C.Opcode = SystemZISD::STRICT_FCMPS;
3623 adjustForFNeg(C);
3624 } else {
3625 assert(!C.Chain);
3626 C.CCValid = SystemZ::CCMASK_ICMP;
3627 C.Opcode = SystemZISD::ICMP;
3628 // Choose the type of comparison. Equality and inequality tests can
3629 // use either signed or unsigned comparisons. The choice also doesn't
3630 // matter if both sign bits are known to be clear. In those cases we
3631 // want to give the main isel code the freedom to choose whichever
3632 // form fits best.
3633 if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
3634 C.CCMask == SystemZ::CCMASK_CMP_NE ||
3635 (DAG.SignBitIsZero(Op: C.Op0) && DAG.SignBitIsZero(Op: C.Op1)))
3636 C.ICmpType = SystemZICMP::Any;
3637 else if (C.CCMask & SystemZ::CCMASK_CMP_UO)
3638 C.ICmpType = SystemZICMP::UnsignedOnly;
3639 else
3640 C.ICmpType = SystemZICMP::SignedOnly;
3641 C.CCMask &= ~SystemZ::CCMASK_CMP_UO;
3642 adjustForRedundantAnd(DAG, DL, C);
3643 adjustZeroCmp(DAG, DL, C);
3644 adjustSubwordCmp(DAG, DL, C);
3645 adjustForSubtraction(DAG, DL, C);
3646 adjustForLTGFR(C);
3647 adjustICmpTruncate(DAG, DL, C);
3648 }
3649
3650 if (shouldSwapCmpOperands(C)) {
3651 std::swap(a&: C.Op0, b&: C.Op1);
3652 C.CCMask = SystemZ::reverseCCMask(CCMask: C.CCMask);
3653 }
3654
3655 adjustForTestUnderMask(DAG, DL, C);
3656 adjustICmp128(DAG, DL, C);
3657 adjustForStackGuardCompare(DAG, DL, C);
3658 return C;
3659}
3660
3661// Emit the comparison instruction described by C.
3662static SDValue emitCmp(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) {
3663 if (!C.Op1.getNode()) {
3664 if (C.Opcode == SystemZISD::CMP_STACKGUARD)
3665 return DAG.getNode(Opcode: SystemZISD::CMP_STACKGUARD, DL, VT: MVT::i32, Operand: C.Op0);
3666 SDNode *Node;
3667 switch (C.Op0.getOpcode()) {
3668 case ISD::INTRINSIC_W_CHAIN:
3669 Node = emitIntrinsicWithCCAndChain(DAG, Op: C.Op0, Opcode: C.Opcode);
3670 return SDValue(Node, 0);
3671 case ISD::INTRINSIC_WO_CHAIN:
3672 Node = emitIntrinsicWithCC(DAG, Op: C.Op0, Opcode: C.Opcode);
3673 return SDValue(Node, Node->getNumValues() - 1);
3674 default:
3675 llvm_unreachable("Invalid comparison operands");
3676 }
3677 }
3678 if (C.Opcode == SystemZISD::ICMP)
3679 return DAG.getNode(Opcode: SystemZISD::ICMP, DL, VT: MVT::i32, N1: C.Op0, N2: C.Op1,
3680 N3: DAG.getTargetConstant(Val: C.ICmpType, DL, VT: MVT::i32));
3681 if (C.Opcode == SystemZISD::TM) {
3682 bool RegisterOnly = (bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_0) !=
3683 bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_1));
3684 return DAG.getNode(Opcode: SystemZISD::TM, DL, VT: MVT::i32, N1: C.Op0, N2: C.Op1,
3685 N3: DAG.getTargetConstant(Val: RegisterOnly, DL, VT: MVT::i32));
3686 }
3687 if (C.Opcode == SystemZISD::VICMPES ||
3688 C.Opcode == SystemZISD::VICMPHS ||
3689 C.Opcode == SystemZISD::VICMPHLS ||
3690 C.Opcode == SystemZISD::VFCMPES ||
3691 C.Opcode == SystemZISD::VFCMPHS ||
3692 C.Opcode == SystemZISD::VFCMPHES) {
3693 EVT IntVT = C.Op0.getValueType().changeVectorElementTypeToInteger();
3694 SDVTList VTs = DAG.getVTList(VT1: IntVT, VT2: MVT::i32);
3695 SDValue Val = DAG.getNode(Opcode: C.Opcode, DL, VTList: VTs, N1: C.Op0, N2: C.Op1);
3696 return SDValue(Val.getNode(), 1);
3697 }
3698 if (C.Chain) {
3699 SDVTList VTs = DAG.getVTList(VT1: MVT::i32, VT2: MVT::Other);
3700 return DAG.getNode(Opcode: C.Opcode, DL, VTList: VTs, N1: C.Chain, N2: C.Op0, N3: C.Op1);
3701 }
3702 return DAG.getNode(Opcode: C.Opcode, DL, VT: MVT::i32, N1: C.Op0, N2: C.Op1);
3703}
3704
3705// Implement a 32-bit *MUL_LOHI operation by extending both operands to
3706// 64 bits. Extend is the extension type to use. Store the high part
3707// in Hi and the low part in Lo.
3708static void lowerMUL_LOHI32(SelectionDAG &DAG, const SDLoc &DL, unsigned Extend,
3709 SDValue Op0, SDValue Op1, SDValue &Hi,
3710 SDValue &Lo) {
3711 Op0 = DAG.getNode(Opcode: Extend, DL, VT: MVT::i64, Operand: Op0);
3712 Op1 = DAG.getNode(Opcode: Extend, DL, VT: MVT::i64, Operand: Op1);
3713 SDValue Mul = DAG.getNode(Opcode: ISD::MUL, DL, VT: MVT::i64, N1: Op0, N2: Op1);
3714 Hi = DAG.getNode(Opcode: ISD::SRL, DL, VT: MVT::i64, N1: Mul,
3715 N2: DAG.getConstant(Val: 32, DL, VT: MVT::i64));
3716 Hi = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: MVT::i32, Operand: Hi);
3717 Lo = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: MVT::i32, Operand: Mul);
3718}
3719
3720// Lower a binary operation that produces two VT results, one in each
3721// half of a GR128 pair. Op0 and Op1 are the VT operands to the operation,
3722// and Opcode performs the GR128 operation. Store the even register result
3723// in Even and the odd register result in Odd.
3724static void lowerGR128Binary(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
3725 unsigned Opcode, SDValue Op0, SDValue Op1,
3726 SDValue &Even, SDValue &Odd) {
3727 SDValue Result = DAG.getNode(Opcode, DL, VT: MVT::Untyped, N1: Op0, N2: Op1);
3728 bool Is32Bit = is32Bit(VT);
3729 Even = DAG.getTargetExtractSubreg(SRIdx: SystemZ::even128(Is32bit: Is32Bit), DL, VT, Operand: Result);
3730 Odd = DAG.getTargetExtractSubreg(SRIdx: SystemZ::odd128(Is32bit: Is32Bit), DL, VT, Operand: Result);
3731}
3732
3733// Return an i32 value that is 1 if the CC value produced by CCReg is
3734// in the mask CCMask and 0 otherwise. CC is known to have a value
3735// in CCValid, so other values can be ignored.
3736static SDValue emitSETCC(SelectionDAG &DAG, const SDLoc &DL, SDValue CCReg,
3737 unsigned CCValid, unsigned CCMask) {
3738 SDValue Ops[] = {DAG.getConstant(Val: 1, DL, VT: MVT::i32),
3739 DAG.getConstant(Val: 0, DL, VT: MVT::i32),
3740 DAG.getTargetConstant(Val: CCValid, DL, VT: MVT::i32),
3741 DAG.getTargetConstant(Val: CCMask, DL, VT: MVT::i32), CCReg};
3742 return DAG.getNode(Opcode: SystemZISD::SELECT_CCMASK, DL, VT: MVT::i32, Ops);
3743}
3744
3745// Return the SystemISD vector comparison operation for CC, or 0 if it cannot
3746// be done directly. Mode is CmpMode::Int for integer comparisons, CmpMode::FP
3747// for regular floating-point comparisons, CmpMode::StrictFP for strict (quiet)
3748// floating-point comparisons, and CmpMode::SignalingFP for strict signaling
3749// floating-point comparisons.
3750enum class CmpMode { Int, FP, StrictFP, SignalingFP };
3751static unsigned getVectorComparison(ISD::CondCode CC, CmpMode Mode) {
3752 switch (CC) {
3753 case ISD::SETOEQ:
3754 case ISD::SETEQ:
3755 switch (Mode) {
3756 case CmpMode::Int: return SystemZISD::VICMPE;
3757 case CmpMode::FP: return SystemZISD::VFCMPE;
3758 case CmpMode::StrictFP: return SystemZISD::STRICT_VFCMPE;
3759 case CmpMode::SignalingFP: return SystemZISD::STRICT_VFCMPES;
3760 }
3761 llvm_unreachable("Bad mode");
3762
3763 case ISD::SETOGE:
3764 case ISD::SETGE:
3765 switch (Mode) {
3766 case CmpMode::Int: return 0;
3767 case CmpMode::FP: return SystemZISD::VFCMPHE;
3768 case CmpMode::StrictFP: return SystemZISD::STRICT_VFCMPHE;
3769 case CmpMode::SignalingFP: return SystemZISD::STRICT_VFCMPHES;
3770 }
3771 llvm_unreachable("Bad mode");
3772
3773 case ISD::SETOGT:
3774 case ISD::SETGT:
3775 switch (Mode) {
3776 case CmpMode::Int: return SystemZISD::VICMPH;
3777 case CmpMode::FP: return SystemZISD::VFCMPH;
3778 case CmpMode::StrictFP: return SystemZISD::STRICT_VFCMPH;
3779 case CmpMode::SignalingFP: return SystemZISD::STRICT_VFCMPHS;
3780 }
3781 llvm_unreachable("Bad mode");
3782
3783 case ISD::SETUGT:
3784 switch (Mode) {
3785 case CmpMode::Int: return SystemZISD::VICMPHL;
3786 case CmpMode::FP: return 0;
3787 case CmpMode::StrictFP: return 0;
3788 case CmpMode::SignalingFP: return 0;
3789 }
3790 llvm_unreachable("Bad mode");
3791
3792 default:
3793 return 0;
3794 }
3795}
3796
3797// Return the SystemZISD vector comparison operation for CC or its inverse,
3798// or 0 if neither can be done directly. Indicate in Invert whether the
3799// result is for the inverse of CC. Mode is as above.
3800static unsigned getVectorComparisonOrInvert(ISD::CondCode CC, CmpMode Mode,
3801 bool &Invert) {
3802 if (unsigned Opcode = getVectorComparison(CC, Mode)) {
3803 Invert = false;
3804 return Opcode;
3805 }
3806
3807 CC = ISD::getSetCCInverse(Operation: CC, Type: Mode == CmpMode::Int ? MVT::i32 : MVT::f32);
3808 if (unsigned Opcode = getVectorComparison(CC, Mode)) {
3809 Invert = true;
3810 return Opcode;
3811 }
3812
3813 return 0;
3814}
3815
3816// Return a v2f64 that contains the extended form of elements Start and Start+1
3817// of v4f32 value Op. If Chain is nonnull, return the strict form.
3818static SDValue expandV4F32ToV2F64(SelectionDAG &DAG, int Start, const SDLoc &DL,
3819 SDValue Op, SDValue Chain) {
3820 int Mask[] = { Start, -1, Start + 1, -1 };
3821 Op = DAG.getVectorShuffle(VT: MVT::v4f32, dl: DL, N1: Op, N2: DAG.getUNDEF(VT: MVT::v4f32), Mask);
3822 if (Chain) {
3823 SDVTList VTs = DAG.getVTList(VT1: MVT::v2f64, VT2: MVT::Other);
3824 return DAG.getNode(Opcode: SystemZISD::STRICT_VEXTEND, DL, VTList: VTs, N1: Chain, N2: Op);
3825 }
3826 return DAG.getNode(Opcode: SystemZISD::VEXTEND, DL, VT: MVT::v2f64, Operand: Op);
3827}
3828
3829// Build a comparison of vectors CmpOp0 and CmpOp1 using opcode Opcode,
3830// producing a result of type VT. If Chain is nonnull, return the strict form.
3831SDValue SystemZTargetLowering::getVectorCmp(SelectionDAG &DAG, unsigned Opcode,
3832 const SDLoc &DL, EVT VT,
3833 SDValue CmpOp0,
3834 SDValue CmpOp1,
3835 SDValue Chain) const {
3836 // There is no hardware support for v4f32 (unless we have the vector
3837 // enhancements facility 1), so extend the vector into two v2f64s
3838 // and compare those.
3839 if (CmpOp0.getValueType() == MVT::v4f32 &&
3840 !Subtarget.hasVectorEnhancements1()) {
3841 SDValue H0 = expandV4F32ToV2F64(DAG, Start: 0, DL, Op: CmpOp0, Chain);
3842 SDValue L0 = expandV4F32ToV2F64(DAG, Start: 2, DL, Op: CmpOp0, Chain);
3843 SDValue H1 = expandV4F32ToV2F64(DAG, Start: 0, DL, Op: CmpOp1, Chain);
3844 SDValue L1 = expandV4F32ToV2F64(DAG, Start: 2, DL, Op: CmpOp1, Chain);
3845 if (Chain) {
3846 SDVTList VTs = DAG.getVTList(VT1: MVT::v2i64, VT2: MVT::Other);
3847 SDValue HRes = DAG.getNode(Opcode, DL, VTList: VTs, N1: Chain, N2: H0, N3: H1);
3848 SDValue LRes = DAG.getNode(Opcode, DL, VTList: VTs, N1: Chain, N2: L0, N3: L1);
3849 SDValue Res = DAG.getNode(Opcode: SystemZISD::PACK, DL, VT, N1: HRes, N2: LRes);
3850 SDValue Chains[6] = { H0.getValue(R: 1), L0.getValue(R: 1),
3851 H1.getValue(R: 1), L1.getValue(R: 1),
3852 HRes.getValue(R: 1), LRes.getValue(R: 1) };
3853 SDValue NewChain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, Ops: Chains);
3854 SDValue Ops[2] = { Res, NewChain };
3855 return DAG.getMergeValues(Ops, dl: DL);
3856 }
3857 SDValue HRes = DAG.getNode(Opcode, DL, VT: MVT::v2i64, N1: H0, N2: H1);
3858 SDValue LRes = DAG.getNode(Opcode, DL, VT: MVT::v2i64, N1: L0, N2: L1);
3859 return DAG.getNode(Opcode: SystemZISD::PACK, DL, VT, N1: HRes, N2: LRes);
3860 }
3861 if (Chain) {
3862 SDVTList VTs = DAG.getVTList(VT1: VT, VT2: MVT::Other);
3863 return DAG.getNode(Opcode, DL, VTList: VTs, N1: Chain, N2: CmpOp0, N3: CmpOp1);
3864 }
3865 return DAG.getNode(Opcode, DL, VT, N1: CmpOp0, N2: CmpOp1);
3866}
3867
3868// Lower a vector comparison of type CC between CmpOp0 and CmpOp1, producing
3869// an integer mask of type VT. If Chain is nonnull, we have a strict
3870// floating-point comparison. If in addition IsSignaling is true, we have
3871// a strict signaling floating-point comparison.
3872SDValue SystemZTargetLowering::lowerVectorSETCC(SelectionDAG &DAG,
3873 const SDLoc &DL, EVT VT,
3874 ISD::CondCode CC,
3875 SDValue CmpOp0,
3876 SDValue CmpOp1,
3877 SDValue Chain,
3878 bool IsSignaling) const {
3879 bool IsFP = CmpOp0.getValueType().isFloatingPoint();
3880 assert (!Chain || IsFP);
3881 assert (!IsSignaling || Chain);
3882 CmpMode Mode = IsSignaling ? CmpMode::SignalingFP :
3883 Chain ? CmpMode::StrictFP : IsFP ? CmpMode::FP : CmpMode::Int;
3884 bool Invert = false;
3885 SDValue Cmp;
3886 switch (CC) {
3887 // Handle tests for order using (or (ogt y x) (oge x y)).
3888 case ISD::SETUO:
3889 Invert = true;
3890 [[fallthrough]];
3891 case ISD::SETO: {
3892 assert(IsFP && "Unexpected integer comparison");
3893 SDValue LT = getVectorCmp(DAG, Opcode: getVectorComparison(CC: ISD::SETOGT, Mode),
3894 DL, VT, CmpOp0: CmpOp1, CmpOp1: CmpOp0, Chain);
3895 SDValue GE = getVectorCmp(DAG, Opcode: getVectorComparison(CC: ISD::SETOGE, Mode),
3896 DL, VT, CmpOp0, CmpOp1, Chain);
3897 Cmp = DAG.getNode(Opcode: ISD::OR, DL, VT, N1: LT, N2: GE);
3898 if (Chain)
3899 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other,
3900 N1: LT.getValue(R: 1), N2: GE.getValue(R: 1));
3901 break;
3902 }
3903
3904 // Handle <> tests using (or (ogt y x) (ogt x y)).
3905 case ISD::SETUEQ:
3906 Invert = true;
3907 [[fallthrough]];
3908 case ISD::SETONE: {
3909 assert(IsFP && "Unexpected integer comparison");
3910 SDValue LT = getVectorCmp(DAG, Opcode: getVectorComparison(CC: ISD::SETOGT, Mode),
3911 DL, VT, CmpOp0: CmpOp1, CmpOp1: CmpOp0, Chain);
3912 SDValue GT = getVectorCmp(DAG, Opcode: getVectorComparison(CC: ISD::SETOGT, Mode),
3913 DL, VT, CmpOp0, CmpOp1, Chain);
3914 Cmp = DAG.getNode(Opcode: ISD::OR, DL, VT, N1: LT, N2: GT);
3915 if (Chain)
3916 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other,
3917 N1: LT.getValue(R: 1), N2: GT.getValue(R: 1));
3918 break;
3919 }
3920
3921 // Otherwise a single comparison is enough. It doesn't really
3922 // matter whether we try the inversion or the swap first, since
3923 // there are no cases where both work.
3924 default:
3925 // Optimize sign-bit comparisons to signed compares.
3926 if (Mode == CmpMode::Int && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
3927 ISD::isConstantSplatVectorAllZeros(N: CmpOp1.getNode())) {
3928 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3929 APInt Mask;
3930 if (CmpOp0.getOpcode() == ISD::AND
3931 && ISD::isConstantSplatVector(N: CmpOp0.getOperand(i: 1).getNode(), SplatValue&: Mask)
3932 && Mask == APInt::getSignMask(BitWidth: EltSize)) {
3933 CC = CC == ISD::SETEQ ? ISD::SETGE : ISD::SETLT;
3934 CmpOp0 = CmpOp0.getOperand(i: 0);
3935 }
3936 }
3937 if (unsigned Opcode = getVectorComparisonOrInvert(CC, Mode, Invert))
3938 Cmp = getVectorCmp(DAG, Opcode, DL, VT, CmpOp0, CmpOp1, Chain);
3939 else {
3940 CC = ISD::getSetCCSwappedOperands(Operation: CC);
3941 if (unsigned Opcode = getVectorComparisonOrInvert(CC, Mode, Invert))
3942 Cmp = getVectorCmp(DAG, Opcode, DL, VT, CmpOp0: CmpOp1, CmpOp1: CmpOp0, Chain);
3943 else
3944 llvm_unreachable("Unhandled comparison");
3945 }
3946 if (Chain)
3947 Chain = Cmp.getValue(R: 1);
3948 break;
3949 }
3950 if (Invert) {
3951 SDValue Mask =
3952 DAG.getSplatBuildVector(VT, DL, Op: DAG.getAllOnesConstant(DL, VT: MVT::i64));
3953 Cmp = DAG.getNode(Opcode: ISD::XOR, DL, VT, N1: Cmp, N2: Mask);
3954 }
3955 if (Chain && Chain.getNode() != Cmp.getNode()) {
3956 SDValue Ops[2] = { Cmp, Chain };
3957 Cmp = DAG.getMergeValues(Ops, dl: DL);
3958 }
3959 return Cmp;
3960}
3961
3962SDValue SystemZTargetLowering::lowerSETCC(SDValue Op,
3963 SelectionDAG &DAG) const {
3964 SDValue CmpOp0 = Op.getOperand(i: 0);
3965 SDValue CmpOp1 = Op.getOperand(i: 1);
3966 ISD::CondCode CC = cast<CondCodeSDNode>(Val: Op.getOperand(i: 2))->get();
3967 SDLoc DL(Op);
3968 EVT VT = Op.getValueType();
3969 if (VT.isVector())
3970 return lowerVectorSETCC(DAG, DL, VT, CC, CmpOp0, CmpOp1);
3971
3972 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, Cond: CC, DL));
3973 SDValue CCReg = emitCmp(DAG, DL, C);
3974 return emitSETCC(DAG, DL, CCReg, CCValid: C.CCValid, CCMask: C.CCMask);
3975}
3976
3977SDValue SystemZTargetLowering::lowerSTRICT_FSETCC(SDValue Op,
3978 SelectionDAG &DAG,
3979 bool IsSignaling) const {
3980 SDValue Chain = Op.getOperand(i: 0);
3981 SDValue CmpOp0 = Op.getOperand(i: 1);
3982 SDValue CmpOp1 = Op.getOperand(i: 2);
3983 ISD::CondCode CC = cast<CondCodeSDNode>(Val: Op.getOperand(i: 3))->get();
3984 SDLoc DL(Op);
3985 EVT VT = Op.getNode()->getValueType(ResNo: 0);
3986 if (VT.isVector()) {
3987 SDValue Res = lowerVectorSETCC(DAG, DL, VT, CC, CmpOp0, CmpOp1,
3988 Chain, IsSignaling);
3989 return Res.getValue(R: Op.getResNo());
3990 }
3991
3992 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, Cond: CC, DL, Chain, IsSignaling));
3993 SDValue CCReg = emitCmp(DAG, DL, C);
3994 CCReg->setFlags(Op->getFlags());
3995 SDValue Result = emitSETCC(DAG, DL, CCReg, CCValid: C.CCValid, CCMask: C.CCMask);
3996 SDValue Ops[2] = { Result, CCReg.getValue(R: 1) };
3997 return DAG.getMergeValues(Ops, dl: DL);
3998}
3999
4000SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
4001 ISD::CondCode CC = cast<CondCodeSDNode>(Val: Op.getOperand(i: 1))->get();
4002 SDValue CmpOp0 = Op.getOperand(i: 2);
4003 SDValue CmpOp1 = Op.getOperand(i: 3);
4004 SDValue Dest = Op.getOperand(i: 4);
4005 SDLoc DL(Op);
4006
4007 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, Cond: CC, DL));
4008 SDValue CCReg = emitCmp(DAG, DL, C);
4009 return DAG.getNode(
4010 Opcode: SystemZISD::BR_CCMASK, DL, VT: Op.getValueType(), N1: Op.getOperand(i: 0),
4011 N2: DAG.getTargetConstant(Val: C.CCValid, DL, VT: MVT::i32),
4012 N3: DAG.getTargetConstant(Val: C.CCMask, DL, VT: MVT::i32), N4: Dest, N5: CCReg);
4013}
4014
4015// Return true if Pos is CmpOp and Neg is the negative of CmpOp,
4016// allowing Pos and Neg to be wider than CmpOp.
4017static bool isAbsolute(SDValue CmpOp, SDValue Pos, SDValue Neg) {
4018 return (Neg.getOpcode() == ISD::SUB &&
4019 Neg.getOperand(i: 0).getOpcode() == ISD::Constant &&
4020 Neg.getConstantOperandVal(i: 0) == 0 && Neg.getOperand(i: 1) == Pos &&
4021 (Pos == CmpOp || (Pos.getOpcode() == ISD::SIGN_EXTEND &&
4022 Pos.getOperand(i: 0) == CmpOp)));
4023}
4024
4025// Return the absolute or negative absolute of Op; IsNegative decides which.
4026static SDValue getAbsolute(SelectionDAG &DAG, const SDLoc &DL, SDValue Op,
4027 bool IsNegative) {
4028 Op = DAG.getNode(Opcode: ISD::ABS, DL, VT: Op.getValueType(), Operand: Op);
4029 if (IsNegative)
4030 Op = DAG.getNode(Opcode: ISD::SUB, DL, VT: Op.getValueType(),
4031 N1: DAG.getConstant(Val: 0, DL, VT: Op.getValueType()), N2: Op);
4032 return Op;
4033}
4034
4035static SDValue getI128Select(SelectionDAG &DAG, const SDLoc &DL,
4036 Comparison C, SDValue TrueOp, SDValue FalseOp) {
4037 EVT VT = MVT::i128;
4038 unsigned Op;
4039
4040 if (C.CCMask == SystemZ::CCMASK_CMP_NE ||
4041 C.CCMask == SystemZ::CCMASK_CMP_GE ||
4042 C.CCMask == SystemZ::CCMASK_CMP_LE) {
4043 std::swap(a&: TrueOp, b&: FalseOp);
4044 C.CCMask ^= C.CCValid;
4045 }
4046 if (C.CCMask == SystemZ::CCMASK_CMP_LT) {
4047 std::swap(a&: C.Op0, b&: C.Op1);
4048 C.CCMask = SystemZ::CCMASK_CMP_GT;
4049 }
4050 switch (C.CCMask) {
4051 case SystemZ::CCMASK_CMP_EQ:
4052 Op = SystemZISD::VICMPE;
4053 break;
4054 case SystemZ::CCMASK_CMP_GT:
4055 if (C.ICmpType == SystemZICMP::UnsignedOnly)
4056 Op = SystemZISD::VICMPHL;
4057 else
4058 Op = SystemZISD::VICMPH;
4059 break;
4060 default:
4061 llvm_unreachable("Unhandled comparison");
4062 break;
4063 }
4064
4065 SDValue Mask = DAG.getNode(Opcode: Op, DL, VT, N1: C.Op0, N2: C.Op1);
4066 TrueOp = DAG.getNode(Opcode: ISD::AND, DL, VT, N1: TrueOp, N2: Mask);
4067 FalseOp = DAG.getNode(Opcode: ISD::AND, DL, VT, N1: FalseOp, N2: DAG.getNOT(DL, Val: Mask, VT));
4068 return DAG.getNode(Opcode: ISD::OR, DL, VT, N1: TrueOp, N2: FalseOp);
4069}
4070
4071SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
4072 SelectionDAG &DAG) const {
4073 SDValue CmpOp0 = Op.getOperand(i: 0);
4074 SDValue CmpOp1 = Op.getOperand(i: 1);
4075 SDValue TrueOp = Op.getOperand(i: 2);
4076 SDValue FalseOp = Op.getOperand(i: 3);
4077 ISD::CondCode CC = cast<CondCodeSDNode>(Val: Op.getOperand(i: 4))->get();
4078 SDLoc DL(Op);
4079
4080 // SELECT_CC involving f16 will not have the cmp-ops promoted by the
4081 // legalizer, as it will be handled according to the type of the resulting
4082 // value. Extend them here if needed.
4083 if (CmpOp0.getSimpleValueType() == MVT::f16) {
4084 CmpOp0 = DAG.getFPExtendOrRound(Op: CmpOp0, DL: SDLoc(CmpOp0), VT: MVT::f32);
4085 CmpOp1 = DAG.getFPExtendOrRound(Op: CmpOp1, DL: SDLoc(CmpOp1), VT: MVT::f32);
4086 }
4087
4088 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, Cond: CC, DL));
4089
4090 // Check for absolute and negative-absolute selections, including those
4091 // where the comparison value is sign-extended (for LPGFR and LNGFR).
4092 // This check supplements the one in DAGCombiner.
4093 if (C.Opcode == SystemZISD::ICMP && C.CCMask != SystemZ::CCMASK_CMP_EQ &&
4094 C.CCMask != SystemZ::CCMASK_CMP_NE &&
4095 C.Op1.getOpcode() == ISD::Constant &&
4096 cast<ConstantSDNode>(Val&: C.Op1)->getValueSizeInBits(ResNo: 0) <= 64 &&
4097 C.Op1->getAsZExtVal() == 0) {
4098 if (isAbsolute(CmpOp: C.Op0, Pos: TrueOp, Neg: FalseOp))
4099 return getAbsolute(DAG, DL, Op: TrueOp, IsNegative: C.CCMask & SystemZ::CCMASK_CMP_LT);
4100 if (isAbsolute(CmpOp: C.Op0, Pos: FalseOp, Neg: TrueOp))
4101 return getAbsolute(DAG, DL, Op: FalseOp, IsNegative: C.CCMask & SystemZ::CCMASK_CMP_GT);
4102 }
4103
4104 if (Subtarget.hasVectorEnhancements3() &&
4105 C.Opcode == SystemZISD::ICMP &&
4106 C.Op0.getValueType() == MVT::i128 &&
4107 TrueOp.getValueType() == MVT::i128) {
4108 return getI128Select(DAG, DL, C, TrueOp, FalseOp);
4109 }
4110
4111 SDValue CCReg = emitCmp(DAG, DL, C);
4112 SDValue Ops[] = {TrueOp, FalseOp,
4113 DAG.getTargetConstant(Val: C.CCValid, DL, VT: MVT::i32),
4114 DAG.getTargetConstant(Val: C.CCMask, DL, VT: MVT::i32), CCReg};
4115
4116 return DAG.getNode(Opcode: SystemZISD::SELECT_CCMASK, DL, VT: Op.getValueType(), Ops);
4117}
4118
4119SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
4120 SelectionDAG &DAG) const {
4121 SDLoc DL(Node);
4122 const GlobalValue *GV = Node->getGlobal();
4123 int64_t Offset = Node->getOffset();
4124 EVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
4125 CodeModel::Model CM = DAG.getTarget().getCodeModel();
4126
4127 SDValue Result;
4128 if (Subtarget.isPC32DBLSymbol(GV, CM)) {
4129 if (isInt<32>(x: Offset)) {
4130 // Assign anchors at 1<<12 byte boundaries.
4131 uint64_t Anchor = Offset & ~uint64_t(0xfff);
4132 Result = DAG.getTargetGlobalAddress(GV, DL, VT: PtrVT, offset: Anchor);
4133 Result = DAG.getNode(Opcode: SystemZISD::PCREL_WRAPPER, DL, VT: PtrVT, Operand: Result);
4134
4135 // The offset can be folded into the address if it is aligned to a
4136 // halfword.
4137 Offset -= Anchor;
4138 if (Offset != 0 && (Offset & 1) == 0) {
4139 SDValue Full =
4140 DAG.getTargetGlobalAddress(GV, DL, VT: PtrVT, offset: Anchor + Offset);
4141 Result = DAG.getNode(Opcode: SystemZISD::PCREL_OFFSET, DL, VT: PtrVT, N1: Full, N2: Result);
4142 Offset = 0;
4143 }
4144 } else {
4145 // Conservatively load a constant offset greater than 32 bits into a
4146 // register below.
4147 Result = DAG.getTargetGlobalAddress(GV, DL, VT: PtrVT);
4148 Result = DAG.getNode(Opcode: SystemZISD::PCREL_WRAPPER, DL, VT: PtrVT, Operand: Result);
4149 }
4150 } else if (Subtarget.isTargetELF()) {
4151 Result = DAG.getTargetGlobalAddress(GV, DL, VT: PtrVT, offset: 0, TargetFlags: SystemZII::MO_GOT);
4152 Result = DAG.getNode(Opcode: SystemZISD::PCREL_WRAPPER, DL, VT: PtrVT, Operand: Result);
4153 Result = DAG.getLoad(VT: PtrVT, dl: DL, Chain: DAG.getEntryNode(), Ptr: Result,
4154 PtrInfo: MachinePointerInfo::getGOT(MF&: DAG.getMachineFunction()));
4155 } else if (Subtarget.isTargetzOS()) {
4156 Result = getADAEntry(DAG, GV, DL, PtrVT);
4157 } else
4158 llvm_unreachable("Unexpected Subtarget");
4159
4160 // If there was a non-zero offset that we didn't fold, create an explicit
4161 // addition for it.
4162 if (Offset != 0)
4163 Result = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: Result,
4164 N2: DAG.getSignedConstant(Val: Offset, DL, VT: PtrVT));
4165
4166 return Result;
4167}
4168
4169SDValue SystemZTargetLowering::lowerTLSGetOffset(GlobalAddressSDNode *Node,
4170 SelectionDAG &DAG,
4171 unsigned Opcode,
4172 SDValue GOTOffset) const {
4173 SDLoc DL(Node);
4174 EVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
4175 SDValue Chain = DAG.getEntryNode();
4176 SDValue Glue;
4177
4178 if (DAG.getMachineFunction().getFunction().getCallingConv() ==
4179 CallingConv::GHC)
4180 report_fatal_error(reason: "In GHC calling convention TLS is not supported");
4181
4182 // __tls_get_offset takes the GOT offset in %r2 and the GOT in %r12.
4183 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(VT: PtrVT);
4184 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: SystemZ::R12D, N: GOT, Glue);
4185 Glue = Chain.getValue(R: 1);
4186 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: SystemZ::R2D, N: GOTOffset, Glue);
4187 Glue = Chain.getValue(R: 1);
4188
4189 // The first call operand is the chain and the second is the TLS symbol.
4190 SmallVector<SDValue, 8> Ops;
4191 Ops.push_back(Elt: Chain);
4192 Ops.push_back(Elt: DAG.getTargetGlobalAddress(GV: Node->getGlobal(), DL,
4193 VT: Node->getValueType(ResNo: 0),
4194 offset: 0, TargetFlags: 0));
4195
4196 // Add argument registers to the end of the list so that they are
4197 // known live into the call.
4198 Ops.push_back(Elt: DAG.getRegister(Reg: SystemZ::R2D, VT: PtrVT));
4199 Ops.push_back(Elt: DAG.getRegister(Reg: SystemZ::R12D, VT: PtrVT));
4200
4201 // Add a register mask operand representing the call-preserved registers.
4202 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
4203 const uint32_t *Mask =
4204 TRI->getCallPreservedMask(MF: DAG.getMachineFunction(), CallingConv::C);
4205 assert(Mask && "Missing call preserved mask for calling convention");
4206 Ops.push_back(Elt: DAG.getRegisterMask(RegMask: Mask));
4207
4208 // Glue the call to the argument copies.
4209 Ops.push_back(Elt: Glue);
4210
4211 // Emit the call.
4212 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
4213 Chain = DAG.getNode(Opcode, DL, VTList: NodeTys, Ops);
4214 Glue = Chain.getValue(R: 1);
4215
4216 // Copy the return value from %r2.
4217 return DAG.getCopyFromReg(Chain, dl: DL, Reg: SystemZ::R2D, VT: PtrVT, Glue);
4218}
4219
4220SDValue SystemZTargetLowering::lowerThreadPointer(const SDLoc &DL,
4221 SelectionDAG &DAG) const {
4222 SDValue Chain = DAG.getEntryNode();
4223 EVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
4224
4225 // The high part of the thread pointer is in access register 0.
4226 SDValue TPHi = DAG.getCopyFromReg(Chain, dl: DL, Reg: SystemZ::A0, VT: MVT::i32);
4227 TPHi = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: PtrVT, Operand: TPHi);
4228
4229 // The low part of the thread pointer is in access register 1.
4230 SDValue TPLo = DAG.getCopyFromReg(Chain, dl: DL, Reg: SystemZ::A1, VT: MVT::i32);
4231 TPLo = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: PtrVT, Operand: TPLo);
4232
4233 // Merge them into a single 64-bit address.
4234 SDValue TPHiShifted = DAG.getNode(Opcode: ISD::SHL, DL, VT: PtrVT, N1: TPHi,
4235 N2: DAG.getConstant(Val: 32, DL, VT: PtrVT));
4236 return DAG.getNode(Opcode: ISD::OR, DL, VT: PtrVT, N1: TPHiShifted, N2: TPLo);
4237}
4238
4239SDValue SystemZTargetLowering::lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
4240 SelectionDAG &DAG) const {
4241 if (DAG.getTarget().useEmulatedTLS())
4242 return LowerToTLSEmulatedModel(GA: Node, DAG);
4243 SDLoc DL(Node);
4244 const GlobalValue *GV = Node->getGlobal();
4245 EVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
4246 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
4247
4248 if (DAG.getMachineFunction().getFunction().getCallingConv() ==
4249 CallingConv::GHC)
4250 report_fatal_error(reason: "In GHC calling convention TLS is not supported");
4251
4252 SDValue TP = lowerThreadPointer(DL, DAG);
4253
4254 // Get the offset of GA from the thread pointer, based on the TLS model.
4255 SDValue Offset;
4256 switch (model) {
4257 case TLSModel::GeneralDynamic: {
4258 // Load the GOT offset of the tls_index (module ID / per-symbol offset).
4259 SystemZConstantPoolValue *CPV =
4260 SystemZConstantPoolValue::Create(GV, Modifier: SystemZCP::TLSGD);
4261
4262 Offset = DAG.getConstantPool(C: CPV, VT: PtrVT, Align: Align(8));
4263 Offset = DAG.getLoad(
4264 VT: PtrVT, dl: DL, Chain: DAG.getEntryNode(), Ptr: Offset,
4265 PtrInfo: MachinePointerInfo::getConstantPool(MF&: DAG.getMachineFunction()));
4266
4267 // Call __tls_get_offset to retrieve the offset.
4268 Offset = lowerTLSGetOffset(Node, DAG, Opcode: SystemZISD::TLS_GDCALL, GOTOffset: Offset);
4269 break;
4270 }
4271
4272 case TLSModel::LocalDynamic: {
4273 // Load the GOT offset of the module ID.
4274 SystemZConstantPoolValue *CPV =
4275 SystemZConstantPoolValue::Create(GV, Modifier: SystemZCP::TLSLDM);
4276
4277 Offset = DAG.getConstantPool(C: CPV, VT: PtrVT, Align: Align(8));
4278 Offset = DAG.getLoad(
4279 VT: PtrVT, dl: DL, Chain: DAG.getEntryNode(), Ptr: Offset,
4280 PtrInfo: MachinePointerInfo::getConstantPool(MF&: DAG.getMachineFunction()));
4281
4282 // Call __tls_get_offset to retrieve the module base offset.
4283 Offset = lowerTLSGetOffset(Node, DAG, Opcode: SystemZISD::TLS_LDCALL, GOTOffset: Offset);
4284
4285 // Note: The SystemZLDCleanupPass will remove redundant computations
4286 // of the module base offset. Count total number of local-dynamic
4287 // accesses to trigger execution of that pass.
4288 SystemZMachineFunctionInfo* MFI =
4289 DAG.getMachineFunction().getInfo<SystemZMachineFunctionInfo>();
4290 MFI->incNumLocalDynamicTLSAccesses();
4291
4292 // Add the per-symbol offset.
4293 CPV = SystemZConstantPoolValue::Create(GV, Modifier: SystemZCP::DTPOFF);
4294
4295 SDValue DTPOffset = DAG.getConstantPool(C: CPV, VT: PtrVT, Align: Align(8));
4296 DTPOffset = DAG.getLoad(
4297 VT: PtrVT, dl: DL, Chain: DAG.getEntryNode(), Ptr: DTPOffset,
4298 PtrInfo: MachinePointerInfo::getConstantPool(MF&: DAG.getMachineFunction()));
4299
4300 Offset = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: Offset, N2: DTPOffset);
4301 break;
4302 }
4303
4304 case TLSModel::InitialExec: {
4305 // Load the offset from the GOT.
4306 Offset = DAG.getTargetGlobalAddress(GV, DL, VT: PtrVT, offset: 0,
4307 TargetFlags: SystemZII::MO_INDNTPOFF);
4308 Offset = DAG.getNode(Opcode: SystemZISD::PCREL_WRAPPER, DL, VT: PtrVT, Operand: Offset);
4309 Offset =
4310 DAG.getLoad(VT: PtrVT, dl: DL, Chain: DAG.getEntryNode(), Ptr: Offset,
4311 PtrInfo: MachinePointerInfo::getGOT(MF&: DAG.getMachineFunction()));
4312 break;
4313 }
4314
4315 case TLSModel::LocalExec: {
4316 // Force the offset into the constant pool and load it from there.
4317 SystemZConstantPoolValue *CPV =
4318 SystemZConstantPoolValue::Create(GV, Modifier: SystemZCP::NTPOFF);
4319
4320 Offset = DAG.getConstantPool(C: CPV, VT: PtrVT, Align: Align(8));
4321 Offset = DAG.getLoad(
4322 VT: PtrVT, dl: DL, Chain: DAG.getEntryNode(), Ptr: Offset,
4323 PtrInfo: MachinePointerInfo::getConstantPool(MF&: DAG.getMachineFunction()));
4324 break;
4325 }
4326 }
4327
4328 // Add the base and offset together.
4329 return DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: TP, N2: Offset);
4330}
4331
4332SDValue SystemZTargetLowering::lowerBlockAddress(BlockAddressSDNode *Node,
4333 SelectionDAG &DAG) const {
4334 SDLoc DL(Node);
4335 const BlockAddress *BA = Node->getBlockAddress();
4336 int64_t Offset = Node->getOffset();
4337 EVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
4338
4339 SDValue Result = DAG.getTargetBlockAddress(BA, VT: PtrVT, Offset);
4340 Result = DAG.getNode(Opcode: SystemZISD::PCREL_WRAPPER, DL, VT: PtrVT, Operand: Result);
4341 return Result;
4342}
4343
4344SDValue SystemZTargetLowering::lowerJumpTable(JumpTableSDNode *JT,
4345 SelectionDAG &DAG) const {
4346 SDLoc DL(JT);
4347 EVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
4348 SDValue Result = DAG.getTargetJumpTable(JTI: JT->getIndex(), VT: PtrVT);
4349
4350 // Use LARL to load the address of the table.
4351 return DAG.getNode(Opcode: SystemZISD::PCREL_WRAPPER, DL, VT: PtrVT, Operand: Result);
4352}
4353
4354SDValue SystemZTargetLowering::lowerConstantPool(ConstantPoolSDNode *CP,
4355 SelectionDAG &DAG) const {
4356 SDLoc DL(CP);
4357 EVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
4358
4359 SDValue Result;
4360 if (CP->isMachineConstantPoolEntry())
4361 Result =
4362 DAG.getTargetConstantPool(C: CP->getMachineCPVal(), VT: PtrVT, Align: CP->getAlign());
4363 else
4364 Result = DAG.getTargetConstantPool(C: CP->getConstVal(), VT: PtrVT, Align: CP->getAlign(),
4365 Offset: CP->getOffset());
4366
4367 // Use LARL to load the address of the constant pool entry.
4368 return DAG.getNode(Opcode: SystemZISD::PCREL_WRAPPER, DL, VT: PtrVT, Operand: Result);
4369}
4370
4371SDValue SystemZTargetLowering::lowerFRAMEADDR(SDValue Op,
4372 SelectionDAG &DAG) const {
4373 auto *TFL = Subtarget.getFrameLowering<SystemZFrameLowering>();
4374 MachineFunction &MF = DAG.getMachineFunction();
4375 MachineFrameInfo &MFI = MF.getFrameInfo();
4376 MFI.setFrameAddressIsTaken(true);
4377
4378 SDLoc DL(Op);
4379 unsigned Depth = Op.getConstantOperandVal(i: 0);
4380 EVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
4381
4382 // By definition, the frame address is the address of the back chain. (In
4383 // the case of packed stack without backchain, return the address where the
4384 // backchain would have been stored. This will either be an unused space or
4385 // contain a saved register).
4386 int BackChainIdx = TFL->getOrCreateFramePointerSaveIndex(MF);
4387 SDValue BackChain = DAG.getFrameIndex(FI: BackChainIdx, VT: PtrVT);
4388
4389 if (Depth > 0) {
4390 // FIXME The frontend should detect this case.
4391 if (!MF.getSubtarget<SystemZSubtarget>().hasBackChain())
4392 report_fatal_error(reason: "Unsupported stack frame traversal count");
4393
4394 SDValue Offset = DAG.getConstant(Val: TFL->getBackchainOffset(MF), DL, VT: PtrVT);
4395 while (Depth--) {
4396 BackChain = DAG.getLoad(VT: PtrVT, dl: DL, Chain: DAG.getEntryNode(), Ptr: BackChain,
4397 PtrInfo: MachinePointerInfo());
4398 BackChain = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: BackChain, N2: Offset);
4399 }
4400 }
4401
4402 return BackChain;
4403}
4404
4405SDValue SystemZTargetLowering::lowerRETURNADDR(SDValue Op,
4406 SelectionDAG &DAG) const {
4407 MachineFunction &MF = DAG.getMachineFunction();
4408 MachineFrameInfo &MFI = MF.getFrameInfo();
4409 MFI.setReturnAddressIsTaken(true);
4410
4411 SDLoc DL(Op);
4412 unsigned Depth = Op.getConstantOperandVal(i: 0);
4413 EVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
4414
4415 if (Depth > 0) {
4416 // FIXME The frontend should detect this case.
4417 if (!MF.getSubtarget<SystemZSubtarget>().hasBackChain())
4418 report_fatal_error(reason: "Unsupported stack frame traversal count");
4419
4420 SDValue FrameAddr = lowerFRAMEADDR(Op, DAG);
4421 const auto *TFL = Subtarget.getFrameLowering<SystemZFrameLowering>();
4422 int Offset = TFL->getReturnAddressOffset(MF);
4423 SDValue Ptr = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: FrameAddr,
4424 N2: DAG.getSignedConstant(Val: Offset, DL, VT: PtrVT));
4425 return DAG.getLoad(VT: PtrVT, dl: DL, Chain: DAG.getEntryNode(), Ptr,
4426 PtrInfo: MachinePointerInfo());
4427 }
4428
4429 // Return R14D (Elf) / R7D (XPLINK), which has the return address. Mark it an
4430 // implicit live-in.
4431 SystemZCallingConventionRegisters *CCR = Subtarget.getSpecialRegisters();
4432 Register LinkReg = MF.addLiveIn(PReg: CCR->getReturnFunctionAddressRegister(),
4433 RC: &SystemZ::GR64BitRegClass);
4434 return DAG.getCopyFromReg(Chain: DAG.getEntryNode(), dl: DL, Reg: LinkReg, VT: PtrVT);
4435}
4436
4437SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
4438 SelectionDAG &DAG) const {
4439 SDLoc DL(Op);
4440 SDValue In = Op.getOperand(i: 0);
4441 EVT InVT = In.getValueType();
4442 EVT ResVT = Op.getValueType();
4443
4444 // Convert loads directly. This is normally done by DAGCombiner,
4445 // but we need this case for bitcasts that are created during lowering
4446 // and which are then lowered themselves.
4447 if (auto *LoadN = dyn_cast<LoadSDNode>(Val&: In))
4448 if (ISD::isNormalLoad(N: LoadN)) {
4449 SDValue NewLoad = DAG.getLoad(VT: ResVT, dl: DL, Chain: LoadN->getChain(),
4450 Ptr: LoadN->getBasePtr(), MMO: LoadN->getMemOperand());
4451 // Update the chain uses.
4452 DAG.ReplaceAllUsesOfValueWith(From: SDValue(LoadN, 1), To: NewLoad.getValue(R: 1));
4453 return NewLoad;
4454 }
4455
4456 if (InVT == MVT::i32 && ResVT == MVT::f32) {
4457 SDValue In64;
4458 if (Subtarget.hasHighWord()) {
4459 SDNode *U64 = DAG.getMachineNode(Opcode: TargetOpcode::IMPLICIT_DEF, dl: DL,
4460 VT: MVT::i64);
4461 In64 = DAG.getTargetInsertSubreg(SRIdx: SystemZ::subreg_h32, DL,
4462 VT: MVT::i64, Operand: SDValue(U64, 0), Subreg: In);
4463 } else {
4464 In64 = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: MVT::i64, Operand: In);
4465 In64 = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i64, N1: In64,
4466 N2: DAG.getConstant(Val: 32, DL, VT: MVT::i64));
4467 }
4468 SDValue Out64 = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: MVT::f64, Operand: In64);
4469 return DAG.getTargetExtractSubreg(SRIdx: SystemZ::subreg_h32,
4470 DL, VT: MVT::f32, Operand: Out64);
4471 }
4472 if (InVT == MVT::f32 && ResVT == MVT::i32) {
4473 SDNode *U64 = DAG.getMachineNode(Opcode: TargetOpcode::IMPLICIT_DEF, dl: DL, VT: MVT::f64);
4474 SDValue In64 = DAG.getTargetInsertSubreg(SRIdx: SystemZ::subreg_h32, DL,
4475 VT: MVT::f64, Operand: SDValue(U64, 0), Subreg: In);
4476 SDValue Out64 = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: MVT::i64, Operand: In64);
4477 if (Subtarget.hasHighWord())
4478 return DAG.getTargetExtractSubreg(SRIdx: SystemZ::subreg_h32, DL,
4479 VT: MVT::i32, Operand: Out64);
4480 SDValue Shift = DAG.getNode(Opcode: ISD::SRL, DL, VT: MVT::i64, N1: Out64,
4481 N2: DAG.getConstant(Val: 32, DL, VT: MVT::i64));
4482 return DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: MVT::i32, Operand: Shift);
4483 }
4484 llvm_unreachable("Unexpected bitcast combination");
4485}
4486
4487SDValue SystemZTargetLowering::lowerVASTART(SDValue Op,
4488 SelectionDAG &DAG) const {
4489
4490 if (Subtarget.isTargetXPLINK64())
4491 return lowerVASTART_XPLINK(Op, DAG);
4492 else
4493 return lowerVASTART_ELF(Op, DAG);
4494}
4495
4496SDValue SystemZTargetLowering::lowerVASTART_XPLINK(SDValue Op,
4497 SelectionDAG &DAG) const {
4498 MachineFunction &MF = DAG.getMachineFunction();
4499 SystemZMachineFunctionInfo *FuncInfo =
4500 MF.getInfo<SystemZMachineFunctionInfo>();
4501
4502 SDLoc DL(Op);
4503
4504 // vastart just stores the address of the VarArgsFrameIndex slot into the
4505 // memory location argument.
4506 EVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
4507 SDValue FR = DAG.getFrameIndex(FI: FuncInfo->getVarArgsFrameIndex(), VT: PtrVT);
4508 const Value *SV = cast<SrcValueSDNode>(Val: Op.getOperand(i: 2))->getValue();
4509 return DAG.getStore(Chain: Op.getOperand(i: 0), dl: DL, Val: FR, Ptr: Op.getOperand(i: 1),
4510 PtrInfo: MachinePointerInfo(SV));
4511}
4512
4513SDValue SystemZTargetLowering::lowerVASTART_ELF(SDValue Op,
4514 SelectionDAG &DAG) const {
4515 MachineFunction &MF = DAG.getMachineFunction();
4516 SystemZMachineFunctionInfo *FuncInfo =
4517 MF.getInfo<SystemZMachineFunctionInfo>();
4518 EVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
4519
4520 SDValue Chain = Op.getOperand(i: 0);
4521 SDValue Addr = Op.getOperand(i: 1);
4522 const Value *SV = cast<SrcValueSDNode>(Val: Op.getOperand(i: 2))->getValue();
4523 SDLoc DL(Op);
4524
4525 // The initial values of each field.
4526 const unsigned NumFields = 4;
4527 SDValue Fields[NumFields] = {
4528 DAG.getConstant(Val: FuncInfo->getVarArgsFirstGPR(), DL, VT: PtrVT),
4529 DAG.getConstant(Val: FuncInfo->getVarArgsFirstFPR(), DL, VT: PtrVT),
4530 DAG.getFrameIndex(FI: FuncInfo->getVarArgsFrameIndex(), VT: PtrVT),
4531 DAG.getFrameIndex(FI: FuncInfo->getRegSaveFrameIndex(), VT: PtrVT)
4532 };
4533
4534 // Store each field into its respective slot.
4535 SDValue MemOps[NumFields];
4536 unsigned Offset = 0;
4537 for (unsigned I = 0; I < NumFields; ++I) {
4538 SDValue FieldAddr = Addr;
4539 if (Offset != 0)
4540 FieldAddr = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: FieldAddr,
4541 N2: DAG.getIntPtrConstant(Val: Offset, DL));
4542 MemOps[I] = DAG.getStore(Chain, dl: DL, Val: Fields[I], Ptr: FieldAddr,
4543 PtrInfo: MachinePointerInfo(SV, Offset));
4544 Offset += 8;
4545 }
4546 return DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, Ops: MemOps);
4547}
4548
4549SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
4550 SelectionDAG &DAG) const {
4551 SDValue Chain = Op.getOperand(i: 0);
4552 SDValue DstPtr = Op.getOperand(i: 1);
4553 SDValue SrcPtr = Op.getOperand(i: 2);
4554 const Value *DstSV = cast<SrcValueSDNode>(Val: Op.getOperand(i: 3))->getValue();
4555 const Value *SrcSV = cast<SrcValueSDNode>(Val: Op.getOperand(i: 4))->getValue();
4556 SDLoc DL(Op);
4557
4558 uint32_t Sz =
4559 Subtarget.isTargetXPLINK64() ? getTargetMachine().getPointerSize(AS: 0) : 32;
4560 return DAG.getMemcpy(Chain, dl: DL, Dst: DstPtr, Src: SrcPtr, Size: DAG.getIntPtrConstant(Val: Sz, DL),
4561 DstAlign: Align(8), SrcAlign: Align(8), /*isVolatile*/ isVol: false,
4562 /*AlwaysInline*/ false,
4563 /*CI=*/nullptr, OverrideTailCall: std::nullopt, DstPtrInfo: MachinePointerInfo(DstSV),
4564 SrcPtrInfo: MachinePointerInfo(SrcSV));
4565}
4566
4567SDValue
4568SystemZTargetLowering::lowerDYNAMIC_STACKALLOC(SDValue Op,
4569 SelectionDAG &DAG) const {
4570 if (Subtarget.isTargetXPLINK64())
4571 return lowerDYNAMIC_STACKALLOC_XPLINK(Op, DAG);
4572 else
4573 return lowerDYNAMIC_STACKALLOC_ELF(Op, DAG);
4574}
4575
4576SDValue
4577SystemZTargetLowering::lowerDYNAMIC_STACKALLOC_XPLINK(SDValue Op,
4578 SelectionDAG &DAG) const {
4579 const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
4580 MachineFunction &MF = DAG.getMachineFunction();
4581 bool RealignOpt = !MF.getFunction().hasFnAttribute(Kind: "no-realign-stack");
4582 SDValue Chain = Op.getOperand(i: 0);
4583 SDValue Size = Op.getOperand(i: 1);
4584 SDValue Align = Op.getOperand(i: 2);
4585 SDLoc DL(Op);
4586
4587 // If user has set the no alignment function attribute, ignore
4588 // alloca alignments.
4589 uint64_t AlignVal = (RealignOpt ? Align->getAsZExtVal() : 0);
4590
4591 uint64_t StackAlign = TFI->getStackAlignment();
4592 uint64_t RequiredAlign = std::max(a: AlignVal, b: StackAlign);
4593 uint64_t ExtraAlignSpace = RequiredAlign - StackAlign;
4594
4595 SDValue NeededSpace = Size;
4596
4597 // Add extra space for alignment if needed.
4598 EVT PtrVT = getPointerTy(DL: MF.getDataLayout());
4599 if (ExtraAlignSpace)
4600 NeededSpace = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: NeededSpace,
4601 N2: DAG.getConstant(Val: ExtraAlignSpace, DL, VT: PtrVT));
4602
4603 bool IsSigned = false;
4604 bool DoesNotReturn = false;
4605 bool IsReturnValueUsed = false;
4606 EVT VT = Op.getValueType();
4607 SDValue AllocaCall =
4608 makeExternalCall(Chain, DAG, CalleeName: "@@ALCAXP", RetVT: VT, Ops: ArrayRef(NeededSpace),
4609 CallConv: CallingConv::C, IsSigned, DL, DoesNotReturn,
4610 IsReturnValueUsed)
4611 .first;
4612
4613 // Perform a CopyFromReg from %GPR4 (stack pointer register). Chain and Glue
4614 // to end of call in order to ensure it isn't broken up from the call
4615 // sequence.
4616 auto &Regs = Subtarget.getSpecialRegisters<SystemZXPLINK64Registers>();
4617 Register SPReg = Regs.getStackPointerRegister();
4618 Chain = AllocaCall.getValue(R: 1);
4619 SDValue Glue = AllocaCall.getValue(R: 2);
4620 SDValue NewSPRegNode = DAG.getCopyFromReg(Chain, dl: DL, Reg: SPReg, VT: PtrVT, Glue);
4621 Chain = NewSPRegNode.getValue(R: 1);
4622
4623 MVT PtrMVT = getPointerMemTy(DL: MF.getDataLayout());
4624 SDValue ArgAdjust = DAG.getNode(Opcode: SystemZISD::ADJDYNALLOC, DL, VT: PtrMVT);
4625 SDValue Result = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrMVT, N1: NewSPRegNode, N2: ArgAdjust);
4626
4627 // Dynamically realign if needed.
4628 if (ExtraAlignSpace) {
4629 Result = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: Result,
4630 N2: DAG.getConstant(Val: ExtraAlignSpace, DL, VT: PtrVT));
4631 Result = DAG.getNode(Opcode: ISD::AND, DL, VT: PtrVT, N1: Result,
4632 N2: DAG.getConstant(Val: ~(RequiredAlign - 1), DL, VT: PtrVT));
4633 }
4634
4635 SDValue Ops[2] = {Result, Chain};
4636 return DAG.getMergeValues(Ops, dl: DL);
4637}
4638
4639SDValue
4640SystemZTargetLowering::lowerDYNAMIC_STACKALLOC_ELF(SDValue Op,
4641 SelectionDAG &DAG) const {
4642 const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
4643 MachineFunction &MF = DAG.getMachineFunction();
4644 bool RealignOpt = !MF.getFunction().hasFnAttribute(Kind: "no-realign-stack");
4645 bool StoreBackchain = MF.getSubtarget<SystemZSubtarget>().hasBackChain();
4646
4647 SDValue Chain = Op.getOperand(i: 0);
4648 SDValue Size = Op.getOperand(i: 1);
4649 SDValue Align = Op.getOperand(i: 2);
4650 SDLoc DL(Op);
4651
4652 // If user has set the no alignment function attribute, ignore
4653 // alloca alignments.
4654 uint64_t AlignVal = (RealignOpt ? Align->getAsZExtVal() : 0);
4655
4656 uint64_t StackAlign = TFI->getStackAlignment();
4657 uint64_t RequiredAlign = std::max(a: AlignVal, b: StackAlign);
4658 uint64_t ExtraAlignSpace = RequiredAlign - StackAlign;
4659
4660 Register SPReg = getStackPointerRegisterToSaveRestore();
4661 SDValue NeededSpace = Size;
4662
4663 // Get a reference to the stack pointer.
4664 SDValue OldSP = DAG.getCopyFromReg(Chain, dl: DL, Reg: SPReg, VT: MVT::i64);
4665
4666 // If we need a backchain, save it now.
4667 SDValue Backchain;
4668 if (StoreBackchain)
4669 Backchain = DAG.getLoad(VT: MVT::i64, dl: DL, Chain, Ptr: getBackchainAddress(SP: OldSP, DAG),
4670 PtrInfo: MachinePointerInfo());
4671
4672 // Add extra space for alignment if needed.
4673 if (ExtraAlignSpace)
4674 NeededSpace = DAG.getNode(Opcode: ISD::ADD, DL, VT: MVT::i64, N1: NeededSpace,
4675 N2: DAG.getConstant(Val: ExtraAlignSpace, DL, VT: MVT::i64));
4676
4677 // Get the new stack pointer value.
4678 SDValue NewSP;
4679 if (hasInlineStackProbe(MF)) {
4680 NewSP = DAG.getNode(Opcode: SystemZISD::PROBED_ALLOCA, DL,
4681 VTList: DAG.getVTList(VT1: MVT::i64, VT2: MVT::Other), N1: Chain, N2: OldSP, N3: NeededSpace);
4682 Chain = NewSP.getValue(R: 1);
4683 }
4684 else {
4685 NewSP = DAG.getNode(Opcode: ISD::SUB, DL, VT: MVT::i64, N1: OldSP, N2: NeededSpace);
4686 // Copy the new stack pointer back.
4687 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: SPReg, N: NewSP);
4688 }
4689
4690 // The allocated data lives above the 160 bytes allocated for the standard
4691 // frame, plus any outgoing stack arguments. We don't know how much that
4692 // amounts to yet, so emit a special ADJDYNALLOC placeholder.
4693 SDValue ArgAdjust = DAG.getNode(Opcode: SystemZISD::ADJDYNALLOC, DL, VT: MVT::i64);
4694 SDValue Result = DAG.getNode(Opcode: ISD::ADD, DL, VT: MVT::i64, N1: NewSP, N2: ArgAdjust);
4695
4696 // Dynamically realign if needed.
4697 if (RequiredAlign > StackAlign) {
4698 Result =
4699 DAG.getNode(Opcode: ISD::ADD, DL, VT: MVT::i64, N1: Result,
4700 N2: DAG.getConstant(Val: ExtraAlignSpace, DL, VT: MVT::i64));
4701 Result =
4702 DAG.getNode(Opcode: ISD::AND, DL, VT: MVT::i64, N1: Result,
4703 N2: DAG.getConstant(Val: ~(RequiredAlign - 1), DL, VT: MVT::i64));
4704 }
4705
4706 if (StoreBackchain)
4707 Chain = DAG.getStore(Chain, dl: DL, Val: Backchain, Ptr: getBackchainAddress(SP: NewSP, DAG),
4708 PtrInfo: MachinePointerInfo());
4709
4710 SDValue Ops[2] = { Result, Chain };
4711 return DAG.getMergeValues(Ops, dl: DL);
4712}
4713
4714SDValue SystemZTargetLowering::lowerGET_DYNAMIC_AREA_OFFSET(
4715 SDValue Op, SelectionDAG &DAG) const {
4716 SDLoc DL(Op);
4717
4718 return DAG.getNode(Opcode: SystemZISD::ADJDYNALLOC, DL, VT: MVT::i64);
4719}
4720
4721SDValue SystemZTargetLowering::lowerMULH(SDValue Op,
4722 SelectionDAG &DAG,
4723 unsigned Opcode) const {
4724 EVT VT = Op.getValueType();
4725 SDLoc DL(Op);
4726 SDValue Even, Odd;
4727
4728 // This custom expander is only used on z17 and later for 64-bit types.
4729 assert(!is32Bit(VT));
4730 assert(Subtarget.hasMiscellaneousExtensions2());
4731
4732 // SystemZISD::xMUL_LOHI returns the low result in the odd register and
4733 // the high result in the even register. Return the latter.
4734 lowerGR128Binary(DAG, DL, VT, Opcode,
4735 Op0: Op.getOperand(i: 0), Op1: Op.getOperand(i: 1), Even, Odd);
4736 return Even;
4737}
4738
4739SDValue SystemZTargetLowering::lowerSMUL_LOHI(SDValue Op,
4740 SelectionDAG &DAG) const {
4741 EVT VT = Op.getValueType();
4742 SDLoc DL(Op);
4743 SDValue Ops[2];
4744 if (is32Bit(VT))
4745 // Just do a normal 64-bit multiplication and extract the results.
4746 // We define this so that it can be used for constant division.
4747 lowerMUL_LOHI32(DAG, DL, Extend: ISD::SIGN_EXTEND, Op0: Op.getOperand(i: 0),
4748 Op1: Op.getOperand(i: 1), Hi&: Ops[1], Lo&: Ops[0]);
4749 else if (Subtarget.hasMiscellaneousExtensions2())
4750 // SystemZISD::SMUL_LOHI returns the low result in the odd register and
4751 // the high result in the even register. ISD::SMUL_LOHI is defined to
4752 // return the low half first, so the results are in reverse order.
4753 lowerGR128Binary(DAG, DL, VT, Opcode: SystemZISD::SMUL_LOHI,
4754 Op0: Op.getOperand(i: 0), Op1: Op.getOperand(i: 1), Even&: Ops[1], Odd&: Ops[0]);
4755 else {
4756 // Do a full 128-bit multiplication based on SystemZISD::UMUL_LOHI:
4757 //
4758 // (ll * rl) + ((lh * rl) << 64) + ((ll * rh) << 64)
4759 //
4760 // but using the fact that the upper halves are either all zeros
4761 // or all ones:
4762 //
4763 // (ll * rl) - ((lh & rl) << 64) - ((ll & rh) << 64)
4764 //
4765 // and grouping the right terms together since they are quicker than the
4766 // multiplication:
4767 //
4768 // (ll * rl) - (((lh & rl) + (ll & rh)) << 64)
4769 SDValue C63 = DAG.getConstant(Val: 63, DL, VT: MVT::i64);
4770 SDValue LL = Op.getOperand(i: 0);
4771 SDValue RL = Op.getOperand(i: 1);
4772 SDValue LH = DAG.getNode(Opcode: ISD::SRA, DL, VT, N1: LL, N2: C63);
4773 SDValue RH = DAG.getNode(Opcode: ISD::SRA, DL, VT, N1: RL, N2: C63);
4774 // SystemZISD::UMUL_LOHI returns the low result in the odd register and
4775 // the high result in the even register. ISD::SMUL_LOHI is defined to
4776 // return the low half first, so the results are in reverse order.
4777 lowerGR128Binary(DAG, DL, VT, Opcode: SystemZISD::UMUL_LOHI,
4778 Op0: LL, Op1: RL, Even&: Ops[1], Odd&: Ops[0]);
4779 SDValue NegLLTimesRH = DAG.getNode(Opcode: ISD::AND, DL, VT, N1: LL, N2: RH);
4780 SDValue NegLHTimesRL = DAG.getNode(Opcode: ISD::AND, DL, VT, N1: LH, N2: RL);
4781 SDValue NegSum = DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: NegLLTimesRH, N2: NegLHTimesRL);
4782 Ops[1] = DAG.getNode(Opcode: ISD::SUB, DL, VT, N1: Ops[1], N2: NegSum);
4783 }
4784 return DAG.getMergeValues(Ops, dl: DL);
4785}
4786
4787SDValue SystemZTargetLowering::lowerUMUL_LOHI(SDValue Op,
4788 SelectionDAG &DAG) const {
4789 EVT VT = Op.getValueType();
4790 SDLoc DL(Op);
4791 SDValue Ops[2];
4792 if (is32Bit(VT))
4793 // Just do a normal 64-bit multiplication and extract the results.
4794 // We define this so that it can be used for constant division.
4795 lowerMUL_LOHI32(DAG, DL, Extend: ISD::ZERO_EXTEND, Op0: Op.getOperand(i: 0),
4796 Op1: Op.getOperand(i: 1), Hi&: Ops[1], Lo&: Ops[0]);
4797 else
4798 // SystemZISD::UMUL_LOHI returns the low result in the odd register and
4799 // the high result in the even register. ISD::UMUL_LOHI is defined to
4800 // return the low half first, so the results are in reverse order.
4801 lowerGR128Binary(DAG, DL, VT, Opcode: SystemZISD::UMUL_LOHI,
4802 Op0: Op.getOperand(i: 0), Op1: Op.getOperand(i: 1), Even&: Ops[1], Odd&: Ops[0]);
4803 return DAG.getMergeValues(Ops, dl: DL);
4804}
4805
4806SDValue SystemZTargetLowering::lowerSDIVREM(SDValue Op,
4807 SelectionDAG &DAG) const {
4808 SDValue Op0 = Op.getOperand(i: 0);
4809 SDValue Op1 = Op.getOperand(i: 1);
4810 EVT VT = Op.getValueType();
4811 SDLoc DL(Op);
4812
4813 // We use DSGF for 32-bit division. This means the first operand must
4814 // always be 64-bit, and the second operand should be 32-bit whenever
4815 // that is possible, to improve performance.
4816 if (is32Bit(VT))
4817 Op0 = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL, VT: MVT::i64, Operand: Op0);
4818 else if (DAG.ComputeNumSignBits(Op: Op1) > 32)
4819 Op1 = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: MVT::i32, Operand: Op1);
4820
4821 // DSG(F) returns the remainder in the even register and the
4822 // quotient in the odd register.
4823 SDValue Ops[2];
4824 lowerGR128Binary(DAG, DL, VT, Opcode: SystemZISD::SDIVREM, Op0, Op1, Even&: Ops[1], Odd&: Ops[0]);
4825 return DAG.getMergeValues(Ops, dl: DL);
4826}
4827
4828SDValue SystemZTargetLowering::lowerUDIVREM(SDValue Op,
4829 SelectionDAG &DAG) const {
4830 EVT VT = Op.getValueType();
4831 SDLoc DL(Op);
4832
4833 // DL(G) returns the remainder in the even register and the
4834 // quotient in the odd register.
4835 SDValue Ops[2];
4836 lowerGR128Binary(DAG, DL, VT, Opcode: SystemZISD::UDIVREM,
4837 Op0: Op.getOperand(i: 0), Op1: Op.getOperand(i: 1), Even&: Ops[1], Odd&: Ops[0]);
4838 return DAG.getMergeValues(Ops, dl: DL);
4839}
4840
4841SDValue SystemZTargetLowering::lowerOR(SDValue Op, SelectionDAG &DAG) const {
4842 assert(Op.getValueType() == MVT::i64 && "Should be 64-bit operation");
4843
4844 // Get the known-zero masks for each operand.
4845 SDValue Ops[] = {Op.getOperand(i: 0), Op.getOperand(i: 1)};
4846 KnownBits Known[2] = {DAG.computeKnownBits(Op: Ops[0]),
4847 DAG.computeKnownBits(Op: Ops[1])};
4848
4849 // See if the upper 32 bits of one operand and the lower 32 bits of the
4850 // other are known zero. They are the low and high operands respectively.
4851 uint64_t Masks[] = { Known[0].Zero.getZExtValue(),
4852 Known[1].Zero.getZExtValue() };
4853 unsigned High, Low;
4854 if ((Masks[0] >> 32) == 0xffffffff && uint32_t(Masks[1]) == 0xffffffff)
4855 High = 1, Low = 0;
4856 else if ((Masks[1] >> 32) == 0xffffffff && uint32_t(Masks[0]) == 0xffffffff)
4857 High = 0, Low = 1;
4858 else
4859 return Op;
4860
4861 SDValue LowOp = Ops[Low];
4862 SDValue HighOp = Ops[High];
4863
4864 // If the high part is a constant, we're better off using IILH.
4865 if (HighOp.getOpcode() == ISD::Constant)
4866 return Op;
4867
4868 // If the low part is a constant that is outside the range of LHI,
4869 // then we're better off using IILF.
4870 if (LowOp.getOpcode() == ISD::Constant) {
4871 int64_t Value = int32_t(LowOp->getAsZExtVal());
4872 if (!isInt<16>(x: Value))
4873 return Op;
4874 }
4875
4876 // Check whether the high part is an AND that doesn't change the
4877 // high 32 bits and just masks out low bits. We can skip it if so.
4878 if (HighOp.getOpcode() == ISD::AND &&
4879 HighOp.getOperand(i: 1).getOpcode() == ISD::Constant) {
4880 SDValue HighOp0 = HighOp.getOperand(i: 0);
4881 uint64_t Mask = HighOp.getConstantOperandVal(i: 1);
4882 if (DAG.MaskedValueIsZero(Op: HighOp0, Mask: APInt(64, ~(Mask | 0xffffffff))))
4883 HighOp = HighOp0;
4884 }
4885
4886 // Take advantage of the fact that all GR32 operations only change the
4887 // low 32 bits by truncating Low to an i32 and inserting it directly
4888 // using a subreg. The interesting cases are those where the truncation
4889 // can be folded.
4890 SDLoc DL(Op);
4891 SDValue Low32 = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: MVT::i32, Operand: LowOp);
4892 return DAG.getTargetInsertSubreg(SRIdx: SystemZ::subreg_l32, DL,
4893 VT: MVT::i64, Operand: HighOp, Subreg: Low32);
4894}
4895
4896// Lower SADDO/SSUBO/UADDO/USUBO nodes.
4897SDValue SystemZTargetLowering::lowerXALUO(SDValue Op,
4898 SelectionDAG &DAG) const {
4899 SDNode *N = Op.getNode();
4900 SDValue LHS = N->getOperand(Num: 0);
4901 SDValue RHS = N->getOperand(Num: 1);
4902 SDLoc DL(N);
4903
4904 if (N->getValueType(ResNo: 0) == MVT::i128) {
4905 unsigned BaseOp = 0;
4906 unsigned FlagOp = 0;
4907 bool IsBorrow = false;
4908 switch (Op.getOpcode()) {
4909 default: llvm_unreachable("Unknown instruction!");
4910 case ISD::UADDO:
4911 BaseOp = ISD::ADD;
4912 FlagOp = SystemZISD::VACC;
4913 break;
4914 case ISD::USUBO:
4915 BaseOp = ISD::SUB;
4916 FlagOp = SystemZISD::VSCBI;
4917 IsBorrow = true;
4918 break;
4919 }
4920 SDValue Result = DAG.getNode(Opcode: BaseOp, DL, VT: MVT::i128, N1: LHS, N2: RHS);
4921 SDValue Flag = DAG.getNode(Opcode: FlagOp, DL, VT: MVT::i128, N1: LHS, N2: RHS);
4922 Flag = DAG.getNode(Opcode: ISD::AssertZext, DL, VT: MVT::i128, N1: Flag,
4923 N2: DAG.getValueType(MVT::i1));
4924 Flag = DAG.getZExtOrTrunc(Op: Flag, DL, VT: N->getValueType(ResNo: 1));
4925 if (IsBorrow)
4926 Flag = DAG.getNode(Opcode: ISD::XOR, DL, VT: Flag.getValueType(),
4927 N1: Flag, N2: DAG.getConstant(Val: 1, DL, VT: Flag.getValueType()));
4928 return DAG.getNode(Opcode: ISD::MERGE_VALUES, DL, VTList: N->getVTList(), N1: Result, N2: Flag);
4929 }
4930
4931 unsigned BaseOp = 0;
4932 unsigned CCValid = 0;
4933 unsigned CCMask = 0;
4934
4935 switch (Op.getOpcode()) {
4936 default: llvm_unreachable("Unknown instruction!");
4937 case ISD::SADDO:
4938 BaseOp = SystemZISD::SADDO;
4939 CCValid = SystemZ::CCMASK_ARITH;
4940 CCMask = SystemZ::CCMASK_ARITH_OVERFLOW;
4941 break;
4942 case ISD::SSUBO:
4943 BaseOp = SystemZISD::SSUBO;
4944 CCValid = SystemZ::CCMASK_ARITH;
4945 CCMask = SystemZ::CCMASK_ARITH_OVERFLOW;
4946 break;
4947 case ISD::UADDO:
4948 BaseOp = SystemZISD::UADDO;
4949 CCValid = SystemZ::CCMASK_LOGICAL;
4950 CCMask = SystemZ::CCMASK_LOGICAL_CARRY;
4951 break;
4952 case ISD::USUBO:
4953 BaseOp = SystemZISD::USUBO;
4954 CCValid = SystemZ::CCMASK_LOGICAL;
4955 CCMask = SystemZ::CCMASK_LOGICAL_BORROW;
4956 break;
4957 }
4958
4959 SDVTList VTs = DAG.getVTList(VT1: N->getValueType(ResNo: 0), VT2: MVT::i32);
4960 SDValue Result = DAG.getNode(Opcode: BaseOp, DL, VTList: VTs, N1: LHS, N2: RHS);
4961
4962 SDValue SetCC = emitSETCC(DAG, DL, CCReg: Result.getValue(R: 1), CCValid, CCMask);
4963 if (N->getValueType(ResNo: 1) == MVT::i1)
4964 SetCC = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: MVT::i1, Operand: SetCC);
4965
4966 return DAG.getNode(Opcode: ISD::MERGE_VALUES, DL, VTList: N->getVTList(), N1: Result, N2: SetCC);
4967}
4968
4969static bool isAddCarryChain(SDValue Carry) {
4970 while (Carry.getOpcode() == ISD::UADDO_CARRY &&
4971 Carry->getValueType(ResNo: 0) != MVT::i128)
4972 Carry = Carry.getOperand(i: 2);
4973 return Carry.getOpcode() == ISD::UADDO &&
4974 Carry->getValueType(ResNo: 0) != MVT::i128;
4975}
4976
4977static bool isSubBorrowChain(SDValue Carry) {
4978 while (Carry.getOpcode() == ISD::USUBO_CARRY &&
4979 Carry->getValueType(ResNo: 0) != MVT::i128)
4980 Carry = Carry.getOperand(i: 2);
4981 return Carry.getOpcode() == ISD::USUBO &&
4982 Carry->getValueType(ResNo: 0) != MVT::i128;
4983}
4984
4985// Lower UADDO_CARRY/USUBO_CARRY nodes.
4986SDValue SystemZTargetLowering::lowerUADDSUBO_CARRY(SDValue Op,
4987 SelectionDAG &DAG) const {
4988
4989 SDNode *N = Op.getNode();
4990 MVT VT = N->getSimpleValueType(ResNo: 0);
4991
4992 // Let legalize expand this if it isn't a legal type yet.
4993 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
4994 return SDValue();
4995
4996 SDValue LHS = N->getOperand(Num: 0);
4997 SDValue RHS = N->getOperand(Num: 1);
4998 SDValue Carry = Op.getOperand(i: 2);
4999 SDLoc DL(N);
5000
5001 if (VT == MVT::i128) {
5002 unsigned BaseOp = 0;
5003 unsigned FlagOp = 0;
5004 bool IsBorrow = false;
5005 switch (Op.getOpcode()) {
5006 default: llvm_unreachable("Unknown instruction!");
5007 case ISD::UADDO_CARRY:
5008 BaseOp = SystemZISD::VAC;
5009 FlagOp = SystemZISD::VACCC;
5010 break;
5011 case ISD::USUBO_CARRY:
5012 BaseOp = SystemZISD::VSBI;
5013 FlagOp = SystemZISD::VSBCBI;
5014 IsBorrow = true;
5015 break;
5016 }
5017 if (IsBorrow)
5018 Carry = DAG.getNode(Opcode: ISD::XOR, DL, VT: Carry.getValueType(),
5019 N1: Carry, N2: DAG.getConstant(Val: 1, DL, VT: Carry.getValueType()));
5020 Carry = DAG.getZExtOrTrunc(Op: Carry, DL, VT: MVT::i128);
5021 SDValue Result = DAG.getNode(Opcode: BaseOp, DL, VT: MVT::i128, N1: LHS, N2: RHS, N3: Carry);
5022 SDValue Flag = DAG.getNode(Opcode: FlagOp, DL, VT: MVT::i128, N1: LHS, N2: RHS, N3: Carry);
5023 Flag = DAG.getNode(Opcode: ISD::AssertZext, DL, VT: MVT::i128, N1: Flag,
5024 N2: DAG.getValueType(MVT::i1));
5025 Flag = DAG.getZExtOrTrunc(Op: Flag, DL, VT: N->getValueType(ResNo: 1));
5026 if (IsBorrow)
5027 Flag = DAG.getNode(Opcode: ISD::XOR, DL, VT: Flag.getValueType(),
5028 N1: Flag, N2: DAG.getConstant(Val: 1, DL, VT: Flag.getValueType()));
5029 return DAG.getNode(Opcode: ISD::MERGE_VALUES, DL, VTList: N->getVTList(), N1: Result, N2: Flag);
5030 }
5031
5032 unsigned BaseOp = 0;
5033 unsigned CCValid = 0;
5034 unsigned CCMask = 0;
5035
5036 switch (Op.getOpcode()) {
5037 default: llvm_unreachable("Unknown instruction!");
5038 case ISD::UADDO_CARRY:
5039 if (!isAddCarryChain(Carry))
5040 return SDValue();
5041
5042 BaseOp = SystemZISD::ADDCARRY;
5043 CCValid = SystemZ::CCMASK_LOGICAL;
5044 CCMask = SystemZ::CCMASK_LOGICAL_CARRY;
5045 break;
5046 case ISD::USUBO_CARRY:
5047 if (!isSubBorrowChain(Carry))
5048 return SDValue();
5049
5050 BaseOp = SystemZISD::SUBCARRY;
5051 CCValid = SystemZ::CCMASK_LOGICAL;
5052 CCMask = SystemZ::CCMASK_LOGICAL_BORROW;
5053 break;
5054 }
5055
5056 // Set the condition code from the carry flag.
5057 Carry = DAG.getNode(Opcode: SystemZISD::GET_CCMASK, DL, VT: MVT::i32, N1: Carry,
5058 N2: DAG.getConstant(Val: CCValid, DL, VT: MVT::i32),
5059 N3: DAG.getConstant(Val: CCMask, DL, VT: MVT::i32));
5060
5061 SDVTList VTs = DAG.getVTList(VT1: VT, VT2: MVT::i32);
5062 SDValue Result = DAG.getNode(Opcode: BaseOp, DL, VTList: VTs, N1: LHS, N2: RHS, N3: Carry);
5063
5064 SDValue SetCC = emitSETCC(DAG, DL, CCReg: Result.getValue(R: 1), CCValid, CCMask);
5065 if (N->getValueType(ResNo: 1) == MVT::i1)
5066 SetCC = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: MVT::i1, Operand: SetCC);
5067
5068 return DAG.getNode(Opcode: ISD::MERGE_VALUES, DL, VTList: N->getVTList(), N1: Result, N2: SetCC);
5069}
5070
5071SDValue SystemZTargetLowering::lowerCTPOP(SDValue Op,
5072 SelectionDAG &DAG) const {
5073 EVT VT = Op.getValueType();
5074 SDLoc DL(Op);
5075 Op = Op.getOperand(i: 0);
5076
5077 if (VT.getScalarSizeInBits() == 128) {
5078 Op = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: MVT::v2i64, Operand: Op);
5079 Op = DAG.getNode(Opcode: ISD::CTPOP, DL, VT: MVT::v2i64, Operand: Op);
5080 SDValue Tmp = DAG.getSplatBuildVector(VT: MVT::v2i64, DL,
5081 Op: DAG.getConstant(Val: 0, DL, VT: MVT::i64));
5082 Op = DAG.getNode(Opcode: SystemZISD::VSUM, DL, VT, N1: Op, N2: Tmp);
5083 return Op;
5084 }
5085
5086 // Handle vector types via VPOPCT.
5087 if (VT.isVector()) {
5088 Op = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: MVT::v16i8, Operand: Op);
5089 Op = DAG.getNode(Opcode: SystemZISD::POPCNT, DL, VT: MVT::v16i8, Operand: Op);
5090 switch (VT.getScalarSizeInBits()) {
5091 case 8:
5092 break;
5093 case 16: {
5094 Op = DAG.getNode(Opcode: ISD::BITCAST, DL, VT, Operand: Op);
5095 SDValue Shift = DAG.getConstant(Val: 8, DL, VT: MVT::i32);
5096 SDValue Tmp = DAG.getNode(Opcode: SystemZISD::VSHL_BY_SCALAR, DL, VT, N1: Op, N2: Shift);
5097 Op = DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: Op, N2: Tmp);
5098 Op = DAG.getNode(Opcode: SystemZISD::VSRL_BY_SCALAR, DL, VT, N1: Op, N2: Shift);
5099 break;
5100 }
5101 case 32: {
5102 SDValue Tmp = DAG.getSplatBuildVector(VT: MVT::v16i8, DL,
5103 Op: DAG.getConstant(Val: 0, DL, VT: MVT::i32));
5104 Op = DAG.getNode(Opcode: SystemZISD::VSUM, DL, VT, N1: Op, N2: Tmp);
5105 break;
5106 }
5107 case 64: {
5108 SDValue Tmp = DAG.getSplatBuildVector(VT: MVT::v16i8, DL,
5109 Op: DAG.getConstant(Val: 0, DL, VT: MVT::i32));
5110 Op = DAG.getNode(Opcode: SystemZISD::VSUM, DL, VT: MVT::v4i32, N1: Op, N2: Tmp);
5111 Op = DAG.getNode(Opcode: SystemZISD::VSUM, DL, VT, N1: Op, N2: Tmp);
5112 break;
5113 }
5114 default:
5115 llvm_unreachable("Unexpected type");
5116 }
5117 return Op;
5118 }
5119
5120 // Get the known-zero mask for the operand.
5121 KnownBits Known = DAG.computeKnownBits(Op);
5122 unsigned NumSignificantBits = Known.getMaxValue().getActiveBits();
5123 if (NumSignificantBits == 0)
5124 return DAG.getConstant(Val: 0, DL, VT);
5125
5126 // Skip known-zero high parts of the operand.
5127 int64_t OrigBitSize = VT.getSizeInBits();
5128 int64_t BitSize = llvm::bit_ceil(Value: NumSignificantBits);
5129 BitSize = std::min(a: BitSize, b: OrigBitSize);
5130
5131 // The POPCNT instruction counts the number of bits in each byte.
5132 Op = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: MVT::i64, Operand: Op);
5133 Op = DAG.getNode(Opcode: SystemZISD::POPCNT, DL, VT: MVT::i64, Operand: Op);
5134 Op = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT, Operand: Op);
5135
5136 // Add up per-byte counts in a binary tree. All bits of Op at
5137 // position larger than BitSize remain zero throughout.
5138 for (int64_t I = BitSize / 2; I >= 8; I = I / 2) {
5139 SDValue Tmp = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: Op, N2: DAG.getConstant(Val: I, DL, VT));
5140 if (BitSize != OrigBitSize)
5141 Tmp = DAG.getNode(Opcode: ISD::AND, DL, VT, N1: Tmp,
5142 N2: DAG.getConstant(Val: ((uint64_t)1 << BitSize) - 1, DL, VT));
5143 Op = DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: Op, N2: Tmp);
5144 }
5145
5146 // Extract overall result from high byte.
5147 if (BitSize > 8)
5148 Op = DAG.getNode(Opcode: ISD::SRL, DL, VT, N1: Op,
5149 N2: DAG.getConstant(Val: BitSize - 8, DL, VT));
5150
5151 return Op;
5152}
5153
5154SDValue SystemZTargetLowering::lowerATOMIC_FENCE(SDValue Op,
5155 SelectionDAG &DAG) const {
5156 SDLoc DL(Op);
5157 AtomicOrdering FenceOrdering =
5158 static_cast<AtomicOrdering>(Op.getConstantOperandVal(i: 1));
5159 SyncScope::ID FenceSSID =
5160 static_cast<SyncScope::ID>(Op.getConstantOperandVal(i: 2));
5161
5162 // The only fence that needs an instruction is a sequentially-consistent
5163 // cross-thread fence.
5164 if (FenceOrdering == AtomicOrdering::SequentiallyConsistent &&
5165 FenceSSID == SyncScope::System) {
5166 return SDValue(DAG.getMachineNode(Opcode: SystemZ::Serialize, dl: DL, VT: MVT::Other,
5167 Op1: Op.getOperand(i: 0)),
5168 0);
5169 }
5170
5171 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
5172 return DAG.getNode(Opcode: ISD::MEMBARRIER, DL, VT: MVT::Other, Operand: Op.getOperand(i: 0));
5173}
5174
5175SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
5176 SelectionDAG &DAG) const {
5177 EVT RegVT = Op.getValueType();
5178 if (RegVT.getSizeInBits() == 128)
5179 return lowerATOMIC_LDST_I128(Op, DAG);
5180 return lowerLoadF16(Op, DAG);
5181}
5182
5183SDValue SystemZTargetLowering::lowerATOMIC_STORE(SDValue Op,
5184 SelectionDAG &DAG) const {
5185 auto *Node = cast<AtomicSDNode>(Val: Op.getNode());
5186 if (Node->getMemoryVT().getSizeInBits() == 128)
5187 return lowerATOMIC_LDST_I128(Op, DAG);
5188 return lowerStoreF16(Op, DAG);
5189}
5190
5191SDValue SystemZTargetLowering::lowerATOMIC_LDST_I128(SDValue Op,
5192 SelectionDAG &DAG) const {
5193 auto *Node = cast<AtomicSDNode>(Val: Op.getNode());
5194 assert(
5195 (Node->getMemoryVT() == MVT::i128 || Node->getMemoryVT() == MVT::f128) &&
5196 "Only custom lowering i128 or f128.");
5197 // Use same code to handle both legal and non-legal i128 types.
5198 SmallVector<SDValue, 2> Results;
5199 LowerOperationWrapper(N: Node, Results, DAG);
5200 return DAG.getMergeValues(Ops: Results, dl: SDLoc(Op));
5201}
5202
5203// Prepare for a Compare And Swap for a subword operation. This needs to be
5204// done in memory with 4 bytes at natural alignment.
5205static void getCSAddressAndShifts(SDValue Addr, SelectionDAG &DAG, SDLoc DL,
5206 SDValue &AlignedAddr, SDValue &BitShift,
5207 SDValue &NegBitShift) {
5208 EVT PtrVT = Addr.getValueType();
5209 EVT WideVT = MVT::i32;
5210
5211 // Get the address of the containing word.
5212 AlignedAddr = DAG.getNode(Opcode: ISD::AND, DL, VT: PtrVT, N1: Addr,
5213 N2: DAG.getSignedConstant(Val: -4, DL, VT: PtrVT));
5214
5215 // Get the number of bits that the word must be rotated left in order
5216 // to bring the field to the top bits of a GR32.
5217 BitShift = DAG.getNode(Opcode: ISD::SHL, DL, VT: PtrVT, N1: Addr,
5218 N2: DAG.getConstant(Val: 3, DL, VT: PtrVT));
5219 BitShift = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: WideVT, Operand: BitShift);
5220
5221 // Get the complementing shift amount, for rotating a field in the top
5222 // bits back to its proper position.
5223 NegBitShift = DAG.getNode(Opcode: ISD::SUB, DL, VT: WideVT,
5224 N1: DAG.getConstant(Val: 0, DL, VT: WideVT), N2: BitShift);
5225
5226}
5227
5228// Op is an 8-, 16-bit or 32-bit ATOMIC_LOAD_* operation. Lower the first
5229// two into the fullword ATOMIC_LOADW_* operation given by Opcode.
5230SDValue SystemZTargetLowering::lowerATOMIC_LOAD_OP(SDValue Op,
5231 SelectionDAG &DAG,
5232 unsigned Opcode) const {
5233 auto *Node = cast<AtomicSDNode>(Val: Op.getNode());
5234
5235 // 32-bit operations need no special handling.
5236 EVT NarrowVT = Node->getMemoryVT();
5237 EVT WideVT = MVT::i32;
5238 if (NarrowVT == WideVT)
5239 return Op;
5240
5241 int64_t BitSize = NarrowVT.getSizeInBits();
5242 SDValue ChainIn = Node->getChain();
5243 SDValue Addr = Node->getBasePtr();
5244 SDValue Src2 = Node->getVal();
5245 MachineMemOperand *MMO = Node->getMemOperand();
5246 SDLoc DL(Node);
5247
5248 // Convert atomic subtracts of constants into additions.
5249 if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
5250 if (auto *Const = dyn_cast<ConstantSDNode>(Val&: Src2)) {
5251 Opcode = SystemZISD::ATOMIC_LOADW_ADD;
5252 Src2 = DAG.getSignedConstant(Val: -Const->getSExtValue(), DL,
5253 VT: Src2.getValueType());
5254 }
5255
5256 SDValue AlignedAddr, BitShift, NegBitShift;
5257 getCSAddressAndShifts(Addr, DAG, DL, AlignedAddr, BitShift, NegBitShift);
5258
5259 // Extend the source operand to 32 bits and prepare it for the inner loop.
5260 // ATOMIC_SWAPW uses RISBG to rotate the field left, but all other
5261 // operations require the source to be shifted in advance. (This shift
5262 // can be folded if the source is constant.) For AND and NAND, the lower
5263 // bits must be set, while for other opcodes they should be left clear.
5264 if (Opcode != SystemZISD::ATOMIC_SWAPW)
5265 Src2 = DAG.getNode(Opcode: ISD::SHL, DL, VT: WideVT, N1: Src2,
5266 N2: DAG.getConstant(Val: 32 - BitSize, DL, VT: WideVT));
5267 if (Opcode == SystemZISD::ATOMIC_LOADW_AND ||
5268 Opcode == SystemZISD::ATOMIC_LOADW_NAND)
5269 Src2 = DAG.getNode(Opcode: ISD::OR, DL, VT: WideVT, N1: Src2,
5270 N2: DAG.getConstant(Val: uint32_t(-1) >> BitSize, DL, VT: WideVT));
5271
5272 // Construct the ATOMIC_LOADW_* node.
5273 SDVTList VTList = DAG.getVTList(VT1: WideVT, VT2: MVT::Other);
5274 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
5275 DAG.getConstant(Val: BitSize, DL, VT: WideVT) };
5276 SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, dl: DL, VTList, Ops,
5277 MemVT: NarrowVT, MMO);
5278
5279 // Rotate the result of the final CS so that the field is in the lower
5280 // bits of a GR32, then truncate it.
5281 SDValue ResultShift = DAG.getNode(Opcode: ISD::ADD, DL, VT: WideVT, N1: BitShift,
5282 N2: DAG.getConstant(Val: BitSize, DL, VT: WideVT));
5283 SDValue Result = DAG.getNode(Opcode: ISD::ROTL, DL, VT: WideVT, N1: AtomicOp, N2: ResultShift);
5284
5285 SDValue RetOps[2] = { Result, AtomicOp.getValue(R: 1) };
5286 return DAG.getMergeValues(Ops: RetOps, dl: DL);
5287}
5288
5289// Op is an ATOMIC_LOAD_SUB operation. Lower 8- and 16-bit operations into
5290// ATOMIC_LOADW_SUBs and convert 32- and 64-bit operations into additions.
5291SDValue SystemZTargetLowering::lowerATOMIC_LOAD_SUB(SDValue Op,
5292 SelectionDAG &DAG) const {
5293 auto *Node = cast<AtomicSDNode>(Val: Op.getNode());
5294 EVT MemVT = Node->getMemoryVT();
5295 if (MemVT == MVT::i32 || MemVT == MVT::i64) {
5296 // A full-width operation: negate and use LAA(G).
5297 assert(Op.getValueType() == MemVT && "Mismatched VTs");
5298 assert(Subtarget.hasInterlockedAccess1() &&
5299 "Should have been expanded by AtomicExpand pass.");
5300 SDValue Src2 = Node->getVal();
5301 SDLoc DL(Src2);
5302 SDValue NegSrc2 =
5303 DAG.getNode(Opcode: ISD::SUB, DL, VT: MemVT, N1: DAG.getConstant(Val: 0, DL, VT: MemVT), N2: Src2);
5304 return DAG.getAtomic(Opcode: ISD::ATOMIC_LOAD_ADD, dl: DL, MemVT,
5305 Chain: Node->getChain(), Ptr: Node->getBasePtr(), Val: NegSrc2,
5306 MMO: Node->getMemOperand());
5307 }
5308
5309 return lowerATOMIC_LOAD_OP(Op, DAG, Opcode: SystemZISD::ATOMIC_LOADW_SUB);
5310}
5311
5312// Lower 8/16/32/64-bit ATOMIC_CMP_SWAP_WITH_SUCCESS node.
5313SDValue SystemZTargetLowering::lowerATOMIC_CMP_SWAP(SDValue Op,
5314 SelectionDAG &DAG) const {
5315 auto *Node = cast<AtomicSDNode>(Val: Op.getNode());
5316 SDValue ChainIn = Node->getOperand(Num: 0);
5317 SDValue Addr = Node->getOperand(Num: 1);
5318 SDValue CmpVal = Node->getOperand(Num: 2);
5319 SDValue SwapVal = Node->getOperand(Num: 3);
5320 MachineMemOperand *MMO = Node->getMemOperand();
5321 SDLoc DL(Node);
5322
5323 if (Node->getMemoryVT() == MVT::i128) {
5324 // Use same code to handle both legal and non-legal i128 types.
5325 SmallVector<SDValue, 3> Results;
5326 LowerOperationWrapper(N: Node, Results, DAG);
5327 return DAG.getMergeValues(Ops: Results, dl: DL);
5328 }
5329
5330 // We have native support for 32-bit and 64-bit compare and swap, but we
5331 // still need to expand extracting the "success" result from the CC.
5332 EVT NarrowVT = Node->getMemoryVT();
5333 EVT WideVT = NarrowVT == MVT::i64 ? MVT::i64 : MVT::i32;
5334 if (NarrowVT == WideVT) {
5335 SDVTList Tys = DAG.getVTList(VT1: WideVT, VT2: MVT::i32, VT3: MVT::Other);
5336 SDValue Ops[] = { ChainIn, Addr, CmpVal, SwapVal };
5337 SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode: SystemZISD::ATOMIC_CMP_SWAP,
5338 dl: DL, VTList: Tys, Ops, MemVT: NarrowVT, MMO);
5339 SDValue Success = emitSETCC(DAG, DL, CCReg: AtomicOp.getValue(R: 1),
5340 CCValid: SystemZ::CCMASK_CS, CCMask: SystemZ::CCMASK_CS_EQ);
5341
5342 DAG.ReplaceAllUsesOfValueWith(From: Op.getValue(R: 0), To: AtomicOp.getValue(R: 0));
5343 DAG.ReplaceAllUsesOfValueWith(From: Op.getValue(R: 1), To: Success);
5344 DAG.ReplaceAllUsesOfValueWith(From: Op.getValue(R: 2), To: AtomicOp.getValue(R: 2));
5345 return SDValue();
5346 }
5347
5348 // Convert 8-bit and 16-bit compare and swap to a loop, implemented
5349 // via a fullword ATOMIC_CMP_SWAPW operation.
5350 int64_t BitSize = NarrowVT.getSizeInBits();
5351
5352 SDValue AlignedAddr, BitShift, NegBitShift;
5353 getCSAddressAndShifts(Addr, DAG, DL, AlignedAddr, BitShift, NegBitShift);
5354
5355 // Construct the ATOMIC_CMP_SWAPW node.
5356 SDVTList VTList = DAG.getVTList(VT1: WideVT, VT2: MVT::i32, VT3: MVT::Other);
5357 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
5358 NegBitShift, DAG.getConstant(Val: BitSize, DL, VT: WideVT) };
5359 SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode: SystemZISD::ATOMIC_CMP_SWAPW, dl: DL,
5360 VTList, Ops, MemVT: NarrowVT, MMO);
5361 SDValue Success = emitSETCC(DAG, DL, CCReg: AtomicOp.getValue(R: 1),
5362 CCValid: SystemZ::CCMASK_ICMP, CCMask: SystemZ::CCMASK_CMP_EQ);
5363
5364 // emitAtomicCmpSwapW() will zero extend the result (original value).
5365 SDValue OrigVal = DAG.getNode(Opcode: ISD::AssertZext, DL, VT: WideVT, N1: AtomicOp.getValue(R: 0),
5366 N2: DAG.getValueType(NarrowVT));
5367 DAG.ReplaceAllUsesOfValueWith(From: Op.getValue(R: 0), To: OrigVal);
5368 DAG.ReplaceAllUsesOfValueWith(From: Op.getValue(R: 1), To: Success);
5369 DAG.ReplaceAllUsesOfValueWith(From: Op.getValue(R: 2), To: AtomicOp.getValue(R: 2));
5370 return SDValue();
5371}
5372
5373MachineMemOperand::Flags
5374SystemZTargetLowering::getTargetMMOFlags(const Instruction &I) const {
5375 // Because of how we convert atomic_load and atomic_store to normal loads and
5376 // stores in the DAG, we need to ensure that the MMOs are marked volatile
5377 // since DAGCombine hasn't been updated to account for atomic, but non
5378 // volatile loads. (See D57601)
5379 if (auto *SI = dyn_cast<StoreInst>(Val: &I))
5380 if (SI->isAtomic())
5381 return MachineMemOperand::MOVolatile;
5382 if (auto *LI = dyn_cast<LoadInst>(Val: &I))
5383 if (LI->isAtomic())
5384 return MachineMemOperand::MOVolatile;
5385 if (auto *AI = dyn_cast<AtomicRMWInst>(Val: &I))
5386 if (AI->isAtomic())
5387 return MachineMemOperand::MOVolatile;
5388 if (auto *AI = dyn_cast<AtomicCmpXchgInst>(Val: &I))
5389 if (AI->isAtomic())
5390 return MachineMemOperand::MOVolatile;
5391 return MachineMemOperand::MONone;
5392}
5393
5394SDValue SystemZTargetLowering::lowerSTACKSAVE(SDValue Op,
5395 SelectionDAG &DAG) const {
5396 MachineFunction &MF = DAG.getMachineFunction();
5397 auto *Regs = Subtarget.getSpecialRegisters();
5398 if (MF.getFunction().getCallingConv() == CallingConv::GHC)
5399 report_fatal_error(reason: "Variable-sized stack allocations are not supported "
5400 "in GHC calling convention");
5401 return DAG.getCopyFromReg(Chain: Op.getOperand(i: 0), dl: SDLoc(Op),
5402 Reg: Regs->getStackPointerRegister(), VT: Op.getValueType());
5403}
5404
5405SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op,
5406 SelectionDAG &DAG) const {
5407 MachineFunction &MF = DAG.getMachineFunction();
5408 auto *Regs = Subtarget.getSpecialRegisters();
5409 bool StoreBackchain = MF.getSubtarget<SystemZSubtarget>().hasBackChain();
5410
5411 if (MF.getFunction().getCallingConv() == CallingConv::GHC)
5412 report_fatal_error(reason: "Variable-sized stack allocations are not supported "
5413 "in GHC calling convention");
5414
5415 SDValue Chain = Op.getOperand(i: 0);
5416 SDValue NewSP = Op.getOperand(i: 1);
5417 SDValue Backchain;
5418 SDLoc DL(Op);
5419
5420 if (StoreBackchain) {
5421 SDValue OldSP = DAG.getCopyFromReg(
5422 Chain, dl: DL, Reg: Regs->getStackPointerRegister(), VT: MVT::i64);
5423 Backchain = DAG.getLoad(VT: MVT::i64, dl: DL, Chain, Ptr: getBackchainAddress(SP: OldSP, DAG),
5424 PtrInfo: MachinePointerInfo());
5425 }
5426
5427 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: Regs->getStackPointerRegister(), N: NewSP);
5428
5429 if (StoreBackchain)
5430 Chain = DAG.getStore(Chain, dl: DL, Val: Backchain, Ptr: getBackchainAddress(SP: NewSP, DAG),
5431 PtrInfo: MachinePointerInfo());
5432
5433 return Chain;
5434}
5435
5436SDValue SystemZTargetLowering::lowerPREFETCH(SDValue Op,
5437 SelectionDAG &DAG) const {
5438 bool IsData = Op.getConstantOperandVal(i: 4);
5439 if (!IsData)
5440 // Just preserve the chain.
5441 return Op.getOperand(i: 0);
5442
5443 SDLoc DL(Op);
5444 bool IsWrite = Op.getConstantOperandVal(i: 2);
5445 unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ;
5446 auto *Node = cast<MemIntrinsicSDNode>(Val: Op.getNode());
5447 SDValue Ops[] = {Op.getOperand(i: 0), DAG.getTargetConstant(Val: Code, DL, VT: MVT::i32),
5448 Op.getOperand(i: 1)};
5449 return DAG.getMemIntrinsicNode(Opcode: SystemZISD::PREFETCH, dl: DL,
5450 VTList: Node->getVTList(), Ops,
5451 MemVT: Node->getMemoryVT(), MMO: Node->getMemOperand());
5452}
5453
5454SDValue
5455SystemZTargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
5456 SelectionDAG &DAG) const {
5457 unsigned Opcode, CCValid;
5458 if (isIntrinsicWithCCAndChain(Op, Opcode, CCValid)) {
5459 assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
5460 SDNode *Node = emitIntrinsicWithCCAndChain(DAG, Op, Opcode);
5461 SDValue CC = getCCResult(DAG, CCReg: SDValue(Node, 0));
5462 DAG.ReplaceAllUsesOfValueWith(From: SDValue(Op.getNode(), 0), To: CC);
5463 return SDValue();
5464 }
5465
5466 return SDValue();
5467}
5468
5469SDValue
5470SystemZTargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
5471 SelectionDAG &DAG) const {
5472 unsigned Opcode, CCValid;
5473 if (isIntrinsicWithCC(Op, Opcode, CCValid)) {
5474 SDNode *Node = emitIntrinsicWithCC(DAG, Op, Opcode);
5475 if (Op->getNumValues() == 1)
5476 return getCCResult(DAG, CCReg: SDValue(Node, 0));
5477 assert(Op->getNumValues() == 2 && "Expected a CC and non-CC result");
5478 return DAG.getNode(Opcode: ISD::MERGE_VALUES, DL: SDLoc(Op), VTList: Op->getVTList(),
5479 N1: SDValue(Node, 0), N2: getCCResult(DAG, CCReg: SDValue(Node, 1)));
5480 }
5481
5482 unsigned Id = Op.getConstantOperandVal(i: 0);
5483 switch (Id) {
5484 case Intrinsic::thread_pointer:
5485 return lowerThreadPointer(DL: SDLoc(Op), DAG);
5486
5487 case Intrinsic::s390_vpdi:
5488 return DAG.getNode(Opcode: SystemZISD::PERMUTE_DWORDS, DL: SDLoc(Op), VT: Op.getValueType(),
5489 N1: Op.getOperand(i: 1), N2: Op.getOperand(i: 2), N3: Op.getOperand(i: 3));
5490
5491 case Intrinsic::s390_vperm:
5492 return DAG.getNode(Opcode: SystemZISD::PERMUTE, DL: SDLoc(Op), VT: Op.getValueType(),
5493 N1: Op.getOperand(i: 1), N2: Op.getOperand(i: 2), N3: Op.getOperand(i: 3));
5494
5495 case Intrinsic::s390_vuphb:
5496 case Intrinsic::s390_vuphh:
5497 case Intrinsic::s390_vuphf:
5498 case Intrinsic::s390_vuphg:
5499 return DAG.getNode(Opcode: SystemZISD::UNPACK_HIGH, DL: SDLoc(Op), VT: Op.getValueType(),
5500 Operand: Op.getOperand(i: 1));
5501
5502 case Intrinsic::s390_vuplhb:
5503 case Intrinsic::s390_vuplhh:
5504 case Intrinsic::s390_vuplhf:
5505 case Intrinsic::s390_vuplhg:
5506 return DAG.getNode(Opcode: SystemZISD::UNPACKL_HIGH, DL: SDLoc(Op), VT: Op.getValueType(),
5507 Operand: Op.getOperand(i: 1));
5508
5509 case Intrinsic::s390_vuplb:
5510 case Intrinsic::s390_vuplhw:
5511 case Intrinsic::s390_vuplf:
5512 case Intrinsic::s390_vuplg:
5513 return DAG.getNode(Opcode: SystemZISD::UNPACK_LOW, DL: SDLoc(Op), VT: Op.getValueType(),
5514 Operand: Op.getOperand(i: 1));
5515
5516 case Intrinsic::s390_vupllb:
5517 case Intrinsic::s390_vupllh:
5518 case Intrinsic::s390_vupllf:
5519 case Intrinsic::s390_vupllg:
5520 return DAG.getNode(Opcode: SystemZISD::UNPACKL_LOW, DL: SDLoc(Op), VT: Op.getValueType(),
5521 Operand: Op.getOperand(i: 1));
5522
5523 case Intrinsic::s390_vsumb:
5524 case Intrinsic::s390_vsumh:
5525 case Intrinsic::s390_vsumgh:
5526 case Intrinsic::s390_vsumgf:
5527 case Intrinsic::s390_vsumqf:
5528 case Intrinsic::s390_vsumqg:
5529 return DAG.getNode(Opcode: SystemZISD::VSUM, DL: SDLoc(Op), VT: Op.getValueType(),
5530 N1: Op.getOperand(i: 1), N2: Op.getOperand(i: 2));
5531
5532 case Intrinsic::s390_vaq:
5533 return DAG.getNode(Opcode: ISD::ADD, DL: SDLoc(Op), VT: Op.getValueType(),
5534 N1: Op.getOperand(i: 1), N2: Op.getOperand(i: 2));
5535 case Intrinsic::s390_vaccb:
5536 case Intrinsic::s390_vacch:
5537 case Intrinsic::s390_vaccf:
5538 case Intrinsic::s390_vaccg:
5539 case Intrinsic::s390_vaccq:
5540 return DAG.getNode(Opcode: SystemZISD::VACC, DL: SDLoc(Op), VT: Op.getValueType(),
5541 N1: Op.getOperand(i: 1), N2: Op.getOperand(i: 2));
5542 case Intrinsic::s390_vacq:
5543 return DAG.getNode(Opcode: SystemZISD::VAC, DL: SDLoc(Op), VT: Op.getValueType(),
5544 N1: Op.getOperand(i: 1), N2: Op.getOperand(i: 2), N3: Op.getOperand(i: 3));
5545 case Intrinsic::s390_vacccq:
5546 return DAG.getNode(Opcode: SystemZISD::VACCC, DL: SDLoc(Op), VT: Op.getValueType(),
5547 N1: Op.getOperand(i: 1), N2: Op.getOperand(i: 2), N3: Op.getOperand(i: 3));
5548
5549 case Intrinsic::s390_vsq:
5550 return DAG.getNode(Opcode: ISD::SUB, DL: SDLoc(Op), VT: Op.getValueType(),
5551 N1: Op.getOperand(i: 1), N2: Op.getOperand(i: 2));
5552 case Intrinsic::s390_vscbib:
5553 case Intrinsic::s390_vscbih:
5554 case Intrinsic::s390_vscbif:
5555 case Intrinsic::s390_vscbig:
5556 case Intrinsic::s390_vscbiq:
5557 return DAG.getNode(Opcode: SystemZISD::VSCBI, DL: SDLoc(Op), VT: Op.getValueType(),
5558 N1: Op.getOperand(i: 1), N2: Op.getOperand(i: 2));
5559 case Intrinsic::s390_vsbiq:
5560 return DAG.getNode(Opcode: SystemZISD::VSBI, DL: SDLoc(Op), VT: Op.getValueType(),
5561 N1: Op.getOperand(i: 1), N2: Op.getOperand(i: 2), N3: Op.getOperand(i: 3));
5562 case Intrinsic::s390_vsbcbiq:
5563 return DAG.getNode(Opcode: SystemZISD::VSBCBI, DL: SDLoc(Op), VT: Op.getValueType(),
5564 N1: Op.getOperand(i: 1), N2: Op.getOperand(i: 2), N3: Op.getOperand(i: 3));
5565
5566 case Intrinsic::s390_vmhb:
5567 case Intrinsic::s390_vmhh:
5568 case Intrinsic::s390_vmhf:
5569 case Intrinsic::s390_vmhg:
5570 case Intrinsic::s390_vmhq:
5571 return DAG.getNode(Opcode: ISD::MULHS, DL: SDLoc(Op), VT: Op.getValueType(),
5572 N1: Op.getOperand(i: 1), N2: Op.getOperand(i: 2));
5573 case Intrinsic::s390_vmlhb:
5574 case Intrinsic::s390_vmlhh:
5575 case Intrinsic::s390_vmlhf:
5576 case Intrinsic::s390_vmlhg:
5577 case Intrinsic::s390_vmlhq:
5578 return DAG.getNode(Opcode: ISD::MULHU, DL: SDLoc(Op), VT: Op.getValueType(),
5579 N1: Op.getOperand(i: 1), N2: Op.getOperand(i: 2));
5580
5581 case Intrinsic::s390_vmahb:
5582 case Intrinsic::s390_vmahh:
5583 case Intrinsic::s390_vmahf:
5584 case Intrinsic::s390_vmahg:
5585 case Intrinsic::s390_vmahq:
5586 return DAG.getNode(Opcode: SystemZISD::VMAH, DL: SDLoc(Op), VT: Op.getValueType(),
5587 N1: Op.getOperand(i: 1), N2: Op.getOperand(i: 2), N3: Op.getOperand(i: 3));
5588 case Intrinsic::s390_vmalhb:
5589 case Intrinsic::s390_vmalhh:
5590 case Intrinsic::s390_vmalhf:
5591 case Intrinsic::s390_vmalhg:
5592 case Intrinsic::s390_vmalhq:
5593 return DAG.getNode(Opcode: SystemZISD::VMALH, DL: SDLoc(Op), VT: Op.getValueType(),
5594 N1: Op.getOperand(i: 1), N2: Op.getOperand(i: 2), N3: Op.getOperand(i: 3));
5595
5596 case Intrinsic::s390_vmeb:
5597 case Intrinsic::s390_vmeh:
5598 case Intrinsic::s390_vmef:
5599 case Intrinsic::s390_vmeg:
5600 return DAG.getNode(Opcode: SystemZISD::VME, DL: SDLoc(Op), VT: Op.getValueType(),
5601 N1: Op.getOperand(i: 1), N2: Op.getOperand(i: 2));
5602 case Intrinsic::s390_vmleb:
5603 case Intrinsic::s390_vmleh:
5604 case Intrinsic::s390_vmlef:
5605 case Intrinsic::s390_vmleg:
5606 return DAG.getNode(Opcode: SystemZISD::VMLE, DL: SDLoc(Op), VT: Op.getValueType(),
5607 N1: Op.getOperand(i: 1), N2: Op.getOperand(i: 2));
5608 case Intrinsic::s390_vmob:
5609 case Intrinsic::s390_vmoh:
5610 case Intrinsic::s390_vmof:
5611 case Intrinsic::s390_vmog:
5612 return DAG.getNode(Opcode: SystemZISD::VMO, DL: SDLoc(Op), VT: Op.getValueType(),
5613 N1: Op.getOperand(i: 1), N2: Op.getOperand(i: 2));
5614 case Intrinsic::s390_vmlob:
5615 case Intrinsic::s390_vmloh:
5616 case Intrinsic::s390_vmlof:
5617 case Intrinsic::s390_vmlog:
5618 return DAG.getNode(Opcode: SystemZISD::VMLO, DL: SDLoc(Op), VT: Op.getValueType(),
5619 N1: Op.getOperand(i: 1), N2: Op.getOperand(i: 2));
5620
5621 case Intrinsic::s390_vmaeb:
5622 case Intrinsic::s390_vmaeh:
5623 case Intrinsic::s390_vmaef:
5624 case Intrinsic::s390_vmaeg:
5625 return DAG.getNode(Opcode: ISD::ADD, DL: SDLoc(Op), VT: Op.getValueType(),
5626 N1: DAG.getNode(Opcode: SystemZISD::VME, DL: SDLoc(Op), VT: Op.getValueType(),
5627 N1: Op.getOperand(i: 1), N2: Op.getOperand(i: 2)),
5628 N2: Op.getOperand(i: 3));
5629 case Intrinsic::s390_vmaleb:
5630 case Intrinsic::s390_vmaleh:
5631 case Intrinsic::s390_vmalef:
5632 case Intrinsic::s390_vmaleg:
5633 return DAG.getNode(Opcode: ISD::ADD, DL: SDLoc(Op), VT: Op.getValueType(),
5634 N1: DAG.getNode(Opcode: SystemZISD::VMLE, DL: SDLoc(Op), VT: Op.getValueType(),
5635 N1: Op.getOperand(i: 1), N2: Op.getOperand(i: 2)),
5636 N2: Op.getOperand(i: 3));
5637 case Intrinsic::s390_vmaob:
5638 case Intrinsic::s390_vmaoh:
5639 case Intrinsic::s390_vmaof:
5640 case Intrinsic::s390_vmaog:
5641 return DAG.getNode(Opcode: ISD::ADD, DL: SDLoc(Op), VT: Op.getValueType(),
5642 N1: DAG.getNode(Opcode: SystemZISD::VMO, DL: SDLoc(Op), VT: Op.getValueType(),
5643 N1: Op.getOperand(i: 1), N2: Op.getOperand(i: 2)),
5644 N2: Op.getOperand(i: 3));
5645 case Intrinsic::s390_vmalob:
5646 case Intrinsic::s390_vmaloh:
5647 case Intrinsic::s390_vmalof:
5648 case Intrinsic::s390_vmalog:
5649 return DAG.getNode(Opcode: ISD::ADD, DL: SDLoc(Op), VT: Op.getValueType(),
5650 N1: DAG.getNode(Opcode: SystemZISD::VMLO, DL: SDLoc(Op), VT: Op.getValueType(),
5651 N1: Op.getOperand(i: 1), N2: Op.getOperand(i: 2)),
5652 N2: Op.getOperand(i: 3));
5653 }
5654
5655 return SDValue();
5656}
5657
5658namespace {
5659// Says that SystemZISD operation Opcode can be used to perform the equivalent
5660// of a VPERM with permute vector Bytes. If Opcode takes three operands,
5661// Operand is the constant third operand, otherwise it is the number of
5662// bytes in each element of the result.
5663struct Permute {
5664 unsigned Opcode;
5665 unsigned Operand;
5666 unsigned char Bytes[SystemZ::VectorBytes];
5667};
5668}
5669
5670static const Permute PermuteForms[] = {
5671 // VMRHG
5672 { .Opcode: SystemZISD::MERGE_HIGH, .Operand: 8,
5673 .Bytes: { 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23 } },
5674 // VMRHF
5675 { .Opcode: SystemZISD::MERGE_HIGH, .Operand: 4,
5676 .Bytes: { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
5677 // VMRHH
5678 { .Opcode: SystemZISD::MERGE_HIGH, .Operand: 2,
5679 .Bytes: { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
5680 // VMRHB
5681 { .Opcode: SystemZISD::MERGE_HIGH, .Operand: 1,
5682 .Bytes: { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
5683 // VMRLG
5684 { .Opcode: SystemZISD::MERGE_LOW, .Operand: 8,
5685 .Bytes: { 8, 9, 10, 11, 12, 13, 14, 15, 24, 25, 26, 27, 28, 29, 30, 31 } },
5686 // VMRLF
5687 { .Opcode: SystemZISD::MERGE_LOW, .Operand: 4,
5688 .Bytes: { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
5689 // VMRLH
5690 { .Opcode: SystemZISD::MERGE_LOW, .Operand: 2,
5691 .Bytes: { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
5692 // VMRLB
5693 { .Opcode: SystemZISD::MERGE_LOW, .Operand: 1,
5694 .Bytes: { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
5695 // VPKG
5696 { .Opcode: SystemZISD::PACK, .Operand: 4,
5697 .Bytes: { 4, 5, 6, 7, 12, 13, 14, 15, 20, 21, 22, 23, 28, 29, 30, 31 } },
5698 // VPKF
5699 { .Opcode: SystemZISD::PACK, .Operand: 2,
5700 .Bytes: { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
5701 // VPKH
5702 { .Opcode: SystemZISD::PACK, .Operand: 1,
5703 .Bytes: { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
5704 // VPDI V1, V2, 4 (low half of V1, high half of V2)
5705 { .Opcode: SystemZISD::PERMUTE_DWORDS, .Operand: 4,
5706 .Bytes: { 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 } },
5707 // VPDI V1, V2, 1 (high half of V1, low half of V2)
5708 { .Opcode: SystemZISD::PERMUTE_DWORDS, .Operand: 1,
5709 .Bytes: { 0, 1, 2, 3, 4, 5, 6, 7, 24, 25, 26, 27, 28, 29, 30, 31 } }
5710};
5711
5712// Called after matching a vector shuffle against a particular pattern.
5713// Both the original shuffle and the pattern have two vector operands.
5714// OpNos[0] is the operand of the original shuffle that should be used for
5715// operand 0 of the pattern, or -1 if operand 0 of the pattern can be anything.
5716// OpNos[1] is the same for operand 1 of the pattern. Resolve these -1s and
5717// set OpNo0 and OpNo1 to the shuffle operands that should actually be used
5718// for operands 0 and 1 of the pattern.
5719static bool chooseShuffleOpNos(int *OpNos, unsigned &OpNo0, unsigned &OpNo1) {
5720 if (OpNos[0] < 0) {
5721 if (OpNos[1] < 0)
5722 return false;
5723 OpNo0 = OpNo1 = OpNos[1];
5724 } else if (OpNos[1] < 0) {
5725 OpNo0 = OpNo1 = OpNos[0];
5726 } else {
5727 OpNo0 = OpNos[0];
5728 OpNo1 = OpNos[1];
5729 }
5730 return true;
5731}
5732
5733// Bytes is a VPERM-like permute vector, except that -1 is used for
5734// undefined bytes. Return true if the VPERM can be implemented using P.
5735// When returning true set OpNo0 to the VPERM operand that should be
5736// used for operand 0 of P and likewise OpNo1 for operand 1 of P.
5737//
5738// For example, if swapping the VPERM operands allows P to match, OpNo0
5739// will be 1 and OpNo1 will be 0. If instead Bytes only refers to one
5740// operand, but rewriting it to use two duplicated operands allows it to
5741// match P, then OpNo0 and OpNo1 will be the same.
5742static bool matchPermute(const SmallVectorImpl<int> &Bytes, const Permute &P,
5743 unsigned &OpNo0, unsigned &OpNo1) {
5744 int OpNos[] = { -1, -1 };
5745 for (unsigned I = 0; I < SystemZ::VectorBytes; ++I) {
5746 int Elt = Bytes[I];
5747 if (Elt >= 0) {
5748 // Make sure that the two permute vectors use the same suboperand
5749 // byte number. Only the operand numbers (the high bits) are
5750 // allowed to differ.
5751 if ((Elt ^ P.Bytes[I]) & (SystemZ::VectorBytes - 1))
5752 return false;
5753 int ModelOpNo = P.Bytes[I] / SystemZ::VectorBytes;
5754 int RealOpNo = unsigned(Elt) / SystemZ::VectorBytes;
5755 // Make sure that the operand mappings are consistent with previous
5756 // elements.
5757 if (OpNos[ModelOpNo] == 1 - RealOpNo)
5758 return false;
5759 OpNos[ModelOpNo] = RealOpNo;
5760 }
5761 }
5762 return chooseShuffleOpNos(OpNos, OpNo0, OpNo1);
5763}
5764
5765// As above, but search for a matching permute.
5766static const Permute *matchPermute(const SmallVectorImpl<int> &Bytes,
5767 unsigned &OpNo0, unsigned &OpNo1) {
5768 for (auto &P : PermuteForms)
5769 if (matchPermute(Bytes, P, OpNo0, OpNo1))
5770 return &P;
5771 return nullptr;
5772}
5773
5774// Bytes is a VPERM-like permute vector, except that -1 is used for
5775// undefined bytes. This permute is an operand of an outer permute.
5776// See whether redistributing the -1 bytes gives a shuffle that can be
5777// implemented using P. If so, set Transform to a VPERM-like permute vector
5778// that, when applied to the result of P, gives the original permute in Bytes.
5779static bool matchDoublePermute(const SmallVectorImpl<int> &Bytes,
5780 const Permute &P,
5781 SmallVectorImpl<int> &Transform) {
5782 unsigned To = 0;
5783 for (unsigned From = 0; From < SystemZ::VectorBytes; ++From) {
5784 int Elt = Bytes[From];
5785 if (Elt < 0)
5786 // Byte number From of the result is undefined.
5787 Transform[From] = -1;
5788 else {
5789 while (P.Bytes[To] != Elt) {
5790 To += 1;
5791 if (To == SystemZ::VectorBytes)
5792 return false;
5793 }
5794 Transform[From] = To;
5795 }
5796 }
5797 return true;
5798}
5799
5800// As above, but search for a matching permute.
5801static const Permute *matchDoublePermute(const SmallVectorImpl<int> &Bytes,
5802 SmallVectorImpl<int> &Transform) {
5803 for (auto &P : PermuteForms)
5804 if (matchDoublePermute(Bytes, P, Transform))
5805 return &P;
5806 return nullptr;
5807}
5808
5809// Convert the mask of the given shuffle op into a byte-level mask,
5810// as if it had type vNi8.
5811static bool getVPermMask(SDValue ShuffleOp,
5812 SmallVectorImpl<int> &Bytes) {
5813 EVT VT = ShuffleOp.getValueType();
5814 unsigned NumElements = VT.getVectorNumElements();
5815 unsigned BytesPerElement = VT.getVectorElementType().getStoreSize();
5816
5817 if (auto *VSN = dyn_cast<ShuffleVectorSDNode>(Val&: ShuffleOp)) {
5818 Bytes.resize(N: NumElements * BytesPerElement, NV: -1);
5819 for (unsigned I = 0; I < NumElements; ++I) {
5820 int Index = VSN->getMaskElt(Idx: I);
5821 if (Index >= 0)
5822 for (unsigned J = 0; J < BytesPerElement; ++J)
5823 Bytes[I * BytesPerElement + J] = Index * BytesPerElement + J;
5824 }
5825 return true;
5826 }
5827 if (SystemZISD::SPLAT == ShuffleOp.getOpcode() &&
5828 isa<ConstantSDNode>(Val: ShuffleOp.getOperand(i: 1))) {
5829 unsigned Index = ShuffleOp.getConstantOperandVal(i: 1);
5830 Bytes.resize(N: NumElements * BytesPerElement, NV: -1);
5831 for (unsigned I = 0; I < NumElements; ++I)
5832 for (unsigned J = 0; J < BytesPerElement; ++J)
5833 Bytes[I * BytesPerElement + J] = Index * BytesPerElement + J;
5834 return true;
5835 }
5836 return false;
5837}
5838
5839// Bytes is a VPERM-like permute vector, except that -1 is used for
5840// undefined bytes. See whether bytes [Start, Start + BytesPerElement) of
5841// the result come from a contiguous sequence of bytes from one input.
5842// Set Base to the selector for the first byte if so.
5843static bool getShuffleInput(const SmallVectorImpl<int> &Bytes, unsigned Start,
5844 unsigned BytesPerElement, int &Base) {
5845 Base = -1;
5846 for (unsigned I = 0; I < BytesPerElement; ++I) {
5847 if (Bytes[Start + I] >= 0) {
5848 unsigned Elem = Bytes[Start + I];
5849 if (Base < 0) {
5850 Base = Elem - I;
5851 // Make sure the bytes would come from one input operand.
5852 if (unsigned(Base) % Bytes.size() + BytesPerElement > Bytes.size())
5853 return false;
5854 } else if (unsigned(Base) != Elem - I)
5855 return false;
5856 }
5857 }
5858 return true;
5859}
5860
5861// Bytes is a VPERM-like permute vector, except that -1 is used for
5862// undefined bytes. Return true if it can be performed using VSLDB.
5863// When returning true, set StartIndex to the shift amount and OpNo0
5864// and OpNo1 to the VPERM operands that should be used as the first
5865// and second shift operand respectively.
5866static bool isShlDoublePermute(const SmallVectorImpl<int> &Bytes,
5867 unsigned &StartIndex, unsigned &OpNo0,
5868 unsigned &OpNo1) {
5869 int OpNos[] = { -1, -1 };
5870 int Shift = -1;
5871 for (unsigned I = 0; I < 16; ++I) {
5872 int Index = Bytes[I];
5873 if (Index >= 0) {
5874 int ExpectedShift = (Index - I) % SystemZ::VectorBytes;
5875 int ModelOpNo = unsigned(ExpectedShift + I) / SystemZ::VectorBytes;
5876 int RealOpNo = unsigned(Index) / SystemZ::VectorBytes;
5877 if (Shift < 0)
5878 Shift = ExpectedShift;
5879 else if (Shift != ExpectedShift)
5880 return false;
5881 // Make sure that the operand mappings are consistent with previous
5882 // elements.
5883 if (OpNos[ModelOpNo] == 1 - RealOpNo)
5884 return false;
5885 OpNos[ModelOpNo] = RealOpNo;
5886 }
5887 }
5888 StartIndex = Shift;
5889 return chooseShuffleOpNos(OpNos, OpNo0, OpNo1);
5890}
5891
5892// Create a node that performs P on operands Op0 and Op1, casting the
5893// operands to the appropriate type. The type of the result is determined by P.
5894static SDValue getPermuteNode(SelectionDAG &DAG, const SDLoc &DL,
5895 const Permute &P, SDValue Op0, SDValue Op1) {
5896 // VPDI (PERMUTE_DWORDS) always operates on v2i64s. The input
5897 // elements of a PACK are twice as wide as the outputs.
5898 unsigned InBytes = (P.Opcode == SystemZISD::PERMUTE_DWORDS ? 8 :
5899 P.Opcode == SystemZISD::PACK ? P.Operand * 2 :
5900 P.Operand);
5901 // Cast both operands to the appropriate type.
5902 MVT InVT = MVT::getVectorVT(VT: MVT::getIntegerVT(BitWidth: InBytes * 8),
5903 NumElements: SystemZ::VectorBytes / InBytes);
5904 Op0 = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: InVT, Operand: Op0);
5905 Op1 = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: InVT, Operand: Op1);
5906 SDValue Op;
5907 if (P.Opcode == SystemZISD::PERMUTE_DWORDS) {
5908 SDValue Op2 = DAG.getTargetConstant(Val: P.Operand, DL, VT: MVT::i32);
5909 Op = DAG.getNode(Opcode: SystemZISD::PERMUTE_DWORDS, DL, VT: InVT, N1: Op0, N2: Op1, N3: Op2);
5910 } else if (P.Opcode == SystemZISD::PACK) {
5911 MVT OutVT = MVT::getVectorVT(VT: MVT::getIntegerVT(BitWidth: P.Operand * 8),
5912 NumElements: SystemZ::VectorBytes / P.Operand);
5913 Op = DAG.getNode(Opcode: SystemZISD::PACK, DL, VT: OutVT, N1: Op0, N2: Op1);
5914 } else {
5915 Op = DAG.getNode(Opcode: P.Opcode, DL, VT: InVT, N1: Op0, N2: Op1);
5916 }
5917 return Op;
5918}
5919
5920static bool isZeroVector(SDValue N) {
5921 if (N->getOpcode() == ISD::BITCAST)
5922 N = N->getOperand(Num: 0);
5923 if (N->getOpcode() == ISD::SPLAT_VECTOR)
5924 if (auto *Op = dyn_cast<ConstantSDNode>(Val: N->getOperand(Num: 0)))
5925 return Op->getZExtValue() == 0;
5926 return ISD::isBuildVectorAllZeros(N: N.getNode());
5927}
5928
5929// Return the index of the zero/undef vector, or UINT32_MAX if not found.
5930static uint32_t findZeroVectorIdx(SDValue *Ops, unsigned Num) {
5931 for (unsigned I = 0; I < Num ; I++)
5932 if (isZeroVector(N: Ops[I]))
5933 return I;
5934 return UINT32_MAX;
5935}
5936
5937// Bytes is a VPERM-like permute vector, except that -1 is used for
5938// undefined bytes. Implement it on operands Ops[0] and Ops[1] using
5939// VSLDB or VPERM.
5940static SDValue getGeneralPermuteNode(SelectionDAG &DAG, const SDLoc &DL,
5941 SDValue *Ops,
5942 const SmallVectorImpl<int> &Bytes) {
5943 for (unsigned I = 0; I < 2; ++I)
5944 Ops[I] = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: MVT::v16i8, Operand: Ops[I]);
5945
5946 // First see whether VSLDB can be used.
5947 unsigned StartIndex, OpNo0, OpNo1;
5948 if (isShlDoublePermute(Bytes, StartIndex, OpNo0, OpNo1))
5949 return DAG.getNode(Opcode: SystemZISD::SHL_DOUBLE, DL, VT: MVT::v16i8, N1: Ops[OpNo0],
5950 N2: Ops[OpNo1],
5951 N3: DAG.getTargetConstant(Val: StartIndex, DL, VT: MVT::i32));
5952
5953 // Fall back on VPERM. Construct an SDNode for the permute vector. Try to
5954 // eliminate a zero vector by reusing any zero index in the permute vector.
5955 unsigned ZeroVecIdx = findZeroVectorIdx(Ops: &Ops[0], Num: 2);
5956 if (ZeroVecIdx != UINT32_MAX) {
5957 bool MaskFirst = true;
5958 int ZeroIdx = -1;
5959 for (unsigned I = 0; I < SystemZ::VectorBytes; ++I) {
5960 unsigned OpNo = unsigned(Bytes[I]) / SystemZ::VectorBytes;
5961 unsigned Byte = unsigned(Bytes[I]) % SystemZ::VectorBytes;
5962 if (OpNo == ZeroVecIdx && I == 0) {
5963 // If the first byte is zero, use mask as first operand.
5964 ZeroIdx = 0;
5965 break;
5966 }
5967 if (OpNo != ZeroVecIdx && Byte == 0) {
5968 // If mask contains a zero, use it by placing that vector first.
5969 ZeroIdx = I + SystemZ::VectorBytes;
5970 MaskFirst = false;
5971 break;
5972 }
5973 }
5974 if (ZeroIdx != -1) {
5975 SDValue IndexNodes[SystemZ::VectorBytes];
5976 for (unsigned I = 0; I < SystemZ::VectorBytes; ++I) {
5977 if (Bytes[I] >= 0) {
5978 unsigned OpNo = unsigned(Bytes[I]) / SystemZ::VectorBytes;
5979 unsigned Byte = unsigned(Bytes[I]) % SystemZ::VectorBytes;
5980 if (OpNo == ZeroVecIdx)
5981 IndexNodes[I] = DAG.getConstant(Val: ZeroIdx, DL, VT: MVT::i32);
5982 else {
5983 unsigned BIdx = MaskFirst ? Byte + SystemZ::VectorBytes : Byte;
5984 IndexNodes[I] = DAG.getConstant(Val: BIdx, DL, VT: MVT::i32);
5985 }
5986 } else
5987 IndexNodes[I] = DAG.getUNDEF(VT: MVT::i32);
5988 }
5989 SDValue Mask = DAG.getBuildVector(VT: MVT::v16i8, DL, Ops: IndexNodes);
5990 SDValue Src = ZeroVecIdx == 0 ? Ops[1] : Ops[0];
5991 if (MaskFirst)
5992 return DAG.getNode(Opcode: SystemZISD::PERMUTE, DL, VT: MVT::v16i8, N1: Mask, N2: Src,
5993 N3: Mask);
5994 else
5995 return DAG.getNode(Opcode: SystemZISD::PERMUTE, DL, VT: MVT::v16i8, N1: Src, N2: Mask,
5996 N3: Mask);
5997 }
5998 }
5999
6000 SDValue IndexNodes[SystemZ::VectorBytes];
6001 for (unsigned I = 0; I < SystemZ::VectorBytes; ++I)
6002 if (Bytes[I] >= 0)
6003 IndexNodes[I] = DAG.getConstant(Val: Bytes[I], DL, VT: MVT::i32);
6004 else
6005 IndexNodes[I] = DAG.getUNDEF(VT: MVT::i32);
6006 SDValue Op2 = DAG.getBuildVector(VT: MVT::v16i8, DL, Ops: IndexNodes);
6007 return DAG.getNode(Opcode: SystemZISD::PERMUTE, DL, VT: MVT::v16i8, N1: Ops[0],
6008 N2: (!Ops[1].isUndef() ? Ops[1] : Ops[0]), N3: Op2);
6009}
6010
6011namespace {
6012// Describes a general N-operand vector shuffle.
6013struct GeneralShuffle {
6014 GeneralShuffle(EVT vt)
6015 : VT(vt), UnpackFromEltSize(UINT_MAX), UnpackLow(false) {}
6016 void addUndef();
6017 bool add(SDValue, unsigned);
6018 SDValue getNode(SelectionDAG &, const SDLoc &);
6019 void tryPrepareForUnpack();
6020 bool unpackWasPrepared() { return UnpackFromEltSize <= 4; }
6021 SDValue insertUnpackIfPrepared(SelectionDAG &DAG, const SDLoc &DL, SDValue Op);
6022
6023 // The operands of the shuffle.
6024 SmallVector<SDValue, SystemZ::VectorBytes> Ops;
6025
6026 // Index I is -1 if byte I of the result is undefined. Otherwise the
6027 // result comes from byte Bytes[I] % SystemZ::VectorBytes of operand
6028 // Bytes[I] / SystemZ::VectorBytes.
6029 SmallVector<int, SystemZ::VectorBytes> Bytes;
6030
6031 // The type of the shuffle result.
6032 EVT VT;
6033
6034 // Holds a value of 1, 2 or 4 if a final unpack has been prepared for.
6035 unsigned UnpackFromEltSize;
6036 // True if the final unpack uses the low half.
6037 bool UnpackLow;
6038};
6039} // namespace
6040
6041// Add an extra undefined element to the shuffle.
6042void GeneralShuffle::addUndef() {
6043 unsigned BytesPerElement = VT.getVectorElementType().getStoreSize();
6044 for (unsigned I = 0; I < BytesPerElement; ++I)
6045 Bytes.push_back(Elt: -1);
6046}
6047
6048// Add an extra element to the shuffle, taking it from element Elem of Op.
6049// A null Op indicates a vector input whose value will be calculated later;
6050// there is at most one such input per shuffle and it always has the same
6051// type as the result. Aborts and returns false if the source vector elements
6052// of an EXTRACT_VECTOR_ELT are smaller than the destination elements. Per
6053// LLVM they become implicitly extended, but this is rare and not optimized.
6054bool GeneralShuffle::add(SDValue Op, unsigned Elem) {
6055 unsigned BytesPerElement = VT.getVectorElementType().getStoreSize();
6056
6057 // The source vector can have wider elements than the result,
6058 // either through an explicit TRUNCATE or because of type legalization.
6059 // We want the least significant part.
6060 EVT FromVT = Op.getNode() ? Op.getValueType() : VT;
6061 unsigned FromBytesPerElement = FromVT.getVectorElementType().getStoreSize();
6062
6063 // Return false if the source elements are smaller than their destination
6064 // elements.
6065 if (FromBytesPerElement < BytesPerElement)
6066 return false;
6067
6068 unsigned Byte = ((Elem * FromBytesPerElement) % SystemZ::VectorBytes +
6069 (FromBytesPerElement - BytesPerElement));
6070
6071 // Look through things like shuffles and bitcasts.
6072 while (Op.getNode()) {
6073 if (Op.getOpcode() == ISD::BITCAST)
6074 Op = Op.getOperand(i: 0);
6075 else if (Op.getOpcode() == ISD::VECTOR_SHUFFLE && Op.hasOneUse()) {
6076 // See whether the bytes we need come from a contiguous part of one
6077 // operand.
6078 SmallVector<int, SystemZ::VectorBytes> OpBytes;
6079 if (!getVPermMask(ShuffleOp: Op, Bytes&: OpBytes))
6080 break;
6081 int NewByte;
6082 if (!getShuffleInput(Bytes: OpBytes, Start: Byte, BytesPerElement, Base&: NewByte))
6083 break;
6084 if (NewByte < 0) {
6085 addUndef();
6086 return true;
6087 }
6088 Op = Op.getOperand(i: unsigned(NewByte) / SystemZ::VectorBytes);
6089 Byte = unsigned(NewByte) % SystemZ::VectorBytes;
6090 } else if (Op.isUndef()) {
6091 addUndef();
6092 return true;
6093 } else
6094 break;
6095 }
6096
6097 // Make sure that the source of the extraction is in Ops.
6098 unsigned OpNo = 0;
6099 for (; OpNo < Ops.size(); ++OpNo)
6100 if (Ops[OpNo] == Op)
6101 break;
6102 if (OpNo == Ops.size())
6103 Ops.push_back(Elt: Op);
6104
6105 // Add the element to Bytes.
6106 unsigned Base = OpNo * SystemZ::VectorBytes + Byte;
6107 for (unsigned I = 0; I < BytesPerElement; ++I)
6108 Bytes.push_back(Elt: Base + I);
6109
6110 return true;
6111}
6112
6113// Return SDNodes for the completed shuffle.
6114SDValue GeneralShuffle::getNode(SelectionDAG &DAG, const SDLoc &DL) {
6115 assert(Bytes.size() == SystemZ::VectorBytes && "Incomplete vector");
6116
6117 if (Ops.size() == 0)
6118 return DAG.getUNDEF(VT);
6119
6120 // Use a single unpack if possible as the last operation.
6121 tryPrepareForUnpack();
6122
6123 // Make sure that there are at least two shuffle operands.
6124 if (Ops.size() == 1)
6125 Ops.push_back(Elt: DAG.getUNDEF(VT: MVT::v16i8));
6126
6127 // Create a tree of shuffles, deferring root node until after the loop.
6128 // Try to redistribute the undefined elements of non-root nodes so that
6129 // the non-root shuffles match something like a pack or merge, then adjust
6130 // the parent node's permute vector to compensate for the new order.
6131 // Among other things, this copes with vectors like <2 x i16> that were
6132 // padded with undefined elements during type legalization.
6133 //
6134 // In the best case this redistribution will lead to the whole tree
6135 // using packs and merges. It should rarely be a loss in other cases.
6136 unsigned Stride = 1;
6137 for (; Stride * 2 < Ops.size(); Stride *= 2) {
6138 for (unsigned I = 0; I < Ops.size() - Stride; I += Stride * 2) {
6139 SDValue SubOps[] = { Ops[I], Ops[I + Stride] };
6140
6141 // Create a mask for just these two operands.
6142 SmallVector<int, SystemZ::VectorBytes> NewBytes(SystemZ::VectorBytes);
6143 for (unsigned J = 0; J < SystemZ::VectorBytes; ++J) {
6144 unsigned OpNo = unsigned(Bytes[J]) / SystemZ::VectorBytes;
6145 unsigned Byte = unsigned(Bytes[J]) % SystemZ::VectorBytes;
6146 if (OpNo == I)
6147 NewBytes[J] = Byte;
6148 else if (OpNo == I + Stride)
6149 NewBytes[J] = SystemZ::VectorBytes + Byte;
6150 else
6151 NewBytes[J] = -1;
6152 }
6153 // See if it would be better to reorganize NewMask to avoid using VPERM.
6154 SmallVector<int, SystemZ::VectorBytes> NewBytesMap(SystemZ::VectorBytes);
6155 if (const Permute *P = matchDoublePermute(Bytes: NewBytes, Transform&: NewBytesMap)) {
6156 Ops[I] = getPermuteNode(DAG, DL, P: *P, Op0: SubOps[0], Op1: SubOps[1]);
6157 // Applying NewBytesMap to Ops[I] gets back to NewBytes.
6158 for (unsigned J = 0; J < SystemZ::VectorBytes; ++J) {
6159 if (NewBytes[J] >= 0) {
6160 assert(unsigned(NewBytesMap[J]) < SystemZ::VectorBytes &&
6161 "Invalid double permute");
6162 Bytes[J] = I * SystemZ::VectorBytes + NewBytesMap[J];
6163 } else
6164 assert(NewBytesMap[J] < 0 && "Invalid double permute");
6165 }
6166 } else {
6167 // Just use NewBytes on the operands.
6168 Ops[I] = getGeneralPermuteNode(DAG, DL, Ops: SubOps, Bytes: NewBytes);
6169 for (unsigned J = 0; J < SystemZ::VectorBytes; ++J)
6170 if (NewBytes[J] >= 0)
6171 Bytes[J] = I * SystemZ::VectorBytes + J;
6172 }
6173 }
6174 }
6175
6176 // Now we just have 2 inputs. Put the second operand in Ops[1].
6177 if (Stride > 1) {
6178 Ops[1] = Ops[Stride];
6179 for (unsigned I = 0; I < SystemZ::VectorBytes; ++I)
6180 if (Bytes[I] >= int(SystemZ::VectorBytes))
6181 Bytes[I] -= (Stride - 1) * SystemZ::VectorBytes;
6182 }
6183
6184 // Look for an instruction that can do the permute without resorting
6185 // to VPERM.
6186 unsigned OpNo0, OpNo1;
6187 SDValue Op;
6188 if (unpackWasPrepared() && Ops[1].isUndef())
6189 Op = Ops[0];
6190 else if (const Permute *P = matchPermute(Bytes, OpNo0, OpNo1))
6191 Op = getPermuteNode(DAG, DL, P: *P, Op0: Ops[OpNo0], Op1: Ops[OpNo1]);
6192 else
6193 Op = getGeneralPermuteNode(DAG, DL, Ops: &Ops[0], Bytes);
6194
6195 Op = insertUnpackIfPrepared(DAG, DL, Op);
6196
6197 return DAG.getNode(Opcode: ISD::BITCAST, DL, VT, Operand: Op);
6198}
6199
6200#ifndef NDEBUG
6201static void dumpBytes(const SmallVectorImpl<int> &Bytes, std::string Msg) {
6202 dbgs() << Msg.c_str() << " { ";
6203 for (unsigned I = 0; I < Bytes.size(); I++)
6204 dbgs() << Bytes[I] << " ";
6205 dbgs() << "}\n";
6206}
6207#endif
6208
6209// If the Bytes vector matches an unpack operation, prepare to do the unpack
6210// after all else by removing the zero vector and the effect of the unpack on
6211// Bytes.
6212void GeneralShuffle::tryPrepareForUnpack() {
6213 uint32_t ZeroVecOpNo = findZeroVectorIdx(Ops: &Ops[0], Num: Ops.size());
6214 if (ZeroVecOpNo == UINT32_MAX || Ops.size() == 1)
6215 return;
6216
6217 // Only do this if removing the zero vector reduces the depth, otherwise
6218 // the critical path will increase with the final unpack.
6219 if (Ops.size() > 2 &&
6220 Log2_32_Ceil(Value: Ops.size()) == Log2_32_Ceil(Value: Ops.size() - 1))
6221 return;
6222
6223 // Find an unpack that would allow removing the zero vector from Ops.
6224 UnpackFromEltSize = 1;
6225 for (; UnpackFromEltSize <= 4; UnpackFromEltSize *= 2) {
6226 bool MatchUnpack = true;
6227 SmallVector<int, SystemZ::VectorBytes> SrcBytes;
6228 for (unsigned Elt = 0; Elt < SystemZ::VectorBytes; Elt++) {
6229 unsigned ToEltSize = UnpackFromEltSize * 2;
6230 bool IsZextByte = (Elt % ToEltSize) < UnpackFromEltSize;
6231 if (!IsZextByte)
6232 SrcBytes.push_back(Elt: Bytes[Elt]);
6233 if (Bytes[Elt] != -1) {
6234 unsigned OpNo = unsigned(Bytes[Elt]) / SystemZ::VectorBytes;
6235 if (IsZextByte != (OpNo == ZeroVecOpNo)) {
6236 MatchUnpack = false;
6237 break;
6238 }
6239 }
6240 }
6241 if (MatchUnpack) {
6242 if (Ops.size() == 2) {
6243 // Don't use unpack if a single source operand needs rearrangement.
6244 bool CanUseUnpackLow = true, CanUseUnpackHigh = true;
6245 for (unsigned i = 0; i < SystemZ::VectorBytes / 2; i++) {
6246 if (SrcBytes[i] == -1)
6247 continue;
6248 if (SrcBytes[i] % 16 != int(i))
6249 CanUseUnpackHigh = false;
6250 if (SrcBytes[i] % 16 != int(i + SystemZ::VectorBytes / 2))
6251 CanUseUnpackLow = false;
6252 if (!CanUseUnpackLow && !CanUseUnpackHigh) {
6253 UnpackFromEltSize = UINT_MAX;
6254 return;
6255 }
6256 }
6257 if (!CanUseUnpackHigh)
6258 UnpackLow = true;
6259 }
6260 break;
6261 }
6262 }
6263 if (UnpackFromEltSize > 4)
6264 return;
6265
6266 LLVM_DEBUG(dbgs() << "Preparing for final unpack of element size "
6267 << UnpackFromEltSize << ". Zero vector is Op#" << ZeroVecOpNo
6268 << ".\n";
6269 dumpBytes(Bytes, "Original Bytes vector:"););
6270
6271 // Apply the unpack in reverse to the Bytes array.
6272 unsigned B = 0;
6273 if (UnpackLow) {
6274 while (B < SystemZ::VectorBytes / 2)
6275 Bytes[B++] = -1;
6276 }
6277 for (unsigned Elt = 0; Elt < SystemZ::VectorBytes;) {
6278 Elt += UnpackFromEltSize;
6279 for (unsigned i = 0; i < UnpackFromEltSize; i++, Elt++, B++)
6280 Bytes[B] = Bytes[Elt];
6281 }
6282 if (!UnpackLow) {
6283 while (B < SystemZ::VectorBytes)
6284 Bytes[B++] = -1;
6285 }
6286
6287 // Remove the zero vector from Ops
6288 Ops.erase(CI: &Ops[ZeroVecOpNo]);
6289 for (unsigned I = 0; I < SystemZ::VectorBytes; ++I)
6290 if (Bytes[I] >= 0) {
6291 unsigned OpNo = unsigned(Bytes[I]) / SystemZ::VectorBytes;
6292 if (OpNo > ZeroVecOpNo)
6293 Bytes[I] -= SystemZ::VectorBytes;
6294 }
6295
6296 LLVM_DEBUG(dumpBytes(Bytes, "Resulting Bytes vector, zero vector removed:");
6297 dbgs() << "\n";);
6298}
6299
6300SDValue GeneralShuffle::insertUnpackIfPrepared(SelectionDAG &DAG,
6301 const SDLoc &DL,
6302 SDValue Op) {
6303 if (!unpackWasPrepared())
6304 return Op;
6305 unsigned InBits = UnpackFromEltSize * 8;
6306 EVT InVT = MVT::getVectorVT(VT: MVT::getIntegerVT(BitWidth: InBits),
6307 NumElements: SystemZ::VectorBits / InBits);
6308 SDValue PackedOp = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: InVT, Operand: Op);
6309 unsigned OutBits = InBits * 2;
6310 EVT OutVT = MVT::getVectorVT(VT: MVT::getIntegerVT(BitWidth: OutBits),
6311 NumElements: SystemZ::VectorBits / OutBits);
6312 return DAG.getNode(Opcode: UnpackLow ? SystemZISD::UNPACKL_LOW
6313 : SystemZISD::UNPACKL_HIGH,
6314 DL, VT: OutVT, Operand: PackedOp);
6315}
6316
6317// Return true if the given BUILD_VECTOR is a scalar-to-vector conversion.
6318static bool isScalarToVector(SDValue Op) {
6319 for (unsigned I = 1, E = Op.getNumOperands(); I != E; ++I)
6320 if (!Op.getOperand(i: I).isUndef())
6321 return false;
6322 return true;
6323}
6324
6325// Return a vector of type VT that contains Value in the first element.
6326// The other elements don't matter.
6327static SDValue buildScalarToVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
6328 SDValue Value) {
6329 // If we have a constant, replicate it to all elements and let the
6330 // BUILD_VECTOR lowering take care of it.
6331 if (Value.getOpcode() == ISD::Constant ||
6332 Value.getOpcode() == ISD::ConstantFP) {
6333 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Value);
6334 return DAG.getBuildVector(VT, DL, Ops);
6335 }
6336 if (Value.isUndef())
6337 return DAG.getUNDEF(VT);
6338 return DAG.getNode(Opcode: ISD::SCALAR_TO_VECTOR, DL, VT, Operand: Value);
6339}
6340
6341// Return a vector of type VT in which Op0 is in element 0 and Op1 is in
6342// element 1. Used for cases in which replication is cheap.
6343static SDValue buildMergeScalars(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
6344 SDValue Op0, SDValue Op1) {
6345 if (Op0.isUndef()) {
6346 if (Op1.isUndef())
6347 return DAG.getUNDEF(VT);
6348 return DAG.getNode(Opcode: SystemZISD::REPLICATE, DL, VT, Operand: Op1);
6349 }
6350 if (Op1.isUndef())
6351 return DAG.getNode(Opcode: SystemZISD::REPLICATE, DL, VT, Operand: Op0);
6352 return DAG.getNode(Opcode: SystemZISD::MERGE_HIGH, DL, VT,
6353 N1: buildScalarToVector(DAG, DL, VT, Value: Op0),
6354 N2: buildScalarToVector(DAG, DL, VT, Value: Op1));
6355}
6356
6357// Extend GPR scalars Op0 and Op1 to doublewords and return a v2i64
6358// vector for them.
6359static SDValue joinDwords(SelectionDAG &DAG, const SDLoc &DL, SDValue Op0,
6360 SDValue Op1) {
6361 if (Op0.isUndef() && Op1.isUndef())
6362 return DAG.getUNDEF(VT: MVT::v2i64);
6363 // If one of the two inputs is undefined then replicate the other one,
6364 // in order to avoid using another register unnecessarily.
6365 if (Op0.isUndef())
6366 Op0 = Op1 = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: MVT::i64, Operand: Op1);
6367 else if (Op1.isUndef())
6368 Op0 = Op1 = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: MVT::i64, Operand: Op0);
6369 else {
6370 Op0 = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: MVT::i64, Operand: Op0);
6371 Op1 = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: MVT::i64, Operand: Op1);
6372 }
6373 return DAG.getNode(Opcode: SystemZISD::JOIN_DWORDS, DL, VT: MVT::v2i64, N1: Op0, N2: Op1);
6374}
6375
6376// If a BUILD_VECTOR contains some EXTRACT_VECTOR_ELTs, it's usually
6377// better to use VECTOR_SHUFFLEs on them, only using BUILD_VECTOR for
6378// the non-EXTRACT_VECTOR_ELT elements. See if the given BUILD_VECTOR
6379// would benefit from this representation and return it if so.
6380static SDValue tryBuildVectorShuffle(SelectionDAG &DAG,
6381 BuildVectorSDNode *BVN) {
6382 EVT VT = BVN->getValueType(ResNo: 0);
6383 unsigned NumElements = VT.getVectorNumElements();
6384
6385 // Represent the BUILD_VECTOR as an N-operand VECTOR_SHUFFLE-like operation
6386 // on byte vectors. If there are non-EXTRACT_VECTOR_ELT elements that still
6387 // need a BUILD_VECTOR, add an additional placeholder operand for that
6388 // BUILD_VECTOR and store its operands in ResidueOps.
6389 GeneralShuffle GS(VT);
6390 SmallVector<SDValue, SystemZ::VectorBytes> ResidueOps;
6391 bool FoundOne = false;
6392 for (unsigned I = 0; I < NumElements; ++I) {
6393 SDValue Op = BVN->getOperand(Num: I);
6394 if (Op.getOpcode() == ISD::TRUNCATE)
6395 Op = Op.getOperand(i: 0);
6396 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6397 Op.getOperand(i: 1).getOpcode() == ISD::Constant) {
6398 unsigned Elem = Op.getConstantOperandVal(i: 1);
6399 if (!GS.add(Op: Op.getOperand(i: 0), Elem))
6400 return SDValue();
6401 FoundOne = true;
6402 } else if (Op.isUndef()) {
6403 GS.addUndef();
6404 } else {
6405 if (!GS.add(Op: SDValue(), Elem: ResidueOps.size()))
6406 return SDValue();
6407 ResidueOps.push_back(Elt: BVN->getOperand(Num: I));
6408 }
6409 }
6410
6411 // Nothing to do if there are no EXTRACT_VECTOR_ELTs.
6412 if (!FoundOne)
6413 return SDValue();
6414
6415 // Create the BUILD_VECTOR for the remaining elements, if any.
6416 if (!ResidueOps.empty()) {
6417 while (ResidueOps.size() < NumElements)
6418 ResidueOps.push_back(Elt: DAG.getUNDEF(VT: ResidueOps[0].getValueType()));
6419 for (auto &Op : GS.Ops) {
6420 if (!Op.getNode()) {
6421 Op = DAG.getBuildVector(VT, DL: SDLoc(BVN), Ops: ResidueOps);
6422 break;
6423 }
6424 }
6425 }
6426 return GS.getNode(DAG, DL: SDLoc(BVN));
6427}
6428
6429bool SystemZTargetLowering::isVectorElementLoad(SDValue Op) const {
6430 if (Op.getOpcode() == ISD::LOAD && cast<LoadSDNode>(Val&: Op)->isUnindexed())
6431 return true;
6432 if (auto *AL = dyn_cast<AtomicSDNode>(Val&: Op))
6433 if (AL->getOpcode() == ISD::ATOMIC_LOAD)
6434 return true;
6435 if (Subtarget.hasVectorEnhancements2() && Op.getOpcode() == SystemZISD::LRV)
6436 return true;
6437 return false;
6438}
6439
6440static SDValue mergeHighParts(SelectionDAG &DAG, const SDLoc &DL,
6441 unsigned MergedBits, EVT VT, SDValue Op0,
6442 SDValue Op1) {
6443 MVT IntVecVT = MVT::getVectorVT(VT: MVT::getIntegerVT(BitWidth: MergedBits),
6444 NumElements: SystemZ::VectorBits / MergedBits);
6445 assert(VT.getSizeInBits() == 128 && IntVecVT.getSizeInBits() == 128 &&
6446 "Handling full vectors only.");
6447 Op0 = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: IntVecVT, Operand: Op0);
6448 Op1 = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: IntVecVT, Operand: Op1);
6449 SDValue Op = DAG.getNode(Opcode: SystemZISD::MERGE_HIGH, DL, VT: IntVecVT, N1: Op0, N2: Op1);
6450 return DAG.getNode(Opcode: ISD::BITCAST, DL, VT, Operand: Op);
6451}
6452
6453static SDValue buildFPVecFromScalars4(SelectionDAG &DAG, const SDLoc &DL,
6454 EVT VT, SmallVectorImpl<SDValue> &Elems,
6455 unsigned Pos) {
6456 SDValue Op01 = buildMergeScalars(DAG, DL, VT, Op0: Elems[Pos + 0], Op1: Elems[Pos + 1]);
6457 SDValue Op23 = buildMergeScalars(DAG, DL, VT, Op0: Elems[Pos + 2], Op1: Elems[Pos + 3]);
6458 // Avoid unnecessary undefs by reusing the other operand.
6459 if (Op01.isUndef()) {
6460 if (Op23.isUndef())
6461 return Op01;
6462 Op01 = Op23;
6463 } else if (Op23.isUndef())
6464 Op23 = Op01;
6465 // Merging identical replications is a no-op.
6466 if (Op01.getOpcode() == SystemZISD::REPLICATE && Op01 == Op23)
6467 return Op01;
6468 unsigned MergedBits = VT.getSimpleVT().getScalarSizeInBits() * 2;
6469 return mergeHighParts(DAG, DL, MergedBits, VT, Op0: Op01, Op1: Op23);
6470}
6471
6472// Combine GPR scalar values Elems into a vector of type VT.
6473SDValue
6474SystemZTargetLowering::buildVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
6475 SmallVectorImpl<SDValue> &Elems) const {
6476 // See whether there is a single replicated value.
6477 SDValue Single;
6478 unsigned int NumElements = Elems.size();
6479 unsigned int Count = 0;
6480 for (auto Elem : Elems) {
6481 if (!Elem.isUndef()) {
6482 if (!Single.getNode())
6483 Single = Elem;
6484 else if (Elem != Single) {
6485 Single = SDValue();
6486 break;
6487 }
6488 Count += 1;
6489 }
6490 }
6491 // There are three cases here:
6492 //
6493 // - if the only defined element is a loaded one, the best sequence
6494 // is a replicating load.
6495 //
6496 // - otherwise, if the only defined element is an i64 value, we will
6497 // end up with the same VLVGP sequence regardless of whether we short-cut
6498 // for replication or fall through to the later code.
6499 //
6500 // - otherwise, if the only defined element is an i32 or smaller value,
6501 // we would need 2 instructions to replicate it: VLVGP followed by VREPx.
6502 // This is only a win if the single defined element is used more than once.
6503 // In other cases we're better off using a single VLVGx.
6504 if (Single.getNode() && (Count > 1 || isVectorElementLoad(Op: Single)))
6505 return DAG.getNode(Opcode: SystemZISD::REPLICATE, DL, VT, Operand: Single);
6506
6507 // If all elements are loads, use VLREP/VLEs (below).
6508 bool AllLoads = true;
6509 for (auto Elem : Elems)
6510 if (!isVectorElementLoad(Op: Elem)) {
6511 AllLoads = false;
6512 break;
6513 }
6514
6515 // The best way of building a v2i64 from two i64s is to use VLVGP.
6516 if (VT == MVT::v2i64 && !AllLoads)
6517 return joinDwords(DAG, DL, Op0: Elems[0], Op1: Elems[1]);
6518
6519 // Use a 64-bit merge high to combine two doubles.
6520 if (VT == MVT::v2f64 && !AllLoads)
6521 return buildMergeScalars(DAG, DL, VT, Op0: Elems[0], Op1: Elems[1]);
6522
6523 // Build v4f32 values directly from the FPRs:
6524 //
6525 // <Axxx> <Bxxx> <Cxxxx> <Dxxx>
6526 // V V VMRHF
6527 // <ABxx> <CDxx>
6528 // V VMRHG
6529 // <ABCD>
6530 if (VT == MVT::v4f32 && !AllLoads)
6531 return buildFPVecFromScalars4(DAG, DL, VT, Elems, Pos: 0);
6532
6533 // Same for v8f16.
6534 if (VT == MVT::v8f16 && !AllLoads) {
6535 SDValue Op0123 = buildFPVecFromScalars4(DAG, DL, VT, Elems, Pos: 0);
6536 SDValue Op4567 = buildFPVecFromScalars4(DAG, DL, VT, Elems, Pos: 4);
6537 // Avoid unnecessary undefs by reusing the other operand.
6538 if (Op0123.isUndef())
6539 Op0123 = Op4567;
6540 else if (Op4567.isUndef())
6541 Op4567 = Op0123;
6542 // Merging identical replications is a no-op.
6543 if (Op0123.getOpcode() == SystemZISD::REPLICATE && Op0123 == Op4567)
6544 return Op0123;
6545 return mergeHighParts(DAG, DL, MergedBits: 64, VT, Op0: Op0123, Op1: Op4567);
6546 }
6547
6548 // Collect the constant terms.
6549 SmallVector<SDValue, SystemZ::VectorBytes> Constants(NumElements, SDValue());
6550 SmallVector<bool, SystemZ::VectorBytes> Done(NumElements, false);
6551
6552 unsigned NumConstants = 0;
6553 for (unsigned I = 0; I < NumElements; ++I) {
6554 SDValue Elem = Elems[I];
6555 if (Elem.getOpcode() == ISD::Constant ||
6556 Elem.getOpcode() == ISD::ConstantFP) {
6557 NumConstants += 1;
6558 Constants[I] = Elem;
6559 Done[I] = true;
6560 }
6561 }
6562 // If there was at least one constant, fill in the other elements of
6563 // Constants with undefs to get a full vector constant and use that
6564 // as the starting point.
6565 SDValue Result;
6566 SDValue ReplicatedVal;
6567 if (NumConstants > 0) {
6568 for (unsigned I = 0; I < NumElements; ++I)
6569 if (!Constants[I].getNode())
6570 Constants[I] = DAG.getUNDEF(VT: Elems[I].getValueType());
6571 Result = DAG.getBuildVector(VT, DL, Ops: Constants);
6572 } else {
6573 // Otherwise try to use VLREP or VLVGP to start the sequence in order to
6574 // avoid a false dependency on any previous contents of the vector
6575 // register.
6576
6577 // Use a VLREP if at least one element is a load. Make sure to replicate
6578 // the load with the most elements having its value.
6579 std::map<const SDNode*, unsigned> UseCounts;
6580 SDNode *LoadMaxUses = nullptr;
6581 for (unsigned I = 0; I < NumElements; ++I)
6582 if (isVectorElementLoad(Op: Elems[I])) {
6583 SDNode *Ld = Elems[I].getNode();
6584 unsigned Count = ++UseCounts[Ld];
6585 if (LoadMaxUses == nullptr || UseCounts[LoadMaxUses] < Count)
6586 LoadMaxUses = Ld;
6587 }
6588 if (LoadMaxUses != nullptr) {
6589 ReplicatedVal = SDValue(LoadMaxUses, 0);
6590 Result = DAG.getNode(Opcode: SystemZISD::REPLICATE, DL, VT, Operand: ReplicatedVal);
6591 } else {
6592 // Try to use VLVGP.
6593 unsigned I1 = NumElements / 2 - 1;
6594 unsigned I2 = NumElements - 1;
6595 bool Def1 = !Elems[I1].isUndef();
6596 bool Def2 = !Elems[I2].isUndef();
6597 if (Def1 || Def2) {
6598 SDValue Elem1 = Elems[Def1 ? I1 : I2];
6599 SDValue Elem2 = Elems[Def2 ? I2 : I1];
6600 Result = DAG.getNode(Opcode: ISD::BITCAST, DL, VT,
6601 Operand: joinDwords(DAG, DL, Op0: Elem1, Op1: Elem2));
6602 Done[I1] = true;
6603 Done[I2] = true;
6604 } else
6605 Result = DAG.getUNDEF(VT);
6606 }
6607 }
6608
6609 // Use VLVGx to insert the other elements.
6610 for (unsigned I = 0; I < NumElements; ++I)
6611 if (!Done[I] && !Elems[I].isUndef() && Elems[I] != ReplicatedVal)
6612 Result = DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL, VT, N1: Result, N2: Elems[I],
6613 N3: DAG.getConstant(Val: I, DL, VT: MVT::i32));
6614 return Result;
6615}
6616
6617SDValue SystemZTargetLowering::lowerBUILD_VECTOR(SDValue Op,
6618 SelectionDAG &DAG) const {
6619 auto *BVN = cast<BuildVectorSDNode>(Val: Op.getNode());
6620 SDLoc DL(Op);
6621 EVT VT = Op.getValueType();
6622
6623 if (BVN->isConstant()) {
6624 if (SystemZVectorConstantInfo(BVN).isVectorConstantLegal(Subtarget))
6625 return Op;
6626
6627 // Fall back to loading it from memory.
6628 return SDValue();
6629 }
6630
6631 // See if we should use shuffles to construct the vector from other vectors.
6632 if (SDValue Res = tryBuildVectorShuffle(DAG, BVN))
6633 return Res;
6634
6635 // Detect SCALAR_TO_VECTOR conversions.
6636 if (isOperationLegal(Op: ISD::SCALAR_TO_VECTOR, VT) && isScalarToVector(Op))
6637 return buildScalarToVector(DAG, DL, VT, Value: Op.getOperand(i: 0));
6638
6639 // Otherwise use buildVector to build the vector up from GPRs.
6640 unsigned NumElements = Op.getNumOperands();
6641 SmallVector<SDValue, SystemZ::VectorBytes> Ops(NumElements);
6642 for (unsigned I = 0; I < NumElements; ++I)
6643 Ops[I] = Op.getOperand(i: I);
6644 return buildVector(DAG, DL, VT, Elems&: Ops);
6645}
6646
6647SDValue SystemZTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
6648 SelectionDAG &DAG) const {
6649 auto *VSN = cast<ShuffleVectorSDNode>(Val: Op.getNode());
6650 SDLoc DL(Op);
6651 EVT VT = Op.getValueType();
6652 unsigned NumElements = VT.getVectorNumElements();
6653
6654 if (VSN->isSplat()) {
6655 SDValue Op0 = Op.getOperand(i: 0);
6656 unsigned Index = VSN->getSplatIndex();
6657 assert(Index < VT.getVectorNumElements() &&
6658 "Splat index should be defined and in first operand");
6659 // See whether the value we're splatting is directly available as a scalar.
6660 if ((Index == 0 && Op0.getOpcode() == ISD::SCALAR_TO_VECTOR) ||
6661 Op0.getOpcode() == ISD::BUILD_VECTOR)
6662 return DAG.getNode(Opcode: SystemZISD::REPLICATE, DL, VT, Operand: Op0.getOperand(i: Index));
6663 // Otherwise keep it as a vector-to-vector operation.
6664 return DAG.getNode(Opcode: SystemZISD::SPLAT, DL, VT, N1: Op.getOperand(i: 0),
6665 N2: DAG.getTargetConstant(Val: Index, DL, VT: MVT::i32));
6666 }
6667
6668 GeneralShuffle GS(VT);
6669 for (unsigned I = 0; I < NumElements; ++I) {
6670 int Elt = VSN->getMaskElt(Idx: I);
6671 if (Elt < 0)
6672 GS.addUndef();
6673 else if (!GS.add(Op: Op.getOperand(i: unsigned(Elt) / NumElements),
6674 Elem: unsigned(Elt) % NumElements))
6675 return SDValue();
6676 }
6677 return GS.getNode(DAG, DL: SDLoc(VSN));
6678}
6679
6680SDValue SystemZTargetLowering::lowerSCALAR_TO_VECTOR(SDValue Op,
6681 SelectionDAG &DAG) const {
6682 SDLoc DL(Op);
6683 // Just insert the scalar into element 0 of an undefined vector.
6684 return DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL,
6685 VT: Op.getValueType(), N1: DAG.getUNDEF(VT: Op.getValueType()),
6686 N2: Op.getOperand(i: 0), N3: DAG.getConstant(Val: 0, DL, VT: MVT::i32));
6687}
6688
6689// Shift the lower 2 bytes of Op to the left in order to insert into the
6690// upper 2 bytes of the FP register.
6691static SDValue convertToF16(SDValue Op, SelectionDAG &DAG) {
6692 assert(Op.getSimpleValueType() == MVT::i64 &&
6693 "Expexted to convert i64 to f16.");
6694 SDLoc DL(Op);
6695 SDValue Shft = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i64, N1: Op,
6696 N2: DAG.getConstant(Val: 48, DL, VT: MVT::i64));
6697 SDValue BCast = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: MVT::f64, Operand: Shft);
6698 SDValue F16Val =
6699 DAG.getTargetExtractSubreg(SRIdx: SystemZ::subreg_h16, DL, VT: MVT::f16, Operand: BCast);
6700 return F16Val;
6701}
6702
6703// Extract Op into GPR and shift the 2 f16 bytes to the right.
6704static SDValue convertFromF16(SDValue Op, SDLoc DL, SelectionDAG &DAG) {
6705 assert(Op.getSimpleValueType() == MVT::f16 &&
6706 "Expected to convert f16 to i64.");
6707 SDNode *U32 = DAG.getMachineNode(Opcode: TargetOpcode::IMPLICIT_DEF, dl: DL, VT: MVT::f64);
6708 SDValue In64 = DAG.getTargetInsertSubreg(SRIdx: SystemZ::subreg_h16, DL, VT: MVT::f64,
6709 Operand: SDValue(U32, 0), Subreg: Op);
6710 SDValue BCast = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: MVT::i64, Operand: In64);
6711 SDValue Shft = DAG.getNode(Opcode: ISD::SRL, DL, VT: MVT::i64, N1: BCast,
6712 N2: DAG.getConstant(Val: 48, DL, VT: MVT::i32));
6713 return Shft;
6714}
6715
6716SDValue SystemZTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
6717 SelectionDAG &DAG) const {
6718 // Handle insertions of floating-point values.
6719 SDLoc DL(Op);
6720 SDValue Op0 = Op.getOperand(i: 0);
6721 SDValue Op1 = Op.getOperand(i: 1);
6722 SDValue Op2 = Op.getOperand(i: 2);
6723 EVT VT = Op.getValueType();
6724
6725 // Insertions into constant indices of a v2f64 can be done using VPDI.
6726 // However, if the inserted value is a bitcast or a constant then it's
6727 // better to use GPRs, as below.
6728 if (VT == MVT::v2f64 &&
6729 Op1.getOpcode() != ISD::BITCAST &&
6730 Op1.getOpcode() != ISD::ConstantFP &&
6731 Op2.getOpcode() == ISD::Constant) {
6732 uint64_t Index = Op2->getAsZExtVal();
6733 unsigned Mask = VT.getVectorNumElements() - 1;
6734 if (Index <= Mask)
6735 return Op;
6736 }
6737
6738 // Otherwise bitcast to the equivalent integer form and insert via a GPR.
6739 MVT IntVT = MVT::getIntegerVT(BitWidth: VT.getScalarSizeInBits());
6740 MVT IntVecVT = MVT::getVectorVT(VT: IntVT, NumElements: VT.getVectorNumElements());
6741 SDValue IntOp1 =
6742 VT == MVT::v8f16
6743 ? DAG.getZExtOrTrunc(Op: convertFromF16(Op: Op1, DL, DAG), DL, VT: MVT::i32)
6744 : DAG.getNode(Opcode: ISD::BITCAST, DL, VT: IntVT, Operand: Op1);
6745 SDValue Res =
6746 DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL, VT: IntVecVT,
6747 N1: DAG.getNode(Opcode: ISD::BITCAST, DL, VT: IntVecVT, Operand: Op0), N2: IntOp1, N3: Op2);
6748 return DAG.getNode(Opcode: ISD::BITCAST, DL, VT, Operand: Res);
6749}
6750
6751SDValue
6752SystemZTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
6753 SelectionDAG &DAG) const {
6754 // Handle extractions of floating-point values.
6755 SDLoc DL(Op);
6756 SDValue Op0 = Op.getOperand(i: 0);
6757 SDValue Op1 = Op.getOperand(i: 1);
6758 EVT VT = Op.getValueType();
6759 EVT VecVT = Op0.getValueType();
6760
6761 // Extractions of constant indices can be done directly.
6762 if (auto *CIndexN = dyn_cast<ConstantSDNode>(Val&: Op1)) {
6763 uint64_t Index = CIndexN->getZExtValue();
6764 unsigned Mask = VecVT.getVectorNumElements() - 1;
6765 if (Index <= Mask)
6766 return Op;
6767 }
6768
6769 // Otherwise bitcast to the equivalent integer form and extract via a GPR.
6770 MVT IntVT = MVT::getIntegerVT(BitWidth: VT.getSizeInBits());
6771 MVT IntVecVT = MVT::getVectorVT(VT: IntVT, NumElements: VecVT.getVectorNumElements());
6772 MVT ExtrVT = IntVT == MVT::i16 ? MVT::i32 : IntVT;
6773 SDValue Extr = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: ExtrVT,
6774 N1: DAG.getNode(Opcode: ISD::BITCAST, DL, VT: IntVecVT, Operand: Op0), N2: Op1);
6775 if (VT == MVT::f16)
6776 return convertToF16(Op: DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: MVT::i64, Operand: Extr), DAG);
6777 return DAG.getNode(Opcode: ISD::BITCAST, DL, VT, Operand: Extr);
6778}
6779
6780SDValue SystemZTargetLowering::
6781lowerSIGN_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const {
6782 SDValue PackedOp = Op.getOperand(i: 0);
6783 EVT OutVT = Op.getValueType();
6784 EVT InVT = PackedOp.getValueType();
6785 unsigned ToBits = OutVT.getScalarSizeInBits();
6786 unsigned FromBits = InVT.getScalarSizeInBits();
6787 unsigned StartOffset = 0;
6788
6789 // If the input is a VECTOR_SHUFFLE, there are a number of important
6790 // cases where we can directly implement the sign-extension of the
6791 // original input lanes of the shuffle.
6792 if (PackedOp.getOpcode() == ISD::VECTOR_SHUFFLE) {
6793 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Val: PackedOp.getNode());
6794 ArrayRef<int> ShuffleMask = SVN->getMask();
6795 int OutNumElts = OutVT.getVectorNumElements();
6796
6797 // Recognize the special case where the sign-extension can be done
6798 // by the VSEG instruction. Handled via the default expander.
6799 if (ToBits == 64 && OutNumElts == 2) {
6800 int NumElem = ToBits / FromBits;
6801 if (ShuffleMask[0] == NumElem - 1 && ShuffleMask[1] == 2 * NumElem - 1)
6802 return SDValue();
6803 }
6804
6805 // Recognize the special case where we can fold the shuffle by
6806 // replacing some of the UNPACK_HIGH with UNPACK_LOW.
6807 int StartOffsetCandidate = -1;
6808 for (int Elt = 0; Elt < OutNumElts; Elt++) {
6809 if (ShuffleMask[Elt] == -1)
6810 continue;
6811 if (ShuffleMask[Elt] % OutNumElts == Elt) {
6812 if (StartOffsetCandidate == -1)
6813 StartOffsetCandidate = ShuffleMask[Elt] - Elt;
6814 if (StartOffsetCandidate == ShuffleMask[Elt] - Elt)
6815 continue;
6816 }
6817 StartOffsetCandidate = -1;
6818 break;
6819 }
6820 if (StartOffsetCandidate != -1) {
6821 StartOffset = StartOffsetCandidate;
6822 PackedOp = PackedOp.getOperand(i: 0);
6823 }
6824 }
6825
6826 do {
6827 FromBits *= 2;
6828 unsigned OutNumElts = SystemZ::VectorBits / FromBits;
6829 EVT OutVT = MVT::getVectorVT(VT: MVT::getIntegerVT(BitWidth: FromBits), NumElements: OutNumElts);
6830 unsigned Opcode = SystemZISD::UNPACK_HIGH;
6831 if (StartOffset >= OutNumElts) {
6832 Opcode = SystemZISD::UNPACK_LOW;
6833 StartOffset -= OutNumElts;
6834 }
6835 PackedOp = DAG.getNode(Opcode, DL: SDLoc(PackedOp), VT: OutVT, Operand: PackedOp);
6836 } while (FromBits != ToBits);
6837 return PackedOp;
6838}
6839
6840// Lower a ZERO_EXTEND_VECTOR_INREG to a vector shuffle with a zero vector.
6841SDValue SystemZTargetLowering::
6842lowerZERO_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const {
6843 SDValue PackedOp = Op.getOperand(i: 0);
6844 SDLoc DL(Op);
6845 EVT OutVT = Op.getValueType();
6846 EVT InVT = PackedOp.getValueType();
6847 unsigned InNumElts = InVT.getVectorNumElements();
6848 unsigned OutNumElts = OutVT.getVectorNumElements();
6849 unsigned NumInPerOut = InNumElts / OutNumElts;
6850
6851 SDValue ZeroVec =
6852 DAG.getSplatVector(VT: InVT, DL, Op: DAG.getConstant(Val: 0, DL, VT: InVT.getScalarType()));
6853
6854 SmallVector<int, 16> Mask(InNumElts);
6855 unsigned ZeroVecElt = InNumElts;
6856 for (unsigned PackedElt = 0; PackedElt < OutNumElts; PackedElt++) {
6857 unsigned MaskElt = PackedElt * NumInPerOut;
6858 unsigned End = MaskElt + NumInPerOut - 1;
6859 for (; MaskElt < End; MaskElt++)
6860 Mask[MaskElt] = ZeroVecElt++;
6861 Mask[MaskElt] = PackedElt;
6862 }
6863 SDValue Shuf = DAG.getVectorShuffle(VT: InVT, dl: DL, N1: PackedOp, N2: ZeroVec, Mask);
6864 return DAG.getNode(Opcode: ISD::BITCAST, DL, VT: OutVT, Operand: Shuf);
6865}
6866
6867SDValue SystemZTargetLowering::lowerShift(SDValue Op, SelectionDAG &DAG,
6868 unsigned ByScalar) const {
6869 // Look for cases where a vector shift can use the *_BY_SCALAR form.
6870 SDValue Op0 = Op.getOperand(i: 0);
6871 SDValue Op1 = Op.getOperand(i: 1);
6872 SDLoc DL(Op);
6873 EVT VT = Op.getValueType();
6874 unsigned ElemBitSize = VT.getScalarSizeInBits();
6875
6876 // See whether the shift vector is a splat represented as BUILD_VECTOR.
6877 if (auto *BVN = dyn_cast<BuildVectorSDNode>(Val&: Op1)) {
6878 APInt SplatBits, SplatUndef;
6879 unsigned SplatBitSize;
6880 bool HasAnyUndefs;
6881 // Check for constant splats. Use ElemBitSize as the minimum element
6882 // width and reject splats that need wider elements.
6883 if (BVN->isConstantSplat(SplatValue&: SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs,
6884 MinSplatBits: ElemBitSize, isBigEndian: true) &&
6885 SplatBitSize == ElemBitSize) {
6886 SDValue Shift = DAG.getConstant(Val: SplatBits.getZExtValue() & 0xfff,
6887 DL, VT: MVT::i32);
6888 return DAG.getNode(Opcode: ByScalar, DL, VT, N1: Op0, N2: Shift);
6889 }
6890 // Check for variable splats.
6891 BitVector UndefElements;
6892 SDValue Splat = BVN->getSplatValue(UndefElements: &UndefElements);
6893 if (Splat) {
6894 // Since i32 is the smallest legal type, we either need a no-op
6895 // or a truncation.
6896 SDValue Shift = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: MVT::i32, Operand: Splat);
6897 return DAG.getNode(Opcode: ByScalar, DL, VT, N1: Op0, N2: Shift);
6898 }
6899 }
6900
6901 // See whether the shift vector is a splat represented as SHUFFLE_VECTOR,
6902 // and the shift amount is directly available in a GPR.
6903 if (auto *VSN = dyn_cast<ShuffleVectorSDNode>(Val&: Op1)) {
6904 if (VSN->isSplat()) {
6905 SDValue VSNOp0 = VSN->getOperand(Num: 0);
6906 unsigned Index = VSN->getSplatIndex();
6907 assert(Index < VT.getVectorNumElements() &&
6908 "Splat index should be defined and in first operand");
6909 if ((Index == 0 && VSNOp0.getOpcode() == ISD::SCALAR_TO_VECTOR) ||
6910 VSNOp0.getOpcode() == ISD::BUILD_VECTOR) {
6911 // Since i32 is the smallest legal type, we either need a no-op
6912 // or a truncation.
6913 SDValue Shift = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: MVT::i32,
6914 Operand: VSNOp0.getOperand(i: Index));
6915 return DAG.getNode(Opcode: ByScalar, DL, VT, N1: Op0, N2: Shift);
6916 }
6917 }
6918 }
6919
6920 // Otherwise just treat the current form as legal.
6921 return Op;
6922}
6923
6924SDValue SystemZTargetLowering::lowerFSHL(SDValue Op, SelectionDAG &DAG) const {
6925 SDLoc DL(Op);
6926
6927 // i128 FSHL with a constant amount that is a multiple of 8 can be
6928 // implemented via VECTOR_SHUFFLE. If we have the vector-enhancements-2
6929 // facility, FSHL with a constant amount less than 8 can be implemented
6930 // via SHL_DOUBLE_BIT, and FSHL with other constant amounts by a
6931 // combination of the two.
6932 if (auto *ShiftAmtNode = dyn_cast<ConstantSDNode>(Val: Op.getOperand(i: 2))) {
6933 uint64_t ShiftAmt = ShiftAmtNode->getZExtValue() & 127;
6934 if ((ShiftAmt & 7) == 0 || Subtarget.hasVectorEnhancements2()) {
6935 SDValue Op0 = DAG.getBitcast(VT: MVT::v16i8, V: Op.getOperand(i: 0));
6936 SDValue Op1 = DAG.getBitcast(VT: MVT::v16i8, V: Op.getOperand(i: 1));
6937 if (ShiftAmt > 120) {
6938 // For N in 121..128, fshl N == fshr (128 - N), and for 1 <= N < 8
6939 // SHR_DOUBLE_BIT emits fewer instructions.
6940 SDValue Val =
6941 DAG.getNode(Opcode: SystemZISD::SHR_DOUBLE_BIT, DL, VT: MVT::v16i8, N1: Op0, N2: Op1,
6942 N3: DAG.getTargetConstant(Val: 128 - ShiftAmt, DL, VT: MVT::i32));
6943 return DAG.getBitcast(VT: MVT::i128, V: Val);
6944 }
6945 SmallVector<int, 16> Mask(16);
6946 for (unsigned Elt = 0; Elt < 16; Elt++)
6947 Mask[Elt] = (ShiftAmt >> 3) + Elt;
6948 SDValue Shuf1 = DAG.getVectorShuffle(VT: MVT::v16i8, dl: DL, N1: Op0, N2: Op1, Mask);
6949 if ((ShiftAmt & 7) == 0)
6950 return DAG.getBitcast(VT: MVT::i128, V: Shuf1);
6951 SDValue Shuf2 = DAG.getVectorShuffle(VT: MVT::v16i8, dl: DL, N1: Op1, N2: Op1, Mask);
6952 SDValue Val =
6953 DAG.getNode(Opcode: SystemZISD::SHL_DOUBLE_BIT, DL, VT: MVT::v16i8, N1: Shuf1, N2: Shuf2,
6954 N3: DAG.getTargetConstant(Val: ShiftAmt & 7, DL, VT: MVT::i32));
6955 return DAG.getBitcast(VT: MVT::i128, V: Val);
6956 }
6957 }
6958
6959 return SDValue();
6960}
6961
6962SDValue SystemZTargetLowering::lowerFSHR(SDValue Op, SelectionDAG &DAG) const {
6963 SDLoc DL(Op);
6964
6965 // i128 FSHR with a constant amount that is a multiple of 8 can be
6966 // implemented via VECTOR_SHUFFLE. If we have the vector-enhancements-2
6967 // facility, FSHR with a constant amount less than 8 can be implemented
6968 // via SHR_DOUBLE_BIT, and FSHR with other constant amounts by a
6969 // combination of the two.
6970 if (auto *ShiftAmtNode = dyn_cast<ConstantSDNode>(Val: Op.getOperand(i: 2))) {
6971 uint64_t ShiftAmt = ShiftAmtNode->getZExtValue() & 127;
6972 if ((ShiftAmt & 7) == 0 || Subtarget.hasVectorEnhancements2()) {
6973 SDValue Op0 = DAG.getBitcast(VT: MVT::v16i8, V: Op.getOperand(i: 0));
6974 SDValue Op1 = DAG.getBitcast(VT: MVT::v16i8, V: Op.getOperand(i: 1));
6975 if (ShiftAmt > 120) {
6976 // For N in 121..128, fshr N == fshl (128 - N), and for 1 <= N < 8
6977 // SHL_DOUBLE_BIT emits fewer instructions.
6978 SDValue Val =
6979 DAG.getNode(Opcode: SystemZISD::SHL_DOUBLE_BIT, DL, VT: MVT::v16i8, N1: Op0, N2: Op1,
6980 N3: DAG.getTargetConstant(Val: 128 - ShiftAmt, DL, VT: MVT::i32));
6981 return DAG.getBitcast(VT: MVT::i128, V: Val);
6982 }
6983 SmallVector<int, 16> Mask(16);
6984 for (unsigned Elt = 0; Elt < 16; Elt++)
6985 Mask[Elt] = 16 - (ShiftAmt >> 3) + Elt;
6986 SDValue Shuf1 = DAG.getVectorShuffle(VT: MVT::v16i8, dl: DL, N1: Op0, N2: Op1, Mask);
6987 if ((ShiftAmt & 7) == 0)
6988 return DAG.getBitcast(VT: MVT::i128, V: Shuf1);
6989 SDValue Shuf2 = DAG.getVectorShuffle(VT: MVT::v16i8, dl: DL, N1: Op0, N2: Op0, Mask);
6990 SDValue Val =
6991 DAG.getNode(Opcode: SystemZISD::SHR_DOUBLE_BIT, DL, VT: MVT::v16i8, N1: Shuf2, N2: Shuf1,
6992 N3: DAG.getTargetConstant(Val: ShiftAmt & 7, DL, VT: MVT::i32));
6993 return DAG.getBitcast(VT: MVT::i128, V: Val);
6994 }
6995 }
6996
6997 return SDValue();
6998}
6999
7000static SDValue lowerAddrSpaceCast(SDValue Op, SelectionDAG &DAG) {
7001 SDLoc DL(Op);
7002 SDValue Src = Op.getOperand(i: 0);
7003 MVT DstVT = Op.getSimpleValueType();
7004
7005 AddrSpaceCastSDNode *N = cast<AddrSpaceCastSDNode>(Val: Op.getNode());
7006 unsigned SrcAS = N->getSrcAddressSpace();
7007
7008 assert(SrcAS != N->getDestAddressSpace() &&
7009 "addrspacecast must be between different address spaces");
7010
7011 // addrspacecast [0 <- 1] : Assinging a ptr32 value to a 64-bit pointer.
7012 // addrspacecast [1 <- 0] : Assigining a 64-bit pointer to a ptr32 value.
7013 if (SrcAS == SYSTEMZAS::PTR32 && DstVT == MVT::i64) {
7014 Op = DAG.getNode(Opcode: ISD::AND, DL, VT: MVT::i32, N1: Src,
7015 N2: DAG.getConstant(Val: 0x7fffffff, DL, VT: MVT::i32));
7016 Op = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: DstVT, Operand: Op);
7017 } else if (DstVT == MVT::i32) {
7018 Op = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: DstVT, Operand: Src);
7019 Op = DAG.getNode(Opcode: ISD::AND, DL, VT: MVT::i32, N1: Op,
7020 N2: DAG.getConstant(Val: 0x7fffffff, DL, VT: MVT::i32));
7021 Op = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: DstVT, Operand: Op);
7022 } else {
7023 report_fatal_error(reason: "Bad address space in addrspacecast");
7024 }
7025 return Op;
7026}
7027
7028SDValue SystemZTargetLowering::lowerFP_EXTEND(SDValue Op,
7029 SelectionDAG &DAG) const {
7030 SDValue In = Op.getOperand(i: Op->isStrictFPOpcode() ? 1 : 0);
7031 if (In.getSimpleValueType() != MVT::f16)
7032 return Op; // Legal
7033 return SDValue(); // Let legalizer emit the libcall.
7034}
7035
7036SDValue SystemZTargetLowering::useLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
7037 MVT VT, SDValue Arg, SDLoc DL,
7038 SDValue Chain, bool IsStrict) const {
7039 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected request for libcall!");
7040 MakeLibCallOptions CallOptions;
7041 SDValue Result;
7042 std::tie(args&: Result, args&: Chain) =
7043 makeLibCall(DAG, LC, RetVT: VT, Ops: Arg, CallOptions, dl: DL, Chain);
7044 return IsStrict ? DAG.getMergeValues(Ops: {Result, Chain}, dl: DL) : Result;
7045}
7046
7047SDValue SystemZTargetLowering::lower_FP_TO_INT(SDValue Op,
7048 SelectionDAG &DAG) const {
7049 bool IsSigned = (Op->getOpcode() == ISD::FP_TO_SINT ||
7050 Op->getOpcode() == ISD::STRICT_FP_TO_SINT);
7051 bool IsStrict = Op->isStrictFPOpcode();
7052 SDLoc DL(Op);
7053 MVT VT = Op.getSimpleValueType();
7054 SDValue InOp = Op.getOperand(i: IsStrict ? 1 : 0);
7055 SDValue Chain = IsStrict ? Op.getOperand(i: 0) : DAG.getEntryNode();
7056 EVT InVT = InOp.getValueType();
7057
7058 // FP to unsigned is not directly supported on z10. Promoting an i32
7059 // result to (signed) i64 doesn't generate an inexact condition (fp
7060 // exception) for values that are outside the i32 range but in the i64
7061 // range, so use the default expansion.
7062 if (!Subtarget.hasFPExtension() && !IsSigned)
7063 // Expand i32/i64. F16 values will be recognized to fit and extended.
7064 return SDValue();
7065
7066 // Conversion from f16 is done via f32.
7067 if (InOp.getSimpleValueType() == MVT::f16) {
7068 SmallVector<SDValue, 2> Results;
7069 LowerOperationWrapper(N: Op.getNode(), Results, DAG);
7070 return DAG.getMergeValues(Ops: Results, dl: DL);
7071 }
7072
7073 if (VT == MVT::i128) {
7074 RTLIB::Libcall LC =
7075 IsSigned ? RTLIB::getFPTOSINT(OpVT: InVT, RetVT: VT) : RTLIB::getFPTOUINT(OpVT: InVT, RetVT: VT);
7076 return useLibCall(DAG, LC, VT, Arg: InOp, DL, Chain, IsStrict);
7077 }
7078
7079 return Op; // Legal
7080}
7081
7082SDValue SystemZTargetLowering::lower_INT_TO_FP(SDValue Op,
7083 SelectionDAG &DAG) const {
7084 bool IsSigned = (Op->getOpcode() == ISD::SINT_TO_FP ||
7085 Op->getOpcode() == ISD::STRICT_SINT_TO_FP);
7086 bool IsStrict = Op->isStrictFPOpcode();
7087 SDLoc DL(Op);
7088 MVT VT = Op.getSimpleValueType();
7089 SDValue InOp = Op.getOperand(i: IsStrict ? 1 : 0);
7090 SDValue Chain = IsStrict ? Op.getOperand(i: 0) : DAG.getEntryNode();
7091 EVT InVT = InOp.getValueType();
7092
7093 // Conversion to f16 is done via f32.
7094 if (VT == MVT::f16) {
7095 SmallVector<SDValue, 2> Results;
7096 LowerOperationWrapper(N: Op.getNode(), Results, DAG);
7097 return DAG.getMergeValues(Ops: Results, dl: DL);
7098 }
7099
7100 // Unsigned to fp is not directly supported on z10.
7101 if (!Subtarget.hasFPExtension() && !IsSigned)
7102 return SDValue(); // Expand i64.
7103
7104 if (InVT == MVT::i128) {
7105 RTLIB::Libcall LC =
7106 IsSigned ? RTLIB::getSINTTOFP(OpVT: InVT, RetVT: VT) : RTLIB::getUINTTOFP(OpVT: InVT, RetVT: VT);
7107 return useLibCall(DAG, LC, VT, Arg: InOp, DL, Chain, IsStrict);
7108 }
7109
7110 return Op; // Legal
7111}
7112
7113// Lower an f16 LOAD in case of no vector support.
7114SDValue SystemZTargetLowering::lowerLoadF16(SDValue Op,
7115 SelectionDAG &DAG) const {
7116 EVT RegVT = Op.getValueType();
7117 assert(RegVT == MVT::f16 && "Expected to lower an f16 load.");
7118 (void)RegVT;
7119
7120 // Load as integer.
7121 SDLoc DL(Op);
7122 SDValue NewLd;
7123 if (auto *AtomicLd = dyn_cast<AtomicSDNode>(Val: Op.getNode())) {
7124 assert(EVT(RegVT) == AtomicLd->getMemoryVT() && "Unhandled f16 load");
7125 NewLd = DAG.getAtomicLoad(ExtType: ISD::EXTLOAD, dl: DL, MemVT: MVT::i16, VT: MVT::i64,
7126 Chain: AtomicLd->getChain(), Ptr: AtomicLd->getBasePtr(),
7127 MMO: AtomicLd->getMemOperand());
7128 } else {
7129 LoadSDNode *Ld = cast<LoadSDNode>(Val: Op.getNode());
7130 assert(EVT(RegVT) == Ld->getMemoryVT() && "Unhandled f16 load");
7131 NewLd = DAG.getExtLoad(ExtType: ISD::EXTLOAD, dl: DL, VT: MVT::i64, Chain: Ld->getChain(),
7132 Ptr: Ld->getBasePtr(), PtrInfo: Ld->getPointerInfo(), MemVT: MVT::i16,
7133 Alignment: Ld->getBaseAlign(), MMOFlags: Ld->getMemOperand()->getFlags());
7134 }
7135 SDValue F16Val = convertToF16(Op: NewLd, DAG);
7136 return DAG.getMergeValues(Ops: {F16Val, NewLd.getValue(R: 1)}, dl: DL);
7137}
7138
7139// Lower an f16 STORE in case of no vector support.
7140SDValue SystemZTargetLowering::lowerStoreF16(SDValue Op,
7141 SelectionDAG &DAG) const {
7142 SDLoc DL(Op);
7143 SDValue Shft = convertFromF16(Op: Op->getOperand(Num: 1), DL, DAG);
7144
7145 if (auto *AtomicSt = dyn_cast<AtomicSDNode>(Val: Op.getNode()))
7146 return DAG.getAtomic(Opcode: ISD::ATOMIC_STORE, dl: DL, MemVT: MVT::i16, Chain: AtomicSt->getChain(),
7147 Ptr: Shft, Val: AtomicSt->getBasePtr(),
7148 MMO: AtomicSt->getMemOperand());
7149
7150 StoreSDNode *St = cast<StoreSDNode>(Val: Op.getNode());
7151 return DAG.getTruncStore(Chain: St->getChain(), dl: DL, Val: Shft, Ptr: St->getBasePtr(), SVT: MVT::i16,
7152 MMO: St->getMemOperand());
7153}
7154
7155SDValue SystemZTargetLowering::lowerIS_FPCLASS(SDValue Op,
7156 SelectionDAG &DAG) const {
7157 SDLoc DL(Op);
7158 MVT ResultVT = Op.getSimpleValueType();
7159 SDValue Arg = Op.getOperand(i: 0);
7160 unsigned Check = Op.getConstantOperandVal(i: 1);
7161
7162 unsigned TDCMask = 0;
7163 if (Check & fcSNan)
7164 TDCMask |= SystemZ::TDCMASK_SNAN_PLUS | SystemZ::TDCMASK_SNAN_MINUS;
7165 if (Check & fcQNan)
7166 TDCMask |= SystemZ::TDCMASK_QNAN_PLUS | SystemZ::TDCMASK_QNAN_MINUS;
7167 if (Check & fcPosInf)
7168 TDCMask |= SystemZ::TDCMASK_INFINITY_PLUS;
7169 if (Check & fcNegInf)
7170 TDCMask |= SystemZ::TDCMASK_INFINITY_MINUS;
7171 if (Check & fcPosNormal)
7172 TDCMask |= SystemZ::TDCMASK_NORMAL_PLUS;
7173 if (Check & fcNegNormal)
7174 TDCMask |= SystemZ::TDCMASK_NORMAL_MINUS;
7175 if (Check & fcPosSubnormal)
7176 TDCMask |= SystemZ::TDCMASK_SUBNORMAL_PLUS;
7177 if (Check & fcNegSubnormal)
7178 TDCMask |= SystemZ::TDCMASK_SUBNORMAL_MINUS;
7179 if (Check & fcPosZero)
7180 TDCMask |= SystemZ::TDCMASK_ZERO_PLUS;
7181 if (Check & fcNegZero)
7182 TDCMask |= SystemZ::TDCMASK_ZERO_MINUS;
7183 SDValue TDCMaskV = DAG.getConstant(Val: TDCMask, DL, VT: MVT::i64);
7184
7185 SDValue Intr = DAG.getNode(Opcode: SystemZISD::TDC, DL, VT: ResultVT, N1: Arg, N2: TDCMaskV);
7186 return getCCResult(DAG, CCReg: Intr);
7187}
7188
7189SDValue SystemZTargetLowering::lowerREADCYCLECOUNTER(SDValue Op,
7190 SelectionDAG &DAG) const {
7191 SDLoc DL(Op);
7192 SDValue Chain = Op.getOperand(i: 0);
7193
7194 // STCKF only supports a memory operand, so we have to use a temporary.
7195 SDValue StackPtr = DAG.CreateStackTemporary(VT: MVT::i64);
7196 int SPFI = cast<FrameIndexSDNode>(Val: StackPtr.getNode())->getIndex();
7197 MachinePointerInfo MPI =
7198 MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI: SPFI);
7199
7200 // Use STCFK to store the TOD clock into the temporary.
7201 SDValue StoreOps[] = {Chain, StackPtr};
7202 Chain = DAG.getMemIntrinsicNode(
7203 Opcode: SystemZISD::STCKF, dl: DL, VTList: DAG.getVTList(VT: MVT::Other), Ops: StoreOps, MemVT: MVT::i64,
7204 PtrInfo: MPI, Alignment: MaybeAlign(), Flags: MachineMemOperand::MOStore);
7205
7206 // And read it back from there.
7207 return DAG.getLoad(VT: MVT::i64, dl: DL, Chain, Ptr: StackPtr, PtrInfo: MPI);
7208}
7209
7210SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
7211 SelectionDAG &DAG) const {
7212 switch (Op.getOpcode()) {
7213 case ISD::FRAMEADDR:
7214 return lowerFRAMEADDR(Op, DAG);
7215 case ISD::RETURNADDR:
7216 return lowerRETURNADDR(Op, DAG);
7217 case ISD::BR_CC:
7218 return lowerBR_CC(Op, DAG);
7219 case ISD::SELECT_CC:
7220 return lowerSELECT_CC(Op, DAG);
7221 case ISD::SETCC:
7222 return lowerSETCC(Op, DAG);
7223 case ISD::STRICT_FSETCC:
7224 return lowerSTRICT_FSETCC(Op, DAG, IsSignaling: false);
7225 case ISD::STRICT_FSETCCS:
7226 return lowerSTRICT_FSETCC(Op, DAG, IsSignaling: true);
7227 case ISD::GlobalAddress:
7228 return lowerGlobalAddress(Node: cast<GlobalAddressSDNode>(Val&: Op), DAG);
7229 case ISD::GlobalTLSAddress:
7230 return lowerGlobalTLSAddress(Node: cast<GlobalAddressSDNode>(Val&: Op), DAG);
7231 case ISD::BlockAddress:
7232 return lowerBlockAddress(Node: cast<BlockAddressSDNode>(Val&: Op), DAG);
7233 case ISD::JumpTable:
7234 return lowerJumpTable(JT: cast<JumpTableSDNode>(Val&: Op), DAG);
7235 case ISD::ConstantPool:
7236 return lowerConstantPool(CP: cast<ConstantPoolSDNode>(Val&: Op), DAG);
7237 case ISD::BITCAST:
7238 return lowerBITCAST(Op, DAG);
7239 case ISD::VASTART:
7240 return lowerVASTART(Op, DAG);
7241 case ISD::VACOPY:
7242 return lowerVACOPY(Op, DAG);
7243 case ISD::DYNAMIC_STACKALLOC:
7244 return lowerDYNAMIC_STACKALLOC(Op, DAG);
7245 case ISD::GET_DYNAMIC_AREA_OFFSET:
7246 return lowerGET_DYNAMIC_AREA_OFFSET(Op, DAG);
7247 case ISD::MULHS:
7248 return lowerMULH(Op, DAG, Opcode: SystemZISD::SMUL_LOHI);
7249 case ISD::MULHU:
7250 return lowerMULH(Op, DAG, Opcode: SystemZISD::UMUL_LOHI);
7251 case ISD::SMUL_LOHI:
7252 return lowerSMUL_LOHI(Op, DAG);
7253 case ISD::UMUL_LOHI:
7254 return lowerUMUL_LOHI(Op, DAG);
7255 case ISD::SDIVREM:
7256 return lowerSDIVREM(Op, DAG);
7257 case ISD::UDIVREM:
7258 return lowerUDIVREM(Op, DAG);
7259 case ISD::SADDO:
7260 case ISD::SSUBO:
7261 case ISD::UADDO:
7262 case ISD::USUBO:
7263 return lowerXALUO(Op, DAG);
7264 case ISD::UADDO_CARRY:
7265 case ISD::USUBO_CARRY:
7266 return lowerUADDSUBO_CARRY(Op, DAG);
7267 case ISD::OR:
7268 return lowerOR(Op, DAG);
7269 case ISD::CTPOP:
7270 return lowerCTPOP(Op, DAG);
7271 case ISD::VECREDUCE_ADD:
7272 return lowerVECREDUCE_ADD(Op, DAG);
7273 case ISD::ATOMIC_FENCE:
7274 return lowerATOMIC_FENCE(Op, DAG);
7275 case ISD::ATOMIC_SWAP:
7276 return lowerATOMIC_LOAD_OP(Op, DAG, Opcode: SystemZISD::ATOMIC_SWAPW);
7277 case ISD::ATOMIC_STORE:
7278 return lowerATOMIC_STORE(Op, DAG);
7279 case ISD::ATOMIC_LOAD:
7280 return lowerATOMIC_LOAD(Op, DAG);
7281 case ISD::ATOMIC_LOAD_ADD:
7282 return lowerATOMIC_LOAD_OP(Op, DAG, Opcode: SystemZISD::ATOMIC_LOADW_ADD);
7283 case ISD::ATOMIC_LOAD_SUB:
7284 return lowerATOMIC_LOAD_SUB(Op, DAG);
7285 case ISD::ATOMIC_LOAD_AND:
7286 return lowerATOMIC_LOAD_OP(Op, DAG, Opcode: SystemZISD::ATOMIC_LOADW_AND);
7287 case ISD::ATOMIC_LOAD_OR:
7288 return lowerATOMIC_LOAD_OP(Op, DAG, Opcode: SystemZISD::ATOMIC_LOADW_OR);
7289 case ISD::ATOMIC_LOAD_XOR:
7290 return lowerATOMIC_LOAD_OP(Op, DAG, Opcode: SystemZISD::ATOMIC_LOADW_XOR);
7291 case ISD::ATOMIC_LOAD_NAND:
7292 return lowerATOMIC_LOAD_OP(Op, DAG, Opcode: SystemZISD::ATOMIC_LOADW_NAND);
7293 case ISD::ATOMIC_LOAD_MIN:
7294 return lowerATOMIC_LOAD_OP(Op, DAG, Opcode: SystemZISD::ATOMIC_LOADW_MIN);
7295 case ISD::ATOMIC_LOAD_MAX:
7296 return lowerATOMIC_LOAD_OP(Op, DAG, Opcode: SystemZISD::ATOMIC_LOADW_MAX);
7297 case ISD::ATOMIC_LOAD_UMIN:
7298 return lowerATOMIC_LOAD_OP(Op, DAG, Opcode: SystemZISD::ATOMIC_LOADW_UMIN);
7299 case ISD::ATOMIC_LOAD_UMAX:
7300 return lowerATOMIC_LOAD_OP(Op, DAG, Opcode: SystemZISD::ATOMIC_LOADW_UMAX);
7301 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
7302 return lowerATOMIC_CMP_SWAP(Op, DAG);
7303 case ISD::STACKSAVE:
7304 return lowerSTACKSAVE(Op, DAG);
7305 case ISD::STACKRESTORE:
7306 return lowerSTACKRESTORE(Op, DAG);
7307 case ISD::PREFETCH:
7308 return lowerPREFETCH(Op, DAG);
7309 case ISD::INTRINSIC_W_CHAIN:
7310 return lowerINTRINSIC_W_CHAIN(Op, DAG);
7311 case ISD::INTRINSIC_WO_CHAIN:
7312 return lowerINTRINSIC_WO_CHAIN(Op, DAG);
7313 case ISD::BUILD_VECTOR:
7314 return lowerBUILD_VECTOR(Op, DAG);
7315 case ISD::VECTOR_SHUFFLE:
7316 return lowerVECTOR_SHUFFLE(Op, DAG);
7317 case ISD::SCALAR_TO_VECTOR:
7318 return lowerSCALAR_TO_VECTOR(Op, DAG);
7319 case ISD::INSERT_VECTOR_ELT:
7320 return lowerINSERT_VECTOR_ELT(Op, DAG);
7321 case ISD::EXTRACT_VECTOR_ELT:
7322 return lowerEXTRACT_VECTOR_ELT(Op, DAG);
7323 case ISD::SIGN_EXTEND_VECTOR_INREG:
7324 return lowerSIGN_EXTEND_VECTOR_INREG(Op, DAG);
7325 case ISD::ZERO_EXTEND_VECTOR_INREG:
7326 return lowerZERO_EXTEND_VECTOR_INREG(Op, DAG);
7327 case ISD::SHL:
7328 return lowerShift(Op, DAG, ByScalar: SystemZISD::VSHL_BY_SCALAR);
7329 case ISD::SRL:
7330 return lowerShift(Op, DAG, ByScalar: SystemZISD::VSRL_BY_SCALAR);
7331 case ISD::SRA:
7332 return lowerShift(Op, DAG, ByScalar: SystemZISD::VSRA_BY_SCALAR);
7333 case ISD::ADDRSPACECAST:
7334 return lowerAddrSpaceCast(Op, DAG);
7335 case ISD::ROTL:
7336 return lowerShift(Op, DAG, ByScalar: SystemZISD::VROTL_BY_SCALAR);
7337 case ISD::FSHL:
7338 return lowerFSHL(Op, DAG);
7339 case ISD::FSHR:
7340 return lowerFSHR(Op, DAG);
7341 case ISD::FP_EXTEND:
7342 case ISD::STRICT_FP_EXTEND:
7343 return lowerFP_EXTEND(Op, DAG);
7344 case ISD::FP_TO_UINT:
7345 case ISD::FP_TO_SINT:
7346 case ISD::STRICT_FP_TO_UINT:
7347 case ISD::STRICT_FP_TO_SINT:
7348 return lower_FP_TO_INT(Op, DAG);
7349 case ISD::UINT_TO_FP:
7350 case ISD::SINT_TO_FP:
7351 case ISD::STRICT_UINT_TO_FP:
7352 case ISD::STRICT_SINT_TO_FP:
7353 return lower_INT_TO_FP(Op, DAG);
7354 case ISD::LOAD:
7355 return lowerLoadF16(Op, DAG);
7356 case ISD::STORE:
7357 return lowerStoreF16(Op, DAG);
7358 case ISD::IS_FPCLASS:
7359 return lowerIS_FPCLASS(Op, DAG);
7360 case ISD::GET_ROUNDING:
7361 return lowerGET_ROUNDING(Op, DAG);
7362 case ISD::READCYCLECOUNTER:
7363 return lowerREADCYCLECOUNTER(Op, DAG);
7364 case ISD::EH_SJLJ_SETJMP:
7365 case ISD::EH_SJLJ_LONGJMP:
7366 // These operations are legal on our platform, but we cannot actually
7367 // set the operation action to Legal as common code would treat this
7368 // as equivalent to Expand. Instead, we keep the operation action to
7369 // Custom and just leave them unchanged here.
7370 return Op;
7371
7372 default:
7373 llvm_unreachable("Unexpected node to lower");
7374 }
7375}
7376
7377static SDValue expandBitCastI128ToF128(SelectionDAG &DAG, SDValue Src,
7378 const SDLoc &SL) {
7379 // If i128 is legal, just use a normal bitcast.
7380 if (DAG.getTargetLoweringInfo().isTypeLegal(VT: MVT::i128))
7381 return DAG.getBitcast(VT: MVT::f128, V: Src);
7382
7383 // Otherwise, f128 must live in FP128, so do a partwise move.
7384 assert(DAG.getTargetLoweringInfo().getRepRegClassFor(MVT::f128) ==
7385 &SystemZ::FP128BitRegClass);
7386
7387 SDValue Hi, Lo;
7388 std::tie(args&: Lo, args&: Hi) = DAG.SplitScalar(N: Src, DL: SL, LoVT: MVT::i64, HiVT: MVT::i64);
7389
7390 Hi = DAG.getBitcast(VT: MVT::f64, V: Hi);
7391 Lo = DAG.getBitcast(VT: MVT::f64, V: Lo);
7392
7393 SDNode *Pair = DAG.getMachineNode(
7394 Opcode: SystemZ::REG_SEQUENCE, dl: SL, VT: MVT::f128,
7395 Ops: {DAG.getTargetConstant(Val: SystemZ::FP128BitRegClassID, DL: SL, VT: MVT::i32), Lo,
7396 DAG.getTargetConstant(Val: SystemZ::subreg_l64, DL: SL, VT: MVT::i32), Hi,
7397 DAG.getTargetConstant(Val: SystemZ::subreg_h64, DL: SL, VT: MVT::i32)});
7398 return SDValue(Pair, 0);
7399}
7400
7401static SDValue expandBitCastF128ToI128(SelectionDAG &DAG, SDValue Src,
7402 const SDLoc &SL) {
7403 // If i128 is legal, just use a normal bitcast.
7404 if (DAG.getTargetLoweringInfo().isTypeLegal(VT: MVT::i128))
7405 return DAG.getBitcast(VT: MVT::i128, V: Src);
7406
7407 // Otherwise, f128 must live in FP128, so do a partwise move.
7408 assert(DAG.getTargetLoweringInfo().getRepRegClassFor(MVT::f128) ==
7409 &SystemZ::FP128BitRegClass);
7410
7411 SDValue LoFP =
7412 DAG.getTargetExtractSubreg(SRIdx: SystemZ::subreg_l64, DL: SL, VT: MVT::f64, Operand: Src);
7413 SDValue HiFP =
7414 DAG.getTargetExtractSubreg(SRIdx: SystemZ::subreg_h64, DL: SL, VT: MVT::f64, Operand: Src);
7415 SDValue Lo = DAG.getNode(Opcode: ISD::BITCAST, DL: SL, VT: MVT::i64, Operand: LoFP);
7416 SDValue Hi = DAG.getNode(Opcode: ISD::BITCAST, DL: SL, VT: MVT::i64, Operand: HiFP);
7417
7418 return DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: SL, VT: MVT::i128, N1: Lo, N2: Hi);
7419}
7420
7421// Lower operations with invalid operand or result types.
7422void
7423SystemZTargetLowering::LowerOperationWrapper(SDNode *N,
7424 SmallVectorImpl<SDValue> &Results,
7425 SelectionDAG &DAG) const {
7426 switch (N->getOpcode()) {
7427 case ISD::ATOMIC_LOAD: {
7428 SDLoc DL(N);
7429 SDVTList Tys = DAG.getVTList(VT1: MVT::Untyped, VT2: MVT::Other);
7430 SDValue Ops[] = { N->getOperand(Num: 0), N->getOperand(Num: 1) };
7431 MachineMemOperand *MMO = cast<AtomicSDNode>(Val: N)->getMemOperand();
7432 SDValue Res = DAG.getMemIntrinsicNode(Opcode: SystemZISD::ATOMIC_LOAD_128,
7433 dl: DL, VTList: Tys, Ops, MemVT: MVT::i128, MMO);
7434
7435 SDValue Lowered = lowerGR128ToI128(DAG, In: Res);
7436 if (N->getValueType(ResNo: 0) == MVT::f128)
7437 Lowered = expandBitCastI128ToF128(DAG, Src: Lowered, SL: DL);
7438 Results.push_back(Elt: Lowered);
7439 Results.push_back(Elt: Res.getValue(R: 1));
7440 break;
7441 }
7442 case ISD::ATOMIC_STORE: {
7443 SDLoc DL(N);
7444 SDVTList Tys = DAG.getVTList(VT: MVT::Other);
7445 SDValue Val = N->getOperand(Num: 1);
7446 if (Val.getValueType() == MVT::f128)
7447 Val = expandBitCastF128ToI128(DAG, Src: Val, SL: DL);
7448 Val = lowerI128ToGR128(DAG, In: Val);
7449
7450 SDValue Ops[] = {N->getOperand(Num: 0), Val, N->getOperand(Num: 2)};
7451 MachineMemOperand *MMO = cast<AtomicSDNode>(Val: N)->getMemOperand();
7452 SDValue Res = DAG.getMemIntrinsicNode(Opcode: SystemZISD::ATOMIC_STORE_128,
7453 dl: DL, VTList: Tys, Ops, MemVT: MVT::i128, MMO);
7454 // We have to enforce sequential consistency by performing a
7455 // serialization operation after the store.
7456 if (cast<AtomicSDNode>(Val: N)->getSuccessOrdering() ==
7457 AtomicOrdering::SequentiallyConsistent)
7458 Res = SDValue(DAG.getMachineNode(Opcode: SystemZ::Serialize, dl: DL,
7459 VT: MVT::Other, Op1: Res), 0);
7460 Results.push_back(Elt: Res);
7461 break;
7462 }
7463 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
7464 SDLoc DL(N);
7465 SDVTList Tys = DAG.getVTList(VT1: MVT::Untyped, VT2: MVT::i32, VT3: MVT::Other);
7466 SDValue Ops[] = { N->getOperand(Num: 0), N->getOperand(Num: 1),
7467 lowerI128ToGR128(DAG, In: N->getOperand(Num: 2)),
7468 lowerI128ToGR128(DAG, In: N->getOperand(Num: 3)) };
7469 MachineMemOperand *MMO = cast<AtomicSDNode>(Val: N)->getMemOperand();
7470 SDValue Res = DAG.getMemIntrinsicNode(Opcode: SystemZISD::ATOMIC_CMP_SWAP_128,
7471 dl: DL, VTList: Tys, Ops, MemVT: MVT::i128, MMO);
7472 SDValue Success = emitSETCC(DAG, DL, CCReg: Res.getValue(R: 1),
7473 CCValid: SystemZ::CCMASK_CS, CCMask: SystemZ::CCMASK_CS_EQ);
7474 Success = DAG.getZExtOrTrunc(Op: Success, DL, VT: N->getValueType(ResNo: 1));
7475 Results.push_back(Elt: lowerGR128ToI128(DAG, In: Res));
7476 Results.push_back(Elt: Success);
7477 Results.push_back(Elt: Res.getValue(R: 2));
7478 break;
7479 }
7480 case ISD::BITCAST: {
7481 if (useSoftFloat())
7482 return;
7483 SDLoc DL(N);
7484 SDValue Src = N->getOperand(Num: 0);
7485 EVT SrcVT = Src.getValueType();
7486 EVT ResVT = N->getValueType(ResNo: 0);
7487 if (ResVT == MVT::i128 && SrcVT == MVT::f128)
7488 Results.push_back(Elt: expandBitCastF128ToI128(DAG, Src, SL: DL));
7489 else if (SrcVT == MVT::i16 && ResVT == MVT::f16) {
7490 if (Subtarget.hasVector()) {
7491 SDValue In32 = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: MVT::i32, Operand: Src);
7492 Results.push_back(Elt: SDValue(
7493 DAG.getMachineNode(Opcode: SystemZ::LEFR_16, dl: DL, VT: MVT::f16, Op1: In32), 0));
7494 } else {
7495 SDValue In64 = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: MVT::i64, Operand: Src);
7496 Results.push_back(Elt: convertToF16(Op: In64, DAG));
7497 }
7498 } else if (SrcVT == MVT::f16 && ResVT == MVT::i16) {
7499 SDValue ExtractedVal =
7500 Subtarget.hasVector()
7501 ? SDValue(DAG.getMachineNode(Opcode: SystemZ::LFER_16, dl: DL, VT: MVT::i32, Op1: Src),
7502 0)
7503 : convertFromF16(Op: Src, DL, DAG);
7504 Results.push_back(Elt: DAG.getZExtOrTrunc(Op: ExtractedVal, DL, VT: ResVT));
7505 }
7506 break;
7507 }
7508 case ISD::UINT_TO_FP:
7509 case ISD::SINT_TO_FP:
7510 case ISD::STRICT_UINT_TO_FP:
7511 case ISD::STRICT_SINT_TO_FP: {
7512 if (useSoftFloat())
7513 return;
7514 bool IsStrict = N->isStrictFPOpcode();
7515 SDLoc DL(N);
7516 SDValue InOp = N->getOperand(Num: IsStrict ? 1 : 0);
7517 EVT ResVT = N->getValueType(ResNo: 0);
7518 SDValue Chain = IsStrict ? N->getOperand(Num: 0) : DAG.getEntryNode();
7519 if (ResVT == MVT::f16) {
7520 if (!IsStrict) {
7521 SDValue OpF32 = DAG.getNode(Opcode: N->getOpcode(), DL, VT: MVT::f32, Operand: InOp);
7522 Results.push_back(Elt: DAG.getFPExtendOrRound(Op: OpF32, DL, VT: MVT::f16));
7523 } else {
7524 SDValue OpF32 =
7525 DAG.getNode(Opcode: N->getOpcode(), DL, VTList: DAG.getVTList(VT1: MVT::f32, VT2: MVT::Other),
7526 Ops: {Chain, InOp});
7527 SDValue F16Res;
7528 std::tie(args&: F16Res, args&: Chain) = DAG.getStrictFPExtendOrRound(
7529 Op: OpF32, Chain: OpF32.getValue(R: 1), DL, VT: MVT::f16);
7530 Results.push_back(Elt: F16Res);
7531 Results.push_back(Elt: Chain);
7532 }
7533 }
7534 break;
7535 }
7536 case ISD::FP_TO_UINT:
7537 case ISD::FP_TO_SINT:
7538 case ISD::STRICT_FP_TO_UINT:
7539 case ISD::STRICT_FP_TO_SINT: {
7540 if (useSoftFloat())
7541 return;
7542 bool IsStrict = N->isStrictFPOpcode();
7543 SDLoc DL(N);
7544 EVT ResVT = N->getValueType(ResNo: 0);
7545 SDValue InOp = N->getOperand(Num: IsStrict ? 1 : 0);
7546 EVT InVT = InOp->getValueType(ResNo: 0);
7547 SDValue Chain = IsStrict ? N->getOperand(Num: 0) : DAG.getEntryNode();
7548 if (InVT == MVT::f16) {
7549 if (!IsStrict) {
7550 SDValue InF32 = DAG.getFPExtendOrRound(Op: InOp, DL, VT: MVT::f32);
7551 Results.push_back(Elt: DAG.getNode(Opcode: N->getOpcode(), DL, VT: ResVT, Operand: InF32));
7552 } else {
7553 SDValue InF32;
7554 std::tie(args&: InF32, args&: Chain) =
7555 DAG.getStrictFPExtendOrRound(Op: InOp, Chain, DL, VT: MVT::f32);
7556 SDValue OpF32 =
7557 DAG.getNode(Opcode: N->getOpcode(), DL, VTList: DAG.getVTList(VT1: ResVT, VT2: MVT::Other),
7558 Ops: {Chain, InF32});
7559 Results.push_back(Elt: OpF32);
7560 Results.push_back(Elt: OpF32.getValue(R: 1));
7561 }
7562 }
7563 break;
7564 }
7565 default:
7566 llvm_unreachable("Unexpected node to lower");
7567 }
7568}
7569
7570void
7571SystemZTargetLowering::ReplaceNodeResults(SDNode *N,
7572 SmallVectorImpl<SDValue> &Results,
7573 SelectionDAG &DAG) const {
7574 return LowerOperationWrapper(N, Results, DAG);
7575}
7576
7577// Return true if VT is a vector whose elements are a whole number of bytes
7578// in width. Also check for presence of vector support.
7579bool SystemZTargetLowering::canTreatAsByteVector(EVT VT) const {
7580 if (!Subtarget.hasVector())
7581 return false;
7582
7583 return VT.isVector() && VT.getScalarSizeInBits() % 8 == 0 && VT.isSimple();
7584}
7585
7586// Try to simplify an EXTRACT_VECTOR_ELT from a vector of type VecVT
7587// producing a result of type ResVT. Op is a possibly bitcast version
7588// of the input vector and Index is the index (based on type VecVT) that
7589// should be extracted. Return the new extraction if a simplification
7590// was possible or if Force is true.
7591SDValue SystemZTargetLowering::combineExtract(const SDLoc &DL, EVT ResVT,
7592 EVT VecVT, SDValue Op,
7593 unsigned Index,
7594 DAGCombinerInfo &DCI,
7595 bool Force) const {
7596 SelectionDAG &DAG = DCI.DAG;
7597
7598 // The number of bytes being extracted.
7599 unsigned BytesPerElement = VecVT.getVectorElementType().getStoreSize();
7600
7601 for (;;) {
7602 unsigned Opcode = Op.getOpcode();
7603 if (Opcode == ISD::BITCAST)
7604 // Look through bitcasts.
7605 Op = Op.getOperand(i: 0);
7606 else if ((Opcode == ISD::VECTOR_SHUFFLE || Opcode == SystemZISD::SPLAT) &&
7607 canTreatAsByteVector(VT: Op.getValueType())) {
7608 // Get a VPERM-like permute mask and see whether the bytes covered
7609 // by the extracted element are a contiguous sequence from one
7610 // source operand.
7611 SmallVector<int, SystemZ::VectorBytes> Bytes;
7612 if (!getVPermMask(ShuffleOp: Op, Bytes))
7613 break;
7614 int First;
7615 if (!getShuffleInput(Bytes, Start: Index * BytesPerElement,
7616 BytesPerElement, Base&: First))
7617 break;
7618 if (First < 0)
7619 return DAG.getUNDEF(VT: ResVT);
7620 // Make sure the contiguous sequence starts at a multiple of the
7621 // original element size.
7622 unsigned Byte = unsigned(First) % Bytes.size();
7623 if (Byte % BytesPerElement != 0)
7624 break;
7625 // We can get the extracted value directly from an input.
7626 Index = Byte / BytesPerElement;
7627 Op = Op.getOperand(i: unsigned(First) / Bytes.size());
7628 Force = true;
7629 } else if (Opcode == ISD::BUILD_VECTOR &&
7630 canTreatAsByteVector(VT: Op.getValueType())) {
7631 // We can only optimize this case if the BUILD_VECTOR elements are
7632 // at least as wide as the extracted value.
7633 EVT OpVT = Op.getValueType();
7634 unsigned OpBytesPerElement = OpVT.getVectorElementType().getStoreSize();
7635 if (OpBytesPerElement < BytesPerElement)
7636 break;
7637 // Make sure that the least-significant bit of the extracted value
7638 // is the least significant bit of an input.
7639 unsigned End = (Index + 1) * BytesPerElement;
7640 if (End % OpBytesPerElement != 0)
7641 break;
7642 // We're extracting the low part of one operand of the BUILD_VECTOR.
7643 Op = Op.getOperand(i: End / OpBytesPerElement - 1);
7644 EVT ResIntVT = MVT::getIntegerVT(BitWidth: ResVT.getSizeInBits());
7645 if (!isTypeLegal(VT: ResIntVT))
7646 break;
7647 if (!Op.getValueType().isInteger()) {
7648 EVT OpIntVT = MVT::getIntegerVT(BitWidth: Op.getValueSizeInBits());
7649 if (!isTypeLegal(VT: OpIntVT))
7650 break;
7651 Op = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: OpIntVT, Operand: Op);
7652 DCI.AddToWorklist(N: Op.getNode());
7653 }
7654 Op = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: ResIntVT, Operand: Op);
7655 if (ResIntVT != ResVT) {
7656 DCI.AddToWorklist(N: Op.getNode());
7657 Op = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: ResVT, Operand: Op);
7658 }
7659 return Op;
7660 } else if ((Opcode == ISD::SIGN_EXTEND_VECTOR_INREG ||
7661 Opcode == ISD::ZERO_EXTEND_VECTOR_INREG ||
7662 Opcode == ISD::ANY_EXTEND_VECTOR_INREG) &&
7663 canTreatAsByteVector(VT: Op.getValueType()) &&
7664 canTreatAsByteVector(VT: Op.getOperand(i: 0).getValueType())) {
7665 // Make sure that only the unextended bits are significant.
7666 EVT ExtVT = Op.getValueType();
7667 EVT OpVT = Op.getOperand(i: 0).getValueType();
7668 unsigned ExtBytesPerElement = ExtVT.getVectorElementType().getStoreSize();
7669 unsigned OpBytesPerElement = OpVT.getVectorElementType().getStoreSize();
7670 unsigned Byte = Index * BytesPerElement;
7671 unsigned SubByte = Byte % ExtBytesPerElement;
7672 unsigned MinSubByte = ExtBytesPerElement - OpBytesPerElement;
7673 if (SubByte < MinSubByte ||
7674 SubByte + BytesPerElement > ExtBytesPerElement)
7675 break;
7676 // Get the byte offset of the unextended element
7677 Byte = Byte / ExtBytesPerElement * OpBytesPerElement;
7678 // ...then add the byte offset relative to that element.
7679 Byte += SubByte - MinSubByte;
7680 if (Byte % BytesPerElement != 0)
7681 break;
7682 Op = Op.getOperand(i: 0);
7683 Index = Byte / BytesPerElement;
7684 Force = true;
7685 } else
7686 break;
7687 }
7688 if (Force) {
7689 if (Op.getValueType() != VecVT) {
7690 Op = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: VecVT, Operand: Op);
7691 DCI.AddToWorklist(N: Op.getNode());
7692 }
7693 return DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: ResVT, N1: Op,
7694 N2: DAG.getConstant(Val: Index, DL, VT: MVT::i32));
7695 }
7696 return SDValue();
7697}
7698
7699// Optimize vector operations in scalar value Op on the basis that Op
7700// is truncated to TruncVT.
7701SDValue SystemZTargetLowering::combineTruncateExtract(
7702 const SDLoc &DL, EVT TruncVT, SDValue Op, DAGCombinerInfo &DCI) const {
7703 // If we have (trunc (extract_vector_elt X, Y)), try to turn it into
7704 // (extract_vector_elt (bitcast X), Y'), where (bitcast X) has elements
7705 // of type TruncVT.
7706 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7707 TruncVT.getSizeInBits() % 8 == 0) {
7708 SDValue Vec = Op.getOperand(i: 0);
7709 EVT VecVT = Vec.getValueType();
7710 if (canTreatAsByteVector(VT: VecVT)) {
7711 if (auto *IndexN = dyn_cast<ConstantSDNode>(Val: Op.getOperand(i: 1))) {
7712 unsigned BytesPerElement = VecVT.getVectorElementType().getStoreSize();
7713 unsigned TruncBytes = TruncVT.getStoreSize();
7714 if (BytesPerElement % TruncBytes == 0) {
7715 // Calculate the value of Y' in the above description. We are
7716 // splitting the original elements into Scale equal-sized pieces
7717 // and for truncation purposes want the last (least-significant)
7718 // of these pieces for IndexN. This is easiest to do by calculating
7719 // the start index of the following element and then subtracting 1.
7720 unsigned Scale = BytesPerElement / TruncBytes;
7721 unsigned NewIndex = (IndexN->getZExtValue() + 1) * Scale - 1;
7722
7723 // Defer the creation of the bitcast from X to combineExtract,
7724 // which might be able to optimize the extraction.
7725 VecVT = EVT::getVectorVT(Context&: *DCI.DAG.getContext(),
7726 VT: MVT::getIntegerVT(BitWidth: TruncBytes * 8),
7727 NumElements: VecVT.getStoreSize() / TruncBytes);
7728 EVT ResVT = (TruncBytes < 4 ? MVT::i32 : TruncVT);
7729 return combineExtract(DL, ResVT, VecVT, Op: Vec, Index: NewIndex, DCI, Force: true);
7730 }
7731 }
7732 }
7733 }
7734 return SDValue();
7735}
7736
7737SDValue SystemZTargetLowering::combineZERO_EXTEND(
7738 SDNode *N, DAGCombinerInfo &DCI) const {
7739 // Convert (zext (select_ccmask C1, C2)) into (select_ccmask C1', C2')
7740 SelectionDAG &DAG = DCI.DAG;
7741 SDValue N0 = N->getOperand(Num: 0);
7742 EVT VT = N->getValueType(ResNo: 0);
7743 if (N0.getOpcode() == SystemZISD::SELECT_CCMASK) {
7744 auto *TrueOp = dyn_cast<ConstantSDNode>(Val: N0.getOperand(i: 0));
7745 auto *FalseOp = dyn_cast<ConstantSDNode>(Val: N0.getOperand(i: 1));
7746 if (TrueOp && FalseOp) {
7747 SDLoc DL(N0);
7748 SDValue Ops[] = { DAG.getConstant(Val: TrueOp->getZExtValue(), DL, VT),
7749 DAG.getConstant(Val: FalseOp->getZExtValue(), DL, VT),
7750 N0.getOperand(i: 2), N0.getOperand(i: 3), N0.getOperand(i: 4) };
7751 SDValue NewSelect = DAG.getNode(Opcode: SystemZISD::SELECT_CCMASK, DL, VT, Ops);
7752 // If N0 has multiple uses, change other uses as well.
7753 if (!N0.hasOneUse()) {
7754 SDValue TruncSelect =
7755 DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: N0.getValueType(), Operand: NewSelect);
7756 DCI.CombineTo(N: N0.getNode(), Res: TruncSelect);
7757 }
7758 return NewSelect;
7759 }
7760 }
7761 // Convert (zext (xor (trunc X), C)) into (xor (trunc X), C') if the size
7762 // of the result is smaller than the size of X and all the truncated bits
7763 // of X are already zero.
7764 if (N0.getOpcode() == ISD::XOR &&
7765 N0.hasOneUse() && N0.getOperand(i: 0).hasOneUse() &&
7766 N0.getOperand(i: 0).getOpcode() == ISD::TRUNCATE &&
7767 N0.getOperand(i: 1).getOpcode() == ISD::Constant) {
7768 SDValue X = N0.getOperand(i: 0).getOperand(i: 0);
7769 if (VT.isScalarInteger() && VT.getSizeInBits() < X.getValueSizeInBits()) {
7770 KnownBits Known = DAG.computeKnownBits(Op: X);
7771 APInt TruncatedBits = APInt::getBitsSet(numBits: X.getValueSizeInBits(),
7772 loBit: N0.getValueSizeInBits(),
7773 hiBit: VT.getSizeInBits());
7774 if (TruncatedBits.isSubsetOf(RHS: Known.Zero)) {
7775 X = DAG.getNode(Opcode: ISD::TRUNCATE, DL: SDLoc(X), VT, Operand: X);
7776 APInt Mask = N0.getConstantOperandAPInt(i: 1).zext(width: VT.getSizeInBits());
7777 return DAG.getNode(Opcode: ISD::XOR, DL: SDLoc(N0), VT,
7778 N1: X, N2: DAG.getConstant(Val: Mask, DL: SDLoc(N0), VT));
7779 }
7780 }
7781 }
7782 // Recognize patterns for VECTOR SUBTRACT COMPUTE BORROW INDICATION
7783 // and VECTOR ADD COMPUTE CARRY for i128:
7784 // (zext (setcc_uge X Y)) --> (VSCBI X Y)
7785 // (zext (setcc_ule Y X)) --> (VSCBI X Y)
7786 // (zext (setcc_ult (add X Y) X/Y) -> (VACC X Y)
7787 // (zext (setcc_ugt X/Y (add X Y)) -> (VACC X Y)
7788 // For vector types, these patterns are recognized in the .td file.
7789 if (N0.getOpcode() == ISD::SETCC && isTypeLegal(VT) && VT == MVT::i128 &&
7790 N0.getOperand(i: 0).getValueType() == VT) {
7791 SDValue Op0 = N0.getOperand(i: 0);
7792 SDValue Op1 = N0.getOperand(i: 1);
7793 const ISD::CondCode CC = cast<CondCodeSDNode>(Val: N0.getOperand(i: 2))->get();
7794 switch (CC) {
7795 case ISD::SETULE:
7796 std::swap(a&: Op0, b&: Op1);
7797 [[fallthrough]];
7798 case ISD::SETUGE:
7799 return DAG.getNode(Opcode: SystemZISD::VSCBI, DL: SDLoc(N0), VT, N1: Op0, N2: Op1);
7800 case ISD::SETUGT:
7801 std::swap(a&: Op0, b&: Op1);
7802 [[fallthrough]];
7803 case ISD::SETULT:
7804 if (Op0->hasOneUse() && Op0->getOpcode() == ISD::ADD &&
7805 (Op0->getOperand(Num: 0) == Op1 || Op0->getOperand(Num: 1) == Op1))
7806 return DAG.getNode(Opcode: SystemZISD::VACC, DL: SDLoc(N0), VT, N1: Op0->getOperand(Num: 0),
7807 N2: Op0->getOperand(Num: 1));
7808 break;
7809 default:
7810 break;
7811 }
7812 }
7813
7814 return SDValue();
7815}
7816
7817SDValue SystemZTargetLowering::combineSIGN_EXTEND_INREG(
7818 SDNode *N, DAGCombinerInfo &DCI) const {
7819 // Convert (sext_in_reg (setcc LHS, RHS, COND), i1)
7820 // and (sext_in_reg (any_extend (setcc LHS, RHS, COND)), i1)
7821 // into (select_cc LHS, RHS, -1, 0, COND)
7822 SelectionDAG &DAG = DCI.DAG;
7823 SDValue N0 = N->getOperand(Num: 0);
7824 EVT VT = N->getValueType(ResNo: 0);
7825 EVT EVT = cast<VTSDNode>(Val: N->getOperand(Num: 1))->getVT();
7826 if (N0.hasOneUse() && N0.getOpcode() == ISD::ANY_EXTEND)
7827 N0 = N0.getOperand(i: 0);
7828 if (EVT == MVT::i1 && N0.hasOneUse() && N0.getOpcode() == ISD::SETCC) {
7829 SDLoc DL(N0);
7830 SDValue Ops[] = { N0.getOperand(i: 0), N0.getOperand(i: 1),
7831 DAG.getAllOnesConstant(DL, VT),
7832 DAG.getConstant(Val: 0, DL, VT), N0.getOperand(i: 2) };
7833 return DAG.getNode(Opcode: ISD::SELECT_CC, DL, VT, Ops);
7834 }
7835 return SDValue();
7836}
7837
7838SDValue SystemZTargetLowering::combineSIGN_EXTEND(
7839 SDNode *N, DAGCombinerInfo &DCI) const {
7840 // Convert (sext (ashr (shl X, C1), C2)) to
7841 // (ashr (shl (anyext X), C1'), C2')), since wider shifts are as
7842 // cheap as narrower ones.
7843 SelectionDAG &DAG = DCI.DAG;
7844 SDValue N0 = N->getOperand(Num: 0);
7845 EVT VT = N->getValueType(ResNo: 0);
7846 if (N0.hasOneUse() && N0.getOpcode() == ISD::SRA) {
7847 auto *SraAmt = dyn_cast<ConstantSDNode>(Val: N0.getOperand(i: 1));
7848 SDValue Inner = N0.getOperand(i: 0);
7849 if (SraAmt && Inner.hasOneUse() && Inner.getOpcode() == ISD::SHL) {
7850 if (auto *ShlAmt = dyn_cast<ConstantSDNode>(Val: Inner.getOperand(i: 1))) {
7851 unsigned Extra = (VT.getSizeInBits() - N0.getValueSizeInBits());
7852 unsigned NewShlAmt = ShlAmt->getZExtValue() + Extra;
7853 unsigned NewSraAmt = SraAmt->getZExtValue() + Extra;
7854 EVT ShiftVT = N0.getOperand(i: 1).getValueType();
7855 SDValue Ext = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(Inner), VT,
7856 Operand: Inner.getOperand(i: 0));
7857 SDValue Shl = DAG.getNode(Opcode: ISD::SHL, DL: SDLoc(Inner), VT, N1: Ext,
7858 N2: DAG.getConstant(Val: NewShlAmt, DL: SDLoc(Inner),
7859 VT: ShiftVT));
7860 return DAG.getNode(Opcode: ISD::SRA, DL: SDLoc(N0), VT, N1: Shl,
7861 N2: DAG.getConstant(Val: NewSraAmt, DL: SDLoc(N0), VT: ShiftVT));
7862 }
7863 }
7864 }
7865
7866 return SDValue();
7867}
7868
7869SDValue SystemZTargetLowering::combineMERGE(
7870 SDNode *N, DAGCombinerInfo &DCI) const {
7871 SelectionDAG &DAG = DCI.DAG;
7872 unsigned Opcode = N->getOpcode();
7873 SDValue Op0 = N->getOperand(Num: 0);
7874 SDValue Op1 = N->getOperand(Num: 1);
7875 if (Op0.getOpcode() == ISD::BITCAST)
7876 Op0 = Op0.getOperand(i: 0);
7877 if (ISD::isBuildVectorAllZeros(N: Op0.getNode())) {
7878 // (z_merge_* 0, 0) -> 0. This is mostly useful for using VLLEZF
7879 // for v4f32.
7880 if (Op1 == N->getOperand(Num: 0))
7881 return Op1;
7882 // (z_merge_? 0, X) -> (z_unpackl_? 0, X).
7883 EVT VT = Op1.getValueType();
7884 unsigned ElemBytes = VT.getVectorElementType().getStoreSize();
7885 if (ElemBytes <= 4) {
7886 Opcode = (Opcode == SystemZISD::MERGE_HIGH ?
7887 SystemZISD::UNPACKL_HIGH : SystemZISD::UNPACKL_LOW);
7888 EVT InVT = VT.changeVectorElementTypeToInteger();
7889 EVT OutVT = MVT::getVectorVT(VT: MVT::getIntegerVT(BitWidth: ElemBytes * 16),
7890 NumElements: SystemZ::VectorBytes / ElemBytes / 2);
7891 if (VT != InVT) {
7892 Op1 = DAG.getNode(Opcode: ISD::BITCAST, DL: SDLoc(N), VT: InVT, Operand: Op1);
7893 DCI.AddToWorklist(N: Op1.getNode());
7894 }
7895 SDValue Op = DAG.getNode(Opcode, DL: SDLoc(N), VT: OutVT, Operand: Op1);
7896 DCI.AddToWorklist(N: Op.getNode());
7897 return DAG.getNode(Opcode: ISD::BITCAST, DL: SDLoc(N), VT, Operand: Op);
7898 }
7899 }
7900 return SDValue();
7901}
7902
7903static bool isI128MovedToParts(LoadSDNode *LD, SDNode *&LoPart,
7904 SDNode *&HiPart) {
7905 LoPart = HiPart = nullptr;
7906
7907 // Scan through all users.
7908 for (SDUse &Use : LD->uses()) {
7909 // Skip the uses of the chain.
7910 if (Use.getResNo() != 0)
7911 continue;
7912
7913 // Verify every user is a TRUNCATE to i64 of the low or high half.
7914 SDNode *User = Use.getUser();
7915 bool IsLoPart = true;
7916 if (User->getOpcode() == ISD::SRL &&
7917 User->getOperand(Num: 1).getOpcode() == ISD::Constant &&
7918 User->getConstantOperandVal(Num: 1) == 64 && User->hasOneUse()) {
7919 User = *User->user_begin();
7920 IsLoPart = false;
7921 }
7922 if (User->getOpcode() != ISD::TRUNCATE || User->getValueType(ResNo: 0) != MVT::i64)
7923 return false;
7924
7925 if (IsLoPart) {
7926 if (LoPart)
7927 return false;
7928 LoPart = User;
7929 } else {
7930 if (HiPart)
7931 return false;
7932 HiPart = User;
7933 }
7934 }
7935 return true;
7936}
7937
7938static bool isF128MovedToParts(LoadSDNode *LD, SDNode *&LoPart,
7939 SDNode *&HiPart) {
7940 LoPart = HiPart = nullptr;
7941
7942 // Scan through all users.
7943 for (SDUse &Use : LD->uses()) {
7944 // Skip the uses of the chain.
7945 if (Use.getResNo() != 0)
7946 continue;
7947
7948 // Verify every user is an EXTRACT_SUBREG of the low or high half.
7949 SDNode *User = Use.getUser();
7950 if (!User->hasOneUse() || !User->isMachineOpcode() ||
7951 User->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
7952 return false;
7953
7954 switch (User->getConstantOperandVal(Num: 1)) {
7955 case SystemZ::subreg_l64:
7956 if (LoPart)
7957 return false;
7958 LoPart = User;
7959 break;
7960 case SystemZ::subreg_h64:
7961 if (HiPart)
7962 return false;
7963 HiPart = User;
7964 break;
7965 default:
7966 return false;
7967 }
7968 }
7969 return true;
7970}
7971
7972SDValue SystemZTargetLowering::combineLOAD(
7973 SDNode *N, DAGCombinerInfo &DCI) const {
7974 SelectionDAG &DAG = DCI.DAG;
7975 EVT LdVT = N->getValueType(ResNo: 0);
7976 if (auto *LN = dyn_cast<LoadSDNode>(Val: N)) {
7977 if (LN->getAddressSpace() == SYSTEMZAS::PTR32) {
7978 MVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
7979 MVT LoadNodeVT = LN->getBasePtr().getSimpleValueType();
7980 if (PtrVT != LoadNodeVT) {
7981 SDLoc DL(LN);
7982 SDValue AddrSpaceCast = DAG.getAddrSpaceCast(
7983 dl: DL, VT: PtrVT, Ptr: LN->getBasePtr(), SrcAS: SYSTEMZAS::PTR32, DestAS: 0);
7984 return DAG.getExtLoad(ExtType: LN->getExtensionType(), dl: DL, VT: LN->getValueType(ResNo: 0),
7985 Chain: LN->getChain(), Ptr: AddrSpaceCast, MemVT: LN->getMemoryVT(),
7986 MMO: LN->getMemOperand());
7987 }
7988 }
7989 }
7990 SDLoc DL(N);
7991
7992 // Replace a 128-bit load that is used solely to move its value into GPRs
7993 // by separate loads of both halves.
7994 LoadSDNode *LD = cast<LoadSDNode>(Val: N);
7995 if (LD->isSimple() && ISD::isNormalLoad(N: LD)) {
7996 SDNode *LoPart, *HiPart;
7997 if ((LdVT == MVT::i128 && isI128MovedToParts(LD, LoPart, HiPart)) ||
7998 (LdVT == MVT::f128 && isF128MovedToParts(LD, LoPart, HiPart))) {
7999 // Rewrite each extraction as an independent load.
8000 SmallVector<SDValue, 2> ArgChains;
8001 if (HiPart) {
8002 SDValue EltLoad = DAG.getLoad(
8003 VT: HiPart->getValueType(ResNo: 0), dl: DL, Chain: LD->getChain(), Ptr: LD->getBasePtr(),
8004 PtrInfo: LD->getPointerInfo(), Alignment: LD->getBaseAlign(),
8005 MMOFlags: LD->getMemOperand()->getFlags(), Metadata: LD->getAAInfo());
8006
8007 DCI.CombineTo(N: HiPart, Res: EltLoad, AddTo: true);
8008 ArgChains.push_back(Elt: EltLoad.getValue(R: 1));
8009 }
8010 if (LoPart) {
8011 SDValue EltLoad = DAG.getLoad(
8012 VT: LoPart->getValueType(ResNo: 0), dl: DL, Chain: LD->getChain(),
8013 Ptr: DAG.getObjectPtrOffset(SL: DL, Ptr: LD->getBasePtr(), Offset: TypeSize::getFixed(ExactSize: 8)),
8014 PtrInfo: LD->getPointerInfo().getWithOffset(O: 8), Alignment: LD->getBaseAlign(),
8015 MMOFlags: LD->getMemOperand()->getFlags(), Metadata: LD->getAAInfo());
8016
8017 DCI.CombineTo(N: LoPart, Res: EltLoad, AddTo: true);
8018 ArgChains.push_back(Elt: EltLoad.getValue(R: 1));
8019 }
8020
8021 // Collect all chains via TokenFactor.
8022 SDValue Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, Ops: ArgChains);
8023 DAG.ReplaceAllUsesOfValueWith(From: SDValue(N, 1), To: Chain);
8024 DCI.AddToWorklist(N: Chain.getNode());
8025 return SDValue(N, 0);
8026 }
8027 }
8028
8029 if (LdVT.isVector() || LdVT.isInteger())
8030 return SDValue();
8031 // Transform a scalar load that is REPLICATEd as well as having other
8032 // use(s) to the form where the other use(s) use the first element of the
8033 // REPLICATE instead of the load. Otherwise instruction selection will not
8034 // produce a VLREP. Avoid extracting to a GPR, so only do this for floating
8035 // point loads.
8036
8037 SDValue Replicate;
8038 SmallVector<SDNode*, 8> OtherUses;
8039 for (SDUse &Use : N->uses()) {
8040 if (Use.getUser()->getOpcode() == SystemZISD::REPLICATE) {
8041 if (Replicate)
8042 return SDValue(); // Should never happen
8043 Replicate = SDValue(Use.getUser(), 0);
8044 } else if (Use.getResNo() == 0)
8045 OtherUses.push_back(Elt: Use.getUser());
8046 }
8047 if (!Replicate || OtherUses.empty())
8048 return SDValue();
8049
8050 SDValue Extract0 = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: LdVT,
8051 N1: Replicate, N2: DAG.getConstant(Val: 0, DL, VT: MVT::i32));
8052 // Update uses of the loaded Value while preserving old chains.
8053 for (SDNode *U : OtherUses) {
8054 SmallVector<SDValue, 8> Ops;
8055 for (SDValue Op : U->ops())
8056 Ops.push_back(Elt: (Op.getNode() == N && Op.getResNo() == 0) ? Extract0 : Op);
8057 DAG.UpdateNodeOperands(N: U, Ops);
8058 }
8059 return SDValue(N, 0);
8060}
8061
8062bool SystemZTargetLowering::canLoadStoreByteSwapped(EVT VT) const {
8063 if (VT == MVT::i16 || VT == MVT::i32 || VT == MVT::i64)
8064 return true;
8065 if (Subtarget.hasVectorEnhancements2())
8066 if (VT == MVT::v8i16 || VT == MVT::v4i32 || VT == MVT::v2i64 || VT == MVT::i128)
8067 return true;
8068 return false;
8069}
8070
8071static bool isVectorElementSwap(ArrayRef<int> M, EVT VT) {
8072 if (!VT.isVector() || !VT.isSimple() ||
8073 VT.getSizeInBits() != 128 ||
8074 VT.getScalarSizeInBits() % 8 != 0)
8075 return false;
8076
8077 unsigned NumElts = VT.getVectorNumElements();
8078 for (unsigned i = 0; i < NumElts; ++i) {
8079 if (M[i] < 0) continue; // ignore UNDEF indices
8080 if ((unsigned) M[i] != NumElts - 1 - i)
8081 return false;
8082 }
8083
8084 return true;
8085}
8086
8087static bool isOnlyUsedByStores(SDValue StoredVal, SelectionDAG &DAG) {
8088 for (auto *U : StoredVal->users()) {
8089 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Val: U)) {
8090 EVT CurrMemVT = ST->getMemoryVT().getScalarType();
8091 if (CurrMemVT.isRound() && CurrMemVT.getStoreSize() <= 16)
8092 continue;
8093 } else if (isa<BuildVectorSDNode>(Val: U)) {
8094 SDValue BuildVector = SDValue(U, 0);
8095 if (DAG.isSplatValue(V: BuildVector, AllowUndefs: true/*AllowUndefs*/) &&
8096 isOnlyUsedByStores(StoredVal: BuildVector, DAG))
8097 continue;
8098 }
8099 return false;
8100 }
8101 return true;
8102}
8103
8104static bool isI128MovedFromParts(SDValue Val, SDValue &LoPart,
8105 SDValue &HiPart) {
8106 if (Val.getOpcode() != ISD::OR || !Val.getNode()->hasOneUse())
8107 return false;
8108
8109 SDValue Op0 = Val.getOperand(i: 0);
8110 SDValue Op1 = Val.getOperand(i: 1);
8111
8112 if (Op0.getOpcode() == ISD::SHL)
8113 std::swap(a&: Op0, b&: Op1);
8114 if (Op1.getOpcode() != ISD::SHL || !Op1.getNode()->hasOneUse() ||
8115 Op1.getOperand(i: 1).getOpcode() != ISD::Constant ||
8116 Op1.getConstantOperandVal(i: 1) != 64)
8117 return false;
8118 Op1 = Op1.getOperand(i: 0);
8119
8120 if (Op0.getOpcode() != ISD::ZERO_EXTEND || !Op0.getNode()->hasOneUse() ||
8121 Op0.getOperand(i: 0).getValueType() != MVT::i64)
8122 return false;
8123 if (Op1.getOpcode() != ISD::ANY_EXTEND || !Op1.getNode()->hasOneUse() ||
8124 Op1.getOperand(i: 0).getValueType() != MVT::i64)
8125 return false;
8126
8127 LoPart = Op0.getOperand(i: 0);
8128 HiPart = Op1.getOperand(i: 0);
8129 return true;
8130}
8131
8132static bool isF128MovedFromParts(SDValue Val, SDValue &LoPart,
8133 SDValue &HiPart) {
8134 if (!Val.getNode()->hasOneUse() || !Val.isMachineOpcode() ||
8135 Val.getMachineOpcode() != TargetOpcode::REG_SEQUENCE)
8136 return false;
8137
8138 if (Val->getNumOperands() != 5 ||
8139 Val->getOperand(Num: 0)->getAsZExtVal() != SystemZ::FP128BitRegClassID ||
8140 Val->getOperand(Num: 2)->getAsZExtVal() != SystemZ::subreg_l64 ||
8141 Val->getOperand(Num: 4)->getAsZExtVal() != SystemZ::subreg_h64)
8142 return false;
8143
8144 LoPart = Val->getOperand(Num: 1);
8145 HiPart = Val->getOperand(Num: 3);
8146 return true;
8147}
8148
8149SDValue SystemZTargetLowering::combineSTORE(
8150 SDNode *N, DAGCombinerInfo &DCI) const {
8151 SelectionDAG &DAG = DCI.DAG;
8152 auto *SN = cast<StoreSDNode>(Val: N);
8153 auto &Op1 = N->getOperand(Num: 1);
8154 EVT MemVT = SN->getMemoryVT();
8155
8156 if (SN->getAddressSpace() == SYSTEMZAS::PTR32) {
8157 MVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
8158 MVT StoreNodeVT = SN->getBasePtr().getSimpleValueType();
8159 if (PtrVT != StoreNodeVT) {
8160 SDLoc DL(SN);
8161 SDValue AddrSpaceCast = DAG.getAddrSpaceCast(dl: DL, VT: PtrVT, Ptr: SN->getBasePtr(),
8162 SrcAS: SYSTEMZAS::PTR32, DestAS: 0);
8163 return DAG.getStore(Chain: SN->getChain(), dl: DL, Val: SN->getValue(), Ptr: AddrSpaceCast,
8164 PtrInfo: SN->getPointerInfo(), Alignment: SN->getBaseAlign(),
8165 MMOFlags: SN->getMemOperand()->getFlags(), Metadata: SN->getAAInfo());
8166 }
8167 }
8168
8169 // If we have (truncstoreiN (extract_vector_elt X, Y), Z) then it is better
8170 // for the extraction to be done on a vMiN value, so that we can use VSTE.
8171 // If X has wider elements then convert it to:
8172 // (truncstoreiN (extract_vector_elt (bitcast X), Y2), Z).
8173 if (MemVT.isInteger() && SN->isTruncatingStore()) {
8174 if (SDValue Value =
8175 combineTruncateExtract(DL: SDLoc(N), TruncVT: MemVT, Op: SN->getValue(), DCI)) {
8176 DCI.AddToWorklist(N: Value.getNode());
8177
8178 // Rewrite the store with the new form of stored value.
8179 return DAG.getTruncStore(Chain: SN->getChain(), dl: SDLoc(SN), Val: Value,
8180 Ptr: SN->getBasePtr(), SVT: SN->getMemoryVT(),
8181 MMO: SN->getMemOperand());
8182 }
8183 }
8184
8185 // combine STORE (LOAD_STACK_GUARD) into MOV_STACKGUARD_DAG
8186 if (Op1->isMachineOpcode() &&
8187 (Op1->getMachineOpcode() == SystemZ::LOAD_STACK_GUARD)) {
8188 // Obtain the frame index the store was targeting.
8189 int FI = cast<FrameIndexSDNode>(Val: SN->getOperand(Num: 2))->getIndex();
8190 // Prepare operands of the MOV_STACKGUARD ISD Node - Chain and FrameIndex.
8191 SDValue Ops[] = {SN->getChain(), DAG.getTargetFrameIndex(FI, VT: MVT::i64)};
8192 return DAG.getNode(Opcode: SystemZISD::MOV_STACKGUARD, DL: SDLoc(SN), VT: MVT::Other, Ops);
8193 }
8194
8195 // Combine STORE (BSWAP) into STRVH/STRV/STRVG/VSTBR
8196 if (!SN->isTruncatingStore() &&
8197 Op1.getOpcode() == ISD::BSWAP &&
8198 Op1.getNode()->hasOneUse() &&
8199 canLoadStoreByteSwapped(VT: Op1.getValueType())) {
8200
8201 SDValue BSwapOp = Op1.getOperand(i: 0);
8202
8203 if (BSwapOp.getValueType() == MVT::i16)
8204 BSwapOp = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: SDLoc(N), VT: MVT::i32, Operand: BSwapOp);
8205
8206 SDValue Ops[] = {
8207 N->getOperand(Num: 0), BSwapOp, N->getOperand(Num: 2)
8208 };
8209
8210 return
8211 DAG.getMemIntrinsicNode(Opcode: SystemZISD::STRV, dl: SDLoc(N), VTList: DAG.getVTList(VT: MVT::Other),
8212 Ops, MemVT, MMO: SN->getMemOperand());
8213 }
8214 // Combine STORE (element-swap) into VSTER
8215 if (!SN->isTruncatingStore() &&
8216 Op1.getOpcode() == ISD::VECTOR_SHUFFLE &&
8217 Op1.getNode()->hasOneUse() &&
8218 Subtarget.hasVectorEnhancements2()) {
8219 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Val: Op1.getNode());
8220 ArrayRef<int> ShuffleMask = SVN->getMask();
8221 if (isVectorElementSwap(M: ShuffleMask, VT: Op1.getValueType())) {
8222 SDValue Ops[] = {
8223 N->getOperand(Num: 0), Op1.getOperand(i: 0), N->getOperand(Num: 2)
8224 };
8225
8226 return DAG.getMemIntrinsicNode(Opcode: SystemZISD::VSTER, dl: SDLoc(N),
8227 VTList: DAG.getVTList(VT: MVT::Other),
8228 Ops, MemVT, MMO: SN->getMemOperand());
8229 }
8230 }
8231
8232 // Combine STORE (READCYCLECOUNTER) into STCKF.
8233 if (!SN->isTruncatingStore() &&
8234 Op1.getOpcode() == ISD::READCYCLECOUNTER &&
8235 Op1.hasOneUse() &&
8236 N->getOperand(Num: 0).reachesChainWithoutSideEffects(Dest: SDValue(Op1.getNode(), 1))) {
8237 SDValue Ops[] = { Op1.getOperand(i: 0), N->getOperand(Num: 2) };
8238 return DAG.getMemIntrinsicNode(Opcode: SystemZISD::STCKF, dl: SDLoc(N),
8239 VTList: DAG.getVTList(VT: MVT::Other),
8240 Ops, MemVT, MMO: SN->getMemOperand());
8241 }
8242
8243 // Transform a store of a 128-bit value moved from parts into two stores.
8244 if (SN->isSimple() && ISD::isNormalStore(N: SN)) {
8245 SDValue LoPart, HiPart;
8246 if ((MemVT == MVT::i128 && isI128MovedFromParts(Val: Op1, LoPart, HiPart)) ||
8247 (MemVT == MVT::f128 && isF128MovedFromParts(Val: Op1, LoPart, HiPart))) {
8248 SDLoc DL(SN);
8249 SDValue Chain0 = DAG.getStore(
8250 Chain: SN->getChain(), dl: DL, Val: HiPart, Ptr: SN->getBasePtr(), PtrInfo: SN->getPointerInfo(),
8251 Alignment: SN->getBaseAlign(), MMOFlags: SN->getMemOperand()->getFlags(), Metadata: SN->getAAInfo());
8252 SDValue Chain1 = DAG.getStore(
8253 Chain: SN->getChain(), dl: DL, Val: LoPart,
8254 Ptr: DAG.getObjectPtrOffset(SL: DL, Ptr: SN->getBasePtr(), Offset: TypeSize::getFixed(ExactSize: 8)),
8255 PtrInfo: SN->getPointerInfo().getWithOffset(O: 8), Alignment: SN->getBaseAlign(),
8256 MMOFlags: SN->getMemOperand()->getFlags(), Metadata: SN->getAAInfo());
8257
8258 return DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, N1: Chain0, N2: Chain1);
8259 }
8260 }
8261
8262 // Replicate a reg or immediate with VREP instead of scalar multiply or
8263 // immediate load. It seems best to do this during the first DAGCombine as
8264 // it is straight-forward to handle the zero-extend node in the initial
8265 // DAG, and also not worry about the keeping the new MemVT legal (e.g. when
8266 // extracting an i16 element from a v16i8 vector).
8267 if (Subtarget.hasVector() && DCI.Level == BeforeLegalizeTypes &&
8268 isOnlyUsedByStores(StoredVal: Op1, DAG)) {
8269 SDValue Word = SDValue();
8270 EVT WordVT;
8271
8272 // Find a replicated immediate and return it if found in Word and its
8273 // type in WordVT.
8274 auto FindReplicatedImm = [&](ConstantSDNode *C, unsigned TotBytes) {
8275 // Some constants are better handled with a scalar store.
8276 if (C->getAPIntValue().getBitWidth() > 64 || C->isAllOnes() ||
8277 isInt<16>(x: C->getSExtValue()) || MemVT.getStoreSize() <= 2)
8278 return;
8279
8280 APInt Val = C->getAPIntValue();
8281 // Truncate Val in case of a truncating store.
8282 if (!llvm::isUIntN(N: TotBytes * 8, x: Val.getZExtValue())) {
8283 assert(SN->isTruncatingStore() &&
8284 "Non-truncating store and immediate value does not fit?");
8285 Val = Val.trunc(width: TotBytes * 8);
8286 }
8287
8288 SystemZVectorConstantInfo VCI(APInt(TotBytes * 8, Val.getZExtValue()));
8289 if (VCI.isVectorConstantLegal(Subtarget) &&
8290 VCI.Opcode == SystemZISD::REPLICATE) {
8291 Word = DAG.getConstant(Val: VCI.OpVals[0], DL: SDLoc(SN), VT: MVT::i32);
8292 WordVT = VCI.VecVT.getScalarType();
8293 }
8294 };
8295
8296 // Find a replicated register and return it if found in Word and its type
8297 // in WordVT.
8298 auto FindReplicatedReg = [&](SDValue MulOp) {
8299 EVT MulVT = MulOp.getValueType();
8300 if (MulOp->getOpcode() == ISD::MUL &&
8301 (MulVT == MVT::i16 || MulVT == MVT::i32 || MulVT == MVT::i64)) {
8302 // Find a zero extended value and its type.
8303 SDValue LHS = MulOp->getOperand(Num: 0);
8304 if (LHS->getOpcode() == ISD::ZERO_EXTEND)
8305 WordVT = LHS->getOperand(Num: 0).getValueType();
8306 else if (LHS->getOpcode() == ISD::AssertZext)
8307 WordVT = cast<VTSDNode>(Val: LHS->getOperand(Num: 1))->getVT();
8308 else
8309 return;
8310 // Find a replicating constant, e.g. 0x00010001.
8311 if (auto *C = dyn_cast<ConstantSDNode>(Val: MulOp->getOperand(Num: 1))) {
8312 SystemZVectorConstantInfo VCI(
8313 APInt(MulVT.getSizeInBits(), C->getZExtValue()));
8314 if (VCI.isVectorConstantLegal(Subtarget) &&
8315 VCI.Opcode == SystemZISD::REPLICATE && VCI.OpVals[0] == 1 &&
8316 WordVT == VCI.VecVT.getScalarType())
8317 Word = DAG.getZExtOrTrunc(Op: LHS->getOperand(Num: 0), DL: SDLoc(SN), VT: WordVT);
8318 }
8319 }
8320 };
8321
8322 if (isa<BuildVectorSDNode>(Val: Op1) &&
8323 DAG.isSplatValue(V: Op1, AllowUndefs: true/*AllowUndefs*/)) {
8324 SDValue SplatVal = Op1->getOperand(Num: 0);
8325 if (auto *C = dyn_cast<ConstantSDNode>(Val&: SplatVal))
8326 FindReplicatedImm(C, SplatVal.getValueType().getStoreSize());
8327 else
8328 FindReplicatedReg(SplatVal);
8329 } else {
8330 if (auto *C = dyn_cast<ConstantSDNode>(Val: Op1))
8331 FindReplicatedImm(C, MemVT.getStoreSize());
8332 else
8333 FindReplicatedReg(Op1);
8334 }
8335
8336 if (Word != SDValue()) {
8337 assert(MemVT.getSizeInBits() % WordVT.getSizeInBits() == 0 &&
8338 "Bad type handling");
8339 unsigned NumElts = MemVT.getSizeInBits() / WordVT.getSizeInBits();
8340 EVT SplatVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: WordVT, NumElements: NumElts);
8341 SDValue SplatVal = DAG.getSplatVector(VT: SplatVT, DL: SDLoc(SN), Op: Word);
8342 return DAG.getStore(Chain: SN->getChain(), dl: SDLoc(SN), Val: SplatVal,
8343 Ptr: SN->getBasePtr(), MMO: SN->getMemOperand());
8344 }
8345 }
8346
8347 return SDValue();
8348}
8349
8350SDValue SystemZTargetLowering::combineVECTOR_SHUFFLE(
8351 SDNode *N, DAGCombinerInfo &DCI) const {
8352 SelectionDAG &DAG = DCI.DAG;
8353 // Combine element-swap (LOAD) into VLER
8354 if (ISD::isNON_EXTLoad(N: N->getOperand(Num: 0).getNode()) &&
8355 N->getOperand(Num: 0).hasOneUse() &&
8356 Subtarget.hasVectorEnhancements2()) {
8357 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Val: N);
8358 ArrayRef<int> ShuffleMask = SVN->getMask();
8359 if (isVectorElementSwap(M: ShuffleMask, VT: N->getValueType(ResNo: 0))) {
8360 SDValue Load = N->getOperand(Num: 0);
8361 LoadSDNode *LD = cast<LoadSDNode>(Val&: Load);
8362
8363 // Create the element-swapping load.
8364 SDValue Ops[] = {
8365 LD->getChain(), // Chain
8366 LD->getBasePtr() // Ptr
8367 };
8368 SDValue ESLoad =
8369 DAG.getMemIntrinsicNode(Opcode: SystemZISD::VLER, dl: SDLoc(N),
8370 VTList: DAG.getVTList(VT1: LD->getValueType(ResNo: 0), VT2: MVT::Other),
8371 Ops, MemVT: LD->getMemoryVT(), MMO: LD->getMemOperand());
8372
8373 // First, combine the VECTOR_SHUFFLE away. This makes the value produced
8374 // by the load dead.
8375 DCI.CombineTo(N, Res: ESLoad);
8376
8377 // Next, combine the load away, we give it a bogus result value but a real
8378 // chain result. The result value is dead because the shuffle is dead.
8379 DCI.CombineTo(N: Load.getNode(), Res0: ESLoad, Res1: ESLoad.getValue(R: 1));
8380
8381 // Return N so it doesn't get rechecked!
8382 return SDValue(N, 0);
8383 }
8384 }
8385
8386 return SDValue();
8387}
8388
8389SDValue SystemZTargetLowering::combineEXTRACT_VECTOR_ELT(
8390 SDNode *N, DAGCombinerInfo &DCI) const {
8391 SelectionDAG &DAG = DCI.DAG;
8392
8393 if (!Subtarget.hasVector())
8394 return SDValue();
8395
8396 // Look through bitcasts that retain the number of vector elements.
8397 SDValue Op = N->getOperand(Num: 0);
8398 if (Op.getOpcode() == ISD::BITCAST &&
8399 Op.getValueType().isVector() &&
8400 Op.getOperand(i: 0).getValueType().isVector() &&
8401 Op.getValueType().getVectorNumElements() ==
8402 Op.getOperand(i: 0).getValueType().getVectorNumElements())
8403 Op = Op.getOperand(i: 0);
8404
8405 // Pull BSWAP out of a vector extraction.
8406 if (Op.getOpcode() == ISD::BSWAP && Op.hasOneUse()) {
8407 EVT VecVT = Op.getValueType();
8408 EVT EltVT = VecVT.getVectorElementType();
8409 Op = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: SDLoc(N), VT: EltVT,
8410 N1: Op.getOperand(i: 0), N2: N->getOperand(Num: 1));
8411 DCI.AddToWorklist(N: Op.getNode());
8412 Op = DAG.getNode(Opcode: ISD::BSWAP, DL: SDLoc(N), VT: EltVT, Operand: Op);
8413 if (EltVT != N->getValueType(ResNo: 0)) {
8414 DCI.AddToWorklist(N: Op.getNode());
8415 Op = DAG.getNode(Opcode: ISD::BITCAST, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), Operand: Op);
8416 }
8417 return Op;
8418 }
8419
8420 // Try to simplify a vector extraction.
8421 if (auto *IndexN = dyn_cast<ConstantSDNode>(Val: N->getOperand(Num: 1))) {
8422 SDValue Op0 = N->getOperand(Num: 0);
8423 EVT VecVT = Op0.getValueType();
8424 if (canTreatAsByteVector(VT: VecVT))
8425 return combineExtract(DL: SDLoc(N), ResVT: N->getValueType(ResNo: 0), VecVT, Op: Op0,
8426 Index: IndexN->getZExtValue(), DCI, Force: false);
8427 }
8428 return SDValue();
8429}
8430
8431SDValue SystemZTargetLowering::combineJOIN_DWORDS(
8432 SDNode *N, DAGCombinerInfo &DCI) const {
8433 SelectionDAG &DAG = DCI.DAG;
8434 // (join_dwords X, X) == (replicate X)
8435 if (N->getOperand(Num: 0) == N->getOperand(Num: 1))
8436 return DAG.getNode(Opcode: SystemZISD::REPLICATE, DL: SDLoc(N), VT: N->getValueType(ResNo: 0),
8437 Operand: N->getOperand(Num: 0));
8438 return SDValue();
8439}
8440
8441static SDValue MergeInputChains(SDNode *N1, SDNode *N2) {
8442 SDValue Chain1 = N1->getOperand(Num: 0);
8443 SDValue Chain2 = N2->getOperand(Num: 0);
8444
8445 // Trivial case: both nodes take the same chain.
8446 if (Chain1 == Chain2)
8447 return Chain1;
8448
8449 // FIXME - we could handle more complex cases via TokenFactor,
8450 // assuming we can verify that this would not create a cycle.
8451 return SDValue();
8452}
8453
8454SDValue SystemZTargetLowering::combineFP_ROUND(
8455 SDNode *N, DAGCombinerInfo &DCI) const {
8456
8457 if (!Subtarget.hasVector())
8458 return SDValue();
8459
8460 // (fpround (extract_vector_elt X 0))
8461 // (fpround (extract_vector_elt X 1)) ->
8462 // (extract_vector_elt (VROUND X) 0)
8463 // (extract_vector_elt (VROUND X) 2)
8464 //
8465 // This is a special case since the target doesn't really support v2f32s.
8466 unsigned OpNo = N->isStrictFPOpcode() ? 1 : 0;
8467 SelectionDAG &DAG = DCI.DAG;
8468 SDValue Op0 = N->getOperand(Num: OpNo);
8469 if (N->getValueType(ResNo: 0) == MVT::f32 && Op0.hasOneUse() &&
8470 Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
8471 Op0.getOperand(i: 0).getValueType() == MVT::v2f64 &&
8472 Op0.getOperand(i: 1).getOpcode() == ISD::Constant &&
8473 Op0.getConstantOperandVal(i: 1) == 0) {
8474 SDValue Vec = Op0.getOperand(i: 0);
8475 for (auto *U : Vec->users()) {
8476 if (U != Op0.getNode() && U->hasOneUse() &&
8477 U->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
8478 U->getOperand(Num: 0) == Vec &&
8479 U->getOperand(Num: 1).getOpcode() == ISD::Constant &&
8480 U->getConstantOperandVal(Num: 1) == 1) {
8481 SDValue OtherRound = SDValue(*U->user_begin(), 0);
8482 if (OtherRound.getOpcode() == N->getOpcode() &&
8483 OtherRound.getOperand(i: OpNo) == SDValue(U, 0) &&
8484 OtherRound.getValueType() == MVT::f32) {
8485 SDValue VRound, Chain;
8486 if (N->isStrictFPOpcode()) {
8487 Chain = MergeInputChains(N1: N, N2: OtherRound.getNode());
8488 if (!Chain)
8489 continue;
8490 VRound = DAG.getNode(Opcode: SystemZISD::STRICT_VROUND, DL: SDLoc(N),
8491 ResultTys: {MVT::v4f32, MVT::Other}, Ops: {Chain, Vec});
8492 Chain = VRound.getValue(R: 1);
8493 } else
8494 VRound = DAG.getNode(Opcode: SystemZISD::VROUND, DL: SDLoc(N),
8495 VT: MVT::v4f32, Operand: Vec);
8496 DCI.AddToWorklist(N: VRound.getNode());
8497 SDValue Extract1 =
8498 DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: SDLoc(U), VT: MVT::f32,
8499 N1: VRound, N2: DAG.getConstant(Val: 2, DL: SDLoc(U), VT: MVT::i32));
8500 DCI.AddToWorklist(N: Extract1.getNode());
8501 DAG.ReplaceAllUsesOfValueWith(From: OtherRound, To: Extract1);
8502 if (Chain)
8503 DAG.ReplaceAllUsesOfValueWith(From: OtherRound.getValue(R: 1), To: Chain);
8504 SDValue Extract0 =
8505 DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: SDLoc(Op0), VT: MVT::f32,
8506 N1: VRound, N2: DAG.getConstant(Val: 0, DL: SDLoc(Op0), VT: MVT::i32));
8507 if (Chain)
8508 return DAG.getNode(Opcode: ISD::MERGE_VALUES, DL: SDLoc(Op0),
8509 VTList: N->getVTList(), N1: Extract0, N2: Chain);
8510 return Extract0;
8511 }
8512 }
8513 }
8514 }
8515 return SDValue();
8516}
8517
8518SDValue SystemZTargetLowering::combineFP_EXTEND(
8519 SDNode *N, DAGCombinerInfo &DCI) const {
8520
8521 if (!Subtarget.hasVector())
8522 return SDValue();
8523
8524 // (fpextend (extract_vector_elt X 0))
8525 // (fpextend (extract_vector_elt X 2)) ->
8526 // (extract_vector_elt (VEXTEND X) 0)
8527 // (extract_vector_elt (VEXTEND X) 1)
8528 //
8529 // This is a special case since the target doesn't really support v2f32s.
8530 unsigned OpNo = N->isStrictFPOpcode() ? 1 : 0;
8531 SelectionDAG &DAG = DCI.DAG;
8532 SDValue Op0 = N->getOperand(Num: OpNo);
8533 if (N->getValueType(ResNo: 0) == MVT::f64 && Op0.hasOneUse() &&
8534 Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
8535 Op0.getOperand(i: 0).getValueType() == MVT::v4f32 &&
8536 Op0.getOperand(i: 1).getOpcode() == ISD::Constant &&
8537 Op0.getConstantOperandVal(i: 1) == 0) {
8538 SDValue Vec = Op0.getOperand(i: 0);
8539 for (auto *U : Vec->users()) {
8540 if (U != Op0.getNode() && U->hasOneUse() &&
8541 U->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
8542 U->getOperand(Num: 0) == Vec &&
8543 U->getOperand(Num: 1).getOpcode() == ISD::Constant &&
8544 U->getConstantOperandVal(Num: 1) == 2) {
8545 SDValue OtherExtend = SDValue(*U->user_begin(), 0);
8546 if (OtherExtend.getOpcode() == N->getOpcode() &&
8547 OtherExtend.getOperand(i: OpNo) == SDValue(U, 0) &&
8548 OtherExtend.getValueType() == MVT::f64) {
8549 SDValue VExtend, Chain;
8550 if (N->isStrictFPOpcode()) {
8551 Chain = MergeInputChains(N1: N, N2: OtherExtend.getNode());
8552 if (!Chain)
8553 continue;
8554 VExtend = DAG.getNode(Opcode: SystemZISD::STRICT_VEXTEND, DL: SDLoc(N),
8555 ResultTys: {MVT::v2f64, MVT::Other}, Ops: {Chain, Vec});
8556 Chain = VExtend.getValue(R: 1);
8557 } else
8558 VExtend = DAG.getNode(Opcode: SystemZISD::VEXTEND, DL: SDLoc(N),
8559 VT: MVT::v2f64, Operand: Vec);
8560 DCI.AddToWorklist(N: VExtend.getNode());
8561 SDValue Extract1 =
8562 DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: SDLoc(U), VT: MVT::f64,
8563 N1: VExtend, N2: DAG.getConstant(Val: 1, DL: SDLoc(U), VT: MVT::i32));
8564 DCI.AddToWorklist(N: Extract1.getNode());
8565 DAG.ReplaceAllUsesOfValueWith(From: OtherExtend, To: Extract1);
8566 if (Chain)
8567 DAG.ReplaceAllUsesOfValueWith(From: OtherExtend.getValue(R: 1), To: Chain);
8568 SDValue Extract0 =
8569 DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL: SDLoc(Op0), VT: MVT::f64,
8570 N1: VExtend, N2: DAG.getConstant(Val: 0, DL: SDLoc(Op0), VT: MVT::i32));
8571 if (Chain)
8572 return DAG.getNode(Opcode: ISD::MERGE_VALUES, DL: SDLoc(Op0),
8573 VTList: N->getVTList(), N1: Extract0, N2: Chain);
8574 return Extract0;
8575 }
8576 }
8577 }
8578 }
8579 return SDValue();
8580}
8581
8582SDValue SystemZTargetLowering::combineINT_TO_FP(
8583 SDNode *N, DAGCombinerInfo &DCI) const {
8584 if (DCI.Level != BeforeLegalizeTypes)
8585 return SDValue();
8586 SelectionDAG &DAG = DCI.DAG;
8587 LLVMContext &Ctx = *DAG.getContext();
8588 unsigned Opcode = N->getOpcode();
8589 EVT OutVT = N->getValueType(ResNo: 0);
8590 Type *OutLLVMTy = OutVT.getTypeForEVT(Context&: Ctx);
8591 SDValue Op = N->getOperand(Num: 0);
8592 unsigned OutScalarBits = OutLLVMTy->getScalarSizeInBits();
8593 unsigned InScalarBits = Op->getValueType(ResNo: 0).getScalarSizeInBits();
8594
8595 // Insert an extension before type-legalization to avoid scalarization, e.g.:
8596 // v2f64 = uint_to_fp v2i16
8597 // =>
8598 // v2f64 = uint_to_fp (v2i64 zero_extend v2i16)
8599 if (OutLLVMTy->isVectorTy() && OutScalarBits > InScalarBits &&
8600 OutScalarBits <= 64) {
8601 unsigned NumElts = cast<FixedVectorType>(Val: OutLLVMTy)->getNumElements();
8602 EVT ExtVT = EVT::getVectorVT(
8603 Context&: Ctx, VT: EVT::getIntegerVT(Context&: Ctx, BitWidth: OutLLVMTy->getScalarSizeInBits()), NumElements: NumElts);
8604 unsigned ExtOpcode =
8605 (Opcode == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND);
8606 SDValue ExtOp = DAG.getNode(Opcode: ExtOpcode, DL: SDLoc(N), VT: ExtVT, Operand: Op);
8607 return DAG.getNode(Opcode, DL: SDLoc(N), VT: OutVT, Operand: ExtOp);
8608 }
8609 return SDValue();
8610}
8611
8612SDValue SystemZTargetLowering::combineFCOPYSIGN(
8613 SDNode *N, DAGCombinerInfo &DCI) const {
8614 SelectionDAG &DAG = DCI.DAG;
8615 EVT VT = N->getValueType(ResNo: 0);
8616 SDValue ValOp = N->getOperand(Num: 0);
8617 SDValue SignOp = N->getOperand(Num: 1);
8618
8619 // Remove the rounding which is not needed.
8620 if (SignOp.getOpcode() == ISD::FP_ROUND) {
8621 SDValue WideOp = SignOp.getOperand(i: 0);
8622 return DAG.getNode(Opcode: ISD::FCOPYSIGN, DL: SDLoc(N), VT, N1: ValOp, N2: WideOp);
8623 }
8624
8625 return SDValue();
8626}
8627
8628SDValue SystemZTargetLowering::combineBSWAP(
8629 SDNode *N, DAGCombinerInfo &DCI) const {
8630 SelectionDAG &DAG = DCI.DAG;
8631 // Combine BSWAP (LOAD) into LRVH/LRV/LRVG/VLBR
8632 if (ISD::isNON_EXTLoad(N: N->getOperand(Num: 0).getNode()) &&
8633 N->getOperand(Num: 0).hasOneUse() &&
8634 canLoadStoreByteSwapped(VT: N->getValueType(ResNo: 0))) {
8635 SDValue Load = N->getOperand(Num: 0);
8636 LoadSDNode *LD = cast<LoadSDNode>(Val&: Load);
8637
8638 // Create the byte-swapping load.
8639 SDValue Ops[] = {
8640 LD->getChain(), // Chain
8641 LD->getBasePtr() // Ptr
8642 };
8643 EVT LoadVT = N->getValueType(ResNo: 0);
8644 if (LoadVT == MVT::i16)
8645 LoadVT = MVT::i32;
8646 SDValue BSLoad =
8647 DAG.getMemIntrinsicNode(Opcode: SystemZISD::LRV, dl: SDLoc(N),
8648 VTList: DAG.getVTList(VT1: LoadVT, VT2: MVT::Other),
8649 Ops, MemVT: LD->getMemoryVT(), MMO: LD->getMemOperand());
8650
8651 // If this is an i16 load, insert the truncate.
8652 SDValue ResVal = BSLoad;
8653 if (N->getValueType(ResNo: 0) == MVT::i16)
8654 ResVal = DAG.getNode(Opcode: ISD::TRUNCATE, DL: SDLoc(N), VT: MVT::i16, Operand: BSLoad);
8655
8656 // First, combine the bswap away. This makes the value produced by the
8657 // load dead.
8658 DCI.CombineTo(N, Res: ResVal);
8659
8660 // Next, combine the load away, we give it a bogus result value but a real
8661 // chain result. The result value is dead because the bswap is dead.
8662 DCI.CombineTo(N: Load.getNode(), Res0: ResVal, Res1: BSLoad.getValue(R: 1));
8663
8664 // Return N so it doesn't get rechecked!
8665 return SDValue(N, 0);
8666 }
8667
8668 // Look through bitcasts that retain the number of vector elements.
8669 SDValue Op = N->getOperand(Num: 0);
8670 if (Op.getOpcode() == ISD::BITCAST &&
8671 Op.getValueType().isVector() &&
8672 Op.getOperand(i: 0).getValueType().isVector() &&
8673 Op.getValueType().getVectorNumElements() ==
8674 Op.getOperand(i: 0).getValueType().getVectorNumElements())
8675 Op = Op.getOperand(i: 0);
8676
8677 // Push BSWAP into a vector insertion if at least one side then simplifies.
8678 if (Op.getOpcode() == ISD::INSERT_VECTOR_ELT && Op.hasOneUse()) {
8679 SDValue Vec = Op.getOperand(i: 0);
8680 SDValue Elt = Op.getOperand(i: 1);
8681 SDValue Idx = Op.getOperand(i: 2);
8682
8683 if (DAG.isConstantIntBuildVectorOrConstantInt(N: Vec) ||
8684 Vec.getOpcode() == ISD::BSWAP || Vec.isUndef() ||
8685 DAG.isConstantIntBuildVectorOrConstantInt(N: Elt) ||
8686 Elt.getOpcode() == ISD::BSWAP || Elt.isUndef() ||
8687 (canLoadStoreByteSwapped(VT: N->getValueType(ResNo: 0)) &&
8688 ISD::isNON_EXTLoad(N: Elt.getNode()) && Elt.hasOneUse())) {
8689 EVT VecVT = N->getValueType(ResNo: 0);
8690 EVT EltVT = N->getValueType(ResNo: 0).getVectorElementType();
8691 if (VecVT != Vec.getValueType()) {
8692 Vec = DAG.getNode(Opcode: ISD::BITCAST, DL: SDLoc(N), VT: VecVT, Operand: Vec);
8693 DCI.AddToWorklist(N: Vec.getNode());
8694 }
8695 if (EltVT != Elt.getValueType()) {
8696 Elt = DAG.getNode(Opcode: ISD::BITCAST, DL: SDLoc(N), VT: EltVT, Operand: Elt);
8697 DCI.AddToWorklist(N: Elt.getNode());
8698 }
8699 Vec = DAG.getNode(Opcode: ISD::BSWAP, DL: SDLoc(N), VT: VecVT, Operand: Vec);
8700 DCI.AddToWorklist(N: Vec.getNode());
8701 Elt = DAG.getNode(Opcode: ISD::BSWAP, DL: SDLoc(N), VT: EltVT, Operand: Elt);
8702 DCI.AddToWorklist(N: Elt.getNode());
8703 return DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL: SDLoc(N), VT: VecVT,
8704 N1: Vec, N2: Elt, N3: Idx);
8705 }
8706 }
8707
8708 // Push BSWAP into a vector shuffle if at least one side then simplifies.
8709 ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(Val&: Op);
8710 if (SV && Op.hasOneUse()) {
8711 SDValue Op0 = Op.getOperand(i: 0);
8712 SDValue Op1 = Op.getOperand(i: 1);
8713
8714 if (DAG.isConstantIntBuildVectorOrConstantInt(N: Op0) ||
8715 Op0.getOpcode() == ISD::BSWAP || Op0.isUndef() ||
8716 DAG.isConstantIntBuildVectorOrConstantInt(N: Op1) ||
8717 Op1.getOpcode() == ISD::BSWAP || Op1.isUndef()) {
8718 EVT VecVT = N->getValueType(ResNo: 0);
8719 if (VecVT != Op0.getValueType()) {
8720 Op0 = DAG.getNode(Opcode: ISD::BITCAST, DL: SDLoc(N), VT: VecVT, Operand: Op0);
8721 DCI.AddToWorklist(N: Op0.getNode());
8722 }
8723 if (VecVT != Op1.getValueType()) {
8724 Op1 = DAG.getNode(Opcode: ISD::BITCAST, DL: SDLoc(N), VT: VecVT, Operand: Op1);
8725 DCI.AddToWorklist(N: Op1.getNode());
8726 }
8727 Op0 = DAG.getNode(Opcode: ISD::BSWAP, DL: SDLoc(N), VT: VecVT, Operand: Op0);
8728 DCI.AddToWorklist(N: Op0.getNode());
8729 Op1 = DAG.getNode(Opcode: ISD::BSWAP, DL: SDLoc(N), VT: VecVT, Operand: Op1);
8730 DCI.AddToWorklist(N: Op1.getNode());
8731 return DAG.getVectorShuffle(VT: VecVT, dl: SDLoc(N), N1: Op0, N2: Op1, Mask: SV->getMask());
8732 }
8733 }
8734
8735 return SDValue();
8736}
8737
8738SDValue SystemZTargetLowering::combineSETCC(
8739 SDNode *N, DAGCombinerInfo &DCI) const {
8740 SelectionDAG &DAG = DCI.DAG;
8741 const ISD::CondCode CC = cast<CondCodeSDNode>(Val: N->getOperand(Num: 2))->get();
8742 const SDValue LHS = N->getOperand(Num: 0);
8743 const SDValue RHS = N->getOperand(Num: 1);
8744 bool CmpNull = isNullConstant(V: RHS);
8745 bool CmpAllOnes = isAllOnesConstant(V: RHS);
8746 EVT VT = N->getValueType(ResNo: 0);
8747 SDLoc DL(N);
8748
8749 // Match icmp_eq/ne(bitcast(icmp(X,Y)),0/-1) reduction patterns, and
8750 // change the outer compare to a i128 compare. This will normally
8751 // allow the reduction to be recognized in adjustICmp128, and even if
8752 // not, the i128 compare will still generate better code.
8753 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && (CmpNull || CmpAllOnes)) {
8754 SDValue Src = peekThroughBitcasts(V: LHS);
8755 if (Src.getOpcode() == ISD::SETCC &&
8756 Src.getValueType().isFixedLengthVector() &&
8757 Src.getValueType().getScalarType() == MVT::i1) {
8758 EVT CmpVT = Src.getOperand(i: 0).getValueType();
8759 if (CmpVT.getSizeInBits() == 128) {
8760 EVT IntVT = CmpVT.changeVectorElementTypeToInteger();
8761 SDValue LHS =
8762 DAG.getBitcast(VT: MVT::i128, V: DAG.getSExtOrTrunc(Op: Src, DL, VT: IntVT));
8763 SDValue RHS = CmpNull ? DAG.getConstant(Val: 0, DL, VT: MVT::i128)
8764 : DAG.getAllOnesConstant(DL, VT: MVT::i128);
8765 return DAG.getNode(Opcode: ISD::SETCC, DL, VT, N1: LHS, N2: RHS, N3: N->getOperand(Num: 2),
8766 Flags: N->getFlags());
8767 }
8768 }
8769 }
8770
8771 return SDValue();
8772}
8773
8774static std::pair<SDValue, int> findCCUse(const SDValue &Val,
8775 unsigned Depth = 0) {
8776 // Limit depth of potentially exponential walk.
8777 if (Depth > 5)
8778 return std::make_pair(x: SDValue(), y: SystemZ::CCMASK_NONE);
8779
8780 switch (Val.getOpcode()) {
8781 default:
8782 return std::make_pair(x: SDValue(), y: SystemZ::CCMASK_NONE);
8783 case SystemZISD::IPM:
8784 if (Val.getOperand(i: 0).getOpcode() == SystemZISD::CLC ||
8785 Val.getOperand(i: 0).getOpcode() == SystemZISD::STRCMP)
8786 return std::make_pair(x: Val.getOperand(i: 0), y: SystemZ::CCMASK_ICMP);
8787 return std::make_pair(x: Val.getOperand(i: 0), y: SystemZ::CCMASK_ANY);
8788 case SystemZISD::SELECT_CCMASK: {
8789 SDValue Op4CCReg = Val.getOperand(i: 4);
8790 if (Op4CCReg.getOpcode() == SystemZISD::ICMP ||
8791 Op4CCReg.getOpcode() == SystemZISD::TM) {
8792 auto [OpCC, OpCCValid] = findCCUse(Val: Op4CCReg.getOperand(i: 0), Depth: Depth + 1);
8793 if (OpCC != SDValue())
8794 return std::make_pair(x&: OpCC, y&: OpCCValid);
8795 }
8796 auto *CCValid = dyn_cast<ConstantSDNode>(Val: Val.getOperand(i: 2));
8797 if (!CCValid)
8798 return std::make_pair(x: SDValue(), y: SystemZ::CCMASK_NONE);
8799 int CCValidVal = CCValid->getZExtValue();
8800 return std::make_pair(x&: Op4CCReg, y&: CCValidVal);
8801 }
8802 case ISD::ADD:
8803 case ISD::AND:
8804 case ISD::OR:
8805 case ISD::XOR:
8806 case ISD::SHL:
8807 case ISD::SRA:
8808 case ISD::SRL:
8809 auto [Op0CC, Op0CCValid] = findCCUse(Val: Val.getOperand(i: 0), Depth: Depth + 1);
8810 if (Op0CC != SDValue())
8811 return std::make_pair(x&: Op0CC, y&: Op0CCValid);
8812 return findCCUse(Val: Val.getOperand(i: 1), Depth: Depth + 1);
8813 }
8814}
8815
8816static bool combineCCMask(SDValue &CCReg, int &CCValid, int &CCMask,
8817 SelectionDAG &DAG);
8818
8819SmallVector<SDValue, 4> static simplifyAssumingCCVal(SDValue &Val, SDValue &CC,
8820 SelectionDAG &DAG) {
8821 SDLoc DL(Val);
8822 auto Opcode = Val.getOpcode();
8823 switch (Opcode) {
8824 default:
8825 return {};
8826 case ISD::Constant:
8827 return {Val, Val, Val, Val};
8828 case SystemZISD::IPM: {
8829 SDValue IPMOp0 = Val.getOperand(i: 0);
8830 if (IPMOp0 != CC)
8831 return {};
8832 SmallVector<SDValue, 4> ShiftedCCVals;
8833 for (auto CC : {0, 1, 2, 3})
8834 ShiftedCCVals.emplace_back(
8835 Args: DAG.getConstant(Val: (CC << SystemZ::IPM_CC), DL, VT: MVT::i32));
8836 return ShiftedCCVals;
8837 }
8838 case SystemZISD::SELECT_CCMASK: {
8839 SDValue TrueVal = Val.getOperand(i: 0), FalseVal = Val.getOperand(i: 1);
8840 auto *CCValid = dyn_cast<ConstantSDNode>(Val: Val.getOperand(i: 2));
8841 auto *CCMask = dyn_cast<ConstantSDNode>(Val: Val.getOperand(i: 3));
8842 if (!CCValid || !CCMask)
8843 return {};
8844
8845 int CCValidVal = CCValid->getZExtValue();
8846 int CCMaskVal = CCMask->getZExtValue();
8847 // Pruning search tree early - Moving CC test and combineCCMask ahead of
8848 // recursive call to simplifyAssumingCCVal.
8849 SDValue Op4CCReg = Val.getOperand(i: 4);
8850 if (Op4CCReg != CC)
8851 combineCCMask(CCReg&: Op4CCReg, CCValid&: CCValidVal, CCMask&: CCMaskVal, DAG);
8852 if (Op4CCReg != CC)
8853 return {};
8854 const auto &&TrueSDVals = simplifyAssumingCCVal(Val&: TrueVal, CC, DAG);
8855 const auto &&FalseSDVals = simplifyAssumingCCVal(Val&: FalseVal, CC, DAG);
8856 if (TrueSDVals.empty() || FalseSDVals.empty())
8857 return {};
8858 SmallVector<SDValue, 4> MergedSDVals;
8859 for (auto &CCVal : {0, 1, 2, 3})
8860 MergedSDVals.emplace_back(Args: ((CCMaskVal & (1 << (3 - CCVal))) != 0)
8861 ? TrueSDVals[CCVal]
8862 : FalseSDVals[CCVal]);
8863 return MergedSDVals;
8864 }
8865 case ISD::ADD:
8866 case ISD::AND:
8867 case ISD::OR:
8868 case ISD::XOR:
8869 case ISD::SRA:
8870 // Avoid introducing CC spills (because ADD/AND/OR/XOR/SRA
8871 // would clobber CC).
8872 if (!Val.hasOneUse())
8873 return {};
8874 [[fallthrough]];
8875 case ISD::SHL:
8876 case ISD::SRL:
8877 SDValue Op0 = Val.getOperand(i: 0), Op1 = Val.getOperand(i: 1);
8878 const auto &&Op0SDVals = simplifyAssumingCCVal(Val&: Op0, CC, DAG);
8879 const auto &&Op1SDVals = simplifyAssumingCCVal(Val&: Op1, CC, DAG);
8880 if (Op0SDVals.empty() || Op1SDVals.empty())
8881 return {};
8882 SmallVector<SDValue, 4> BinaryOpSDVals;
8883 for (auto CCVal : {0, 1, 2, 3})
8884 BinaryOpSDVals.emplace_back(Args: DAG.getNode(
8885 Opcode, DL, VT: Val.getValueType(), N1: Op0SDVals[CCVal], N2: Op1SDVals[CCVal]));
8886 return BinaryOpSDVals;
8887 }
8888}
8889
8890static bool combineCCMask(SDValue &CCReg, int &CCValid, int &CCMask,
8891 SelectionDAG &DAG) {
8892 // We have a SELECT_CCMASK or BR_CCMASK comparing the condition code
8893 // set by the CCReg instruction using the CCValid / CCMask masks,
8894 // If the CCReg instruction is itself a ICMP / TM testing the condition
8895 // code set by some other instruction, see whether we can directly
8896 // use that condition code.
8897 auto *CCNode = CCReg.getNode();
8898 if (!CCNode)
8899 return false;
8900
8901 if (CCNode->getOpcode() == SystemZISD::TM) {
8902 if (CCValid != SystemZ::CCMASK_TM)
8903 return false;
8904 auto emulateTMCCMask = [](const SDValue &Op0Val, const SDValue &Op1Val) {
8905 auto *Op0Node = dyn_cast<ConstantSDNode>(Val: Op0Val.getNode());
8906 auto *Op1Node = dyn_cast<ConstantSDNode>(Val: Op1Val.getNode());
8907 if (!Op0Node || !Op1Node)
8908 return -1;
8909 auto Op0APVal = Op0Node->getAPIntValue();
8910 auto Op1APVal = Op1Node->getAPIntValue();
8911 auto Result = Op0APVal & Op1APVal;
8912 bool AllOnes = Result == Op1APVal;
8913 bool AllZeros = Result == 0;
8914 bool IsLeftMostBitSet = Result[Op1APVal.getActiveBits() - 1] != 0;
8915 return AllZeros ? 0 : AllOnes ? 3 : IsLeftMostBitSet ? 2 : 1;
8916 };
8917 SDValue Op0 = CCNode->getOperand(Num: 0);
8918 SDValue Op1 = CCNode->getOperand(Num: 1);
8919 auto [Op0CC, Op0CCValid] = findCCUse(Val: Op0);
8920 if (Op0CC == SDValue())
8921 return false;
8922 const auto &&Op0SDVals = simplifyAssumingCCVal(Val&: Op0, CC&: Op0CC, DAG);
8923 const auto &&Op1SDVals = simplifyAssumingCCVal(Val&: Op1, CC&: Op0CC, DAG);
8924 if (Op0SDVals.empty() || Op1SDVals.empty())
8925 return false;
8926 int NewCCMask = 0;
8927 for (auto CC : {0, 1, 2, 3}) {
8928 auto CCVal = emulateTMCCMask(Op0SDVals[CC], Op1SDVals[CC]);
8929 if (CCVal < 0)
8930 return false;
8931 NewCCMask <<= 1;
8932 NewCCMask |= (CCMask & (1 << (3 - CCVal))) != 0;
8933 }
8934 NewCCMask &= Op0CCValid;
8935 CCReg = Op0CC;
8936 CCMask = NewCCMask;
8937 CCValid = Op0CCValid;
8938 return true;
8939 }
8940 if (CCNode->getOpcode() != SystemZISD::ICMP ||
8941 CCValid != SystemZ::CCMASK_ICMP)
8942 return false;
8943
8944 SDValue CmpOp0 = CCNode->getOperand(Num: 0);
8945 SDValue CmpOp1 = CCNode->getOperand(Num: 1);
8946 SDValue CmpOp2 = CCNode->getOperand(Num: 2);
8947 auto [Op0CC, Op0CCValid] = findCCUse(Val: CmpOp0);
8948 if (Op0CC != SDValue()) {
8949 const auto &&Op0SDVals = simplifyAssumingCCVal(Val&: CmpOp0, CC&: Op0CC, DAG);
8950 const auto &&Op1SDVals = simplifyAssumingCCVal(Val&: CmpOp1, CC&: Op0CC, DAG);
8951 if (Op0SDVals.empty() || Op1SDVals.empty())
8952 return false;
8953
8954 auto *CmpType = dyn_cast<ConstantSDNode>(Val&: CmpOp2);
8955 auto CmpTypeVal = CmpType->getZExtValue();
8956 const auto compareCCSigned = [&CmpTypeVal](const SDValue &Op0Val,
8957 const SDValue &Op1Val) {
8958 auto *Op0Node = dyn_cast<ConstantSDNode>(Val: Op0Val.getNode());
8959 auto *Op1Node = dyn_cast<ConstantSDNode>(Val: Op1Val.getNode());
8960 if (!Op0Node || !Op1Node)
8961 return -1;
8962 auto Op0APVal = Op0Node->getAPIntValue();
8963 auto Op1APVal = Op1Node->getAPIntValue();
8964 if (CmpTypeVal == SystemZICMP::SignedOnly)
8965 return Op0APVal == Op1APVal ? 0 : Op0APVal.slt(RHS: Op1APVal) ? 1 : 2;
8966 return Op0APVal == Op1APVal ? 0 : Op0APVal.ult(RHS: Op1APVal) ? 1 : 2;
8967 };
8968 int NewCCMask = 0;
8969 for (auto CC : {0, 1, 2, 3}) {
8970 auto CCVal = compareCCSigned(Op0SDVals[CC], Op1SDVals[CC]);
8971 if (CCVal < 0)
8972 return false;
8973 NewCCMask <<= 1;
8974 NewCCMask |= (CCMask & (1 << (3 - CCVal))) != 0;
8975 }
8976 NewCCMask &= Op0CCValid;
8977 CCMask = NewCCMask;
8978 CCReg = Op0CC;
8979 CCValid = Op0CCValid;
8980 return true;
8981 }
8982
8983 return false;
8984}
8985
8986// Merging versus split in multiple branches cost.
8987TargetLoweringBase::CondMergingParams
8988SystemZTargetLowering::getJumpConditionMergingParams(Instruction::BinaryOps Opc,
8989 const Value *Lhs,
8990 const Value *Rhs,
8991 const Function *) const {
8992 const auto isFlagOutOpCC = [](const Value *V) {
8993 using namespace llvm::PatternMatch;
8994 const Value *RHSVal;
8995 const APInt *RHSC;
8996 if (const auto *I = dyn_cast<Instruction>(Val: V)) {
8997 // PatternMatch.h provides concise tree-based pattern match of llvm IR.
8998 if (match(V: I->getOperand(i: 0), P: m_And(L: m_Value(V&: RHSVal), R: m_APInt(Res&: RHSC))) ||
8999 match(V: I, P: m_Cmp(L: m_Value(V&: RHSVal), R: m_APInt(Res&: RHSC)))) {
9000 if (const auto *CB = dyn_cast<CallBase>(Val: RHSVal)) {
9001 if (CB->isInlineAsm()) {
9002 const InlineAsm *IA = cast<InlineAsm>(Val: CB->getCalledOperand());
9003 return IA && IA->getConstraintString().contains(Other: "{@cc}");
9004 }
9005 }
9006 }
9007 }
9008 return false;
9009 };
9010 // Pattern (ICmp %asm) or (ICmp (And %asm)).
9011 // Cost of longest dependency chain (ICmp, And) is 2. CostThreshold or
9012 // BaseCost can be set >=2. If cost of instruction <= CostThreshold
9013 // conditionals will be merged or else conditionals will be split.
9014 if (isFlagOutOpCC(Lhs) && isFlagOutOpCC(Rhs))
9015 return {.BaseCost: 3, .LikelyBias: 0, .UnlikelyBias: -1};
9016 // Default.
9017 return {.BaseCost: -1, .LikelyBias: -1, .UnlikelyBias: -1};
9018}
9019
9020SDValue SystemZTargetLowering::combineBR_CCMASK(SDNode *N,
9021 DAGCombinerInfo &DCI) const {
9022 SelectionDAG &DAG = DCI.DAG;
9023
9024 // Combine BR_CCMASK (ICMP (SELECT_CCMASK)) into a single BR_CCMASK.
9025 auto *CCValid = dyn_cast<ConstantSDNode>(Val: N->getOperand(Num: 1));
9026 auto *CCMask = dyn_cast<ConstantSDNode>(Val: N->getOperand(Num: 2));
9027 if (!CCValid || !CCMask)
9028 return SDValue();
9029
9030 int CCValidVal = CCValid->getZExtValue();
9031 int CCMaskVal = CCMask->getZExtValue();
9032 SDValue Chain = N->getOperand(Num: 0);
9033 SDValue CCReg = N->getOperand(Num: 4);
9034 // If combineCMask was able to merge or simplify ccvalid or ccmask, re-emit
9035 // the modified BR_CCMASK with the new values.
9036 // In order to avoid conditional branches with full or empty cc masks, do not
9037 // do this if ccmask is 0 or equal to ccvalid.
9038 if (combineCCMask(CCReg, CCValid&: CCValidVal, CCMask&: CCMaskVal, DAG) && CCMaskVal != 0 &&
9039 CCMaskVal != CCValidVal)
9040 return DAG.getNode(Opcode: SystemZISD::BR_CCMASK, DL: SDLoc(N), VT: N->getValueType(ResNo: 0),
9041 N1: Chain,
9042 N2: DAG.getTargetConstant(Val: CCValidVal, DL: SDLoc(N), VT: MVT::i32),
9043 N3: DAG.getTargetConstant(Val: CCMaskVal, DL: SDLoc(N), VT: MVT::i32),
9044 N4: N->getOperand(Num: 3), N5: CCReg);
9045 return SDValue();
9046}
9047
9048SDValue SystemZTargetLowering::combineSELECT_CCMASK(
9049 SDNode *N, DAGCombinerInfo &DCI) const {
9050 SelectionDAG &DAG = DCI.DAG;
9051
9052 // Combine SELECT_CCMASK (ICMP (SELECT_CCMASK)) into a single SELECT_CCMASK.
9053 auto *CCValid = dyn_cast<ConstantSDNode>(Val: N->getOperand(Num: 2));
9054 auto *CCMask = dyn_cast<ConstantSDNode>(Val: N->getOperand(Num: 3));
9055 if (!CCValid || !CCMask)
9056 return SDValue();
9057
9058 int CCValidVal = CCValid->getZExtValue();
9059 int CCMaskVal = CCMask->getZExtValue();
9060 SDValue CCReg = N->getOperand(Num: 4);
9061
9062 bool IsCombinedCCReg = combineCCMask(CCReg, CCValid&: CCValidVal, CCMask&: CCMaskVal, DAG);
9063
9064 // Populate SDVals vector for each condition code ccval for given Val, which
9065 // can again be another nested select_ccmask with the same CC.
9066 const auto constructCCSDValsFromSELECT = [&CCReg](SDValue &Val) {
9067 if (Val.getOpcode() == SystemZISD::SELECT_CCMASK) {
9068 SmallVector<SDValue, 4> Res;
9069 if (Val.getOperand(i: 4) != CCReg)
9070 return SmallVector<SDValue, 4>{};
9071 SDValue TrueVal = Val.getOperand(i: 0), FalseVal = Val.getOperand(i: 1);
9072 auto *CCMask = dyn_cast<ConstantSDNode>(Val: Val.getOperand(i: 3));
9073 if (!CCMask)
9074 return SmallVector<SDValue, 4>{};
9075
9076 int CCMaskVal = CCMask->getZExtValue();
9077 for (auto &CC : {0, 1, 2, 3})
9078 Res.emplace_back(Args&: ((CCMaskVal & (1 << (3 - CC))) != 0) ? TrueVal
9079 : FalseVal);
9080 return Res;
9081 }
9082 return SmallVector<SDValue, 4>{Val, Val, Val, Val};
9083 };
9084 // Attempting to optimize TrueVal/FalseVal in outermost select_ccmask either
9085 // with CCReg found by combineCCMask or original CCReg.
9086 SDValue TrueVal = N->getOperand(Num: 0);
9087 SDValue FalseVal = N->getOperand(Num: 1);
9088 auto &&TrueSDVals = simplifyAssumingCCVal(Val&: TrueVal, CC&: CCReg, DAG);
9089 auto &&FalseSDVals = simplifyAssumingCCVal(Val&: FalseVal, CC&: CCReg, DAG);
9090 // TrueSDVals/FalseSDVals might be empty in case of non-constant
9091 // TrueVal/FalseVal for select_ccmask, which can not be optimized further.
9092 if (TrueSDVals.empty())
9093 TrueSDVals = constructCCSDValsFromSELECT(TrueVal);
9094 if (FalseSDVals.empty())
9095 FalseSDVals = constructCCSDValsFromSELECT(FalseVal);
9096 if (!TrueSDVals.empty() && !FalseSDVals.empty()) {
9097 SmallSet<SDValue, 4> MergedSDValsSet;
9098 // Ignoring CC values outside CCValiid.
9099 for (auto CC : {0, 1, 2, 3}) {
9100 if ((CCValidVal & ((1 << (3 - CC)))) != 0)
9101 MergedSDValsSet.insert(V: ((CCMaskVal & (1 << (3 - CC))) != 0)
9102 ? TrueSDVals[CC]
9103 : FalseSDVals[CC]);
9104 }
9105 if (MergedSDValsSet.size() == 1)
9106 return *MergedSDValsSet.begin();
9107 if (MergedSDValsSet.size() == 2) {
9108 auto BeginIt = MergedSDValsSet.begin();
9109 SDValue NewTrueVal = *BeginIt, NewFalseVal = *next(x: BeginIt);
9110 if (NewTrueVal == FalseVal || NewFalseVal == TrueVal)
9111 std::swap(a&: NewTrueVal, b&: NewFalseVal);
9112 int NewCCMask = 0;
9113 for (auto CC : {0, 1, 2, 3}) {
9114 NewCCMask <<= 1;
9115 NewCCMask |= ((CCMaskVal & (1 << (3 - CC))) != 0)
9116 ? (TrueSDVals[CC] == NewTrueVal)
9117 : (FalseSDVals[CC] == NewTrueVal);
9118 }
9119 CCMaskVal = NewCCMask;
9120 CCMaskVal &= CCValidVal;
9121 TrueVal = NewTrueVal;
9122 FalseVal = NewFalseVal;
9123 IsCombinedCCReg = true;
9124 }
9125 }
9126 // If the condition is trivially false or trivially true after
9127 // combineCCMask, just collapse this SELECT_CCMASK to the indicated value
9128 // (possibly modified by constructCCSDValsFromSELECT).
9129 if (CCMaskVal == 0)
9130 return FalseVal;
9131 if (CCMaskVal == CCValidVal)
9132 return TrueVal;
9133
9134 if (IsCombinedCCReg)
9135 return DAG.getNode(
9136 Opcode: SystemZISD::SELECT_CCMASK, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), N1: TrueVal,
9137 N2: FalseVal, N3: DAG.getTargetConstant(Val: CCValidVal, DL: SDLoc(N), VT: MVT::i32),
9138 N4: DAG.getTargetConstant(Val: CCMaskVal, DL: SDLoc(N), VT: MVT::i32), N5: CCReg);
9139
9140 return SDValue();
9141}
9142
9143SDValue SystemZTargetLowering::combineGET_CCMASK(
9144 SDNode *N, DAGCombinerInfo &DCI) const {
9145
9146 // Optimize away GET_CCMASK (SELECT_CCMASK) if the CC masks are compatible
9147 auto *CCValid = dyn_cast<ConstantSDNode>(Val: N->getOperand(Num: 1));
9148 auto *CCMask = dyn_cast<ConstantSDNode>(Val: N->getOperand(Num: 2));
9149 if (!CCValid || !CCMask)
9150 return SDValue();
9151 int CCValidVal = CCValid->getZExtValue();
9152 int CCMaskVal = CCMask->getZExtValue();
9153
9154 SDValue Select = N->getOperand(Num: 0);
9155 if (Select->getOpcode() == ISD::TRUNCATE)
9156 Select = Select->getOperand(Num: 0);
9157 if (Select->getOpcode() != SystemZISD::SELECT_CCMASK)
9158 return SDValue();
9159
9160 auto *SelectCCValid = dyn_cast<ConstantSDNode>(Val: Select->getOperand(Num: 2));
9161 auto *SelectCCMask = dyn_cast<ConstantSDNode>(Val: Select->getOperand(Num: 3));
9162 if (!SelectCCValid || !SelectCCMask)
9163 return SDValue();
9164 int SelectCCValidVal = SelectCCValid->getZExtValue();
9165 int SelectCCMaskVal = SelectCCMask->getZExtValue();
9166
9167 auto *TrueVal = dyn_cast<ConstantSDNode>(Val: Select->getOperand(Num: 0));
9168 auto *FalseVal = dyn_cast<ConstantSDNode>(Val: Select->getOperand(Num: 1));
9169 if (!TrueVal || !FalseVal)
9170 return SDValue();
9171 if (TrueVal->getZExtValue() == 1 && FalseVal->getZExtValue() == 0)
9172 ;
9173 else if (TrueVal->getZExtValue() == 0 && FalseVal->getZExtValue() == 1)
9174 SelectCCMaskVal ^= SelectCCValidVal;
9175 else
9176 return SDValue();
9177
9178 if (SelectCCValidVal & ~CCValidVal)
9179 return SDValue();
9180 if (SelectCCMaskVal != (CCMaskVal & SelectCCValidVal))
9181 return SDValue();
9182
9183 return Select->getOperand(Num: 4);
9184}
9185
9186SDValue SystemZTargetLowering::combineIntDIVREM(
9187 SDNode *N, DAGCombinerInfo &DCI) const {
9188 SelectionDAG &DAG = DCI.DAG;
9189 EVT VT = N->getValueType(ResNo: 0);
9190 // In the case where the divisor is a vector of constants a cheaper
9191 // sequence of instructions can replace the divide. BuildSDIV is called to
9192 // do this during DAG combining, but it only succeeds when it can build a
9193 // multiplication node. The only option for SystemZ is ISD::SMUL_LOHI, and
9194 // since it is not Legal but Custom it can only happen before
9195 // legalization. Therefore we must scalarize this early before Combine
9196 // 1. For widened vectors, this is already the result of type legalization.
9197 if (DCI.Level == BeforeLegalizeTypes && VT.isVector() && isTypeLegal(VT) &&
9198 DAG.isConstantIntBuildVectorOrConstantInt(N: N->getOperand(Num: 1)))
9199 return DAG.UnrollVectorOp(N);
9200 return SDValue();
9201}
9202
9203
9204// Transform a right shift of a multiply-and-add into a multiply-and-add-high.
9205// This is closely modeled after the common-code combineShiftToMULH.
9206SDValue SystemZTargetLowering::combineShiftToMulAddHigh(
9207 SDNode *N, DAGCombinerInfo &DCI) const {
9208 SelectionDAG &DAG = DCI.DAG;
9209 SDLoc DL(N);
9210
9211 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
9212 "SRL or SRA node is required here!");
9213
9214 if (!Subtarget.hasVector())
9215 return SDValue();
9216
9217 // Check the shift amount. Proceed with the transformation if the shift
9218 // amount is constant.
9219 ConstantSDNode *ShiftAmtSrc = isConstOrConstSplat(N: N->getOperand(Num: 1));
9220 if (!ShiftAmtSrc)
9221 return SDValue();
9222
9223 // The operation feeding into the shift must be an add.
9224 SDValue ShiftOperand = N->getOperand(Num: 0);
9225 if (ShiftOperand.getOpcode() != ISD::ADD)
9226 return SDValue();
9227
9228 // One operand of the add must be a multiply.
9229 SDValue MulOp = ShiftOperand.getOperand(i: 0);
9230 SDValue AddOp = ShiftOperand.getOperand(i: 1);
9231 if (MulOp.getOpcode() != ISD::MUL) {
9232 if (AddOp.getOpcode() != ISD::MUL)
9233 return SDValue();
9234 std::swap(a&: MulOp, b&: AddOp);
9235 }
9236
9237 // All operands must be equivalent extend nodes.
9238 SDValue LeftOp = MulOp.getOperand(i: 0);
9239 SDValue RightOp = MulOp.getOperand(i: 1);
9240
9241 bool IsSignExt = LeftOp.getOpcode() == ISD::SIGN_EXTEND;
9242 bool IsZeroExt = LeftOp.getOpcode() == ISD::ZERO_EXTEND;
9243
9244 if (!IsSignExt && !IsZeroExt)
9245 return SDValue();
9246
9247 EVT NarrowVT = LeftOp.getOperand(i: 0).getValueType();
9248 unsigned NarrowVTSize = NarrowVT.getScalarSizeInBits();
9249
9250 SDValue MulhRightOp;
9251 if (ConstantSDNode *Constant = isConstOrConstSplat(N: RightOp)) {
9252 unsigned ActiveBits = IsSignExt
9253 ? Constant->getAPIntValue().getSignificantBits()
9254 : Constant->getAPIntValue().getActiveBits();
9255 if (ActiveBits > NarrowVTSize)
9256 return SDValue();
9257 MulhRightOp = DAG.getConstant(
9258 Val: Constant->getAPIntValue().trunc(width: NarrowVT.getScalarSizeInBits()), DL,
9259 VT: NarrowVT);
9260 } else {
9261 if (LeftOp.getOpcode() != RightOp.getOpcode())
9262 return SDValue();
9263 // Check that the two extend nodes are the same type.
9264 if (NarrowVT != RightOp.getOperand(i: 0).getValueType())
9265 return SDValue();
9266 MulhRightOp = RightOp.getOperand(i: 0);
9267 }
9268
9269 SDValue MulhAddOp;
9270 if (ConstantSDNode *Constant = isConstOrConstSplat(N: AddOp)) {
9271 unsigned ActiveBits = IsSignExt
9272 ? Constant->getAPIntValue().getSignificantBits()
9273 : Constant->getAPIntValue().getActiveBits();
9274 if (ActiveBits > NarrowVTSize)
9275 return SDValue();
9276 MulhAddOp = DAG.getConstant(
9277 Val: Constant->getAPIntValue().trunc(width: NarrowVT.getScalarSizeInBits()), DL,
9278 VT: NarrowVT);
9279 } else {
9280 if (LeftOp.getOpcode() != AddOp.getOpcode())
9281 return SDValue();
9282 // Check that the two extend nodes are the same type.
9283 if (NarrowVT != AddOp.getOperand(i: 0).getValueType())
9284 return SDValue();
9285 MulhAddOp = AddOp.getOperand(i: 0);
9286 }
9287
9288 EVT WideVT = LeftOp.getValueType();
9289 // Proceed with the transformation if the wide types match.
9290 assert((WideVT == RightOp.getValueType()) &&
9291 "Cannot have a multiply node with two different operand types.");
9292 assert((WideVT == AddOp.getValueType()) &&
9293 "Cannot have an add node with two different operand types.");
9294
9295 // Proceed with the transformation if the wide type is twice as large
9296 // as the narrow type.
9297 if (WideVT.getScalarSizeInBits() != 2 * NarrowVTSize)
9298 return SDValue();
9299
9300 // Check the shift amount with the narrow type size.
9301 // Proceed with the transformation if the shift amount is the width
9302 // of the narrow type.
9303 unsigned ShiftAmt = ShiftAmtSrc->getZExtValue();
9304 if (ShiftAmt != NarrowVTSize)
9305 return SDValue();
9306
9307 // Proceed if we support the multiply-and-add-high operation.
9308 if (!(NarrowVT == MVT::v16i8 || NarrowVT == MVT::v8i16 ||
9309 NarrowVT == MVT::v4i32 ||
9310 (Subtarget.hasVectorEnhancements3() &&
9311 (NarrowVT == MVT::v2i64 || NarrowVT == MVT::i128))))
9312 return SDValue();
9313
9314 // Emit the VMAH (signed) or VMALH (unsigned) operation.
9315 SDValue Result = DAG.getNode(Opcode: IsSignExt ? SystemZISD::VMAH : SystemZISD::VMALH,
9316 DL, VT: NarrowVT, N1: LeftOp.getOperand(i: 0),
9317 N2: MulhRightOp, N3: MulhAddOp);
9318 bool IsSigned = N->getOpcode() == ISD::SRA;
9319 return DAG.getExtOrTrunc(IsSigned, Op: Result, DL, VT: WideVT);
9320}
9321
9322// Op is an operand of a multiplication. Check whether this can be folded
9323// into an even/odd widening operation; if so, return the opcode to be used
9324// and update Op to the appropriate sub-operand. Note that the caller must
9325// verify that *both* operands of the multiplication support the operation.
9326static unsigned detectEvenOddMultiplyOperand(const SelectionDAG &DAG,
9327 const SystemZSubtarget &Subtarget,
9328 SDValue &Op) {
9329 EVT VT = Op.getValueType();
9330
9331 // Check for (sign/zero_extend_vector_inreg (vector_shuffle)) corresponding
9332 // to selecting the even or odd vector elements.
9333 if (VT.isVector() && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
9334 (Op.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG ||
9335 Op.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG)) {
9336 bool IsSigned = Op.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG;
9337 unsigned NumElts = VT.getVectorNumElements();
9338 Op = Op.getOperand(i: 0);
9339 if (Op.getValueType().getVectorNumElements() == 2 * NumElts &&
9340 Op.getOpcode() == ISD::VECTOR_SHUFFLE) {
9341 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Val: Op.getNode());
9342 ArrayRef<int> ShuffleMask = SVN->getMask();
9343 bool CanUseEven = true, CanUseOdd = true;
9344 for (unsigned Elt = 0; Elt < NumElts; Elt++) {
9345 if (ShuffleMask[Elt] == -1)
9346 continue;
9347 if (unsigned(ShuffleMask[Elt]) != 2 * Elt)
9348 CanUseEven = false;
9349 if (unsigned(ShuffleMask[Elt]) != 2 * Elt + 1)
9350 CanUseOdd = false;
9351 }
9352 Op = Op.getOperand(i: 0);
9353 if (CanUseEven)
9354 return IsSigned ? SystemZISD::VME : SystemZISD::VMLE;
9355 if (CanUseOdd)
9356 return IsSigned ? SystemZISD::VMO : SystemZISD::VMLO;
9357 }
9358 }
9359
9360 // For z17, we can also support the v2i64->i128 case, which looks like
9361 // (sign/zero_extend (extract_vector_elt X 0/1))
9362 if (VT == MVT::i128 && Subtarget.hasVectorEnhancements3() &&
9363 (Op.getOpcode() == ISD::SIGN_EXTEND ||
9364 Op.getOpcode() == ISD::ZERO_EXTEND)) {
9365 bool IsSigned = Op.getOpcode() == ISD::SIGN_EXTEND;
9366 Op = Op.getOperand(i: 0);
9367 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
9368 Op.getOperand(i: 0).getValueType() == MVT::v2i64 &&
9369 Op.getOperand(i: 1).getOpcode() == ISD::Constant) {
9370 unsigned Elem = Op.getConstantOperandVal(i: 1);
9371 Op = Op.getOperand(i: 0);
9372 if (Elem == 0)
9373 return IsSigned ? SystemZISD::VME : SystemZISD::VMLE;
9374 if (Elem == 1)
9375 return IsSigned ? SystemZISD::VMO : SystemZISD::VMLO;
9376 }
9377 }
9378
9379 return 0;
9380}
9381
9382SDValue SystemZTargetLowering::combineMUL(
9383 SDNode *N, DAGCombinerInfo &DCI) const {
9384 SelectionDAG &DAG = DCI.DAG;
9385
9386 // Detect even/odd widening multiplication.
9387 SDValue Op0 = N->getOperand(Num: 0);
9388 SDValue Op1 = N->getOperand(Num: 1);
9389 unsigned OpcodeCand0 = detectEvenOddMultiplyOperand(DAG, Subtarget, Op&: Op0);
9390 unsigned OpcodeCand1 = detectEvenOddMultiplyOperand(DAG, Subtarget, Op&: Op1);
9391 if (OpcodeCand0 && OpcodeCand0 == OpcodeCand1)
9392 return DAG.getNode(Opcode: OpcodeCand0, DL: SDLoc(N), VT: N->getValueType(ResNo: 0), N1: Op0, N2: Op1);
9393
9394 return SDValue();
9395}
9396
9397SDValue SystemZTargetLowering::combineINTRINSIC(
9398 SDNode *N, DAGCombinerInfo &DCI) const {
9399 SelectionDAG &DAG = DCI.DAG;
9400
9401 unsigned Id = N->getConstantOperandVal(Num: 1);
9402 switch (Id) {
9403 // VECTOR LOAD (RIGHTMOST) WITH LENGTH with a length operand of 15
9404 // or larger is simply a vector load.
9405 case Intrinsic::s390_vll:
9406 case Intrinsic::s390_vlrl:
9407 if (auto *C = dyn_cast<ConstantSDNode>(Val: N->getOperand(Num: 2)))
9408 if (C->getZExtValue() >= 15)
9409 return DAG.getLoad(VT: N->getValueType(ResNo: 0), dl: SDLoc(N), Chain: N->getOperand(Num: 0),
9410 Ptr: N->getOperand(Num: 3), PtrInfo: MachinePointerInfo());
9411 break;
9412 // Likewise for VECTOR STORE (RIGHTMOST) WITH LENGTH.
9413 case Intrinsic::s390_vstl:
9414 case Intrinsic::s390_vstrl:
9415 if (auto *C = dyn_cast<ConstantSDNode>(Val: N->getOperand(Num: 3)))
9416 if (C->getZExtValue() >= 15)
9417 return DAG.getStore(Chain: N->getOperand(Num: 0), dl: SDLoc(N), Val: N->getOperand(Num: 2),
9418 Ptr: N->getOperand(Num: 4), PtrInfo: MachinePointerInfo());
9419 break;
9420 }
9421
9422 return SDValue();
9423}
9424
9425SDValue SystemZTargetLowering::unwrapAddress(SDValue N) const {
9426 if (N->getOpcode() == SystemZISD::PCREL_WRAPPER)
9427 return N->getOperand(Num: 0);
9428 return N;
9429}
9430
9431SDValue SystemZTargetLowering::PerformDAGCombine(SDNode *N,
9432 DAGCombinerInfo &DCI) const {
9433 switch(N->getOpcode()) {
9434 default: break;
9435 case ISD::ZERO_EXTEND: return combineZERO_EXTEND(N, DCI);
9436 case ISD::SIGN_EXTEND: return combineSIGN_EXTEND(N, DCI);
9437 case ISD::SIGN_EXTEND_INREG: return combineSIGN_EXTEND_INREG(N, DCI);
9438 case SystemZISD::MERGE_HIGH:
9439 case SystemZISD::MERGE_LOW: return combineMERGE(N, DCI);
9440 case ISD::LOAD: return combineLOAD(N, DCI);
9441 case ISD::STORE: return combineSTORE(N, DCI);
9442 case ISD::VECTOR_SHUFFLE: return combineVECTOR_SHUFFLE(N, DCI);
9443 case ISD::EXTRACT_VECTOR_ELT: return combineEXTRACT_VECTOR_ELT(N, DCI);
9444 case SystemZISD::JOIN_DWORDS: return combineJOIN_DWORDS(N, DCI);
9445 case ISD::STRICT_FP_ROUND:
9446 case ISD::FP_ROUND: return combineFP_ROUND(N, DCI);
9447 case ISD::STRICT_FP_EXTEND:
9448 case ISD::FP_EXTEND: return combineFP_EXTEND(N, DCI);
9449 case ISD::SINT_TO_FP:
9450 case ISD::UINT_TO_FP: return combineINT_TO_FP(N, DCI);
9451 case ISD::FCOPYSIGN: return combineFCOPYSIGN(N, DCI);
9452 case ISD::BSWAP: return combineBSWAP(N, DCI);
9453 case ISD::SETCC: return combineSETCC(N, DCI);
9454 case SystemZISD::BR_CCMASK: return combineBR_CCMASK(N, DCI);
9455 case SystemZISD::SELECT_CCMASK: return combineSELECT_CCMASK(N, DCI);
9456 case SystemZISD::GET_CCMASK: return combineGET_CCMASK(N, DCI);
9457 case ISD::SRL:
9458 case ISD::SRA: return combineShiftToMulAddHigh(N, DCI);
9459 case ISD::MUL: return combineMUL(N, DCI);
9460 case ISD::SDIV:
9461 case ISD::UDIV:
9462 case ISD::SREM:
9463 case ISD::UREM: return combineIntDIVREM(N, DCI);
9464 case ISD::INTRINSIC_W_CHAIN:
9465 case ISD::INTRINSIC_VOID: return combineINTRINSIC(N, DCI);
9466 }
9467
9468 return SDValue();
9469}
9470
9471// Return the demanded elements for the OpNo source operand of Op. DemandedElts
9472// are for Op.
9473static APInt getDemandedSrcElements(SDValue Op, const APInt &DemandedElts,
9474 unsigned OpNo) {
9475 EVT VT = Op.getValueType();
9476 unsigned NumElts = (VT.isVector() ? VT.getVectorNumElements() : 1);
9477 APInt SrcDemE;
9478 unsigned Opcode = Op.getOpcode();
9479 if (Opcode == ISD::INTRINSIC_WO_CHAIN) {
9480 unsigned Id = Op.getConstantOperandVal(i: 0);
9481 switch (Id) {
9482 case Intrinsic::s390_vpksh: // PACKS
9483 case Intrinsic::s390_vpksf:
9484 case Intrinsic::s390_vpksg:
9485 case Intrinsic::s390_vpkshs: // PACKS_CC
9486 case Intrinsic::s390_vpksfs:
9487 case Intrinsic::s390_vpksgs:
9488 case Intrinsic::s390_vpklsh: // PACKLS
9489 case Intrinsic::s390_vpklsf:
9490 case Intrinsic::s390_vpklsg:
9491 case Intrinsic::s390_vpklshs: // PACKLS_CC
9492 case Intrinsic::s390_vpklsfs:
9493 case Intrinsic::s390_vpklsgs:
9494 // VECTOR PACK truncates the elements of two source vectors into one.
9495 SrcDemE = DemandedElts;
9496 if (OpNo == 2)
9497 SrcDemE.lshrInPlace(ShiftAmt: NumElts / 2);
9498 SrcDemE = SrcDemE.trunc(width: NumElts / 2);
9499 break;
9500 // VECTOR UNPACK extends half the elements of the source vector.
9501 case Intrinsic::s390_vuphb: // VECTOR UNPACK HIGH
9502 case Intrinsic::s390_vuphh:
9503 case Intrinsic::s390_vuphf:
9504 case Intrinsic::s390_vuplhb: // VECTOR UNPACK LOGICAL HIGH
9505 case Intrinsic::s390_vuplhh:
9506 case Intrinsic::s390_vuplhf:
9507 SrcDemE = APInt(NumElts * 2, 0);
9508 SrcDemE.insertBits(SubBits: DemandedElts, bitPosition: 0);
9509 break;
9510 case Intrinsic::s390_vuplb: // VECTOR UNPACK LOW
9511 case Intrinsic::s390_vuplhw:
9512 case Intrinsic::s390_vuplf:
9513 case Intrinsic::s390_vupllb: // VECTOR UNPACK LOGICAL LOW
9514 case Intrinsic::s390_vupllh:
9515 case Intrinsic::s390_vupllf:
9516 SrcDemE = APInt(NumElts * 2, 0);
9517 SrcDemE.insertBits(SubBits: DemandedElts, bitPosition: NumElts);
9518 break;
9519 case Intrinsic::s390_vpdi: {
9520 // VECTOR PERMUTE DWORD IMMEDIATE selects one element from each source.
9521 SrcDemE = APInt(NumElts, 0);
9522 if (!DemandedElts[OpNo - 1])
9523 break;
9524 unsigned Mask = Op.getConstantOperandVal(i: 3);
9525 unsigned MaskBit = ((OpNo - 1) ? 1 : 4);
9526 // Demand input element 0 or 1, given by the mask bit value.
9527 SrcDemE.setBit((Mask & MaskBit)? 1 : 0);
9528 break;
9529 }
9530 case Intrinsic::s390_vsldb: {
9531 // VECTOR SHIFT LEFT DOUBLE BY BYTE
9532 assert(VT == MVT::v16i8 && "Unexpected type.");
9533 unsigned FirstIdx = Op.getConstantOperandVal(i: 3);
9534 assert (FirstIdx > 0 && FirstIdx < 16 && "Unused operand.");
9535 unsigned NumSrc0Els = 16 - FirstIdx;
9536 SrcDemE = APInt(NumElts, 0);
9537 if (OpNo == 1) {
9538 APInt DemEls = DemandedElts.trunc(width: NumSrc0Els);
9539 SrcDemE.insertBits(SubBits: DemEls, bitPosition: FirstIdx);
9540 } else {
9541 APInt DemEls = DemandedElts.lshr(shiftAmt: NumSrc0Els);
9542 SrcDemE.insertBits(SubBits: DemEls, bitPosition: 0);
9543 }
9544 break;
9545 }
9546 case Intrinsic::s390_vperm:
9547 SrcDemE = APInt::getAllOnes(numBits: NumElts);
9548 break;
9549 default:
9550 llvm_unreachable("Unhandled intrinsic.");
9551 break;
9552 }
9553 } else {
9554 switch (Opcode) {
9555 case SystemZISD::JOIN_DWORDS:
9556 // Scalar operand.
9557 SrcDemE = APInt(1, 1);
9558 break;
9559 case SystemZISD::SELECT_CCMASK:
9560 SrcDemE = DemandedElts;
9561 break;
9562 default:
9563 llvm_unreachable("Unhandled opcode.");
9564 break;
9565 }
9566 }
9567 return SrcDemE;
9568}
9569
9570static void computeKnownBitsBinOp(const SDValue Op, KnownBits &Known,
9571 const APInt &DemandedElts,
9572 const SelectionDAG &DAG, unsigned Depth,
9573 unsigned OpNo) {
9574 APInt Src0DemE = getDemandedSrcElements(Op, DemandedElts, OpNo);
9575 APInt Src1DemE = getDemandedSrcElements(Op, DemandedElts, OpNo: OpNo + 1);
9576 KnownBits LHSKnown =
9577 DAG.computeKnownBits(Op: Op.getOperand(i: OpNo), DemandedElts: Src0DemE, Depth: Depth + 1);
9578 KnownBits RHSKnown =
9579 DAG.computeKnownBits(Op: Op.getOperand(i: OpNo + 1), DemandedElts: Src1DemE, Depth: Depth + 1);
9580 Known = LHSKnown.intersectWith(RHS: RHSKnown);
9581}
9582
9583void
9584SystemZTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
9585 KnownBits &Known,
9586 const APInt &DemandedElts,
9587 const SelectionDAG &DAG,
9588 unsigned Depth) const {
9589 Known.resetAll();
9590
9591 // Intrinsic CC result is returned in the two low bits.
9592 unsigned Tmp0, Tmp1; // not used
9593 if (Op.getResNo() == 1 && isIntrinsicWithCC(Op, Opcode&: Tmp0, CCValid&: Tmp1)) {
9594 Known.Zero.setBitsFrom(2);
9595 return;
9596 }
9597 EVT VT = Op.getValueType();
9598 if (Op.getResNo() != 0 || VT == MVT::Untyped)
9599 return;
9600 assert (Known.getBitWidth() == VT.getScalarSizeInBits() &&
9601 "KnownBits does not match VT in bitwidth");
9602 assert ((!VT.isVector() ||
9603 (DemandedElts.getBitWidth() == VT.getVectorNumElements())) &&
9604 "DemandedElts does not match VT number of elements");
9605 unsigned BitWidth = Known.getBitWidth();
9606 unsigned Opcode = Op.getOpcode();
9607 if (Opcode == ISD::INTRINSIC_WO_CHAIN) {
9608 bool IsLogical = false;
9609 unsigned Id = Op.getConstantOperandVal(i: 0);
9610 switch (Id) {
9611 case Intrinsic::s390_vpksh: // PACKS
9612 case Intrinsic::s390_vpksf:
9613 case Intrinsic::s390_vpksg:
9614 case Intrinsic::s390_vpkshs: // PACKS_CC
9615 case Intrinsic::s390_vpksfs:
9616 case Intrinsic::s390_vpksgs:
9617 case Intrinsic::s390_vpklsh: // PACKLS
9618 case Intrinsic::s390_vpklsf:
9619 case Intrinsic::s390_vpklsg:
9620 case Intrinsic::s390_vpklshs: // PACKLS_CC
9621 case Intrinsic::s390_vpklsfs:
9622 case Intrinsic::s390_vpklsgs:
9623 case Intrinsic::s390_vpdi:
9624 case Intrinsic::s390_vsldb:
9625 case Intrinsic::s390_vperm:
9626 computeKnownBitsBinOp(Op, Known, DemandedElts, DAG, Depth, OpNo: 1);
9627 break;
9628 case Intrinsic::s390_vuplhb: // VECTOR UNPACK LOGICAL HIGH
9629 case Intrinsic::s390_vuplhh:
9630 case Intrinsic::s390_vuplhf:
9631 case Intrinsic::s390_vupllb: // VECTOR UNPACK LOGICAL LOW
9632 case Intrinsic::s390_vupllh:
9633 case Intrinsic::s390_vupllf:
9634 IsLogical = true;
9635 [[fallthrough]];
9636 case Intrinsic::s390_vuphb: // VECTOR UNPACK HIGH
9637 case Intrinsic::s390_vuphh:
9638 case Intrinsic::s390_vuphf:
9639 case Intrinsic::s390_vuplb: // VECTOR UNPACK LOW
9640 case Intrinsic::s390_vuplhw:
9641 case Intrinsic::s390_vuplf: {
9642 SDValue SrcOp = Op.getOperand(i: 1);
9643 APInt SrcDemE = getDemandedSrcElements(Op, DemandedElts, OpNo: 0);
9644 Known = DAG.computeKnownBits(Op: SrcOp, DemandedElts: SrcDemE, Depth: Depth + 1);
9645 if (IsLogical) {
9646 Known = Known.zext(BitWidth);
9647 } else
9648 Known = Known.sext(BitWidth);
9649 break;
9650 }
9651 default:
9652 break;
9653 }
9654 } else {
9655 switch (Opcode) {
9656 case SystemZISD::JOIN_DWORDS:
9657 case SystemZISD::SELECT_CCMASK:
9658 computeKnownBitsBinOp(Op, Known, DemandedElts, DAG, Depth, OpNo: 0);
9659 break;
9660 case SystemZISD::REPLICATE: {
9661 SDValue SrcOp = Op.getOperand(i: 0);
9662 Known = DAG.computeKnownBits(Op: SrcOp, Depth: Depth + 1);
9663 if (Known.getBitWidth() < BitWidth && isa<ConstantSDNode>(Val: SrcOp))
9664 Known = Known.sext(BitWidth); // VREPI sign extends the immedate.
9665 break;
9666 }
9667 default:
9668 break;
9669 }
9670 }
9671
9672 // Known has the width of the source operand(s). Adjust if needed to match
9673 // the passed bitwidth.
9674 if (Known.getBitWidth() != BitWidth)
9675 Known = Known.anyextOrTrunc(BitWidth);
9676}
9677
9678static unsigned computeNumSignBitsBinOp(SDValue Op, const APInt &DemandedElts,
9679 const SelectionDAG &DAG, unsigned Depth,
9680 unsigned OpNo) {
9681 APInt Src0DemE = getDemandedSrcElements(Op, DemandedElts, OpNo);
9682 unsigned LHS = DAG.ComputeNumSignBits(Op: Op.getOperand(i: OpNo), DemandedElts: Src0DemE, Depth: Depth + 1);
9683 if (LHS == 1) return 1; // Early out.
9684 APInt Src1DemE = getDemandedSrcElements(Op, DemandedElts, OpNo: OpNo + 1);
9685 unsigned RHS = DAG.ComputeNumSignBits(Op: Op.getOperand(i: OpNo + 1), DemandedElts: Src1DemE, Depth: Depth + 1);
9686 if (RHS == 1) return 1; // Early out.
9687 unsigned Common = std::min(a: LHS, b: RHS);
9688 unsigned SrcBitWidth = Op.getOperand(i: OpNo).getScalarValueSizeInBits();
9689 EVT VT = Op.getValueType();
9690 unsigned VTBits = VT.getScalarSizeInBits();
9691 if (SrcBitWidth > VTBits) { // PACK
9692 unsigned SrcExtraBits = SrcBitWidth - VTBits;
9693 if (Common > SrcExtraBits)
9694 return (Common - SrcExtraBits);
9695 return 1;
9696 }
9697 assert (SrcBitWidth == VTBits && "Expected operands of same bitwidth.");
9698 return Common;
9699}
9700
9701unsigned
9702SystemZTargetLowering::ComputeNumSignBitsForTargetNode(
9703 SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
9704 unsigned Depth) const {
9705 if (Op.getResNo() != 0)
9706 return 1;
9707 unsigned Opcode = Op.getOpcode();
9708 if (Opcode == ISD::INTRINSIC_WO_CHAIN) {
9709 unsigned Id = Op.getConstantOperandVal(i: 0);
9710 switch (Id) {
9711 case Intrinsic::s390_vpksh: // PACKS
9712 case Intrinsic::s390_vpksf:
9713 case Intrinsic::s390_vpksg:
9714 case Intrinsic::s390_vpkshs: // PACKS_CC
9715 case Intrinsic::s390_vpksfs:
9716 case Intrinsic::s390_vpksgs:
9717 case Intrinsic::s390_vpklsh: // PACKLS
9718 case Intrinsic::s390_vpklsf:
9719 case Intrinsic::s390_vpklsg:
9720 case Intrinsic::s390_vpklshs: // PACKLS_CC
9721 case Intrinsic::s390_vpklsfs:
9722 case Intrinsic::s390_vpklsgs:
9723 case Intrinsic::s390_vpdi:
9724 case Intrinsic::s390_vsldb:
9725 case Intrinsic::s390_vperm:
9726 return computeNumSignBitsBinOp(Op, DemandedElts, DAG, Depth, OpNo: 1);
9727 case Intrinsic::s390_vuphb: // VECTOR UNPACK HIGH
9728 case Intrinsic::s390_vuphh:
9729 case Intrinsic::s390_vuphf:
9730 case Intrinsic::s390_vuplb: // VECTOR UNPACK LOW
9731 case Intrinsic::s390_vuplhw:
9732 case Intrinsic::s390_vuplf: {
9733 SDValue PackedOp = Op.getOperand(i: 1);
9734 APInt SrcDemE = getDemandedSrcElements(Op, DemandedElts, OpNo: 1);
9735 unsigned Tmp = DAG.ComputeNumSignBits(Op: PackedOp, DemandedElts: SrcDemE, Depth: Depth + 1);
9736 EVT VT = Op.getValueType();
9737 unsigned VTBits = VT.getScalarSizeInBits();
9738 Tmp += VTBits - PackedOp.getScalarValueSizeInBits();
9739 return Tmp;
9740 }
9741 default:
9742 break;
9743 }
9744 } else {
9745 switch (Opcode) {
9746 case SystemZISD::SELECT_CCMASK:
9747 return computeNumSignBitsBinOp(Op, DemandedElts, DAG, Depth, OpNo: 0);
9748 default:
9749 break;
9750 }
9751 }
9752
9753 return 1;
9754}
9755
9756bool SystemZTargetLowering::isGuaranteedNotToBeUndefOrPoisonForTargetNode(
9757 SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
9758 UndefPoisonKind Kind, unsigned Depth) const {
9759 switch (Op->getOpcode()) {
9760 case SystemZISD::PCREL_WRAPPER:
9761 case SystemZISD::PCREL_OFFSET:
9762 return true;
9763 }
9764 return false;
9765}
9766
9767unsigned
9768SystemZTargetLowering::getStackProbeSize(const MachineFunction &MF) const {
9769 const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
9770 unsigned StackAlign = TFI->getStackAlignment();
9771 assert(StackAlign >=1 && isPowerOf2_32(StackAlign) &&
9772 "Unexpected stack alignment");
9773 // The default stack probe size is 4096 if the function has no
9774 // stack-probe-size attribute.
9775 unsigned StackProbeSize =
9776 MF.getFunction().getFnAttributeAsParsedInteger(Kind: "stack-probe-size", Default: 4096);
9777 // Round down to the stack alignment.
9778 StackProbeSize &= ~(StackAlign - 1);
9779 return StackProbeSize ? StackProbeSize : StackAlign;
9780}
9781
9782//===----------------------------------------------------------------------===//
9783// Custom insertion
9784//===----------------------------------------------------------------------===//
9785
9786// Force base value Base into a register before MI. Return the register.
9787static Register forceReg(MachineInstr &MI, MachineOperand &Base,
9788 const SystemZInstrInfo *TII) {
9789 MachineBasicBlock *MBB = MI.getParent();
9790 MachineFunction &MF = *MBB->getParent();
9791 MachineRegisterInfo &MRI = MF.getRegInfo();
9792
9793 if (Base.isReg()) {
9794 // Copy Base into a new virtual register to help register coalescing in
9795 // cases with multiple uses.
9796 Register Reg = MRI.createVirtualRegister(RegClass: &SystemZ::ADDR64BitRegClass);
9797 BuildMI(BB&: *MBB, I&: MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: SystemZ::COPY), DestReg: Reg)
9798 .add(MO: Base);
9799 return Reg;
9800 }
9801
9802 Register Reg = MRI.createVirtualRegister(RegClass: &SystemZ::ADDR64BitRegClass);
9803 BuildMI(BB&: *MBB, I&: MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: SystemZ::LA), DestReg: Reg)
9804 .add(MO: Base)
9805 .addImm(Val: 0)
9806 .addReg(RegNo: 0);
9807 return Reg;
9808}
9809
9810// The CC operand of MI might be missing a kill marker because there
9811// were multiple uses of CC, and ISel didn't know which to mark.
9812// Figure out whether MI should have had a kill marker.
9813static bool checkCCKill(MachineInstr &MI, MachineBasicBlock *MBB) {
9814 // Scan forward through BB for a use/def of CC.
9815 MachineBasicBlock::iterator miI(std::next(x: MachineBasicBlock::iterator(MI)));
9816 for (MachineBasicBlock::iterator miE = MBB->end(); miI != miE; ++miI) {
9817 const MachineInstr &MI = *miI;
9818 if (MI.readsRegister(Reg: SystemZ::CC, /*TRI=*/nullptr))
9819 return false;
9820 if (MI.definesRegister(Reg: SystemZ::CC, /*TRI=*/nullptr))
9821 break; // Should have kill-flag - update below.
9822 }
9823
9824 // If we hit the end of the block, check whether CC is live into a
9825 // successor.
9826 if (miI == MBB->end()) {
9827 for (const MachineBasicBlock *Succ : MBB->successors())
9828 if (Succ->isLiveIn(Reg: SystemZ::CC))
9829 return false;
9830 }
9831
9832 return true;
9833}
9834
9835// Return true if it is OK for this Select pseudo-opcode to be cascaded
9836// together with other Select pseudo-opcodes into a single basic-block with
9837// a conditional jump around it.
9838static bool isSelectPseudo(MachineInstr &MI) {
9839 switch (MI.getOpcode()) {
9840 case SystemZ::Select32:
9841 case SystemZ::Select64:
9842 case SystemZ::Select128:
9843 case SystemZ::SelectF32:
9844 case SystemZ::SelectF64:
9845 case SystemZ::SelectF128:
9846 case SystemZ::SelectVR32:
9847 case SystemZ::SelectVR64:
9848 case SystemZ::SelectVR128:
9849 return true;
9850
9851 default:
9852 return false;
9853 }
9854}
9855
9856// Helper function, which inserts PHI functions into SinkMBB:
9857// %Result(i) = phi [ %FalseValue(i), FalseMBB ], [ %TrueValue(i), TrueMBB ],
9858// where %FalseValue(i) and %TrueValue(i) are taken from Selects.
9859static void createPHIsForSelects(SmallVector<MachineInstr*, 8> &Selects,
9860 MachineBasicBlock *TrueMBB,
9861 MachineBasicBlock *FalseMBB,
9862 MachineBasicBlock *SinkMBB) {
9863 MachineFunction *MF = TrueMBB->getParent();
9864 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
9865
9866 MachineInstr *FirstMI = Selects.front();
9867 unsigned CCValid = FirstMI->getOperand(i: 3).getImm();
9868 unsigned CCMask = FirstMI->getOperand(i: 4).getImm();
9869
9870 MachineBasicBlock::iterator SinkInsertionPoint = SinkMBB->begin();
9871
9872 // As we are creating the PHIs, we have to be careful if there is more than
9873 // one. Later Selects may reference the results of earlier Selects, but later
9874 // PHIs have to reference the individual true/false inputs from earlier PHIs.
9875 // That also means that PHI construction must work forward from earlier to
9876 // later, and that the code must maintain a mapping from earlier PHI's
9877 // destination registers, and the registers that went into the PHI.
9878 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
9879
9880 for (auto *MI : Selects) {
9881 Register DestReg = MI->getOperand(i: 0).getReg();
9882 Register TrueReg = MI->getOperand(i: 1).getReg();
9883 Register FalseReg = MI->getOperand(i: 2).getReg();
9884
9885 // If this Select we are generating is the opposite condition from
9886 // the jump we generated, then we have to swap the operands for the
9887 // PHI that is going to be generated.
9888 if (MI->getOperand(i: 4).getImm() == (CCValid ^ CCMask))
9889 std::swap(a&: TrueReg, b&: FalseReg);
9890
9891 if (auto It = RegRewriteTable.find(Val: TrueReg); It != RegRewriteTable.end())
9892 TrueReg = It->second.first;
9893
9894 if (auto It = RegRewriteTable.find(Val: FalseReg); It != RegRewriteTable.end())
9895 FalseReg = It->second.second;
9896
9897 DebugLoc DL = MI->getDebugLoc();
9898 BuildMI(BB&: *SinkMBB, I: SinkInsertionPoint, MIMD: DL, MCID: TII->get(Opcode: SystemZ::PHI), DestReg)
9899 .addReg(RegNo: TrueReg).addMBB(MBB: TrueMBB)
9900 .addReg(RegNo: FalseReg).addMBB(MBB: FalseMBB);
9901
9902 // Add this PHI to the rewrite table.
9903 RegRewriteTable[DestReg] = std::make_pair(x&: TrueReg, y&: FalseReg);
9904 }
9905
9906 MF->getProperties().resetNoPHIs();
9907}
9908
9909MachineBasicBlock *
9910SystemZTargetLowering::emitAdjCallStack(MachineInstr &MI,
9911 MachineBasicBlock *BB) const {
9912 MachineFunction &MF = *BB->getParent();
9913 MachineFrameInfo &MFI = MF.getFrameInfo();
9914 auto *TFL = Subtarget.getFrameLowering<SystemZFrameLowering>();
9915 assert(TFL->hasReservedCallFrame(MF) &&
9916 "ADJSTACKDOWN and ADJSTACKUP should be no-ops");
9917 (void)TFL;
9918 // Get the MaxCallFrameSize value and erase MI since it serves no further
9919 // purpose as the call frame is statically reserved in the prolog. Set
9920 // AdjustsStack as MI is *not* mapped as a frame instruction.
9921 uint32_t NumBytes = MI.getOperand(i: 0).getImm();
9922 if (NumBytes > MFI.getMaxCallFrameSize())
9923 MFI.setMaxCallFrameSize(NumBytes);
9924 MFI.setAdjustsStack(true);
9925
9926 MI.eraseFromParent();
9927 return BB;
9928}
9929
9930// Implement EmitInstrWithCustomInserter for pseudo Select* instruction MI.
9931MachineBasicBlock *
9932SystemZTargetLowering::emitSelect(MachineInstr &MI,
9933 MachineBasicBlock *MBB) const {
9934 assert(isSelectPseudo(MI) && "Bad call to emitSelect()");
9935 const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
9936
9937 unsigned CCValid = MI.getOperand(i: 3).getImm();
9938 unsigned CCMask = MI.getOperand(i: 4).getImm();
9939
9940 // If we have a sequence of Select* pseudo instructions using the
9941 // same condition code value, we want to expand all of them into
9942 // a single pair of basic blocks using the same condition.
9943 SmallVector<MachineInstr*, 8> Selects;
9944 SmallVector<MachineInstr*, 8> DbgValues;
9945 Selects.push_back(Elt: &MI);
9946 unsigned Count = 0;
9947 for (MachineInstr &NextMI : llvm::make_range(
9948 x: std::next(x: MachineBasicBlock::iterator(MI)), y: MBB->end())) {
9949 if (isSelectPseudo(MI&: NextMI)) {
9950 assert(NextMI.getOperand(3).getImm() == CCValid &&
9951 "Bad CCValid operands since CC was not redefined.");
9952 if (NextMI.getOperand(i: 4).getImm() == CCMask ||
9953 NextMI.getOperand(i: 4).getImm() == (CCValid ^ CCMask)) {
9954 Selects.push_back(Elt: &NextMI);
9955 continue;
9956 }
9957 break;
9958 }
9959 if (NextMI.definesRegister(Reg: SystemZ::CC, /*TRI=*/nullptr) ||
9960 NextMI.usesCustomInsertionHook())
9961 break;
9962 bool User = false;
9963 for (auto *SelMI : Selects)
9964 if (NextMI.readsVirtualRegister(Reg: SelMI->getOperand(i: 0).getReg())) {
9965 User = true;
9966 break;
9967 }
9968 if (NextMI.isDebugInstr()) {
9969 if (User) {
9970 assert(NextMI.isDebugValue() && "Unhandled debug opcode.");
9971 DbgValues.push_back(Elt: &NextMI);
9972 }
9973 } else if (User || ++Count > 20)
9974 break;
9975 }
9976
9977 MachineInstr *LastMI = Selects.back();
9978 bool CCKilled = (LastMI->killsRegister(Reg: SystemZ::CC, /*TRI=*/nullptr) ||
9979 checkCCKill(MI&: *LastMI, MBB));
9980 MachineBasicBlock *StartMBB = MBB;
9981 MachineBasicBlock *JoinMBB = SystemZ::splitBlockAfter(MI: LastMI, MBB);
9982 MachineBasicBlock *FalseMBB = SystemZ::emitBlockAfter(MBB: StartMBB);
9983
9984 // Unless CC was killed in the last Select instruction, mark it as
9985 // live-in to both FalseMBB and JoinMBB.
9986 if (!CCKilled) {
9987 FalseMBB->addLiveIn(PhysReg: SystemZ::CC);
9988 JoinMBB->addLiveIn(PhysReg: SystemZ::CC);
9989 }
9990
9991 // StartMBB:
9992 // BRC CCMask, JoinMBB
9993 // # fallthrough to FalseMBB
9994 MBB = StartMBB;
9995 BuildMI(BB: MBB, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: SystemZ::BRC))
9996 .addImm(Val: CCValid).addImm(Val: CCMask).addMBB(MBB: JoinMBB);
9997 MBB->addSuccessor(Succ: JoinMBB);
9998 MBB->addSuccessor(Succ: FalseMBB);
9999
10000 // FalseMBB:
10001 // # fallthrough to JoinMBB
10002 MBB = FalseMBB;
10003 MBB->addSuccessor(Succ: JoinMBB);
10004
10005 // JoinMBB:
10006 // %Result = phi [ %FalseReg, FalseMBB ], [ %TrueReg, StartMBB ]
10007 // ...
10008 MBB = JoinMBB;
10009 createPHIsForSelects(Selects, TrueMBB: StartMBB, FalseMBB, SinkMBB: MBB);
10010 for (auto *SelMI : Selects)
10011 SelMI->eraseFromParent();
10012
10013 MachineBasicBlock::iterator InsertPos = MBB->getFirstNonPHI();
10014 for (auto *DbgMI : DbgValues)
10015 MBB->splice(Where: InsertPos, Other: StartMBB, From: DbgMI);
10016
10017 return JoinMBB;
10018}
10019
10020// Implement EmitInstrWithCustomInserter for pseudo CondStore* instruction MI.
10021// StoreOpcode is the store to use and Invert says whether the store should
10022// happen when the condition is false rather than true. If a STORE ON
10023// CONDITION is available, STOCOpcode is its opcode, otherwise it is 0.
10024MachineBasicBlock *SystemZTargetLowering::emitCondStore(MachineInstr &MI,
10025 MachineBasicBlock *MBB,
10026 unsigned StoreOpcode,
10027 unsigned STOCOpcode,
10028 bool Invert) const {
10029 const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
10030
10031 Register SrcReg = MI.getOperand(i: 0).getReg();
10032 MachineOperand Base = MI.getOperand(i: 1);
10033 int64_t Disp = MI.getOperand(i: 2).getImm();
10034 Register IndexReg = MI.getOperand(i: 3).getReg();
10035 unsigned CCValid = MI.getOperand(i: 4).getImm();
10036 unsigned CCMask = MI.getOperand(i: 5).getImm();
10037 DebugLoc DL = MI.getDebugLoc();
10038
10039 StoreOpcode = TII->getOpcodeForOffset(Opcode: StoreOpcode, Offset: Disp);
10040
10041 // ISel pattern matching also adds a load memory operand of the same
10042 // address, so take special care to find the storing memory operand.
10043 MachineMemOperand *MMO = nullptr;
10044 for (auto *I : MI.memoperands())
10045 if (I->isStore()) {
10046 MMO = I;
10047 break;
10048 }
10049
10050 // Use STOCOpcode if possible. We could use different store patterns in
10051 // order to avoid matching the index register, but the performance trade-offs
10052 // might be more complicated in that case.
10053 if (STOCOpcode && !IndexReg && Subtarget.hasLoadStoreOnCond()) {
10054 if (Invert)
10055 CCMask ^= CCValid;
10056
10057 BuildMI(BB&: *MBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: STOCOpcode))
10058 .addReg(RegNo: SrcReg)
10059 .add(MO: Base)
10060 .addImm(Val: Disp)
10061 .addImm(Val: CCValid)
10062 .addImm(Val: CCMask)
10063 .addMemOperand(MMO);
10064
10065 MI.eraseFromParent();
10066 return MBB;
10067 }
10068
10069 // Get the condition needed to branch around the store.
10070 if (!Invert)
10071 CCMask ^= CCValid;
10072
10073 MachineBasicBlock *StartMBB = MBB;
10074 MachineBasicBlock *JoinMBB = SystemZ::splitBlockBefore(MI, MBB);
10075 MachineBasicBlock *FalseMBB = SystemZ::emitBlockAfter(MBB: StartMBB);
10076
10077 // Unless CC was killed in the CondStore instruction, mark it as
10078 // live-in to both FalseMBB and JoinMBB.
10079 if (!MI.killsRegister(Reg: SystemZ::CC, /*TRI=*/nullptr) &&
10080 !checkCCKill(MI, MBB: JoinMBB)) {
10081 FalseMBB->addLiveIn(PhysReg: SystemZ::CC);
10082 JoinMBB->addLiveIn(PhysReg: SystemZ::CC);
10083 }
10084
10085 // StartMBB:
10086 // BRC CCMask, JoinMBB
10087 // # fallthrough to FalseMBB
10088 MBB = StartMBB;
10089 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::BRC))
10090 .addImm(Val: CCValid).addImm(Val: CCMask).addMBB(MBB: JoinMBB);
10091 MBB->addSuccessor(Succ: JoinMBB);
10092 MBB->addSuccessor(Succ: FalseMBB);
10093
10094 // FalseMBB:
10095 // store %SrcReg, %Disp(%Index,%Base)
10096 // # fallthrough to JoinMBB
10097 MBB = FalseMBB;
10098 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: StoreOpcode))
10099 .addReg(RegNo: SrcReg)
10100 .add(MO: Base)
10101 .addImm(Val: Disp)
10102 .addReg(RegNo: IndexReg)
10103 .addMemOperand(MMO);
10104 MBB->addSuccessor(Succ: JoinMBB);
10105
10106 MI.eraseFromParent();
10107 return JoinMBB;
10108}
10109
10110// Implement EmitInstrWithCustomInserter for pseudo [SU]Cmp128Hi instruction MI.
10111MachineBasicBlock *
10112SystemZTargetLowering::emitICmp128Hi(MachineInstr &MI,
10113 MachineBasicBlock *MBB,
10114 bool Unsigned) const {
10115 MachineFunction &MF = *MBB->getParent();
10116 const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
10117 MachineRegisterInfo &MRI = MF.getRegInfo();
10118
10119 // Synthetic instruction to compare 128-bit values.
10120 // Sets CC 1 if Op0 > Op1, sets a different CC otherwise.
10121 Register Op0 = MI.getOperand(i: 0).getReg();
10122 Register Op1 = MI.getOperand(i: 1).getReg();
10123
10124 MachineBasicBlock *StartMBB = MBB;
10125 MachineBasicBlock *JoinMBB = SystemZ::splitBlockAfter(MI, MBB);
10126 MachineBasicBlock *HiEqMBB = SystemZ::emitBlockAfter(MBB: StartMBB);
10127
10128 // StartMBB:
10129 //
10130 // Use VECTOR ELEMENT COMPARE [LOGICAL] to compare the high parts.
10131 // Swap the inputs to get:
10132 // CC 1 if high(Op0) > high(Op1)
10133 // CC 2 if high(Op0) < high(Op1)
10134 // CC 0 if high(Op0) == high(Op1)
10135 //
10136 // If CC != 0, we'd done, so jump over the next instruction.
10137 //
10138 // VEC[L]G Op1, Op0
10139 // JNE JoinMBB
10140 // # fallthrough to HiEqMBB
10141 MBB = StartMBB;
10142 int HiOpcode = Unsigned? SystemZ::VECLG : SystemZ::VECG;
10143 BuildMI(BB: MBB, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: HiOpcode))
10144 .addReg(RegNo: Op1).addReg(RegNo: Op0);
10145 BuildMI(BB: MBB, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: SystemZ::BRC))
10146 .addImm(Val: SystemZ::CCMASK_ICMP).addImm(Val: SystemZ::CCMASK_CMP_NE).addMBB(MBB: JoinMBB);
10147 MBB->addSuccessor(Succ: JoinMBB);
10148 MBB->addSuccessor(Succ: HiEqMBB);
10149
10150 // HiEqMBB:
10151 //
10152 // Otherwise, use VECTOR COMPARE HIGH LOGICAL.
10153 // Since we already know the high parts are equal, the CC
10154 // result will only depend on the low parts:
10155 // CC 1 if low(Op0) > low(Op1)
10156 // CC 3 if low(Op0) <= low(Op1)
10157 //
10158 // VCHLGS Tmp, Op0, Op1
10159 // # fallthrough to JoinMBB
10160 MBB = HiEqMBB;
10161 Register Temp = MRI.createVirtualRegister(RegClass: &SystemZ::VR128BitRegClass);
10162 BuildMI(BB: MBB, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: SystemZ::VCHLGS), DestReg: Temp)
10163 .addReg(RegNo: Op0).addReg(RegNo: Op1);
10164 MBB->addSuccessor(Succ: JoinMBB);
10165
10166 // Mark CC as live-in to JoinMBB.
10167 JoinMBB->addLiveIn(PhysReg: SystemZ::CC);
10168
10169 MI.eraseFromParent();
10170 return JoinMBB;
10171}
10172
10173// Implement EmitInstrWithCustomInserter for subword pseudo ATOMIC_LOADW_* or
10174// ATOMIC_SWAPW instruction MI. BinOpcode is the instruction that performs
10175// the binary operation elided by "*", or 0 for ATOMIC_SWAPW. Invert says
10176// whether the field should be inverted after performing BinOpcode (e.g. for
10177// NAND).
10178MachineBasicBlock *SystemZTargetLowering::emitAtomicLoadBinary(
10179 MachineInstr &MI, MachineBasicBlock *MBB, unsigned BinOpcode,
10180 bool Invert) const {
10181 MachineFunction &MF = *MBB->getParent();
10182 const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
10183 MachineRegisterInfo &MRI = MF.getRegInfo();
10184
10185 // Extract the operands. Base can be a register or a frame index.
10186 // Src2 can be a register or immediate.
10187 Register Dest = MI.getOperand(i: 0).getReg();
10188 MachineOperand Base = earlyUseOperand(Op: MI.getOperand(i: 1));
10189 int64_t Disp = MI.getOperand(i: 2).getImm();
10190 MachineOperand Src2 = earlyUseOperand(Op: MI.getOperand(i: 3));
10191 Register BitShift = MI.getOperand(i: 4).getReg();
10192 Register NegBitShift = MI.getOperand(i: 5).getReg();
10193 unsigned BitSize = MI.getOperand(i: 6).getImm();
10194 DebugLoc DL = MI.getDebugLoc();
10195
10196 // Get the right opcodes for the displacement.
10197 unsigned LOpcode = TII->getOpcodeForOffset(Opcode: SystemZ::L, Offset: Disp);
10198 unsigned CSOpcode = TII->getOpcodeForOffset(Opcode: SystemZ::CS, Offset: Disp);
10199 assert(LOpcode && CSOpcode && "Displacement out of range");
10200
10201 // Create virtual registers for temporary results.
10202 Register OrigVal = MRI.createVirtualRegister(RegClass: &SystemZ::GR32BitRegClass);
10203 Register OldVal = MRI.createVirtualRegister(RegClass: &SystemZ::GR32BitRegClass);
10204 Register NewVal = MRI.createVirtualRegister(RegClass: &SystemZ::GR32BitRegClass);
10205 Register RotatedOldVal = MRI.createVirtualRegister(RegClass: &SystemZ::GR32BitRegClass);
10206 Register RotatedNewVal = MRI.createVirtualRegister(RegClass: &SystemZ::GR32BitRegClass);
10207
10208 // Insert a basic block for the main loop.
10209 MachineBasicBlock *StartMBB = MBB;
10210 MachineBasicBlock *DoneMBB = SystemZ::splitBlockBefore(MI, MBB);
10211 MachineBasicBlock *LoopMBB = SystemZ::emitBlockAfter(MBB: StartMBB);
10212
10213 // StartMBB:
10214 // ...
10215 // %OrigVal = L Disp(%Base)
10216 // # fall through to LoopMBB
10217 MBB = StartMBB;
10218 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: LOpcode), DestReg: OrigVal).add(MO: Base).addImm(Val: Disp).addReg(RegNo: 0);
10219 MBB->addSuccessor(Succ: LoopMBB);
10220
10221 // LoopMBB:
10222 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, LoopMBB ]
10223 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
10224 // %RotatedNewVal = OP %RotatedOldVal, %Src2
10225 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
10226 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
10227 // JNE LoopMBB
10228 // # fall through to DoneMBB
10229 MBB = LoopMBB;
10230 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::PHI), DestReg: OldVal)
10231 .addReg(RegNo: OrigVal).addMBB(MBB: StartMBB)
10232 .addReg(RegNo: Dest).addMBB(MBB: LoopMBB);
10233 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::RLL), DestReg: RotatedOldVal)
10234 .addReg(RegNo: OldVal).addReg(RegNo: BitShift).addImm(Val: 0);
10235 if (Invert) {
10236 // Perform the operation normally and then invert every bit of the field.
10237 Register Tmp = MRI.createVirtualRegister(RegClass: &SystemZ::GR32BitRegClass);
10238 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: BinOpcode), DestReg: Tmp).addReg(RegNo: RotatedOldVal).add(MO: Src2);
10239 // XILF with the upper BitSize bits set.
10240 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::XILF), DestReg: RotatedNewVal)
10241 .addReg(RegNo: Tmp).addImm(Val: -1U << (32 - BitSize));
10242 } else if (BinOpcode)
10243 // A simply binary operation.
10244 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: BinOpcode), DestReg: RotatedNewVal)
10245 .addReg(RegNo: RotatedOldVal)
10246 .add(MO: Src2);
10247 else
10248 // Use RISBG to rotate Src2 into position and use it to replace the
10249 // field in RotatedOldVal.
10250 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::RISBG32), DestReg: RotatedNewVal)
10251 .addReg(RegNo: RotatedOldVal).addReg(RegNo: Src2.getReg())
10252 .addImm(Val: 32).addImm(Val: 31 + BitSize).addImm(Val: 32 - BitSize);
10253 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::RLL), DestReg: NewVal)
10254 .addReg(RegNo: RotatedNewVal).addReg(RegNo: NegBitShift).addImm(Val: 0);
10255 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: CSOpcode), DestReg: Dest)
10256 .addReg(RegNo: OldVal)
10257 .addReg(RegNo: NewVal)
10258 .add(MO: Base)
10259 .addImm(Val: Disp);
10260 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::BRC))
10261 .addImm(Val: SystemZ::CCMASK_CS).addImm(Val: SystemZ::CCMASK_CS_NE).addMBB(MBB: LoopMBB);
10262 MBB->addSuccessor(Succ: LoopMBB);
10263 MBB->addSuccessor(Succ: DoneMBB);
10264
10265 MI.eraseFromParent();
10266 return DoneMBB;
10267}
10268
10269// Implement EmitInstrWithCustomInserter for subword pseudo
10270// ATOMIC_LOADW_{,U}{MIN,MAX} instruction MI. CompareOpcode is the
10271// instruction that should be used to compare the current field with the
10272// minimum or maximum value. KeepOldMask is the BRC condition-code mask
10273// for when the current field should be kept.
10274MachineBasicBlock *SystemZTargetLowering::emitAtomicLoadMinMax(
10275 MachineInstr &MI, MachineBasicBlock *MBB, unsigned CompareOpcode,
10276 unsigned KeepOldMask) const {
10277 MachineFunction &MF = *MBB->getParent();
10278 const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
10279 MachineRegisterInfo &MRI = MF.getRegInfo();
10280
10281 // Extract the operands. Base can be a register or a frame index.
10282 Register Dest = MI.getOperand(i: 0).getReg();
10283 MachineOperand Base = earlyUseOperand(Op: MI.getOperand(i: 1));
10284 int64_t Disp = MI.getOperand(i: 2).getImm();
10285 Register Src2 = MI.getOperand(i: 3).getReg();
10286 Register BitShift = MI.getOperand(i: 4).getReg();
10287 Register NegBitShift = MI.getOperand(i: 5).getReg();
10288 unsigned BitSize = MI.getOperand(i: 6).getImm();
10289 DebugLoc DL = MI.getDebugLoc();
10290
10291 // Get the right opcodes for the displacement.
10292 unsigned LOpcode = TII->getOpcodeForOffset(Opcode: SystemZ::L, Offset: Disp);
10293 unsigned CSOpcode = TII->getOpcodeForOffset(Opcode: SystemZ::CS, Offset: Disp);
10294 assert(LOpcode && CSOpcode && "Displacement out of range");
10295
10296 // Create virtual registers for temporary results.
10297 Register OrigVal = MRI.createVirtualRegister(RegClass: &SystemZ::GR32BitRegClass);
10298 Register OldVal = MRI.createVirtualRegister(RegClass: &SystemZ::GR32BitRegClass);
10299 Register NewVal = MRI.createVirtualRegister(RegClass: &SystemZ::GR32BitRegClass);
10300 Register RotatedOldVal = MRI.createVirtualRegister(RegClass: &SystemZ::GR32BitRegClass);
10301 Register RotatedAltVal = MRI.createVirtualRegister(RegClass: &SystemZ::GR32BitRegClass);
10302 Register RotatedNewVal = MRI.createVirtualRegister(RegClass: &SystemZ::GR32BitRegClass);
10303
10304 // Insert 3 basic blocks for the loop.
10305 MachineBasicBlock *StartMBB = MBB;
10306 MachineBasicBlock *DoneMBB = SystemZ::splitBlockBefore(MI, MBB);
10307 MachineBasicBlock *LoopMBB = SystemZ::emitBlockAfter(MBB: StartMBB);
10308 MachineBasicBlock *UseAltMBB = SystemZ::emitBlockAfter(MBB: LoopMBB);
10309 MachineBasicBlock *UpdateMBB = SystemZ::emitBlockAfter(MBB: UseAltMBB);
10310
10311 // StartMBB:
10312 // ...
10313 // %OrigVal = L Disp(%Base)
10314 // # fall through to LoopMBB
10315 MBB = StartMBB;
10316 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: LOpcode), DestReg: OrigVal).add(MO: Base).addImm(Val: Disp).addReg(RegNo: 0);
10317 MBB->addSuccessor(Succ: LoopMBB);
10318
10319 // LoopMBB:
10320 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, UpdateMBB ]
10321 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
10322 // CompareOpcode %RotatedOldVal, %Src2
10323 // BRC KeepOldMask, UpdateMBB
10324 MBB = LoopMBB;
10325 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::PHI), DestReg: OldVal)
10326 .addReg(RegNo: OrigVal).addMBB(MBB: StartMBB)
10327 .addReg(RegNo: Dest).addMBB(MBB: UpdateMBB);
10328 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::RLL), DestReg: RotatedOldVal)
10329 .addReg(RegNo: OldVal).addReg(RegNo: BitShift).addImm(Val: 0);
10330 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: CompareOpcode))
10331 .addReg(RegNo: RotatedOldVal).addReg(RegNo: Src2);
10332 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::BRC))
10333 .addImm(Val: SystemZ::CCMASK_ICMP).addImm(Val: KeepOldMask).addMBB(MBB: UpdateMBB);
10334 MBB->addSuccessor(Succ: UpdateMBB);
10335 MBB->addSuccessor(Succ: UseAltMBB);
10336
10337 // UseAltMBB:
10338 // %RotatedAltVal = RISBG %RotatedOldVal, %Src2, 32, 31 + BitSize, 0
10339 // # fall through to UpdateMBB
10340 MBB = UseAltMBB;
10341 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::RISBG32), DestReg: RotatedAltVal)
10342 .addReg(RegNo: RotatedOldVal).addReg(RegNo: Src2)
10343 .addImm(Val: 32).addImm(Val: 31 + BitSize).addImm(Val: 0);
10344 MBB->addSuccessor(Succ: UpdateMBB);
10345
10346 // UpdateMBB:
10347 // %RotatedNewVal = PHI [ %RotatedOldVal, LoopMBB ],
10348 // [ %RotatedAltVal, UseAltMBB ]
10349 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
10350 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
10351 // JNE LoopMBB
10352 // # fall through to DoneMBB
10353 MBB = UpdateMBB;
10354 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::PHI), DestReg: RotatedNewVal)
10355 .addReg(RegNo: RotatedOldVal).addMBB(MBB: LoopMBB)
10356 .addReg(RegNo: RotatedAltVal).addMBB(MBB: UseAltMBB);
10357 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::RLL), DestReg: NewVal)
10358 .addReg(RegNo: RotatedNewVal).addReg(RegNo: NegBitShift).addImm(Val: 0);
10359 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: CSOpcode), DestReg: Dest)
10360 .addReg(RegNo: OldVal)
10361 .addReg(RegNo: NewVal)
10362 .add(MO: Base)
10363 .addImm(Val: Disp);
10364 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::BRC))
10365 .addImm(Val: SystemZ::CCMASK_CS).addImm(Val: SystemZ::CCMASK_CS_NE).addMBB(MBB: LoopMBB);
10366 MBB->addSuccessor(Succ: LoopMBB);
10367 MBB->addSuccessor(Succ: DoneMBB);
10368
10369 MI.eraseFromParent();
10370 return DoneMBB;
10371}
10372
10373// Implement EmitInstrWithCustomInserter for subword pseudo ATOMIC_CMP_SWAPW
10374// instruction MI.
10375MachineBasicBlock *
10376SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr &MI,
10377 MachineBasicBlock *MBB) const {
10378 MachineFunction &MF = *MBB->getParent();
10379 const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
10380 MachineRegisterInfo &MRI = MF.getRegInfo();
10381
10382 // Extract the operands. Base can be a register or a frame index.
10383 Register Dest = MI.getOperand(i: 0).getReg();
10384 MachineOperand Base = earlyUseOperand(Op: MI.getOperand(i: 1));
10385 int64_t Disp = MI.getOperand(i: 2).getImm();
10386 Register CmpVal = MI.getOperand(i: 3).getReg();
10387 Register OrigSwapVal = MI.getOperand(i: 4).getReg();
10388 Register BitShift = MI.getOperand(i: 5).getReg();
10389 Register NegBitShift = MI.getOperand(i: 6).getReg();
10390 int64_t BitSize = MI.getOperand(i: 7).getImm();
10391 DebugLoc DL = MI.getDebugLoc();
10392
10393 const TargetRegisterClass *RC = &SystemZ::GR32BitRegClass;
10394
10395 // Get the right opcodes for the displacement and zero-extension.
10396 unsigned LOpcode = TII->getOpcodeForOffset(Opcode: SystemZ::L, Offset: Disp);
10397 unsigned CSOpcode = TII->getOpcodeForOffset(Opcode: SystemZ::CS, Offset: Disp);
10398 unsigned ZExtOpcode = BitSize == 8 ? SystemZ::LLCR : SystemZ::LLHR;
10399 assert(LOpcode && CSOpcode && "Displacement out of range");
10400
10401 // Create virtual registers for temporary results.
10402 Register OrigOldVal = MRI.createVirtualRegister(RegClass: RC);
10403 Register OldVal = MRI.createVirtualRegister(RegClass: RC);
10404 Register SwapVal = MRI.createVirtualRegister(RegClass: RC);
10405 Register StoreVal = MRI.createVirtualRegister(RegClass: RC);
10406 Register OldValRot = MRI.createVirtualRegister(RegClass: RC);
10407 Register RetryOldVal = MRI.createVirtualRegister(RegClass: RC);
10408 Register RetrySwapVal = MRI.createVirtualRegister(RegClass: RC);
10409
10410 // Insert 2 basic blocks for the loop.
10411 MachineBasicBlock *StartMBB = MBB;
10412 MachineBasicBlock *DoneMBB = SystemZ::splitBlockBefore(MI, MBB);
10413 MachineBasicBlock *LoopMBB = SystemZ::emitBlockAfter(MBB: StartMBB);
10414 MachineBasicBlock *SetMBB = SystemZ::emitBlockAfter(MBB: LoopMBB);
10415
10416 // StartMBB:
10417 // ...
10418 // %OrigOldVal = L Disp(%Base)
10419 // # fall through to LoopMBB
10420 MBB = StartMBB;
10421 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: LOpcode), DestReg: OrigOldVal)
10422 .add(MO: Base)
10423 .addImm(Val: Disp)
10424 .addReg(RegNo: 0);
10425 MBB->addSuccessor(Succ: LoopMBB);
10426
10427 // LoopMBB:
10428 // %OldVal = phi [ %OrigOldVal, EntryBB ], [ %RetryOldVal, SetMBB ]
10429 // %SwapVal = phi [ %OrigSwapVal, EntryBB ], [ %RetrySwapVal, SetMBB ]
10430 // %OldValRot = RLL %OldVal, BitSize(%BitShift)
10431 // ^^ The low BitSize bits contain the field
10432 // of interest.
10433 // %RetrySwapVal = RISBG32 %SwapVal, %OldValRot, 32, 63-BitSize, 0
10434 // ^^ Replace the upper 32-BitSize bits of the
10435 // swap value with those that we loaded and rotated.
10436 // %Dest = LL[CH] %OldValRot
10437 // CR %Dest, %CmpVal
10438 // JNE DoneMBB
10439 // # Fall through to SetMBB
10440 MBB = LoopMBB;
10441 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::PHI), DestReg: OldVal)
10442 .addReg(RegNo: OrigOldVal).addMBB(MBB: StartMBB)
10443 .addReg(RegNo: RetryOldVal).addMBB(MBB: SetMBB);
10444 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::PHI), DestReg: SwapVal)
10445 .addReg(RegNo: OrigSwapVal).addMBB(MBB: StartMBB)
10446 .addReg(RegNo: RetrySwapVal).addMBB(MBB: SetMBB);
10447 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::RLL), DestReg: OldValRot)
10448 .addReg(RegNo: OldVal).addReg(RegNo: BitShift).addImm(Val: BitSize);
10449 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::RISBG32), DestReg: RetrySwapVal)
10450 .addReg(RegNo: SwapVal).addReg(RegNo: OldValRot).addImm(Val: 32).addImm(Val: 63 - BitSize).addImm(Val: 0);
10451 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: ZExtOpcode), DestReg: Dest)
10452 .addReg(RegNo: OldValRot);
10453 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::CR))
10454 .addReg(RegNo: Dest).addReg(RegNo: CmpVal);
10455 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::BRC))
10456 .addImm(Val: SystemZ::CCMASK_ICMP)
10457 .addImm(Val: SystemZ::CCMASK_CMP_NE).addMBB(MBB: DoneMBB);
10458 MBB->addSuccessor(Succ: DoneMBB);
10459 MBB->addSuccessor(Succ: SetMBB);
10460
10461 // SetMBB:
10462 // %StoreVal = RLL %RetrySwapVal, -BitSize(%NegBitShift)
10463 // ^^ Rotate the new field to its proper position.
10464 // %RetryOldVal = CS %OldVal, %StoreVal, Disp(%Base)
10465 // JNE LoopMBB
10466 // # fall through to ExitMBB
10467 MBB = SetMBB;
10468 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::RLL), DestReg: StoreVal)
10469 .addReg(RegNo: RetrySwapVal).addReg(RegNo: NegBitShift).addImm(Val: -BitSize);
10470 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: CSOpcode), DestReg: RetryOldVal)
10471 .addReg(RegNo: OldVal)
10472 .addReg(RegNo: StoreVal)
10473 .add(MO: Base)
10474 .addImm(Val: Disp);
10475 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::BRC))
10476 .addImm(Val: SystemZ::CCMASK_CS).addImm(Val: SystemZ::CCMASK_CS_NE).addMBB(MBB: LoopMBB);
10477 MBB->addSuccessor(Succ: LoopMBB);
10478 MBB->addSuccessor(Succ: DoneMBB);
10479
10480 // If the CC def wasn't dead in the ATOMIC_CMP_SWAPW, mark CC as live-in
10481 // to the block after the loop. At this point, CC may have been defined
10482 // either by the CR in LoopMBB or by the CS in SetMBB.
10483 if (!MI.registerDefIsDead(Reg: SystemZ::CC, /*TRI=*/nullptr))
10484 DoneMBB->addLiveIn(PhysReg: SystemZ::CC);
10485
10486 MI.eraseFromParent();
10487 return DoneMBB;
10488}
10489
10490// Emit a move from two GR64s to a GR128.
10491MachineBasicBlock *
10492SystemZTargetLowering::emitPair128(MachineInstr &MI,
10493 MachineBasicBlock *MBB) const {
10494 const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
10495 const DebugLoc &DL = MI.getDebugLoc();
10496
10497 Register Dest = MI.getOperand(i: 0).getReg();
10498 BuildMI(BB&: *MBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: TargetOpcode::REG_SEQUENCE), DestReg: Dest)
10499 .add(MO: MI.getOperand(i: 1))
10500 .addImm(Val: SystemZ::subreg_h64)
10501 .add(MO: MI.getOperand(i: 2))
10502 .addImm(Val: SystemZ::subreg_l64);
10503 MI.eraseFromParent();
10504 return MBB;
10505}
10506
10507// Emit an extension from a GR64 to a GR128. ClearEven is true
10508// if the high register of the GR128 value must be cleared or false if
10509// it's "don't care".
10510MachineBasicBlock *SystemZTargetLowering::emitExt128(MachineInstr &MI,
10511 MachineBasicBlock *MBB,
10512 bool ClearEven) const {
10513 MachineFunction &MF = *MBB->getParent();
10514 const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
10515 MachineRegisterInfo &MRI = MF.getRegInfo();
10516 DebugLoc DL = MI.getDebugLoc();
10517
10518 Register Dest = MI.getOperand(i: 0).getReg();
10519 Register Src = MI.getOperand(i: 1).getReg();
10520 Register In128 = MRI.createVirtualRegister(RegClass: &SystemZ::GR128BitRegClass);
10521
10522 BuildMI(BB&: *MBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: TargetOpcode::IMPLICIT_DEF), DestReg: In128);
10523 if (ClearEven) {
10524 Register NewIn128 = MRI.createVirtualRegister(RegClass: &SystemZ::GR128BitRegClass);
10525 Register Zero64 = MRI.createVirtualRegister(RegClass: &SystemZ::GR64BitRegClass);
10526
10527 BuildMI(BB&: *MBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: SystemZ::LLILL), DestReg: Zero64)
10528 .addImm(Val: 0);
10529 BuildMI(BB&: *MBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: TargetOpcode::INSERT_SUBREG), DestReg: NewIn128)
10530 .addReg(RegNo: In128).addReg(RegNo: Zero64).addImm(Val: SystemZ::subreg_h64);
10531 In128 = NewIn128;
10532 }
10533 BuildMI(BB&: *MBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: TargetOpcode::INSERT_SUBREG), DestReg: Dest)
10534 .addReg(RegNo: In128).addReg(RegNo: Src).addImm(Val: SystemZ::subreg_l64);
10535
10536 MI.eraseFromParent();
10537 return MBB;
10538}
10539
10540MachineBasicBlock *
10541SystemZTargetLowering::emitMemMemWrapper(MachineInstr &MI,
10542 MachineBasicBlock *MBB,
10543 unsigned Opcode, bool IsMemset) const {
10544 MachineFunction &MF = *MBB->getParent();
10545 const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
10546 MachineRegisterInfo &MRI = MF.getRegInfo();
10547 DebugLoc DL = MI.getDebugLoc();
10548
10549 MachineOperand DestBase = earlyUseOperand(Op: MI.getOperand(i: 0));
10550 uint64_t DestDisp = MI.getOperand(i: 1).getImm();
10551 MachineOperand SrcBase = MachineOperand::CreateReg(Reg: 0U, isDef: false);
10552 uint64_t SrcDisp;
10553
10554 // Fold the displacement Disp if it is out of range.
10555 auto foldDisplIfNeeded = [&](MachineOperand &Base, uint64_t &Disp) -> void {
10556 if (!isUInt<12>(x: Disp)) {
10557 Register Reg = MRI.createVirtualRegister(RegClass: &SystemZ::ADDR64BitRegClass);
10558 unsigned Opcode = TII->getOpcodeForOffset(Opcode: SystemZ::LA, Offset: Disp);
10559 BuildMI(BB&: *MI.getParent(), I&: MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode), DestReg: Reg)
10560 .add(MO: Base).addImm(Val: Disp).addReg(RegNo: 0);
10561 Base = MachineOperand::CreateReg(Reg, isDef: false);
10562 Disp = 0;
10563 }
10564 };
10565
10566 if (!IsMemset) {
10567 SrcBase = earlyUseOperand(Op: MI.getOperand(i: 2));
10568 SrcDisp = MI.getOperand(i: 3).getImm();
10569 } else {
10570 SrcBase = DestBase;
10571 SrcDisp = DestDisp++;
10572 foldDisplIfNeeded(DestBase, DestDisp);
10573 }
10574
10575 MachineOperand &LengthMO = MI.getOperand(i: IsMemset ? 2 : 4);
10576 bool IsImmForm = LengthMO.isImm();
10577 bool IsRegForm = !IsImmForm;
10578
10579 // Build and insert one Opcode of Length, with special treatment for memset.
10580 auto insertMemMemOp = [&](MachineBasicBlock *InsMBB,
10581 MachineBasicBlock::iterator InsPos,
10582 MachineOperand DBase, uint64_t DDisp,
10583 MachineOperand SBase, uint64_t SDisp,
10584 unsigned Length) -> void {
10585 assert(Length > 0 && Length <= 256 && "Building memory op with bad length.");
10586 if (IsMemset) {
10587 MachineOperand ByteMO = earlyUseOperand(Op: MI.getOperand(i: 3));
10588 if (ByteMO.isImm())
10589 BuildMI(BB&: *InsMBB, I: InsPos, MIMD: DL, MCID: TII->get(Opcode: SystemZ::MVI))
10590 .add(MO: SBase).addImm(Val: SDisp).add(MO: ByteMO);
10591 else
10592 BuildMI(BB&: *InsMBB, I: InsPos, MIMD: DL, MCID: TII->get(Opcode: SystemZ::STC))
10593 .add(MO: ByteMO).add(MO: SBase).addImm(Val: SDisp).addReg(RegNo: 0);
10594 if (--Length == 0)
10595 return;
10596 }
10597 BuildMI(BB&: *MBB, I: InsPos, MIMD: DL, MCID: TII->get(Opcode))
10598 .add(MO: DBase).addImm(Val: DDisp).addImm(Val: Length)
10599 .add(MO: SBase).addImm(Val: SDisp)
10600 .setMemRefs(MI.memoperands());
10601 };
10602
10603 bool NeedsLoop = false;
10604 uint64_t ImmLength = 0;
10605 Register LenAdjReg = SystemZ::NoRegister;
10606 if (IsImmForm) {
10607 ImmLength = LengthMO.getImm();
10608 ImmLength += IsMemset ? 2 : 1; // Add back the subtracted adjustment.
10609 if (ImmLength == 0) {
10610 MI.eraseFromParent();
10611 return MBB;
10612 }
10613 if (Opcode == SystemZ::CLC) {
10614 if (ImmLength > 3 * 256)
10615 // A two-CLC sequence is a clear win over a loop, not least because
10616 // it needs only one branch. A three-CLC sequence needs the same
10617 // number of branches as a loop (i.e. 2), but is shorter. That
10618 // brings us to lengths greater than 768 bytes. It seems relatively
10619 // likely that a difference will be found within the first 768 bytes,
10620 // so we just optimize for the smallest number of branch
10621 // instructions, in order to avoid polluting the prediction buffer
10622 // too much.
10623 NeedsLoop = true;
10624 } else if (ImmLength > 6 * 256)
10625 // The heuristic we use is to prefer loops for anything that would
10626 // require 7 or more MVCs. With these kinds of sizes there isn't much
10627 // to choose between straight-line code and looping code, since the
10628 // time will be dominated by the MVCs themselves.
10629 NeedsLoop = true;
10630 } else {
10631 NeedsLoop = true;
10632 LenAdjReg = LengthMO.getReg();
10633 }
10634
10635 // When generating more than one CLC, all but the last will need to
10636 // branch to the end when a difference is found.
10637 MachineBasicBlock *EndMBB =
10638 (Opcode == SystemZ::CLC && (ImmLength > 256 || NeedsLoop)
10639 ? SystemZ::splitBlockAfter(MI, MBB)
10640 : nullptr);
10641
10642 if (NeedsLoop) {
10643 Register StartCountReg =
10644 MRI.createVirtualRegister(RegClass: &SystemZ::GR64BitRegClass);
10645 if (IsImmForm) {
10646 TII->loadImmediate(MBB&: *MBB, MBBI: MI, Reg: StartCountReg, Value: ImmLength / 256);
10647 ImmLength &= 255;
10648 } else {
10649 BuildMI(BB&: *MBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: SystemZ::SRLG), DestReg: StartCountReg)
10650 .addReg(RegNo: LenAdjReg)
10651 .addReg(RegNo: 0)
10652 .addImm(Val: 8);
10653 }
10654
10655 bool HaveSingleBase = DestBase.isIdenticalTo(Other: SrcBase);
10656 auto loadZeroAddress = [&]() -> MachineOperand {
10657 Register Reg = MRI.createVirtualRegister(RegClass: &SystemZ::ADDR64BitRegClass);
10658 BuildMI(BB&: *MBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: SystemZ::LGHI), DestReg: Reg).addImm(Val: 0);
10659 return MachineOperand::CreateReg(Reg, isDef: false);
10660 };
10661 if (DestBase.isReg() && DestBase.getReg() == SystemZ::NoRegister)
10662 DestBase = loadZeroAddress();
10663 if (SrcBase.isReg() && SrcBase.getReg() == SystemZ::NoRegister)
10664 SrcBase = HaveSingleBase ? DestBase : loadZeroAddress();
10665
10666 MachineBasicBlock *StartMBB = nullptr;
10667 MachineBasicBlock *LoopMBB = nullptr;
10668 MachineBasicBlock *NextMBB = nullptr;
10669 MachineBasicBlock *DoneMBB = nullptr;
10670 MachineBasicBlock *AllDoneMBB = nullptr;
10671
10672 Register StartSrcReg = forceReg(MI, Base&: SrcBase, TII);
10673 Register StartDestReg =
10674 (HaveSingleBase ? StartSrcReg : forceReg(MI, Base&: DestBase, TII));
10675
10676 const TargetRegisterClass *RC = &SystemZ::ADDR64BitRegClass;
10677 Register ThisSrcReg = MRI.createVirtualRegister(RegClass: RC);
10678 Register ThisDestReg =
10679 (HaveSingleBase ? ThisSrcReg : MRI.createVirtualRegister(RegClass: RC));
10680 Register NextSrcReg = MRI.createVirtualRegister(RegClass: RC);
10681 Register NextDestReg =
10682 (HaveSingleBase ? NextSrcReg : MRI.createVirtualRegister(RegClass: RC));
10683 RC = &SystemZ::GR64BitRegClass;
10684 Register ThisCountReg = MRI.createVirtualRegister(RegClass: RC);
10685 Register NextCountReg = MRI.createVirtualRegister(RegClass: RC);
10686
10687 if (IsRegForm) {
10688 AllDoneMBB = SystemZ::splitBlockBefore(MI, MBB);
10689 StartMBB = SystemZ::emitBlockAfter(MBB);
10690 LoopMBB = SystemZ::emitBlockAfter(MBB: StartMBB);
10691 NextMBB = (EndMBB ? SystemZ::emitBlockAfter(MBB: LoopMBB) : LoopMBB);
10692 DoneMBB = SystemZ::emitBlockAfter(MBB: NextMBB);
10693
10694 // MBB:
10695 // # Jump to AllDoneMBB if LenAdjReg means 0, or fall thru to StartMBB.
10696 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::CGHI))
10697 .addReg(RegNo: LenAdjReg).addImm(Val: IsMemset ? -2 : -1);
10698 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::BRC))
10699 .addImm(Val: SystemZ::CCMASK_ICMP).addImm(Val: SystemZ::CCMASK_CMP_EQ)
10700 .addMBB(MBB: AllDoneMBB);
10701 MBB->addSuccessor(Succ: AllDoneMBB);
10702 if (!IsMemset)
10703 MBB->addSuccessor(Succ: StartMBB);
10704 else {
10705 // MemsetOneCheckMBB:
10706 // # Jump to MemsetOneMBB for a memset of length 1, or
10707 // # fall thru to StartMBB.
10708 MachineBasicBlock *MemsetOneCheckMBB = SystemZ::emitBlockAfter(MBB);
10709 MachineBasicBlock *MemsetOneMBB = SystemZ::emitBlockAfter(MBB: &*MF.rbegin());
10710 MBB->addSuccessor(Succ: MemsetOneCheckMBB);
10711 MBB = MemsetOneCheckMBB;
10712 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::CGHI))
10713 .addReg(RegNo: LenAdjReg).addImm(Val: -1);
10714 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::BRC))
10715 .addImm(Val: SystemZ::CCMASK_ICMP).addImm(Val: SystemZ::CCMASK_CMP_EQ)
10716 .addMBB(MBB: MemsetOneMBB);
10717 MBB->addSuccessor(Succ: MemsetOneMBB, Prob: {10, 100});
10718 MBB->addSuccessor(Succ: StartMBB, Prob: {90, 100});
10719
10720 // MemsetOneMBB:
10721 // # Jump back to AllDoneMBB after a single MVI or STC.
10722 MBB = MemsetOneMBB;
10723 insertMemMemOp(MBB, MBB->end(),
10724 MachineOperand::CreateReg(Reg: StartDestReg, isDef: false), DestDisp,
10725 MachineOperand::CreateReg(Reg: StartSrcReg, isDef: false), SrcDisp,
10726 1);
10727 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::J)).addMBB(MBB: AllDoneMBB);
10728 MBB->addSuccessor(Succ: AllDoneMBB);
10729 }
10730
10731 // StartMBB:
10732 // # Jump to DoneMBB if %StartCountReg is zero, or fall through to LoopMBB.
10733 MBB = StartMBB;
10734 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::CGHI))
10735 .addReg(RegNo: StartCountReg).addImm(Val: 0);
10736 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::BRC))
10737 .addImm(Val: SystemZ::CCMASK_ICMP).addImm(Val: SystemZ::CCMASK_CMP_EQ)
10738 .addMBB(MBB: DoneMBB);
10739 MBB->addSuccessor(Succ: DoneMBB);
10740 MBB->addSuccessor(Succ: LoopMBB);
10741 }
10742 else {
10743 StartMBB = MBB;
10744 DoneMBB = SystemZ::splitBlockBefore(MI, MBB);
10745 LoopMBB = SystemZ::emitBlockAfter(MBB: StartMBB);
10746 NextMBB = (EndMBB ? SystemZ::emitBlockAfter(MBB: LoopMBB) : LoopMBB);
10747
10748 // StartMBB:
10749 // # fall through to LoopMBB
10750 MBB->addSuccessor(Succ: LoopMBB);
10751
10752 DestBase = MachineOperand::CreateReg(Reg: NextDestReg, isDef: false);
10753 SrcBase = MachineOperand::CreateReg(Reg: NextSrcReg, isDef: false);
10754 if (EndMBB && !ImmLength)
10755 // If the loop handled the whole CLC range, DoneMBB will be empty with
10756 // CC live-through into EndMBB, so add it as live-in.
10757 DoneMBB->addLiveIn(PhysReg: SystemZ::CC);
10758 }
10759
10760 // LoopMBB:
10761 // %ThisDestReg = phi [ %StartDestReg, StartMBB ],
10762 // [ %NextDestReg, NextMBB ]
10763 // %ThisSrcReg = phi [ %StartSrcReg, StartMBB ],
10764 // [ %NextSrcReg, NextMBB ]
10765 // %ThisCountReg = phi [ %StartCountReg, StartMBB ],
10766 // [ %NextCountReg, NextMBB ]
10767 // ( PFD 2, 768+DestDisp(%ThisDestReg) )
10768 // Opcode DestDisp(256,%ThisDestReg), SrcDisp(%ThisSrcReg)
10769 // ( JLH EndMBB )
10770 //
10771 // The prefetch is used only for MVC. The JLH is used only for CLC.
10772 MBB = LoopMBB;
10773 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::PHI), DestReg: ThisDestReg)
10774 .addReg(RegNo: StartDestReg).addMBB(MBB: StartMBB)
10775 .addReg(RegNo: NextDestReg).addMBB(MBB: NextMBB);
10776 if (!HaveSingleBase)
10777 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::PHI), DestReg: ThisSrcReg)
10778 .addReg(RegNo: StartSrcReg).addMBB(MBB: StartMBB)
10779 .addReg(RegNo: NextSrcReg).addMBB(MBB: NextMBB);
10780 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::PHI), DestReg: ThisCountReg)
10781 .addReg(RegNo: StartCountReg).addMBB(MBB: StartMBB)
10782 .addReg(RegNo: NextCountReg).addMBB(MBB: NextMBB);
10783 if (Opcode == SystemZ::MVC)
10784 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::PFD))
10785 .addImm(Val: SystemZ::PFD_WRITE)
10786 .addReg(RegNo: ThisDestReg).addImm(Val: DestDisp - IsMemset + 768).addReg(RegNo: 0);
10787 insertMemMemOp(MBB, MBB->end(),
10788 MachineOperand::CreateReg(Reg: ThisDestReg, isDef: false), DestDisp,
10789 MachineOperand::CreateReg(Reg: ThisSrcReg, isDef: false), SrcDisp, 256);
10790 if (EndMBB) {
10791 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::BRC))
10792 .addImm(Val: SystemZ::CCMASK_ICMP).addImm(Val: SystemZ::CCMASK_CMP_NE)
10793 .addMBB(MBB: EndMBB);
10794 MBB->addSuccessor(Succ: EndMBB);
10795 MBB->addSuccessor(Succ: NextMBB);
10796 }
10797
10798 // NextMBB:
10799 // %NextDestReg = LA 256(%ThisDestReg)
10800 // %NextSrcReg = LA 256(%ThisSrcReg)
10801 // %NextCountReg = AGHI %ThisCountReg, -1
10802 // CGHI %NextCountReg, 0
10803 // JLH LoopMBB
10804 // # fall through to DoneMBB
10805 //
10806 // The AGHI, CGHI and JLH should be converted to BRCTG by later passes.
10807 MBB = NextMBB;
10808 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::LA), DestReg: NextDestReg)
10809 .addReg(RegNo: ThisDestReg).addImm(Val: 256).addReg(RegNo: 0);
10810 if (!HaveSingleBase)
10811 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::LA), DestReg: NextSrcReg)
10812 .addReg(RegNo: ThisSrcReg).addImm(Val: 256).addReg(RegNo: 0);
10813 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::AGHI), DestReg: NextCountReg)
10814 .addReg(RegNo: ThisCountReg).addImm(Val: -1);
10815 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::CGHI))
10816 .addReg(RegNo: NextCountReg).addImm(Val: 0);
10817 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::BRC))
10818 .addImm(Val: SystemZ::CCMASK_ICMP).addImm(Val: SystemZ::CCMASK_CMP_NE)
10819 .addMBB(MBB: LoopMBB);
10820 MBB->addSuccessor(Succ: LoopMBB);
10821 MBB->addSuccessor(Succ: DoneMBB);
10822
10823 MBB = DoneMBB;
10824 if (IsRegForm) {
10825 // DoneMBB:
10826 // # Make PHIs for RemDestReg/RemSrcReg as the loop may or may not run.
10827 // # Use EXecute Relative Long for the remainder of the bytes. The target
10828 // instruction of the EXRL will have a length field of 1 since 0 is an
10829 // illegal value. The number of bytes processed becomes (%LenAdjReg &
10830 // 0xff) + 1.
10831 // # Fall through to AllDoneMBB.
10832 Register RemSrcReg = MRI.createVirtualRegister(RegClass: &SystemZ::ADDR64BitRegClass);
10833 Register RemDestReg = HaveSingleBase ? RemSrcReg
10834 : MRI.createVirtualRegister(RegClass: &SystemZ::ADDR64BitRegClass);
10835 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::PHI), DestReg: RemDestReg)
10836 .addReg(RegNo: StartDestReg).addMBB(MBB: StartMBB)
10837 .addReg(RegNo: NextDestReg).addMBB(MBB: NextMBB);
10838 if (!HaveSingleBase)
10839 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::PHI), DestReg: RemSrcReg)
10840 .addReg(RegNo: StartSrcReg).addMBB(MBB: StartMBB)
10841 .addReg(RegNo: NextSrcReg).addMBB(MBB: NextMBB);
10842 if (IsMemset)
10843 insertMemMemOp(MBB, MBB->end(),
10844 MachineOperand::CreateReg(Reg: RemDestReg, isDef: false), DestDisp,
10845 MachineOperand::CreateReg(Reg: RemSrcReg, isDef: false), SrcDisp, 1);
10846 MachineInstrBuilder EXRL_MIB =
10847 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::EXRL_Pseudo))
10848 .addImm(Val: Opcode)
10849 .addReg(RegNo: LenAdjReg)
10850 .addReg(RegNo: RemDestReg).addImm(Val: DestDisp)
10851 .addReg(RegNo: RemSrcReg).addImm(Val: SrcDisp);
10852 MBB->addSuccessor(Succ: AllDoneMBB);
10853 MBB = AllDoneMBB;
10854 if (Opcode != SystemZ::MVC) {
10855 EXRL_MIB.addReg(RegNo: SystemZ::CC, Flags: RegState::ImplicitDefine);
10856 if (EndMBB)
10857 MBB->addLiveIn(PhysReg: SystemZ::CC);
10858 }
10859 }
10860 MF.getProperties().resetNoPHIs();
10861 }
10862
10863 // Handle any remaining bytes with straight-line code.
10864 while (ImmLength > 0) {
10865 uint64_t ThisLength = std::min(a: ImmLength, b: uint64_t(256));
10866 // The previous iteration might have created out-of-range displacements.
10867 // Apply them using LA/LAY if so.
10868 foldDisplIfNeeded(DestBase, DestDisp);
10869 foldDisplIfNeeded(SrcBase, SrcDisp);
10870 insertMemMemOp(MBB, MI, DestBase, DestDisp, SrcBase, SrcDisp, ThisLength);
10871 DestDisp += ThisLength;
10872 SrcDisp += ThisLength;
10873 ImmLength -= ThisLength;
10874 // If there's another CLC to go, branch to the end if a difference
10875 // was found.
10876 if (EndMBB && ImmLength > 0) {
10877 MachineBasicBlock *NextMBB = SystemZ::splitBlockBefore(MI, MBB);
10878 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::BRC))
10879 .addImm(Val: SystemZ::CCMASK_ICMP).addImm(Val: SystemZ::CCMASK_CMP_NE)
10880 .addMBB(MBB: EndMBB);
10881 MBB->addSuccessor(Succ: EndMBB);
10882 MBB->addSuccessor(Succ: NextMBB);
10883 MBB = NextMBB;
10884 }
10885 }
10886 if (EndMBB) {
10887 MBB->addSuccessor(Succ: EndMBB);
10888 MBB = EndMBB;
10889 MBB->addLiveIn(PhysReg: SystemZ::CC);
10890 }
10891
10892 MI.eraseFromParent();
10893 return MBB;
10894}
10895
10896MachineBasicBlock *
10897SystemZTargetLowering::emitMemmoveImm(MachineInstr &MI,
10898 MachineBasicBlock *MBB) const {
10899 const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
10900
10901 DebugLoc DL = MI.getDebugLoc();
10902 MachineOperand DstAddr = earlyUseOperand(Op: MI.getOperand(i: 0));
10903 MachineOperand SrcAddr = earlyUseOperand(Op: MI.getOperand(i: 1));
10904 uint64_t Len = MI.getOperand(i: 2).getImm();
10905 assert(Len > 0 && Len <= 256 && "Memmove of of unsupported constant length.");
10906
10907 // Use MVC or MVCRL after comparing the addresses.
10908 MachineBasicBlock *DoneMBB = SystemZ::splitBlockAfter(MI, MBB);
10909 MachineBasicBlock *MvcMBB = SystemZ::emitBlockAfter(MBB);
10910 MachineBasicBlock *MvcrlMBB = SystemZ::emitBlockAfter(MBB: MvcMBB);
10911 MBB->addSuccessor(Succ: MvcMBB);
10912 MBB->addSuccessor(Succ: MvcrlMBB);
10913 MvcMBB->addSuccessor(Succ: DoneMBB);
10914 MvcrlMBB->addSuccessor(Succ: DoneMBB);
10915
10916 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::CLGR)).add(MO: SrcAddr).add(MO: DstAddr);
10917 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::BRC))
10918 .addImm(Val: SystemZ::CCMASK_ICMP).addImm(Val: SystemZ::CCMASK_CMP_LT)
10919 .addMBB(MBB: MvcrlMBB);
10920
10921 BuildMI(BB: MvcMBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::MVC))
10922 .add(MO: DstAddr).addImm(Val: 0)
10923 .addImm(Val: Len)
10924 .add(MO: SrcAddr).addImm(Val: 0)
10925 .setMemRefs(MI.memoperands());
10926 BuildMI(BB: MvcMBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::J)).addMBB(MBB: DoneMBB);
10927
10928 BuildMI(BB: MvcrlMBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::LHI), DestReg: SystemZ::R0L).addImm(Val: Len - 1);
10929 BuildMI(BB: MvcrlMBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::MVCRL))
10930 .add(MO: DstAddr).addImm(Val: 0)
10931 .add(MO: SrcAddr).addImm(Val: 0)
10932 .setMemRefs(MI.memoperands());
10933
10934 MI.eraseFromParent();
10935 return DoneMBB;
10936}
10937
10938// Decompose string pseudo-instruction MI into a loop that continually performs
10939// Opcode until CC != 3.
10940MachineBasicBlock *SystemZTargetLowering::emitStringWrapper(
10941 MachineInstr &MI, MachineBasicBlock *MBB, unsigned Opcode) const {
10942 MachineFunction &MF = *MBB->getParent();
10943 const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
10944 MachineRegisterInfo &MRI = MF.getRegInfo();
10945 DebugLoc DL = MI.getDebugLoc();
10946
10947 uint64_t End1Reg = MI.getOperand(i: 0).getReg();
10948 uint64_t Start1Reg = MI.getOperand(i: 1).getReg();
10949 uint64_t Start2Reg = MI.getOperand(i: 2).getReg();
10950 uint64_t CharReg = MI.getOperand(i: 3).getReg();
10951
10952 const TargetRegisterClass *RC = &SystemZ::GR64BitRegClass;
10953 uint64_t This1Reg = MRI.createVirtualRegister(RegClass: RC);
10954 uint64_t This2Reg = MRI.createVirtualRegister(RegClass: RC);
10955 uint64_t End2Reg = MRI.createVirtualRegister(RegClass: RC);
10956
10957 MachineBasicBlock *StartMBB = MBB;
10958 MachineBasicBlock *DoneMBB = SystemZ::splitBlockBefore(MI, MBB);
10959 MachineBasicBlock *LoopMBB = SystemZ::emitBlockAfter(MBB: StartMBB);
10960
10961 // StartMBB:
10962 // # fall through to LoopMBB
10963 MBB->addSuccessor(Succ: LoopMBB);
10964
10965 // LoopMBB:
10966 // %This1Reg = phi [ %Start1Reg, StartMBB ], [ %End1Reg, LoopMBB ]
10967 // %This2Reg = phi [ %Start2Reg, StartMBB ], [ %End2Reg, LoopMBB ]
10968 // R0L = %CharReg
10969 // %End1Reg, %End2Reg = CLST %This1Reg, %This2Reg -- uses R0L
10970 // JO LoopMBB
10971 // # fall through to DoneMBB
10972 //
10973 // The load of R0L can be hoisted by post-RA LICM.
10974 MBB = LoopMBB;
10975
10976 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::PHI), DestReg: This1Reg)
10977 .addReg(RegNo: Start1Reg).addMBB(MBB: StartMBB)
10978 .addReg(RegNo: End1Reg).addMBB(MBB: LoopMBB);
10979 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::PHI), DestReg: This2Reg)
10980 .addReg(RegNo: Start2Reg).addMBB(MBB: StartMBB)
10981 .addReg(RegNo: End2Reg).addMBB(MBB: LoopMBB);
10982 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: TargetOpcode::COPY), DestReg: SystemZ::R0L).addReg(RegNo: CharReg);
10983 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode))
10984 .addReg(RegNo: End1Reg, Flags: RegState::Define).addReg(RegNo: End2Reg, Flags: RegState::Define)
10985 .addReg(RegNo: This1Reg).addReg(RegNo: This2Reg);
10986 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::BRC))
10987 .addImm(Val: SystemZ::CCMASK_ANY).addImm(Val: SystemZ::CCMASK_3).addMBB(MBB: LoopMBB);
10988 MBB->addSuccessor(Succ: LoopMBB);
10989 MBB->addSuccessor(Succ: DoneMBB);
10990
10991 DoneMBB->addLiveIn(PhysReg: SystemZ::CC);
10992
10993 MI.eraseFromParent();
10994 return DoneMBB;
10995}
10996
10997// Update TBEGIN instruction with final opcode and register clobbers.
10998MachineBasicBlock *SystemZTargetLowering::emitTransactionBegin(
10999 MachineInstr &MI, MachineBasicBlock *MBB, unsigned Opcode,
11000 bool NoFloat) const {
11001 MachineFunction &MF = *MBB->getParent();
11002 const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
11003 const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
11004
11005 // Update opcode.
11006 MI.setDesc(TII->get(Opcode));
11007
11008 // We cannot handle a TBEGIN that clobbers the stack or frame pointer.
11009 // Make sure to add the corresponding GRSM bits if they are missing.
11010 uint64_t Control = MI.getOperand(i: 2).getImm();
11011 static const unsigned GPRControlBit[16] = {
11012 0x8000, 0x8000, 0x4000, 0x4000, 0x2000, 0x2000, 0x1000, 0x1000,
11013 0x0800, 0x0800, 0x0400, 0x0400, 0x0200, 0x0200, 0x0100, 0x0100
11014 };
11015 Control |= GPRControlBit[15];
11016 if (TFI->hasFP(MF))
11017 Control |= GPRControlBit[11];
11018 MI.getOperand(i: 2).setImm(Control);
11019
11020 // Add GPR clobbers.
11021 for (int I = 0; I < 16; I++) {
11022 if ((Control & GPRControlBit[I]) == 0) {
11023 unsigned Reg = SystemZMC::GR64Regs[I];
11024 MI.addOperand(Op: MachineOperand::CreateReg(Reg, isDef: true, isImp: true));
11025 }
11026 }
11027
11028 // Add FPR/VR clobbers.
11029 if (!NoFloat && (Control & 4) != 0) {
11030 if (Subtarget.hasVector()) {
11031 for (unsigned Reg : SystemZMC::VR128Regs) {
11032 MI.addOperand(Op: MachineOperand::CreateReg(Reg, isDef: true, isImp: true));
11033 }
11034 } else {
11035 for (unsigned Reg : SystemZMC::FP64Regs) {
11036 MI.addOperand(Op: MachineOperand::CreateReg(Reg, isDef: true, isImp: true));
11037 }
11038 }
11039 }
11040
11041 return MBB;
11042}
11043
11044MachineBasicBlock *SystemZTargetLowering::emitLoadAndTestCmp0(
11045 MachineInstr &MI, MachineBasicBlock *MBB, unsigned Opcode) const {
11046 MachineFunction &MF = *MBB->getParent();
11047 MachineRegisterInfo *MRI = &MF.getRegInfo();
11048 const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
11049 DebugLoc DL = MI.getDebugLoc();
11050
11051 Register SrcReg = MI.getOperand(i: 0).getReg();
11052
11053 // Create new virtual register of the same class as source.
11054 const TargetRegisterClass *RC = MRI->getRegClass(Reg: SrcReg);
11055 Register DstReg = MRI->createVirtualRegister(RegClass: RC);
11056
11057 // Replace pseudo with a normal load-and-test that models the def as
11058 // well.
11059 BuildMI(BB&: *MBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode), DestReg: DstReg)
11060 .addReg(RegNo: SrcReg)
11061 .setMIFlags(MI.getFlags());
11062 MI.eraseFromParent();
11063
11064 return MBB;
11065}
11066
11067MachineBasicBlock *SystemZTargetLowering::emitProbedAlloca(
11068 MachineInstr &MI, MachineBasicBlock *MBB) const {
11069 MachineFunction &MF = *MBB->getParent();
11070 MachineRegisterInfo *MRI = &MF.getRegInfo();
11071 const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
11072 DebugLoc DL = MI.getDebugLoc();
11073 const unsigned ProbeSize = getStackProbeSize(MF);
11074 Register DstReg = MI.getOperand(i: 0).getReg();
11075 Register SizeReg = MI.getOperand(i: 2).getReg();
11076
11077 MachineBasicBlock *StartMBB = MBB;
11078 MachineBasicBlock *DoneMBB = SystemZ::splitBlockAfter(MI, MBB);
11079 MachineBasicBlock *LoopTestMBB = SystemZ::emitBlockAfter(MBB: StartMBB);
11080 MachineBasicBlock *LoopBodyMBB = SystemZ::emitBlockAfter(MBB: LoopTestMBB);
11081 MachineBasicBlock *TailTestMBB = SystemZ::emitBlockAfter(MBB: LoopBodyMBB);
11082 MachineBasicBlock *TailMBB = SystemZ::emitBlockAfter(MBB: TailTestMBB);
11083
11084 MachineMemOperand *VolLdMMO = MF.getMachineMemOperand(PtrInfo: MachinePointerInfo(),
11085 F: MachineMemOperand::MOVolatile | MachineMemOperand::MOLoad, Size: 8, BaseAlignment: Align(1));
11086
11087 Register PHIReg = MRI->createVirtualRegister(RegClass: &SystemZ::ADDR64BitRegClass);
11088 Register IncReg = MRI->createVirtualRegister(RegClass: &SystemZ::ADDR64BitRegClass);
11089
11090 // LoopTestMBB
11091 // BRC TailTestMBB
11092 // # fallthrough to LoopBodyMBB
11093 StartMBB->addSuccessor(Succ: LoopTestMBB);
11094 MBB = LoopTestMBB;
11095 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::PHI), DestReg: PHIReg)
11096 .addReg(RegNo: SizeReg)
11097 .addMBB(MBB: StartMBB)
11098 .addReg(RegNo: IncReg)
11099 .addMBB(MBB: LoopBodyMBB);
11100 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::CLGFI))
11101 .addReg(RegNo: PHIReg)
11102 .addImm(Val: ProbeSize);
11103 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::BRC))
11104 .addImm(Val: SystemZ::CCMASK_ICMP).addImm(Val: SystemZ::CCMASK_CMP_LT)
11105 .addMBB(MBB: TailTestMBB);
11106 MBB->addSuccessor(Succ: LoopBodyMBB);
11107 MBB->addSuccessor(Succ: TailTestMBB);
11108
11109 // LoopBodyMBB: Allocate and probe by means of a volatile compare.
11110 // J LoopTestMBB
11111 MBB = LoopBodyMBB;
11112 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::SLGFI), DestReg: IncReg)
11113 .addReg(RegNo: PHIReg)
11114 .addImm(Val: ProbeSize);
11115 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::SLGFI), DestReg: SystemZ::R15D)
11116 .addReg(RegNo: SystemZ::R15D)
11117 .addImm(Val: ProbeSize);
11118 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::CG)).addReg(RegNo: SystemZ::R15D)
11119 .addReg(RegNo: SystemZ::R15D).addImm(Val: ProbeSize - 8).addReg(RegNo: 0)
11120 .setMemRefs(VolLdMMO);
11121 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::J)).addMBB(MBB: LoopTestMBB);
11122 MBB->addSuccessor(Succ: LoopTestMBB);
11123
11124 // TailTestMBB
11125 // BRC DoneMBB
11126 // # fallthrough to TailMBB
11127 MBB = TailTestMBB;
11128 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::CGHI))
11129 .addReg(RegNo: PHIReg)
11130 .addImm(Val: 0);
11131 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::BRC))
11132 .addImm(Val: SystemZ::CCMASK_ICMP).addImm(Val: SystemZ::CCMASK_CMP_EQ)
11133 .addMBB(MBB: DoneMBB);
11134 MBB->addSuccessor(Succ: TailMBB);
11135 MBB->addSuccessor(Succ: DoneMBB);
11136
11137 // TailMBB
11138 // # fallthrough to DoneMBB
11139 MBB = TailMBB;
11140 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::SLGR), DestReg: SystemZ::R15D)
11141 .addReg(RegNo: SystemZ::R15D)
11142 .addReg(RegNo: PHIReg);
11143 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: SystemZ::CG)).addReg(RegNo: SystemZ::R15D)
11144 .addReg(RegNo: SystemZ::R15D).addImm(Val: -8).addReg(RegNo: PHIReg)
11145 .setMemRefs(VolLdMMO);
11146 MBB->addSuccessor(Succ: DoneMBB);
11147
11148 // DoneMBB
11149 MBB = DoneMBB;
11150 BuildMI(BB&: *MBB, I: MBB->begin(), MIMD: DL, MCID: TII->get(Opcode: TargetOpcode::COPY), DestReg: DstReg)
11151 .addReg(RegNo: SystemZ::R15D);
11152
11153 MI.eraseFromParent();
11154 return DoneMBB;
11155}
11156
11157SDValue SystemZTargetLowering::
11158getBackchainAddress(SDValue SP, SelectionDAG &DAG) const {
11159 MachineFunction &MF = DAG.getMachineFunction();
11160 auto *TFL = Subtarget.getFrameLowering<SystemZELFFrameLowering>();
11161 SDLoc DL(SP);
11162 return DAG.getNode(Opcode: ISD::ADD, DL, VT: MVT::i64, N1: SP,
11163 N2: DAG.getIntPtrConstant(Val: TFL->getBackchainOffset(MF), DL));
11164}
11165
11166// Replace a _STACKGUARD_DAG pseudo with a _STACKGUARD pseudo, adding
11167// a dead early-clobber def reg that will be used as a scratch register
11168// when the pseudo is expanded.
11169MachineBasicBlock *SystemZTargetLowering::emitStackGuardPseudo(
11170 MachineInstr &MI, MachineBasicBlock *MBB, unsigned PseudoOp) const {
11171 MachineRegisterInfo *MRI = &MBB->getParent()->getRegInfo();
11172 const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
11173 DebugLoc DL = MI.getDebugLoc();
11174 Register AddrReg = MRI->createVirtualRegister(RegClass: &SystemZ::ADDR64BitRegClass);
11175 BuildMI(BB&: *MBB, I&: MI, MIMD: DL, MCID: TII->get(Opcode: PseudoOp), DestReg: AddrReg)
11176 .addFrameIndex(Idx: MI.getOperand(i: 0).getIndex())
11177 .addImm(Val: MI.getOperand(i: 1).getImm());
11178 MI.eraseFromParent();
11179 return MBB;
11180}
11181
11182MachineBasicBlock *SystemZTargetLowering::EmitInstrWithCustomInserter(
11183 MachineInstr &MI, MachineBasicBlock *MBB) const {
11184 switch (MI.getOpcode()) {
11185 case SystemZ::ADJCALLSTACKDOWN:
11186 case SystemZ::ADJCALLSTACKUP:
11187 return emitAdjCallStack(MI, BB: MBB);
11188
11189 case SystemZ::Select32:
11190 case SystemZ::Select64:
11191 case SystemZ::Select128:
11192 case SystemZ::SelectF32:
11193 case SystemZ::SelectF64:
11194 case SystemZ::SelectF128:
11195 case SystemZ::SelectVR32:
11196 case SystemZ::SelectVR64:
11197 case SystemZ::SelectVR128:
11198 return emitSelect(MI, MBB);
11199
11200 case SystemZ::CondStore8Mux:
11201 return emitCondStore(MI, MBB, StoreOpcode: SystemZ::STCMux, STOCOpcode: 0, Invert: false);
11202 case SystemZ::CondStore8MuxInv:
11203 return emitCondStore(MI, MBB, StoreOpcode: SystemZ::STCMux, STOCOpcode: 0, Invert: true);
11204 case SystemZ::CondStore16Mux:
11205 return emitCondStore(MI, MBB, StoreOpcode: SystemZ::STHMux, STOCOpcode: 0, Invert: false);
11206 case SystemZ::CondStore16MuxInv:
11207 return emitCondStore(MI, MBB, StoreOpcode: SystemZ::STHMux, STOCOpcode: 0, Invert: true);
11208 case SystemZ::CondStore32Mux:
11209 return emitCondStore(MI, MBB, StoreOpcode: SystemZ::STMux, STOCOpcode: SystemZ::STOCMux, Invert: false);
11210 case SystemZ::CondStore32MuxInv:
11211 return emitCondStore(MI, MBB, StoreOpcode: SystemZ::STMux, STOCOpcode: SystemZ::STOCMux, Invert: true);
11212 case SystemZ::CondStore8:
11213 return emitCondStore(MI, MBB, StoreOpcode: SystemZ::STC, STOCOpcode: 0, Invert: false);
11214 case SystemZ::CondStore8Inv:
11215 return emitCondStore(MI, MBB, StoreOpcode: SystemZ::STC, STOCOpcode: 0, Invert: true);
11216 case SystemZ::CondStore16:
11217 return emitCondStore(MI, MBB, StoreOpcode: SystemZ::STH, STOCOpcode: 0, Invert: false);
11218 case SystemZ::CondStore16Inv:
11219 return emitCondStore(MI, MBB, StoreOpcode: SystemZ::STH, STOCOpcode: 0, Invert: true);
11220 case SystemZ::CondStore32:
11221 return emitCondStore(MI, MBB, StoreOpcode: SystemZ::ST, STOCOpcode: SystemZ::STOC, Invert: false);
11222 case SystemZ::CondStore32Inv:
11223 return emitCondStore(MI, MBB, StoreOpcode: SystemZ::ST, STOCOpcode: SystemZ::STOC, Invert: true);
11224 case SystemZ::CondStore64:
11225 return emitCondStore(MI, MBB, StoreOpcode: SystemZ::STG, STOCOpcode: SystemZ::STOCG, Invert: false);
11226 case SystemZ::CondStore64Inv:
11227 return emitCondStore(MI, MBB, StoreOpcode: SystemZ::STG, STOCOpcode: SystemZ::STOCG, Invert: true);
11228 case SystemZ::CondStoreF32:
11229 return emitCondStore(MI, MBB, StoreOpcode: SystemZ::STE, STOCOpcode: 0, Invert: false);
11230 case SystemZ::CondStoreF32Inv:
11231 return emitCondStore(MI, MBB, StoreOpcode: SystemZ::STE, STOCOpcode: 0, Invert: true);
11232 case SystemZ::CondStoreF64:
11233 return emitCondStore(MI, MBB, StoreOpcode: SystemZ::STD, STOCOpcode: 0, Invert: false);
11234 case SystemZ::CondStoreF64Inv:
11235 return emitCondStore(MI, MBB, StoreOpcode: SystemZ::STD, STOCOpcode: 0, Invert: true);
11236
11237 case SystemZ::SCmp128Hi:
11238 return emitICmp128Hi(MI, MBB, Unsigned: false);
11239 case SystemZ::UCmp128Hi:
11240 return emitICmp128Hi(MI, MBB, Unsigned: true);
11241
11242 case SystemZ::PAIR128:
11243 return emitPair128(MI, MBB);
11244 case SystemZ::AEXT128:
11245 return emitExt128(MI, MBB, ClearEven: false);
11246 case SystemZ::ZEXT128:
11247 return emitExt128(MI, MBB, ClearEven: true);
11248
11249 case SystemZ::ATOMIC_SWAPW:
11250 return emitAtomicLoadBinary(MI, MBB, BinOpcode: 0);
11251
11252 case SystemZ::ATOMIC_LOADW_AR:
11253 return emitAtomicLoadBinary(MI, MBB, BinOpcode: SystemZ::AR);
11254 case SystemZ::ATOMIC_LOADW_AFI:
11255 return emitAtomicLoadBinary(MI, MBB, BinOpcode: SystemZ::AFI);
11256
11257 case SystemZ::ATOMIC_LOADW_SR:
11258 return emitAtomicLoadBinary(MI, MBB, BinOpcode: SystemZ::SR);
11259
11260 case SystemZ::ATOMIC_LOADW_NR:
11261 return emitAtomicLoadBinary(MI, MBB, BinOpcode: SystemZ::NR);
11262 case SystemZ::ATOMIC_LOADW_NILH:
11263 return emitAtomicLoadBinary(MI, MBB, BinOpcode: SystemZ::NILH);
11264
11265 case SystemZ::ATOMIC_LOADW_OR:
11266 return emitAtomicLoadBinary(MI, MBB, BinOpcode: SystemZ::OR);
11267 case SystemZ::ATOMIC_LOADW_OILH:
11268 return emitAtomicLoadBinary(MI, MBB, BinOpcode: SystemZ::OILH);
11269
11270 case SystemZ::ATOMIC_LOADW_XR:
11271 return emitAtomicLoadBinary(MI, MBB, BinOpcode: SystemZ::XR);
11272 case SystemZ::ATOMIC_LOADW_XILF:
11273 return emitAtomicLoadBinary(MI, MBB, BinOpcode: SystemZ::XILF);
11274
11275 case SystemZ::ATOMIC_LOADW_NRi:
11276 return emitAtomicLoadBinary(MI, MBB, BinOpcode: SystemZ::NR, Invert: true);
11277 case SystemZ::ATOMIC_LOADW_NILHi:
11278 return emitAtomicLoadBinary(MI, MBB, BinOpcode: SystemZ::NILH, Invert: true);
11279
11280 case SystemZ::ATOMIC_LOADW_MIN:
11281 return emitAtomicLoadMinMax(MI, MBB, CompareOpcode: SystemZ::CR, KeepOldMask: SystemZ::CCMASK_CMP_LE);
11282 case SystemZ::ATOMIC_LOADW_MAX:
11283 return emitAtomicLoadMinMax(MI, MBB, CompareOpcode: SystemZ::CR, KeepOldMask: SystemZ::CCMASK_CMP_GE);
11284 case SystemZ::ATOMIC_LOADW_UMIN:
11285 return emitAtomicLoadMinMax(MI, MBB, CompareOpcode: SystemZ::CLR, KeepOldMask: SystemZ::CCMASK_CMP_LE);
11286 case SystemZ::ATOMIC_LOADW_UMAX:
11287 return emitAtomicLoadMinMax(MI, MBB, CompareOpcode: SystemZ::CLR, KeepOldMask: SystemZ::CCMASK_CMP_GE);
11288
11289 case SystemZ::ATOMIC_CMP_SWAPW:
11290 return emitAtomicCmpSwapW(MI, MBB);
11291 case SystemZ::MVCImm:
11292 case SystemZ::MVCReg:
11293 return emitMemMemWrapper(MI, MBB, Opcode: SystemZ::MVC);
11294 case SystemZ::NCImm:
11295 return emitMemMemWrapper(MI, MBB, Opcode: SystemZ::NC);
11296 case SystemZ::OCImm:
11297 return emitMemMemWrapper(MI, MBB, Opcode: SystemZ::OC);
11298 case SystemZ::XCImm:
11299 case SystemZ::XCReg:
11300 return emitMemMemWrapper(MI, MBB, Opcode: SystemZ::XC);
11301 case SystemZ::CLCImm:
11302 case SystemZ::CLCReg:
11303 return emitMemMemWrapper(MI, MBB, Opcode: SystemZ::CLC);
11304 case SystemZ::MemsetImmImm:
11305 case SystemZ::MemsetImmReg:
11306 case SystemZ::MemsetRegImm:
11307 case SystemZ::MemsetRegReg:
11308 return emitMemMemWrapper(MI, MBB, Opcode: SystemZ::MVC, IsMemset: true/*IsMemset*/);
11309 case SystemZ::MemmoveImm:
11310 return emitMemmoveImm(MI, MBB);
11311 case SystemZ::CLSTLoop:
11312 return emitStringWrapper(MI, MBB, Opcode: SystemZ::CLST);
11313 case SystemZ::MVSTLoop:
11314 return emitStringWrapper(MI, MBB, Opcode: SystemZ::MVST);
11315 case SystemZ::SRSTLoop:
11316 return emitStringWrapper(MI, MBB, Opcode: SystemZ::SRST);
11317 case SystemZ::TBEGIN:
11318 return emitTransactionBegin(MI, MBB, Opcode: SystemZ::TBEGIN, NoFloat: false);
11319 case SystemZ::TBEGIN_nofloat:
11320 return emitTransactionBegin(MI, MBB, Opcode: SystemZ::TBEGIN, NoFloat: true);
11321 case SystemZ::TBEGINC:
11322 return emitTransactionBegin(MI, MBB, Opcode: SystemZ::TBEGINC, NoFloat: true);
11323 case SystemZ::LTEBRCompare_Pseudo:
11324 return emitLoadAndTestCmp0(MI, MBB, Opcode: SystemZ::LTEBR);
11325 case SystemZ::LTDBRCompare_Pseudo:
11326 return emitLoadAndTestCmp0(MI, MBB, Opcode: SystemZ::LTDBR);
11327 case SystemZ::LTXBRCompare_Pseudo:
11328 return emitLoadAndTestCmp0(MI, MBB, Opcode: SystemZ::LTXBR);
11329
11330 case SystemZ::PROBED_ALLOCA:
11331 return emitProbedAlloca(MI, MBB);
11332 case SystemZ::EH_SjLj_SetJmp:
11333 return emitEHSjLjSetJmp(MI, MBB);
11334 case SystemZ::EH_SjLj_LongJmp:
11335 return emitEHSjLjLongJmp(MI, MBB);
11336
11337 case TargetOpcode::STACKMAP:
11338 case TargetOpcode::PATCHPOINT:
11339 return emitPatchPoint(MI, MBB);
11340
11341 case SystemZ::MOV_STACKGUARD_DAG:
11342 return emitStackGuardPseudo(MI, MBB, PseudoOp: SystemZ::MOV_STACKGUARD);
11343
11344 case SystemZ::CMP_STACKGUARD_DAG:
11345 return emitStackGuardPseudo(MI, MBB, PseudoOp: SystemZ::CMP_STACKGUARD);
11346
11347 default:
11348 llvm_unreachable("Unexpected instr type to insert");
11349 }
11350}
11351
11352// This is only used by the isel schedulers, and is needed only to prevent
11353// compiler from crashing when list-ilp is used.
11354const TargetRegisterClass *
11355SystemZTargetLowering::getRepRegClassFor(MVT VT) const {
11356 if (VT == MVT::Untyped)
11357 return &SystemZ::ADDR128BitRegClass;
11358 return TargetLowering::getRepRegClassFor(VT);
11359}
11360
11361SDValue SystemZTargetLowering::lowerGET_ROUNDING(SDValue Op,
11362 SelectionDAG &DAG) const {
11363 SDLoc dl(Op);
11364 /*
11365 The rounding method is in FPC Byte 3 bits 6-7, and has the following
11366 settings:
11367 00 Round to nearest
11368 01 Round to 0
11369 10 Round to +inf
11370 11 Round to -inf
11371
11372 FLT_ROUNDS, on the other hand, expects the following:
11373 -1 Undefined
11374 0 Round to 0
11375 1 Round to nearest
11376 2 Round to +inf
11377 3 Round to -inf
11378 */
11379
11380 // Save FPC to register.
11381 SDValue Chain = Op.getOperand(i: 0);
11382 SDValue EFPC(
11383 DAG.getMachineNode(Opcode: SystemZ::EFPC, dl, ResultTys: {MVT::i32, MVT::Other}, Ops: Chain), 0);
11384 Chain = EFPC.getValue(R: 1);
11385
11386 // Transform as necessary
11387 SDValue CWD1 = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: MVT::i32, N1: EFPC,
11388 N2: DAG.getConstant(Val: 3, DL: dl, VT: MVT::i32));
11389 // RetVal = (CWD1 ^ (CWD1 >> 1)) ^ 1
11390 SDValue CWD2 = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: MVT::i32, N1: CWD1,
11391 N2: DAG.getNode(Opcode: ISD::SRL, DL: dl, VT: MVT::i32, N1: CWD1,
11392 N2: DAG.getConstant(Val: 1, DL: dl, VT: MVT::i32)));
11393
11394 SDValue RetVal = DAG.getNode(Opcode: ISD::XOR, DL: dl, VT: MVT::i32, N1: CWD2,
11395 N2: DAG.getConstant(Val: 1, DL: dl, VT: MVT::i32));
11396 RetVal = DAG.getZExtOrTrunc(Op: RetVal, DL: dl, VT: Op.getValueType());
11397
11398 return DAG.getMergeValues(Ops: {RetVal, Chain}, dl);
11399}
11400
11401SDValue SystemZTargetLowering::lowerVECREDUCE_ADD(SDValue Op,
11402 SelectionDAG &DAG) const {
11403 EVT VT = Op.getValueType();
11404 Op = Op.getOperand(i: 0);
11405 EVT OpVT = Op.getValueType();
11406
11407 assert(OpVT.isVector() && "Operand type for VECREDUCE_ADD is not a vector.");
11408
11409 SDLoc DL(Op);
11410
11411 // load a 0 vector for the third operand of VSUM.
11412 SDValue Zero = DAG.getSplatBuildVector(VT: OpVT, DL, Op: DAG.getConstant(Val: 0, DL, VT));
11413
11414 // execute VSUM.
11415 switch (OpVT.getScalarSizeInBits()) {
11416 case 8:
11417 case 16:
11418 Op = DAG.getNode(Opcode: SystemZISD::VSUM, DL, VT: MVT::v4i32, N1: Op, N2: Zero);
11419 [[fallthrough]];
11420 case 32:
11421 case 64:
11422 Op = DAG.getNode(Opcode: SystemZISD::VSUM, DL, VT: MVT::i128, N1: Op,
11423 N2: DAG.getBitcast(VT: Op.getValueType(), V: Zero));
11424 break;
11425 case 128:
11426 break; // VSUM over v1i128 should not happen and would be a noop
11427 default:
11428 llvm_unreachable("Unexpected scalar size.");
11429 }
11430 // Cast to original vector type, retrieve last element.
11431 return DAG.getNode(
11432 Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT, N1: DAG.getBitcast(VT: OpVT, V: Op),
11433 N2: DAG.getConstant(Val: OpVT.getVectorNumElements() - 1, DL, VT: MVT::i32));
11434}
11435
11436static void printFunctionArgExts(const Function *F, raw_fd_ostream &OS) {
11437 FunctionType *FT = F->getFunctionType();
11438 const AttributeList &Attrs = F->getAttributes();
11439 if (Attrs.hasRetAttrs())
11440 OS << Attrs.getAsString(Index: AttributeList::ReturnIndex) << " ";
11441 OS << *F->getReturnType() << " @" << F->getName() << "(";
11442 for (unsigned I = 0, E = FT->getNumParams(); I != E; ++I) {
11443 if (I)
11444 OS << ", ";
11445 OS << *FT->getParamType(i: I);
11446 AttributeSet ArgAttrs = Attrs.getParamAttrs(ArgNo: I);
11447 for (auto A : {Attribute::SExt, Attribute::ZExt, Attribute::NoExt})
11448 if (ArgAttrs.hasAttribute(Kind: A))
11449 OS << " " << Attribute::getNameFromAttrKind(AttrKind: A);
11450 }
11451 OS << ")\n";
11452}
11453
11454bool SystemZTargetLowering::isInternal(const Function *Fn) const {
11455 std::map<const Function *, bool>::iterator Itr = IsInternalCache.find(x: Fn);
11456 if (Itr == IsInternalCache.end())
11457 Itr = IsInternalCache
11458 .insert(x: std::pair<const Function *, bool>(
11459 Fn, (Fn->hasLocalLinkage() && !Fn->hasAddressTaken())))
11460 .first;
11461 return Itr->second;
11462}
11463
11464void SystemZTargetLowering::
11465verifyNarrowIntegerArgs_Call(const SmallVectorImpl<ISD::OutputArg> &Outs,
11466 const Function *F, SDValue Callee) const {
11467 // Temporarily only do the check when explicitly requested, until it can be
11468 // enabled by default.
11469 if (!EnableIntArgExtCheck)
11470 return;
11471
11472 bool IsInternal = false;
11473 const Function *CalleeFn = nullptr;
11474 if (auto *G = dyn_cast<GlobalAddressSDNode>(Val&: Callee))
11475 if ((CalleeFn = dyn_cast<Function>(Val: G->getGlobal())))
11476 IsInternal = isInternal(Fn: CalleeFn);
11477 if (!IsInternal && !verifyNarrowIntegerArgs(Outs)) {
11478 errs() << "ERROR: Missing extension attribute of passed "
11479 << "value in call to function:\n" << "Callee: ";
11480 if (CalleeFn != nullptr)
11481 printFunctionArgExts(F: CalleeFn, OS&: errs());
11482 else
11483 errs() << "-\n";
11484 errs() << "Caller: ";
11485 printFunctionArgExts(F, OS&: errs());
11486 llvm_unreachable("");
11487 }
11488}
11489
11490void SystemZTargetLowering::
11491verifyNarrowIntegerArgs_Ret(const SmallVectorImpl<ISD::OutputArg> &Outs,
11492 const Function *F) const {
11493 // Temporarily only do the check when explicitly requested, until it can be
11494 // enabled by default.
11495 if (!EnableIntArgExtCheck)
11496 return;
11497
11498 if (!isInternal(Fn: F) && !verifyNarrowIntegerArgs(Outs)) {
11499 errs() << "ERROR: Missing extension attribute of returned "
11500 << "value from function:\n";
11501 printFunctionArgExts(F, OS&: errs());
11502 llvm_unreachable("");
11503 }
11504}
11505
11506// Verify that narrow integer arguments are extended as required by the ABI.
11507// Return false if an error is found.
11508bool SystemZTargetLowering::verifyNarrowIntegerArgs(
11509 const SmallVectorImpl<ISD::OutputArg> &Outs) const {
11510 if (!Subtarget.isTargetELF())
11511 return true;
11512
11513 if (EnableIntArgExtCheck.getNumOccurrences()) {
11514 if (!EnableIntArgExtCheck)
11515 return true;
11516 } else if (!getTargetMachine().Options.VerifyArgABICompliance)
11517 return true;
11518
11519 for (unsigned i = 0; i < Outs.size(); ++i) {
11520 MVT VT = Outs[i].VT;
11521 ISD::ArgFlagsTy Flags = Outs[i].Flags;
11522 if (VT.isInteger()) {
11523 assert((VT == MVT::i32 || VT.getSizeInBits() >= 64) &&
11524 "Unexpected integer argument VT.");
11525 if (VT == MVT::i32 &&
11526 !Flags.isSExt() && !Flags.isZExt() && !Flags.isNoExt())
11527 return false;
11528 }
11529 }
11530
11531 return true;
11532}
11533
11534void SystemZTargetLowering::insertSSPDeclarations(
11535 Module &M, const LibcallLoweringInfo &Libcalls) const {
11536 StringRef GuardMode = M.getStackProtectorGuard();
11537
11538 // In the TLS case, no symbol needs to be inserted.
11539 if (GuardMode == "tls" || GuardMode.empty())
11540 return;
11541
11542 // Otherwise (in the global case), insert the appropriate global variable.
11543 TargetLowering::insertSSPDeclarations(M, Libcalls);
11544}
11545