1//===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the SystemZ implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "SystemZInstrInfo.h"
14#include "MCTargetDesc/SystemZMCTargetDesc.h"
15#include "SystemZ.h"
16#include "SystemZInstrBuilder.h"
17#include "SystemZSubtarget.h"
18#include "llvm/ADT/Statistic.h"
19#include "llvm/CodeGen/LiveInterval.h"
20#include "llvm/CodeGen/LiveIntervals.h"
21#include "llvm/CodeGen/LiveRegUnits.h"
22#include "llvm/CodeGen/LiveVariables.h"
23#include "llvm/CodeGen/MachineBasicBlock.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineInstr.h"
27#include "llvm/CodeGen/MachineMemOperand.h"
28#include "llvm/CodeGen/MachineOperand.h"
29#include "llvm/CodeGen/MachineRegisterInfo.h"
30#include "llvm/CodeGen/SlotIndexes.h"
31#include "llvm/CodeGen/StackMaps.h"
32#include "llvm/CodeGen/TargetInstrInfo.h"
33#include "llvm/CodeGen/TargetOpcodes.h"
34#include "llvm/CodeGen/TargetSubtargetInfo.h"
35#include "llvm/CodeGen/VirtRegMap.h"
36#include "llvm/IR/Module.h"
37#include "llvm/MC/MCInstBuilder.h"
38#include "llvm/MC/MCInstrDesc.h"
39#include "llvm/MC/MCRegisterInfo.h"
40#include "llvm/Support/BranchProbability.h"
41#include "llvm/Support/ErrorHandling.h"
42#include "llvm/Support/MathExtras.h"
43#include "llvm/Target/TargetMachine.h"
44#include <cassert>
45#include <cstdint>
46#include <iterator>
47
48using namespace llvm;
49
50#define GET_INSTRINFO_CTOR_DTOR
51#define GET_INSTRMAP_INFO
52#include "SystemZGenInstrInfo.inc"
53
54#define DEBUG_TYPE "systemz-II"
55
56// Return a mask with Count low bits set.
57static uint64_t allOnes(unsigned int Count) {
58 return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
59}
60
61// Pin the vtable to this file.
62void SystemZInstrInfo::anchor() {}
63
64SystemZInstrInfo::SystemZInstrInfo(const SystemZSubtarget &sti)
65 : SystemZGenInstrInfo(sti, RI, -1, -1),
66 RI(sti.getSpecialRegisters()->getReturnFunctionAddressRegister(),
67 sti.getHwMode()),
68 STI(sti) {}
69
70// MI is a 128-bit load or store. Split it into two 64-bit loads or stores,
71// each having the opcode given by NewOpcode.
72void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
73 unsigned NewOpcode) const {
74 MachineBasicBlock *MBB = MI->getParent();
75 MachineFunction &MF = *MBB->getParent();
76
77 // Get two load or store instructions. Use the original instruction for
78 // one of them and create a clone for the other.
79 MachineInstr *HighPartMI = MF.CloneMachineInstr(Orig: &*MI);
80 MachineInstr *LowPartMI = &*MI;
81 MBB->insert(I: LowPartMI, MI: HighPartMI);
82
83 // Set up the two 64-bit registers and remember super reg and its flags.
84 MachineOperand &HighRegOp = HighPartMI->getOperand(i: 0);
85 MachineOperand &LowRegOp = LowPartMI->getOperand(i: 0);
86 Register Reg128 = LowRegOp.getReg();
87 RegState Reg128Killed = getKillRegState(B: LowRegOp.isKill());
88 RegState Reg128Undef = getUndefRegState(B: LowRegOp.isUndef());
89 HighRegOp.setReg(RI.getSubReg(Reg: HighRegOp.getReg(), Idx: SystemZ::subreg_h64));
90 LowRegOp.setReg(RI.getSubReg(Reg: LowRegOp.getReg(), Idx: SystemZ::subreg_l64));
91
92 // The address in the first (high) instruction is already correct.
93 // Adjust the offset in the second (low) instruction.
94 MachineOperand &HighOffsetOp = HighPartMI->getOperand(i: 2);
95 MachineOperand &LowOffsetOp = LowPartMI->getOperand(i: 2);
96 LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
97
98 // Set the opcodes.
99 unsigned HighOpcode = getOpcodeForOffset(Opcode: NewOpcode, Offset: HighOffsetOp.getImm());
100 unsigned LowOpcode = getOpcodeForOffset(Opcode: NewOpcode, Offset: LowOffsetOp.getImm());
101 assert(HighOpcode && LowOpcode && "Both offsets should be in range");
102 HighPartMI->setDesc(get(Opcode: HighOpcode));
103 LowPartMI->setDesc(get(Opcode: LowOpcode));
104
105 MachineInstr *FirstMI = HighPartMI;
106 if (MI->mayStore()) {
107 FirstMI->getOperand(i: 0).setIsKill(false);
108 // Add implicit uses of the super register in case one of the subregs is
109 // undefined. We could track liveness and skip storing an undefined
110 // subreg, but this is hopefully rare (discovered with llvm-stress).
111 // If Reg128 was killed, set kill flag on MI.
112 RegState Reg128UndefImpl = (Reg128Undef | RegState::Implicit);
113 MachineInstrBuilder(MF, HighPartMI).addReg(RegNo: Reg128, Flags: Reg128UndefImpl);
114 MachineInstrBuilder(MF, LowPartMI).addReg(RegNo: Reg128, Flags: (Reg128UndefImpl | Reg128Killed));
115 } else {
116 // If HighPartMI clobbers any of the address registers, it needs to come
117 // after LowPartMI.
118 auto overlapsAddressReg = [&](Register Reg) -> bool {
119 return RI.regsOverlap(RegA: Reg, RegB: MI->getOperand(i: 1).getReg()) ||
120 RI.regsOverlap(RegA: Reg, RegB: MI->getOperand(i: 3).getReg());
121 };
122 if (overlapsAddressReg(HighRegOp.getReg())) {
123 assert(!overlapsAddressReg(LowRegOp.getReg()) &&
124 "Both loads clobber address!");
125 MBB->splice(Where: HighPartMI, Other: MBB, From: LowPartMI);
126 FirstMI = LowPartMI;
127 }
128 }
129
130 // Clear the kill flags on the address registers in the first instruction.
131 FirstMI->getOperand(i: 1).setIsKill(false);
132 FirstMI->getOperand(i: 3).setIsKill(false);
133}
134
135// Split ADJDYNALLOC instruction MI.
136void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const {
137 MachineBasicBlock *MBB = MI->getParent();
138 MachineFunction &MF = *MBB->getParent();
139 MachineFrameInfo &MFFrame = MF.getFrameInfo();
140 MachineOperand &OffsetMO = MI->getOperand(i: 2);
141 SystemZCallingConventionRegisters *Regs = STI.getSpecialRegisters();
142
143 uint64_t Offset = (MFFrame.getMaxCallFrameSize() +
144 Regs->getCallFrameSize() +
145 Regs->getStackPointerBias() +
146 OffsetMO.getImm());
147 unsigned NewOpcode = getOpcodeForOffset(Opcode: SystemZ::LA, Offset);
148 assert(NewOpcode && "No support for huge argument lists yet");
149 MI->setDesc(get(Opcode: NewOpcode));
150 OffsetMO.setImm(Offset);
151}
152
153// MI is an RI-style pseudo instruction. Replace it with LowOpcode
154// if the first operand is a low GR32 and HighOpcode if the first operand
155// is a high GR32. ConvertHigh is true if LowOpcode takes a signed operand
156// and HighOpcode takes an unsigned 32-bit operand. In those cases,
157// MI has the same kind of operand as LowOpcode, so needs to be converted
158// if HighOpcode is used.
159void SystemZInstrInfo::expandRIPseudo(MachineInstr &MI, unsigned LowOpcode,
160 unsigned HighOpcode,
161 bool ConvertHigh) const {
162 Register Reg = MI.getOperand(i: 0).getReg();
163 bool IsHigh = SystemZ::isHighReg(Reg);
164 MI.setDesc(get(Opcode: IsHigh ? HighOpcode : LowOpcode));
165 if (IsHigh && ConvertHigh)
166 MI.getOperand(i: 1).setImm(uint32_t(MI.getOperand(i: 1).getImm()));
167}
168
169// MI is a three-operand RIE-style pseudo instruction. Replace it with
170// LowOpcodeK if the registers are both low GR32s, otherwise use a move
171// followed by HighOpcode or LowOpcode, depending on whether the target
172// is a high or low GR32.
173void SystemZInstrInfo::expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
174 unsigned LowOpcodeK,
175 unsigned HighOpcode) const {
176 Register DestReg = MI.getOperand(i: 0).getReg();
177 Register SrcReg = MI.getOperand(i: 1).getReg();
178 bool DestIsHigh = SystemZ::isHighReg(Reg: DestReg);
179 bool SrcIsHigh = SystemZ::isHighReg(Reg: SrcReg);
180 if (!DestIsHigh && !SrcIsHigh)
181 MI.setDesc(get(Opcode: LowOpcodeK));
182 else {
183 if (DestReg != SrcReg) {
184 emitGRX32Move(MBB&: *MI.getParent(), MBBI: MI, DL: MI.getDebugLoc(), DestReg, SrcReg,
185 LowLowOpcode: SystemZ::LR, Size: 32, KillSrc: MI.getOperand(i: 1).isKill(),
186 UndefSrc: MI.getOperand(i: 1).isUndef());
187 MI.getOperand(i: 1).setReg(DestReg);
188 }
189 MI.setDesc(get(Opcode: DestIsHigh ? HighOpcode : LowOpcode));
190 MI.tieOperands(DefIdx: 0, UseIdx: 1);
191 }
192}
193
194// MI is an RXY-style pseudo instruction. Replace it with LowOpcode
195// if the first operand is a low GR32 and HighOpcode if the first operand
196// is a high GR32.
197void SystemZInstrInfo::expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
198 unsigned HighOpcode) const {
199 Register Reg = MI.getOperand(i: 0).getReg();
200 unsigned Opcode = getOpcodeForOffset(
201 Opcode: SystemZ::isHighReg(Reg) ? HighOpcode : LowOpcode,
202 Offset: MI.getOperand(i: 2).getImm());
203 MI.setDesc(get(Opcode));
204}
205
206// MI is a load-on-condition pseudo instruction with a single register
207// (source or destination) operand. Replace it with LowOpcode if the
208// register is a low GR32 and HighOpcode if the register is a high GR32.
209void SystemZInstrInfo::expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
210 unsigned HighOpcode) const {
211 Register Reg = MI.getOperand(i: 0).getReg();
212 unsigned Opcode = SystemZ::isHighReg(Reg) ? HighOpcode : LowOpcode;
213 MI.setDesc(get(Opcode));
214}
215
216// MI is an RR-style pseudo instruction that zero-extends the low Size bits
217// of one GRX32 into another. Replace it with LowOpcode if both operands
218// are low registers, otherwise use RISB[LH]G.
219void SystemZInstrInfo::expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
220 unsigned Size) const {
221 MachineInstrBuilder MIB =
222 emitGRX32Move(MBB&: *MI.getParent(), MBBI: MI, DL: MI.getDebugLoc(),
223 DestReg: MI.getOperand(i: 0).getReg(), SrcReg: MI.getOperand(i: 1).getReg(), LowLowOpcode: LowOpcode,
224 Size, KillSrc: MI.getOperand(i: 1).isKill(), UndefSrc: MI.getOperand(i: 1).isUndef());
225
226 // Keep the remaining operands as-is.
227 for (const MachineOperand &MO : llvm::drop_begin(RangeOrContainer: MI.operands(), N: 2))
228 MIB.add(MO);
229
230 MI.eraseFromParent();
231}
232
233// Emit a zero-extending move from 32-bit GPR SrcReg to 32-bit GPR
234// DestReg before MBBI in MBB. Use LowLowOpcode when both DestReg and SrcReg
235// are low registers, otherwise use RISB[LH]G. Size is the number of bits
236// taken from the low end of SrcReg (8 for LLCR, 16 for LLHR and 32 for LR).
237// KillSrc is true if this move is the last use of SrcReg.
238MachineInstrBuilder
239SystemZInstrInfo::emitGRX32Move(MachineBasicBlock &MBB,
240 MachineBasicBlock::iterator MBBI,
241 const DebugLoc &DL, unsigned DestReg,
242 unsigned SrcReg, unsigned LowLowOpcode,
243 unsigned Size, bool KillSrc,
244 bool UndefSrc) const {
245 unsigned Opcode;
246 bool DestIsHigh = SystemZ::isHighReg(Reg: DestReg);
247 bool SrcIsHigh = SystemZ::isHighReg(Reg: SrcReg);
248 if (DestIsHigh && SrcIsHigh)
249 Opcode = SystemZ::RISBHH;
250 else if (DestIsHigh && !SrcIsHigh)
251 Opcode = SystemZ::RISBHL;
252 else if (!DestIsHigh && SrcIsHigh)
253 Opcode = SystemZ::RISBLH;
254 else {
255 return BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: LowLowOpcode), DestReg)
256 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrc) | getUndefRegState(B: UndefSrc));
257 }
258 unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);
259 return BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode), DestReg)
260 .addReg(RegNo: DestReg, Flags: RegState::Undef)
261 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrc) | getUndefRegState(B: UndefSrc))
262 .addImm(Val: 32 - Size).addImm(Val: 128 + 31).addImm(Val: Rotate);
263}
264
265MachineInstr *SystemZInstrInfo::commuteInstructionImpl(MachineInstr &MI,
266 bool NewMI,
267 unsigned OpIdx1,
268 unsigned OpIdx2) const {
269 auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
270 if (NewMI)
271 return *MI.getParent()->getParent()->CloneMachineInstr(Orig: &MI);
272 return MI;
273 };
274
275 switch (MI.getOpcode()) {
276 case SystemZ::SELRMux:
277 case SystemZ::SELFHR:
278 case SystemZ::SELR:
279 case SystemZ::SELGR:
280 case SystemZ::LOCRMux:
281 case SystemZ::LOCFHR:
282 case SystemZ::LOCR:
283 case SystemZ::LOCGR: {
284 auto &WorkingMI = cloneIfNew(MI);
285 // Invert condition.
286 unsigned CCValid = WorkingMI.getOperand(i: 3).getImm();
287 unsigned CCMask = WorkingMI.getOperand(i: 4).getImm();
288 WorkingMI.getOperand(i: 4).setImm(CCMask ^ CCValid);
289 return TargetInstrInfo::commuteInstructionImpl(MI&: WorkingMI, /*NewMI=*/false,
290 OpIdx1, OpIdx2);
291 }
292 default:
293 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
294 }
295}
296
297// If MI is a simple load or store for a frame object, return the register
298// it loads or stores and set FrameIndex to the index of the frame object.
299// Return 0 otherwise.
300//
301// Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
302static int isSimpleMove(const MachineInstr &MI, int &FrameIndex,
303 unsigned Flag) {
304 const MCInstrDesc &MCID = MI.getDesc();
305 if ((MCID.TSFlags & Flag) && MI.getOperand(i: 1).isFI() &&
306 MI.getOperand(i: 2).getImm() == 0 && MI.getOperand(i: 3).getReg() == 0) {
307 FrameIndex = MI.getOperand(i: 1).getIndex();
308 return MI.getOperand(i: 0).getReg();
309 }
310 return 0;
311}
312
313Register SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
314 int &FrameIndex) const {
315 return isSimpleMove(MI, FrameIndex, Flag: SystemZII::SimpleBDXLoad);
316}
317
318Register SystemZInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
319 int &FrameIndex) const {
320 return isSimpleMove(MI, FrameIndex, Flag: SystemZII::SimpleBDXStore);
321}
322
323Register SystemZInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
324 int &FrameIndex) const {
325 // if this is not a simple load from memory, it's not a load from stack slot
326 // either.
327 const MCInstrDesc &MCID = MI.getDesc();
328 if (!(MCID.TSFlags & SystemZII::SimpleBDXLoad))
329 return 0;
330
331 // This version of isLoadFromStackSlot should only be used post frame-index
332 // elimination.
333 assert(!MI.getOperand(1).isFI());
334
335 // Now attempt to derive frame index from MachineMemOperands.
336 SmallVector<const MachineMemOperand *, 1> Accesses;
337 if (hasLoadFromStackSlot(MI, Accesses)) {
338 FrameIndex =
339 cast<FixedStackPseudoSourceValue>(Val: Accesses.front()->getPseudoValue())
340 ->getFrameIndex();
341 return MI.getOperand(i: 0).getReg();
342 }
343 return 0;
344}
345
346Register SystemZInstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
347 int &FrameIndex) const {
348 // if this is not a simple store to memory, it's not a store to stack slot
349 // either.
350 const MCInstrDesc &MCID = MI.getDesc();
351 if (!(MCID.TSFlags & SystemZII::SimpleBDXStore))
352 return 0;
353
354 // This version of isStoreToStackSlot should only be used post frame-index
355 // elimination.
356 assert(!MI.getOperand(1).isFI());
357
358 // Now attempt to derive frame index from MachineMemOperands.
359 SmallVector<const MachineMemOperand *, 1> Accesses;
360 if (hasStoreToStackSlot(MI, Accesses)) {
361 FrameIndex =
362 cast<FixedStackPseudoSourceValue>(Val: Accesses.front()->getPseudoValue())
363 ->getFrameIndex();
364 return MI.getOperand(i: 0).getReg();
365 }
366 return 0;
367}
368
369bool SystemZInstrInfo::isStackSlotCopy(const MachineInstr &MI,
370 int &DestFrameIndex,
371 int &SrcFrameIndex) const {
372 // Check for MVC 0(Length,FI1),0(FI2)
373 const MachineFrameInfo &MFI = MI.getParent()->getParent()->getFrameInfo();
374 if (MI.getOpcode() != SystemZ::MVC || !MI.getOperand(i: 0).isFI() ||
375 MI.getOperand(i: 1).getImm() != 0 || !MI.getOperand(i: 3).isFI() ||
376 MI.getOperand(i: 4).getImm() != 0)
377 return false;
378
379 // Check that Length covers the full slots.
380 int64_t Length = MI.getOperand(i: 2).getImm();
381 unsigned FI1 = MI.getOperand(i: 0).getIndex();
382 unsigned FI2 = MI.getOperand(i: 3).getIndex();
383 if (MFI.getObjectSize(ObjectIdx: FI1) != Length ||
384 MFI.getObjectSize(ObjectIdx: FI2) != Length)
385 return false;
386
387 DestFrameIndex = FI1;
388 SrcFrameIndex = FI2;
389 return true;
390}
391
392bool SystemZInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
393 MachineBasicBlock *&TBB,
394 MachineBasicBlock *&FBB,
395 SmallVectorImpl<MachineOperand> &Cond,
396 bool AllowModify) const {
397 // Most of the code and comments here are boilerplate.
398
399 // Start from the bottom of the block and work up, examining the
400 // terminator instructions.
401 MachineBasicBlock::iterator I = MBB.end();
402 while (I != MBB.begin()) {
403 --I;
404 if (I->isDebugInstr())
405 continue;
406
407 // Working from the bottom, when we see a non-terminator instruction, we're
408 // done.
409 if (!isUnpredicatedTerminator(MI: *I))
410 break;
411
412 // A terminator that isn't a branch can't easily be handled by this
413 // analysis.
414 if (!I->isBranch())
415 return true;
416
417 // Can't handle indirect branches.
418 SystemZII::Branch Branch(getBranchInfo(MI: *I));
419 if (!Branch.hasMBBTarget())
420 return true;
421
422 // Punt on compound branches.
423 if (Branch.Type != SystemZII::BranchNormal)
424 return true;
425
426 if (Branch.CCMask == SystemZ::CCMASK_ANY) {
427 // Handle unconditional branches.
428 if (!AllowModify) {
429 TBB = Branch.getMBBTarget();
430 continue;
431 }
432
433 // If the block has any instructions after a JMP, delete them.
434 MBB.erase(I: std::next(x: I), E: MBB.end());
435
436 Cond.clear();
437 FBB = nullptr;
438
439 // Delete the JMP if it's equivalent to a fall-through.
440 if (MBB.isLayoutSuccessor(MBB: Branch.getMBBTarget())) {
441 TBB = nullptr;
442 I->eraseFromParent();
443 I = MBB.end();
444 continue;
445 }
446
447 // TBB is used to indicate the unconditinal destination.
448 TBB = Branch.getMBBTarget();
449 continue;
450 }
451
452 // Working from the bottom, handle the first conditional branch.
453 if (Cond.empty()) {
454 // FIXME: add X86-style branch swap
455 FBB = TBB;
456 TBB = Branch.getMBBTarget();
457 Cond.push_back(Elt: MachineOperand::CreateImm(Val: Branch.CCValid));
458 Cond.push_back(Elt: MachineOperand::CreateImm(Val: Branch.CCMask));
459 continue;
460 }
461
462 // Handle subsequent conditional branches.
463 assert(Cond.size() == 2 && TBB && "Should have seen a conditional branch");
464
465 // Only handle the case where all conditional branches branch to the same
466 // destination.
467 if (TBB != Branch.getMBBTarget())
468 return true;
469
470 // If the conditions are the same, we can leave them alone.
471 unsigned OldCCValid = Cond[0].getImm();
472 unsigned OldCCMask = Cond[1].getImm();
473 if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask)
474 continue;
475
476 // FIXME: Try combining conditions like X86 does. Should be easy on Z!
477 return false;
478 }
479
480 return false;
481}
482
483unsigned SystemZInstrInfo::removeBranch(MachineBasicBlock &MBB,
484 int *BytesRemoved) const {
485 assert(!BytesRemoved && "code size not handled");
486
487 // Most of the code and comments here are boilerplate.
488 MachineBasicBlock::iterator I = MBB.end();
489 unsigned Count = 0;
490
491 while (I != MBB.begin()) {
492 --I;
493 if (I->isDebugInstr())
494 continue;
495 if (!I->isBranch())
496 break;
497 if (!getBranchInfo(MI: *I).hasMBBTarget())
498 break;
499 // Remove the branch.
500 I->eraseFromParent();
501 I = MBB.end();
502 ++Count;
503 }
504
505 return Count;
506}
507
508bool SystemZInstrInfo::
509reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
510 assert(Cond.size() == 2 && "Invalid condition");
511 Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());
512 return false;
513}
514
515unsigned SystemZInstrInfo::insertBranch(MachineBasicBlock &MBB,
516 MachineBasicBlock *TBB,
517 MachineBasicBlock *FBB,
518 ArrayRef<MachineOperand> Cond,
519 const DebugLoc &DL,
520 int *BytesAdded) const {
521 // In this function we output 32-bit branches, which should always
522 // have enough range. They can be shortened and relaxed by later code
523 // in the pipeline, if desired.
524
525 // Shouldn't be a fall through.
526 assert(TBB && "insertBranch must not be told to insert a fallthrough");
527 assert((Cond.size() == 2 || Cond.size() == 0) &&
528 "SystemZ branch conditions have one component!");
529 assert(!BytesAdded && "code size not handled");
530
531 if (Cond.empty()) {
532 // Unconditional branch?
533 assert(!FBB && "Unconditional branch with multiple successors!");
534 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: SystemZ::J)).addMBB(MBB: TBB);
535 return 1;
536 }
537
538 // Conditional branch.
539 unsigned Count = 0;
540 unsigned CCValid = Cond[0].getImm();
541 unsigned CCMask = Cond[1].getImm();
542 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: SystemZ::BRC))
543 .addImm(Val: CCValid).addImm(Val: CCMask).addMBB(MBB: TBB);
544 ++Count;
545
546 if (FBB) {
547 // Two-way Conditional branch. Insert the second branch.
548 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: SystemZ::J)).addMBB(MBB: FBB);
549 ++Count;
550 }
551 return Count;
552}
553
554bool SystemZInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
555 Register &SrcReg2, int64_t &Mask,
556 int64_t &Value) const {
557 assert(MI.isCompare() && "Caller should have checked for a comparison");
558
559 if (MI.getNumExplicitOperands() == 2 && MI.getOperand(i: 0).isReg() &&
560 MI.getOperand(i: 1).isImm()) {
561 SrcReg = MI.getOperand(i: 0).getReg();
562 SrcReg2 = 0;
563 Value = MI.getOperand(i: 1).getImm();
564 Mask = ~0;
565 return true;
566 }
567
568 return false;
569}
570
571bool SystemZInstrInfo::canInsertSelect(const MachineBasicBlock &MBB,
572 ArrayRef<MachineOperand> Pred,
573 Register DstReg, Register TrueReg,
574 Register FalseReg, int &CondCycles,
575 int &TrueCycles,
576 int &FalseCycles) const {
577 // Not all subtargets have LOCR instructions.
578 if (!STI.hasLoadStoreOnCond())
579 return false;
580 if (Pred.size() != 2)
581 return false;
582
583 // Check register classes.
584 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
585 const TargetRegisterClass *RC =
586 RI.getCommonSubClass(A: MRI.getRegClass(Reg: TrueReg), B: MRI.getRegClass(Reg: FalseReg));
587 if (!RC)
588 return false;
589
590 // We have LOCR instructions for 32 and 64 bit general purpose registers.
591 if ((STI.hasLoadStoreOnCond2() &&
592 SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) ||
593 SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
594 SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {
595 CondCycles = 2;
596 TrueCycles = 2;
597 FalseCycles = 2;
598 return true;
599 }
600
601 // Can't do anything else.
602 return false;
603}
604
605void SystemZInstrInfo::insertSelect(MachineBasicBlock &MBB,
606 MachineBasicBlock::iterator I,
607 const DebugLoc &DL, Register DstReg,
608 ArrayRef<MachineOperand> Pred,
609 Register TrueReg,
610 Register FalseReg) const {
611 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
612 const TargetRegisterClass *RC = MRI.getRegClass(Reg: DstReg);
613
614 assert(Pred.size() == 2 && "Invalid condition");
615 unsigned CCValid = Pred[0].getImm();
616 unsigned CCMask = Pred[1].getImm();
617
618 unsigned Opc;
619 if (SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) {
620 if (STI.hasMiscellaneousExtensions3())
621 Opc = SystemZ::SELRMux;
622 else if (STI.hasLoadStoreOnCond2())
623 Opc = SystemZ::LOCRMux;
624 else {
625 Opc = SystemZ::LOCR;
626 MRI.constrainRegClass(Reg: DstReg, RC: &SystemZ::GR32BitRegClass);
627 Register TReg = MRI.createVirtualRegister(RegClass: &SystemZ::GR32BitRegClass);
628 Register FReg = MRI.createVirtualRegister(RegClass: &SystemZ::GR32BitRegClass);
629 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: TargetOpcode::COPY), DestReg: TReg).addReg(RegNo: TrueReg);
630 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: TargetOpcode::COPY), DestReg: FReg).addReg(RegNo: FalseReg);
631 TrueReg = TReg;
632 FalseReg = FReg;
633 }
634 } else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC)) {
635 if (STI.hasMiscellaneousExtensions3())
636 Opc = SystemZ::SELGR;
637 else
638 Opc = SystemZ::LOCGR;
639 } else
640 llvm_unreachable("Invalid register class");
641
642 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Opc), DestReg: DstReg)
643 .addReg(RegNo: FalseReg).addReg(RegNo: TrueReg)
644 .addImm(Val: CCValid).addImm(Val: CCMask);
645}
646
647bool SystemZInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
648 Register Reg,
649 MachineRegisterInfo *MRI) const {
650 unsigned DefOpc = DefMI.getOpcode();
651
652 if (DefOpc == SystemZ::VGBM) {
653 int64_t ImmVal = DefMI.getOperand(i: 1).getImm();
654 if (ImmVal != 0) // TODO: Handle other values
655 return false;
656
657 // Fold gr128 = COPY (vr128 VGBM imm)
658 //
659 // %tmp:gr64 = LGHI 0
660 // to gr128 = REG_SEQUENCE %tmp, %tmp
661 assert(DefMI.getOperand(0).getReg() == Reg);
662
663 if (!UseMI.isCopy())
664 return false;
665
666 Register CopyDstReg = UseMI.getOperand(i: 0).getReg();
667 if (CopyDstReg.isVirtual() &&
668 MRI->getRegClass(Reg: CopyDstReg) == &SystemZ::GR128BitRegClass &&
669 MRI->hasOneNonDBGUse(RegNo: Reg)) {
670 // TODO: Handle physical registers
671 // TODO: Handle gr64 uses with subregister indexes
672 // TODO: Should this multi-use cases?
673 Register TmpReg = MRI->createVirtualRegister(RegClass: &SystemZ::GR64BitRegClass);
674 MachineBasicBlock &MBB = *UseMI.getParent();
675
676 loadImmediate(MBB, MBBI: UseMI.getIterator(), Reg: TmpReg, Value: ImmVal);
677
678 UseMI.setDesc(get(Opcode: SystemZ::REG_SEQUENCE));
679 UseMI.getOperand(i: 1).setReg(TmpReg);
680 MachineInstrBuilder(*MBB.getParent(), &UseMI)
681 .addImm(Val: SystemZ::subreg_h64)
682 .addReg(RegNo: TmpReg)
683 .addImm(Val: SystemZ::subreg_l64);
684
685 if (MRI->use_nodbg_empty(RegNo: Reg))
686 DefMI.eraseFromParent();
687 return true;
688 }
689
690 return false;
691 }
692
693 if (DefOpc != SystemZ::LHIMux && DefOpc != SystemZ::LHI &&
694 DefOpc != SystemZ::LGHI)
695 return false;
696 if (DefMI.getOperand(i: 0).getReg() != Reg)
697 return false;
698 int32_t ImmVal = (int32_t)DefMI.getOperand(i: 1).getImm();
699
700 unsigned UseOpc = UseMI.getOpcode();
701 unsigned NewUseOpc;
702 unsigned UseIdx;
703 int CommuteIdx = -1;
704 bool TieOps = false;
705 switch (UseOpc) {
706 case SystemZ::SELRMux:
707 TieOps = true;
708 [[fallthrough]];
709 case SystemZ::LOCRMux:
710 if (!STI.hasLoadStoreOnCond2())
711 return false;
712 NewUseOpc = SystemZ::LOCHIMux;
713 if (UseMI.getOperand(i: 2).getReg() == Reg)
714 UseIdx = 2;
715 else if (UseMI.getOperand(i: 1).getReg() == Reg)
716 UseIdx = 2, CommuteIdx = 1;
717 else
718 return false;
719 break;
720 case SystemZ::SELGR:
721 TieOps = true;
722 [[fallthrough]];
723 case SystemZ::LOCGR:
724 if (!STI.hasLoadStoreOnCond2())
725 return false;
726 NewUseOpc = SystemZ::LOCGHI;
727 if (UseMI.getOperand(i: 2).getReg() == Reg)
728 UseIdx = 2;
729 else if (UseMI.getOperand(i: 1).getReg() == Reg)
730 UseIdx = 2, CommuteIdx = 1;
731 else
732 return false;
733 break;
734 default:
735 return false;
736 }
737
738 if (CommuteIdx != -1)
739 if (!commuteInstruction(MI&: UseMI, NewMI: false, OpIdx1: CommuteIdx, OpIdx2: UseIdx))
740 return false;
741
742 bool DeleteDef = MRI->hasOneNonDBGUse(RegNo: Reg);
743 UseMI.setDesc(get(Opcode: NewUseOpc));
744 if (TieOps)
745 UseMI.tieOperands(DefIdx: 0, UseIdx: 1);
746 UseMI.getOperand(i: UseIdx).ChangeToImmediate(ImmVal);
747 if (DeleteDef)
748 DefMI.eraseFromParent();
749
750 return true;
751}
752
753bool SystemZInstrInfo::isPredicable(const MachineInstr &MI) const {
754 unsigned Opcode = MI.getOpcode();
755 if (Opcode == SystemZ::Return ||
756 Opcode == SystemZ::Return_XPLINK ||
757 Opcode == SystemZ::Trap ||
758 Opcode == SystemZ::CallJG ||
759 Opcode == SystemZ::CallBR)
760 return true;
761 return false;
762}
763
764bool SystemZInstrInfo::
765isProfitableToIfCvt(MachineBasicBlock &MBB,
766 unsigned NumCycles, unsigned ExtraPredCycles,
767 BranchProbability Probability) const {
768 // Avoid using conditional returns at the end of a loop (since then
769 // we'd need to emit an unconditional branch to the beginning anyway,
770 // making the loop body longer). This doesn't apply for low-probability
771 // loops (eg. compare-and-swap retry), so just decide based on branch
772 // probability instead of looping structure.
773 // However, since Compare and Trap instructions cost the same as a regular
774 // Compare instruction, we should allow the if conversion to convert this
775 // into a Conditional Compare regardless of the branch probability.
776 if (MBB.getLastNonDebugInstr()->getOpcode() != SystemZ::Trap &&
777 MBB.succ_empty() && Probability < BranchProbability(1, 8))
778 return false;
779 // For now only convert single instructions.
780 return NumCycles == 1;
781}
782
783bool SystemZInstrInfo::
784isProfitableToIfCvt(MachineBasicBlock &TMBB,
785 unsigned NumCyclesT, unsigned ExtraPredCyclesT,
786 MachineBasicBlock &FMBB,
787 unsigned NumCyclesF, unsigned ExtraPredCyclesF,
788 BranchProbability Probability) const {
789 // For now avoid converting mutually-exclusive cases.
790 return false;
791}
792
793bool SystemZInstrInfo::
794isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
795 BranchProbability Probability) const {
796 // For now only duplicate single instructions.
797 return NumCycles == 1;
798}
799
800bool SystemZInstrInfo::PredicateInstruction(
801 MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
802 assert(Pred.size() == 2 && "Invalid condition");
803 unsigned CCValid = Pred[0].getImm();
804 unsigned CCMask = Pred[1].getImm();
805 assert(CCMask > 0 && CCMask < 15 && "Invalid predicate");
806 unsigned Opcode = MI.getOpcode();
807 if (Opcode == SystemZ::Trap) {
808 MI.setDesc(get(Opcode: SystemZ::CondTrap));
809 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
810 .addImm(Val: CCValid).addImm(Val: CCMask)
811 .addReg(RegNo: SystemZ::CC, Flags: RegState::Implicit);
812 return true;
813 }
814 if (Opcode == SystemZ::Return || Opcode == SystemZ::Return_XPLINK) {
815 MI.setDesc(get(Opcode: Opcode == SystemZ::Return ? SystemZ::CondReturn
816 : SystemZ::CondReturn_XPLINK));
817 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
818 .addImm(Val: CCValid)
819 .addImm(Val: CCMask)
820 .addReg(RegNo: SystemZ::CC, Flags: RegState::Implicit);
821 return true;
822 }
823 if (Opcode == SystemZ::CallJG) {
824 MachineOperand FirstOp = MI.getOperand(i: 0);
825 const uint32_t *RegMask = MI.getOperand(i: 1).getRegMask();
826 MI.removeOperand(OpNo: 1);
827 MI.removeOperand(OpNo: 0);
828 MI.setDesc(get(Opcode: SystemZ::CallBRCL));
829 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
830 .addImm(Val: CCValid)
831 .addImm(Val: CCMask)
832 .add(MO: FirstOp)
833 .addRegMask(Mask: RegMask)
834 .addReg(RegNo: SystemZ::CC, Flags: RegState::Implicit);
835 return true;
836 }
837 if (Opcode == SystemZ::CallBR) {
838 MachineOperand Target = MI.getOperand(i: 0);
839 const uint32_t *RegMask = MI.getOperand(i: 1).getRegMask();
840 MI.removeOperand(OpNo: 1);
841 MI.removeOperand(OpNo: 0);
842 MI.setDesc(get(Opcode: SystemZ::CallBCR));
843 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
844 .addImm(Val: CCValid).addImm(Val: CCMask)
845 .add(MO: Target)
846 .addRegMask(Mask: RegMask)
847 .addReg(RegNo: SystemZ::CC, Flags: RegState::Implicit);
848 return true;
849 }
850 return false;
851}
852
853void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
854 MachineBasicBlock::iterator MBBI,
855 const DebugLoc &DL, Register DestReg,
856 Register SrcReg, bool KillSrc,
857 bool RenamableDest,
858 bool RenamableSrc) const {
859 // Split 128-bit GPR moves into two 64-bit moves. Add implicit uses of the
860 // super register in case one of the subregs is undefined.
861 // This handles ADDR128 too.
862 if (SystemZ::GR128BitRegClass.contains(Reg1: DestReg, Reg2: SrcReg)) {
863 copyPhysReg(MBB, MBBI, DL, DestReg: RI.getSubReg(Reg: DestReg, Idx: SystemZ::subreg_h64),
864 SrcReg: RI.getSubReg(Reg: SrcReg, Idx: SystemZ::subreg_h64), KillSrc);
865 MachineInstrBuilder(*MBB.getParent(), std::prev(x: MBBI))
866 .addReg(RegNo: SrcReg, Flags: RegState::Implicit);
867 copyPhysReg(MBB, MBBI, DL, DestReg: RI.getSubReg(Reg: DestReg, Idx: SystemZ::subreg_l64),
868 SrcReg: RI.getSubReg(Reg: SrcReg, Idx: SystemZ::subreg_l64), KillSrc);
869 MachineInstrBuilder(*MBB.getParent(), std::prev(x: MBBI))
870 .addReg(RegNo: SrcReg, Flags: (getKillRegState(B: KillSrc) | RegState::Implicit));
871 return;
872 }
873
874 if (SystemZ::GRX32BitRegClass.contains(Reg1: DestReg, Reg2: SrcReg)) {
875 emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, LowLowOpcode: SystemZ::LR, Size: 32, KillSrc,
876 UndefSrc: false);
877 return;
878 }
879
880 // Move 128-bit floating-point values between VR128 and FP128.
881 if (SystemZ::VR128BitRegClass.contains(Reg: DestReg) &&
882 SystemZ::FP128BitRegClass.contains(Reg: SrcReg)) {
883 MCRegister SrcRegHi =
884 RI.getMatchingSuperReg(Reg: RI.getSubReg(Reg: SrcReg, Idx: SystemZ::subreg_h64),
885 SubIdx: SystemZ::subreg_h64, RC: &SystemZ::VR128BitRegClass);
886 MCRegister SrcRegLo =
887 RI.getMatchingSuperReg(Reg: RI.getSubReg(Reg: SrcReg, Idx: SystemZ::subreg_l64),
888 SubIdx: SystemZ::subreg_h64, RC: &SystemZ::VR128BitRegClass);
889
890 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: SystemZ::VMRHG), DestReg)
891 .addReg(RegNo: SrcRegHi, Flags: getKillRegState(B: KillSrc))
892 .addReg(RegNo: SrcRegLo, Flags: getKillRegState(B: KillSrc));
893 return;
894 }
895 if (SystemZ::FP128BitRegClass.contains(Reg: DestReg) &&
896 SystemZ::VR128BitRegClass.contains(Reg: SrcReg)) {
897 MCRegister DestRegHi =
898 RI.getMatchingSuperReg(Reg: RI.getSubReg(Reg: DestReg, Idx: SystemZ::subreg_h64),
899 SubIdx: SystemZ::subreg_h64, RC: &SystemZ::VR128BitRegClass);
900 MCRegister DestRegLo =
901 RI.getMatchingSuperReg(Reg: RI.getSubReg(Reg: DestReg, Idx: SystemZ::subreg_l64),
902 SubIdx: SystemZ::subreg_h64, RC: &SystemZ::VR128BitRegClass);
903
904 if (DestRegHi != SrcReg.asMCReg())
905 copyPhysReg(MBB, MBBI, DL, DestReg: DestRegHi, SrcReg, KillSrc: false);
906 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: SystemZ::VREPG), DestReg: DestRegLo)
907 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrc)).addImm(Val: 1);
908 return;
909 }
910
911 if (SystemZ::FP128BitRegClass.contains(Reg: DestReg) &&
912 SystemZ::GR128BitRegClass.contains(Reg: SrcReg)) {
913 MCRegister DestRegHi = RI.getSubReg(Reg: DestReg, Idx: SystemZ::subreg_h64);
914 MCRegister DestRegLo = RI.getSubReg(Reg: DestReg, Idx: SystemZ::subreg_l64);
915 MCRegister SrcRegHi = RI.getSubReg(Reg: SrcReg, Idx: SystemZ::subreg_h64);
916 MCRegister SrcRegLo = RI.getSubReg(Reg: SrcReg, Idx: SystemZ::subreg_l64);
917
918 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: SystemZ::LDGR), DestReg: DestRegHi)
919 .addReg(RegNo: SrcRegHi)
920 .addReg(RegNo: DestReg, Flags: RegState::ImplicitDefine);
921
922 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: SystemZ::LDGR), DestReg: DestRegLo)
923 .addReg(RegNo: SrcRegLo, Flags: getKillRegState(B: KillSrc));
924 return;
925 }
926
927 // Move CC value from a GR32.
928 if (DestReg == SystemZ::CC) {
929 unsigned Opcode =
930 SystemZ::GR32BitRegClass.contains(Reg: SrcReg) ? SystemZ::TMLH : SystemZ::TMHH;
931 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode))
932 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrc))
933 .addImm(Val: 3 << (SystemZ::IPM_CC - 16));
934 return;
935 }
936
937 if (SystemZ::GR128BitRegClass.contains(Reg: DestReg) &&
938 SystemZ::VR128BitRegClass.contains(Reg: SrcReg)) {
939 MCRegister DestH64 = RI.getSubReg(Reg: DestReg, Idx: SystemZ::subreg_h64);
940 MCRegister DestL64 = RI.getSubReg(Reg: DestReg, Idx: SystemZ::subreg_l64);
941
942 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: SystemZ::VLGVG), DestReg: DestH64)
943 .addReg(RegNo: SrcReg)
944 .addReg(RegNo: SystemZ::NoRegister)
945 .addImm(Val: 0)
946 .addDef(RegNo: DestReg, Flags: RegState::Implicit);
947 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: SystemZ::VLGVG), DestReg: DestL64)
948 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrc))
949 .addReg(RegNo: SystemZ::NoRegister)
950 .addImm(Val: 1);
951 return;
952 }
953
954 if (SystemZ::VR128BitRegClass.contains(Reg: DestReg) &&
955 SystemZ::GR128BitRegClass.contains(Reg: SrcReg)) {
956 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: SystemZ::VLVGP), DestReg)
957 .addReg(RegNo: RI.getSubReg(Reg: SrcReg, Idx: SystemZ::subreg_h64))
958 .addReg(RegNo: RI.getSubReg(Reg: SrcReg, Idx: SystemZ::subreg_l64));
959 return;
960 }
961
962 // Everything else needs only one instruction.
963 unsigned Opcode;
964 if (SystemZ::GR64BitRegClass.contains(Reg1: DestReg, Reg2: SrcReg))
965 Opcode = SystemZ::LGR;
966 else if (SystemZ::FP16BitRegClass.contains(Reg1: DestReg, Reg2: SrcReg))
967 Opcode = STI.hasVector() ? SystemZ::LDR16 : SystemZ::LER16;
968 else if (SystemZ::FP32BitRegClass.contains(Reg1: DestReg, Reg2: SrcReg))
969 // For z13 we prefer LDR over LER to avoid partial register dependencies.
970 Opcode = STI.hasVector() ? SystemZ::LDR32 : SystemZ::LER;
971 else if (SystemZ::FP64BitRegClass.contains(Reg1: DestReg, Reg2: SrcReg))
972 Opcode = SystemZ::LDR;
973 else if (SystemZ::FP128BitRegClass.contains(Reg1: DestReg, Reg2: SrcReg))
974 Opcode = SystemZ::LXR;
975 else if (SystemZ::VR16BitRegClass.contains(Reg1: DestReg, Reg2: SrcReg))
976 Opcode = SystemZ::VLR16;
977 else if (SystemZ::VR32BitRegClass.contains(Reg1: DestReg, Reg2: SrcReg))
978 Opcode = SystemZ::VLR32;
979 else if (SystemZ::VR64BitRegClass.contains(Reg1: DestReg, Reg2: SrcReg))
980 Opcode = SystemZ::VLR64;
981 else if (SystemZ::VR128BitRegClass.contains(Reg1: DestReg, Reg2: SrcReg))
982 Opcode = SystemZ::VLR;
983 else if (SystemZ::AR32BitRegClass.contains(Reg1: DestReg, Reg2: SrcReg))
984 Opcode = SystemZ::CPYA;
985 else if (SystemZ::GR64BitRegClass.contains(Reg: DestReg) &&
986 SystemZ::FP64BitRegClass.contains(Reg: SrcReg))
987 Opcode = SystemZ::LGDR;
988 else if (SystemZ::FP64BitRegClass.contains(Reg: DestReg) &&
989 SystemZ::GR64BitRegClass.contains(Reg: SrcReg))
990 Opcode = SystemZ::LDGR;
991 else
992 llvm_unreachable("Impossible reg-to-reg copy");
993
994 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode), DestReg)
995 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrc));
996}
997
998void SystemZInstrInfo::storeRegToStackSlot(
999 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
1000 bool isKill, int FrameIdx, const TargetRegisterClass *RC,
1001
1002 Register VReg, MachineInstr::MIFlag Flags) const {
1003 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1004
1005 // Callers may expect a single instruction, so keep 128-bit moves
1006 // together for now and lower them after register allocation.
1007 unsigned LoadOpcode, StoreOpcode;
1008 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
1009 addFrameReference(MIB: BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: StoreOpcode))
1010 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill)),
1011 FI: FrameIdx);
1012}
1013
1014void SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1015 MachineBasicBlock::iterator MBBI,
1016 Register DestReg, int FrameIdx,
1017 const TargetRegisterClass *RC,
1018 Register VReg, unsigned SubReg,
1019 MachineInstr::MIFlag Flags) const {
1020 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1021
1022 // Callers may expect a single instruction, so keep 128-bit moves
1023 // together for now and lower them after register allocation.
1024 unsigned LoadOpcode, StoreOpcode;
1025 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
1026 addFrameReference(MIB: BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: LoadOpcode), DestReg),
1027 FI: FrameIdx);
1028}
1029
1030// Return true if MI is a simple load or store with a 12-bit displacement
1031// and no index. Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
1032static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) {
1033 const MCInstrDesc &MCID = MI->getDesc();
1034 return ((MCID.TSFlags & Flag) &&
1035 isUInt<12>(x: MI->getOperand(i: 2).getImm()) &&
1036 MI->getOperand(i: 3).getReg() == 0);
1037}
1038
1039namespace {
1040
1041struct LogicOp {
1042 LogicOp() = default;
1043 LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)
1044 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
1045
1046 explicit operator bool() const { return RegSize; }
1047
1048 unsigned RegSize = 0;
1049 unsigned ImmLSB = 0;
1050 unsigned ImmSize = 0;
1051};
1052
1053} // end anonymous namespace
1054
1055static LogicOp interpretAndImmediate(unsigned Opcode) {
1056 switch (Opcode) {
1057 case SystemZ::NILMux: return LogicOp(32, 0, 16);
1058 case SystemZ::NIHMux: return LogicOp(32, 16, 16);
1059 case SystemZ::NILL64: return LogicOp(64, 0, 16);
1060 case SystemZ::NILH64: return LogicOp(64, 16, 16);
1061 case SystemZ::NIHL64: return LogicOp(64, 32, 16);
1062 case SystemZ::NIHH64: return LogicOp(64, 48, 16);
1063 case SystemZ::NIFMux: return LogicOp(32, 0, 32);
1064 case SystemZ::NILF64: return LogicOp(64, 0, 32);
1065 case SystemZ::NIHF64: return LogicOp(64, 32, 32);
1066 default: return LogicOp();
1067 }
1068}
1069
1070static void transferDeadCC(MachineInstr *OldMI, MachineInstr *NewMI) {
1071 if (OldMI->registerDefIsDead(Reg: SystemZ::CC, /*TRI=*/nullptr)) {
1072 MachineOperand *CCDef =
1073 NewMI->findRegisterDefOperand(Reg: SystemZ::CC, /*TRI=*/nullptr);
1074 if (CCDef != nullptr)
1075 CCDef->setIsDead(true);
1076 }
1077}
1078
1079static void transferMIFlag(MachineInstr *OldMI, MachineInstr *NewMI,
1080 MachineInstr::MIFlag Flag) {
1081 if (OldMI->getFlag(Flag))
1082 NewMI->setFlag(Flag);
1083}
1084
1085MachineInstr *
1086SystemZInstrInfo::convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
1087 LiveIntervals *LIS) const {
1088 MachineBasicBlock *MBB = MI.getParent();
1089
1090 // Try to convert an AND into an RISBG-type instruction.
1091 // TODO: It might be beneficial to select RISBG and shorten to AND instead.
1092 if (LogicOp And = interpretAndImmediate(Opcode: MI.getOpcode())) {
1093 uint64_t Imm = MI.getOperand(i: 2).getImm() << And.ImmLSB;
1094 // AND IMMEDIATE leaves the other bits of the register unchanged.
1095 Imm |= allOnes(Count: And.RegSize) & ~(allOnes(Count: And.ImmSize) << And.ImmLSB);
1096 unsigned Start, End;
1097 if (isRxSBGMask(Mask: Imm, BitSize: And.RegSize, Start, End)) {
1098 unsigned NewOpcode;
1099 if (And.RegSize == 64) {
1100 NewOpcode = SystemZ::RISBG;
1101 // Prefer RISBGN if available, since it does not clobber CC.
1102 if (STI.hasMiscellaneousExtensions())
1103 NewOpcode = SystemZ::RISBGN;
1104 } else {
1105 NewOpcode = SystemZ::RISBMux;
1106 Start &= 31;
1107 End &= 31;
1108 }
1109 MachineOperand &Dest = MI.getOperand(i: 0);
1110 MachineOperand &Src = MI.getOperand(i: 1);
1111 MachineInstrBuilder MIB =
1112 BuildMI(BB&: *MBB, I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: NewOpcode))
1113 .add(MO: Dest)
1114 .addReg(RegNo: 0)
1115 .addReg(RegNo: Src.getReg(), Flags: getKillRegState(B: Src.isKill()),
1116 SubReg: Src.getSubReg())
1117 .addImm(Val: Start)
1118 .addImm(Val: End + 128)
1119 .addImm(Val: 0);
1120 if (LV) {
1121 unsigned NumOps = MI.getNumOperands();
1122 for (unsigned I = 1; I < NumOps; ++I) {
1123 MachineOperand &Op = MI.getOperand(i: I);
1124 if (Op.isReg() && Op.isKill())
1125 LV->replaceKillInstruction(Reg: Op.getReg(), OldMI&: MI, NewMI&: *MIB);
1126 }
1127 }
1128 if (LIS)
1129 LIS->ReplaceMachineInstrInMaps(MI, NewMI&: *MIB);
1130 transferDeadCC(OldMI: &MI, NewMI: MIB);
1131 return MIB;
1132 }
1133 }
1134 return nullptr;
1135}
1136
1137bool SystemZInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst,
1138 bool Invert) const {
1139 unsigned Opc = Inst.getOpcode();
1140 if (Invert) {
1141 auto InverseOpcode = getInverseOpcode(Opcode: Opc);
1142 if (!InverseOpcode)
1143 return false;
1144 Opc = *InverseOpcode;
1145 }
1146
1147 switch (Opc) {
1148 default:
1149 break;
1150 // Adds and multiplications.
1151 case SystemZ::WFADB:
1152 case SystemZ::WFASB:
1153 case SystemZ::WFAXB:
1154 case SystemZ::VFADB:
1155 case SystemZ::VFASB:
1156 case SystemZ::WFMDB:
1157 case SystemZ::WFMSB:
1158 case SystemZ::WFMXB:
1159 case SystemZ::VFMDB:
1160 case SystemZ::VFMSB:
1161 return (Inst.getFlag(Flag: MachineInstr::MIFlag::FmReassoc) &&
1162 Inst.getFlag(Flag: MachineInstr::MIFlag::FmNsz));
1163 }
1164
1165 return false;
1166}
1167
1168std::optional<unsigned>
1169SystemZInstrInfo::getInverseOpcode(unsigned Opcode) const {
1170 // fadd => fsub
1171 switch (Opcode) {
1172 case SystemZ::WFADB:
1173 return SystemZ::WFSDB;
1174 case SystemZ::WFASB:
1175 return SystemZ::WFSSB;
1176 case SystemZ::WFAXB:
1177 return SystemZ::WFSXB;
1178 case SystemZ::VFADB:
1179 return SystemZ::VFSDB;
1180 case SystemZ::VFASB:
1181 return SystemZ::VFSSB;
1182 // fsub => fadd
1183 case SystemZ::WFSDB:
1184 return SystemZ::WFADB;
1185 case SystemZ::WFSSB:
1186 return SystemZ::WFASB;
1187 case SystemZ::WFSXB:
1188 return SystemZ::WFAXB;
1189 case SystemZ::VFSDB:
1190 return SystemZ::VFADB;
1191 case SystemZ::VFSSB:
1192 return SystemZ::VFASB;
1193 default:
1194 return std::nullopt;
1195 }
1196}
1197
1198MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
1199 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
1200 int FrameIndex, MachineInstr *&CopyMI, LiveIntervals *LIS,
1201 VirtRegMap *VRM) const {
1202 MachineBasicBlock::iterator InsertPt = MI;
1203 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
1204 MachineRegisterInfo &MRI = MF.getRegInfo();
1205 const MachineFrameInfo &MFI = MF.getFrameInfo();
1206 unsigned Size = MFI.getObjectSize(ObjectIdx: FrameIndex);
1207 unsigned Opcode = MI.getOpcode();
1208
1209 // Check CC liveness if new instruction introduces a dead def of CC.
1210 SlotIndex MISlot = SlotIndex();
1211 LiveRange *CCLiveRange = nullptr;
1212 bool CCLiveAtMI = true;
1213 if (LIS) {
1214 MISlot = LIS->getSlotIndexes()->getInstructionIndex(MI).getRegSlot();
1215 auto CCUnits = TRI->regunits(Reg: MCRegister::from(Val: SystemZ::CC));
1216 assert(range_size(CCUnits) == 1 && "CC only has one reg unit.");
1217 CCLiveRange = &LIS->getRegUnit(Unit: *CCUnits.begin());
1218 CCLiveAtMI = CCLiveRange->liveAt(index: MISlot);
1219 }
1220
1221 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
1222 if (!CCLiveAtMI && (Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&
1223 isInt<8>(x: MI.getOperand(i: 2).getImm()) && !MI.getOperand(i: 3).getReg()) {
1224 // LA(Y) %reg, CONST(%reg) -> AGSI %mem, CONST
1225 MachineInstr *BuiltMI = BuildMI(BB&: *InsertPt->getParent(), I: InsertPt,
1226 MIMD: MI.getDebugLoc(), MCID: get(Opcode: SystemZ::AGSI))
1227 .addFrameIndex(Idx: FrameIndex)
1228 .addImm(Val: 0)
1229 .addImm(Val: MI.getOperand(i: 2).getImm());
1230 BuiltMI->findRegisterDefOperand(Reg: SystemZ::CC, /*TRI=*/nullptr)
1231 ->setIsDead(true);
1232 CCLiveRange->createDeadDef(Def: MISlot, VNIAlloc&: LIS->getVNInfoAllocator());
1233 return BuiltMI;
1234 }
1235 return nullptr;
1236 }
1237
1238 // All other cases require a single operand.
1239 if (Ops.size() != 1)
1240 return nullptr;
1241
1242 unsigned OpNum = Ops[0];
1243 const TargetRegisterClass *RC =
1244 MF.getRegInfo().getRegClass(Reg: MI.getOperand(i: OpNum).getReg());
1245 assert((Size * 8 == TRI->getRegSizeInBits(*RC) ||
1246 (RC == &SystemZ::FP16BitRegClass && Size == 4 && !STI.hasVector())) &&
1247 "Invalid size combination");
1248 (void)RC;
1249
1250 if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) && OpNum == 0 &&
1251 isInt<8>(x: MI.getOperand(i: 2).getImm())) {
1252 // A(G)HI %reg, CONST -> A(G)SI %mem, CONST
1253 Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);
1254 MachineInstr *BuiltMI =
1255 BuildMI(BB&: *InsertPt->getParent(), I: InsertPt, MIMD: MI.getDebugLoc(), MCID: get(Opcode))
1256 .addFrameIndex(Idx: FrameIndex)
1257 .addImm(Val: 0)
1258 .addImm(Val: MI.getOperand(i: 2).getImm());
1259 transferDeadCC(OldMI: &MI, NewMI: BuiltMI);
1260 transferMIFlag(OldMI: &MI, NewMI: BuiltMI, Flag: MachineInstr::NoSWrap);
1261 return BuiltMI;
1262 }
1263
1264 if ((Opcode == SystemZ::ALFI && OpNum == 0 &&
1265 isInt<8>(x: (int32_t)MI.getOperand(i: 2).getImm())) ||
1266 (Opcode == SystemZ::ALGFI && OpNum == 0 &&
1267 isInt<8>(x: MI.getOperand(i: 2).getImm()))) {
1268 // AL(G)FI %reg, CONST -> AL(G)SI %mem, CONST
1269 Opcode = (Opcode == SystemZ::ALFI ? SystemZ::ALSI : SystemZ::ALGSI);
1270 MachineInstr *BuiltMI =
1271 BuildMI(BB&: *InsertPt->getParent(), I: InsertPt, MIMD: MI.getDebugLoc(), MCID: get(Opcode))
1272 .addFrameIndex(Idx: FrameIndex)
1273 .addImm(Val: 0)
1274 .addImm(Val: (int8_t)MI.getOperand(i: 2).getImm());
1275 transferDeadCC(OldMI: &MI, NewMI: BuiltMI);
1276 return BuiltMI;
1277 }
1278
1279 if ((Opcode == SystemZ::SLFI && OpNum == 0 &&
1280 isInt<8>(x: (int32_t)-MI.getOperand(i: 2).getImm())) ||
1281 (Opcode == SystemZ::SLGFI && OpNum == 0 &&
1282 isInt<8>(x: (-MI.getOperand(i: 2).getImm())))) {
1283 // SL(G)FI %reg, CONST -> AL(G)SI %mem, -CONST
1284 Opcode = (Opcode == SystemZ::SLFI ? SystemZ::ALSI : SystemZ::ALGSI);
1285 MachineInstr *BuiltMI =
1286 BuildMI(BB&: *InsertPt->getParent(), I: InsertPt, MIMD: MI.getDebugLoc(), MCID: get(Opcode))
1287 .addFrameIndex(Idx: FrameIndex)
1288 .addImm(Val: 0)
1289 .addImm(Val: (int8_t)-MI.getOperand(i: 2).getImm());
1290 transferDeadCC(OldMI: &MI, NewMI: BuiltMI);
1291 return BuiltMI;
1292 }
1293
1294 unsigned MemImmOpc = 0;
1295 switch (Opcode) {
1296 case SystemZ::LHIMux:
1297 case SystemZ::LHI: MemImmOpc = SystemZ::MVHI; break;
1298 case SystemZ::LGHI: MemImmOpc = SystemZ::MVGHI; break;
1299 case SystemZ::CHIMux:
1300 case SystemZ::CHI: MemImmOpc = SystemZ::CHSI; break;
1301 case SystemZ::CGHI: MemImmOpc = SystemZ::CGHSI; break;
1302 case SystemZ::CLFIMux:
1303 case SystemZ::CLFI:
1304 if (isUInt<16>(x: MI.getOperand(i: 1).getImm()))
1305 MemImmOpc = SystemZ::CLFHSI;
1306 break;
1307 case SystemZ::CLGFI:
1308 if (isUInt<16>(x: MI.getOperand(i: 1).getImm()))
1309 MemImmOpc = SystemZ::CLGHSI;
1310 break;
1311 default: break;
1312 }
1313 if (MemImmOpc)
1314 return BuildMI(BB&: *InsertPt->getParent(), I: InsertPt, MIMD: MI.getDebugLoc(),
1315 MCID: get(Opcode: MemImmOpc))
1316 .addFrameIndex(Idx: FrameIndex)
1317 .addImm(Val: 0)
1318 .addImm(Val: MI.getOperand(i: 1).getImm());
1319
1320 if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
1321 bool Op0IsGPR = (Opcode == SystemZ::LGDR);
1322 bool Op1IsGPR = (Opcode == SystemZ::LDGR);
1323 // If we're spilling the destination of an LDGR or LGDR, store the
1324 // source register instead.
1325 if (OpNum == 0) {
1326 unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
1327 return BuildMI(BB&: *InsertPt->getParent(), I: InsertPt, MIMD: MI.getDebugLoc(),
1328 MCID: get(Opcode: StoreOpcode))
1329 .add(MO: MI.getOperand(i: 1))
1330 .addFrameIndex(Idx: FrameIndex)
1331 .addImm(Val: 0)
1332 .addReg(RegNo: 0);
1333 }
1334 // If we're spilling the source of an LDGR or LGDR, load the
1335 // destination register instead.
1336 if (OpNum == 1) {
1337 unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;
1338 return BuildMI(BB&: *InsertPt->getParent(), I: InsertPt, MIMD: MI.getDebugLoc(),
1339 MCID: get(Opcode: LoadOpcode))
1340 .add(MO: MI.getOperand(i: 0))
1341 .addFrameIndex(Idx: FrameIndex)
1342 .addImm(Val: 0)
1343 .addReg(RegNo: 0);
1344 }
1345 }
1346
1347 // Look for cases where the source of a simple store or the destination
1348 // of a simple load is being spilled. Try to use MVC instead.
1349 //
1350 // Although MVC is in practice a fast choice in these cases, it is still
1351 // logically a bytewise copy. This means that we cannot use it if the
1352 // load or store is volatile. We also wouldn't be able to use MVC if
1353 // the two memories partially overlap, but that case cannot occur here,
1354 // because we know that one of the memories is a full frame index.
1355 //
1356 // For performance reasons, we also want to avoid using MVC if the addresses
1357 // might be equal. We don't worry about that case here, because spill slot
1358 // coloring happens later, and because we have special code to remove
1359 // MVCs that turn out to be redundant.
1360 if (OpNum == 0 && MI.hasOneMemOperand()) {
1361 MachineMemOperand *MMO = *MI.memoperands_begin();
1362 if (MMO->getSize() == Size && !MMO->isVolatile() && !MMO->isAtomic()) {
1363 // Handle conversion of loads.
1364 if (isSimpleBD12Move(MI: &MI, Flag: SystemZII::SimpleBDXLoad)) {
1365 return BuildMI(BB&: *InsertPt->getParent(), I: InsertPt, MIMD: MI.getDebugLoc(),
1366 MCID: get(Opcode: SystemZ::MVC))
1367 .addFrameIndex(Idx: FrameIndex)
1368 .addImm(Val: 0)
1369 .addImm(Val: Size)
1370 .add(MO: MI.getOperand(i: 1))
1371 .addImm(Val: MI.getOperand(i: 2).getImm())
1372 .addMemOperand(MMO);
1373 }
1374 // Handle conversion of stores.
1375 if (isSimpleBD12Move(MI: &MI, Flag: SystemZII::SimpleBDXStore)) {
1376 return BuildMI(BB&: *InsertPt->getParent(), I: InsertPt, MIMD: MI.getDebugLoc(),
1377 MCID: get(Opcode: SystemZ::MVC))
1378 .add(MO: MI.getOperand(i: 1))
1379 .addImm(Val: MI.getOperand(i: 2).getImm())
1380 .addImm(Val: Size)
1381 .addFrameIndex(Idx: FrameIndex)
1382 .addImm(Val: 0)
1383 .addMemOperand(MMO);
1384 }
1385 }
1386 }
1387
1388 // If the spilled operand is the final one or the instruction is
1389 // commutable, try to change <INSN>R into <INSN>. Don't introduce a def of
1390 // CC if it is live and MI does not define it.
1391 unsigned NumOps = MI.getNumExplicitOperands();
1392 int MemOpcode = SystemZ::getMemOpcode(Opcode);
1393 if (MemOpcode == -1 ||
1394 (CCLiveAtMI && !MI.definesRegister(Reg: SystemZ::CC, /*TRI=*/nullptr) &&
1395 get(Opcode: MemOpcode).hasImplicitDefOfPhysReg(Reg: SystemZ::CC)))
1396 return nullptr;
1397
1398 // Check if all other vregs have a usable allocation in the case of vector
1399 // to FP conversion.
1400 const MCInstrDesc &MCID = MI.getDesc();
1401 for (unsigned I = 0, E = MCID.getNumOperands(); I != E; ++I) {
1402 const MCOperandInfo &MCOI = MCID.operands()[I];
1403 if (MCOI.OperandType != MCOI::OPERAND_REGISTER || I == OpNum)
1404 continue;
1405 const TargetRegisterClass *RC = TRI->getRegClass(i: MCOI.RegClass);
1406 if (RC == &SystemZ::VR32BitRegClass || RC == &SystemZ::VR64BitRegClass) {
1407 Register Reg = MI.getOperand(i: I).getReg();
1408 Register PhysReg = Reg.isVirtual()
1409 ? (VRM ? Register(VRM->getPhys(virtReg: Reg)) : Register())
1410 : Reg;
1411 if (!PhysReg ||
1412 !(SystemZ::FP32BitRegClass.contains(Reg: PhysReg) ||
1413 SystemZ::FP64BitRegClass.contains(Reg: PhysReg) ||
1414 SystemZ::VF128BitRegClass.contains(Reg: PhysReg)))
1415 return nullptr;
1416 }
1417 }
1418 // Fused multiply and add/sub need to have the same dst and accumulator reg.
1419 bool FusedFPOp = (Opcode == SystemZ::WFMADB || Opcode == SystemZ::WFMASB ||
1420 Opcode == SystemZ::WFMSDB || Opcode == SystemZ::WFMSSB);
1421 if (FusedFPOp) {
1422 Register DstReg = VRM->getPhys(virtReg: MI.getOperand(i: 0).getReg());
1423 Register AccReg = VRM->getPhys(virtReg: MI.getOperand(i: 3).getReg());
1424 if (OpNum == 0 || OpNum == 3 || DstReg != AccReg)
1425 return nullptr;
1426 }
1427
1428 // Try to swap compare operands if possible.
1429 bool NeedsCommute = false;
1430 if ((MI.getOpcode() == SystemZ::CR || MI.getOpcode() == SystemZ::CGR ||
1431 MI.getOpcode() == SystemZ::CLR || MI.getOpcode() == SystemZ::CLGR ||
1432 MI.getOpcode() == SystemZ::WFCDB || MI.getOpcode() == SystemZ::WFCSB ||
1433 MI.getOpcode() == SystemZ::WFKDB || MI.getOpcode() == SystemZ::WFKSB) &&
1434 OpNum == 0 && prepareCompareSwapOperands(MBBI: MI))
1435 NeedsCommute = true;
1436
1437 bool CCOperands = false;
1438 if (MI.getOpcode() == SystemZ::LOCRMux || MI.getOpcode() == SystemZ::LOCGR ||
1439 MI.getOpcode() == SystemZ::SELRMux || MI.getOpcode() == SystemZ::SELGR) {
1440 assert(MI.getNumOperands() == 6 && NumOps == 5 &&
1441 "LOCR/SELR instruction operands corrupt?");
1442 NumOps -= 2;
1443 CCOperands = true;
1444 }
1445
1446 // See if this is a 3-address instruction that is convertible to 2-address
1447 // and suitable for folding below. Only try this with virtual registers
1448 // and a provided VRM (during regalloc).
1449 if (NumOps == 3 && SystemZ::getTargetMemOpcode(Opcode: MemOpcode) != -1) {
1450 if (VRM == nullptr)
1451 return nullptr;
1452 else {
1453 Register DstReg = MI.getOperand(i: 0).getReg();
1454 Register DstPhys =
1455 (DstReg.isVirtual() ? Register(VRM->getPhys(virtReg: DstReg)) : DstReg);
1456 Register SrcReg = (OpNum == 2 ? MI.getOperand(i: 1).getReg()
1457 : ((OpNum == 1 && MI.isCommutable())
1458 ? MI.getOperand(i: 2).getReg()
1459 : Register()));
1460 if (DstPhys && !SystemZ::GRH32BitRegClass.contains(Reg: DstPhys) && SrcReg &&
1461 SrcReg.isVirtual() && DstPhys == VRM->getPhys(virtReg: SrcReg))
1462 NeedsCommute = (OpNum == 1);
1463 else
1464 return nullptr;
1465 }
1466 }
1467
1468 if ((OpNum == NumOps - 1) || NeedsCommute || FusedFPOp) {
1469 const MCInstrDesc &MemDesc = get(Opcode: MemOpcode);
1470 uint64_t AccessBytes = SystemZII::getAccessSize(Flags: MemDesc.TSFlags);
1471 assert(AccessBytes != 0 && "Size of access should be known");
1472 assert(AccessBytes <= Size && "Access outside the frame index");
1473 uint64_t Offset = Size - AccessBytes;
1474 MachineInstrBuilder MIB = BuildMI(BB&: *InsertPt->getParent(), I: InsertPt,
1475 MIMD: MI.getDebugLoc(), MCID: get(Opcode: MemOpcode));
1476 if (MI.isCompare()) {
1477 assert(NumOps == 2 && "Expected 2 register operands for a compare.");
1478 MIB.add(MO: MI.getOperand(i: NeedsCommute ? 1 : 0));
1479 }
1480 else if (FusedFPOp) {
1481 MIB.add(MO: MI.getOperand(i: 0));
1482 MIB.add(MO: MI.getOperand(i: 3));
1483 MIB.add(MO: MI.getOperand(i: OpNum == 1 ? 2 : 1));
1484 }
1485 else {
1486 MIB.add(MO: MI.getOperand(i: 0));
1487 if (NeedsCommute)
1488 MIB.add(MO: MI.getOperand(i: 2));
1489 else
1490 for (unsigned I = 1; I < OpNum; ++I)
1491 MIB.add(MO: MI.getOperand(i: I));
1492 }
1493 MIB.addFrameIndex(Idx: FrameIndex).addImm(Val: Offset);
1494 if (MemDesc.TSFlags & SystemZII::HasIndex)
1495 MIB.addReg(RegNo: 0);
1496 if (CCOperands) {
1497 unsigned CCValid = MI.getOperand(i: NumOps).getImm();
1498 unsigned CCMask = MI.getOperand(i: NumOps + 1).getImm();
1499 MIB.addImm(Val: CCValid);
1500 MIB.addImm(Val: NeedsCommute ? CCMask ^ CCValid : CCMask);
1501 }
1502 if (MIB->definesRegister(Reg: SystemZ::CC, /*TRI=*/nullptr) &&
1503 (!MI.definesRegister(Reg: SystemZ::CC, /*TRI=*/nullptr) ||
1504 MI.registerDefIsDead(Reg: SystemZ::CC, /*TRI=*/nullptr))) {
1505 MIB->addRegisterDead(Reg: SystemZ::CC, RegInfo: TRI);
1506 if (CCLiveRange)
1507 CCLiveRange->createDeadDef(Def: MISlot, VNIAlloc&: LIS->getVNInfoAllocator());
1508 }
1509 // Constrain the register classes if converted from a vector opcode. The
1510 // allocated regs are in an FP reg-class per previous check above.
1511 for (const MachineOperand &MO : MIB->operands())
1512 if (MO.isReg() && MO.getReg().isVirtual()) {
1513 Register Reg = MO.getReg();
1514 if (MRI.getRegClass(Reg) == &SystemZ::VR32BitRegClass)
1515 MRI.setRegClass(Reg, RC: &SystemZ::FP32BitRegClass);
1516 else if (MRI.getRegClass(Reg) == &SystemZ::VR64BitRegClass)
1517 MRI.setRegClass(Reg, RC: &SystemZ::FP64BitRegClass);
1518 else if (MRI.getRegClass(Reg) == &SystemZ::VR128BitRegClass)
1519 MRI.setRegClass(Reg, RC: &SystemZ::VF128BitRegClass);
1520 }
1521
1522 transferDeadCC(OldMI: &MI, NewMI: MIB);
1523 transferMIFlag(OldMI: &MI, NewMI: MIB, Flag: MachineInstr::NoSWrap);
1524 transferMIFlag(OldMI: &MI, NewMI: MIB, Flag: MachineInstr::NoFPExcept);
1525 return MIB;
1526 }
1527
1528 return nullptr;
1529}
1530
1531MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
1532 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
1533 MachineInstr &LoadMI, MachineInstr *&CopyMI, LiveIntervals *LIS,
1534 VirtRegMap *VRM) const {
1535 MachineBasicBlock::iterator InsertPt = MI;
1536 MachineRegisterInfo *MRI = &MF.getRegInfo();
1537 MachineBasicBlock *MBB = MI.getParent();
1538
1539 // For reassociable FP operations, any loads have been purposefully left
1540 // unfolded so that MachineCombiner can do its work on reg/reg
1541 // opcodes. After that, as many loads as possible are now folded.
1542 // TODO: This may be beneficial with other opcodes as well as machine-sink
1543 // can move loads close to their user in a different MBB, which the isel
1544 // matcher did not see.
1545 unsigned LoadOpc = 0;
1546 unsigned RegMemOpcode = 0;
1547 const TargetRegisterClass *FPRC = nullptr;
1548 RegMemOpcode = MI.getOpcode() == SystemZ::WFADB ? SystemZ::ADB
1549 : MI.getOpcode() == SystemZ::WFSDB ? SystemZ::SDB
1550 : MI.getOpcode() == SystemZ::WFMDB ? SystemZ::MDB
1551 : 0;
1552 if (RegMemOpcode) {
1553 LoadOpc = SystemZ::VL64;
1554 FPRC = &SystemZ::FP64BitRegClass;
1555 } else {
1556 RegMemOpcode = MI.getOpcode() == SystemZ::WFASB ? SystemZ::AEB
1557 : MI.getOpcode() == SystemZ::WFSSB ? SystemZ::SEB
1558 : MI.getOpcode() == SystemZ::WFMSB ? SystemZ::MEEB
1559 : 0;
1560 if (RegMemOpcode) {
1561 LoadOpc = SystemZ::VL32;
1562 FPRC = &SystemZ::FP32BitRegClass;
1563 }
1564 }
1565 if (!RegMemOpcode || LoadMI.getOpcode() != LoadOpc)
1566 return nullptr;
1567
1568 // If RegMemOpcode clobbers CC, first make sure CC is not live at this point.
1569 if (get(Opcode: RegMemOpcode).hasImplicitDefOfPhysReg(Reg: SystemZ::CC)) {
1570 for (MachineBasicBlock::iterator MII = InsertPt;;) {
1571 if (MII == MBB->begin()) {
1572 if (MBB->isLiveIn(Reg: SystemZ::CC))
1573 return nullptr;
1574 break;
1575 }
1576 --MII;
1577 if (MII->definesRegister(Reg: SystemZ::CC, /*TRI=*/nullptr)) {
1578 if (!MII->registerDefIsDead(Reg: SystemZ::CC, /*TRI=*/nullptr))
1579 return nullptr;
1580 break;
1581 }
1582 }
1583 }
1584
1585 Register FoldAsLoadDefReg = LoadMI.getOperand(i: 0).getReg();
1586 if (Ops.size() != 1 || FoldAsLoadDefReg != MI.getOperand(i: Ops[0]).getReg())
1587 return nullptr;
1588 Register DstReg = MI.getOperand(i: 0).getReg();
1589 MachineOperand LHS = MI.getOperand(i: 1);
1590 MachineOperand RHS = MI.getOperand(i: 2);
1591 MachineOperand &RegMO = RHS.getReg() == FoldAsLoadDefReg ? LHS : RHS;
1592 if ((RegMemOpcode == SystemZ::SDB || RegMemOpcode == SystemZ::SEB) &&
1593 FoldAsLoadDefReg != RHS.getReg())
1594 return nullptr;
1595 if (!MRI->isSSA() && DstReg != RegMO.getReg())
1596 return nullptr;
1597
1598 MachineOperand &Base = LoadMI.getOperand(i: 1);
1599 MachineOperand &Disp = LoadMI.getOperand(i: 2);
1600 MachineOperand &Indx = LoadMI.getOperand(i: 3);
1601 MachineInstrBuilder MIB =
1602 BuildMI(BB&: *MI.getParent(), I: InsertPt, MIMD: MI.getDebugLoc(), MCID: get(Opcode: RegMemOpcode), DestReg: DstReg)
1603 .add(MO: RegMO)
1604 .add(MO: Base)
1605 .add(MO: Disp)
1606 .add(MO: Indx);
1607 MIB->addRegisterDead(Reg: SystemZ::CC, RegInfo: &RI);
1608 MRI->setRegClass(Reg: DstReg, RC: FPRC);
1609 MRI->setRegClass(Reg: RegMO.getReg(), RC: FPRC);
1610 transferMIFlag(OldMI: &MI, NewMI: MIB, Flag: MachineInstr::NoFPExcept);
1611
1612 return MIB;
1613}
1614
1615bool SystemZInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1616 switch (MI.getOpcode()) {
1617 case SystemZ::L128:
1618 splitMove(MI, NewOpcode: SystemZ::LG);
1619 return true;
1620
1621 case SystemZ::ST128:
1622 splitMove(MI, NewOpcode: SystemZ::STG);
1623 return true;
1624
1625 case SystemZ::LX:
1626 splitMove(MI, NewOpcode: SystemZ::LD);
1627 return true;
1628
1629 case SystemZ::STX:
1630 splitMove(MI, NewOpcode: SystemZ::STD);
1631 return true;
1632
1633 case SystemZ::LBMux:
1634 expandRXYPseudo(MI, LowOpcode: SystemZ::LB, HighOpcode: SystemZ::LBH);
1635 return true;
1636
1637 case SystemZ::LHMux:
1638 expandRXYPseudo(MI, LowOpcode: SystemZ::LH, HighOpcode: SystemZ::LHH);
1639 return true;
1640
1641 case SystemZ::LLCRMux:
1642 expandZExtPseudo(MI, LowOpcode: SystemZ::LLCR, Size: 8);
1643 return true;
1644
1645 case SystemZ::LLHRMux:
1646 expandZExtPseudo(MI, LowOpcode: SystemZ::LLHR, Size: 16);
1647 return true;
1648
1649 case SystemZ::LLCMux:
1650 expandRXYPseudo(MI, LowOpcode: SystemZ::LLC, HighOpcode: SystemZ::LLCH);
1651 return true;
1652
1653 case SystemZ::LLHMux:
1654 expandRXYPseudo(MI, LowOpcode: SystemZ::LLH, HighOpcode: SystemZ::LLHH);
1655 return true;
1656
1657 case SystemZ::LMux:
1658 expandRXYPseudo(MI, LowOpcode: SystemZ::L, HighOpcode: SystemZ::LFH);
1659 return true;
1660
1661 case SystemZ::LOCMux:
1662 expandLOCPseudo(MI, LowOpcode: SystemZ::LOC, HighOpcode: SystemZ::LOCFH);
1663 return true;
1664
1665 case SystemZ::LOCHIMux:
1666 expandLOCPseudo(MI, LowOpcode: SystemZ::LOCHI, HighOpcode: SystemZ::LOCHHI);
1667 return true;
1668
1669 case SystemZ::STCMux:
1670 expandRXYPseudo(MI, LowOpcode: SystemZ::STC, HighOpcode: SystemZ::STCH);
1671 return true;
1672
1673 case SystemZ::STHMux:
1674 expandRXYPseudo(MI, LowOpcode: SystemZ::STH, HighOpcode: SystemZ::STHH);
1675 return true;
1676
1677 case SystemZ::STMux:
1678 expandRXYPseudo(MI, LowOpcode: SystemZ::ST, HighOpcode: SystemZ::STFH);
1679 return true;
1680
1681 case SystemZ::STOCMux:
1682 expandLOCPseudo(MI, LowOpcode: SystemZ::STOC, HighOpcode: SystemZ::STOCFH);
1683 return true;
1684
1685 case SystemZ::LHIMux:
1686 expandRIPseudo(MI, LowOpcode: SystemZ::LHI, HighOpcode: SystemZ::IIHF, ConvertHigh: true);
1687 return true;
1688
1689 case SystemZ::IIFMux:
1690 expandRIPseudo(MI, LowOpcode: SystemZ::IILF, HighOpcode: SystemZ::IIHF, ConvertHigh: false);
1691 return true;
1692
1693 case SystemZ::IILMux:
1694 expandRIPseudo(MI, LowOpcode: SystemZ::IILL, HighOpcode: SystemZ::IIHL, ConvertHigh: false);
1695 return true;
1696
1697 case SystemZ::IIHMux:
1698 expandRIPseudo(MI, LowOpcode: SystemZ::IILH, HighOpcode: SystemZ::IIHH, ConvertHigh: false);
1699 return true;
1700
1701 case SystemZ::NIFMux:
1702 expandRIPseudo(MI, LowOpcode: SystemZ::NILF, HighOpcode: SystemZ::NIHF, ConvertHigh: false);
1703 return true;
1704
1705 case SystemZ::NILMux:
1706 expandRIPseudo(MI, LowOpcode: SystemZ::NILL, HighOpcode: SystemZ::NIHL, ConvertHigh: false);
1707 return true;
1708
1709 case SystemZ::NIHMux:
1710 expandRIPseudo(MI, LowOpcode: SystemZ::NILH, HighOpcode: SystemZ::NIHH, ConvertHigh: false);
1711 return true;
1712
1713 case SystemZ::OIFMux:
1714 expandRIPseudo(MI, LowOpcode: SystemZ::OILF, HighOpcode: SystemZ::OIHF, ConvertHigh: false);
1715 return true;
1716
1717 case SystemZ::OILMux:
1718 expandRIPseudo(MI, LowOpcode: SystemZ::OILL, HighOpcode: SystemZ::OIHL, ConvertHigh: false);
1719 return true;
1720
1721 case SystemZ::OIHMux:
1722 expandRIPseudo(MI, LowOpcode: SystemZ::OILH, HighOpcode: SystemZ::OIHH, ConvertHigh: false);
1723 return true;
1724
1725 case SystemZ::XIFMux:
1726 expandRIPseudo(MI, LowOpcode: SystemZ::XILF, HighOpcode: SystemZ::XIHF, ConvertHigh: false);
1727 return true;
1728
1729 case SystemZ::TMLMux:
1730 expandRIPseudo(MI, LowOpcode: SystemZ::TMLL, HighOpcode: SystemZ::TMHL, ConvertHigh: false);
1731 return true;
1732
1733 case SystemZ::TMHMux:
1734 expandRIPseudo(MI, LowOpcode: SystemZ::TMLH, HighOpcode: SystemZ::TMHH, ConvertHigh: false);
1735 return true;
1736
1737 case SystemZ::AHIMux:
1738 expandRIPseudo(MI, LowOpcode: SystemZ::AHI, HighOpcode: SystemZ::AIH, ConvertHigh: false);
1739 return true;
1740
1741 case SystemZ::AHIMuxK:
1742 expandRIEPseudo(MI, LowOpcode: SystemZ::AHI, LowOpcodeK: SystemZ::AHIK, HighOpcode: SystemZ::AIH);
1743 return true;
1744
1745 case SystemZ::AFIMux:
1746 expandRIPseudo(MI, LowOpcode: SystemZ::AFI, HighOpcode: SystemZ::AIH, ConvertHigh: false);
1747 return true;
1748
1749 case SystemZ::CHIMux:
1750 expandRIPseudo(MI, LowOpcode: SystemZ::CHI, HighOpcode: SystemZ::CIH, ConvertHigh: false);
1751 return true;
1752
1753 case SystemZ::CFIMux:
1754 expandRIPseudo(MI, LowOpcode: SystemZ::CFI, HighOpcode: SystemZ::CIH, ConvertHigh: false);
1755 return true;
1756
1757 case SystemZ::CLFIMux:
1758 expandRIPseudo(MI, LowOpcode: SystemZ::CLFI, HighOpcode: SystemZ::CLIH, ConvertHigh: false);
1759 return true;
1760
1761 case SystemZ::CMux:
1762 expandRXYPseudo(MI, LowOpcode: SystemZ::C, HighOpcode: SystemZ::CHF);
1763 return true;
1764
1765 case SystemZ::CLMux:
1766 expandRXYPseudo(MI, LowOpcode: SystemZ::CL, HighOpcode: SystemZ::CLHF);
1767 return true;
1768
1769 case SystemZ::RISBMux: {
1770 bool DestIsHigh = SystemZ::isHighReg(Reg: MI.getOperand(i: 0).getReg());
1771 bool SrcIsHigh = SystemZ::isHighReg(Reg: MI.getOperand(i: 2).getReg());
1772 if (SrcIsHigh == DestIsHigh)
1773 MI.setDesc(get(Opcode: DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
1774 else {
1775 MI.setDesc(get(Opcode: DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));
1776 MI.getOperand(i: 5).setImm(MI.getOperand(i: 5).getImm() ^ 32);
1777 }
1778 return true;
1779 }
1780
1781 case SystemZ::ADJDYNALLOC:
1782 splitAdjDynAlloc(MI);
1783 return true;
1784
1785 case SystemZ::MOV_STACKGUARD:
1786 expandStackGuardPseudo(MI, Opcode: SystemZ::MVC);
1787 return true;
1788
1789 case SystemZ::CMP_STACKGUARD:
1790 expandStackGuardPseudo(MI, Opcode: SystemZ::CLC);
1791 return true;
1792
1793 default:
1794 return false;
1795 }
1796}
1797
1798void SystemZInstrInfo::expandStackGuardPseudo(MachineInstr &MI,
1799 unsigned Opcode) const {
1800 MachineBasicBlock &MBB = *(MI.getParent());
1801 const MachineFunction &MF = *(MBB.getParent());
1802 const auto DL = MI.getDebugLoc();
1803 const Module *M = MF.getFunction().getParent();
1804 StringRef GuardType = M->getStackProtectorGuard();
1805 unsigned int Offset = 0;
1806
1807 Register AddrReg = MI.getOperand(i: 0).getReg();
1808
1809 assert(
1810 AddrReg != MI.getOperand(1).getReg() &&
1811 "Scratch register for stack guard address blocked by operand register.");
1812
1813 // Emit an appropriate pseudo for the guard type, which loads the address of
1814 // said guard into the scratch register AddrReg.
1815 if (GuardType.empty() || (GuardType == "tls")) {
1816 // Emit a load of the TLS block's address
1817 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: SystemZ::LOAD_TLS_BLOCK_ADDR), DestReg: AddrReg);
1818 // Record the appropriate stack guard offset (40 in the tls case).
1819 Offset = 40;
1820 } else if (GuardType == "global") {
1821 // Emit a load of the global stack guard's address
1822 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: SystemZ::LOAD_GLOBAL_STACKGUARD_ADDR), DestReg: AddrReg);
1823 } else {
1824 report_fatal_error(reason: Twine("unknown stack protector type \"") + GuardType +
1825 "\".");
1826 }
1827
1828 // Construct the appropriate move or compare instruction using the
1829 // scratch register.
1830 BuildMI(BB&: *(MI.getParent()), I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode))
1831 .addReg(RegNo: MI.getOperand(i: 1).getReg())
1832 .addImm(Val: MI.getOperand(i: 2).getImm())
1833 .addImm(Val: 8)
1834 .addReg(RegNo: AddrReg)
1835 .addImm(Val: Offset);
1836
1837 MI.removeFromParent();
1838}
1839
1840unsigned SystemZInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
1841 if (MI.isInlineAsm()) {
1842 const MachineFunction *MF = MI.getParent()->getParent();
1843 const char *AsmStr = MI.getOperand(i: 0).getSymbolName();
1844 return getInlineAsmLength(Str: AsmStr, MAI: MF->getTarget().getMCAsmInfo());
1845 }
1846 else if (MI.getOpcode() == SystemZ::PATCHPOINT)
1847 return PatchPointOpers(&MI).getNumPatchBytes();
1848 else if (MI.getOpcode() == SystemZ::STACKMAP)
1849 return MI.getOperand(i: 1).getImm();
1850 else if (MI.getOpcode() == SystemZ::FENTRY_CALL)
1851 return 6;
1852 if (MI.getOpcode() == TargetOpcode::PATCHABLE_FUNCTION_ENTER)
1853 return 18;
1854 if (MI.getOpcode() == TargetOpcode::PATCHABLE_RET)
1855 return 18 + (MI.getOperand(i: 0).getImm() == SystemZ::CondReturn ? 4 : 0);
1856 if (MI.getOpcode() == TargetOpcode::BUNDLE)
1857 return getInstBundleSize(MI);
1858 if (MI.getOpcode() == SystemZ::LOAD_TLS_BLOCK_ADDR)
1859 // ear (4), sllg (6), ear (4) = 14 bytes
1860 return 14;
1861 if (MI.getOpcode() == SystemZ::LOAD_GLOBAL_STACKGUARD_ADDR)
1862 // Both larl and lgrl are 6 bytes long.
1863 return 6;
1864
1865 return MI.getDesc().getSize();
1866}
1867
1868SystemZII::Branch
1869SystemZInstrInfo::getBranchInfo(const MachineInstr &MI) const {
1870 switch (MI.getOpcode()) {
1871 case SystemZ::BR:
1872 case SystemZ::BI:
1873 case SystemZ::J:
1874 case SystemZ::JG:
1875 return SystemZII::Branch(SystemZII::BranchNormal, SystemZ::CCMASK_ANY,
1876 SystemZ::CCMASK_ANY, &MI.getOperand(i: 0));
1877
1878 case SystemZ::BRC:
1879 case SystemZ::BRCL:
1880 return SystemZII::Branch(SystemZII::BranchNormal, MI.getOperand(i: 0).getImm(),
1881 MI.getOperand(i: 1).getImm(), &MI.getOperand(i: 2));
1882
1883 case SystemZ::BRCT:
1884 case SystemZ::BRCTH:
1885 return SystemZII::Branch(SystemZII::BranchCT, SystemZ::CCMASK_ICMP,
1886 SystemZ::CCMASK_CMP_NE, &MI.getOperand(i: 2));
1887
1888 case SystemZ::BRCTG:
1889 return SystemZII::Branch(SystemZII::BranchCTG, SystemZ::CCMASK_ICMP,
1890 SystemZ::CCMASK_CMP_NE, &MI.getOperand(i: 2));
1891
1892 case SystemZ::CIJ:
1893 case SystemZ::CRJ:
1894 return SystemZII::Branch(SystemZII::BranchC, SystemZ::CCMASK_ICMP,
1895 MI.getOperand(i: 2).getImm(), &MI.getOperand(i: 3));
1896
1897 case SystemZ::CLIJ:
1898 case SystemZ::CLRJ:
1899 return SystemZII::Branch(SystemZII::BranchCL, SystemZ::CCMASK_ICMP,
1900 MI.getOperand(i: 2).getImm(), &MI.getOperand(i: 3));
1901
1902 case SystemZ::CGIJ:
1903 case SystemZ::CGRJ:
1904 return SystemZII::Branch(SystemZII::BranchCG, SystemZ::CCMASK_ICMP,
1905 MI.getOperand(i: 2).getImm(), &MI.getOperand(i: 3));
1906
1907 case SystemZ::CLGIJ:
1908 case SystemZ::CLGRJ:
1909 return SystemZII::Branch(SystemZII::BranchCLG, SystemZ::CCMASK_ICMP,
1910 MI.getOperand(i: 2).getImm(), &MI.getOperand(i: 3));
1911
1912 case SystemZ::INLINEASM_BR:
1913 // Don't try to analyze asm goto, so pass nullptr as branch target argument.
1914 return SystemZII::Branch(SystemZII::AsmGoto, 0, 0, nullptr);
1915
1916 default:
1917 llvm_unreachable("Unrecognized branch opcode");
1918 }
1919}
1920
1921void SystemZInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC,
1922 unsigned &LoadOpcode,
1923 unsigned &StoreOpcode) const {
1924 if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
1925 LoadOpcode = SystemZ::L;
1926 StoreOpcode = SystemZ::ST;
1927 } else if (RC == &SystemZ::GRH32BitRegClass) {
1928 LoadOpcode = SystemZ::LFH;
1929 StoreOpcode = SystemZ::STFH;
1930 } else if (RC == &SystemZ::GRX32BitRegClass) {
1931 LoadOpcode = SystemZ::LMux;
1932 StoreOpcode = SystemZ::STMux;
1933 } else if (RC == &SystemZ::GR64BitRegClass ||
1934 RC == &SystemZ::ADDR64BitRegClass) {
1935 LoadOpcode = SystemZ::LG;
1936 StoreOpcode = SystemZ::STG;
1937 } else if (RC == &SystemZ::GR128BitRegClass ||
1938 RC == &SystemZ::ADDR128BitRegClass) {
1939 LoadOpcode = SystemZ::L128;
1940 StoreOpcode = SystemZ::ST128;
1941 } else if (RC == &SystemZ::FP16BitRegClass && !STI.hasVector()) {
1942 LoadOpcode = SystemZ::LE16;
1943 StoreOpcode = SystemZ::STE16;
1944 } else if (RC == &SystemZ::FP32BitRegClass) {
1945 LoadOpcode = SystemZ::LE;
1946 StoreOpcode = SystemZ::STE;
1947 } else if (RC == &SystemZ::FP64BitRegClass) {
1948 LoadOpcode = SystemZ::LD;
1949 StoreOpcode = SystemZ::STD;
1950 } else if (RC == &SystemZ::FP128BitRegClass) {
1951 LoadOpcode = SystemZ::LX;
1952 StoreOpcode = SystemZ::STX;
1953 } else if (RC == &SystemZ::FP16BitRegClass ||
1954 RC == &SystemZ::VR16BitRegClass) {
1955 LoadOpcode = SystemZ::VL16;
1956 StoreOpcode = SystemZ::VST16;
1957 } else if (RC == &SystemZ::VR32BitRegClass) {
1958 LoadOpcode = SystemZ::VL32;
1959 StoreOpcode = SystemZ::VST32;
1960 } else if (RC == &SystemZ::VR64BitRegClass) {
1961 LoadOpcode = SystemZ::VL64;
1962 StoreOpcode = SystemZ::VST64;
1963 } else if (RC == &SystemZ::VF128BitRegClass ||
1964 RC == &SystemZ::VR128BitRegClass) {
1965 LoadOpcode = SystemZ::VL;
1966 StoreOpcode = SystemZ::VST;
1967 } else
1968 llvm_unreachable("Unsupported regclass to load or store");
1969}
1970
1971unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
1972 int64_t Offset,
1973 const MachineInstr *MI) const {
1974 const MCInstrDesc &MCID = get(Opcode);
1975 int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset);
1976 if (isUInt<12>(x: Offset) && isUInt<12>(x: Offset2)) {
1977 // Get the instruction to use for unsigned 12-bit displacements.
1978 int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
1979 if (Disp12Opcode >= 0)
1980 return Disp12Opcode;
1981
1982 // All address-related instructions can use unsigned 12-bit
1983 // displacements.
1984 return Opcode;
1985 }
1986 if (isInt<20>(x: Offset) && isInt<20>(x: Offset2)) {
1987 // Get the instruction to use for signed 20-bit displacements.
1988 int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
1989 if (Disp20Opcode >= 0)
1990 return Disp20Opcode;
1991
1992 // Check whether Opcode allows signed 20-bit displacements.
1993 if (MCID.TSFlags & SystemZII::Has20BitOffset)
1994 return Opcode;
1995
1996 // If a VR32/VR64 reg ended up in an FP register, use the FP opcode.
1997 if (MI && MI->getOperand(i: 0).isReg()) {
1998 Register Reg = MI->getOperand(i: 0).getReg();
1999 if (Reg.isPhysical() && SystemZMC::getFirstReg(Reg) < 16) {
2000 switch (Opcode) {
2001 case SystemZ::VL32:
2002 return SystemZ::LEY;
2003 case SystemZ::VST32:
2004 return SystemZ::STEY;
2005 case SystemZ::VL64:
2006 return SystemZ::LDY;
2007 case SystemZ::VST64:
2008 return SystemZ::STDY;
2009 default: break;
2010 }
2011 }
2012 }
2013 }
2014 return 0;
2015}
2016
2017bool SystemZInstrInfo::hasDisplacementPairInsn(unsigned Opcode) const {
2018 const MCInstrDesc &MCID = get(Opcode);
2019 if (MCID.TSFlags & SystemZII::Has20BitOffset)
2020 return SystemZ::getDisp12Opcode(Opcode) >= 0;
2021 return SystemZ::getDisp20Opcode(Opcode) >= 0;
2022}
2023
2024unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const {
2025 switch (Opcode) {
2026 case SystemZ::L: return SystemZ::LT;
2027 case SystemZ::LY: return SystemZ::LT;
2028 case SystemZ::LG: return SystemZ::LTG;
2029 case SystemZ::LGF: return SystemZ::LTGF;
2030 case SystemZ::LR: return SystemZ::LTR;
2031 case SystemZ::LGFR: return SystemZ::LTGFR;
2032 case SystemZ::LGR: return SystemZ::LTGR;
2033 case SystemZ::LCDFR: return SystemZ::LCDBR;
2034 case SystemZ::LPDFR: return SystemZ::LPDBR;
2035 case SystemZ::LNDFR: return SystemZ::LNDBR;
2036 case SystemZ::LCDFR_32: return SystemZ::LCEBR;
2037 case SystemZ::LPDFR_32: return SystemZ::LPEBR;
2038 case SystemZ::LNDFR_32: return SystemZ::LNEBR;
2039 // On zEC12 we prefer to use RISBGN. But if there is a chance to
2040 // actually use the condition code, we may turn it back into RISGB.
2041 // Note that RISBG is not really a "load-and-test" instruction,
2042 // but sets the same condition code values, so is OK to use here.
2043 case SystemZ::RISBGN: return SystemZ::RISBG;
2044 default: return 0;
2045 }
2046}
2047
2048bool SystemZInstrInfo::isRxSBGMask(uint64_t Mask, unsigned BitSize,
2049 unsigned &Start, unsigned &End) const {
2050 // Reject trivial all-zero masks.
2051 Mask &= allOnes(Count: BitSize);
2052 if (Mask == 0)
2053 return false;
2054
2055 // Handle the 1+0+ or 0+1+0* cases. Start then specifies the index of
2056 // the msb and End specifies the index of the lsb.
2057 unsigned LSB, Length;
2058 if (isShiftedMask_64(Value: Mask, MaskIdx&: LSB, MaskLen&: Length)) {
2059 Start = 63 - (LSB + Length - 1);
2060 End = 63 - LSB;
2061 return true;
2062 }
2063
2064 // Handle the wrap-around 1+0+1+ cases. Start then specifies the msb
2065 // of the low 1s and End specifies the lsb of the high 1s.
2066 if (isShiftedMask_64(Value: Mask ^ allOnes(Count: BitSize), MaskIdx&: LSB, MaskLen&: Length)) {
2067 assert(LSB > 0 && "Bottom bit must be set");
2068 assert(LSB + Length < BitSize && "Top bit must be set");
2069 Start = 63 - (LSB - 1);
2070 End = 63 - (LSB + Length);
2071 return true;
2072 }
2073
2074 return false;
2075}
2076
2077unsigned SystemZInstrInfo::getFusedCompare(unsigned Opcode,
2078 SystemZII::FusedCompareType Type,
2079 const MachineInstr *MI) const {
2080 switch (Opcode) {
2081 case SystemZ::CHI:
2082 case SystemZ::CGHI:
2083 if (!(MI && isInt<8>(x: MI->getOperand(i: 1).getImm())))
2084 return 0;
2085 break;
2086 case SystemZ::CLFI:
2087 case SystemZ::CLGFI:
2088 if (!(MI && isUInt<8>(x: MI->getOperand(i: 1).getImm())))
2089 return 0;
2090 break;
2091 case SystemZ::CL:
2092 case SystemZ::CLG:
2093 if (!STI.hasMiscellaneousExtensions())
2094 return 0;
2095 if (!(MI && MI->getOperand(i: 3).getReg() == 0))
2096 return 0;
2097 break;
2098 }
2099 switch (Type) {
2100 case SystemZII::CompareAndBranch:
2101 switch (Opcode) {
2102 case SystemZ::CR:
2103 return SystemZ::CRJ;
2104 case SystemZ::CGR:
2105 return SystemZ::CGRJ;
2106 case SystemZ::CHI:
2107 return SystemZ::CIJ;
2108 case SystemZ::CGHI:
2109 return SystemZ::CGIJ;
2110 case SystemZ::CLR:
2111 return SystemZ::CLRJ;
2112 case SystemZ::CLGR:
2113 return SystemZ::CLGRJ;
2114 case SystemZ::CLFI:
2115 return SystemZ::CLIJ;
2116 case SystemZ::CLGFI:
2117 return SystemZ::CLGIJ;
2118 default:
2119 return 0;
2120 }
2121 case SystemZII::CompareAndReturn:
2122 switch (Opcode) {
2123 case SystemZ::CR:
2124 return SystemZ::CRBReturn;
2125 case SystemZ::CGR:
2126 return SystemZ::CGRBReturn;
2127 case SystemZ::CHI:
2128 return SystemZ::CIBReturn;
2129 case SystemZ::CGHI:
2130 return SystemZ::CGIBReturn;
2131 case SystemZ::CLR:
2132 return SystemZ::CLRBReturn;
2133 case SystemZ::CLGR:
2134 return SystemZ::CLGRBReturn;
2135 case SystemZ::CLFI:
2136 return SystemZ::CLIBReturn;
2137 case SystemZ::CLGFI:
2138 return SystemZ::CLGIBReturn;
2139 default:
2140 return 0;
2141 }
2142 case SystemZII::CompareAndSibcall:
2143 switch (Opcode) {
2144 case SystemZ::CR:
2145 return SystemZ::CRBCall;
2146 case SystemZ::CGR:
2147 return SystemZ::CGRBCall;
2148 case SystemZ::CHI:
2149 return SystemZ::CIBCall;
2150 case SystemZ::CGHI:
2151 return SystemZ::CGIBCall;
2152 case SystemZ::CLR:
2153 return SystemZ::CLRBCall;
2154 case SystemZ::CLGR:
2155 return SystemZ::CLGRBCall;
2156 case SystemZ::CLFI:
2157 return SystemZ::CLIBCall;
2158 case SystemZ::CLGFI:
2159 return SystemZ::CLGIBCall;
2160 default:
2161 return 0;
2162 }
2163 case SystemZII::CompareAndTrap:
2164 switch (Opcode) {
2165 case SystemZ::CR:
2166 return SystemZ::CRT;
2167 case SystemZ::CGR:
2168 return SystemZ::CGRT;
2169 case SystemZ::CHI:
2170 return SystemZ::CIT;
2171 case SystemZ::CGHI:
2172 return SystemZ::CGIT;
2173 case SystemZ::CLR:
2174 return SystemZ::CLRT;
2175 case SystemZ::CLGR:
2176 return SystemZ::CLGRT;
2177 case SystemZ::CLFI:
2178 return SystemZ::CLFIT;
2179 case SystemZ::CLGFI:
2180 return SystemZ::CLGIT;
2181 case SystemZ::CL:
2182 return SystemZ::CLT;
2183 case SystemZ::CLG:
2184 return SystemZ::CLGT;
2185 default:
2186 return 0;
2187 }
2188 }
2189 return 0;
2190}
2191
2192bool SystemZInstrInfo::isLoadAndTestAsCmp(const MachineInstr &MI) const {
2193 // If we during isel used a load-and-test as a compare with 0, the
2194 // def operand is dead.
2195 return (MI.getOpcode() == SystemZ::LTEBR ||
2196 MI.getOpcode() == SystemZ::LTDBR ||
2197 MI.getOpcode() == SystemZ::LTXBR) &&
2198 MI.getOperand(i: 0).isDead();
2199}
2200
2201bool SystemZInstrInfo::isCompareZero(const MachineInstr &Compare) const {
2202 if (isLoadAndTestAsCmp(MI: Compare))
2203 return true;
2204 return Compare.isCompare() && Compare.getNumExplicitOperands() == 2 &&
2205 Compare.getOperand(i: 1).isImm() && Compare.getOperand(i: 1).getImm() == 0;
2206}
2207
2208Register
2209SystemZInstrInfo::getCompareSourceReg(const MachineInstr &Compare) const {
2210 assert(isCompareZero(Compare) && "Expected a compare with 0.");
2211 return Compare.getOperand(i: isLoadAndTestAsCmp(MI: Compare) ? 1 : 0).getReg();
2212}
2213
2214bool SystemZInstrInfo::
2215prepareCompareSwapOperands(MachineBasicBlock::iterator const MBBI) const {
2216 assert(MBBI->isCompare() && MBBI->getOperand(0).isReg() &&
2217 MBBI->getOperand(1).isReg() && !MBBI->mayLoad() &&
2218 "Not a compare reg/reg.");
2219
2220 MachineBasicBlock *MBB = MBBI->getParent();
2221 bool CCLive = true;
2222 SmallVector<MachineInstr *, 4> CCUsers;
2223 for (MachineInstr &MI : llvm::make_range(x: std::next(x: MBBI), y: MBB->end())) {
2224 if (MI.readsRegister(Reg: SystemZ::CC, /*TRI=*/nullptr)) {
2225 unsigned Flags = MI.getDesc().TSFlags;
2226 if ((Flags & SystemZII::CCMaskFirst) || (Flags & SystemZII::CCMaskLast))
2227 CCUsers.push_back(Elt: &MI);
2228 else
2229 return false;
2230 }
2231 if (MI.definesRegister(Reg: SystemZ::CC, /*TRI=*/nullptr)) {
2232 CCLive = false;
2233 break;
2234 }
2235 }
2236 if (CCLive) {
2237 LiveRegUnits LiveRegs(*MBB->getParent()->getSubtarget().getRegisterInfo());
2238 LiveRegs.addLiveOuts(MBB: *MBB);
2239 if (!LiveRegs.available(Reg: SystemZ::CC))
2240 return false;
2241 }
2242
2243 // Update all CC users.
2244 for (unsigned Idx = 0; Idx < CCUsers.size(); ++Idx) {
2245 unsigned Flags = CCUsers[Idx]->getDesc().TSFlags;
2246 unsigned FirstOpNum = ((Flags & SystemZII::CCMaskFirst) ?
2247 0 : CCUsers[Idx]->getNumExplicitOperands() - 2);
2248 MachineOperand &CCMaskMO = CCUsers[Idx]->getOperand(i: FirstOpNum + 1);
2249 unsigned NewCCMask = SystemZ::reverseCCMask(CCMask: CCMaskMO.getImm());
2250 CCMaskMO.setImm(NewCCMask);
2251 }
2252
2253 return true;
2254}
2255
2256unsigned SystemZ::reverseCCMask(unsigned CCMask) {
2257 return ((CCMask & SystemZ::CCMASK_CMP_EQ) |
2258 ((CCMask & SystemZ::CCMASK_CMP_GT) ? SystemZ::CCMASK_CMP_LT : 0) |
2259 ((CCMask & SystemZ::CCMASK_CMP_LT) ? SystemZ::CCMASK_CMP_GT : 0) |
2260 (CCMask & SystemZ::CCMASK_CMP_UO));
2261}
2262
2263MachineBasicBlock *SystemZ::emitBlockAfter(MachineBasicBlock *MBB) {
2264 MachineFunction &MF = *MBB->getParent();
2265 MachineBasicBlock *NewMBB = MF.CreateMachineBasicBlock(BB: MBB->getBasicBlock());
2266 MF.insert(MBBI: std::next(x: MachineFunction::iterator(MBB)), MBB: NewMBB);
2267 return NewMBB;
2268}
2269
2270MachineBasicBlock *SystemZ::splitBlockAfter(MachineBasicBlock::iterator MI,
2271 MachineBasicBlock *MBB) {
2272 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
2273 NewMBB->splice(Where: NewMBB->begin(), Other: MBB,
2274 From: std::next(x: MachineBasicBlock::iterator(MI)), To: MBB->end());
2275 NewMBB->transferSuccessorsAndUpdatePHIs(FromMBB: MBB);
2276 return NewMBB;
2277}
2278
2279MachineBasicBlock *SystemZ::splitBlockBefore(MachineBasicBlock::iterator MI,
2280 MachineBasicBlock *MBB) {
2281 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
2282 NewMBB->splice(Where: NewMBB->begin(), Other: MBB, From: MI, To: MBB->end());
2283 NewMBB->transferSuccessorsAndUpdatePHIs(FromMBB: MBB);
2284 return NewMBB;
2285}
2286
2287unsigned SystemZInstrInfo::getLoadAndTrap(unsigned Opcode) const {
2288 if (!STI.hasLoadAndTrap())
2289 return 0;
2290 switch (Opcode) {
2291 case SystemZ::L:
2292 case SystemZ::LY:
2293 return SystemZ::LAT;
2294 case SystemZ::LG:
2295 return SystemZ::LGAT;
2296 case SystemZ::LFH:
2297 return SystemZ::LFHAT;
2298 case SystemZ::LLGF:
2299 return SystemZ::LLGFAT;
2300 case SystemZ::LLGT:
2301 return SystemZ::LLGTAT;
2302 }
2303 return 0;
2304}
2305
2306void SystemZInstrInfo::loadImmediate(MachineBasicBlock &MBB,
2307 MachineBasicBlock::iterator MBBI,
2308 unsigned Reg, uint64_t Value) const {
2309 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
2310 unsigned Opcode = 0;
2311 if (isInt<16>(x: Value))
2312 Opcode = SystemZ::LGHI;
2313 else if (SystemZ::isImmLL(Val: Value))
2314 Opcode = SystemZ::LLILL;
2315 else if (SystemZ::isImmLH(Val: Value)) {
2316 Opcode = SystemZ::LLILH;
2317 Value >>= 16;
2318 }
2319 else if (isInt<32>(x: Value))
2320 Opcode = SystemZ::LGFI;
2321 if (Opcode) {
2322 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode), DestReg: Reg).addImm(Val: Value);
2323 return;
2324 }
2325
2326 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2327 assert (MRI.isSSA() && "Huge values only handled before reg-alloc .");
2328 Register Reg0 = MRI.createVirtualRegister(RegClass: &SystemZ::GR64BitRegClass);
2329 Register Reg1 = MRI.createVirtualRegister(RegClass: &SystemZ::GR64BitRegClass);
2330 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: SystemZ::IMPLICIT_DEF), DestReg: Reg0);
2331 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: SystemZ::IIHF64), DestReg: Reg1)
2332 .addReg(RegNo: Reg0).addImm(Val: Value >> 32);
2333 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: SystemZ::IILF64), DestReg: Reg)
2334 .addReg(RegNo: Reg1).addImm(Val: Value & ((uint64_t(1) << 32) - 1));
2335}
2336
2337bool SystemZInstrInfo::verifyInstruction(const MachineInstr &MI,
2338 StringRef &ErrInfo) const {
2339 const MCInstrDesc &MCID = MI.getDesc();
2340 for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
2341 if (I >= MCID.getNumOperands())
2342 break;
2343 const MachineOperand &Op = MI.getOperand(i: I);
2344 const MCOperandInfo &MCOI = MCID.operands()[I];
2345 // Addressing modes have register and immediate operands. Op should be a
2346 // register (or frame index) operand if MCOI.RegClass contains a valid
2347 // register class, or an immediate otherwise.
2348 if (MCOI.OperandType == MCOI::OPERAND_MEMORY &&
2349 ((MCOI.RegClass != -1 && !Op.isReg() && !Op.isFI()) ||
2350 (MCOI.RegClass == -1 && !Op.isImm()))) {
2351 ErrInfo = "Addressing mode operands corrupt!";
2352 return false;
2353 }
2354 }
2355
2356 return true;
2357}
2358
2359bool SystemZInstrInfo::
2360areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
2361 const MachineInstr &MIb) const {
2362
2363 if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand())
2364 return false;
2365
2366 // If mem-operands show that the same address Value is used by both
2367 // instructions, check for non-overlapping offsets and widths. Not
2368 // sure if a register based analysis would be an improvement...
2369
2370 MachineMemOperand *MMOa = *MIa.memoperands_begin();
2371 MachineMemOperand *MMOb = *MIb.memoperands_begin();
2372 const Value *VALa = MMOa->getValue();
2373 const Value *VALb = MMOb->getValue();
2374 bool SameVal = (VALa && VALb && (VALa == VALb));
2375 if (!SameVal) {
2376 const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
2377 const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
2378 if (PSVa && PSVb && (PSVa == PSVb))
2379 SameVal = true;
2380 }
2381 if (SameVal) {
2382 int OffsetA = MMOa->getOffset(), OffsetB = MMOb->getOffset();
2383 LocationSize WidthA = MMOa->getSize(), WidthB = MMOb->getSize();
2384 int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;
2385 int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;
2386 LocationSize LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
2387 if (LowWidth.hasValue() &&
2388 LowOffset + (int)LowWidth.getValue() <= HighOffset)
2389 return true;
2390 }
2391
2392 return false;
2393}
2394
2395bool SystemZInstrInfo::getConstValDefinedInReg(const MachineInstr &MI,
2396 const Register Reg,
2397 int64_t &ImmVal) const {
2398
2399 if (MI.getOpcode() == SystemZ::VGBM && Reg == MI.getOperand(i: 0).getReg()) {
2400 ImmVal = MI.getOperand(i: 1).getImm();
2401 // TODO: Handle non-0 values
2402 return ImmVal == 0;
2403 }
2404
2405 return false;
2406}
2407
2408std::optional<DestSourcePair>
2409SystemZInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
2410 // if MI is a simple single-register copy operation, return operand pair
2411 if (MI.isMoveReg())
2412 return DestSourcePair(MI.getOperand(i: 0), MI.getOperand(i: 1));
2413
2414 return std::nullopt;
2415}
2416
2417std::pair<unsigned, unsigned>
2418SystemZInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
2419 return std::make_pair(x&: TF, y: 0u);
2420}
2421
2422ArrayRef<std::pair<unsigned, const char *>>
2423SystemZInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
2424 using namespace SystemZII;
2425
2426 static const std::pair<unsigned, const char *> TargetFlags[] = {
2427 {MO_GOT, "systemz-got"},
2428 {MO_INDNTPOFF, "systemz-indntpoff"},
2429 {MO_ADA_DATA_SYMBOL_ADDR, "systemz-ada-datasymboladdr"},
2430 {MO_ADA_INDIRECT_FUNC_DESC, "systemz-ada-indirectfuncdesc"},
2431 {MO_ADA_DIRECT_FUNC_DESC, "systemz-ada-directfuncdesc"}};
2432 return ArrayRef(TargetFlags);
2433}
2434
2435MCInst SystemZInstrInfo::getNop() const {
2436 return MCInstBuilder(SystemZ::NOPR).addReg(Reg: 0);
2437}
2438