1//=- WebAssemblyISelLowering.cpp - WebAssembly DAG Lowering Implementation -==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file implements the WebAssemblyTargetLowering class.
11///
12//===----------------------------------------------------------------------===//
13
14#include "WebAssemblyISelLowering.h"
15#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
16#include "Utils/WebAssemblyTypeUtilities.h"
17#include "WebAssemblyMachineFunctionInfo.h"
18#include "WebAssemblySubtarget.h"
19#include "WebAssemblyTargetMachine.h"
20#include "WebAssemblyUtilities.h"
21#include "llvm/CodeGen/CallingConvLower.h"
22#include "llvm/CodeGen/MachineFrameInfo.h"
23#include "llvm/CodeGen/MachineInstrBuilder.h"
24#include "llvm/CodeGen/MachineJumpTableInfo.h"
25#include "llvm/CodeGen/MachineModuleInfo.h"
26#include "llvm/CodeGen/MachineRegisterInfo.h"
27#include "llvm/CodeGen/SDPatternMatch.h"
28#include "llvm/CodeGen/SelectionDAG.h"
29#include "llvm/CodeGen/SelectionDAGNodes.h"
30#include "llvm/IR/DiagnosticInfo.h"
31#include "llvm/IR/DiagnosticPrinter.h"
32#include "llvm/IR/Function.h"
33#include "llvm/IR/IntrinsicInst.h"
34#include "llvm/IR/Intrinsics.h"
35#include "llvm/IR/IntrinsicsWebAssembly.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/KnownBits.h"
38#include "llvm/Support/MathExtras.h"
39#include "llvm/Target/TargetOptions.h"
40using namespace llvm;
41
42#define DEBUG_TYPE "wasm-lower"
43
44WebAssemblyTargetLowering::WebAssemblyTargetLowering(
45 const TargetMachine &TM, const WebAssemblySubtarget &STI)
46 : TargetLowering(TM, STI), Subtarget(&STI) {
47 auto MVTPtr = Subtarget->hasAddr64() ? MVT::i64 : MVT::i32;
48
49 // Set the load count for memcmp expand optimization
50 MaxLoadsPerMemcmp = 8;
51 MaxLoadsPerMemcmpOptSize = 4;
52
53 // Booleans always contain 0 or 1.
54 setBooleanContents(ZeroOrOneBooleanContent);
55 // Except in SIMD vectors
56 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
57 // We don't know the microarchitecture here, so just reduce register pressure.
58 setSchedulingPreference(Sched::RegPressure);
59 // Tell ISel that we have a stack pointer.
60 setStackPointerRegisterToSaveRestore(
61 Subtarget->hasAddr64() ? WebAssembly::SP64 : WebAssembly::SP32);
62 // Set up the register classes.
63 addRegisterClass(VT: MVT::i32, RC: &WebAssembly::I32RegClass);
64 addRegisterClass(VT: MVT::i64, RC: &WebAssembly::I64RegClass);
65 addRegisterClass(VT: MVT::f32, RC: &WebAssembly::F32RegClass);
66 addRegisterClass(VT: MVT::f64, RC: &WebAssembly::F64RegClass);
67 if (Subtarget->hasSIMD128()) {
68 addRegisterClass(VT: MVT::v16i8, RC: &WebAssembly::V128RegClass);
69 addRegisterClass(VT: MVT::v8i16, RC: &WebAssembly::V128RegClass);
70 addRegisterClass(VT: MVT::v4i32, RC: &WebAssembly::V128RegClass);
71 addRegisterClass(VT: MVT::v4f32, RC: &WebAssembly::V128RegClass);
72 addRegisterClass(VT: MVT::v2i64, RC: &WebAssembly::V128RegClass);
73 addRegisterClass(VT: MVT::v2f64, RC: &WebAssembly::V128RegClass);
74 }
75 if (Subtarget->hasFP16()) {
76 addRegisterClass(VT: MVT::v8f16, RC: &WebAssembly::V128RegClass);
77 }
78 if (Subtarget->hasReferenceTypes()) {
79 addRegisterClass(VT: MVT::externref, RC: &WebAssembly::EXTERNREFRegClass);
80 addRegisterClass(VT: MVT::funcref, RC: &WebAssembly::FUNCREFRegClass);
81 if (Subtarget->hasExceptionHandling()) {
82 addRegisterClass(VT: MVT::exnref, RC: &WebAssembly::EXNREFRegClass);
83 }
84 }
85 // Compute derived properties from the register classes.
86 computeRegisterProperties(TRI: Subtarget->getRegisterInfo());
87
88 // Transform loads and stores to pointers in address space 1 to loads and
89 // stores to WebAssembly global variables, outside linear memory.
90 for (auto T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64}) {
91 setOperationAction(Op: ISD::LOAD, VT: T, Action: Custom);
92 setOperationAction(Op: ISD::STORE, VT: T, Action: Custom);
93 }
94 if (Subtarget->hasSIMD128()) {
95 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
96 MVT::v2f64}) {
97 setOperationAction(Op: ISD::LOAD, VT: T, Action: Custom);
98 setOperationAction(Op: ISD::STORE, VT: T, Action: Custom);
99 }
100 }
101 if (Subtarget->hasFP16()) {
102 setOperationAction(Op: ISD::LOAD, VT: MVT::v8f16, Action: Custom);
103 setOperationAction(Op: ISD::STORE, VT: MVT::v8f16, Action: Custom);
104 }
105 if (Subtarget->hasReferenceTypes()) {
106 // We need custom load and store lowering for both externref, funcref and
107 // Other. The MVT::Other here represents tables of reference types.
108 for (auto T : {MVT::externref, MVT::funcref, MVT::Other}) {
109 setOperationAction(Op: ISD::LOAD, VT: T, Action: Custom);
110 setOperationAction(Op: ISD::STORE, VT: T, Action: Custom);
111 }
112 }
113
114 setOperationAction(Op: ISD::GlobalAddress, VT: MVTPtr, Action: Custom);
115 setOperationAction(Op: ISD::GlobalTLSAddress, VT: MVTPtr, Action: Custom);
116 setOperationAction(Op: ISD::ExternalSymbol, VT: MVTPtr, Action: Custom);
117 setOperationAction(Op: ISD::JumpTable, VT: MVTPtr, Action: Custom);
118 setOperationAction(Op: ISD::BlockAddress, VT: MVTPtr, Action: Custom);
119 setOperationAction(Op: ISD::BRIND, VT: MVT::Other, Action: Custom);
120 setOperationAction(Op: ISD::CLEAR_CACHE, VT: MVT::Other, Action: Custom);
121
122 // Take the default expansion for va_arg, va_copy, and va_end. There is no
123 // default action for va_start, so we do that custom.
124 setOperationAction(Op: ISD::VASTART, VT: MVT::Other, Action: Custom);
125 setOperationAction(Op: ISD::VAARG, VT: MVT::Other, Action: Expand);
126 setOperationAction(Op: ISD::VACOPY, VT: MVT::Other, Action: Expand);
127 setOperationAction(Op: ISD::VAEND, VT: MVT::Other, Action: Expand);
128
129 for (auto T : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64, MVT::v8f16}) {
130 if (!Subtarget->hasFP16() && T == MVT::v8f16) {
131 continue;
132 }
133 // Don't expand the floating-point types to constant pools.
134 setOperationAction(Op: ISD::ConstantFP, VT: T, Action: Legal);
135 // Expand floating-point comparisons.
136 for (auto CC : {ISD::SETO, ISD::SETUO, ISD::SETUEQ, ISD::SETONE,
137 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE})
138 setCondCodeAction(CCs: CC, VT: T, Action: Expand);
139 // Expand floating-point library function operators.
140 for (auto Op : {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FMA})
141 setOperationAction(Op, VT: T, Action: Expand);
142 // Expand vector FREM, but use a libcall rather than an expansion for scalar
143 if (MVT(T).isVector())
144 setOperationAction(Op: ISD::FREM, VT: T, Action: Expand);
145 else
146 setOperationAction(Op: ISD::FREM, VT: T, Action: LibCall);
147 // Note supported floating-point library function operators that otherwise
148 // default to expand.
149 for (auto Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT,
150 ISD::FRINT, ISD::FROUNDEVEN})
151 setOperationAction(Op, VT: T, Action: Legal);
152 // Support minimum and maximum, which otherwise default to expand.
153 setOperationAction(Op: ISD::FMINIMUM, VT: T, Action: Legal);
154 setOperationAction(Op: ISD::FMAXIMUM, VT: T, Action: Legal);
155 if (Subtarget->hasSIMD128() && MVT(T).isVector()) {
156 setOperationAction(Op: ISD::PSEUDO_FMIN, VT: T, Action: Legal);
157 setOperationAction(Op: ISD::PSEUDO_FMAX, VT: T, Action: Legal);
158 }
159 // When experimental v8f16 support is enabled these instructions don't need
160 // to be expanded.
161 if (T != MVT::v8f16) {
162 setOperationAction(Op: ISD::FP16_TO_FP, VT: T, Action: Expand);
163 setOperationAction(Op: ISD::FP_TO_FP16, VT: T, Action: Expand);
164 }
165 if (Subtarget->hasFP16() && T == MVT::f32) {
166 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: T, MemVT: MVT::f16, Action: Legal);
167 setTruncStoreAction(ValVT: T, MemVT: MVT::f16, Action: Legal);
168 } else {
169 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: T, MemVT: MVT::f16, Action: Expand);
170 setTruncStoreAction(ValVT: T, MemVT: MVT::f16, Action: Expand);
171 }
172 }
173
174 // Expand unavailable integer operations.
175 for (auto Op :
176 {ISD::BSWAP, ISD::SMUL_LOHI, ISD::UMUL_LOHI, ISD::MULHS, ISD::MULHU,
177 ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS, ISD::SRA_PARTS,
178 ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) {
179 for (auto T : {MVT::i32, MVT::i64})
180 setOperationAction(Op, VT: T, Action: Expand);
181 if (Subtarget->hasSIMD128())
182 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
183 setOperationAction(Op, VT: T, Action: Expand);
184 }
185
186 if (Subtarget->hasWideArithmetic()) {
187 setOperationAction(Op: ISD::ADD, VT: MVT::i128, Action: Custom);
188 setOperationAction(Op: ISD::SUB, VT: MVT::i128, Action: Custom);
189 setOperationAction(Op: ISD::SMUL_LOHI, VT: MVT::i64, Action: Custom);
190 setOperationAction(Op: ISD::UMUL_LOHI, VT: MVT::i64, Action: Custom);
191 setOperationAction(Op: ISD::UADDO, VT: MVT::i64, Action: Custom);
192 }
193
194 if (Subtarget->hasNontrappingFPToInt())
195 for (auto Op : {ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT})
196 for (auto T : {MVT::i32, MVT::i64})
197 setOperationAction(Op, VT: T, Action: Custom);
198
199 if (Subtarget->hasRelaxedSIMD()) {
200 setOperationAction(
201 Ops: {ISD::FMINNUM, ISD::FMINIMUMNUM, ISD::FMAXNUM, ISD::FMAXIMUMNUM},
202 VTs: {MVT::v4f32, MVT::v2f64}, Action: Custom);
203 }
204
205 // Combine expands these operations, because wasi-libc and emscripten do not
206 // yet have the dedicated libcalls.
207 setTargetDAGCombine(
208 {ISD::FMINIMUM, ISD::FMAXIMUM, ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM});
209
210 // SIMD-specific configuration
211 if (Subtarget->hasSIMD128()) {
212
213 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
214
215 // Combine wide-vector muls, with extend inputs, to extmul_half.
216 setTargetDAGCombine(ISD::MUL);
217 setTargetDAGCombine(ISD::SHL);
218
219 // Combine vector mask reductions into alltrue/anytrue
220 setTargetDAGCombine(ISD::SETCC);
221
222 // Convert vector to integer bitcasts to bitmask
223 setTargetDAGCombine(ISD::BITCAST);
224
225 // Hoist bitcasts out of shuffles
226 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
227
228 // Combine extends of extract_subvectors into widening ops
229 setTargetDAGCombine({ISD::SIGN_EXTEND, ISD::ZERO_EXTEND});
230
231 // Combine int_to_fp or fp_extend of extract_vectors and vice versa into
232 // conversions ops
233 setTargetDAGCombine({ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_EXTEND,
234 ISD::EXTRACT_SUBVECTOR});
235
236 // Combine fp_to_{s,u}int_sat or fp_round of concat_vectors or vice versa
237 // into conversion ops
238 setTargetDAGCombine({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT,
239 ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::FP_ROUND,
240 ISD::CONCAT_VECTORS});
241
242 setTargetDAGCombine(ISD::TRUNCATE);
243
244 // Support saturating add/sub for i8x16 and i16x8
245 for (auto Op : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT})
246 for (auto T : {MVT::v16i8, MVT::v8i16})
247 setOperationAction(Op, VT: T, Action: Legal);
248
249 // Support integer abs
250 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
251 setOperationAction(Op: ISD::ABS, VT: T, Action: Legal);
252
253 // Custom lower BUILD_VECTORs to minimize number of replace_lanes
254 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
255 MVT::v2f64})
256 setOperationAction(Op: ISD::BUILD_VECTOR, VT: T, Action: Custom);
257
258 if (Subtarget->hasFP16()) {
259 setOperationAction(Op: ISD::BUILD_VECTOR, VT: MVT::f16, Action: Custom);
260 setOperationAction(Op: ISD::INSERT_VECTOR_ELT, VT: MVT::f16, Action: Custom);
261 setOperationAction(Op: ISD::FP_ROUND, VT: MVT::v4f16, Action: Custom);
262 }
263
264 // We have custom shuffle lowering to expose the shuffle mask
265 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
266 MVT::v2f64})
267 setOperationAction(Op: ISD::VECTOR_SHUFFLE, VT: T, Action: Custom);
268
269 if (Subtarget->hasFP16())
270 setOperationAction(Op: ISD::VECTOR_SHUFFLE, VT: MVT::v8f16, Action: Custom);
271
272 // Support splatting
273 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
274 MVT::v2f64})
275 setOperationAction(Op: ISD::SPLAT_VECTOR, VT: T, Action: Legal);
276
277 setOperationAction(Ops: ISD::AVGCEILU, VTs: {MVT::v8i16, MVT::v16i8}, Action: Legal);
278
279 // Custom lowering since wasm shifts must have a scalar shift amount
280 for (auto Op : {ISD::SHL, ISD::SRA, ISD::SRL})
281 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
282 setOperationAction(Op, VT: T, Action: Custom);
283
284 // Custom lower lane accesses to expand out variable indices
285 for (auto Op : {ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT})
286 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
287 MVT::v2f64})
288 setOperationAction(Op, VT: T, Action: Custom);
289
290 // There is no i8x16.mul instruction
291 setOperationAction(Op: ISD::MUL, VT: MVT::v16i8, Action: Expand);
292
293 // Expand integer operations supported for scalars but not SIMD
294 for (auto Op :
295 {ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM, ISD::ROTL, ISD::ROTR})
296 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
297 setOperationAction(Op, VT: T, Action: Expand);
298
299 // But we do have integer min and max operations
300 for (auto Op : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
301 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32})
302 setOperationAction(Op, VT: T, Action: Legal);
303
304 // And we have popcnt for i8x16. It can be used to expand ctlz/cttz.
305 setOperationAction(Op: ISD::CTPOP, VT: MVT::v16i8, Action: Legal);
306 setOperationAction(Op: ISD::CTLZ, VT: MVT::v16i8, Action: Expand);
307 setOperationAction(Op: ISD::CTTZ, VT: MVT::v16i8, Action: Expand);
308
309 // Custom lower bit counting operations for other types to scalarize them.
310 for (auto Op : {ISD::CTLZ, ISD::CTTZ, ISD::CTPOP})
311 for (auto T : {MVT::v8i16, MVT::v4i32, MVT::v2i64})
312 setOperationAction(Op, VT: T, Action: Custom);
313
314 // Expand float operations supported for scalars but not SIMD
315 for (auto Op : {ISD::FCOPYSIGN, ISD::FLOG, ISD::FLOG2, ISD::FLOG10,
316 ISD::FEXP, ISD::FEXP2, ISD::FEXP10})
317 for (auto T : {MVT::v4f32, MVT::v2f64})
318 setOperationAction(Op, VT: T, Action: Expand);
319
320 // Unsigned comparison operations are unavailable for i64x2 vectors.
321 for (auto CC : {ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE})
322 setCondCodeAction(CCs: CC, VT: MVT::v2i64, Action: Custom);
323
324 // 64x2 conversions are not in the spec
325 for (auto Op :
326 {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT})
327 for (auto T : {MVT::v2i64, MVT::v2f64})
328 setOperationAction(Op, VT: T, Action: Expand);
329
330 // But saturating fp_to_int conversions are
331 for (auto Op : {ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}) {
332 setOperationAction(Op, VT: MVT::v4i32, Action: Custom);
333 if (Subtarget->hasFP16()) {
334 setOperationAction(Op, VT: MVT::v8i16, Action: Custom);
335 }
336 }
337
338 // Support vector extending
339 for (auto T : MVT::integer_fixedlen_vector_valuetypes()) {
340 setOperationAction(Op: ISD::ANY_EXTEND_VECTOR_INREG, VT: T, Action: Custom);
341 setOperationAction(Op: ISD::SIGN_EXTEND_VECTOR_INREG, VT: T, Action: Custom);
342 setOperationAction(Op: ISD::ZERO_EXTEND_VECTOR_INREG, VT: T, Action: Custom);
343 }
344
345 if (Subtarget->hasFP16()) {
346 setOperationAction(Op: ISD::FMA, VT: MVT::v8f16, Action: Legal);
347 }
348
349 if (Subtarget->hasRelaxedSIMD()) {
350 setOperationAction(Op: ISD::FMULADD, VT: MVT::v4f32, Action: Legal);
351 setOperationAction(Op: ISD::FMULADD, VT: MVT::v2f64, Action: Legal);
352 }
353
354 // Partial MLA reductions.
355 for (auto Op : {ISD::PARTIAL_REDUCE_SMLA, ISD::PARTIAL_REDUCE_UMLA}) {
356 setPartialReduceMLAAction(Opc: Op, AccVT: MVT::v4i32, InputVT: MVT::v16i8, Action: Legal);
357 setPartialReduceMLAAction(Opc: Op, AccVT: MVT::v4i32, InputVT: MVT::v8i16, Action: Legal);
358 }
359 }
360
361 // As a special case, these operators use the type to mean the type to
362 // sign-extend from.
363 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: MVT::i1, Action: Expand);
364 if (!Subtarget->hasSignExt()) {
365 // Sign extends are legal only when extending a vector extract
366 auto Action = Subtarget->hasSIMD128() ? Custom : Expand;
367 for (auto T : {MVT::i8, MVT::i16, MVT::i32})
368 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: T, Action);
369 }
370 for (auto T : MVT::integer_fixedlen_vector_valuetypes())
371 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: T, Action: Expand);
372
373 // Dynamic stack allocation: use the default expansion.
374 setOperationAction(Op: ISD::STACKSAVE, VT: MVT::Other, Action: Expand);
375 setOperationAction(Op: ISD::STACKRESTORE, VT: MVT::Other, Action: Expand);
376 setOperationAction(Op: ISD::DYNAMIC_STACKALLOC, VT: MVTPtr, Action: Expand);
377
378 setOperationAction(Op: ISD::FrameIndex, VT: MVT::i32, Action: Custom);
379 setOperationAction(Op: ISD::FrameIndex, VT: MVT::i64, Action: Custom);
380 setOperationAction(Op: ISD::CopyToReg, VT: MVT::Other, Action: Custom);
381
382 // Expand these forms; we pattern-match the forms that we can handle in isel.
383 for (auto T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64})
384 for (auto Op : {ISD::BR_CC, ISD::SELECT_CC})
385 setOperationAction(Op, VT: T, Action: Expand);
386
387 if (Subtarget->hasReferenceTypes())
388 for (auto Op : {ISD::BR_CC, ISD::SELECT_CC})
389 for (auto T : {MVT::externref, MVT::funcref})
390 setOperationAction(Op, VT: T, Action: Expand);
391
392 // There is no vector conditional select instruction
393 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
394 MVT::v2f64, MVT::v8f16})
395 setOperationAction(Op: ISD::SELECT_CC, VT: T, Action: Expand);
396
397 // We have custom switch handling.
398 setOperationAction(Op: ISD::BR_JT, VT: MVT::Other, Action: Custom);
399
400 // WebAssembly doesn't have:
401 // - Floating-point extending loads.
402 // - Floating-point truncating stores.
403 // - i1 extending loads.
404 // - truncating SIMD stores and most extending loads
405 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: MVT::f64, MemVT: MVT::f32, Action: Expand);
406 setTruncStoreAction(ValVT: MVT::f64, MemVT: MVT::f32, Action: Expand);
407 for (auto T : MVT::integer_valuetypes())
408 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD})
409 setLoadExtAction(ExtType: Ext, ValVT: T, MemVT: MVT::i1, Action: Promote);
410 if (Subtarget->hasSIMD128()) {
411 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32,
412 MVT::v2f64}) {
413 for (auto MemT : MVT::fixedlen_vector_valuetypes()) {
414 if (MVT(T) != MemT) {
415 setTruncStoreAction(ValVT: T, MemVT: MemT, Action: Expand);
416 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD})
417 setLoadExtAction(ExtType: Ext, ValVT: T, MemVT: MemT, Action: Expand);
418 }
419 }
420 }
421 // But some vector extending loads are legal
422 for (auto Ext : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
423 setLoadExtAction(ExtType: Ext, ValVT: MVT::v8i16, MemVT: MVT::v8i8, Action: Legal);
424 setLoadExtAction(ExtType: Ext, ValVT: MVT::v4i32, MemVT: MVT::v4i16, Action: Legal);
425 setLoadExtAction(ExtType: Ext, ValVT: MVT::v2i64, MemVT: MVT::v2i32, Action: Legal);
426 }
427 setLoadExtAction(ExtType: ISD::EXTLOAD, ValVT: MVT::v2f64, MemVT: MVT::v2f32, Action: Legal);
428 }
429
430 // Don't do anything clever with build_pairs
431 setOperationAction(Op: ISD::BUILD_PAIR, VT: MVT::i64, Action: Expand);
432
433 // Trap lowers to wasm unreachable
434 setOperationAction(Op: ISD::TRAP, VT: MVT::Other, Action: Legal);
435 setOperationAction(Op: ISD::DEBUGTRAP, VT: MVT::Other, Action: Legal);
436
437 // Exception handling intrinsics
438 setOperationAction(Op: ISD::INTRINSIC_WO_CHAIN, VT: MVT::Other, Action: Custom);
439 setOperationAction(Op: ISD::INTRINSIC_W_CHAIN, VT: MVT::Other, Action: Custom);
440 setOperationAction(Op: ISD::INTRINSIC_VOID, VT: MVT::Other, Action: Custom);
441
442 setMaxAtomicSizeInBitsSupported(64);
443
444 // Always convert switches to br_tables unless there is only one case, which
445 // is equivalent to a simple branch. This reduces code size for wasm, and we
446 // defer possible jump table optimizations to the VM.
447 setMinimumJumpTableEntries(2);
448}
449
450TargetLowering::AtomicExpansionKind
451WebAssemblyTargetLowering::shouldExpandAtomicRMWInIR(
452 const AtomicRMWInst *AI) const {
453 // We have wasm instructions for these
454 switch (AI->getOperation()) {
455 case AtomicRMWInst::Add:
456 case AtomicRMWInst::Sub:
457 case AtomicRMWInst::And:
458 case AtomicRMWInst::Or:
459 case AtomicRMWInst::Xor:
460 case AtomicRMWInst::Xchg:
461 return AtomicExpansionKind::None;
462 default:
463 break;
464 }
465 return AtomicExpansionKind::CmpXChg;
466}
467
468bool WebAssemblyTargetLowering::shouldScalarizeBinop(SDValue VecOp) const {
469 // Implementation copied from X86TargetLowering.
470 unsigned Opc = VecOp.getOpcode();
471
472 // Assume target opcodes can't be scalarized.
473 // TODO - do we have any exceptions?
474 if (Opc >= ISD::BUILTIN_OP_END || !isBinOp(Opcode: Opc))
475 return false;
476
477 // If the vector op is not supported, try to convert to scalar.
478 EVT VecVT = VecOp.getValueType();
479 if (!isOperationLegalOrCustomOrPromote(Op: Opc, VT: VecVT))
480 return true;
481
482 // If the vector op is supported, but the scalar op is not, the transform may
483 // not be worthwhile.
484 EVT ScalarVT = VecVT.getScalarType();
485 return isOperationLegalOrCustomOrPromote(Op: Opc, VT: ScalarVT);
486}
487
488FastISel *WebAssemblyTargetLowering::createFastISel(
489 FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo,
490 const LibcallLoweringInfo *LibcallLowering) const {
491 return WebAssembly::createFastISel(funcInfo&: FuncInfo, libInfo: LibInfo, libcallLowering: LibcallLowering);
492}
493
494MVT WebAssemblyTargetLowering::getScalarShiftAmountTy(const DataLayout & /*DL*/,
495 EVT VT) const {
496 unsigned BitWidth = NextPowerOf2(A: VT.getSizeInBits() - 1);
497 if (BitWidth > 1 && BitWidth < 8)
498 BitWidth = 8;
499
500 if (BitWidth > 64) {
501 // The shift will be lowered to a libcall, and compiler-rt libcalls expect
502 // the count to be an i32.
503 BitWidth = 32;
504 assert(BitWidth >= Log2_32_Ceil(VT.getSizeInBits()) &&
505 "32-bit shift counts ought to be enough for anyone");
506 }
507
508 MVT Result = MVT::getIntegerVT(BitWidth);
509 assert(Result != MVT::INVALID_SIMPLE_VALUE_TYPE &&
510 "Unable to represent scalar shift amount type");
511 return Result;
512}
513
514// Lower an fp-to-int conversion operator from the LLVM opcode, which has an
515// undefined result on invalid/overflow, to the WebAssembly opcode, which
516// traps on invalid/overflow.
517static MachineBasicBlock *LowerFPToInt(MachineInstr &MI, DebugLoc DL,
518 MachineBasicBlock *BB,
519 const TargetInstrInfo &TII,
520 bool IsUnsigned, bool Int64,
521 bool Float64, unsigned LoweredOpcode) {
522 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
523
524 Register OutReg = MI.getOperand(i: 0).getReg();
525 Register InReg = MI.getOperand(i: 1).getReg();
526
527 unsigned Abs = Float64 ? WebAssembly::ABS_F64 : WebAssembly::ABS_F32;
528 unsigned FConst = Float64 ? WebAssembly::CONST_F64 : WebAssembly::CONST_F32;
529 unsigned LT = Float64 ? WebAssembly::LT_F64 : WebAssembly::LT_F32;
530 unsigned GE = Float64 ? WebAssembly::GE_F64 : WebAssembly::GE_F32;
531 unsigned IConst = Int64 ? WebAssembly::CONST_I64 : WebAssembly::CONST_I32;
532 unsigned Eqz = WebAssembly::EQZ_I32;
533 unsigned And = WebAssembly::AND_I32;
534 int64_t Limit = Int64 ? INT64_MIN : INT32_MIN;
535 int64_t Substitute = IsUnsigned ? 0 : Limit;
536 double CmpVal = IsUnsigned ? -(double)Limit * 2.0 : -(double)Limit;
537 auto &Context = BB->getParent()->getFunction().getContext();
538 Type *Ty = Float64 ? Type::getDoubleTy(C&: Context) : Type::getFloatTy(C&: Context);
539
540 const BasicBlock *LLVMBB = BB->getBasicBlock();
541 MachineFunction *F = BB->getParent();
542 MachineBasicBlock *TrueMBB = F->CreateMachineBasicBlock(BB: LLVMBB);
543 MachineBasicBlock *FalseMBB = F->CreateMachineBasicBlock(BB: LLVMBB);
544 MachineBasicBlock *DoneMBB = F->CreateMachineBasicBlock(BB: LLVMBB);
545
546 MachineFunction::iterator It = ++BB->getIterator();
547 F->insert(MBBI: It, MBB: FalseMBB);
548 F->insert(MBBI: It, MBB: TrueMBB);
549 F->insert(MBBI: It, MBB: DoneMBB);
550
551 // Transfer the remainder of BB and its successor edges to DoneMBB.
552 DoneMBB->splice(Where: DoneMBB->begin(), Other: BB, From: std::next(x: MI.getIterator()), To: BB->end());
553 DoneMBB->transferSuccessorsAndUpdatePHIs(FromMBB: BB);
554
555 BB->addSuccessor(Succ: TrueMBB);
556 BB->addSuccessor(Succ: FalseMBB);
557 TrueMBB->addSuccessor(Succ: DoneMBB);
558 FalseMBB->addSuccessor(Succ: DoneMBB);
559
560 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg;
561 Tmp0 = MRI.createVirtualRegister(RegClass: MRI.getRegClass(Reg: InReg));
562 Tmp1 = MRI.createVirtualRegister(RegClass: MRI.getRegClass(Reg: InReg));
563 CmpReg = MRI.createVirtualRegister(RegClass: &WebAssembly::I32RegClass);
564 EqzReg = MRI.createVirtualRegister(RegClass: &WebAssembly::I32RegClass);
565 FalseReg = MRI.createVirtualRegister(RegClass: MRI.getRegClass(Reg: OutReg));
566 TrueReg = MRI.createVirtualRegister(RegClass: MRI.getRegClass(Reg: OutReg));
567
568 MI.eraseFromParent();
569 // For signed numbers, we can do a single comparison to determine whether
570 // fabs(x) is within range.
571 if (IsUnsigned) {
572 Tmp0 = InReg;
573 } else {
574 BuildMI(BB, MIMD: DL, MCID: TII.get(Opcode: Abs), DestReg: Tmp0).addReg(RegNo: InReg);
575 }
576 BuildMI(BB, MIMD: DL, MCID: TII.get(Opcode: FConst), DestReg: Tmp1)
577 .addFPImm(Val: cast<ConstantFP>(Val: ConstantFP::get(Ty, V: CmpVal)));
578 BuildMI(BB, MIMD: DL, MCID: TII.get(Opcode: LT), DestReg: CmpReg).addReg(RegNo: Tmp0).addReg(RegNo: Tmp1);
579
580 // For unsigned numbers, we have to do a separate comparison with zero.
581 if (IsUnsigned) {
582 Tmp1 = MRI.createVirtualRegister(RegClass: MRI.getRegClass(Reg: InReg));
583 Register SecondCmpReg =
584 MRI.createVirtualRegister(RegClass: &WebAssembly::I32RegClass);
585 Register AndReg = MRI.createVirtualRegister(RegClass: &WebAssembly::I32RegClass);
586 BuildMI(BB, MIMD: DL, MCID: TII.get(Opcode: FConst), DestReg: Tmp1)
587 .addFPImm(Val: cast<ConstantFP>(Val: ConstantFP::get(Ty, V: 0.0)));
588 BuildMI(BB, MIMD: DL, MCID: TII.get(Opcode: GE), DestReg: SecondCmpReg).addReg(RegNo: Tmp0).addReg(RegNo: Tmp1);
589 BuildMI(BB, MIMD: DL, MCID: TII.get(Opcode: And), DestReg: AndReg).addReg(RegNo: CmpReg).addReg(RegNo: SecondCmpReg);
590 CmpReg = AndReg;
591 }
592
593 BuildMI(BB, MIMD: DL, MCID: TII.get(Opcode: Eqz), DestReg: EqzReg).addReg(RegNo: CmpReg);
594
595 // Create the CFG diamond to select between doing the conversion or using
596 // the substitute value.
597 BuildMI(BB, MIMD: DL, MCID: TII.get(Opcode: WebAssembly::BR_IF)).addMBB(MBB: TrueMBB).addReg(RegNo: EqzReg);
598 BuildMI(BB: FalseMBB, MIMD: DL, MCID: TII.get(Opcode: LoweredOpcode), DestReg: FalseReg).addReg(RegNo: InReg);
599 BuildMI(BB: FalseMBB, MIMD: DL, MCID: TII.get(Opcode: WebAssembly::BR)).addMBB(MBB: DoneMBB);
600 BuildMI(BB: TrueMBB, MIMD: DL, MCID: TII.get(Opcode: IConst), DestReg: TrueReg).addImm(Val: Substitute);
601 BuildMI(BB&: *DoneMBB, I: DoneMBB->begin(), MIMD: DL, MCID: TII.get(Opcode: TargetOpcode::PHI), DestReg: OutReg)
602 .addReg(RegNo: FalseReg)
603 .addMBB(MBB: FalseMBB)
604 .addReg(RegNo: TrueReg)
605 .addMBB(MBB: TrueMBB);
606
607 return DoneMBB;
608}
609
610// Lower a `MEMCPY` instruction into a CFG triangle around a `MEMORY_COPY`
611// instruction to handle the zero-length case.
612static MachineBasicBlock *LowerMemcpy(MachineInstr &MI, DebugLoc DL,
613 MachineBasicBlock *BB,
614 const TargetInstrInfo &TII, bool Int64) {
615 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
616
617 MachineOperand DstMem = MI.getOperand(i: 0);
618 MachineOperand SrcMem = MI.getOperand(i: 1);
619 MachineOperand Dst = MI.getOperand(i: 2);
620 MachineOperand Src = MI.getOperand(i: 3);
621 MachineOperand Len = MI.getOperand(i: 4);
622
623 // If the length is a constant, we don't actually need the check.
624 if (MachineInstr *Def = MRI.getVRegDef(Reg: Len.getReg())) {
625 if (Def->getOpcode() == WebAssembly::CONST_I32 ||
626 Def->getOpcode() == WebAssembly::CONST_I64) {
627 if (Def->getOperand(i: 1).getImm() == 0) {
628 // A zero-length memcpy is a no-op.
629 MI.eraseFromParent();
630 return BB;
631 }
632 // A non-zero-length memcpy doesn't need a zero check.
633 unsigned MemoryCopy =
634 Int64 ? WebAssembly::MEMORY_COPY_A64 : WebAssembly::MEMORY_COPY_A32;
635 BuildMI(BB&: *BB, I&: MI, MIMD: DL, MCID: TII.get(Opcode: MemoryCopy))
636 .add(MO: DstMem)
637 .add(MO: SrcMem)
638 .add(MO: Dst)
639 .add(MO: Src)
640 .add(MO: Len);
641 MI.eraseFromParent();
642 return BB;
643 }
644 }
645
646 // We're going to add an extra use to `Len` to test if it's zero; that
647 // use shouldn't be a kill, even if the original use is.
648 MachineOperand NoKillLen = Len;
649 NoKillLen.setIsKill(false);
650
651 // Decide on which `MachineInstr` opcode we're going to use.
652 unsigned Eqz = Int64 ? WebAssembly::EQZ_I64 : WebAssembly::EQZ_I32;
653 unsigned MemoryCopy =
654 Int64 ? WebAssembly::MEMORY_COPY_A64 : WebAssembly::MEMORY_COPY_A32;
655
656 // Create two new basic blocks; one for the new `memory.fill` that we can
657 // branch over, and one for the rest of the instructions after the original
658 // `memory.fill`.
659 const BasicBlock *LLVMBB = BB->getBasicBlock();
660 MachineFunction *F = BB->getParent();
661 MachineBasicBlock *TrueMBB = F->CreateMachineBasicBlock(BB: LLVMBB);
662 MachineBasicBlock *DoneMBB = F->CreateMachineBasicBlock(BB: LLVMBB);
663
664 MachineFunction::iterator It = ++BB->getIterator();
665 F->insert(MBBI: It, MBB: TrueMBB);
666 F->insert(MBBI: It, MBB: DoneMBB);
667
668 // Transfer the remainder of BB and its successor edges to DoneMBB.
669 DoneMBB->splice(Where: DoneMBB->begin(), Other: BB, From: std::next(x: MI.getIterator()), To: BB->end());
670 DoneMBB->transferSuccessorsAndUpdatePHIs(FromMBB: BB);
671
672 // Connect the CFG edges.
673 BB->addSuccessor(Succ: TrueMBB);
674 BB->addSuccessor(Succ: DoneMBB);
675 TrueMBB->addSuccessor(Succ: DoneMBB);
676
677 // Create a virtual register for the `Eqz` result.
678 unsigned EqzReg;
679 EqzReg = MRI.createVirtualRegister(RegClass: &WebAssembly::I32RegClass);
680
681 // Erase the original `memory.copy`.
682 MI.eraseFromParent();
683
684 // Test if `Len` is zero.
685 BuildMI(BB, MIMD: DL, MCID: TII.get(Opcode: Eqz), DestReg: EqzReg).add(MO: NoKillLen);
686
687 // Insert a new `memory.copy`.
688 BuildMI(BB: TrueMBB, MIMD: DL, MCID: TII.get(Opcode: MemoryCopy))
689 .add(MO: DstMem)
690 .add(MO: SrcMem)
691 .add(MO: Dst)
692 .add(MO: Src)
693 .add(MO: Len);
694
695 // Create the CFG triangle.
696 BuildMI(BB, MIMD: DL, MCID: TII.get(Opcode: WebAssembly::BR_IF)).addMBB(MBB: DoneMBB).addReg(RegNo: EqzReg);
697 BuildMI(BB: TrueMBB, MIMD: DL, MCID: TII.get(Opcode: WebAssembly::BR)).addMBB(MBB: DoneMBB);
698
699 return DoneMBB;
700}
701
702// Lower a `MEMSET` instruction into a CFG triangle around a `MEMORY_FILL`
703// instruction to handle the zero-length case.
704static MachineBasicBlock *LowerMemset(MachineInstr &MI, DebugLoc DL,
705 MachineBasicBlock *BB,
706 const TargetInstrInfo &TII, bool Int64) {
707 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
708
709 MachineOperand Mem = MI.getOperand(i: 0);
710 MachineOperand Dst = MI.getOperand(i: 1);
711 MachineOperand Val = MI.getOperand(i: 2);
712 MachineOperand Len = MI.getOperand(i: 3);
713
714 // If the length is a constant, we don't actually need the check.
715 if (MachineInstr *Def = MRI.getVRegDef(Reg: Len.getReg())) {
716 if (Def->getOpcode() == WebAssembly::CONST_I32 ||
717 Def->getOpcode() == WebAssembly::CONST_I64) {
718 if (Def->getOperand(i: 1).getImm() == 0) {
719 // A zero-length memset is a no-op.
720 MI.eraseFromParent();
721 return BB;
722 }
723 // A non-zero-length memset doesn't need a zero check.
724 unsigned MemoryFill =
725 Int64 ? WebAssembly::MEMORY_FILL_A64 : WebAssembly::MEMORY_FILL_A32;
726 BuildMI(BB&: *BB, I&: MI, MIMD: DL, MCID: TII.get(Opcode: MemoryFill))
727 .add(MO: Mem)
728 .add(MO: Dst)
729 .add(MO: Val)
730 .add(MO: Len);
731 MI.eraseFromParent();
732 return BB;
733 }
734 }
735
736 // We're going to add an extra use to `Len` to test if it's zero; that
737 // use shouldn't be a kill, even if the original use is.
738 MachineOperand NoKillLen = Len;
739 NoKillLen.setIsKill(false);
740
741 // Decide on which `MachineInstr` opcode we're going to use.
742 unsigned Eqz = Int64 ? WebAssembly::EQZ_I64 : WebAssembly::EQZ_I32;
743 unsigned MemoryFill =
744 Int64 ? WebAssembly::MEMORY_FILL_A64 : WebAssembly::MEMORY_FILL_A32;
745
746 // Create two new basic blocks; one for the new `memory.fill` that we can
747 // branch over, and one for the rest of the instructions after the original
748 // `memory.fill`.
749 const BasicBlock *LLVMBB = BB->getBasicBlock();
750 MachineFunction *F = BB->getParent();
751 MachineBasicBlock *TrueMBB = F->CreateMachineBasicBlock(BB: LLVMBB);
752 MachineBasicBlock *DoneMBB = F->CreateMachineBasicBlock(BB: LLVMBB);
753
754 MachineFunction::iterator It = ++BB->getIterator();
755 F->insert(MBBI: It, MBB: TrueMBB);
756 F->insert(MBBI: It, MBB: DoneMBB);
757
758 // Transfer the remainder of BB and its successor edges to DoneMBB.
759 DoneMBB->splice(Where: DoneMBB->begin(), Other: BB, From: std::next(x: MI.getIterator()), To: BB->end());
760 DoneMBB->transferSuccessorsAndUpdatePHIs(FromMBB: BB);
761
762 // Connect the CFG edges.
763 BB->addSuccessor(Succ: TrueMBB);
764 BB->addSuccessor(Succ: DoneMBB);
765 TrueMBB->addSuccessor(Succ: DoneMBB);
766
767 // Create a virtual register for the `Eqz` result.
768 unsigned EqzReg;
769 EqzReg = MRI.createVirtualRegister(RegClass: &WebAssembly::I32RegClass);
770
771 // Erase the original `memory.fill`.
772 MI.eraseFromParent();
773
774 // Test if `Len` is zero.
775 BuildMI(BB, MIMD: DL, MCID: TII.get(Opcode: Eqz), DestReg: EqzReg).add(MO: NoKillLen);
776
777 // Insert a new `memory.copy`.
778 BuildMI(BB: TrueMBB, MIMD: DL, MCID: TII.get(Opcode: MemoryFill)).add(MO: Mem).add(MO: Dst).add(MO: Val).add(MO: Len);
779
780 // Create the CFG triangle.
781 BuildMI(BB, MIMD: DL, MCID: TII.get(Opcode: WebAssembly::BR_IF)).addMBB(MBB: DoneMBB).addReg(RegNo: EqzReg);
782 BuildMI(BB: TrueMBB, MIMD: DL, MCID: TII.get(Opcode: WebAssembly::BR)).addMBB(MBB: DoneMBB);
783
784 return DoneMBB;
785}
786
787static MachineBasicBlock *
788LowerCallResults(MachineInstr &CallResults, DebugLoc DL, MachineBasicBlock *BB,
789 const WebAssemblySubtarget *Subtarget,
790 const TargetInstrInfo &TII) {
791 MachineInstr &CallParams = *CallResults.getPrevNode();
792 assert(CallParams.getOpcode() == WebAssembly::CALL_PARAMS);
793 assert(CallResults.getOpcode() == WebAssembly::CALL_RESULTS ||
794 CallResults.getOpcode() == WebAssembly::RET_CALL_RESULTS);
795
796 bool IsIndirect =
797 CallParams.getOperand(i: 0).isReg() || CallParams.getOperand(i: 0).isFI();
798 bool IsRetCall = CallResults.getOpcode() == WebAssembly::RET_CALL_RESULTS;
799
800 bool IsFuncrefCall = false;
801 if (IsIndirect && CallParams.getOperand(i: 0).isReg()) {
802 Register Reg = CallParams.getOperand(i: 0).getReg();
803 const MachineFunction *MF = BB->getParent();
804 const MachineRegisterInfo &MRI = MF->getRegInfo();
805 const TargetRegisterClass *TRC = MRI.getRegClass(Reg);
806 IsFuncrefCall = (TRC == &WebAssembly::FUNCREFRegClass);
807 assert(!IsFuncrefCall || Subtarget->hasReferenceTypes());
808 }
809
810 unsigned CallOp;
811 if (IsIndirect && IsRetCall) {
812 CallOp = WebAssembly::RET_CALL_INDIRECT;
813 } else if (IsIndirect) {
814 CallOp = WebAssembly::CALL_INDIRECT;
815 } else if (IsRetCall) {
816 CallOp = WebAssembly::RET_CALL;
817 } else {
818 CallOp = WebAssembly::CALL;
819 }
820
821 MachineFunction &MF = *BB->getParent();
822 const MCInstrDesc &MCID = TII.get(Opcode: CallOp);
823 MachineInstrBuilder MIB(MF, MF.CreateMachineInstr(MCID, DL));
824
825 // Move the function pointer to the end of the arguments for indirect calls
826 if (IsIndirect) {
827 auto FnPtr = CallParams.getOperand(i: 0);
828 CallParams.removeOperand(OpNo: 0);
829
830 // For funcrefs, call_indirect is done through __funcref_call_table and the
831 // funcref is always installed in slot 0 of the table, therefore instead of
832 // having the function pointer added at the end of the params list, a zero
833 // (the index in
834 // __funcref_call_table is added).
835 if (IsFuncrefCall) {
836 Register RegZero =
837 MF.getRegInfo().createVirtualRegister(RegClass: &WebAssembly::I32RegClass);
838 MachineInstrBuilder MIBC0 =
839 BuildMI(MF, MIMD: DL, MCID: TII.get(Opcode: WebAssembly::CONST_I32), DestReg: RegZero).addImm(Val: 0);
840
841 BB->insert(I: CallResults.getIterator(), M: MIBC0);
842 MachineInstrBuilder(MF, CallParams).addReg(RegNo: RegZero);
843 } else
844 CallParams.addOperand(Op: FnPtr);
845 }
846
847 for (auto Def : CallResults.defs())
848 MIB.add(MO: Def);
849
850 if (IsIndirect) {
851 // Placeholder for the type index.
852 // This gets replaced with the correct value in WebAssemblyMCInstLower.cpp
853 MIB.addImm(Val: 0);
854 // The table into which this call_indirect indexes.
855 MCSymbolWasm *Table = IsFuncrefCall
856 ? WebAssembly::getOrCreateFuncrefCallTableSymbol(
857 Ctx&: MF.getContext(), Subtarget)
858 : WebAssembly::getOrCreateFunctionTableSymbol(
859 Ctx&: MF.getContext(), Subtarget);
860 if (Subtarget->hasCallIndirectOverlong()) {
861 MIB.addSym(Sym: Table);
862 } else {
863 // For the MVP there is at most one table whose number is 0, but we can't
864 // write a table symbol or issue relocations. Instead we just ensure the
865 // table is live and write a zero.
866 Table->setNoStrip();
867 MIB.addImm(Val: 0);
868 }
869 }
870
871 for (auto Use : CallParams.uses())
872 MIB.add(MO: Use);
873
874 BB->insert(I: CallResults.getIterator(), M: MIB);
875 CallParams.eraseFromParent();
876 CallResults.eraseFromParent();
877
878 // If this is a funcref call, to avoid hidden GC roots, we need to clear the
879 // table slot with ref.null upon call_indirect return.
880 //
881 // This generates the following code, which comes right after a call_indirect
882 // of a funcref:
883 //
884 // i32.const 0
885 // ref.null func
886 // table.set __funcref_call_table
887 if (IsIndirect && IsFuncrefCall) {
888 MCSymbolWasm *Table = WebAssembly::getOrCreateFuncrefCallTableSymbol(
889 Ctx&: MF.getContext(), Subtarget);
890 Register RegZero =
891 MF.getRegInfo().createVirtualRegister(RegClass: &WebAssembly::I32RegClass);
892 MachineInstr *Const0 =
893 BuildMI(MF, MIMD: DL, MCID: TII.get(Opcode: WebAssembly::CONST_I32), DestReg: RegZero).addImm(Val: 0);
894 BB->insertAfter(I: MIB.getInstr()->getIterator(), MI: Const0);
895
896 Register RegFuncref =
897 MF.getRegInfo().createVirtualRegister(RegClass: &WebAssembly::FUNCREFRegClass);
898 MachineInstr *RefNull =
899 BuildMI(MF, MIMD: DL, MCID: TII.get(Opcode: WebAssembly::REF_NULL_FUNCREF), DestReg: RegFuncref);
900 BB->insertAfter(I: Const0->getIterator(), MI: RefNull);
901
902 MachineInstr *TableSet =
903 BuildMI(MF, MIMD: DL, MCID: TII.get(Opcode: WebAssembly::TABLE_SET_FUNCREF))
904 .addSym(Sym: Table)
905 .addReg(RegNo: RegZero)
906 .addReg(RegNo: RegFuncref);
907 BB->insertAfter(I: RefNull->getIterator(), MI: TableSet);
908 }
909
910 return BB;
911}
912
913MachineBasicBlock *WebAssemblyTargetLowering::EmitInstrWithCustomInserter(
914 MachineInstr &MI, MachineBasicBlock *BB) const {
915 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
916 DebugLoc DL = MI.getDebugLoc();
917
918 switch (MI.getOpcode()) {
919 default:
920 llvm_unreachable("Unexpected instr type to insert");
921 case WebAssembly::FP_TO_SINT_I32_F32:
922 return LowerFPToInt(MI, DL, BB, TII, IsUnsigned: false, Int64: false, Float64: false,
923 LoweredOpcode: WebAssembly::I32_TRUNC_S_F32);
924 case WebAssembly::FP_TO_UINT_I32_F32:
925 return LowerFPToInt(MI, DL, BB, TII, IsUnsigned: true, Int64: false, Float64: false,
926 LoweredOpcode: WebAssembly::I32_TRUNC_U_F32);
927 case WebAssembly::FP_TO_SINT_I64_F32:
928 return LowerFPToInt(MI, DL, BB, TII, IsUnsigned: false, Int64: true, Float64: false,
929 LoweredOpcode: WebAssembly::I64_TRUNC_S_F32);
930 case WebAssembly::FP_TO_UINT_I64_F32:
931 return LowerFPToInt(MI, DL, BB, TII, IsUnsigned: true, Int64: true, Float64: false,
932 LoweredOpcode: WebAssembly::I64_TRUNC_U_F32);
933 case WebAssembly::FP_TO_SINT_I32_F64:
934 return LowerFPToInt(MI, DL, BB, TII, IsUnsigned: false, Int64: false, Float64: true,
935 LoweredOpcode: WebAssembly::I32_TRUNC_S_F64);
936 case WebAssembly::FP_TO_UINT_I32_F64:
937 return LowerFPToInt(MI, DL, BB, TII, IsUnsigned: true, Int64: false, Float64: true,
938 LoweredOpcode: WebAssembly::I32_TRUNC_U_F64);
939 case WebAssembly::FP_TO_SINT_I64_F64:
940 return LowerFPToInt(MI, DL, BB, TII, IsUnsigned: false, Int64: true, Float64: true,
941 LoweredOpcode: WebAssembly::I64_TRUNC_S_F64);
942 case WebAssembly::FP_TO_UINT_I64_F64:
943 return LowerFPToInt(MI, DL, BB, TII, IsUnsigned: true, Int64: true, Float64: true,
944 LoweredOpcode: WebAssembly::I64_TRUNC_U_F64);
945 case WebAssembly::MEMCPY_A32:
946 return LowerMemcpy(MI, DL, BB, TII, Int64: false);
947 case WebAssembly::MEMCPY_A64:
948 return LowerMemcpy(MI, DL, BB, TII, Int64: true);
949 case WebAssembly::MEMSET_A32:
950 return LowerMemset(MI, DL, BB, TII, Int64: false);
951 case WebAssembly::MEMSET_A64:
952 return LowerMemset(MI, DL, BB, TII, Int64: true);
953 case WebAssembly::CALL_RESULTS:
954 case WebAssembly::RET_CALL_RESULTS:
955 return LowerCallResults(CallResults&: MI, DL, BB, Subtarget, TII);
956 }
957}
958
959std::pair<unsigned, const TargetRegisterClass *>
960WebAssemblyTargetLowering::getRegForInlineAsmConstraint(
961 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
962 // First, see if this is a constraint that directly corresponds to a
963 // WebAssembly register class.
964 if (Constraint.size() == 1) {
965 switch (Constraint[0]) {
966 case 'r':
967 assert(VT != MVT::iPTR && "Pointer MVT not expected here");
968 if (Subtarget->hasSIMD128() && VT.isVector()) {
969 if (VT.getSizeInBits() == 128)
970 return std::make_pair(x: 0U, y: &WebAssembly::V128RegClass);
971 }
972 if (VT.isInteger() && !VT.isVector()) {
973 if (VT.getSizeInBits() <= 32)
974 return std::make_pair(x: 0U, y: &WebAssembly::I32RegClass);
975 if (VT.getSizeInBits() <= 64)
976 return std::make_pair(x: 0U, y: &WebAssembly::I64RegClass);
977 }
978 if (VT.isFloatingPoint() && !VT.isVector()) {
979 switch (VT.getSizeInBits()) {
980 case 32:
981 return std::make_pair(x: 0U, y: &WebAssembly::F32RegClass);
982 case 64:
983 return std::make_pair(x: 0U, y: &WebAssembly::F64RegClass);
984 default:
985 break;
986 }
987 }
988 break;
989 default:
990 break;
991 }
992 }
993
994 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
995}
996
997bool WebAssemblyTargetLowering::isCheapToSpeculateCttz(Type *Ty) const {
998 // Assume ctz is a relatively cheap operation.
999 return true;
1000}
1001
1002bool WebAssemblyTargetLowering::isCheapToSpeculateCtlz(Type *Ty) const {
1003 // Assume clz is a relatively cheap operation.
1004 return true;
1005}
1006
1007bool WebAssemblyTargetLowering::isLegalAddressingMode(const DataLayout &DL,
1008 const AddrMode &AM,
1009 Type *Ty, unsigned AS,
1010 Instruction *I) const {
1011 // WebAssembly offsets are added as unsigned without wrapping. The
1012 // isLegalAddressingMode gives us no way to determine if wrapping could be
1013 // happening, so we approximate this by accepting only non-negative offsets.
1014 if (AM.BaseOffs < 0)
1015 return false;
1016
1017 // WebAssembly has no scale register operands.
1018 if (AM.Scale != 0)
1019 return false;
1020
1021 // Everything else is legal.
1022 return true;
1023}
1024
1025bool WebAssemblyTargetLowering::allowsMisalignedMemoryAccesses(
1026 EVT /*VT*/, unsigned /*AddrSpace*/, Align /*Align*/,
1027 MachineMemOperand::Flags /*Flags*/, unsigned *Fast) const {
1028 // WebAssembly supports unaligned accesses, though it should be declared
1029 // with the p2align attribute on loads and stores which do so, and there
1030 // may be a performance impact. We tell LLVM they're "fast" because
1031 // for the kinds of things that LLVM uses this for (merging adjacent stores
1032 // of constants, etc.), WebAssembly implementations will either want the
1033 // unaligned access or they'll split anyway.
1034 if (Fast)
1035 *Fast = 1;
1036 return true;
1037}
1038
1039bool WebAssemblyTargetLowering::isIntDivCheap(EVT VT,
1040 AttributeList Attr) const {
1041 // The current thinking is that wasm engines will perform this optimization,
1042 // so we can save on code size.
1043 return true;
1044}
1045
1046bool WebAssemblyTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const {
1047 EVT ExtT = ExtVal.getValueType();
1048 SDValue N0 = peekThroughFreeze(V: ExtVal->getOperand(Num: 0));
1049 auto *Load = dyn_cast<LoadSDNode>(Val&: N0);
1050 if (!Load)
1051 return false;
1052 EVT MemT = Load->getValueType(ResNo: 0);
1053 return (ExtT == MVT::v8i16 && MemT == MVT::v8i8) ||
1054 (ExtT == MVT::v4i32 && MemT == MVT::v4i16) ||
1055 (ExtT == MVT::v2i64 && MemT == MVT::v2i32);
1056}
1057
1058bool WebAssemblyTargetLowering::isOffsetFoldingLegal(
1059 const GlobalAddressSDNode *GA) const {
1060 // Wasm doesn't support function addresses with offsets
1061 const GlobalValue *GV = GA->getGlobal();
1062 return isa<Function>(Val: GV) ? false : TargetLowering::isOffsetFoldingLegal(GA);
1063}
1064
1065EVT WebAssemblyTargetLowering::getSetCCResultType(const DataLayout &DL,
1066 LLVMContext &C,
1067 EVT VT) const {
1068 if (VT.isVector()) {
1069 if (VT.getVectorElementType() == MVT::f16 && !Subtarget->hasFP16())
1070 return VT.changeElementType(Context&: C, EltVT: MVT::i1);
1071
1072 return VT.changeVectorElementTypeToInteger();
1073 }
1074
1075 // So far, all branch instructions in Wasm take an I32 condition.
1076 // The default TargetLowering::getSetCCResultType returns the pointer size,
1077 // which would be useful to reduce instruction counts when testing
1078 // against 64-bit pointers/values if at some point Wasm supports that.
1079 return EVT::getIntegerVT(Context&: C, BitWidth: 32);
1080}
1081
1082void WebAssemblyTargetLowering::getTgtMemIntrinsic(
1083 SmallVectorImpl<IntrinsicInfo> &Infos, const CallBase &I,
1084 MachineFunction &MF, unsigned Intrinsic) const {
1085 IntrinsicInfo Info;
1086 switch (Intrinsic) {
1087 case Intrinsic::wasm_memory_atomic_notify:
1088 Info.opc = ISD::INTRINSIC_W_CHAIN;
1089 Info.memVT = MVT::i32;
1090 Info.ptrVal = I.getArgOperand(i: 0);
1091 Info.offset = 0;
1092 Info.align = Align(4);
1093 // atomic.notify instruction does not really load the memory specified with
1094 // this argument, but MachineMemOperand should either be load or store, so
1095 // we set this to a load.
1096 // FIXME Volatile isn't really correct, but currently all LLVM atomic
1097 // instructions are treated as volatiles in the backend, so we should be
1098 // consistent. The same applies for wasm_atomic_wait intrinsics too.
1099 Info.flags = MachineMemOperand::MOVolatile | MachineMemOperand::MOLoad;
1100 Infos.push_back(Elt: Info);
1101 return;
1102 case Intrinsic::wasm_memory_atomic_wait32:
1103 Info.opc = ISD::INTRINSIC_W_CHAIN;
1104 Info.memVT = MVT::i32;
1105 Info.ptrVal = I.getArgOperand(i: 0);
1106 Info.offset = 0;
1107 Info.align = Align(4);
1108 Info.flags = MachineMemOperand::MOVolatile | MachineMemOperand::MOLoad;
1109 Infos.push_back(Elt: Info);
1110 return;
1111 case Intrinsic::wasm_memory_atomic_wait64:
1112 Info.opc = ISD::INTRINSIC_W_CHAIN;
1113 Info.memVT = MVT::i64;
1114 Info.ptrVal = I.getArgOperand(i: 0);
1115 Info.offset = 0;
1116 Info.align = Align(8);
1117 Info.flags = MachineMemOperand::MOVolatile | MachineMemOperand::MOLoad;
1118 Infos.push_back(Elt: Info);
1119 return;
1120 case Intrinsic::wasm_loadf16_f32:
1121 Info.opc = ISD::INTRINSIC_W_CHAIN;
1122 Info.memVT = MVT::f16;
1123 Info.ptrVal = I.getArgOperand(i: 0);
1124 Info.offset = 0;
1125 Info.align = Align(2);
1126 Info.flags = MachineMemOperand::MOLoad;
1127 Infos.push_back(Elt: Info);
1128 return;
1129 case Intrinsic::wasm_storef16_f32:
1130 Info.opc = ISD::INTRINSIC_VOID;
1131 Info.memVT = MVT::f16;
1132 Info.ptrVal = I.getArgOperand(i: 1);
1133 Info.offset = 0;
1134 Info.align = Align(2);
1135 Info.flags = MachineMemOperand::MOStore;
1136 Infos.push_back(Elt: Info);
1137 return;
1138 default:
1139 return;
1140 }
1141}
1142
1143void WebAssemblyTargetLowering::computeKnownBitsForTargetNode(
1144 const SDValue Op, KnownBits &Known, const APInt &DemandedElts,
1145 const SelectionDAG &DAG, unsigned Depth) const {
1146 switch (Op.getOpcode()) {
1147 default:
1148 break;
1149 case ISD::INTRINSIC_WO_CHAIN: {
1150 unsigned IntNo = Op.getConstantOperandVal(i: 0);
1151 switch (IntNo) {
1152 default:
1153 break;
1154 case Intrinsic::wasm_bitmask: {
1155 unsigned BitWidth = Known.getBitWidth();
1156 EVT VT = Op.getOperand(i: 1).getSimpleValueType();
1157 unsigned PossibleBits = VT.getVectorNumElements();
1158 APInt ZeroMask = APInt::getHighBitsSet(numBits: BitWidth, hiBitsSet: BitWidth - PossibleBits);
1159 Known.Zero |= ZeroMask;
1160 break;
1161 }
1162 }
1163 break;
1164 }
1165 case WebAssemblyISD::EXTEND_LOW_U:
1166 case WebAssemblyISD::EXTEND_HIGH_U: {
1167 // We know the high half, of each destination vector element, will be zero.
1168 SDValue SrcOp = Op.getOperand(i: 0);
1169 EVT VT = SrcOp.getSimpleValueType();
1170 unsigned BitWidth = Known.getBitWidth();
1171 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
1172 assert(BitWidth >= 8 && "Unexpected width!");
1173 APInt Mask = APInt::getHighBitsSet(numBits: BitWidth, hiBitsSet: BitWidth - 8);
1174 Known.Zero |= Mask;
1175 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
1176 assert(BitWidth >= 16 && "Unexpected width!");
1177 APInt Mask = APInt::getHighBitsSet(numBits: BitWidth, hiBitsSet: BitWidth - 16);
1178 Known.Zero |= Mask;
1179 } else if (VT == MVT::v2i32 || VT == MVT::v4i32) {
1180 assert(BitWidth >= 32 && "Unexpected width!");
1181 APInt Mask = APInt::getHighBitsSet(numBits: BitWidth, hiBitsSet: BitWidth - 32);
1182 Known.Zero |= Mask;
1183 }
1184 break;
1185 }
1186 // For 128-bit addition if the upper bits are all zero then it's known that
1187 // the upper bits of the result will have all bits guaranteed zero except the
1188 // first.
1189 case WebAssemblyISD::I64_ADD128:
1190 if (Op.getResNo() == 1) {
1191 SDValue LHS_HI = Op.getOperand(i: 1);
1192 SDValue RHS_HI = Op.getOperand(i: 3);
1193 if (isNullConstant(V: LHS_HI) && isNullConstant(V: RHS_HI))
1194 Known.Zero.setBitsFrom(1);
1195 }
1196 break;
1197 }
1198}
1199
1200TargetLoweringBase::LegalizeTypeAction
1201WebAssemblyTargetLowering::getPreferredVectorAction(MVT VT) const {
1202 if (VT.isFixedLengthVector()) {
1203 MVT EltVT = VT.getVectorElementType();
1204 // We have legal vector types with these lane types, so widening the
1205 // vector would let us use some of the lanes directly without having to
1206 // extend or truncate values.
1207 if (EltVT == MVT::i8 || EltVT == MVT::i16 || EltVT == MVT::i32 ||
1208 EltVT == MVT::i64 || EltVT == MVT::f32 || EltVT == MVT::f64)
1209 return TypeWidenVector;
1210 }
1211
1212 return TargetLoweringBase::getPreferredVectorAction(VT);
1213}
1214
1215bool WebAssemblyTargetLowering::isFMAFasterThanFMulAndFAdd(
1216 const MachineFunction &MF, EVT VT) const {
1217 if (!Subtarget->hasFP16() || !VT.isVector())
1218 return false;
1219
1220 EVT ScalarVT = VT.getScalarType();
1221 if (!ScalarVT.isSimple())
1222 return false;
1223
1224 return ScalarVT.getSimpleVT().SimpleTy == MVT::f16;
1225}
1226
1227bool WebAssemblyTargetLowering::shouldSimplifyDemandedVectorElts(
1228 SDValue Op, const TargetLoweringOpt &TLO) const {
1229 // ISel process runs DAGCombiner after legalization; this step is called
1230 // SelectionDAG optimization phase. This post-legalization combining process
1231 // runs DAGCombiner on each node, and if there was a change to be made,
1232 // re-runs legalization again on it and its user nodes to make sure
1233 // everythiing is in a legalized state.
1234 //
1235 // The legalization calls lowering routines, and we do our custom lowering for
1236 // build_vectors (LowerBUILD_VECTOR), which converts undef vector elements
1237 // into zeros. But there is a set of routines in DAGCombiner that turns unused
1238 // (= not demanded) nodes into undef, among which SimplifyDemandedVectorElts
1239 // turns unused vector elements into undefs. But this routine does not work
1240 // with our custom LowerBUILD_VECTOR, which turns undefs into zeros. This
1241 // combination can result in a infinite loop, in which undefs are converted to
1242 // zeros in legalization and back to undefs in combining.
1243 //
1244 // So after DAG is legalized, we prevent SimplifyDemandedVectorElts from
1245 // running for build_vectors.
1246 if (Op.getOpcode() == ISD::BUILD_VECTOR && TLO.LegalOps && TLO.LegalTys)
1247 return false;
1248 return true;
1249}
1250
1251//===----------------------------------------------------------------------===//
1252// WebAssembly Lowering private implementation.
1253//===----------------------------------------------------------------------===//
1254
1255//===----------------------------------------------------------------------===//
1256// Lowering Code
1257//===----------------------------------------------------------------------===//
1258
1259static void fail(const SDLoc &DL, SelectionDAG &DAG, const char *Msg) {
1260 MachineFunction &MF = DAG.getMachineFunction();
1261 DAG.getContext()->diagnose(
1262 DI: DiagnosticInfoUnsupported(MF.getFunction(), Msg, DL.getDebugLoc()));
1263}
1264
1265// Test whether the given calling convention is supported.
1266static bool callingConvSupported(CallingConv::ID CallConv) {
1267 // We currently support the language-independent target-independent
1268 // conventions. We don't yet have a way to annotate calls with properties like
1269 // "cold", and we don't have any call-clobbered registers, so these are mostly
1270 // all handled the same.
1271 return CallConv == CallingConv::C || CallConv == CallingConv::Fast ||
1272 CallConv == CallingConv::Cold ||
1273 CallConv == CallingConv::PreserveMost ||
1274 CallConv == CallingConv::PreserveAll ||
1275 CallConv == CallingConv::CXX_FAST_TLS ||
1276 CallConv == CallingConv::WASM_EmscriptenInvoke ||
1277 CallConv == CallingConv::Swift || CallConv == CallingConv::SwiftTail;
1278}
1279
1280SDValue
1281WebAssemblyTargetLowering::LowerCall(CallLoweringInfo &CLI,
1282 SmallVectorImpl<SDValue> &InVals) const {
1283 SelectionDAG &DAG = CLI.DAG;
1284 SDLoc DL = CLI.DL;
1285 SDValue Chain = CLI.Chain;
1286 SDValue Callee = CLI.Callee;
1287 MachineFunction &MF = DAG.getMachineFunction();
1288 auto Layout = MF.getDataLayout();
1289
1290 // A call through a funcref is expressed in IR as a call through the pointer
1291 // produced by the llvm.wasm.funcref.to_ptr intrinsic. Detect this here and
1292 // recover the underlying funcref value so the call can be lowered to a
1293 // table.set + call_indirect through the dedicated __funcref_call_table.
1294 bool IsFuncrefCall = false;
1295 if (Callee.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
1296 Callee.getConstantOperandVal(i: 0) == Intrinsic::wasm_funcref_to_ptr) {
1297 Callee = Callee.getOperand(i: 1);
1298 IsFuncrefCall = true;
1299 }
1300
1301 CallingConv::ID CallConv = CLI.CallConv;
1302 if (!callingConvSupported(CallConv))
1303 fail(DL, DAG,
1304 Msg: "WebAssembly doesn't support language-specific or target-specific "
1305 "calling conventions yet");
1306 if (CLI.IsPatchPoint)
1307 fail(DL, DAG, Msg: "WebAssembly doesn't support patch point yet");
1308
1309 if (CLI.IsTailCall) {
1310 auto NoTail = [&](const char *Msg) {
1311 if (CLI.CB && CLI.CB->isMustTailCall())
1312 fail(DL, DAG, Msg);
1313 CLI.IsTailCall = false;
1314 };
1315
1316 if (!Subtarget->hasTailCall())
1317 NoTail("WebAssembly 'tail-call' feature not enabled");
1318
1319 // Varargs calls cannot be tail calls because the buffer is on the stack
1320 if (CLI.IsVarArg)
1321 NoTail("WebAssembly does not support varargs tail calls");
1322
1323 // Do not tail call unless caller and callee return types match
1324 const Function &F = MF.getFunction();
1325 const TargetMachine &TM = getTargetMachine();
1326 Type *RetTy = F.getReturnType();
1327 SmallVector<MVT, 4> CallerRetTys;
1328 SmallVector<MVT, 4> CalleeRetTys;
1329 computeLegalValueVTs(F, TM, Ty: RetTy, ValueVTs&: CallerRetTys);
1330 computeLegalValueVTs(F, TM, Ty: CLI.RetTy, ValueVTs&: CalleeRetTys);
1331 bool TypesMatch = CallerRetTys.size() == CalleeRetTys.size() &&
1332 std::equal(first1: CallerRetTys.begin(), last1: CallerRetTys.end(),
1333 first2: CalleeRetTys.begin());
1334 if (!TypesMatch)
1335 NoTail("WebAssembly tail call requires caller and callee return types to "
1336 "match");
1337
1338 // If pointers to local stack values are passed, we cannot tail call
1339 if (CLI.CB) {
1340 for (auto &Arg : CLI.CB->args()) {
1341 Value *Val = Arg.get();
1342 // Trace the value back through pointer operations
1343 while (true) {
1344 Value *Src = Val->stripPointerCastsAndAliases();
1345 if (auto *GEP = dyn_cast<GetElementPtrInst>(Val: Src))
1346 Src = GEP->getPointerOperand();
1347 if (Val == Src)
1348 break;
1349 Val = Src;
1350 }
1351 if (isa<AllocaInst>(Val)) {
1352 NoTail(
1353 "WebAssembly does not support tail calling with stack arguments");
1354 break;
1355 }
1356 }
1357 }
1358 }
1359
1360 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1361 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1362 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1363
1364 // The generic code may have added an sret argument. If we're lowering an
1365 // invoke function, the ABI requires that the function pointer be the first
1366 // argument, so we may have to swap the arguments.
1367 if (CallConv == CallingConv::WASM_EmscriptenInvoke && Outs.size() >= 2 &&
1368 Outs[0].Flags.isSRet()) {
1369 std::swap(a&: Outs[0], b&: Outs[1]);
1370 std::swap(a&: OutVals[0], b&: OutVals[1]);
1371 }
1372
1373 bool HasSwiftSelfArg = false;
1374 bool HasSwiftErrorArg = false;
1375 bool HasSwiftAsyncArg = false;
1376 unsigned NumFixedArgs = 0;
1377 for (unsigned I = 0; I < Outs.size(); ++I) {
1378 const ISD::OutputArg &Out = Outs[I];
1379 SDValue &OutVal = OutVals[I];
1380 HasSwiftSelfArg |= Out.Flags.isSwiftSelf();
1381 HasSwiftErrorArg |= Out.Flags.isSwiftError();
1382 HasSwiftAsyncArg |= Out.Flags.isSwiftAsync();
1383 if (Out.Flags.isNest())
1384 fail(DL, DAG, Msg: "WebAssembly hasn't implemented nest arguments");
1385 if (Out.Flags.isInAlloca())
1386 fail(DL, DAG, Msg: "WebAssembly hasn't implemented inalloca arguments");
1387 if (Out.Flags.isInConsecutiveRegs())
1388 fail(DL, DAG, Msg: "WebAssembly hasn't implemented cons regs arguments");
1389 if (Out.Flags.isInConsecutiveRegsLast())
1390 fail(DL, DAG, Msg: "WebAssembly hasn't implemented cons regs last arguments");
1391 if (Out.Flags.isByVal() && Out.Flags.getByValSize() != 0) {
1392 auto &MFI = MF.getFrameInfo();
1393 int FI = MFI.CreateStackObject(Size: Out.Flags.getByValSize(),
1394 Alignment: Out.Flags.getNonZeroByValAlign(),
1395 /*isSS=*/isSpillSlot: false);
1396 SDValue SizeNode =
1397 DAG.getConstant(Val: Out.Flags.getByValSize(), DL, VT: MVT::i32);
1398 SDValue FINode = DAG.getFrameIndex(FI, VT: getPointerTy(DL: Layout));
1399 Align Alignment = Out.Flags.getNonZeroByValAlign();
1400 Chain = DAG.getMemcpy(Chain, dl: DL, Dst: FINode, Src: OutVal, Size: SizeNode, DstAlign: Alignment,
1401 SrcAlign: Alignment,
1402 /*isVolatile*/ isVol: false, /*AlwaysInline=*/false,
1403 /*CI=*/nullptr, OverrideTailCall: std::nullopt, DstPtrInfo: MachinePointerInfo(),
1404 SrcPtrInfo: MachinePointerInfo());
1405 OutVal = FINode;
1406 }
1407 // Count the number of fixed args *after* legalization.
1408 NumFixedArgs += !Out.Flags.isVarArg();
1409 }
1410
1411 bool IsVarArg = CLI.IsVarArg;
1412 auto PtrVT = getPointerTy(DL: Layout);
1413
1414 // For swiftcc and swifttailcc, emit additional swiftself, swifterror, and
1415 // (for swifttailcc) swiftasync arguments if there aren't. These additional
1416 // arguments are also added for callee signature. They are necessary to match
1417 // callee and caller signature for indirect call.
1418 if (CallConv == CallingConv::Swift || CallConv == CallingConv::SwiftTail) {
1419 Type *PtrTy = PointerType::getUnqual(C&: *DAG.getContext());
1420 if (!HasSwiftSelfArg) {
1421 NumFixedArgs++;
1422 ISD::ArgFlagsTy Flags;
1423 Flags.setSwiftSelf();
1424 ISD::OutputArg Arg(Flags, PtrVT, EVT(PtrVT), PtrTy, 0, 0);
1425 CLI.Outs.push_back(Elt: Arg);
1426 SDValue ArgVal = DAG.getUNDEF(VT: PtrVT);
1427 CLI.OutVals.push_back(Elt: ArgVal);
1428 }
1429 if (!HasSwiftErrorArg) {
1430 NumFixedArgs++;
1431 ISD::ArgFlagsTy Flags;
1432 Flags.setSwiftError();
1433 ISD::OutputArg Arg(Flags, PtrVT, EVT(PtrVT), PtrTy, 0, 0);
1434 CLI.Outs.push_back(Elt: Arg);
1435 SDValue ArgVal = DAG.getUNDEF(VT: PtrVT);
1436 CLI.OutVals.push_back(Elt: ArgVal);
1437 }
1438 if (CallConv == CallingConv::SwiftTail && !HasSwiftAsyncArg) {
1439 NumFixedArgs++;
1440 ISD::ArgFlagsTy Flags;
1441 Flags.setSwiftAsync();
1442 ISD::OutputArg Arg(Flags, PtrVT, EVT(PtrVT), PtrTy, 0, 0);
1443 CLI.Outs.push_back(Elt: Arg);
1444 SDValue ArgVal = DAG.getUNDEF(VT: PtrVT);
1445 CLI.OutVals.push_back(Elt: ArgVal);
1446 }
1447 }
1448
1449 // Analyze operands of the call, assigning locations to each operand.
1450 SmallVector<CCValAssign, 16> ArgLocs;
1451 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
1452
1453 if (IsVarArg) {
1454 // Outgoing non-fixed arguments are placed in a buffer. First
1455 // compute their offsets and the total amount of buffer space needed.
1456 for (unsigned I = NumFixedArgs; I < Outs.size(); ++I) {
1457 const ISD::OutputArg &Out = Outs[I];
1458 SDValue &Arg = OutVals[I];
1459 EVT VT = Arg.getValueType();
1460 assert(VT != MVT::iPTR && "Legalized args should be concrete");
1461 Type *Ty = VT.getTypeForEVT(Context&: *DAG.getContext());
1462 Align Alignment =
1463 std::max(a: Out.Flags.getNonZeroOrigAlign(), b: Layout.getABITypeAlign(Ty));
1464 unsigned Offset =
1465 CCInfo.AllocateStack(Size: Layout.getTypeAllocSize(Ty), Alignment);
1466 CCInfo.addLoc(V: CCValAssign::getMem(ValNo: ArgLocs.size(), ValVT: VT.getSimpleVT(),
1467 Offset, LocVT: VT.getSimpleVT(),
1468 HTP: CCValAssign::Full));
1469 }
1470 }
1471
1472 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
1473
1474 SDValue FINode;
1475 if (IsVarArg && NumBytes) {
1476 // For non-fixed arguments, next emit stores to store the argument values
1477 // to the stack buffer at the offsets computed above.
1478 MaybeAlign StackAlign = Layout.getStackAlignment();
1479 assert(StackAlign && "data layout string is missing stack alignment");
1480 int FI = MF.getFrameInfo().CreateStackObject(Size: NumBytes, Alignment: *StackAlign,
1481 /*isSS=*/isSpillSlot: false);
1482 unsigned ValNo = 0;
1483 SmallVector<SDValue, 8> Chains;
1484 for (SDValue Arg : drop_begin(RangeOrContainer&: OutVals, N: NumFixedArgs)) {
1485 assert(ArgLocs[ValNo].getValNo() == ValNo &&
1486 "ArgLocs should remain in order and only hold varargs args");
1487 unsigned Offset = ArgLocs[ValNo++].getLocMemOffset();
1488 FINode = DAG.getFrameIndex(FI, VT: getPointerTy(DL: Layout));
1489 SDValue Add = DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: FINode,
1490 N2: DAG.getConstant(Val: Offset, DL, VT: PtrVT));
1491 Chains.push_back(
1492 Elt: DAG.getStore(Chain, dl: DL, Val: Arg, Ptr: Add,
1493 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI, Offset)));
1494 }
1495 if (!Chains.empty())
1496 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, Ops: Chains);
1497 } else if (IsVarArg) {
1498 FINode = DAG.getIntPtrConstant(Val: 0, DL);
1499 }
1500
1501 if (Callee->getOpcode() == ISD::GlobalAddress) {
1502 // If the callee is a GlobalAddress node (quite common, every direct call
1503 // is) turn it into a TargetGlobalAddress node so that LowerGlobalAddress
1504 // doesn't at MO_GOT which is not needed for direct calls.
1505 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Val&: Callee);
1506 Callee = DAG.getTargetGlobalAddress(GV: GA->getGlobal(), DL,
1507 VT: getPointerTy(DL: DAG.getDataLayout()),
1508 offset: GA->getOffset());
1509 Callee = DAG.getNode(Opcode: WebAssemblyISD::Wrapper, DL,
1510 VT: getPointerTy(DL: DAG.getDataLayout()), Operand: Callee);
1511 }
1512
1513 // Compute the operands for the CALLn node.
1514 SmallVector<SDValue, 16> Ops;
1515 Ops.push_back(Elt: Chain);
1516 Ops.push_back(Elt: Callee);
1517
1518 // Add all fixed arguments. Note that for non-varargs calls, NumFixedArgs
1519 // isn't reliable.
1520 Ops.append(in_start: OutVals.begin(),
1521 in_end: IsVarArg ? OutVals.begin() + NumFixedArgs : OutVals.end());
1522 // Add a pointer to the vararg buffer.
1523 if (IsVarArg)
1524 Ops.push_back(Elt: FINode);
1525
1526 SmallVector<EVT, 8> InTys;
1527 for (const auto &In : Ins) {
1528 assert(!In.Flags.isByVal() && "byval is not valid for return values");
1529 assert(!In.Flags.isNest() && "nest is not valid for return values");
1530 if (In.Flags.isInAlloca())
1531 fail(DL, DAG, Msg: "WebAssembly hasn't implemented inalloca return values");
1532 if (In.Flags.isInConsecutiveRegs())
1533 fail(DL, DAG, Msg: "WebAssembly hasn't implemented cons regs return values");
1534 if (In.Flags.isInConsecutiveRegsLast())
1535 fail(DL, DAG,
1536 Msg: "WebAssembly hasn't implemented cons regs last return values");
1537 // Ignore In.getNonZeroOrigAlign() because all our arguments are passed in
1538 // registers.
1539 InTys.push_back(Elt: In.VT);
1540 }
1541
1542 // Lastly, if this is a call to a funcref we need to add an instruction
1543 // table.set to the chain and transform the call.
1544 if (IsFuncrefCall) {
1545 // In the absence of function references proposal where a funcref call is
1546 // lowered to call_ref, using reference types we generate a table.set to set
1547 // the funcref to a special table used solely for this purpose, followed by
1548 // a call_indirect. Here we just generate the table set, and return the
1549 // SDValue of the table.set so that LowerCall can finalize the lowering by
1550 // generating the call_indirect.
1551 SDValue Chain = Ops[0];
1552
1553 MCSymbolWasm *Table = WebAssembly::getOrCreateFuncrefCallTableSymbol(
1554 Ctx&: MF.getContext(), Subtarget);
1555 SDValue Sym = DAG.getMCSymbol(Sym: Table, VT: PtrVT);
1556 SDValue TableSlot = DAG.getConstant(Val: 0, DL, VT: MVT::i32);
1557 SDValue TableSetOps[] = {Chain, Sym, TableSlot, Callee};
1558 SDValue TableSet = DAG.getMemIntrinsicNode(
1559 Opcode: WebAssemblyISD::TABLE_SET, dl: DL, VTList: DAG.getVTList(VT: MVT::Other), Ops: TableSetOps,
1560 MemVT: MVT::funcref, PtrInfo: MachinePointerInfo(), Alignment: Align(1),
1561 Flags: MachineMemOperand::MOStore);
1562
1563 Ops[0] = TableSet; // The new chain is the TableSet itself
1564 }
1565
1566 if (CLI.IsTailCall) {
1567 // ret_calls do not return values to the current frame
1568 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
1569 return DAG.getNode(Opcode: WebAssemblyISD::RET_CALL, DL, VTList: NodeTys, Ops);
1570 }
1571
1572 InTys.push_back(Elt: MVT::Other);
1573 SDVTList InTyList = DAG.getVTList(VTs: InTys);
1574 SDValue Res = DAG.getNode(Opcode: WebAssemblyISD::CALL, DL, VTList: InTyList, Ops);
1575
1576 for (size_t I = 0; I < Ins.size(); ++I)
1577 InVals.push_back(Elt: Res.getValue(R: I));
1578
1579 // Return the chain
1580 return Res.getValue(R: Ins.size());
1581}
1582
1583bool WebAssemblyTargetLowering::CanLowerReturn(
1584 CallingConv::ID /*CallConv*/, MachineFunction & /*MF*/, bool /*IsVarArg*/,
1585 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext & /*Context*/,
1586 const Type *RetTy) const {
1587 // WebAssembly can only handle returning tuples with multivalue enabled
1588 return WebAssembly::canLowerReturn(ResultSize: Outs.size(), Subtarget);
1589}
1590
1591SDValue WebAssemblyTargetLowering::LowerReturn(
1592 SDValue Chain, CallingConv::ID CallConv, bool /*IsVarArg*/,
1593 const SmallVectorImpl<ISD::OutputArg> &Outs,
1594 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
1595 SelectionDAG &DAG) const {
1596 assert(WebAssembly::canLowerReturn(Outs.size(), Subtarget) &&
1597 "MVP WebAssembly can only return up to one value");
1598 if (!callingConvSupported(CallConv))
1599 fail(DL, DAG, Msg: "WebAssembly doesn't support non-C calling conventions");
1600
1601 SmallVector<SDValue, 4> RetOps(1, Chain);
1602 RetOps.append(in_start: OutVals.begin(), in_end: OutVals.end());
1603 Chain = DAG.getNode(Opcode: WebAssemblyISD::RETURN, DL, VT: MVT::Other, Ops: RetOps);
1604
1605 // Record the number and types of the return values.
1606 for (const ISD::OutputArg &Out : Outs) {
1607 assert(!Out.Flags.isByVal() && "byval is not valid for return values");
1608 assert(!Out.Flags.isNest() && "nest is not valid for return values");
1609 assert(!Out.Flags.isVarArg() && "non-fixed return value is not valid");
1610 if (Out.Flags.isInAlloca())
1611 fail(DL, DAG, Msg: "WebAssembly hasn't implemented inalloca results");
1612 if (Out.Flags.isInConsecutiveRegs())
1613 fail(DL, DAG, Msg: "WebAssembly hasn't implemented cons regs results");
1614 if (Out.Flags.isInConsecutiveRegsLast())
1615 fail(DL, DAG, Msg: "WebAssembly hasn't implemented cons regs last results");
1616 }
1617
1618 return Chain;
1619}
1620
1621SDValue WebAssemblyTargetLowering::LowerFormalArguments(
1622 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
1623 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
1624 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1625 if (!callingConvSupported(CallConv))
1626 fail(DL, DAG, Msg: "WebAssembly doesn't support non-C calling conventions");
1627
1628 MachineFunction &MF = DAG.getMachineFunction();
1629 auto *MFI = MF.getInfo<WebAssemblyFunctionInfo>();
1630
1631 // Set up the incoming ARGUMENTS value, which serves to represent the liveness
1632 // of the incoming values before they're represented by virtual registers.
1633 MF.getRegInfo().addLiveIn(Reg: WebAssembly::ARGUMENTS);
1634
1635 bool HasSwiftErrorArg = false;
1636 bool HasSwiftSelfArg = false;
1637 bool HasSwiftAsyncArg = false;
1638 for (const ISD::InputArg &In : Ins) {
1639 HasSwiftSelfArg |= In.Flags.isSwiftSelf();
1640 HasSwiftErrorArg |= In.Flags.isSwiftError();
1641 HasSwiftAsyncArg |= In.Flags.isSwiftAsync();
1642 if (In.Flags.isInAlloca())
1643 fail(DL, DAG, Msg: "WebAssembly hasn't implemented inalloca arguments");
1644 if (In.Flags.isNest())
1645 fail(DL, DAG, Msg: "WebAssembly hasn't implemented nest arguments");
1646 if (In.Flags.isInConsecutiveRegs())
1647 fail(DL, DAG, Msg: "WebAssembly hasn't implemented cons regs arguments");
1648 if (In.Flags.isInConsecutiveRegsLast())
1649 fail(DL, DAG, Msg: "WebAssembly hasn't implemented cons regs last arguments");
1650 // Ignore In.getNonZeroOrigAlign() because all our arguments are passed in
1651 // registers.
1652 InVals.push_back(Elt: In.Used ? DAG.getNode(Opcode: WebAssemblyISD::ARGUMENT, DL, VT: In.VT,
1653 Operand: DAG.getTargetConstant(Val: InVals.size(),
1654 DL, VT: MVT::i32))
1655 : DAG.getUNDEF(VT: In.VT));
1656
1657 // Record the number and types of arguments.
1658 MFI->addParam(VT: In.VT);
1659 }
1660
1661 // For swiftcc and swifttailcc, emit additional swiftself, swifterror, and
1662 // (for swifttailcc) swiftasync arguments if there aren't. These additional
1663 // arguments are also added for callee signature. They are necessary to match
1664 // callee and caller signature for indirect call.
1665 auto PtrVT = getPointerTy(DL: MF.getDataLayout());
1666 if (CallConv == CallingConv::Swift || CallConv == CallingConv::SwiftTail) {
1667 if (!HasSwiftSelfArg) {
1668 MFI->addParam(VT: PtrVT);
1669 }
1670 if (!HasSwiftErrorArg) {
1671 MFI->addParam(VT: PtrVT);
1672 }
1673 if (CallConv == CallingConv::SwiftTail && !HasSwiftAsyncArg) {
1674 MFI->addParam(VT: PtrVT);
1675 }
1676 }
1677 // Varargs are copied into a buffer allocated by the caller, and a pointer to
1678 // the buffer is passed as an argument.
1679 if (IsVarArg) {
1680 MVT PtrVT = getPointerTy(DL: MF.getDataLayout());
1681 Register VarargVreg =
1682 MF.getRegInfo().createVirtualRegister(RegClass: getRegClassFor(VT: PtrVT));
1683 MFI->setVarargBufferVreg(VarargVreg);
1684 Chain = DAG.getCopyToReg(
1685 Chain, dl: DL, Reg: VarargVreg,
1686 N: DAG.getNode(Opcode: WebAssemblyISD::ARGUMENT, DL, VT: PtrVT,
1687 Operand: DAG.getTargetConstant(Val: Ins.size(), DL, VT: MVT::i32)));
1688 MFI->addParam(VT: PtrVT);
1689 }
1690
1691 // Record the number and types of arguments and results.
1692 SmallVector<MVT, 4> Params;
1693 SmallVector<MVT, 4> Results;
1694 computeSignatureVTs(Ty: MF.getFunction().getFunctionType(), TargetFunc: &MF.getFunction(),
1695 ContextFunc: MF.getFunction(), TM: DAG.getTarget(), Params, Results);
1696 for (MVT VT : Results)
1697 MFI->addResult(VT);
1698 // TODO: Use signatures in WebAssemblyMachineFunctionInfo too and unify
1699 // the param logic here with ComputeSignatureVTs
1700 assert(MFI->getParams().size() == Params.size() &&
1701 std::equal(MFI->getParams().begin(), MFI->getParams().end(),
1702 Params.begin()));
1703
1704 return Chain;
1705}
1706
1707void WebAssemblyTargetLowering::ReplaceNodeResults(
1708 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
1709 switch (N->getOpcode()) {
1710 case ISD::SIGN_EXTEND_INREG:
1711 // Do not add any results, signifying that N should not be custom lowered
1712 // after all. This happens because simd128 turns on custom lowering for
1713 // SIGN_EXTEND_INREG, but for non-vector sign extends the result might be an
1714 // illegal type.
1715 break;
1716 case ISD::ANY_EXTEND_VECTOR_INREG:
1717 case ISD::SIGN_EXTEND_VECTOR_INREG:
1718 case ISD::ZERO_EXTEND_VECTOR_INREG:
1719 // Do not add any results, signifying that N should not be custom lowered.
1720 // EXTEND_VECTOR_INREG is implemented for some vectors, but not all.
1721 break;
1722 case ISD::FP_ROUND: {
1723 EVT VT = N->getValueType(ResNo: 0);
1724 SDValue Src = N->getOperand(Num: 0);
1725 if (VT == MVT::v4f16 && Src.getValueType() == MVT::v4f32) {
1726 Results.push_back(
1727 Elt: DAG.getNode(Opcode: WebAssemblyISD::DEMOTE_ZERO, DL: SDLoc(N), VT: MVT::v8f16, Operand: Src));
1728 }
1729 break;
1730 }
1731 case ISD::ADD:
1732 case ISD::SUB:
1733 Results.push_back(Elt: Replace128Op(N, DAG));
1734 break;
1735 default:
1736 llvm_unreachable(
1737 "ReplaceNodeResults not implemented for this op for WebAssembly!");
1738 }
1739}
1740
1741//===----------------------------------------------------------------------===//
1742// Custom lowering hooks.
1743//===----------------------------------------------------------------------===//
1744
1745SDValue WebAssemblyTargetLowering::LowerOperation(SDValue Op,
1746 SelectionDAG &DAG) const {
1747 SDLoc DL(Op);
1748 switch (Op.getOpcode()) {
1749 default:
1750 llvm_unreachable("unimplemented operation lowering");
1751 return SDValue();
1752 case ISD::FrameIndex:
1753 return LowerFrameIndex(Op, DAG);
1754 case ISD::GlobalAddress:
1755 return LowerGlobalAddress(Op, DAG);
1756 case ISD::GlobalTLSAddress:
1757 return LowerGlobalTLSAddress(Op, DAG);
1758 case ISD::ExternalSymbol:
1759 return LowerExternalSymbol(Op, DAG);
1760 case ISD::JumpTable:
1761 return LowerJumpTable(Op, DAG);
1762 case ISD::BR_JT:
1763 return LowerBR_JT(Op, DAG);
1764 case ISD::VASTART:
1765 return LowerVASTART(Op, DAG);
1766 case ISD::BlockAddress:
1767 case ISD::BRIND:
1768 fail(DL, DAG, Msg: "WebAssembly hasn't implemented computed gotos");
1769 return SDValue();
1770 case ISD::RETURNADDR:
1771 return LowerRETURNADDR(Op, DAG);
1772 case ISD::FRAMEADDR:
1773 return LowerFRAMEADDR(Op, DAG);
1774 case ISD::CopyToReg:
1775 return LowerCopyToReg(Op, DAG);
1776 case ISD::EXTRACT_VECTOR_ELT:
1777 case ISD::INSERT_VECTOR_ELT:
1778 return LowerAccessVectorElement(Op, DAG);
1779 case ISD::INTRINSIC_VOID:
1780 case ISD::INTRINSIC_WO_CHAIN:
1781 case ISD::INTRINSIC_W_CHAIN:
1782 return LowerIntrinsic(Op, DAG);
1783 case ISD::SIGN_EXTEND_INREG:
1784 return LowerSIGN_EXTEND_INREG(Op, DAG);
1785 case ISD::ZERO_EXTEND_VECTOR_INREG:
1786 case ISD::SIGN_EXTEND_VECTOR_INREG:
1787 case ISD::ANY_EXTEND_VECTOR_INREG:
1788 return LowerEXTEND_VECTOR_INREG(Op, DAG);
1789 case ISD::BUILD_VECTOR:
1790 return LowerBUILD_VECTOR(Op, DAG);
1791 case ISD::VECTOR_SHUFFLE:
1792 return LowerVECTOR_SHUFFLE(Op, DAG);
1793 case ISD::SETCC:
1794 return LowerSETCC(Op, DAG);
1795 case ISD::SHL:
1796 case ISD::SRA:
1797 case ISD::SRL:
1798 return LowerShift(Op, DAG);
1799 case ISD::FP_TO_SINT_SAT:
1800 case ISD::FP_TO_UINT_SAT:
1801 return LowerFP_TO_INT_SAT(Op, DAG);
1802 case ISD::FMINNUM:
1803 case ISD::FMINIMUMNUM:
1804 return LowerFMIN(Op, DAG);
1805 case ISD::FMAXNUM:
1806 case ISD::FMAXIMUMNUM:
1807 return LowerFMAX(Op, DAG);
1808 case ISD::LOAD:
1809 return LowerLoad(Op, DAG);
1810 case ISD::STORE:
1811 return LowerStore(Op, DAG);
1812 case ISD::CTPOP:
1813 case ISD::CTLZ:
1814 case ISD::CTTZ:
1815 return DAG.UnrollVectorOp(N: Op.getNode());
1816 case ISD::CLEAR_CACHE:
1817 report_fatal_error(reason: "llvm.clear_cache is not supported on wasm");
1818 case ISD::SMUL_LOHI:
1819 case ISD::UMUL_LOHI:
1820 return LowerMUL_LOHI(Op, DAG);
1821 case ISD::UADDO:
1822 return LowerUADDO(Op, DAG);
1823 }
1824}
1825
1826static bool IsWebAssemblyGlobal(SDValue Op) {
1827 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Val&: Op))
1828 return WebAssembly::isWasmVarAddressSpace(AS: GA->getAddressSpace());
1829
1830 return false;
1831}
1832
1833static std::optional<unsigned> IsWebAssemblyLocal(SDValue Op,
1834 SelectionDAG &DAG) {
1835 const FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Val&: Op);
1836 if (!FI)
1837 return std::nullopt;
1838
1839 auto &MF = DAG.getMachineFunction();
1840 return WebAssemblyFrameLowering::getLocalForStackObject(MF, FrameIndex: FI->getIndex());
1841}
1842
1843SDValue WebAssemblyTargetLowering::LowerStore(SDValue Op,
1844 SelectionDAG &DAG) const {
1845 SDLoc DL(Op);
1846 StoreSDNode *SN = cast<StoreSDNode>(Val: Op.getNode());
1847 const SDValue &Value = SN->getValue();
1848 const SDValue &Base = SN->getBasePtr();
1849 const SDValue &Offset = SN->getOffset();
1850
1851 if (IsWebAssemblyGlobal(Op: Base)) {
1852 if (!Offset->isUndef())
1853 report_fatal_error(reason: "unexpected offset when storing to webassembly global",
1854 gen_crash_diag: false);
1855
1856 SDVTList Tys = DAG.getVTList(VT: MVT::Other);
1857 SDValue Ops[] = {SN->getChain(), Value, Base};
1858 return DAG.getMemIntrinsicNode(Opcode: WebAssemblyISD::GLOBAL_SET, dl: DL, VTList: Tys, Ops,
1859 MemVT: SN->getMemoryVT(), MMO: SN->getMemOperand());
1860 }
1861
1862 if (std::optional<unsigned> Local = IsWebAssemblyLocal(Op: Base, DAG)) {
1863 if (!Offset->isUndef())
1864 report_fatal_error(reason: "unexpected offset when storing to webassembly local",
1865 gen_crash_diag: false);
1866
1867 SDValue Idx = DAG.getTargetConstant(Val: *Local, DL: Base, VT: MVT::i32);
1868 SDVTList Tys = DAG.getVTList(VT: MVT::Other); // The chain.
1869 SDValue Ops[] = {SN->getChain(), Idx, Value};
1870 return DAG.getNode(Opcode: WebAssemblyISD::LOCAL_SET, DL, VTList: Tys, Ops);
1871 }
1872
1873 if (WebAssembly::isWasmVarAddressSpace(AS: SN->getAddressSpace()))
1874 report_fatal_error(
1875 reason: "Encountered an unlowerable store to the wasm_var address space",
1876 gen_crash_diag: false);
1877
1878 return Op;
1879}
1880
1881SDValue WebAssemblyTargetLowering::LowerLoad(SDValue Op,
1882 SelectionDAG &DAG) const {
1883 SDLoc DL(Op);
1884 LoadSDNode *LN = cast<LoadSDNode>(Val: Op.getNode());
1885 const SDValue &Base = LN->getBasePtr();
1886 const SDValue &Offset = LN->getOffset();
1887
1888 if (IsWebAssemblyGlobal(Op: Base)) {
1889 if (!Offset->isUndef())
1890 report_fatal_error(
1891 reason: "unexpected offset when loading from webassembly global", gen_crash_diag: false);
1892
1893 SDVTList Tys = DAG.getVTList(VT1: LN->getValueType(ResNo: 0), VT2: MVT::Other);
1894 SDValue Ops[] = {LN->getChain(), Base};
1895 return DAG.getMemIntrinsicNode(Opcode: WebAssemblyISD::GLOBAL_GET, dl: DL, VTList: Tys, Ops,
1896 MemVT: LN->getMemoryVT(), MMO: LN->getMemOperand());
1897 }
1898
1899 if (std::optional<unsigned> Local = IsWebAssemblyLocal(Op: Base, DAG)) {
1900 if (!Offset->isUndef())
1901 report_fatal_error(
1902 reason: "unexpected offset when loading from webassembly local", gen_crash_diag: false);
1903
1904 SDValue Idx = DAG.getTargetConstant(Val: *Local, DL: Base, VT: MVT::i32);
1905 EVT LocalVT = LN->getValueType(ResNo: 0);
1906 return DAG.getNode(Opcode: WebAssemblyISD::LOCAL_GET, DL, ResultTys: {LocalVT, MVT::Other},
1907 Ops: {LN->getChain(), Idx});
1908 }
1909
1910 if (WebAssembly::isWasmVarAddressSpace(AS: LN->getAddressSpace()))
1911 report_fatal_error(
1912 reason: "Encountered an unlowerable load from the wasm_var address space",
1913 gen_crash_diag: false);
1914
1915 return Op;
1916}
1917
1918SDValue WebAssemblyTargetLowering::LowerMUL_LOHI(SDValue Op,
1919 SelectionDAG &DAG) const {
1920 assert(Subtarget->hasWideArithmetic());
1921 assert(Op.getValueType() == MVT::i64);
1922 SDLoc DL(Op);
1923 unsigned Opcode;
1924 switch (Op.getOpcode()) {
1925 case ISD::UMUL_LOHI:
1926 Opcode = WebAssemblyISD::I64_MUL_WIDE_U;
1927 break;
1928 case ISD::SMUL_LOHI:
1929 Opcode = WebAssemblyISD::I64_MUL_WIDE_S;
1930 break;
1931 default:
1932 llvm_unreachable("unexpected opcode");
1933 }
1934 SDValue LHS = Op.getOperand(i: 0);
1935 SDValue RHS = Op.getOperand(i: 1);
1936 SDValue Lo =
1937 DAG.getNode(Opcode, DL, VTList: DAG.getVTList(VT1: MVT::i64, VT2: MVT::i64), N1: LHS, N2: RHS);
1938 SDValue Hi(Lo.getNode(), 1);
1939 SDValue Ops[] = {Lo, Hi};
1940 return DAG.getMergeValues(Ops, dl: DL);
1941}
1942
1943// Lowers `UADDO` intrinsics to an `i64.add128` instruction when it's enabled.
1944//
1945// This enables generating a single wasm instruction for this operation where
1946// the upper half of both operands are constant zeros. The upper half of the
1947// result is then whether the overflow happened.
1948SDValue WebAssemblyTargetLowering::LowerUADDO(SDValue Op,
1949 SelectionDAG &DAG) const {
1950 assert(Subtarget->hasWideArithmetic());
1951 assert(Op.getValueType() == MVT::i64);
1952 assert(Op.getOpcode() == ISD::UADDO);
1953 SDLoc DL(Op);
1954 SDValue LHS = Op.getOperand(i: 0);
1955 SDValue RHS = Op.getOperand(i: 1);
1956 SDValue Zero = DAG.getConstant(Val: 0, DL, VT: MVT::i64);
1957 SDValue Result =
1958 DAG.getNode(Opcode: WebAssemblyISD::I64_ADD128, DL,
1959 VTList: DAG.getVTList(VT1: MVT::i64, VT2: MVT::i64), N1: LHS, N2: Zero, N3: RHS, N4: Zero);
1960 SDValue CarryI64(Result.getNode(), 1);
1961 SDValue CarryI32 = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: MVT::i32, Operand: CarryI64);
1962 SDValue Ops[] = {Result, CarryI32};
1963 return DAG.getMergeValues(Ops, dl: DL);
1964}
1965
1966SDValue WebAssemblyTargetLowering::Replace128Op(SDNode *N,
1967 SelectionDAG &DAG) const {
1968 assert(Subtarget->hasWideArithmetic());
1969 assert(N->getValueType(0) == MVT::i128);
1970 SDLoc DL(N);
1971 unsigned Opcode;
1972 switch (N->getOpcode()) {
1973 case ISD::ADD:
1974 Opcode = WebAssemblyISD::I64_ADD128;
1975 break;
1976 case ISD::SUB:
1977 Opcode = WebAssemblyISD::I64_SUB128;
1978 break;
1979 default:
1980 llvm_unreachable("unexpected opcode");
1981 }
1982 SDValue LHS = N->getOperand(Num: 0);
1983 SDValue RHS = N->getOperand(Num: 1);
1984
1985 SDValue C0 = DAG.getConstant(Val: 0, DL, VT: MVT::i64);
1986 SDValue C1 = DAG.getConstant(Val: 1, DL, VT: MVT::i64);
1987 SDValue LHS_0 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i64, N1: LHS, N2: C0);
1988 SDValue LHS_1 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i64, N1: LHS, N2: C1);
1989 SDValue RHS_0 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i64, N1: RHS, N2: C0);
1990 SDValue RHS_1 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i64, N1: RHS, N2: C1);
1991 SDValue Result_LO = DAG.getNode(Opcode, DL, VTList: DAG.getVTList(VT1: MVT::i64, VT2: MVT::i64),
1992 N1: LHS_0, N2: LHS_1, N3: RHS_0, N4: RHS_1);
1993 SDValue Result_HI(Result_LO.getNode(), 1);
1994 return DAG.getNode(Opcode: ISD::BUILD_PAIR, DL, VTList: N->getVTList(), N1: Result_LO, N2: Result_HI);
1995}
1996
1997SDValue WebAssemblyTargetLowering::LowerCopyToReg(SDValue Op,
1998 SelectionDAG &DAG) const {
1999 SDValue Src = Op.getOperand(i: 2);
2000 if (isa<FrameIndexSDNode>(Val: Src.getNode())) {
2001 // CopyToReg nodes don't support FrameIndex operands. Other targets select
2002 // the FI to some LEA-like instruction, but since we don't have that, we
2003 // need to insert some kind of instruction that can take an FI operand and
2004 // produces a value usable by CopyToReg (i.e. in a vreg). So insert a dummy
2005 // local.copy between Op and its FI operand.
2006 SDValue Chain = Op.getOperand(i: 0);
2007 SDLoc DL(Op);
2008 Register Reg = cast<RegisterSDNode>(Val: Op.getOperand(i: 1))->getReg();
2009 EVT VT = Src.getValueType();
2010 SDValue Copy(DAG.getMachineNode(Opcode: VT == MVT::i32 ? WebAssembly::COPY_I32
2011 : WebAssembly::COPY_I64,
2012 dl: DL, VT, Op1: Src),
2013 0);
2014 return Op.getNode()->getNumValues() == 1
2015 ? DAG.getCopyToReg(Chain, dl: DL, Reg, N: Copy)
2016 : DAG.getCopyToReg(Chain, dl: DL, Reg, N: Copy,
2017 Glue: Op.getNumOperands() == 4 ? Op.getOperand(i: 3)
2018 : SDValue());
2019 }
2020 return SDValue();
2021}
2022
2023SDValue WebAssemblyTargetLowering::LowerFrameIndex(SDValue Op,
2024 SelectionDAG &DAG) const {
2025 int FI = cast<FrameIndexSDNode>(Val&: Op)->getIndex();
2026 return DAG.getTargetFrameIndex(FI, VT: Op.getValueType());
2027}
2028
2029SDValue WebAssemblyTargetLowering::LowerRETURNADDR(SDValue Op,
2030 SelectionDAG &DAG) const {
2031 SDLoc DL(Op);
2032
2033 if (!Subtarget->getTargetTriple().isOSEmscripten()) {
2034 fail(DL, DAG,
2035 Msg: "Non-Emscripten WebAssembly hasn't implemented "
2036 "__builtin_return_address");
2037 return SDValue();
2038 }
2039
2040 unsigned Depth = Op.getConstantOperandVal(i: 0);
2041 MakeLibCallOptions CallOptions;
2042 return makeLibCall(DAG, LC: RTLIB::RETURN_ADDRESS, RetVT: Op.getValueType(),
2043 Ops: {DAG.getConstant(Val: Depth, DL, VT: MVT::i32)}, CallOptions, dl: DL)
2044 .first;
2045}
2046
2047SDValue WebAssemblyTargetLowering::LowerFRAMEADDR(SDValue Op,
2048 SelectionDAG &DAG) const {
2049 // Non-zero depths are not supported by WebAssembly currently. Use the
2050 // legalizer's default expansion, which is to return 0 (what this function is
2051 // documented to do).
2052 if (Op.getConstantOperandVal(i: 0) > 0)
2053 return SDValue();
2054
2055 DAG.getMachineFunction().getFrameInfo().setFrameAddressIsTaken(true);
2056 EVT VT = Op.getValueType();
2057 Register FP =
2058 Subtarget->getRegisterInfo()->getFrameRegister(MF: DAG.getMachineFunction());
2059 return DAG.getCopyFromReg(Chain: DAG.getEntryNode(), dl: SDLoc(Op), Reg: FP, VT);
2060}
2061
2062SDValue
2063WebAssemblyTargetLowering::LowerGlobalTLSAddress(SDValue Op,
2064 SelectionDAG &DAG) const {
2065 SDLoc DL(Op);
2066 const auto *GA = cast<GlobalAddressSDNode>(Val&: Op);
2067
2068 MachineFunction &MF = DAG.getMachineFunction();
2069 if (!MF.getSubtarget<WebAssemblySubtarget>().hasBulkMemory())
2070 report_fatal_error(reason: "cannot use thread-local storage without bulk memory",
2071 gen_crash_diag: false);
2072
2073 const GlobalValue *GV = GA->getGlobal();
2074
2075 // Currently only Emscripten supports dynamic linking with threads. Therefore,
2076 // on other targets, if we have thread-local storage, only the local-exec
2077 // model is possible.
2078 auto model = Subtarget->getTargetTriple().isOSEmscripten()
2079 ? GV->getThreadLocalMode()
2080 : GlobalValue::LocalExecTLSModel;
2081
2082 // Unsupported TLS modes
2083 assert(model != GlobalValue::NotThreadLocal);
2084 assert(model != GlobalValue::InitialExecTLSModel);
2085
2086 if (model == GlobalValue::LocalExecTLSModel ||
2087 model == GlobalValue::LocalDynamicTLSModel ||
2088 (model == GlobalValue::GeneralDynamicTLSModel &&
2089 getTargetMachine().shouldAssumeDSOLocal(GV))) {
2090 // For DSO-local TLS variables we use offset from __tls_base, or
2091 // __wasm_get_tls_base() if using libcall thread context.
2092
2093 MVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
2094 SDValue BaseAddr(WebAssembly::getTLSBase(DAG, DL, Subtarget), 0);
2095
2096 SDValue TLSOffset = DAG.getTargetGlobalAddress(
2097 GV, DL, VT: PtrVT, offset: GA->getOffset(), TargetFlags: WebAssemblyII::MO_TLS_BASE_REL);
2098 SDValue SymOffset =
2099 DAG.getNode(Opcode: WebAssemblyISD::WrapperREL, DL, VT: PtrVT, Operand: TLSOffset);
2100
2101 return DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: BaseAddr, N2: SymOffset);
2102 }
2103
2104 assert(model == GlobalValue::GeneralDynamicTLSModel);
2105
2106 EVT VT = Op.getValueType();
2107 return DAG.getNode(Opcode: WebAssemblyISD::Wrapper, DL, VT,
2108 Operand: DAG.getTargetGlobalAddress(GV: GA->getGlobal(), DL, VT,
2109 offset: GA->getOffset(),
2110 TargetFlags: WebAssemblyII::MO_GOT_TLS));
2111}
2112
2113SDValue WebAssemblyTargetLowering::LowerGlobalAddress(SDValue Op,
2114 SelectionDAG &DAG) const {
2115 SDLoc DL(Op);
2116 const auto *GA = cast<GlobalAddressSDNode>(Val&: Op);
2117 EVT VT = Op.getValueType();
2118 assert(GA->getTargetFlags() == 0 &&
2119 "Unexpected target flags on generic GlobalAddressSDNode");
2120 if (!WebAssembly::isValidAddressSpace(AS: GA->getAddressSpace()))
2121 fail(DL, DAG, Msg: "Invalid address space for WebAssembly target");
2122
2123 unsigned OperandFlags = 0;
2124 const GlobalValue *GV = GA->getGlobal();
2125 // Since WebAssembly tables cannot yet be shared across modules, we don't
2126 // need special treatment for tables in PIC mode.
2127 if (isPositionIndependent() &&
2128 !WebAssembly::isWebAssemblyTableType(Ty: GV->getValueType())) {
2129 if (getTargetMachine().shouldAssumeDSOLocal(GV)) {
2130 MachineFunction &MF = DAG.getMachineFunction();
2131 MVT PtrVT = getPointerTy(DL: MF.getDataLayout());
2132 const char *BaseName;
2133 if (GV->getValueType()->isFunctionTy()) {
2134 BaseName = MF.createExternalSymbolName(Name: "__table_base");
2135 OperandFlags = WebAssemblyII::MO_TABLE_BASE_REL;
2136 } else {
2137 BaseName = MF.createExternalSymbolName(Name: "__memory_base");
2138 OperandFlags = WebAssemblyII::MO_MEMORY_BASE_REL;
2139 }
2140 SDValue BaseAddr =
2141 DAG.getNode(Opcode: WebAssemblyISD::Wrapper, DL, VT: PtrVT,
2142 Operand: DAG.getTargetExternalSymbol(Sym: BaseName, VT: PtrVT));
2143
2144 SDValue SymAddr = DAG.getNode(
2145 Opcode: WebAssemblyISD::WrapperREL, DL, VT,
2146 Operand: DAG.getTargetGlobalAddress(GV: GA->getGlobal(), DL, VT, offset: GA->getOffset(),
2147 TargetFlags: OperandFlags));
2148
2149 return DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: BaseAddr, N2: SymAddr);
2150 }
2151 OperandFlags = WebAssemblyII::MO_GOT;
2152 }
2153
2154 return DAG.getNode(Opcode: WebAssemblyISD::Wrapper, DL, VT,
2155 Operand: DAG.getTargetGlobalAddress(GV: GA->getGlobal(), DL, VT,
2156 offset: GA->getOffset(), TargetFlags: OperandFlags));
2157}
2158
2159SDValue
2160WebAssemblyTargetLowering::LowerExternalSymbol(SDValue Op,
2161 SelectionDAG &DAG) const {
2162 SDLoc DL(Op);
2163 const auto *ES = cast<ExternalSymbolSDNode>(Val&: Op);
2164 EVT VT = Op.getValueType();
2165 assert(ES->getTargetFlags() == 0 &&
2166 "Unexpected target flags on generic ExternalSymbolSDNode");
2167 return DAG.getNode(Opcode: WebAssemblyISD::Wrapper, DL, VT,
2168 Operand: DAG.getTargetExternalSymbol(Sym: ES->getSymbol(), VT));
2169}
2170
2171SDValue WebAssemblyTargetLowering::LowerJumpTable(SDValue Op,
2172 SelectionDAG &DAG) const {
2173 // There's no need for a Wrapper node because we always incorporate a jump
2174 // table operand into a BR_TABLE instruction, rather than ever
2175 // materializing it in a register.
2176 const JumpTableSDNode *JT = cast<JumpTableSDNode>(Val&: Op);
2177 return DAG.getTargetJumpTable(JTI: JT->getIndex(), VT: Op.getValueType(),
2178 TargetFlags: JT->getTargetFlags());
2179}
2180
2181SDValue WebAssemblyTargetLowering::LowerBR_JT(SDValue Op,
2182 SelectionDAG &DAG) const {
2183 SDLoc DL(Op);
2184 SDValue Chain = Op.getOperand(i: 0);
2185 const auto *JT = cast<JumpTableSDNode>(Val: Op.getOperand(i: 1));
2186 SDValue Index = Op.getOperand(i: 2);
2187 assert(JT->getTargetFlags() == 0 && "WebAssembly doesn't set target flags");
2188
2189 SmallVector<SDValue, 8> Ops;
2190 Ops.push_back(Elt: Chain);
2191 Ops.push_back(Elt: Index);
2192
2193 MachineJumpTableInfo *MJTI = DAG.getMachineFunction().getJumpTableInfo();
2194 const auto &MBBs = MJTI->getJumpTables()[JT->getIndex()].MBBs;
2195
2196 // Add an operand for each case.
2197 for (auto *MBB : MBBs)
2198 Ops.push_back(Elt: DAG.getBasicBlock(MBB));
2199
2200 // Add the first MBB as a dummy default target for now. This will be replaced
2201 // with the proper default target (and the preceding range check eliminated)
2202 // if possible by WebAssemblyFixBrTableDefaults.
2203 Ops.push_back(Elt: DAG.getBasicBlock(MBB: *MBBs.begin()));
2204 return DAG.getNode(Opcode: WebAssemblyISD::BR_TABLE, DL, VT: MVT::Other, Ops);
2205}
2206
2207SDValue WebAssemblyTargetLowering::LowerVASTART(SDValue Op,
2208 SelectionDAG &DAG) const {
2209 SDLoc DL(Op);
2210 EVT PtrVT = getPointerTy(DL: DAG.getMachineFunction().getDataLayout());
2211
2212 auto *MFI = DAG.getMachineFunction().getInfo<WebAssemblyFunctionInfo>();
2213 const Value *SV = cast<SrcValueSDNode>(Val: Op.getOperand(i: 2))->getValue();
2214
2215 SDValue ArgN = DAG.getCopyFromReg(Chain: DAG.getEntryNode(), dl: DL,
2216 Reg: MFI->getVarargBufferVreg(), VT: PtrVT);
2217 return DAG.getStore(Chain: Op.getOperand(i: 0), dl: DL, Val: ArgN, Ptr: Op.getOperand(i: 1),
2218 PtrInfo: MachinePointerInfo(SV));
2219}
2220
2221SDValue WebAssemblyTargetLowering::LowerIntrinsic(SDValue Op,
2222 SelectionDAG &DAG) const {
2223 MachineFunction &MF = DAG.getMachineFunction();
2224 unsigned IntNo;
2225 switch (Op.getOpcode()) {
2226 case ISD::INTRINSIC_VOID:
2227 case ISD::INTRINSIC_W_CHAIN:
2228 IntNo = Op.getConstantOperandVal(i: 1);
2229 break;
2230 case ISD::INTRINSIC_WO_CHAIN:
2231 IntNo = Op.getConstantOperandVal(i: 0);
2232 break;
2233 default:
2234 llvm_unreachable("Invalid intrinsic");
2235 }
2236 SDLoc DL(Op);
2237
2238 switch (IntNo) {
2239 default:
2240 return SDValue(); // Don't custom lower most intrinsics.
2241
2242 case Intrinsic::wasm_lsda: {
2243 auto PtrVT = getPointerTy(DL: MF.getDataLayout());
2244 const char *SymName = MF.createExternalSymbolName(
2245 Name: "GCC_except_table" + std::to_string(val: MF.getFunctionNumber()));
2246 if (isPositionIndependent()) {
2247 SDValue Node = DAG.getTargetExternalSymbol(
2248 Sym: SymName, VT: PtrVT, TargetFlags: WebAssemblyII::MO_MEMORY_BASE_REL);
2249 const char *BaseName = MF.createExternalSymbolName(Name: "__memory_base");
2250 SDValue BaseAddr =
2251 DAG.getNode(Opcode: WebAssemblyISD::Wrapper, DL, VT: PtrVT,
2252 Operand: DAG.getTargetExternalSymbol(Sym: BaseName, VT: PtrVT));
2253 SDValue SymAddr =
2254 DAG.getNode(Opcode: WebAssemblyISD::WrapperREL, DL, VT: PtrVT, Operand: Node);
2255 return DAG.getNode(Opcode: ISD::ADD, DL, VT: PtrVT, N1: BaseAddr, N2: SymAddr);
2256 }
2257 SDValue Node = DAG.getTargetExternalSymbol(Sym: SymName, VT: PtrVT);
2258 return DAG.getNode(Opcode: WebAssemblyISD::Wrapper, DL, VT: PtrVT, Operand: Node);
2259 }
2260
2261 case Intrinsic::wasm_shuffle: {
2262 // Drop in-chain and replace undefs, but otherwise pass through unchanged
2263 SDValue Ops[18];
2264 size_t OpIdx = 0;
2265 Ops[OpIdx++] = Op.getOperand(i: 1);
2266 Ops[OpIdx++] = Op.getOperand(i: 2);
2267 while (OpIdx < 18) {
2268 const SDValue &MaskIdx = Op.getOperand(i: OpIdx + 1);
2269 if (MaskIdx.isUndef() || MaskIdx.getNode()->getAsZExtVal() >= 32) {
2270 bool isTarget = MaskIdx.getNode()->getOpcode() == ISD::TargetConstant;
2271 Ops[OpIdx++] = DAG.getConstant(Val: 0, DL, VT: MVT::i32, isTarget);
2272 } else {
2273 Ops[OpIdx++] = MaskIdx;
2274 }
2275 }
2276 return DAG.getNode(Opcode: WebAssemblyISD::SHUFFLE, DL, VT: Op.getValueType(), Ops);
2277 }
2278
2279 case Intrinsic::wasm_funcref_to_ptr: {
2280 // llvm.wasm.funcref.to_ptr only has a defined lowering when its result
2281 // feeds directly into an indirect call. Reaching here means the pointer
2282 // escapes a direct call. We haven't implemented conversion of a funcref
2283 // into a real function pointer so we crash if we get here.
2284 fail(DL, DAG,
2285 Msg: "a funcref can only be converted to a pointer to be directly called; "
2286 "the resulting pointer cannot otherwise be used");
2287 return DAG.getPOISON(VT: Op.getValueType());
2288 }
2289
2290 case Intrinsic::thread_pointer: {
2291 return SDValue(WebAssembly::getTLSBase(DAG, DL, Subtarget), 0);
2292 }
2293 }
2294}
2295
2296SDValue
2297WebAssemblyTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
2298 SelectionDAG &DAG) const {
2299 SDLoc DL(Op);
2300 // If sign extension operations are disabled, allow sext_inreg only if operand
2301 // is a vector extract of an i8 or i16 lane. SIMD does not depend on sign
2302 // extension operations, but allowing sext_inreg in this context lets us have
2303 // simple patterns to select extract_lane_s instructions. Expanding sext_inreg
2304 // everywhere would be simpler in this file, but would necessitate large and
2305 // brittle patterns to undo the expansion and select extract_lane_s
2306 // instructions.
2307 assert(!Subtarget->hasSignExt() && Subtarget->hasSIMD128());
2308 if (Op.getOperand(i: 0).getOpcode() != ISD::EXTRACT_VECTOR_ELT)
2309 return SDValue();
2310
2311 const SDValue &Extract = Op.getOperand(i: 0);
2312 MVT VecT = Extract.getOperand(i: 0).getSimpleValueType();
2313 if (VecT.getVectorElementType().getSizeInBits() > 32)
2314 return SDValue();
2315 MVT ExtractedLaneT =
2316 cast<VTSDNode>(Val: Op.getOperand(i: 1).getNode())->getVT().getSimpleVT();
2317 MVT ExtractedVecT =
2318 MVT::getVectorVT(VT: ExtractedLaneT, NumElements: 128 / ExtractedLaneT.getSizeInBits());
2319 if (ExtractedVecT == VecT)
2320 return Op;
2321
2322 // Bitcast vector to appropriate type to ensure ISel pattern coverage
2323 const SDNode *Index = Extract.getOperand(i: 1).getNode();
2324 if (!isa<ConstantSDNode>(Val: Index))
2325 return SDValue();
2326 unsigned IndexVal = Index->getAsZExtVal();
2327 unsigned Scale =
2328 ExtractedVecT.getVectorNumElements() / VecT.getVectorNumElements();
2329 assert(Scale > 1);
2330 SDValue NewIndex =
2331 DAG.getConstant(Val: IndexVal * Scale, DL, VT: Index->getValueType(ResNo: 0));
2332 SDValue NewExtract = DAG.getNode(
2333 Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: Extract.getValueType(),
2334 N1: DAG.getBitcast(VT: ExtractedVecT, V: Extract.getOperand(i: 0)), N2: NewIndex);
2335 return DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL, VT: Op.getValueType(), N1: NewExtract,
2336 N2: Op.getOperand(i: 1));
2337}
2338
2339static SDValue GetExtendHigh(SDValue Op, unsigned UserOpc, EVT VT,
2340 SelectionDAG &DAG) {
2341 SDValue Source = peekThroughBitcasts(V: Op);
2342 if (Source.getOpcode() != ISD::VECTOR_SHUFFLE)
2343 return SDValue();
2344
2345 assert((UserOpc == WebAssemblyISD::EXTEND_LOW_U ||
2346 UserOpc == WebAssemblyISD::EXTEND_LOW_S) &&
2347 "expected extend_low");
2348 auto *Shuffle = cast<ShuffleVectorSDNode>(Val: Source.getNode());
2349
2350 ArrayRef<int> Mask = Shuffle->getMask();
2351 // Look for a shuffle which moves from the high half to the low half.
2352 size_t FirstIdx = Mask.size() / 2;
2353 for (size_t i = 0; i < Mask.size() / 2; ++i) {
2354 if (Mask[i] != static_cast<int>(FirstIdx + i)) {
2355 return SDValue();
2356 }
2357 }
2358
2359 SDLoc DL(Op);
2360 unsigned Opc = UserOpc == WebAssemblyISD::EXTEND_LOW_S
2361 ? WebAssemblyISD::EXTEND_HIGH_S
2362 : WebAssemblyISD::EXTEND_HIGH_U;
2363 SDValue ShuffleSrc = Shuffle->getOperand(Num: 0);
2364 if (Op.getOpcode() == ISD::BITCAST)
2365 ShuffleSrc = DAG.getBitcast(VT: Op.getValueType(), V: ShuffleSrc);
2366
2367 return DAG.getNode(Opcode: Opc, DL, VT, Operand: ShuffleSrc);
2368}
2369
2370SDValue
2371WebAssemblyTargetLowering::LowerEXTEND_VECTOR_INREG(SDValue Op,
2372 SelectionDAG &DAG) const {
2373 SDLoc DL(Op);
2374 EVT VT = Op.getValueType();
2375 SDValue Src = Op.getOperand(i: 0);
2376 EVT SrcVT = Src.getValueType();
2377
2378 if (SrcVT.getVectorElementType() == MVT::i1 ||
2379 SrcVT.getVectorElementType() == MVT::i64)
2380 return SDValue();
2381
2382 assert(VT.getScalarSizeInBits() % SrcVT.getScalarSizeInBits() == 0 &&
2383 "Unexpected extension factor.");
2384 unsigned Scale = VT.getScalarSizeInBits() / SrcVT.getScalarSizeInBits();
2385
2386 if (Scale != 2 && Scale != 4 && Scale != 8)
2387 return SDValue();
2388
2389 unsigned Ext;
2390 switch (Op.getOpcode()) {
2391 default:
2392 llvm_unreachable("unexpected opcode");
2393 case ISD::ANY_EXTEND_VECTOR_INREG:
2394 case ISD::ZERO_EXTEND_VECTOR_INREG:
2395 Ext = WebAssemblyISD::EXTEND_LOW_U;
2396 break;
2397 case ISD::SIGN_EXTEND_VECTOR_INREG:
2398 Ext = WebAssemblyISD::EXTEND_LOW_S;
2399 break;
2400 }
2401
2402 if (Scale == 2) {
2403 // See if we can use EXTEND_HIGH.
2404 if (auto ExtendHigh = GetExtendHigh(Op: Op.getOperand(i: 0), UserOpc: Ext, VT, DAG))
2405 return ExtendHigh;
2406 }
2407
2408 SDValue Ret = Src;
2409 while (Scale != 1) {
2410 Ret = DAG.getNode(Opcode: Ext, DL,
2411 VT: Ret.getValueType()
2412 .widenIntegerVectorElementType(Context&: *DAG.getContext())
2413 .getHalfNumVectorElementsVT(Context&: *DAG.getContext()),
2414 Operand: Ret);
2415 Scale /= 2;
2416 }
2417 assert(Ret.getValueType() == VT);
2418 return Ret;
2419}
2420
2421static SDValue LowerConvertLow(SDValue Op, SelectionDAG &DAG) {
2422 SDLoc DL(Op);
2423 if (Op.getValueType() != MVT::v2f64 && Op.getValueType() != MVT::v4f32)
2424 return SDValue();
2425
2426 auto GetConvertedLane = [](SDValue Op, unsigned &Opcode, SDValue &SrcVec,
2427 unsigned &Index) -> bool {
2428 switch (Op.getOpcode()) {
2429 case ISD::SINT_TO_FP:
2430 Opcode = WebAssemblyISD::CONVERT_LOW_S;
2431 break;
2432 case ISD::UINT_TO_FP:
2433 Opcode = WebAssemblyISD::CONVERT_LOW_U;
2434 break;
2435 case ISD::FP_EXTEND:
2436 case ISD::FP16_TO_FP:
2437 Opcode = WebAssemblyISD::PROMOTE_LOW;
2438 break;
2439 default:
2440 return false;
2441 }
2442
2443 auto ExtractVector = Op.getOperand(i: 0);
2444 if (ExtractVector.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
2445 return false;
2446
2447 if (!isa<ConstantSDNode>(Val: ExtractVector.getOperand(i: 1).getNode()))
2448 return false;
2449
2450 SrcVec = ExtractVector.getOperand(i: 0);
2451 Index = ExtractVector.getConstantOperandVal(i: 1);
2452 return true;
2453 };
2454
2455 unsigned NumLanes = Op.getValueType() == MVT::v2f64 ? 2 : 4;
2456 unsigned FirstOpcode = 0, SecondOpcode = 0, ThirdOpcode = 0, FourthOpcode = 0;
2457 unsigned FirstIndex = 0, SecondIndex = 0, ThirdIndex = 0, FourthIndex = 0;
2458 SDValue FirstSrcVec, SecondSrcVec, ThirdSrcVec, FourthSrcVec;
2459
2460 if (!GetConvertedLane(Op.getOperand(i: 0), FirstOpcode, FirstSrcVec,
2461 FirstIndex) ||
2462 !GetConvertedLane(Op.getOperand(i: 1), SecondOpcode, SecondSrcVec,
2463 SecondIndex))
2464 return SDValue();
2465
2466 // If we're converting to v4f32, check the third and fourth lanes, too.
2467 if (NumLanes == 4 && (!GetConvertedLane(Op.getOperand(i: 2), ThirdOpcode,
2468 ThirdSrcVec, ThirdIndex) ||
2469 !GetConvertedLane(Op.getOperand(i: 3), FourthOpcode,
2470 FourthSrcVec, FourthIndex)))
2471 return SDValue();
2472
2473 if (FirstOpcode != SecondOpcode)
2474 return SDValue();
2475
2476 // TODO Add an optimization similar to the v2f64 below for shuffling the
2477 // vectors when the lanes are in the wrong order or come from different src
2478 // vectors.
2479 if (NumLanes == 4 &&
2480 (FirstOpcode != ThirdOpcode || FirstOpcode != FourthOpcode ||
2481 FirstSrcVec != SecondSrcVec || FirstSrcVec != ThirdSrcVec ||
2482 FirstSrcVec != FourthSrcVec || FirstIndex != 0 || SecondIndex != 1 ||
2483 ThirdIndex != 2 || FourthIndex != 3))
2484 return SDValue();
2485
2486 MVT ExpectedSrcVT;
2487 switch (FirstOpcode) {
2488 case WebAssemblyISD::CONVERT_LOW_S:
2489 case WebAssemblyISD::CONVERT_LOW_U:
2490 ExpectedSrcVT = MVT::v4i32;
2491 break;
2492 case WebAssemblyISD::PROMOTE_LOW:
2493 ExpectedSrcVT = NumLanes == 2 ? MVT::v4f32 : MVT::v8i16;
2494 break;
2495 }
2496 if (FirstSrcVec.getValueType() != ExpectedSrcVT)
2497 return SDValue();
2498
2499 auto Src = FirstSrcVec;
2500 if (NumLanes == 2 &&
2501 (FirstIndex != 0 || SecondIndex != 1 || FirstSrcVec != SecondSrcVec)) {
2502 // Shuffle the source vector so that the converted lanes are the low lanes.
2503 Src = DAG.getVectorShuffle(VT: ExpectedSrcVT, dl: DL, N1: FirstSrcVec, N2: SecondSrcVec,
2504 Mask: {static_cast<int>(FirstIndex),
2505 static_cast<int>(SecondIndex) + 4, -1, -1});
2506 }
2507 return DAG.getNode(Opcode: FirstOpcode, DL, VT: NumLanes == 2 ? MVT::v2f64 : MVT::v4f32,
2508 Operand: Src);
2509}
2510
2511SDValue WebAssemblyTargetLowering::LowerBUILD_VECTOR(SDValue Op,
2512 SelectionDAG &DAG) const {
2513 MVT VT = Op.getSimpleValueType();
2514 if (VT == MVT::v8f16) {
2515 // BUILD_VECTOR can't handle FP16 operands since Wasm doesn't have a scalar
2516 // FP16 type, so cast them to I16s.
2517 MVT IVT = VT.changeVectorElementType(EltVT: MVT::i16);
2518 SmallVector<SDValue, 8> NewOps;
2519 for (unsigned I = 0, E = Op.getNumOperands(); I < E; ++I)
2520 NewOps.push_back(Elt: DAG.getBitcast(VT: MVT::i16, V: Op.getOperand(i: I)));
2521 SDValue Res = DAG.getNode(Opcode: ISD::BUILD_VECTOR, DL: SDLoc(), VT: IVT, Ops: NewOps);
2522 return DAG.getBitcast(VT, V: Res);
2523 }
2524
2525 if (auto ConvertLow = LowerConvertLow(Op, DAG))
2526 return ConvertLow;
2527
2528 SDLoc DL(Op);
2529 const EVT VecT = Op.getValueType();
2530 const EVT LaneT = Op.getOperand(i: 0).getValueType();
2531 const size_t Lanes = Op.getNumOperands();
2532 bool CanSwizzle = VecT == MVT::v16i8;
2533
2534 // BUILD_VECTORs are lowered to the instruction that initializes the highest
2535 // possible number of lanes at once followed by a sequence of replace_lane
2536 // instructions to individually initialize any remaining lanes.
2537
2538 // TODO: Tune this. For example, lanewise swizzling is very expensive, so
2539 // swizzled lanes should be given greater weight.
2540
2541 // TODO: Investigate looping rather than always extracting/replacing specific
2542 // lanes to fill gaps.
2543
2544 auto IsConstant = [](const SDValue &V) {
2545 return V.getOpcode() == ISD::Constant || V.getOpcode() == ISD::ConstantFP;
2546 };
2547
2548 // Returns the source vector and index vector pair if they exist. Checks for:
2549 // (extract_vector_elt
2550 // $src,
2551 // (sign_extend_inreg (extract_vector_elt $indices, $i))
2552 // )
2553 auto GetSwizzleSrcs = [](size_t I, const SDValue &Lane) {
2554 auto Bail = std::make_pair(x: SDValue(), y: SDValue());
2555 if (Lane->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
2556 return Bail;
2557 const SDValue &SwizzleSrc = Lane->getOperand(Num: 0);
2558 const SDValue &IndexExt = Lane->getOperand(Num: 1);
2559 if (IndexExt->getOpcode() != ISD::SIGN_EXTEND_INREG)
2560 return Bail;
2561 const SDValue &Index = IndexExt->getOperand(Num: 0);
2562 if (Index->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
2563 return Bail;
2564 const SDValue &SwizzleIndices = Index->getOperand(Num: 0);
2565 if (SwizzleSrc.getValueType() != MVT::v16i8 ||
2566 SwizzleIndices.getValueType() != MVT::v16i8 ||
2567 Index->getOperand(Num: 1)->getOpcode() != ISD::Constant ||
2568 Index->getConstantOperandVal(Num: 1) != I)
2569 return Bail;
2570 return std::make_pair(x: SwizzleSrc, y: SwizzleIndices);
2571 };
2572
2573 // If the lane is extracted from another vector at a constant index, return
2574 // that vector. The source vector must not have more lanes than the dest
2575 // because the shufflevector indices are in terms of the destination lanes and
2576 // would not be able to address the smaller individual source lanes.
2577 auto GetShuffleSrc = [&](const SDValue &Lane) {
2578 if (Lane->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
2579 return SDValue();
2580 if (!isa<ConstantSDNode>(Val: Lane->getOperand(Num: 1).getNode()))
2581 return SDValue();
2582 if (Lane->getOperand(Num: 0).getValueType().getVectorNumElements() >
2583 VecT.getVectorNumElements())
2584 return SDValue();
2585 return Lane->getOperand(Num: 0);
2586 };
2587
2588 using ValueEntry = std::pair<SDValue, size_t>;
2589 SmallVector<ValueEntry, 16> SplatValueCounts;
2590
2591 using SwizzleEntry = std::pair<std::pair<SDValue, SDValue>, size_t>;
2592 SmallVector<SwizzleEntry, 16> SwizzleCounts;
2593
2594 using ShuffleEntry = std::pair<SDValue, size_t>;
2595 SmallVector<ShuffleEntry, 16> ShuffleCounts;
2596
2597 auto AddCount = [](auto &Counts, const auto &Val) {
2598 auto CountIt =
2599 llvm::find_if(Counts, [&Val](auto E) { return E.first == Val; });
2600 if (CountIt == Counts.end()) {
2601 Counts.emplace_back(Val, 1);
2602 } else {
2603 CountIt->second++;
2604 }
2605 };
2606
2607 auto GetMostCommon = [](auto &Counts) {
2608 auto CommonIt = llvm::max_element(Counts, llvm::less_second());
2609 assert(CommonIt != Counts.end() && "Unexpected all-undef build_vector");
2610 return *CommonIt;
2611 };
2612
2613 size_t NumConstantLanes = 0;
2614
2615 // Count eligible lanes for each type of vector creation op
2616 for (size_t I = 0; I < Lanes; ++I) {
2617 const SDValue &Lane = Op->getOperand(Num: I);
2618 if (Lane.isUndef())
2619 continue;
2620
2621 AddCount(SplatValueCounts, Lane);
2622
2623 if (IsConstant(Lane))
2624 NumConstantLanes++;
2625 if (auto ShuffleSrc = GetShuffleSrc(Lane))
2626 AddCount(ShuffleCounts, ShuffleSrc);
2627 if (CanSwizzle) {
2628 auto SwizzleSrcs = GetSwizzleSrcs(I, Lane);
2629 if (SwizzleSrcs.first)
2630 AddCount(SwizzleCounts, SwizzleSrcs);
2631 }
2632 }
2633
2634 SDValue SplatValue;
2635 size_t NumSplatLanes;
2636 std::tie(args&: SplatValue, args&: NumSplatLanes) = GetMostCommon(SplatValueCounts);
2637
2638 SDValue SwizzleSrc;
2639 SDValue SwizzleIndices;
2640 size_t NumSwizzleLanes = 0;
2641 if (SwizzleCounts.size())
2642 std::forward_as_tuple(args: std::tie(args&: SwizzleSrc, args&: SwizzleIndices),
2643 args&: NumSwizzleLanes) = GetMostCommon(SwizzleCounts);
2644
2645 // Shuffles can draw from up to two vectors, so find the two most common
2646 // sources.
2647 SDValue ShuffleSrc1, ShuffleSrc2;
2648 size_t NumShuffleLanes = 0;
2649 if (ShuffleCounts.size()) {
2650 std::tie(args&: ShuffleSrc1, args&: NumShuffleLanes) = GetMostCommon(ShuffleCounts);
2651 llvm::erase_if(C&: ShuffleCounts,
2652 P: [&](const auto &Pair) { return Pair.first == ShuffleSrc1; });
2653 }
2654 if (ShuffleCounts.size()) {
2655 size_t AdditionalShuffleLanes;
2656 std::tie(args&: ShuffleSrc2, args&: AdditionalShuffleLanes) =
2657 GetMostCommon(ShuffleCounts);
2658 NumShuffleLanes += AdditionalShuffleLanes;
2659 }
2660
2661 // Predicate returning true if the lane is properly initialized by the
2662 // original instruction
2663 std::function<bool(size_t, const SDValue &)> IsLaneConstructed;
2664 SDValue Result;
2665 // Prefer swizzles over shuffles over vector consts over splats
2666 if (NumSwizzleLanes >= NumShuffleLanes &&
2667 NumSwizzleLanes >= NumConstantLanes && NumSwizzleLanes >= NumSplatLanes) {
2668 Result = DAG.getNode(Opcode: WebAssemblyISD::SWIZZLE, DL, VT: VecT, N1: SwizzleSrc,
2669 N2: SwizzleIndices);
2670 auto Swizzled = std::make_pair(x&: SwizzleSrc, y&: SwizzleIndices);
2671 IsLaneConstructed = [&, Swizzled](size_t I, const SDValue &Lane) {
2672 return Swizzled == GetSwizzleSrcs(I, Lane);
2673 };
2674 } else if (NumShuffleLanes >= NumConstantLanes &&
2675 NumShuffleLanes >= NumSplatLanes) {
2676 size_t DestLaneSize = VecT.getVectorElementType().getFixedSizeInBits() / 8;
2677 size_t DestLaneCount = VecT.getVectorNumElements();
2678 size_t Scale1 = 1;
2679 size_t Scale2 = 1;
2680 SDValue Src1 = ShuffleSrc1;
2681 SDValue Src2 = ShuffleSrc2 ? ShuffleSrc2 : DAG.getUNDEF(VT: VecT);
2682 if (Src1.getValueType() != VecT) {
2683 size_t LaneSize =
2684 Src1.getValueType().getVectorElementType().getFixedSizeInBits() / 8;
2685 assert(LaneSize > DestLaneSize);
2686 Scale1 = LaneSize / DestLaneSize;
2687 Src1 = DAG.getBitcast(VT: VecT, V: Src1);
2688 }
2689 if (Src2.getValueType() != VecT) {
2690 size_t LaneSize =
2691 Src2.getValueType().getVectorElementType().getFixedSizeInBits() / 8;
2692 assert(LaneSize > DestLaneSize);
2693 Scale2 = LaneSize / DestLaneSize;
2694 Src2 = DAG.getBitcast(VT: VecT, V: Src2);
2695 }
2696
2697 int Mask[16];
2698 assert(DestLaneCount <= 16);
2699 for (size_t I = 0; I < DestLaneCount; ++I) {
2700 const SDValue &Lane = Op->getOperand(Num: I);
2701 SDValue Src = GetShuffleSrc(Lane);
2702 if (Src == ShuffleSrc1) {
2703 Mask[I] = Lane->getConstantOperandVal(Num: 1) * Scale1;
2704 } else if (Src && Src == ShuffleSrc2) {
2705 Mask[I] = DestLaneCount + Lane->getConstantOperandVal(Num: 1) * Scale2;
2706 } else {
2707 Mask[I] = -1;
2708 }
2709 }
2710 ArrayRef<int> MaskRef(Mask, DestLaneCount);
2711 Result = DAG.getVectorShuffle(VT: VecT, dl: DL, N1: Src1, N2: Src2, Mask: MaskRef);
2712 IsLaneConstructed = [&](size_t, const SDValue &Lane) {
2713 auto Src = GetShuffleSrc(Lane);
2714 return Src == ShuffleSrc1 || (Src && Src == ShuffleSrc2);
2715 };
2716 } else if (NumConstantLanes >= NumSplatLanes) {
2717 SmallVector<SDValue, 16> ConstLanes;
2718 for (const SDValue &Lane : Op->op_values()) {
2719 if (IsConstant(Lane)) {
2720 // Values may need to be fixed so that they will sign extend to be
2721 // within the expected range during ISel. Check whether the value is in
2722 // bounds based on the lane bit width and if it is out of bounds, lop
2723 // off the extra bits.
2724 uint64_t LaneBits = 128 / Lanes;
2725 if (auto *Const = dyn_cast<ConstantSDNode>(Val: Lane.getNode())) {
2726 ConstLanes.push_back(Elt: DAG.getConstant(
2727 Val: Const->getAPIntValue().trunc(width: LaneBits).getZExtValue(),
2728 DL: SDLoc(Lane), VT: LaneT));
2729 } else {
2730 ConstLanes.push_back(Elt: Lane);
2731 }
2732 } else if (LaneT.isFloatingPoint()) {
2733 ConstLanes.push_back(Elt: DAG.getConstantFP(Val: 0, DL, VT: LaneT));
2734 } else {
2735 ConstLanes.push_back(Elt: DAG.getConstant(Val: 0, DL, VT: LaneT));
2736 }
2737 }
2738 Result = DAG.getBuildVector(VT: VecT, DL, Ops: ConstLanes);
2739 IsLaneConstructed = [&IsConstant](size_t _, const SDValue &Lane) {
2740 return IsConstant(Lane);
2741 };
2742 } else {
2743 size_t DestLaneSize = VecT.getVectorElementType().getFixedSizeInBits();
2744 if (NumSplatLanes == 1 && Op->getOperand(Num: 0) == SplatValue &&
2745 (DestLaneSize == 32 || DestLaneSize == 64)) {
2746 // Could be selected to load_zero.
2747 Result = DAG.getNode(Opcode: ISD::SCALAR_TO_VECTOR, DL, VT: VecT, Operand: SplatValue);
2748 } else {
2749 // Use a splat (which might be selected as a load splat)
2750 Result = DAG.getSplatBuildVector(VT: VecT, DL, Op: SplatValue);
2751 }
2752 IsLaneConstructed = [&SplatValue](size_t _, const SDValue &Lane) {
2753 return Lane == SplatValue;
2754 };
2755 }
2756
2757 assert(Result);
2758 assert(IsLaneConstructed);
2759
2760 // Add replace_lane instructions for any unhandled values
2761 for (size_t I = 0; I < Lanes; ++I) {
2762 const SDValue &Lane = Op->getOperand(Num: I);
2763 if (!Lane.isUndef() && !IsLaneConstructed(I, Lane))
2764 Result = DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL, VT: VecT, N1: Result, N2: Lane,
2765 N3: DAG.getConstant(Val: I, DL, VT: MVT::i32));
2766 }
2767
2768 return Result;
2769}
2770
2771SDValue
2772WebAssemblyTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
2773 SelectionDAG &DAG) const {
2774 SDLoc DL(Op);
2775 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Val: Op.getNode())->getMask();
2776 MVT VecType = Op.getOperand(i: 0).getSimpleValueType();
2777 assert(VecType.is128BitVector() && "Unexpected shuffle vector type");
2778 size_t LaneBytes = VecType.getVectorElementType().getSizeInBits() / 8;
2779
2780 // Space for two vector args and sixteen mask indices
2781 SDValue Ops[18];
2782 size_t OpIdx = 0;
2783 Ops[OpIdx++] = Op.getOperand(i: 0);
2784 Ops[OpIdx++] = Op.getOperand(i: 1);
2785
2786 // Expand mask indices to byte indices and materialize them as operands
2787 for (int M : Mask) {
2788 for (size_t J = 0; J < LaneBytes; ++J) {
2789 // Lower undefs (represented by -1 in mask) to {0..J}, which use a
2790 // whole lane of vector input, to allow further reduction at VM. E.g.
2791 // match an 8x16 byte shuffle to an equivalent cheaper 32x4 shuffle.
2792 uint64_t ByteIndex = M == -1 ? J : (uint64_t)M * LaneBytes + J;
2793 Ops[OpIdx++] = DAG.getConstant(Val: ByteIndex, DL, VT: MVT::i32);
2794 }
2795 }
2796
2797 return DAG.getNode(Opcode: WebAssemblyISD::SHUFFLE, DL, VT: Op.getValueType(), Ops);
2798}
2799
2800SDValue WebAssemblyTargetLowering::LowerSETCC(SDValue Op,
2801 SelectionDAG &DAG) const {
2802 SDLoc DL(Op);
2803 // The legalizer does not know how to expand the unsupported comparison modes
2804 // of i64x2 vectors, so we manually unroll them here.
2805 assert(Op->getOperand(0)->getSimpleValueType(0) == MVT::v2i64);
2806 SmallVector<SDValue, 2> LHS, RHS;
2807 DAG.ExtractVectorElements(Op: Op->getOperand(Num: 0), Args&: LHS);
2808 DAG.ExtractVectorElements(Op: Op->getOperand(Num: 1), Args&: RHS);
2809 const SDValue &CC = Op->getOperand(Num: 2);
2810 auto MakeLane = [&](unsigned I) {
2811 return DAG.getNode(Opcode: ISD::SELECT_CC, DL, VT: MVT::i64, N1: LHS[I], N2: RHS[I],
2812 N3: DAG.getConstant(Val: uint64_t(-1), DL, VT: MVT::i64),
2813 N4: DAG.getConstant(Val: uint64_t(0), DL, VT: MVT::i64), N5: CC);
2814 };
2815 return DAG.getBuildVector(VT: Op->getValueType(ResNo: 0), DL,
2816 Ops: {MakeLane(0), MakeLane(1)});
2817}
2818
2819SDValue
2820WebAssemblyTargetLowering::LowerAccessVectorElement(SDValue Op,
2821 SelectionDAG &DAG) const {
2822 if (Op.getOpcode() == ISD::INSERT_VECTOR_ELT &&
2823 Op.getValueType() == MVT::v8f16) {
2824 // INSERT_VECTOR_ELT can't handle FP16 operands since Wasm doesn't have a
2825 // scalar FP16 type, so cast them to I16s.
2826 SDLoc DL(Op);
2827 SDValue IntVector = DAG.getBitcast(VT: MVT::v8i16, V: Op.getOperand(i: 0));
2828 SDValue IntElement = DAG.getBitcast(VT: MVT::i16, V: Op.getOperand(i: 1));
2829 SDValue Inserted = DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL, VT: MVT::v8i16,
2830 N1: IntVector, N2: IntElement, N3: Op.getOperand(i: 2));
2831 return DAG.getBitcast(VT: MVT::v8f16, V: Inserted);
2832 }
2833
2834 // Allow constant lane indices, expand variable lane indices
2835 SDNode *IdxNode = Op.getOperand(i: Op.getNumOperands() - 1).getNode();
2836 if (isa<ConstantSDNode>(Val: IdxNode)) {
2837 // Ensure the index type is i32 to match the tablegen patterns
2838 uint64_t Idx = IdxNode->getAsZExtVal();
2839 SmallVector<SDValue, 3> Ops(Op.getNode()->ops());
2840 Ops[Op.getNumOperands() - 1] =
2841 DAG.getConstant(Val: Idx, DL: SDLoc(IdxNode), VT: MVT::i32);
2842 return DAG.getNode(Opcode: Op.getOpcode(), DL: SDLoc(Op), VT: Op.getValueType(), Ops);
2843 }
2844 // Perform default expansion
2845 return SDValue();
2846}
2847
2848static SDValue unrollVectorShift(SDValue Op, SelectionDAG &DAG) {
2849 EVT LaneT = Op.getSimpleValueType().getVectorElementType();
2850 // 32-bit and 64-bit unrolled shifts will have proper semantics
2851 if (LaneT.bitsGE(VT: MVT::i32))
2852 return DAG.UnrollVectorOp(N: Op.getNode());
2853 // Otherwise mask the shift value to get proper semantics from 32-bit shift
2854 SDLoc DL(Op);
2855 size_t NumLanes = Op.getSimpleValueType().getVectorNumElements();
2856 SDValue Mask = DAG.getConstant(Val: LaneT.getSizeInBits() - 1, DL, VT: MVT::i32);
2857 unsigned ShiftOpcode = Op.getOpcode();
2858 SmallVector<SDValue, 16> ShiftedElements;
2859 DAG.ExtractVectorElements(Op: Op.getOperand(i: 0), Args&: ShiftedElements, Start: 0, Count: 0, EltVT: MVT::i32);
2860 SmallVector<SDValue, 16> ShiftElements;
2861 DAG.ExtractVectorElements(Op: Op.getOperand(i: 1), Args&: ShiftElements, Start: 0, Count: 0, EltVT: MVT::i32);
2862 SmallVector<SDValue, 16> UnrolledOps;
2863 for (size_t i = 0; i < NumLanes; ++i) {
2864 SDValue MaskedShiftValue =
2865 DAG.getNode(Opcode: ISD::AND, DL, VT: MVT::i32, N1: ShiftElements[i], N2: Mask);
2866 SDValue ShiftedValue = ShiftedElements[i];
2867 if (ShiftOpcode == ISD::SRA)
2868 ShiftedValue = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL, VT: MVT::i32,
2869 N1: ShiftedValue, N2: DAG.getValueType(LaneT));
2870 UnrolledOps.push_back(
2871 Elt: DAG.getNode(Opcode: ShiftOpcode, DL, VT: MVT::i32, N1: ShiftedValue, N2: MaskedShiftValue));
2872 }
2873 return DAG.getBuildVector(VT: Op.getValueType(), DL, Ops: UnrolledOps);
2874}
2875
2876SDValue WebAssemblyTargetLowering::LowerShift(SDValue Op,
2877 SelectionDAG &DAG) const {
2878 SDLoc DL(Op);
2879 // Only manually lower vector shifts
2880 assert(Op.getSimpleValueType().isVector());
2881
2882 uint64_t LaneBits = Op.getValueType().getScalarSizeInBits();
2883 auto ShiftVal = Op.getOperand(i: 1);
2884
2885 // Try to skip bitmask operation since it is implied inside shift instruction
2886 auto SkipImpliedMask = [](SDValue MaskOp, uint64_t MaskBits) {
2887 if (MaskOp.getOpcode() != ISD::AND)
2888 return MaskOp;
2889 SDValue LHS = MaskOp.getOperand(i: 0);
2890 SDValue RHS = MaskOp.getOperand(i: 1);
2891 if (MaskOp.getValueType().isVector()) {
2892 APInt MaskVal;
2893 if (!ISD::isConstantSplatVector(N: RHS.getNode(), SplatValue&: MaskVal))
2894 std::swap(a&: LHS, b&: RHS);
2895
2896 if (ISD::isConstantSplatVector(N: RHS.getNode(), SplatValue&: MaskVal) &&
2897 MaskVal == MaskBits)
2898 MaskOp = LHS;
2899 } else {
2900 if (!isa<ConstantSDNode>(Val: RHS.getNode()))
2901 std::swap(a&: LHS, b&: RHS);
2902
2903 auto ConstantRHS = dyn_cast<ConstantSDNode>(Val: RHS.getNode());
2904 if (ConstantRHS && ConstantRHS->getAPIntValue() == MaskBits)
2905 MaskOp = LHS;
2906 }
2907
2908 return MaskOp;
2909 };
2910
2911 // Skip vector and operation
2912 ShiftVal = SkipImpliedMask(ShiftVal, LaneBits - 1);
2913 ShiftVal = DAG.getSplatValue(V: ShiftVal);
2914 if (!ShiftVal)
2915 return unrollVectorShift(Op, DAG);
2916
2917 // Skip scalar and operation
2918 ShiftVal = SkipImpliedMask(ShiftVal, LaneBits - 1);
2919 // Use anyext because none of the high bits can affect the shift
2920 ShiftVal = DAG.getAnyExtOrTrunc(Op: ShiftVal, DL, VT: MVT::i32);
2921
2922 unsigned Opcode;
2923 switch (Op.getOpcode()) {
2924 case ISD::SHL:
2925 Opcode = WebAssemblyISD::VEC_SHL;
2926 break;
2927 case ISD::SRA:
2928 Opcode = WebAssemblyISD::VEC_SHR_S;
2929 break;
2930 case ISD::SRL:
2931 Opcode = WebAssemblyISD::VEC_SHR_U;
2932 break;
2933 default:
2934 llvm_unreachable("unexpected opcode");
2935 }
2936
2937 return DAG.getNode(Opcode, DL, VT: Op.getValueType(), N1: Op.getOperand(i: 0), N2: ShiftVal);
2938}
2939
2940SDValue WebAssemblyTargetLowering::LowerFP_TO_INT_SAT(SDValue Op,
2941 SelectionDAG &DAG) const {
2942 EVT ResT = Op.getValueType();
2943 EVT SatVT = cast<VTSDNode>(Val: Op.getOperand(i: 1))->getVT();
2944
2945 if ((ResT == MVT::i32 || ResT == MVT::i64) &&
2946 (SatVT == MVT::i32 || SatVT == MVT::i64))
2947 return Op;
2948
2949 if (ResT == MVT::v4i32 && SatVT == MVT::i32)
2950 return Op;
2951
2952 if (ResT == MVT::v8i16 && SatVT == MVT::i16)
2953 return Op;
2954
2955 return SDValue();
2956}
2957
2958static bool HasNoSignedZerosOrNaNs(SDValue Op, SelectionDAG &DAG) {
2959 return (Op->getFlags().hasNoNaNs() ||
2960 (DAG.isKnownNeverNaN(Op: Op->getOperand(Num: 0)) &&
2961 DAG.isKnownNeverNaN(Op: Op->getOperand(Num: 1)))) &&
2962 (Op->getFlags().hasNoSignedZeros() ||
2963 DAG.isKnownNeverLogicalZero(Op: Op->getOperand(Num: 0)) ||
2964 DAG.isKnownNeverLogicalZero(Op: Op->getOperand(Num: 1)));
2965}
2966
2967SDValue WebAssemblyTargetLowering::LowerFMIN(SDValue Op,
2968 SelectionDAG &DAG) const {
2969 if (Subtarget->hasRelaxedSIMD() && HasNoSignedZerosOrNaNs(Op, DAG)) {
2970 return DAG.getNode(Opcode: WebAssemblyISD::RELAXED_FMIN, DL: SDLoc(Op),
2971 VT: Op.getValueType(), N1: Op.getOperand(i: 0), N2: Op.getOperand(i: 1));
2972 }
2973 return SDValue();
2974}
2975
2976SDValue WebAssemblyTargetLowering::LowerFMAX(SDValue Op,
2977 SelectionDAG &DAG) const {
2978 if (Subtarget->hasRelaxedSIMD() && HasNoSignedZerosOrNaNs(Op, DAG)) {
2979 return DAG.getNode(Opcode: WebAssemblyISD::RELAXED_FMAX, DL: SDLoc(Op),
2980 VT: Op.getValueType(), N1: Op.getOperand(i: 0), N2: Op.getOperand(i: 1));
2981 }
2982 return SDValue();
2983}
2984
2985//===----------------------------------------------------------------------===//
2986// Custom DAG combine hooks
2987//===----------------------------------------------------------------------===//
2988static SDValue
2989performVECTOR_SHUFFLECombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
2990 auto &DAG = DCI.DAG;
2991 auto Shuffle = cast<ShuffleVectorSDNode>(Val: N);
2992
2993 // Hoist vector bitcasts that don't change the number of lanes out of unary
2994 // shuffles, where they are less likely to get in the way of other combines.
2995 // (shuffle (vNxT1 (bitcast (vNxT0 x))), undef, mask) ->
2996 // (vNxT1 (bitcast (vNxT0 (shuffle x, undef, mask))))
2997 SDValue Bitcast = N->getOperand(Num: 0);
2998 if (Bitcast.getOpcode() != ISD::BITCAST)
2999 return SDValue();
3000 if (!N->getOperand(Num: 1).isUndef())
3001 return SDValue();
3002 SDValue CastOp = Bitcast.getOperand(i: 0);
3003 EVT SrcType = CastOp.getValueType();
3004 EVT DstType = Bitcast.getValueType();
3005 if (!SrcType.is128BitVector() ||
3006 SrcType.getVectorNumElements() != DstType.getVectorNumElements())
3007 return SDValue();
3008 SDValue NewShuffle = DAG.getVectorShuffle(
3009 VT: SrcType, dl: SDLoc(N), N1: CastOp, N2: DAG.getUNDEF(VT: SrcType), Mask: Shuffle->getMask());
3010 return DAG.getBitcast(VT: DstType, V: NewShuffle);
3011}
3012
3013/// Convert ({u,s}itofp vec) --> ({u,s}itofp ({s,z}ext vec)) so it doesn't get
3014/// split up into scalar instructions during legalization, and the vector
3015/// extending instructions are selected in performVectorExtendCombine below.
3016static SDValue
3017performVectorExtendToFPCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
3018 const WebAssemblySubtarget *Subtarget) {
3019 auto &DAG = DCI.DAG;
3020 assert(N->getOpcode() == ISD::UINT_TO_FP ||
3021 N->getOpcode() == ISD::SINT_TO_FP);
3022
3023 EVT InVT = N->getOperand(Num: 0)->getValueType(ResNo: 0);
3024 EVT ResVT = N->getValueType(ResNo: 0);
3025 MVT ExtVT;
3026 if (ResVT == MVT::v4f32 && (InVT == MVT::v4i16 || InVT == MVT::v4i8))
3027 ExtVT = MVT::v4i32;
3028 else if (ResVT == MVT::v2f64 && (InVT == MVT::v2i16 || InVT == MVT::v2i8))
3029 ExtVT = MVT::v2i32;
3030 else if (Subtarget->hasFP16() && ResVT == MVT::v8f16 && InVT == MVT::v8i8)
3031 ExtVT = MVT::v8i16;
3032 else
3033 return SDValue();
3034
3035 unsigned Op =
3036 N->getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
3037 SDValue Conv = DAG.getNode(Opcode: Op, DL: SDLoc(N), VT: ExtVT, Operand: N->getOperand(Num: 0));
3038 return DAG.getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: ResVT, Operand: Conv);
3039}
3040
3041static SDValue
3042performVectorNonNegToFPCombine(SDNode *N,
3043 TargetLowering::DAGCombinerInfo &DCI) {
3044 auto &DAG = DCI.DAG;
3045
3046 SDNodeFlags Flags = N->getFlags();
3047 SDValue Op0 = N->getOperand(Num: 0);
3048 EVT VT = N->getValueType(ResNo: 0);
3049
3050 // Optimize uitofp to sitofp when the sign bit is known to be zero.
3051 // Depending on the target (runtime) backend, this might be performance
3052 // neutral (e.g. AArch64) or a significant improvement (e.g. x86_64).
3053 if (VT.isVector() && (Flags.hasNonNeg() || DAG.SignBitIsZero(Op: Op0))) {
3054 return DAG.getNode(Opcode: ISD::SINT_TO_FP, DL: SDLoc(N), VT, Operand: Op0);
3055 }
3056
3057 return SDValue();
3058}
3059
3060static SDValue
3061performVectorExtendCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
3062 auto &DAG = DCI.DAG;
3063 assert(N->getOpcode() == ISD::SIGN_EXTEND ||
3064 N->getOpcode() == ISD::ZERO_EXTEND);
3065
3066 EVT ResVT = N->getValueType(ResNo: 0);
3067 bool IsSext = N->getOpcode() == ISD::SIGN_EXTEND;
3068 SDLoc DL(N);
3069
3070 if (ResVT == MVT::v16i32 && N->getOperand(Num: 0)->getValueType(ResNo: 0) == MVT::v16i8) {
3071 // Use a tree of extend low/high to split and extend the input in two
3072 // layers to avoid doing several shuffles and even more extends.
3073 unsigned LowOp =
3074 IsSext ? WebAssemblyISD::EXTEND_LOW_S : WebAssemblyISD::EXTEND_LOW_U;
3075 unsigned HighOp =
3076 IsSext ? WebAssemblyISD::EXTEND_HIGH_S : WebAssemblyISD::EXTEND_HIGH_U;
3077 SDValue Input = N->getOperand(Num: 0);
3078 SDValue LowHalf = DAG.getNode(Opcode: LowOp, DL, VT: MVT::v8i16, Operand: Input);
3079 SDValue HighHalf = DAG.getNode(Opcode: HighOp, DL, VT: MVT::v8i16, Operand: Input);
3080 SDValue Subvectors[] = {
3081 DAG.getNode(Opcode: LowOp, DL, VT: MVT::v4i32, Operand: LowHalf),
3082 DAG.getNode(Opcode: HighOp, DL, VT: MVT::v4i32, Operand: LowHalf),
3083 DAG.getNode(Opcode: LowOp, DL, VT: MVT::v4i32, Operand: HighHalf),
3084 DAG.getNode(Opcode: HighOp, DL, VT: MVT::v4i32, Operand: HighHalf),
3085 };
3086 return DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL, VT: ResVT, Ops: Subvectors);
3087 }
3088
3089 // Combine ({s,z}ext (extract_subvector src, i)) into a widening operation if
3090 // possible before the extract_subvector can be expanded.
3091 auto Extract = N->getOperand(Num: 0);
3092 if (Extract.getOpcode() != ISD::EXTRACT_SUBVECTOR)
3093 return SDValue();
3094 auto Source = Extract.getOperand(i: 0);
3095 auto *IndexNode = dyn_cast<ConstantSDNode>(Val: Extract.getOperand(i: 1));
3096 if (IndexNode == nullptr)
3097 return SDValue();
3098 auto Index = IndexNode->getZExtValue();
3099
3100 // Only v8i8, v4i16, and v2i32 extracts can be widened, and only if the
3101 // extracted subvector is the low or high half of its source.
3102 if (ResVT == MVT::v8i16) {
3103 if (Extract.getValueType() != MVT::v8i8 ||
3104 Source.getValueType() != MVT::v16i8 || (Index != 0 && Index != 8))
3105 return SDValue();
3106 } else if (ResVT == MVT::v4i32) {
3107 if (Extract.getValueType() != MVT::v4i16 ||
3108 Source.getValueType() != MVT::v8i16 || (Index != 0 && Index != 4))
3109 return SDValue();
3110 } else if (ResVT == MVT::v2i64) {
3111 if (Extract.getValueType() != MVT::v2i32 ||
3112 Source.getValueType() != MVT::v4i32 || (Index != 0 && Index != 2))
3113 return SDValue();
3114 } else {
3115 return SDValue();
3116 }
3117
3118 bool IsLow = Index == 0;
3119
3120 unsigned Op = IsSext ? (IsLow ? WebAssemblyISD::EXTEND_LOW_S
3121 : WebAssemblyISD::EXTEND_HIGH_S)
3122 : (IsLow ? WebAssemblyISD::EXTEND_LOW_U
3123 : WebAssemblyISD::EXTEND_HIGH_U);
3124
3125 return DAG.getNode(Opcode: Op, DL, VT: ResVT, Operand: Source);
3126}
3127
3128static SDValue
3129performVectorTruncZeroCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
3130 auto &DAG = DCI.DAG;
3131
3132 auto GetWasmConversionOp = [](unsigned Op) {
3133 switch (Op) {
3134 case ISD::FP_TO_SINT_SAT:
3135 return WebAssemblyISD::TRUNC_SAT_ZERO_S;
3136 case ISD::FP_TO_UINT_SAT:
3137 return WebAssemblyISD::TRUNC_SAT_ZERO_U;
3138 case ISD::FP_ROUND:
3139 return WebAssemblyISD::DEMOTE_ZERO;
3140 }
3141 llvm_unreachable("unexpected op");
3142 };
3143
3144 auto IsZeroSplat = [](SDValue SplatVal) {
3145 auto *Splat = dyn_cast<BuildVectorSDNode>(Val: SplatVal.getNode());
3146 APInt SplatValue, SplatUndef;
3147 unsigned SplatBitSize;
3148 bool HasAnyUndefs;
3149 // Endianness doesn't matter in this context because we are looking for
3150 // an all-zero value.
3151 return Splat &&
3152 Splat->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
3153 HasAnyUndefs) &&
3154 SplatValue == 0;
3155 };
3156
3157 if (N->getOpcode() == ISD::CONCAT_VECTORS) {
3158 // Combine this:
3159 //
3160 // (concat_vectors (v2i32 (fp_to_{s,u}int_sat $x, 32)), (v2i32 (splat 0)))
3161 //
3162 // into (i32x4.trunc_sat_f64x2_zero_{s,u} $x).
3163 //
3164 // Or this:
3165 //
3166 // (concat_vectors ({v2f32, v4f16} (fp_round ({v2f64, v4f32} $x))),
3167 // ({v2f32, v4f16} (splat 0)))
3168 //
3169 // into ({f32x4, f16x8}.demote_zero_{f64x2, f32x4} $x).
3170 EVT ResVT;
3171 EVT ExpectedConversionType;
3172 auto Conversion = N->getOperand(Num: 0);
3173 auto ConversionOp = Conversion.getOpcode();
3174 switch (ConversionOp) {
3175 case ISD::FP_TO_SINT_SAT:
3176 case ISD::FP_TO_UINT_SAT:
3177 ResVT = MVT::v4i32;
3178 ExpectedConversionType = MVT::v2i32;
3179 break;
3180 case ISD::FP_ROUND:
3181 if (Conversion.getValueType() == MVT::v2f32) {
3182 ResVT = MVT::v4f32;
3183 ExpectedConversionType = MVT::v2f32;
3184 } else if (Conversion.getValueType() == MVT::v4f16) {
3185 ResVT = MVT::v8f16;
3186 ExpectedConversionType = MVT::v4f16;
3187 } else {
3188 return SDValue();
3189 }
3190 break;
3191 default:
3192 return SDValue();
3193 }
3194
3195 if (N->getValueType(ResNo: 0) != ResVT)
3196 return SDValue();
3197
3198 if (Conversion.getValueType() != ExpectedConversionType)
3199 return SDValue();
3200
3201 auto Source = Conversion.getOperand(i: 0);
3202 if (!((Source.getValueType() == MVT::v2f64 && ResVT == MVT::v4f32) ||
3203 (Source.getValueType() == MVT::v2f64 && ResVT == MVT::v4i32) ||
3204 (Source.getValueType() == MVT::v4f32 && ResVT == MVT::v8f16)))
3205 return SDValue();
3206
3207 if (!IsZeroSplat(N->getOperand(Num: 1)) ||
3208 N->getOperand(Num: 1).getValueType() != ExpectedConversionType)
3209 return SDValue();
3210
3211 unsigned Op = GetWasmConversionOp(ConversionOp);
3212 return DAG.getNode(Opcode: Op, DL: SDLoc(N), VT: ResVT, Operand: Source);
3213 }
3214
3215 // Combine this:
3216 //
3217 // (fp_to_{s,u}int_sat (concat_vectors $x, (v2f64 (splat 0))), 32)
3218 //
3219 // into (i32x4.trunc_sat_f64x2_zero_{s,u} $x).
3220 //
3221 // Or this:
3222 //
3223 // ({v4f32, v8f16} (fp_round (concat_vectors $x,
3224 // ({v2f64, v4f32} (splat 0)))))
3225 //
3226 // into ({f32x4, f16x8}.demote_zero_{f64x2, f32x4} $x).
3227 EVT ResVT;
3228 auto ConversionOp = N->getOpcode();
3229 switch (ConversionOp) {
3230 case ISD::FP_TO_SINT_SAT:
3231 case ISD::FP_TO_UINT_SAT:
3232 ResVT = MVT::v4i32;
3233 break;
3234 case ISD::FP_ROUND:
3235 ResVT = N->getValueType(ResNo: 0);
3236 break;
3237 default:
3238 llvm_unreachable("unexpected op");
3239 }
3240
3241 if (N->getValueType(ResNo: 0) != ResVT)
3242 return SDValue();
3243
3244 auto Concat = N->getOperand(Num: 0);
3245 if (Concat.getOpcode() != ISD::CONCAT_VECTORS)
3246 return SDValue();
3247 EVT ConcatVT = Concat.getValueType();
3248 EVT SourceVT = Concat.getOperand(i: 0).getValueType();
3249
3250 if (!IsZeroSplat(Concat.getOperand(i: 1)))
3251 return SDValue();
3252
3253 if (ConversionOp == ISD::FP_ROUND) {
3254 bool IsF64ToF32 =
3255 ConcatVT == MVT::v4f64 && SourceVT == MVT::v2f64 && ResVT == MVT::v4f32;
3256 bool IsF32ToF16 =
3257 ConcatVT == MVT::v8f32 && SourceVT == MVT::v4f32 && ResVT == MVT::v8f16;
3258 if (!(IsF64ToF32 || IsF32ToF16))
3259 return SDValue();
3260 } else {
3261 if (ConcatVT != MVT::v4f64 || SourceVT != MVT::v2f64 || ResVT != MVT::v4i32)
3262 return SDValue();
3263 }
3264
3265 unsigned Op = GetWasmConversionOp(ConversionOp);
3266 return DAG.getNode(Opcode: Op, DL: SDLoc(N), VT: ResVT, Operand: Concat.getOperand(i: 0));
3267}
3268
3269// Helper to extract VectorWidth bits from Vec, starting from IdxVal.
3270static SDValue extractSubVector(SDValue Vec, unsigned IdxVal, SelectionDAG &DAG,
3271 const SDLoc &DL, unsigned VectorWidth) {
3272 EVT VT = Vec.getValueType();
3273 EVT ElVT = VT.getVectorElementType();
3274 unsigned Factor = VT.getSizeInBits() / VectorWidth;
3275 EVT ResultVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: ElVT,
3276 NumElements: VT.getVectorNumElements() / Factor);
3277
3278 // Extract the relevant VectorWidth bits. Generate an EXTRACT_SUBVECTOR
3279 unsigned ElemsPerChunk = VectorWidth / ElVT.getSizeInBits();
3280 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
3281
3282 // This is the index of the first element of the VectorWidth-bit chunk
3283 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
3284 IdxVal &= ~(ElemsPerChunk - 1);
3285
3286 // If the input is a buildvector just emit a smaller one.
3287 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
3288 return DAG.getBuildVector(VT: ResultVT, DL,
3289 Ops: Vec->ops().slice(N: IdxVal, M: ElemsPerChunk));
3290
3291 SDValue VecIdx = DAG.getIntPtrConstant(Val: IdxVal, DL);
3292 return DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL, VT: ResultVT, N1: Vec, N2: VecIdx);
3293}
3294
3295// Helper to recursively truncate vector elements in half with NARROW_U. DstVT
3296// is the expected destination value type after recursion. In is the initial
3297// input. Note that the input should have enough leading zero bits to prevent
3298// NARROW_U from saturating results.
3299static SDValue truncateVectorWithNARROW(EVT DstVT, SDValue In, const SDLoc &DL,
3300 SelectionDAG &DAG) {
3301 EVT SrcVT = In.getValueType();
3302
3303 // No truncation required, we might get here due to recursive calls.
3304 if (SrcVT == DstVT)
3305 return In;
3306
3307 unsigned SrcSizeInBits = SrcVT.getSizeInBits();
3308 unsigned NumElems = SrcVT.getVectorNumElements();
3309 if (!isPowerOf2_32(Value: NumElems))
3310 return SDValue();
3311 assert(DstVT.getVectorNumElements() == NumElems && "Illegal truncation");
3312 assert(SrcSizeInBits > DstVT.getSizeInBits() && "Illegal truncation");
3313
3314 LLVMContext &Ctx = *DAG.getContext();
3315 EVT PackedSVT = EVT::getIntegerVT(Context&: Ctx, BitWidth: SrcVT.getScalarSizeInBits() / 2);
3316
3317 // Narrow to the largest type possible:
3318 // vXi64/vXi32 -> i16x8.narrow_i32x4_u and vXi16 -> i8x16.narrow_i16x8_u.
3319 EVT InVT = MVT::i16, OutVT = MVT::i8;
3320 if (SrcVT.getScalarSizeInBits() > 16) {
3321 InVT = MVT::i32;
3322 OutVT = MVT::i16;
3323 }
3324 unsigned SubSizeInBits = SrcSizeInBits / 2;
3325 InVT = EVT::getVectorVT(Context&: Ctx, VT: InVT, NumElements: SubSizeInBits / InVT.getSizeInBits());
3326 OutVT = EVT::getVectorVT(Context&: Ctx, VT: OutVT, NumElements: SubSizeInBits / OutVT.getSizeInBits());
3327
3328 // Split lower/upper subvectors.
3329 SDValue Lo = extractSubVector(Vec: In, IdxVal: 0, DAG, DL, VectorWidth: SubSizeInBits);
3330 SDValue Hi = extractSubVector(Vec: In, IdxVal: NumElems / 2, DAG, DL, VectorWidth: SubSizeInBits);
3331
3332 // 256bit -> 128bit truncate - Narrow lower/upper 128-bit subvectors.
3333 if (SrcVT.is256BitVector() && DstVT.is128BitVector()) {
3334 Lo = DAG.getBitcast(VT: InVT, V: Lo);
3335 Hi = DAG.getBitcast(VT: InVT, V: Hi);
3336 SDValue Res = DAG.getNode(Opcode: WebAssemblyISD::NARROW_U, DL, VT: OutVT, N1: Lo, N2: Hi);
3337 return DAG.getBitcast(VT: DstVT, V: Res);
3338 }
3339
3340 // Recursively narrow lower/upper subvectors, concat result and narrow again.
3341 EVT PackedVT = EVT::getVectorVT(Context&: Ctx, VT: PackedSVT, NumElements: NumElems / 2);
3342 Lo = truncateVectorWithNARROW(DstVT: PackedVT, In: Lo, DL, DAG);
3343 Hi = truncateVectorWithNARROW(DstVT: PackedVT, In: Hi, DL, DAG);
3344
3345 PackedVT = EVT::getVectorVT(Context&: Ctx, VT: PackedSVT, NumElements: NumElems);
3346 SDValue Res = DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL, VT: PackedVT, N1: Lo, N2: Hi);
3347 return truncateVectorWithNARROW(DstVT, In: Res, DL, DAG);
3348}
3349
3350static SDValue performTruncateCombine(SDNode *N,
3351 TargetLowering::DAGCombinerInfo &DCI) {
3352 auto &DAG = DCI.DAG;
3353
3354 SDValue In = N->getOperand(Num: 0);
3355 EVT InVT = In.getValueType();
3356 if (!InVT.isSimple())
3357 return SDValue();
3358
3359 EVT OutVT = N->getValueType(ResNo: 0);
3360 if (!OutVT.isVector())
3361 return SDValue();
3362
3363 EVT OutSVT = OutVT.getVectorElementType();
3364 EVT InSVT = InVT.getVectorElementType();
3365 // Currently only cover truncate to v16i8 or v8i16.
3366 if (!((InSVT == MVT::i16 || InSVT == MVT::i32 || InSVT == MVT::i64) &&
3367 (OutSVT == MVT::i8 || OutSVT == MVT::i16) && OutVT.is128BitVector()))
3368 return SDValue();
3369
3370 SDLoc DL(N);
3371 APInt Mask = APInt::getLowBitsSet(numBits: InVT.getScalarSizeInBits(),
3372 loBitsSet: OutVT.getScalarSizeInBits());
3373 In = DAG.getNode(Opcode: ISD::AND, DL, VT: InVT, N1: In, N2: DAG.getConstant(Val: Mask, DL, VT: InVT));
3374 return truncateVectorWithNARROW(DstVT: OutVT, In, DL, DAG);
3375}
3376
3377static SDValue performBitcastCombine(SDNode *N,
3378 TargetLowering::DAGCombinerInfo &DCI) {
3379 using namespace llvm::SDPatternMatch;
3380 auto &DAG = DCI.DAG;
3381 SDLoc DL(N);
3382 SDValue Src = N->getOperand(Num: 0);
3383 EVT VT = N->getValueType(ResNo: 0);
3384 EVT SrcVT = Src.getValueType();
3385
3386 if (!(DCI.isBeforeLegalize() && VT.isScalarInteger() &&
3387 SrcVT.isFixedLengthVectorOf(EltVT: MVT::i1)))
3388 return SDValue();
3389
3390 unsigned NumElts = SrcVT.getVectorNumElements();
3391 EVT Width = MVT::getIntegerVT(BitWidth: 128 / NumElts);
3392
3393 // bitcast <N x i1> to iN, where N = 2, 4, 8, 16 (legal)
3394 // ==> bitmask
3395 if (NumElts == 2 || NumElts == 4 || NumElts == 8 || NumElts == 16) {
3396 return DAG.getZExtOrTrunc(
3397 Op: DAG.getNode(Opcode: ISD::INTRINSIC_WO_CHAIN, DL, VT: MVT::i32,
3398 Ops: {DAG.getConstant(Val: Intrinsic::wasm_bitmask, DL, VT: MVT::i32),
3399 DAG.getSExtOrTrunc(Op: N->getOperand(Num: 0), DL,
3400 VT: SrcVT.changeVectorElementType(
3401 Context&: *DAG.getContext(), EltVT: Width))}),
3402 DL, VT);
3403 }
3404
3405 // bitcast <N x i1>(setcc ...) to concat iN, where N = 32 and 64 (illegal)
3406 if (NumElts == 32 || NumElts == 64) {
3407 SDValue Concat, SetCCVector;
3408 ISD::CondCode SetCond;
3409
3410 if (!sd_match(N, P: m_BitCast(Op: m_c_SetCC(LHS: m_Value(N&: Concat), RHS: m_Value(N&: SetCCVector),
3411 CC: m_CondCode(CC&: SetCond)))))
3412 return SDValue();
3413 if (Concat.getOpcode() != ISD::CONCAT_VECTORS)
3414 return SDValue();
3415
3416 // Reconstruct the wide bitmask from each CONCAT_VECTORS operand.
3417 // Derive the per-chunk mask/integer types from the actual operand type
3418 // instead of hardcoding v16i1 / i16 for every chunk.
3419 EVT ConcatOperandVT = Concat.getOperand(i: 0).getValueType();
3420 unsigned ConcatOperandNumElts = ConcatOperandVT.getVectorNumElements();
3421
3422 EVT ConcatOperandMaskVT =
3423 EVT::getVectorVT(Context&: *DAG.getContext(), VT: MVT::i1,
3424 EC: ElementCount::getFixed(MinVal: ConcatOperandNumElts));
3425 EVT ConcatOperandBitmaskVT =
3426 EVT::getIntegerVT(Context&: *DAG.getContext(), BitWidth: ConcatOperandNumElts);
3427 EVT ReturnVT = N->getValueType(ResNo: 0);
3428 SDValue ReconstructedBitmask = DAG.getConstant(Val: 0, DL, VT: ReturnVT);
3429 // Example:
3430 // v32i16 = concat(v8i16, v8i16, v8i16, v8i16)
3431 // -> v8i1 + v8i1 + v8i1 + v8i1
3432 // -> i8 + i8 + i8 + i8
3433 // -> reconstructed i32 bitmask
3434 for (size_t I = 0; I < Concat->ops().size(); ++I) {
3435 SDValue ConcatOperand = Concat.getOperand(i: I);
3436 assert(ConcatOperand.getValueType() == ConcatOperandVT &&
3437 "concat_vectors operands must have the same type");
3438
3439 SDValue SetCCVectorOperand =
3440 extractSubVector(Vec: SetCCVector, IdxVal: I * ConcatOperandNumElts, DAG, DL, VectorWidth: 128);
3441 if (!SetCCVectorOperand ||
3442 SetCCVectorOperand.getValueType() != ConcatOperandVT)
3443 return SDValue();
3444
3445 // Build the per-chunk mask using the correct chunk type:
3446 // v16i8 -> v16i1 -> i16
3447 // v8i16 -> v8i1 -> i8
3448 // v4i32 -> v4i1 -> i4
3449 // v2i64 -> v2i1 -> i2
3450 SDValue ConcatOperandMask = DAG.getSetCC(
3451 DL, VT: ConcatOperandMaskVT, LHS: ConcatOperand, RHS: SetCCVectorOperand, Cond: SetCond);
3452 SDValue ConcatOperandBitmask =
3453 DAG.getBitcast(VT: ConcatOperandBitmaskVT, V: ConcatOperandMask);
3454 SDValue ExtendedConcatOperandBitmask =
3455 DAG.getZExtOrTrunc(Op: ConcatOperandBitmask, DL, VT: ReturnVT);
3456
3457 // Shift the previously reconstructed bits to make room for this chunk.
3458 if (I != 0) {
3459 ReconstructedBitmask = DAG.getNode(
3460 Opcode: ISD::SHL, DL, VT: ReturnVT, N1: ReconstructedBitmask,
3461 N2: DAG.getShiftAmountConstant(Val: ConcatOperandNumElts, VT: ReturnVT, DL));
3462 }
3463
3464 // Merge disjoint partial bitmasks with OR.
3465 ReconstructedBitmask =
3466 DAG.getNode(Opcode: ISD::OR, DL, VT: ReturnVT, N1: ReconstructedBitmask,
3467 N2: ExtendedConcatOperandBitmask);
3468 }
3469
3470 return ReconstructedBitmask;
3471 }
3472
3473 return SDValue();
3474}
3475
3476static SDValue performBitmaskCombine(SDNode *N, SelectionDAG &DAG) {
3477 // bitmask (setcc <X>, 0, setlt) => bitmask X
3478 assert(N->getOpcode() == ISD::INTRINSIC_WO_CHAIN);
3479 using namespace llvm::SDPatternMatch;
3480
3481 if (N->getConstantOperandVal(Num: 0) != Intrinsic::wasm_bitmask)
3482 return SDValue();
3483
3484 SDValue LHS;
3485 if (!sd_match(N: N->getOperand(Num: 1), P: m_c_SetCC(LHS: m_Value(N&: LHS), RHS: m_Zero(),
3486 CC: m_SpecificCondCode(CC: ISD::SETLT))))
3487 return SDValue();
3488
3489 SDLoc DL(N);
3490 return DAG.getNode(
3491 Opcode: ISD::INTRINSIC_WO_CHAIN, DL, VT: N->getValueType(ResNo: 0),
3492 Ops: {DAG.getConstant(Val: Intrinsic::wasm_bitmask, DL, VT: MVT::i32), LHS});
3493}
3494
3495static SDValue performAnyAllCombine(SDNode *N, SelectionDAG &DAG) {
3496 // any_true (setcc <X>, 0, eq) => (not (all_true X))
3497 // all_true (setcc <X>, 0, eq) => (not (any_true X))
3498 // any_true (setcc <X>, 0, ne) => (any_true X)
3499 // all_true (setcc <X>, 0, ne) => (all_true X)
3500 assert(N->getOpcode() == ISD::INTRINSIC_WO_CHAIN);
3501 using namespace llvm::SDPatternMatch;
3502
3503 SDValue LHS;
3504 if (N->getNumOperands() < 2 ||
3505 !sd_match(N: N->getOperand(Num: 1),
3506 P: m_c_SetCC(LHS: m_Value(N&: LHS), RHS: m_Zero(), CC: m_CondCode())))
3507 return SDValue();
3508 EVT LT = LHS.getValueType();
3509 if (LT.getScalarSizeInBits() > 128 / LT.getVectorNumElements())
3510 return SDValue();
3511
3512 auto CombineSetCC = [&N, &DAG](Intrinsic::WASMIntrinsics InPre,
3513 ISD::CondCode SetType,
3514 Intrinsic::WASMIntrinsics InPost) {
3515 if (N->getConstantOperandVal(Num: 0) != InPre)
3516 return SDValue();
3517
3518 SDValue LHS;
3519 if (!sd_match(N: N->getOperand(Num: 1), P: m_c_SetCC(LHS: m_Value(N&: LHS), RHS: m_Zero(),
3520 CC: m_SpecificCondCode(CC: SetType))))
3521 return SDValue();
3522
3523 SDLoc DL(N);
3524 SDValue Ret = DAG.getNode(Opcode: ISD::INTRINSIC_WO_CHAIN, DL, VT: MVT::i32,
3525 Ops: {DAG.getConstant(Val: InPost, DL, VT: MVT::i32), LHS});
3526 if (SetType == ISD::SETEQ)
3527 Ret = DAG.getNode(Opcode: ISD::XOR, DL, VT: MVT::i32, N1: Ret,
3528 N2: DAG.getConstant(Val: 1, DL, VT: MVT::i32));
3529 return DAG.getZExtOrTrunc(Op: Ret, DL, VT: N->getValueType(ResNo: 0));
3530 };
3531
3532 if (SDValue AnyTrueEQ = CombineSetCC(Intrinsic::wasm_anytrue, ISD::SETEQ,
3533 Intrinsic::wasm_alltrue))
3534 return AnyTrueEQ;
3535 if (SDValue AllTrueEQ = CombineSetCC(Intrinsic::wasm_alltrue, ISD::SETEQ,
3536 Intrinsic::wasm_anytrue))
3537 return AllTrueEQ;
3538 if (SDValue AnyTrueNE = CombineSetCC(Intrinsic::wasm_anytrue, ISD::SETNE,
3539 Intrinsic::wasm_anytrue))
3540 return AnyTrueNE;
3541 if (SDValue AllTrueNE = CombineSetCC(Intrinsic::wasm_alltrue, ISD::SETNE,
3542 Intrinsic::wasm_alltrue))
3543 return AllTrueNE;
3544
3545 return SDValue();
3546}
3547
3548struct MaskReduceInfo {
3549 Intrinsic::ID IID;
3550 unsigned WideCombineOpcode;
3551 bool Invert;
3552};
3553
3554static SDValue combineSmallMaskReduction(SDNode *N, EVT FromVT,
3555 unsigned NumElts,
3556 const MaskReduceInfo &Info,
3557 SelectionDAG &DAG) {
3558 EVT VecVT = FromVT.changeVectorElementType(Context&: *DAG.getContext(),
3559 EltVT: MVT::getIntegerVT(BitWidth: 128 / NumElts));
3560 assert(VecVT.getSizeInBits() == 128 &&
3561 "mask reduction should be widened to a 128-bit vector");
3562
3563 SDLoc DL(N);
3564 SDValue Mask = N->getOperand(Num: 0)->getOperand(Num: 0);
3565 SDValue Ret = DAG.getNode(Opcode: ISD::INTRINSIC_WO_CHAIN, DL, VT: MVT::i32,
3566 Ops: {DAG.getConstant(Val: Info.IID, DL, VT: MVT::i32),
3567 DAG.getSExtOrTrunc(Op: Mask, DL, VT: VecVT)});
3568 if (Info.Invert)
3569 Ret = DAG.getNode(Opcode: ISD::XOR, DL, VT: MVT::i32, N1: Ret,
3570 N2: DAG.getConstant(Val: 1, DL, VT: MVT::i32));
3571 return DAG.getZExtOrTrunc(Op: Ret, DL, VT: N->getValueType(ResNo: 0));
3572}
3573
3574static SDValue combineWideMaskReduction(SDNode *N, SDValue Mask, EVT MaskVT,
3575 unsigned NumElts,
3576 const MaskReduceInfo &Info,
3577 SelectionDAG &DAG) {
3578 assert((NumElts == 32 || NumElts == 64) &&
3579 "combineWideMaskReduction is only for wide masks");
3580 assert(MaskVT.isFixedLengthVector() &&
3581 MaskVT.getVectorElementType() == MVT::i1);
3582 SDLoc DL(N);
3583 unsigned ChunkElts = 16;
3584 EVT ChunkMaskVT = EVT::getVectorVT(Context&: *DAG.getContext(), VT: MVT::i1,
3585 EC: ElementCount::getFixed(MinVal: ChunkElts));
3586 EVT LegalVecVT = ChunkMaskVT.changeVectorElementType(
3587 Context&: *DAG.getContext(), EltVT: MVT::getIntegerVT(BitWidth: 128 / ChunkElts));
3588
3589 SmallVector<SDValue, 4> ChunkResults;
3590 // Split the wide mask into v16i1 chunks and reduce each chunk separately.
3591 // For example:
3592 // v32i1: [0..15] [16..31]
3593 // | |
3594 // v v
3595 // chunk0 chunk1
3596 //
3597 // v64i1: [0..15] [16..31] [32..47] [48..63]
3598 // | | | |
3599 // v v v v
3600 // chunk0 chunk1 chunk2 chunk3
3601 //
3602 // each chunk:
3603 // v16i1 -> v16i8 -> wasm_anytrue/alltrue -> i32 0/1
3604 for (unsigned I = 0; I < NumElts; I += ChunkElts) {
3605 SDValue ChunkMask = DAG.getNode(Opcode: ISD::EXTRACT_SUBVECTOR, DL, VT: ChunkMaskVT,
3606 N1: Mask, N2: DAG.getVectorIdxConstant(Val: I, DL));
3607 SDValue LegalMask = DAG.getSExtOrTrunc(Op: ChunkMask, DL, VT: LegalVecVT);
3608 SDValue Reduced =
3609 DAG.getNode(Opcode: ISD::INTRINSIC_WO_CHAIN, DL, VT: MVT::i32,
3610 N1: DAG.getConstant(Val: Info.IID, DL, VT: MVT::i32), N2: LegalMask);
3611 ChunkResults.push_back(Elt: Reduced);
3612 }
3613
3614 SDValue Acc = ChunkResults[0];
3615 for (unsigned I = 1; I < ChunkResults.size(); ++I)
3616 Acc =
3617 DAG.getNode(Opcode: Info.WideCombineOpcode, DL, VT: MVT::i32, N1: Acc, N2: ChunkResults[I]);
3618
3619 if (Info.Invert)
3620 Acc = DAG.getNode(Opcode: ISD::XOR, DL, VT: MVT::i32, N1: Acc,
3621 N2: DAG.getConstant(Val: 1, DL, VT: MVT::i32));
3622
3623 return DAG.getZExtOrTrunc(Op: Acc, DL, VT: N->getValueType(ResNo: 0));
3624}
3625
3626static std::optional<MaskReduceInfo> classifyMaskReduction(SDNode *N) {
3627 auto *C = dyn_cast<ConstantSDNode>(Val: N->getOperand(Num: 1));
3628 if (!C)
3629 return std::nullopt;
3630
3631 ISD::CondCode CC = cast<CondCodeSDNode>(Val: N->getOperand(Num: 2))->get();
3632
3633 // setcc (bitcast mask), 0, ne -> any_true(mask)
3634 if (C->isZero() && CC == ISD::SETNE)
3635 return MaskReduceInfo{.IID: Intrinsic::wasm_anytrue, .WideCombineOpcode: ISD::OR, .Invert: false};
3636
3637 // setcc (bitcast mask), 0, eq -> !any_true(mask)
3638 if (C->isZero() && CC == ISD::SETEQ)
3639 return MaskReduceInfo{.IID: Intrinsic::wasm_anytrue, .WideCombineOpcode: ISD::OR, .Invert: true};
3640
3641 // setcc (bitcast mask), -1, eq -> all_true(mask)
3642 if (C->isAllOnes() && CC == ISD::SETEQ)
3643 return MaskReduceInfo{.IID: Intrinsic::wasm_alltrue, .WideCombineOpcode: ISD::AND, .Invert: false};
3644
3645 // setcc (bitcast mask), -1, ne -> !all_true(mask)
3646 if (C->isAllOnes() && CC == ISD::SETNE)
3647 return MaskReduceInfo{.IID: Intrinsic::wasm_alltrue, .WideCombineOpcode: ISD::AND, .Invert: true};
3648
3649 return std::nullopt;
3650}
3651
3652/// Try to convert a i128 comparison to a v16i8 comparison before type
3653/// legalization splits it up into chunks
3654static SDValue
3655combineVectorSizedSetCCEquality(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
3656 const WebAssemblySubtarget *Subtarget) {
3657
3658 SDLoc DL(N);
3659 SDValue X = N->getOperand(Num: 0);
3660 SDValue Y = N->getOperand(Num: 1);
3661 EVT VT = N->getValueType(ResNo: 0);
3662 EVT OpVT = X.getValueType();
3663
3664 SelectionDAG &DAG = DCI.DAG;
3665 if (DCI.DAG.getMachineFunction().getFunction().hasFnAttribute(
3666 Kind: Attribute::NoImplicitFloat))
3667 return SDValue();
3668
3669 ISD::CondCode CC = cast<CondCodeSDNode>(Val: N->getOperand(Num: 2))->get();
3670 // We're looking for an oversized integer equality comparison with SIMD
3671 if (!OpVT.isScalarInteger() || !OpVT.isByteSized() || OpVT != MVT::i128 ||
3672 !Subtarget->hasSIMD128() || !isIntEqualitySetCC(Code: CC))
3673 return SDValue();
3674
3675 // Don't perform this combine if constructing the vector will be expensive.
3676 auto IsVectorBitCastCheap = [](SDValue X) {
3677 X = peekThroughBitcasts(V: X);
3678 return isa<ConstantSDNode>(Val: X) || X.getOpcode() == ISD::LOAD;
3679 };
3680
3681 if (!IsVectorBitCastCheap(X) || !IsVectorBitCastCheap(Y))
3682 return SDValue();
3683
3684 SDValue VecX = DAG.getBitcast(VT: MVT::v16i8, V: X);
3685 SDValue VecY = DAG.getBitcast(VT: MVT::v16i8, V: Y);
3686 SDValue Cmp = DAG.getSetCC(DL, VT: MVT::v16i8, LHS: VecX, RHS: VecY, Cond: CC);
3687
3688 SDValue Intr =
3689 DAG.getNode(Opcode: ISD::INTRINSIC_WO_CHAIN, DL, VT: MVT::i32,
3690 Ops: {DAG.getConstant(Val: CC == ISD::SETEQ ? Intrinsic::wasm_alltrue
3691 : Intrinsic::wasm_anytrue,
3692 DL, VT: MVT::i32),
3693 Cmp});
3694
3695 return DAG.getSetCC(DL, VT, LHS: Intr, RHS: DAG.getConstant(Val: 0, DL, VT: MVT::i32),
3696 Cond: ISD::SETNE);
3697}
3698
3699static SDValue performSETCCCombine(SDNode *N,
3700 TargetLowering::DAGCombinerInfo &DCI,
3701 const WebAssemblySubtarget *Subtarget) {
3702 if (!DCI.isBeforeLegalize())
3703 return SDValue();
3704
3705 EVT VT = N->getValueType(ResNo: 0);
3706 if (!VT.isScalarInteger())
3707 return SDValue();
3708
3709 if (SDValue V = combineVectorSizedSetCCEquality(N, DCI, Subtarget))
3710 return V;
3711
3712 SDValue LHS = N->getOperand(Num: 0);
3713 if (LHS->getOpcode() != ISD::BITCAST)
3714 return SDValue();
3715
3716 EVT FromVT = LHS->getOperand(Num: 0).getValueType();
3717 if (!FromVT.isFixedLengthVectorOf(EltVT: MVT::i1))
3718 return SDValue();
3719
3720 unsigned NumElts = FromVT.getVectorNumElements();
3721 auto Info = classifyMaskReduction(N);
3722 if (!Info)
3723 return SDValue();
3724
3725 auto &DAG = DCI.DAG;
3726 if (NumElts == 2 || NumElts == 4 || NumElts == 8 || NumElts == 16)
3727 return combineSmallMaskReduction(N, FromVT, NumElts, Info: *Info, DAG);
3728
3729 if (NumElts == 32 || NumElts == 64)
3730 return combineWideMaskReduction(N, Mask: LHS.getOperand(i: 0), MaskVT: FromVT, NumElts,
3731 Info: *Info, DAG);
3732
3733 return SDValue();
3734}
3735
3736static SDValue TryWideExtMulCombine(SDNode *N, SelectionDAG &DAG) {
3737 EVT VT = N->getValueType(ResNo: 0);
3738 if (VT != MVT::v8i32 && VT != MVT::v16i32)
3739 return SDValue();
3740
3741 // Mul with extending inputs.
3742 SDValue LHS = N->getOperand(Num: 0);
3743 SDValue RHS = N->getOperand(Num: 1);
3744 if (LHS.getOpcode() != RHS.getOpcode())
3745 return SDValue();
3746
3747 if (LHS.getOpcode() != ISD::SIGN_EXTEND &&
3748 LHS.getOpcode() != ISD::ZERO_EXTEND)
3749 return SDValue();
3750
3751 if (LHS->getOperand(Num: 0).getValueType() != RHS->getOperand(Num: 0).getValueType())
3752 return SDValue();
3753
3754 EVT FromVT = LHS->getOperand(Num: 0).getValueType();
3755 EVT EltTy = FromVT.getVectorElementType();
3756 if (EltTy != MVT::i8)
3757 return SDValue();
3758
3759 // For an input DAG that looks like this
3760 // %a = input_type
3761 // %b = input_type
3762 // %lhs = extend %a to output_type
3763 // %rhs = extend %b to output_type
3764 // %mul = mul %lhs, %rhs
3765
3766 // input_type | output_type | instructions
3767 // v16i8 | v16i32 | %low = i16x8.extmul_low_i8x16_ %a, %b
3768 // | | %high = i16x8.extmul_high_i8x16_, %a, %b
3769 // | | %low_low = i32x4.ext_low_i16x8_ %low
3770 // | | %low_high = i32x4.ext_high_i16x8_ %low
3771 // | | %high_low = i32x4.ext_low_i16x8_ %high
3772 // | | %high_high = i32x4.ext_high_i16x8_ %high
3773 // | | %res = concat_vector(...)
3774 // v8i8 | v8i32 | %low = i16x8.extmul_low_i8x16_ %a, %b
3775 // | | %low_low = i32x4.ext_low_i16x8_ %low
3776 // | | %low_high = i32x4.ext_high_i16x8_ %low
3777 // | | %res = concat_vector(%low_low, %low_high)
3778
3779 SDLoc DL(N);
3780 unsigned NumElts = VT.getVectorNumElements();
3781 SDValue ExtendInLHS = LHS->getOperand(Num: 0);
3782 SDValue ExtendInRHS = RHS->getOperand(Num: 0);
3783 bool IsSigned = LHS->getOpcode() == ISD::SIGN_EXTEND;
3784 unsigned ExtendLowOpc =
3785 IsSigned ? WebAssemblyISD::EXTEND_LOW_S : WebAssemblyISD::EXTEND_LOW_U;
3786 unsigned ExtendHighOpc =
3787 IsSigned ? WebAssemblyISD::EXTEND_HIGH_S : WebAssemblyISD::EXTEND_HIGH_U;
3788
3789 auto GetExtendLow = [&DAG, &DL, &ExtendLowOpc](EVT VT, SDValue Op) {
3790 return DAG.getNode(Opcode: ExtendLowOpc, DL, VT, Operand: Op);
3791 };
3792 auto GetExtendHigh = [&DAG, &DL, &ExtendHighOpc](EVT VT, SDValue Op) {
3793 return DAG.getNode(Opcode: ExtendHighOpc, DL, VT, Operand: Op);
3794 };
3795
3796 if (NumElts == 16) {
3797 SDValue LowLHS = GetExtendLow(MVT::v8i16, ExtendInLHS);
3798 SDValue LowRHS = GetExtendLow(MVT::v8i16, ExtendInRHS);
3799 SDValue MulLow = DAG.getNode(Opcode: ISD::MUL, DL, VT: MVT::v8i16, N1: LowLHS, N2: LowRHS);
3800 SDValue HighLHS = GetExtendHigh(MVT::v8i16, ExtendInLHS);
3801 SDValue HighRHS = GetExtendHigh(MVT::v8i16, ExtendInRHS);
3802 SDValue MulHigh = DAG.getNode(Opcode: ISD::MUL, DL, VT: MVT::v8i16, N1: HighLHS, N2: HighRHS);
3803 SDValue SubVectors[] = {
3804 GetExtendLow(MVT::v4i32, MulLow),
3805 GetExtendHigh(MVT::v4i32, MulLow),
3806 GetExtendLow(MVT::v4i32, MulHigh),
3807 GetExtendHigh(MVT::v4i32, MulHigh),
3808 };
3809 return DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL, VT, Ops: SubVectors);
3810 } else {
3811 assert(NumElts == 8);
3812 SDValue LowLHS = DAG.getNode(Opcode: LHS->getOpcode(), DL, VT: MVT::v8i16, Operand: ExtendInLHS);
3813 SDValue LowRHS = DAG.getNode(Opcode: RHS->getOpcode(), DL, VT: MVT::v8i16, Operand: ExtendInRHS);
3814 SDValue MulLow = DAG.getNode(Opcode: ISD::MUL, DL, VT: MVT::v8i16, N1: LowLHS, N2: LowRHS);
3815 SDValue Lo = GetExtendLow(MVT::v4i32, MulLow);
3816 SDValue Hi = GetExtendHigh(MVT::v4i32, MulLow);
3817 return DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL, VT, N1: Lo, N2: Hi);
3818 }
3819 return SDValue();
3820}
3821
3822static SDValue performMulCombine(SDNode *N,
3823 TargetLowering::DAGCombinerInfo &DCI) {
3824 assert(N->getOpcode() == ISD::MUL);
3825 EVT VT = N->getValueType(ResNo: 0);
3826 if (!VT.isVector())
3827 return SDValue();
3828
3829 if (auto Res = TryWideExtMulCombine(N, DAG&: DCI.DAG))
3830 return Res;
3831
3832 // We don't natively support v16i8 or v8i8 mul, but we do support v8i16. So,
3833 // extend them to v8i16.
3834 if (VT != MVT::v8i8 && VT != MVT::v16i8)
3835 return SDValue();
3836
3837 SDLoc DL(N);
3838 SelectionDAG &DAG = DCI.DAG;
3839 SDValue LHS = N->getOperand(Num: 0);
3840 SDValue RHS = N->getOperand(Num: 1);
3841 EVT MulVT = MVT::v8i16;
3842
3843 if (VT == MVT::v8i8) {
3844 SDValue PromotedLHS = DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL, VT: MVT::v16i8, N1: LHS,
3845 N2: DAG.getUNDEF(VT: MVT::v8i8));
3846 SDValue PromotedRHS = DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL, VT: MVT::v16i8, N1: RHS,
3847 N2: DAG.getUNDEF(VT: MVT::v8i8));
3848 SDValue LowLHS =
3849 DAG.getNode(Opcode: WebAssemblyISD::EXTEND_LOW_U, DL, VT: MulVT, Operand: PromotedLHS);
3850 SDValue LowRHS =
3851 DAG.getNode(Opcode: WebAssemblyISD::EXTEND_LOW_U, DL, VT: MulVT, Operand: PromotedRHS);
3852 SDValue MulLow = DAG.getBitcast(
3853 VT: MVT::v16i8, V: DAG.getNode(Opcode: ISD::MUL, DL, VT: MulVT, N1: LowLHS, N2: LowRHS));
3854 // Take the low byte of each lane.
3855 SDValue Shuffle = DAG.getVectorShuffle(
3856 VT: MVT::v16i8, dl: DL, N1: MulLow, N2: DAG.getUNDEF(VT: MVT::v16i8),
3857 Mask: {0, 2, 4, 6, 8, 10, 12, 14, -1, -1, -1, -1, -1, -1, -1, -1});
3858 return extractSubVector(Vec: Shuffle, IdxVal: 0, DAG, DL, VectorWidth: 64);
3859 } else {
3860 assert(VT == MVT::v16i8 && "Expected v16i8");
3861 SDValue LowLHS = DAG.getNode(Opcode: WebAssemblyISD::EXTEND_LOW_U, DL, VT: MulVT, Operand: LHS);
3862 SDValue LowRHS = DAG.getNode(Opcode: WebAssemblyISD::EXTEND_LOW_U, DL, VT: MulVT, Operand: RHS);
3863 SDValue HighLHS =
3864 DAG.getNode(Opcode: WebAssemblyISD::EXTEND_HIGH_U, DL, VT: MulVT, Operand: LHS);
3865 SDValue HighRHS =
3866 DAG.getNode(Opcode: WebAssemblyISD::EXTEND_HIGH_U, DL, VT: MulVT, Operand: RHS);
3867
3868 SDValue MulLow =
3869 DAG.getBitcast(VT, V: DAG.getNode(Opcode: ISD::MUL, DL, VT: MulVT, N1: LowLHS, N2: LowRHS));
3870 SDValue MulHigh =
3871 DAG.getBitcast(VT, V: DAG.getNode(Opcode: ISD::MUL, DL, VT: MulVT, N1: HighLHS, N2: HighRHS));
3872
3873 // Take the low byte of each lane.
3874 return DAG.getVectorShuffle(
3875 VT, dl: DL, N1: MulLow, N2: MulHigh,
3876 Mask: {0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30});
3877 }
3878}
3879
3880SDValue DoubleVectorWidth(SDValue In, unsigned RequiredNumElems,
3881 SelectionDAG &DAG) {
3882 SDLoc DL(In);
3883 LLVMContext &Ctx = *DAG.getContext();
3884 EVT InVT = In.getValueType();
3885 unsigned NumElems = InVT.getVectorNumElements() * 2;
3886 EVT OutVT = EVT::getVectorVT(Context&: Ctx, VT: InVT.getVectorElementType(), NumElements: NumElems);
3887 SDValue Concat =
3888 DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL, VT: OutVT, N1: In, N2: DAG.getPOISON(VT: InVT));
3889 if (NumElems < RequiredNumElems) {
3890 return DoubleVectorWidth(In: Concat, RequiredNumElems, DAG);
3891 }
3892 return Concat;
3893}
3894
3895SDValue performConvertFPCombine(SDNode *N, SelectionDAG &DAG) {
3896 EVT OutVT = N->getValueType(ResNo: 0);
3897 if (!OutVT.isVector())
3898 return SDValue();
3899
3900 EVT OutElTy = OutVT.getVectorElementType();
3901 if (OutElTy != MVT::i8 && OutElTy != MVT::i16)
3902 return SDValue();
3903
3904 unsigned NumElems = OutVT.getVectorNumElements();
3905 if (!isPowerOf2_32(Value: NumElems))
3906 return SDValue();
3907
3908 EVT FPVT = N->getOperand(Num: 0)->getValueType(ResNo: 0);
3909 if (FPVT.getVectorElementType() != MVT::f32)
3910 return SDValue();
3911
3912 SDLoc DL(N);
3913
3914 // First, convert to i32.
3915 LLVMContext &Ctx = *DAG.getContext();
3916 EVT IntVT = EVT::getVectorVT(Context&: Ctx, VT: MVT::i32, NumElements: NumElems);
3917 SDValue ToInt = DAG.getNode(Opcode: N->getOpcode(), DL, VT: IntVT, Operand: N->getOperand(Num: 0));
3918 APInt Mask = APInt::getLowBitsSet(numBits: IntVT.getScalarSizeInBits(),
3919 loBitsSet: OutVT.getScalarSizeInBits());
3920 // Mask out the top MSBs.
3921 SDValue Masked =
3922 DAG.getNode(Opcode: ISD::AND, DL, VT: IntVT, N1: ToInt, N2: DAG.getConstant(Val: Mask, DL, VT: IntVT));
3923
3924 if (OutVT.getSizeInBits() < 128) {
3925 // Create a wide enough vector that we can use narrow.
3926 EVT NarrowedVT = OutElTy == MVT::i8 ? MVT::v16i8 : MVT::v8i16;
3927 unsigned NumRequiredElems = NarrowedVT.getVectorNumElements();
3928 SDValue WideVector = DoubleVectorWidth(In: Masked, RequiredNumElems: NumRequiredElems, DAG);
3929 SDValue Trunc = truncateVectorWithNARROW(DstVT: NarrowedVT, In: WideVector, DL, DAG);
3930 return DAG.getBitcast(
3931 VT: OutVT, V: extractSubVector(Vec: Trunc, IdxVal: 0, DAG, DL, VectorWidth: OutVT.getSizeInBits()));
3932 } else {
3933 return truncateVectorWithNARROW(DstVT: OutVT, In: Masked, DL, DAG);
3934 }
3935 return SDValue();
3936}
3937
3938// Wide vector shift operations such as v8i32 with sign-extended
3939// operands cause Type Legalizer crashes because the target-specific
3940// extension nodes cannot be directly mapped to the 256-bit size.
3941//
3942// To resolve the crash and optimize performance, we intercept the
3943// illegal v8i32 shift in DAGCombine. We convert the shift amounts
3944// into multipliers and manually split the vector into two v4i32 halves.
3945//
3946// Before: t1: v8i32 = shl (sign_extend v8i16), const_vec
3947// After : t2: v4i32 = mul (ext_low_s v8i16), (ext_low_s narrow_vec)
3948// t3: v4i32 = mul (ext_high_s v8i16), (ext_high_s narrow_vec)
3949// t4: v8i32 = concat_vectors t2, t3
3950static SDValue performShiftCombine(SDNode *N,
3951 TargetLowering::DAGCombinerInfo &DCI) {
3952 SelectionDAG &DAG = DCI.DAG;
3953 assert(N->getOpcode() == ISD::SHL);
3954 EVT VT = N->getValueType(ResNo: 0);
3955 if (VT != MVT::v8i32)
3956 return SDValue();
3957
3958 SDValue LHS = N->getOperand(Num: 0);
3959 SDValue RHS = N->getOperand(Num: 1);
3960 unsigned ExtOpc = LHS.getOpcode();
3961 if (ExtOpc != ISD::SIGN_EXTEND && ExtOpc != ISD::ZERO_EXTEND)
3962 return SDValue();
3963
3964 if (RHS.getOpcode() != ISD::BUILD_VECTOR)
3965 return SDValue();
3966
3967 SDLoc DL(N);
3968 SDValue ExtendIn = LHS.getOperand(i: 0);
3969 EVT FromVT = ExtendIn.getValueType();
3970 if (FromVT != MVT::v8i16)
3971 return SDValue();
3972
3973 unsigned NumElts = VT.getVectorNumElements();
3974 unsigned BitWidth = FromVT.getScalarSizeInBits();
3975 bool IsSigned = (ExtOpc == ISD::SIGN_EXTEND);
3976 unsigned MaxValidShift = IsSigned ? (BitWidth - 1) : BitWidth;
3977 SmallVector<SDValue, 16> MulConsts;
3978 for (unsigned I = 0; I < NumElts; ++I) {
3979 auto *C = dyn_cast<ConstantSDNode>(Val: RHS.getOperand(i: I));
3980 if (!C)
3981 return SDValue();
3982
3983 const APInt &ShiftAmt = C->getAPIntValue();
3984 if (ShiftAmt.uge(RHS: MaxValidShift))
3985 return SDValue();
3986
3987 APInt MulAmt = APInt::getOneBitSet(numBits: BitWidth, BitNo: ShiftAmt.getZExtValue());
3988 MulConsts.push_back(Elt: DAG.getConstant(Val: MulAmt, DL, VT: FromVT.getScalarType(),
3989 /*isTarget=*/false, /*isOpaque=*/true));
3990 }
3991
3992 SDValue NarrowConst = DAG.getBuildVector(VT: FromVT, DL, Ops: MulConsts);
3993 unsigned ExtLowOpc =
3994 IsSigned ? WebAssemblyISD::EXTEND_LOW_S : WebAssemblyISD::EXTEND_LOW_U;
3995 unsigned ExtHighOpc =
3996 IsSigned ? WebAssemblyISD::EXTEND_HIGH_S : WebAssemblyISD::EXTEND_HIGH_U;
3997
3998 EVT HalfVT = MVT::v4i32;
3999 SDValue LHSLo = DAG.getNode(Opcode: ExtLowOpc, DL, VT: HalfVT, Operand: ExtendIn);
4000 SDValue LHSHi = DAG.getNode(Opcode: ExtHighOpc, DL, VT: HalfVT, Operand: ExtendIn);
4001 SDValue RHSLo = DAG.getNode(Opcode: ExtLowOpc, DL, VT: HalfVT, Operand: NarrowConst);
4002 SDValue RHSHi = DAG.getNode(Opcode: ExtHighOpc, DL, VT: HalfVT, Operand: NarrowConst);
4003 SDValue MulLo = DAG.getNode(Opcode: ISD::MUL, DL, VT: HalfVT, N1: LHSLo, N2: RHSLo);
4004 SDValue MulHi = DAG.getNode(Opcode: ISD::MUL, DL, VT: HalfVT, N1: LHSHi, N2: RHSHi);
4005 return DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL, VT, N1: MulLo, N2: MulHi);
4006}
4007
4008static SDValue performMinMaxF128Combine(SDNode *N, SelectionDAG &DAG) {
4009 if (N->getValueType(ResNo: 0) != MVT::f128)
4010 return SDValue();
4011
4012 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4013 switch (N->getOpcode()) {
4014 // wasi-libc and emscripten do not currently define fminimuml and fmaximuml.
4015 case ISD::FMINIMUM:
4016 case ISD::FMAXIMUM:
4017 return TLI.expandFMINIMUM_FMAXIMUM(N, DAG);
4018
4019 // wasi-libc and emscripten do not currently define fminimum_numl and
4020 // fmaximum_numl.
4021 case ISD::FMINIMUMNUM:
4022 case ISD::FMAXIMUMNUM:
4023 return TLI.expandFMINIMUMNUM_FMAXIMUMNUM(N, DAG);
4024
4025 default:
4026 return SDValue();
4027 }
4028}
4029
4030SDValue
4031WebAssemblyTargetLowering::PerformDAGCombine(SDNode *N,
4032 DAGCombinerInfo &DCI) const {
4033 switch (N->getOpcode()) {
4034 default:
4035 return SDValue();
4036 case ISD::BITCAST:
4037 return performBitcastCombine(N, DCI);
4038 case ISD::SETCC:
4039 return performSETCCCombine(N, DCI, Subtarget);
4040 case ISD::VECTOR_SHUFFLE:
4041 return performVECTOR_SHUFFLECombine(N, DCI);
4042 case ISD::SIGN_EXTEND:
4043 case ISD::ZERO_EXTEND:
4044 return performVectorExtendCombine(N, DCI);
4045 case ISD::UINT_TO_FP:
4046 if (auto ExtCombine = performVectorExtendToFPCombine(N, DCI, Subtarget))
4047 return ExtCombine;
4048 return performVectorNonNegToFPCombine(N, DCI);
4049 case ISD::SINT_TO_FP:
4050 return performVectorExtendToFPCombine(N, DCI, Subtarget);
4051 case ISD::FP_TO_SINT_SAT:
4052 case ISD::FP_TO_UINT_SAT:
4053 case ISD::FP_ROUND:
4054 case ISD::CONCAT_VECTORS:
4055 return performVectorTruncZeroCombine(N, DCI);
4056 case ISD::FP_TO_SINT:
4057 case ISD::FP_TO_UINT:
4058 return performConvertFPCombine(N, DAG&: DCI.DAG);
4059 case ISD::TRUNCATE:
4060 return performTruncateCombine(N, DCI);
4061 case ISD::INTRINSIC_WO_CHAIN: {
4062 if (SDValue V = performBitmaskCombine(N, DAG&: DCI.DAG))
4063 return V;
4064 return performAnyAllCombine(N, DAG&: DCI.DAG);
4065 }
4066 case ISD::MUL:
4067 return performMulCombine(N, DCI);
4068 case ISD::SHL:
4069 return performShiftCombine(N, DCI);
4070 case ISD::FMINIMUM:
4071 case ISD::FMAXIMUM:
4072 case ISD::FMINIMUMNUM:
4073 case ISD::FMAXIMUMNUM:
4074 return performMinMaxF128Combine(N, DAG&: DCI.DAG);
4075 }
4076}
4077