1//===-- WebAssemblySubtarget.cpp - WebAssembly Subtarget Information ------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file implements the WebAssembly-specific subclass of
11/// TargetSubtarget.
12///
13//===----------------------------------------------------------------------===//
14
15#include "WebAssemblySubtarget.h"
16#include "GISel/WebAssemblyCallLowering.h"
17#include "GISel/WebAssemblyLegalizerInfo.h"
18#include "GISel/WebAssemblyRegisterBankInfo.h"
19#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
20#include "WebAssembly.h"
21#include "WebAssemblyInstrInfo.h"
22#include "WebAssemblyTargetMachine.h"
23#include "llvm/MC/TargetRegistry.h"
24using namespace llvm;
25
26#define DEBUG_TYPE "wasm-subtarget"
27
28#define GET_SUBTARGETINFO_CTOR
29#define GET_SUBTARGETINFO_TARGET_DESC
30#include "WebAssemblyGenSubtargetInfo.inc"
31
32WebAssemblySubtarget &
33WebAssemblySubtarget::initializeSubtargetDependencies(StringRef CPU,
34 StringRef FS) {
35 // Determine default and user-specified characteristics
36 LLVM_DEBUG(llvm::dbgs() << "initializeSubtargetDependencies\n");
37
38 if (CPU.empty())
39 CPU = "generic";
40
41 ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS);
42
43 // WASIP3 uses cooperative multithreading, which implies using libcall
44 // thread context.
45 if (TargetTriple.getOS() == Triple::WASIp3) {
46 HasCooperativeMultithreading = true;
47 HasLibcallThreadContext = true;
48 }
49
50 FeatureBitset Bits = getFeatureBits();
51
52 // bulk-memory implies bulk-memory-opt
53 if (HasBulkMemory) {
54 HasBulkMemoryOpt = true;
55 Bits.set(WebAssembly::FeatureBulkMemoryOpt);
56 }
57
58 // gc implies reference-types
59 if (HasGC) {
60 HasReferenceTypes = true;
61 }
62
63 // reference-types implies call-indirect-overlong
64 if (HasReferenceTypes) {
65 HasCallIndirectOverlong = true;
66 Bits.set(WebAssembly::FeatureCallIndirectOverlong);
67 }
68
69 // In case we changed any bits, update `MCSubtargetInfo`'s `FeatureBitset`.
70 setFeatureBits(Bits);
71
72 return *this;
73}
74
75WebAssemblySubtarget::WebAssemblySubtarget(const Triple &TT,
76 const std::string &CPU,
77 const std::string &FS,
78 const TargetMachine &TM)
79 : WebAssemblyGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
80 TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)),
81 TLInfo(TM, *this) {
82 CallLoweringInfo.reset(p: new WebAssemblyCallLowering(*getTargetLowering()));
83 Legalizer.reset(p: new WebAssemblyLegalizerInfo(*this));
84 auto *RBI = new WebAssemblyRegisterBankInfo(*getRegisterInfo());
85 RegBankInfo.reset(p: RBI);
86
87 InstSelector.reset(p: createWebAssemblyInstructionSelector(
88 *static_cast<const WebAssemblyTargetMachine *>(&TM), *this, *RBI));
89}
90
91bool WebAssemblySubtarget::enableAtomicExpand() const {
92 // If atomics are disabled, atomic ops are lowered instead of expanded
93 return hasAtomics();
94}
95
96bool WebAssemblySubtarget::enableMachineScheduler() const {
97 // Disable the MachineScheduler for now. Even with ShouldTrackPressure set and
98 // enableMachineSchedDefaultSched overridden, it appears to have an overall
99 // negative effect for the kinds of register optimizations we're doing.
100 return false;
101}
102
103bool WebAssemblySubtarget::useAA() const { return true; }
104
105const CallLowering *WebAssemblySubtarget::getCallLowering() const {
106 return CallLoweringInfo.get();
107}
108
109InstructionSelector *WebAssemblySubtarget::getInstructionSelector() const {
110 return InstSelector.get();
111}
112
113const LegalizerInfo *WebAssemblySubtarget::getLegalizerInfo() const {
114 return Legalizer.get();
115}
116
117const RegisterBankInfo *WebAssemblySubtarget::getRegBankInfo() const {
118 return RegBankInfo.get();
119}
120