1//===-- WebAssemblySubtarget.cpp - WebAssembly Subtarget Information ------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file implements the WebAssembly-specific subclass of
11/// TargetSubtarget.
12///
13//===----------------------------------------------------------------------===//
14
15#include "WebAssemblySubtarget.h"
16#include "GISel/WebAssemblyCallLowering.h"
17#include "GISel/WebAssemblyLegalizerInfo.h"
18#include "GISel/WebAssemblyRegisterBankInfo.h"
19#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
20#include "WebAssembly.h"
21#include "WebAssemblyInstrInfo.h"
22#include "WebAssemblyTargetMachine.h"
23#include "llvm/MC/TargetRegistry.h"
24using namespace llvm;
25
26#define DEBUG_TYPE "wasm-subtarget"
27
28#define GET_SUBTARGETINFO_CTOR
29#define GET_SUBTARGETINFO_TARGET_DESC
30#include "WebAssemblyGenSubtargetInfo.inc"
31
32WebAssemblySubtarget &
33WebAssemblySubtarget::initializeSubtargetDependencies(StringRef CPU,
34 StringRef FS) {
35 // Determine default and user-specified characteristics
36 LLVM_DEBUG(llvm::dbgs() << "initializeSubtargetDependencies\n");
37
38 if (CPU.empty())
39 CPU = "generic";
40
41 ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS);
42
43 FeatureBitset Bits = getFeatureBits();
44
45 // bulk-memory implies bulk-memory-opt
46 if (HasBulkMemory) {
47 HasBulkMemoryOpt = true;
48 Bits.set(WebAssembly::FeatureBulkMemoryOpt);
49 }
50
51 // gc implies reference-types
52 if (HasGC) {
53 HasReferenceTypes = true;
54 }
55
56 // reference-types implies call-indirect-overlong
57 if (HasReferenceTypes) {
58 HasCallIndirectOverlong = true;
59 Bits.set(WebAssembly::FeatureCallIndirectOverlong);
60 }
61
62 // In case we changed any bits, update `MCSubtargetInfo`'s `FeatureBitset`.
63 setFeatureBits(Bits);
64
65 return *this;
66}
67
68WebAssemblySubtarget::WebAssemblySubtarget(const Triple &TT,
69 const std::string &CPU,
70 const std::string &FS,
71 const TargetMachine &TM)
72 : WebAssemblyGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
73 TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)),
74 TLInfo(TM, *this) {
75 CallLoweringInfo.reset(p: new WebAssemblyCallLowering(*getTargetLowering()));
76 Legalizer.reset(p: new WebAssemblyLegalizerInfo(*this));
77 auto *RBI = new WebAssemblyRegisterBankInfo(*getRegisterInfo());
78 RegBankInfo.reset(p: RBI);
79
80 InstSelector.reset(p: createWebAssemblyInstructionSelector(
81 *static_cast<const WebAssemblyTargetMachine *>(&TM), *this, *RBI));
82}
83
84bool WebAssemblySubtarget::enableAtomicExpand() const {
85 // If atomics are disabled, atomic ops are lowered instead of expanded
86 return hasAtomics();
87}
88
89bool WebAssemblySubtarget::enableMachineScheduler() const {
90 // Disable the MachineScheduler for now. Even with ShouldTrackPressure set and
91 // enableMachineSchedDefaultSched overridden, it appears to have an overall
92 // negative effect for the kinds of register optimizations we're doing.
93 return false;
94}
95
96bool WebAssemblySubtarget::useAA() const { return true; }
97
98const CallLowering *WebAssemblySubtarget::getCallLowering() const {
99 return CallLoweringInfo.get();
100}
101
102InstructionSelector *WebAssemblySubtarget::getInstructionSelector() const {
103 return InstSelector.get();
104}
105
106const LegalizerInfo *WebAssemblySubtarget::getLegalizerInfo() const {
107 return Legalizer.get();
108}
109
110const RegisterBankInfo *WebAssemblySubtarget::getRegBankInfo() const {
111 return RegBankInfo.get();
112}
113