1//===-- XCoreInstrInfo.cpp - XCore Instruction Information ----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the XCore implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "XCoreInstrInfo.h"
14#include "XCoreSubtarget.h"
15#include "llvm/CodeGen/MachineConstantPool.h"
16#include "llvm/CodeGen/MachineFrameInfo.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "llvm/CodeGen/MachineMemOperand.h"
19#include "llvm/IR/Constants.h"
20#include "llvm/IR/Function.h"
21#include "llvm/MC/MCContext.h"
22#include "llvm/Support/ErrorHandling.h"
23
24using namespace llvm;
25
26#define GET_INSTRINFO_CTOR_DTOR
27#include "XCoreGenInstrInfo.inc"
28
29namespace llvm {
30namespace XCore {
31
32 // XCore Condition Codes
33 enum CondCode {
34 COND_TRUE,
35 COND_FALSE,
36 COND_INVALID
37 };
38}
39}
40
41// Pin the vtable to this file.
42void XCoreInstrInfo::anchor() {}
43
44XCoreInstrInfo::XCoreInstrInfo(const XCoreSubtarget &ST)
45 : XCoreGenInstrInfo(ST, RI, XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
46 RI() {}
47
48static bool isZeroImm(const MachineOperand &op) {
49 return op.isImm() && op.getImm() == 0;
50}
51
52/// isLoadFromStackSlot - If the specified machine instruction is a direct
53/// load from a stack slot, return the virtual or physical register number of
54/// the destination along with the FrameIndex of the loaded stack slot. If
55/// not, return 0. This predicate must return 0 if the instruction has
56/// any side effects other than loading from the stack slot.
57Register XCoreInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
58 int &FrameIndex) const {
59 int Opcode = MI.getOpcode();
60 if (Opcode == XCore::LDWFI)
61 {
62 if ((MI.getOperand(i: 1).isFI()) && // is a stack slot
63 (MI.getOperand(i: 2).isImm()) && // the imm is zero
64 (isZeroImm(op: MI.getOperand(i: 2)))) {
65 FrameIndex = MI.getOperand(i: 1).getIndex();
66 return MI.getOperand(i: 0).getReg();
67 }
68 }
69 return 0;
70}
71
72 /// isStoreToStackSlot - If the specified machine instruction is a direct
73 /// store to a stack slot, return the virtual or physical register number of
74 /// the source reg along with the FrameIndex of the loaded stack slot. If
75 /// not, return 0. This predicate must return 0 if the instruction has
76 /// any side effects other than storing to the stack slot.
77Register XCoreInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
78 int &FrameIndex) const {
79 int Opcode = MI.getOpcode();
80 if (Opcode == XCore::STWFI)
81 {
82 if ((MI.getOperand(i: 1).isFI()) && // is a stack slot
83 (MI.getOperand(i: 2).isImm()) && // the imm is zero
84 (isZeroImm(op: MI.getOperand(i: 2)))) {
85 FrameIndex = MI.getOperand(i: 1).getIndex();
86 return MI.getOperand(i: 0).getReg();
87 }
88 }
89 return 0;
90}
91
92//===----------------------------------------------------------------------===//
93// Branch Analysis
94//===----------------------------------------------------------------------===//
95
96static inline bool IsBRU(unsigned BrOpc) {
97 return BrOpc == XCore::BRFU_u6
98 || BrOpc == XCore::BRFU_lu6
99 || BrOpc == XCore::BRBU_u6
100 || BrOpc == XCore::BRBU_lu6;
101}
102
103static inline bool IsBRT(unsigned BrOpc) {
104 return BrOpc == XCore::BRFT_ru6
105 || BrOpc == XCore::BRFT_lru6
106 || BrOpc == XCore::BRBT_ru6
107 || BrOpc == XCore::BRBT_lru6;
108}
109
110static inline bool IsBRF(unsigned BrOpc) {
111 return BrOpc == XCore::BRFF_ru6
112 || BrOpc == XCore::BRFF_lru6
113 || BrOpc == XCore::BRBF_ru6
114 || BrOpc == XCore::BRBF_lru6;
115}
116
117static inline bool IsCondBranch(unsigned BrOpc) {
118 return IsBRF(BrOpc) || IsBRT(BrOpc);
119}
120
121static inline bool IsBR_JT(unsigned BrOpc) {
122 return BrOpc == XCore::BR_JT
123 || BrOpc == XCore::BR_JT32;
124}
125
126/// GetCondFromBranchOpc - Return the XCore CC that matches
127/// the correspondent Branch instruction opcode.
128static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc)
129{
130 if (IsBRT(BrOpc)) {
131 return XCore::COND_TRUE;
132 } else if (IsBRF(BrOpc)) {
133 return XCore::COND_FALSE;
134 } else {
135 return XCore::COND_INVALID;
136 }
137}
138
139/// GetCondBranchFromCond - Return the Branch instruction
140/// opcode that matches the cc.
141static inline unsigned GetCondBranchFromCond(XCore::CondCode CC)
142{
143 switch (CC) {
144 default: llvm_unreachable("Illegal condition code!");
145 case XCore::COND_TRUE : return XCore::BRFT_lru6;
146 case XCore::COND_FALSE : return XCore::BRFF_lru6;
147 }
148}
149
150/// GetOppositeBranchCondition - Return the inverse of the specified
151/// condition, e.g. turning COND_E to COND_NE.
152static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC)
153{
154 switch (CC) {
155 default: llvm_unreachable("Illegal condition code!");
156 case XCore::COND_TRUE : return XCore::COND_FALSE;
157 case XCore::COND_FALSE : return XCore::COND_TRUE;
158 }
159}
160
161/// analyzeBranch - Analyze the branching code at the end of MBB, returning
162/// true if it cannot be understood (e.g. it's a switch dispatch or isn't
163/// implemented for a target). Upon success, this returns false and returns
164/// with the following information in various cases:
165///
166/// 1. If this block ends with no branches (it just falls through to its succ)
167/// just return false, leaving TBB/FBB null.
168/// 2. If this block ends with only an unconditional branch, it sets TBB to be
169/// the destination block.
170/// 3. If this block ends with an conditional branch and it falls through to
171/// an successor block, it sets TBB to be the branch destination block and a
172/// list of operands that evaluate the condition. These
173/// operands can be passed to other TargetInstrInfo methods to create new
174/// branches.
175/// 4. If this block ends with an conditional branch and an unconditional
176/// block, it returns the 'true' destination in TBB, the 'false' destination
177/// in FBB, and a list of operands that evaluate the condition. These
178/// operands can be passed to other TargetInstrInfo methods to create new
179/// branches.
180///
181/// Note that removeBranch and insertBranch must be implemented to support
182/// cases where this method returns success.
183///
184bool XCoreInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
185 MachineBasicBlock *&TBB,
186 MachineBasicBlock *&FBB,
187 SmallVectorImpl<MachineOperand> &Cond,
188 bool AllowModify) const {
189 // If the block has no terminators, it just falls into the block after it.
190 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
191 if (I == MBB.end())
192 return false;
193
194 if (!isUnpredicatedTerminator(MI: *I))
195 return false;
196
197 // Get the last instruction in the block.
198 MachineInstr *LastInst = &*I;
199
200 // If there is only one terminator instruction, process it.
201 if (I == MBB.begin() || !isUnpredicatedTerminator(MI: *--I)) {
202 if (IsBRU(BrOpc: LastInst->getOpcode())) {
203 TBB = LastInst->getOperand(i: 0).getMBB();
204 return false;
205 }
206
207 XCore::CondCode BranchCode = GetCondFromBranchOpc(BrOpc: LastInst->getOpcode());
208 if (BranchCode == XCore::COND_INVALID)
209 return true; // Can't handle indirect branch.
210
211 // Conditional branch
212 // Block ends with fall-through condbranch.
213
214 TBB = LastInst->getOperand(i: 1).getMBB();
215 Cond.push_back(Elt: MachineOperand::CreateImm(Val: BranchCode));
216 Cond.push_back(Elt: LastInst->getOperand(i: 0));
217 return false;
218 }
219
220 // Get the instruction before it if it's a terminator.
221 MachineInstr *SecondLastInst = &*I;
222
223 // If there are three terminators, we don't know what sort of block this is.
224 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(MI: *--I))
225 return true;
226
227 unsigned SecondLastOpc = SecondLastInst->getOpcode();
228 XCore::CondCode BranchCode = GetCondFromBranchOpc(BrOpc: SecondLastOpc);
229
230 // If the block ends with conditional branch followed by unconditional,
231 // handle it.
232 if (BranchCode != XCore::COND_INVALID
233 && IsBRU(BrOpc: LastInst->getOpcode())) {
234
235 TBB = SecondLastInst->getOperand(i: 1).getMBB();
236 Cond.push_back(Elt: MachineOperand::CreateImm(Val: BranchCode));
237 Cond.push_back(Elt: SecondLastInst->getOperand(i: 0));
238
239 FBB = LastInst->getOperand(i: 0).getMBB();
240 return false;
241 }
242
243 // If the block ends with two unconditional branches, handle it. The second
244 // one is not executed, so remove it.
245 if (IsBRU(BrOpc: SecondLastInst->getOpcode()) &&
246 IsBRU(BrOpc: LastInst->getOpcode())) {
247 TBB = SecondLastInst->getOperand(i: 0).getMBB();
248 I = LastInst;
249 if (AllowModify)
250 I->eraseFromParent();
251 return false;
252 }
253
254 // Likewise if it ends with a branch table followed by an unconditional branch.
255 if (IsBR_JT(BrOpc: SecondLastInst->getOpcode()) && IsBRU(BrOpc: LastInst->getOpcode())) {
256 I = LastInst;
257 if (AllowModify)
258 I->eraseFromParent();
259 return true;
260 }
261
262 // Otherwise, can't handle this.
263 return true;
264}
265
266unsigned XCoreInstrInfo::insertBranch(MachineBasicBlock &MBB,
267 MachineBasicBlock *TBB,
268 MachineBasicBlock *FBB,
269 ArrayRef<MachineOperand> Cond,
270 const DebugLoc &DL,
271 int *BytesAdded) const {
272 // Shouldn't be a fall through.
273 assert(TBB && "insertBranch must not be told to insert a fallthrough");
274 assert((Cond.size() == 2 || Cond.size() == 0) &&
275 "Unexpected number of components!");
276 assert(!BytesAdded && "code size not handled");
277
278 if (!FBB) { // One way branch.
279 if (Cond.empty()) {
280 // Unconditional branch
281 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: XCore::BRFU_lu6)).addMBB(MBB: TBB);
282 } else {
283 // Conditional branch.
284 unsigned Opc = GetCondBranchFromCond(CC: (XCore::CondCode)Cond[0].getImm());
285 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: Opc)).addReg(RegNo: Cond[1].getReg())
286 .addMBB(MBB: TBB);
287 }
288 return 1;
289 }
290
291 // Two-way Conditional branch.
292 assert(Cond.size() == 2 && "Unexpected number of components!");
293 unsigned Opc = GetCondBranchFromCond(CC: (XCore::CondCode)Cond[0].getImm());
294 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: Opc)).addReg(RegNo: Cond[1].getReg())
295 .addMBB(MBB: TBB);
296 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: XCore::BRFU_lu6)).addMBB(MBB: FBB);
297 return 2;
298}
299
300unsigned
301XCoreInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const {
302 assert(!BytesRemoved && "code size not handled");
303
304 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
305 if (I == MBB.end())
306 return 0;
307
308 if (!IsBRU(BrOpc: I->getOpcode()) && !IsCondBranch(BrOpc: I->getOpcode()))
309 return 0;
310
311 // Remove the branch.
312 I->eraseFromParent();
313
314 I = MBB.end();
315
316 if (I == MBB.begin()) return 1;
317 --I;
318 if (!IsCondBranch(BrOpc: I->getOpcode()))
319 return 1;
320
321 // Remove the branch.
322 I->eraseFromParent();
323 return 2;
324}
325
326void XCoreInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
327 MachineBasicBlock::iterator I,
328 const DebugLoc &DL, Register DestReg,
329 Register SrcReg, bool KillSrc,
330 bool RenamableDest, bool RenamableSrc) const {
331 bool GRDest = XCore::GRRegsRegClass.contains(Reg: DestReg);
332 bool GRSrc = XCore::GRRegsRegClass.contains(Reg: SrcReg);
333
334 if (GRDest && GRSrc) {
335 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: XCore::ADD_2rus), DestReg)
336 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrc))
337 .addImm(Val: 0);
338 return;
339 }
340
341 if (GRDest && SrcReg == XCore::SP) {
342 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: XCore::LDAWSP_ru6), DestReg).addImm(Val: 0);
343 return;
344 }
345
346 if (DestReg == XCore::SP && GRSrc) {
347 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: XCore::SETSP_1r))
348 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrc));
349 return;
350 }
351 llvm_unreachable("Impossible reg-to-reg copy");
352}
353
354void XCoreInstrInfo::storeRegToStackSlot(
355 MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg,
356 bool isKill, int FrameIndex, const TargetRegisterClass *RC,
357
358 Register VReg, MachineInstr::MIFlag Flags) const {
359 DebugLoc DL;
360 if (I != MBB.end() && !I->isDebugInstr())
361 DL = I->getDebugLoc();
362 MachineFunction *MF = MBB.getParent();
363 const MachineFrameInfo &MFI = MF->getFrameInfo();
364 MachineMemOperand *MMO = MF->getMachineMemOperand(
365 PtrInfo: MachinePointerInfo::getFixedStack(MF&: *MF, FI: FrameIndex),
366 F: MachineMemOperand::MOStore, Size: MFI.getObjectSize(ObjectIdx: FrameIndex),
367 BaseAlignment: MFI.getObjectAlign(ObjectIdx: FrameIndex));
368 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: XCore::STWFI))
369 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill))
370 .addFrameIndex(Idx: FrameIndex)
371 .addImm(Val: 0)
372 .addMemOperand(MMO);
373}
374
375void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
376 MachineBasicBlock::iterator I,
377 Register DestReg, int FrameIndex,
378 const TargetRegisterClass *RC,
379 Register VReg, unsigned SubReg,
380 MachineInstr::MIFlag Flags) const {
381 DebugLoc DL;
382 if (I != MBB.end() && !I->isDebugInstr())
383 DL = I->getDebugLoc();
384 MachineFunction *MF = MBB.getParent();
385 const MachineFrameInfo &MFI = MF->getFrameInfo();
386 MachineMemOperand *MMO = MF->getMachineMemOperand(
387 PtrInfo: MachinePointerInfo::getFixedStack(MF&: *MF, FI: FrameIndex),
388 F: MachineMemOperand::MOLoad, Size: MFI.getObjectSize(ObjectIdx: FrameIndex),
389 BaseAlignment: MFI.getObjectAlign(ObjectIdx: FrameIndex));
390 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: XCore::LDWFI), DestReg)
391 .addFrameIndex(Idx: FrameIndex)
392 .addImm(Val: 0)
393 .addMemOperand(MMO);
394}
395
396bool XCoreInstrInfo::
397reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
398 assert((Cond.size() == 2) &&
399 "Invalid XCore branch condition!");
400 Cond[0].setImm(GetOppositeBranchCondition(CC: (XCore::CondCode)Cond[0].getImm()));
401 return false;
402}
403
404static inline bool isImmU6(unsigned val) {
405 return val < (1 << 6);
406}
407
408static inline bool isImmU16(unsigned val) {
409 return val < (1 << 16);
410}
411
412static bool isImmMskBitp(unsigned val) {
413 if (!isMask_32(Value: val)) {
414 return false;
415 }
416 int N = llvm::bit_width(Value: val);
417 return (N >= 1 && N <= 8) || N == 16 || N == 24 || N == 32;
418}
419
420MachineBasicBlock::iterator XCoreInstrInfo::loadImmediate(
421 MachineBasicBlock &MBB,
422 MachineBasicBlock::iterator MI,
423 unsigned Reg, uint64_t Value) const {
424 DebugLoc dl;
425 if (MI != MBB.end() && !MI->isDebugInstr())
426 dl = MI->getDebugLoc();
427 if (isImmMskBitp(val: Value)) {
428 int N = llvm::bit_width(Value);
429 return BuildMI(BB&: MBB, I: MI, MIMD: dl, MCID: get(Opcode: XCore::MKMSK_rus), DestReg: Reg)
430 .addImm(Val: N)
431 .getInstr();
432 }
433 if (isImmU16(val: Value)) {
434 int Opcode = isImmU6(val: Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
435 return BuildMI(BB&: MBB, I: MI, MIMD: dl, MCID: get(Opcode), DestReg: Reg).addImm(Val: Value).getInstr();
436 }
437 MachineConstantPool *ConstantPool = MBB.getParent()->getConstantPool();
438 const Constant *C = ConstantInt::get(
439 Ty: Type::getInt32Ty(C&: MBB.getParent()->getFunction().getContext()), V: Value);
440 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Alignment: Align(4));
441 return BuildMI(BB&: MBB, I: MI, MIMD: dl, MCID: get(Opcode: XCore::LDWCP_lru6), DestReg: Reg)
442 .addConstantPoolIndex(Idx)
443 .getInstr();
444}
445