1//===-- FunctionLoweringInfo.cpp ------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This implements routines for translating functions from LLVM IR into
10// Machine IR.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/FunctionLoweringInfo.h"
15#include "llvm/ADT/APInt.h"
16#include "llvm/Analysis/UniformityAnalysis.h"
17#include "llvm/CodeGen/Analysis.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/CodeGen/TargetFrameLowering.h"
23#include "llvm/CodeGen/TargetInstrInfo.h"
24#include "llvm/CodeGen/TargetLowering.h"
25#include "llvm/CodeGen/TargetRegisterInfo.h"
26#include "llvm/CodeGen/TargetSubtargetInfo.h"
27#include "llvm/CodeGen/WasmEHFuncInfo.h"
28#include "llvm/CodeGen/WinEHFuncInfo.h"
29#include "llvm/IR/DataLayout.h"
30#include "llvm/IR/DerivedTypes.h"
31#include "llvm/IR/Function.h"
32#include "llvm/IR/Instructions.h"
33#include "llvm/IR/IntrinsicInst.h"
34#include "llvm/IR/Intrinsics.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38#include <algorithm>
39using namespace llvm;
40
41#define DEBUG_TYPE "function-lowering-info"
42
43/// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
44/// PHI nodes or outside of the basic block that defines it, or used by a
45/// switch or atomic instruction, which may expand to multiple basic blocks.
46static bool isUsedOutsideOfDefiningBlock(const Instruction *I) {
47 if (I->use_empty()) return false;
48 if (isa<PHINode>(Val: I)) return true;
49 const BasicBlock *BB = I->getParent();
50 for (const User *U : I->users())
51 if (cast<Instruction>(Val: U)->getParent() != BB || isa<PHINode>(Val: U))
52 return true;
53
54 return false;
55}
56
57static ISD::NodeType getPreferredExtendForValue(const Instruction *I) {
58 // For the users of the source value being used for compare instruction, if
59 // the number of signed predicate is greater than unsigned predicate, we
60 // prefer to use SIGN_EXTEND.
61 //
62 // With this optimization, we would be able to reduce some redundant sign or
63 // zero extension instruction, and eventually more machine CSE opportunities
64 // can be exposed.
65 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
66 unsigned NumOfSigned = 0, NumOfUnsigned = 0;
67 for (const Use &U : I->uses()) {
68 if (const auto *CI = dyn_cast<CmpInst>(Val: U.getUser())) {
69 NumOfSigned += CI->isSigned();
70 NumOfUnsigned += CI->isUnsigned();
71 }
72 if (const auto *CallI = dyn_cast<CallBase>(Val: U.getUser())) {
73 if (!CallI->isArgOperand(U: &U))
74 continue;
75 unsigned ArgNo = CallI->getArgOperandNo(U: &U);
76 NumOfUnsigned += CallI->paramHasAttr(ArgNo, Kind: Attribute::ZExt);
77 NumOfSigned += CallI->paramHasAttr(ArgNo, Kind: Attribute::SExt);
78 }
79 }
80 if (NumOfSigned > NumOfUnsigned)
81 ExtendKind = ISD::SIGN_EXTEND;
82
83 return ExtendKind;
84}
85
86void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
87 SelectionDAG *DAG) {
88 Fn = &fn;
89 MF = &mf;
90 TLI = MF->getSubtarget().getTargetLowering();
91 RegInfo = &MF->getRegInfo();
92 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
93 UA = DAG->getUniformityInfo();
94
95 // Check whether the function can return without sret-demotion.
96 SmallVector<ISD::OutputArg, 4> Outs;
97 CallingConv::ID CC = Fn->getCallingConv();
98
99 GetReturnInfo(CC, ReturnType: Fn->getReturnType(), attr: Fn->getAttributes(), Outs, TLI: *TLI,
100 DL: mf.getDataLayout());
101 CanLowerReturn =
102 TLI->CanLowerReturn(CC, *MF, Fn->isVarArg(), Outs, Fn->getContext(), RetTy: Fn->getReturnType());
103
104 // If this personality uses funclets, we need to do a bit more work.
105 DenseMap<const AllocaInst *, TinyPtrVector<int *>> CatchObjects;
106 EHPersonality Personality = classifyEHPersonality(
107 Pers: Fn->hasPersonalityFn() ? Fn->getPersonalityFn() : nullptr);
108 if (isFuncletEHPersonality(Pers: Personality)) {
109 // Calculate state numbers if we haven't already.
110 WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo();
111 if (Personality == EHPersonality::MSVC_CXX)
112 calculateWinCXXEHStateNumbers(ParentFn: &fn, FuncInfo&: EHInfo);
113 else if (isAsynchronousEHPersonality(Pers: Personality))
114 calculateSEHStateNumbers(ParentFn: &fn, FuncInfo&: EHInfo);
115 else if (Personality == EHPersonality::CoreCLR)
116 calculateClrEHStateNumbers(Fn: &fn, FuncInfo&: EHInfo);
117
118 // Map all BB references in the WinEH data to MBBs.
119 for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
120 for (WinEHHandlerType &H : TBME.HandlerArray) {
121 if (const AllocaInst *AI = H.CatchObj.Alloca)
122 CatchObjects[AI].push_back(NewVal: &H.CatchObj.FrameIndex);
123 else
124 H.CatchObj.FrameIndex = INT_MAX;
125 }
126 }
127 }
128
129 // Initialize the mapping of values to registers. This is only set up for
130 // instruction values that are used outside of the block that defines
131 // them.
132 const Align StackAlign = TFI->getStackAlign();
133 for (const BasicBlock &BB : *Fn) {
134 for (const Instruction &I : BB) {
135 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Val: &I)) {
136 Type *Ty = AI->getAllocatedType();
137 Align Alignment = AI->getAlign();
138
139 // Static allocas can be folded into the initial stack frame
140 // adjustment. For targets that don't realign the stack, don't
141 // do this if there is an extra alignment requirement.
142 if (AI->isStaticAlloca() &&
143 (TFI->isStackRealignable() || (Alignment <= StackAlign))) {
144 const ConstantInt *CUI = cast<ConstantInt>(Val: AI->getArraySize());
145 uint64_t TySize =
146 MF->getDataLayout().getTypeAllocSize(Ty).getKnownMinValue();
147
148 TySize *= CUI->getZExtValue(); // Get total allocated size.
149 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
150 int FrameIndex = INT_MAX;
151 auto Iter = CatchObjects.find(Val: AI);
152 if (Iter != CatchObjects.end() && TLI->needsFixedCatchObjects()) {
153 FrameIndex = MF->getFrameInfo().CreateFixedObject(
154 Size: TySize, SPOffset: 0, /*IsImmutable=*/false, /*isAliased=*/true);
155 MF->getFrameInfo().setObjectAlignment(ObjectIdx: FrameIndex, Alignment);
156 } else {
157 FrameIndex = MF->getFrameInfo().CreateStackObject(Size: TySize, Alignment,
158 isSpillSlot: false, Alloca: AI);
159 }
160
161 // Scalable vectors and structures that contain scalable vectors may
162 // need a special StackID to distinguish them from other (fixed size)
163 // stack objects.
164 if (Ty->isScalableTy())
165 MF->getFrameInfo().setStackID(ObjectIdx: FrameIndex,
166 ID: TFI->getStackIDForScalableVectors());
167
168 StaticAllocaMap[AI] = FrameIndex;
169 // Update the catch handler information.
170 if (Iter != CatchObjects.end()) {
171 for (int *CatchObjPtr : Iter->second)
172 *CatchObjPtr = FrameIndex;
173 }
174 } else {
175 // FIXME: Overaligned static allocas should be grouped into
176 // a single dynamic allocation instead of using a separate
177 // stack allocation for each one.
178 // Inform the Frame Information that we have variable-sized objects.
179 MF->getFrameInfo().CreateVariableSizedObject(
180 Alignment: Alignment <= StackAlign ? Align(1) : Alignment, Alloca: AI);
181 }
182 } else if (auto *Call = dyn_cast<CallBase>(Val: &I)) {
183 // Look for inline asm that clobbers the SP register.
184 if (Call->isInlineAsm()) {
185 Register SP = TLI->getStackPointerRegisterToSaveRestore();
186 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
187 std::vector<TargetLowering::AsmOperandInfo> Ops =
188 TLI->ParseConstraints(DL: Fn->getDataLayout(), TRI,
189 Call: *Call);
190 for (TargetLowering::AsmOperandInfo &Op : Ops) {
191 if (Op.Type == InlineAsm::isClobber) {
192 // Clobbers don't have SDValue operands, hence SDValue().
193 TLI->ComputeConstraintToUse(OpInfo&: Op, Op: SDValue(), DAG);
194 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
195 TLI->getRegForInlineAsmConstraint(TRI, Constraint: Op.ConstraintCode,
196 VT: Op.ConstraintVT);
197 if (PhysReg.first == SP)
198 MF->getFrameInfo().setHasOpaqueSPAdjustment(true);
199 }
200 }
201 }
202 if (const auto *II = dyn_cast<IntrinsicInst>(Val: &I)) {
203 switch (II->getIntrinsicID()) {
204 case Intrinsic::vastart:
205 // Look for calls to the @llvm.va_start intrinsic. We can omit
206 // some prologue boilerplate for variadic functions that don't
207 // examine their arguments.
208 MF->getFrameInfo().setHasVAStart(true);
209 break;
210 case Intrinsic::fake_use:
211 // Look for llvm.fake.uses, so that we can remove loads into fake
212 // uses later if necessary.
213 MF->setHasFakeUses(true);
214 break;
215 default:
216 break;
217 }
218 }
219
220 // If we have a musttail call in a variadic function, we need to ensure
221 // we forward implicit register parameters.
222 if (const auto *CI = dyn_cast<CallInst>(Val: &I)) {
223 if (CI->isMustTailCall() && Fn->isVarArg())
224 MF->getFrameInfo().setHasMustTailInVarArgFunc(true);
225 }
226
227 // Determine if there is a call to setjmp in the machine function.
228 if (Call->hasFnAttr(Kind: Attribute::ReturnsTwice))
229 MF->setExposesReturnsTwice(true);
230 }
231
232 // Mark values used outside their block as exported, by allocating
233 // a virtual register for them.
234 if (isUsedOutsideOfDefiningBlock(I: &I))
235 if (!isa<AllocaInst>(Val: I) || !StaticAllocaMap.count(Val: cast<AllocaInst>(Val: &I)))
236 InitializeRegForValue(V: &I);
237
238 // Decide the preferred extend type for a value. This iterates over all
239 // users and therefore isn't cheap, so don't do this at O0.
240 if (DAG->getOptLevel() != CodeGenOptLevel::None)
241 PreferredExtendType[&I] = getPreferredExtendForValue(I: &I);
242 }
243 }
244
245 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
246 // also creates the initial PHI MachineInstrs, though none of the input
247 // operands are populated.
248 MBBMap.resize(N: Fn->getMaxBlockNumber());
249 for (const BasicBlock &BB : *Fn) {
250 // Don't create MachineBasicBlocks for imaginary EH pad blocks. These blocks
251 // are really data, and no instructions can live here.
252 if (BB.isEHPad()) {
253 BasicBlock::const_iterator PadInst = BB.getFirstNonPHIIt();
254 // If this is a non-landingpad EH pad, mark this function as using
255 // funclets.
256 // FIXME: SEH catchpads do not create EH scope/funclets, so we could avoid
257 // setting this in such cases in order to improve frame layout.
258 if (!isa<LandingPadInst>(Val: PadInst)) {
259 MF->setHasEHScopes(true);
260 MF->setHasEHFunclets(true);
261 MF->getFrameInfo().setHasOpaqueSPAdjustment(true);
262 }
263 if (isa<CatchSwitchInst>(Val: PadInst)) {
264 assert(BB.begin() == PadInst &&
265 "WinEHPrepare failed to remove PHIs from imaginary BBs");
266 continue;
267 }
268 if (isa<FuncletPadInst>(Val: PadInst) &&
269 Personality != EHPersonality::Wasm_CXX)
270 assert(BB.begin() == PadInst && "WinEHPrepare failed to demote PHIs");
271 }
272
273 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB: &BB);
274 MBBMap[BB.getNumber()] = MBB;
275 MF->push_back(MBB);
276
277 // Transfer the address-taken flag. This is necessary because there could
278 // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only
279 // the first one should be marked.
280 if (BB.hasAddressTaken())
281 MBB->setAddressTakenIRBlock(const_cast<BasicBlock *>(&BB));
282
283 // Mark landing pad blocks.
284 if (BB.isEHPad())
285 MBB->setIsEHPad();
286
287 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
288 // appropriate.
289 for (const PHINode &PN : BB.phis()) {
290 if (PN.use_empty())
291 continue;
292
293 // Skip empty types
294 if (PN.getType()->isEmptyTy())
295 continue;
296
297 DebugLoc DL = PN.getDebugLoc();
298 Register PHIReg = ValueMap[&PN];
299 assert(PHIReg && "PHI node does not have an assigned virtual register!");
300
301 SmallVector<EVT, 4> ValueVTs;
302 ComputeValueVTs(TLI: *TLI, DL: MF->getDataLayout(), Ty: PN.getType(), ValueVTs);
303 for (EVT VT : ValueVTs) {
304 unsigned NumRegisters = TLI->getNumRegisters(Context&: Fn->getContext(), VT);
305 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
306 for (unsigned i = 0; i != NumRegisters; ++i)
307 BuildMI(BB: MBB, MIMD: DL, MCID: TII->get(Opcode: TargetOpcode::PHI), DestReg: PHIReg + i);
308 PHIReg += NumRegisters;
309 }
310 }
311 }
312
313 if (isFuncletEHPersonality(Pers: Personality)) {
314 WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo();
315
316 // Map all BB references in the WinEH data to MBBs.
317 for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
318 for (WinEHHandlerType &H : TBME.HandlerArray) {
319 if (H.Handler)
320 H.Handler = getMBB(BB: cast<const BasicBlock *>(Val&: H.Handler));
321 }
322 }
323 for (CxxUnwindMapEntry &UME : EHInfo.CxxUnwindMap)
324 if (UME.Cleanup)
325 UME.Cleanup = getMBB(BB: cast<const BasicBlock *>(Val&: UME.Cleanup));
326 for (SEHUnwindMapEntry &UME : EHInfo.SEHUnwindMap)
327 UME.Handler = getMBB(BB: cast<const BasicBlock *>(Val&: UME.Handler));
328 for (ClrEHUnwindMapEntry &CME : EHInfo.ClrEHUnwindMap)
329 CME.Handler = getMBB(BB: cast<const BasicBlock *>(Val&: CME.Handler));
330 } else if (Personality == EHPersonality::Wasm_CXX) {
331 WasmEHFuncInfo &EHInfo = *MF->getWasmEHFuncInfo();
332 calculateWasmEHInfo(F: &fn, EHInfo);
333
334 // Map all BB references in the Wasm EH data to MBBs.
335 DenseMap<BBOrMBB, BBOrMBB> SrcToUnwindDest;
336 for (auto &KV : EHInfo.SrcToUnwindDest) {
337 const auto *Src = cast<const BasicBlock *>(Val&: KV.first);
338 const auto *Dest = cast<const BasicBlock *>(Val&: KV.second);
339 SrcToUnwindDest[getMBB(BB: Src)] = getMBB(BB: Dest);
340 }
341 EHInfo.SrcToUnwindDest = std::move(SrcToUnwindDest);
342 DenseMap<BBOrMBB, SmallPtrSet<BBOrMBB, 4>> UnwindDestToSrcs;
343 for (auto &KV : EHInfo.UnwindDestToSrcs) {
344 const auto *Dest = cast<const BasicBlock *>(Val&: KV.first);
345 MachineBasicBlock *DestMBB = getMBB(BB: Dest);
346 auto &Srcs = UnwindDestToSrcs[DestMBB];
347 for (const auto P : KV.second)
348 Srcs.insert(Ptr: getMBB(BB: cast<const BasicBlock *>(Val: P)));
349 }
350 EHInfo.UnwindDestToSrcs = std::move(UnwindDestToSrcs);
351 }
352}
353
354/// clear - Clear out all the function-specific state. This returns this
355/// FunctionLoweringInfo to an empty state, ready to be used for a
356/// different function.
357void FunctionLoweringInfo::clear() {
358 MBBMap.clear();
359 ValueMap.clear();
360 VirtReg2Value.clear();
361 StaticAllocaMap.clear();
362 LiveOutRegInfo.clear();
363 VisitedBBs.clear();
364 ArgDbgValues.clear();
365 DescribedArgs.clear();
366 ByValArgFrameIndexMap.clear();
367 RegFixups.clear();
368 RegsWithFixups.clear();
369 StatepointStackSlots.clear();
370 StatepointRelocationMaps.clear();
371 PreferredExtendType.clear();
372 PreprocessedDVRDeclares.clear();
373}
374
375/// CreateReg - Allocate a single virtual register for the given type.
376Register FunctionLoweringInfo::CreateReg(MVT VT, bool isDivergent) {
377 return RegInfo->createVirtualRegister(RegClass: TLI->getRegClassFor(VT, isDivergent));
378}
379
380/// CreateRegs - Allocate the appropriate number of virtual registers of
381/// the correctly promoted or expanded types. Assign these registers
382/// consecutive vreg numbers and return the first assigned number.
383///
384/// In the case that the given value has struct or array type, this function
385/// will assign registers for each member or element.
386///
387Register FunctionLoweringInfo::CreateRegs(Type *Ty, bool isDivergent) {
388 SmallVector<EVT, 4> ValueVTs;
389 ComputeValueVTs(TLI: *TLI, DL: MF->getDataLayout(), Ty, ValueVTs);
390
391 Register FirstReg;
392 for (EVT ValueVT : ValueVTs) {
393 MVT RegisterVT = TLI->getRegisterType(Context&: Ty->getContext(), VT: ValueVT);
394
395 unsigned NumRegs = TLI->getNumRegisters(Context&: Ty->getContext(), VT: ValueVT);
396 for (unsigned i = 0; i != NumRegs; ++i) {
397 Register R = CreateReg(VT: RegisterVT, isDivergent);
398 if (!FirstReg) FirstReg = R;
399 }
400 }
401 return FirstReg;
402}
403
404Register FunctionLoweringInfo::CreateRegs(const Value *V) {
405 return CreateRegs(Ty: V->getType(), isDivergent: UA && UA->isDivergent(V) &&
406 !TLI->requiresUniformRegister(MF&: *MF, V));
407}
408
409Register FunctionLoweringInfo::InitializeRegForValue(const Value *V) {
410 // Tokens live in vregs only when used for convergence control.
411 if (V->getType()->isTokenTy() && !isa<ConvergenceControlInst>(Val: V))
412 return 0;
413 Register &R = ValueMap[V];
414 assert(R == Register() && "Already initialized this value register!");
415 assert(VirtReg2Value.empty());
416 return R = CreateRegs(V);
417}
418
419/// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
420/// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
421/// the register's LiveOutInfo is for a smaller bit width, it is extended to
422/// the larger bit width by zero extension. The bit width must be no smaller
423/// than the LiveOutInfo's existing bit width.
424const FunctionLoweringInfo::LiveOutInfo *
425FunctionLoweringInfo::GetLiveOutRegInfo(Register Reg, unsigned BitWidth) {
426 if (!LiveOutRegInfo.inBounds(n: Reg))
427 return nullptr;
428
429 LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
430 if (!LOI->IsValid)
431 return nullptr;
432
433 if (BitWidth > LOI->Known.getBitWidth()) {
434 LOI->NumSignBits = 1;
435 LOI->Known = LOI->Known.anyext(BitWidth);
436 }
437
438 return LOI;
439}
440
441/// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
442/// register based on the LiveOutInfo of its operands.
443void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
444 Type *Ty = PN->getType();
445 if (!Ty->isIntegerTy() || Ty->isVectorTy())
446 return;
447
448 SmallVector<EVT, 1> ValueVTs;
449 ComputeValueVTs(TLI: *TLI, DL: MF->getDataLayout(), Ty, ValueVTs);
450 assert(ValueVTs.size() == 1 &&
451 "PHIs with non-vector integer types should have a single VT.");
452 EVT IntVT = ValueVTs[0];
453
454 if (TLI->getNumRegisters(Context&: PN->getContext(), VT: IntVT) != 1)
455 return;
456 IntVT = TLI->getRegisterType(Context&: PN->getContext(), VT: IntVT);
457 unsigned BitWidth = IntVT.getSizeInBits();
458
459 auto It = ValueMap.find(Val: PN);
460 if (It == ValueMap.end())
461 return;
462
463 Register DestReg = It->second;
464 if (DestReg == 0)
465 return;
466 assert(DestReg.isVirtual() && "Expected a virtual reg");
467 LiveOutRegInfo.grow(n: DestReg);
468 LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
469
470 Value *V = PN->getIncomingValue(i: 0);
471 if (isa<UndefValue>(Val: V) || isa<ConstantExpr>(Val: V)) {
472 DestLOI.NumSignBits = 1;
473 DestLOI.Known = KnownBits(BitWidth);
474 return;
475 }
476
477 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val: V)) {
478 APInt Val;
479 if (TLI->signExtendConstant(C: CI))
480 Val = CI->getValue().sext(width: BitWidth);
481 else
482 Val = CI->getValue().zext(width: BitWidth);
483 DestLOI.NumSignBits = Val.getNumSignBits();
484 DestLOI.Known = KnownBits::makeConstant(C: Val);
485 } else {
486 assert(ValueMap.count(V) && "V should have been placed in ValueMap when its"
487 "CopyToReg node was created.");
488 Register SrcReg = ValueMap[V];
489 if (!SrcReg.isVirtual()) {
490 DestLOI.IsValid = false;
491 return;
492 }
493 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(Reg: SrcReg, BitWidth);
494 if (!SrcLOI) {
495 DestLOI.IsValid = false;
496 return;
497 }
498 DestLOI = *SrcLOI;
499 }
500
501 assert(DestLOI.Known.Zero.getBitWidth() == BitWidth &&
502 DestLOI.Known.One.getBitWidth() == BitWidth &&
503 "Masks should have the same bit width as the type.");
504
505 for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) {
506 Value *V = PN->getIncomingValue(i);
507 if (isa<UndefValue>(Val: V) || isa<ConstantExpr>(Val: V)) {
508 DestLOI.NumSignBits = 1;
509 DestLOI.Known = KnownBits(BitWidth);
510 return;
511 }
512
513 if (ConstantInt *CI = dyn_cast<ConstantInt>(Val: V)) {
514 APInt Val;
515 if (TLI->signExtendConstant(C: CI))
516 Val = CI->getValue().sext(width: BitWidth);
517 else
518 Val = CI->getValue().zext(width: BitWidth);
519 DestLOI.NumSignBits = std::min(a: DestLOI.NumSignBits, b: Val.getNumSignBits());
520 DestLOI.Known.Zero &= ~Val;
521 DestLOI.Known.One &= Val;
522 continue;
523 }
524
525 assert(ValueMap.count(V) && "V should have been placed in ValueMap when "
526 "its CopyToReg node was created.");
527 Register SrcReg = ValueMap[V];
528 if (!SrcReg.isVirtual()) {
529 DestLOI.IsValid = false;
530 return;
531 }
532 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(Reg: SrcReg, BitWidth);
533 if (!SrcLOI) {
534 DestLOI.IsValid = false;
535 return;
536 }
537 DestLOI.NumSignBits = std::min(a: DestLOI.NumSignBits, b: SrcLOI->NumSignBits);
538 DestLOI.Known = DestLOI.Known.intersectWith(RHS: SrcLOI->Known);
539 }
540}
541
542/// setArgumentFrameIndex - Record frame index for the byval
543/// argument. This overrides previous frame index entry for this argument,
544/// if any.
545void FunctionLoweringInfo::setArgumentFrameIndex(const Argument *A,
546 int FI) {
547 ByValArgFrameIndexMap[A] = FI;
548}
549
550/// getArgumentFrameIndex - Get frame index for the byval argument.
551/// If the argument does not have any assigned frame index then 0 is
552/// returned.
553int FunctionLoweringInfo::getArgumentFrameIndex(const Argument *A) {
554 auto I = ByValArgFrameIndexMap.find(Val: A);
555 if (I != ByValArgFrameIndexMap.end())
556 return I->second;
557 LLVM_DEBUG(dbgs() << "Argument does not have assigned frame index!\n");
558 return INT_MAX;
559}
560
561Register FunctionLoweringInfo::getCatchPadExceptionPointerVReg(
562 const Value *CPI, const TargetRegisterClass *RC) {
563 MachineRegisterInfo &MRI = MF->getRegInfo();
564 auto I = CatchPadExceptionPointers.insert(KV: {CPI, 0});
565 Register &VReg = I.first->second;
566 if (I.second)
567 VReg = MRI.createVirtualRegister(RegClass: RC);
568 assert(VReg && "null vreg in exception pointer table!");
569 return VReg;
570}
571
572const Value *
573FunctionLoweringInfo::getValueFromVirtualReg(Register Vreg) {
574 if (VirtReg2Value.empty()) {
575 SmallVector<EVT, 4> ValueVTs;
576 for (auto &P : ValueMap) {
577 ValueVTs.clear();
578 ComputeValueVTs(TLI: *TLI, DL: Fn->getDataLayout(),
579 Ty: P.first->getType(), ValueVTs);
580 Register Reg = P.second;
581 for (EVT VT : ValueVTs) {
582 unsigned NumRegisters = TLI->getNumRegisters(Context&: Fn->getContext(), VT);
583 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
584 VirtReg2Value[Reg++] = P.first;
585 }
586 }
587 }
588 return VirtReg2Value.lookup(Val: Vreg);
589}
590