1//===-- AMDGPUMCCodeEmitter.cpp - AMDGPU Code Emitter ---------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// The AMDGPU code emitter produces machine code that can be executed
11/// directly on the GPU device.
12//
13//===----------------------------------------------------------------------===//
14
15#include "MCTargetDesc/AMDGPUFixupKinds.h"
16#include "MCTargetDesc/AMDGPUMCExpr.h"
17#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
18#include "SIDefines.h"
19#include "Utils/AMDGPUBaseInfo.h"
20#include "llvm/ADT/APInt.h"
21#include "llvm/MC/MCCodeEmitter.h"
22#include "llvm/MC/MCContext.h"
23#include "llvm/MC/MCExpr.h"
24#include "llvm/MC/MCInstrInfo.h"
25#include "llvm/MC/MCRegisterInfo.h"
26#include "llvm/MC/MCSubtargetInfo.h"
27#include "llvm/Support/Casting.h"
28#include "llvm/Support/EndianStream.h"
29#include <optional>
30
31using namespace llvm;
32
33namespace {
34
35class AMDGPUMCCodeEmitter : public MCCodeEmitter {
36 const MCRegisterInfo &MRI;
37 const MCInstrInfo &MCII;
38
39public:
40 AMDGPUMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI)
41 : MRI(MRI), MCII(MCII) {}
42
43 /// Encode the instruction and write it to the OS.
44 void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
45 SmallVectorImpl<MCFixup> &Fixups,
46 const MCSubtargetInfo &STI) const override;
47
48 void getMachineOpValue(const MCInst &MI, const MCOperand &MO, APInt &Op,
49 SmallVectorImpl<MCFixup> &Fixups,
50 const MCSubtargetInfo &STI) const;
51
52 void getMachineOpValueT16(const MCInst &MI, unsigned OpNo, APInt &Op,
53 SmallVectorImpl<MCFixup> &Fixups,
54 const MCSubtargetInfo &STI) const;
55
56 void getMachineOpValueT16Lo128(const MCInst &MI, unsigned OpNo, APInt &Op,
57 SmallVectorImpl<MCFixup> &Fixups,
58 const MCSubtargetInfo &STI) const;
59
60 /// Use a fixup to encode the simm16 field for SOPP branch
61 /// instructions.
62 void getSOPPBrEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
63 SmallVectorImpl<MCFixup> &Fixups,
64 const MCSubtargetInfo &STI) const;
65
66 void getSMEMOffsetEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
67 SmallVectorImpl<MCFixup> &Fixups,
68 const MCSubtargetInfo &STI) const;
69
70 void getSDWASrcEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
71 SmallVectorImpl<MCFixup> &Fixups,
72 const MCSubtargetInfo &STI) const;
73
74 void getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
75 SmallVectorImpl<MCFixup> &Fixups,
76 const MCSubtargetInfo &STI) const;
77
78 void getAVOperandEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
79 SmallVectorImpl<MCFixup> &Fixups,
80 const MCSubtargetInfo &STI) const;
81
82private:
83 uint64_t getImplicitOpSelHiEncoding(int Opcode) const;
84 void getMachineOpValueCommon(const MCInst &MI, const MCOperand &MO,
85 unsigned OpNo, APInt &Op,
86 SmallVectorImpl<MCFixup> &Fixups,
87 const MCSubtargetInfo &STI) const;
88
89 /// Encode an fp or int literal.
90 std::optional<uint32_t> getLitEncoding(const MCOperand &MO,
91 const MCOperandInfo &OpInfo,
92 const MCSubtargetInfo &STI) const;
93
94 void getBinaryCodeForInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
95 APInt &Inst, APInt &Scratch,
96 const MCSubtargetInfo &STI) const;
97};
98
99} // end anonymous namespace
100
101MCCodeEmitter *llvm::createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII,
102 MCContext &Ctx) {
103 return new AMDGPUMCCodeEmitter(MCII, *Ctx.getRegisterInfo());
104}
105
106// Returns the encoding value to use if the given integer is an integer inline
107// immediate value, or 0 if it is not.
108template <typename IntTy>
109static uint32_t getIntInlineImmEncoding(IntTy Imm) {
110 if (Imm >= 0 && Imm <= 64)
111 return 128 + Imm;
112
113 if (Imm >= -16 && Imm <= -1)
114 return 192 + std::abs(Imm);
115
116 return 0;
117}
118
119static uint32_t getLit16Encoding(uint16_t Val, const MCSubtargetInfo &STI) {
120 uint16_t IntImm = getIntInlineImmEncoding(Imm: static_cast<int16_t>(Val));
121 if (IntImm != 0)
122 return IntImm;
123
124 if (Val == 0x3800) // 0.5
125 return 240;
126
127 if (Val == 0xB800) // -0.5
128 return 241;
129
130 if (Val == 0x3C00) // 1.0
131 return 242;
132
133 if (Val == 0xBC00) // -1.0
134 return 243;
135
136 if (Val == 0x4000) // 2.0
137 return 244;
138
139 if (Val == 0xC000) // -2.0
140 return 245;
141
142 if (Val == 0x4400) // 4.0
143 return 246;
144
145 if (Val == 0xC400) // -4.0
146 return 247;
147
148 if (Val == 0x3118 && // 1.0 / (2.0 * pi)
149 STI.hasFeature(Feature: AMDGPU::FeatureInv2PiInlineImm))
150 return 248;
151
152 return 255;
153}
154
155static uint32_t getLitBF16Encoding(uint16_t Val) {
156 uint16_t IntImm = getIntInlineImmEncoding(Imm: static_cast<int16_t>(Val));
157 if (IntImm != 0)
158 return IntImm;
159
160 // clang-format off
161 switch (Val) {
162 case 0x3F00: return 240; // 0.5
163 case 0xBF00: return 241; // -0.5
164 case 0x3F80: return 242; // 1.0
165 case 0xBF80: return 243; // -1.0
166 case 0x4000: return 244; // 2.0
167 case 0xC000: return 245; // -2.0
168 case 0x4080: return 246; // 4.0
169 case 0xC080: return 247; // -4.0
170 case 0x3E22: return 248; // 1.0 / (2.0 * pi)
171 default: return 255;
172 }
173 // clang-format on
174}
175
176static uint32_t getLit32Encoding(uint32_t Val, const MCSubtargetInfo &STI) {
177 uint32_t IntImm = getIntInlineImmEncoding(Imm: static_cast<int32_t>(Val));
178 if (IntImm != 0)
179 return IntImm;
180
181 if (Val == llvm::bit_cast<uint32_t>(from: 0.5f))
182 return 240;
183
184 if (Val == llvm::bit_cast<uint32_t>(from: -0.5f))
185 return 241;
186
187 if (Val == llvm::bit_cast<uint32_t>(from: 1.0f))
188 return 242;
189
190 if (Val == llvm::bit_cast<uint32_t>(from: -1.0f))
191 return 243;
192
193 if (Val == llvm::bit_cast<uint32_t>(from: 2.0f))
194 return 244;
195
196 if (Val == llvm::bit_cast<uint32_t>(from: -2.0f))
197 return 245;
198
199 if (Val == llvm::bit_cast<uint32_t>(from: 4.0f))
200 return 246;
201
202 if (Val == llvm::bit_cast<uint32_t>(from: -4.0f))
203 return 247;
204
205 if (Val == 0x3e22f983 && // 1.0 / (2.0 * pi)
206 STI.hasFeature(Feature: AMDGPU::FeatureInv2PiInlineImm))
207 return 248;
208
209 return 255;
210}
211
212static uint32_t getLit16IntEncoding(uint32_t Val, const MCSubtargetInfo &STI) {
213 return getLit32Encoding(Val, STI);
214}
215
216static uint32_t getLit64Encoding(uint64_t Val, const MCSubtargetInfo &STI) {
217 uint32_t IntImm = getIntInlineImmEncoding(Imm: static_cast<int64_t>(Val));
218 if (IntImm != 0)
219 return IntImm;
220
221 if (Val == llvm::bit_cast<uint64_t>(from: 0.5))
222 return 240;
223
224 if (Val == llvm::bit_cast<uint64_t>(from: -0.5))
225 return 241;
226
227 if (Val == llvm::bit_cast<uint64_t>(from: 1.0))
228 return 242;
229
230 if (Val == llvm::bit_cast<uint64_t>(from: -1.0))
231 return 243;
232
233 if (Val == llvm::bit_cast<uint64_t>(from: 2.0))
234 return 244;
235
236 if (Val == llvm::bit_cast<uint64_t>(from: -2.0))
237 return 245;
238
239 if (Val == llvm::bit_cast<uint64_t>(from: 4.0))
240 return 246;
241
242 if (Val == llvm::bit_cast<uint64_t>(from: -4.0))
243 return 247;
244
245 if (Val == 0x3fc45f306dc9c882 && // 1.0 / (2.0 * pi)
246 STI.hasFeature(Feature: AMDGPU::FeatureInv2PiInlineImm))
247 return 248;
248
249 return 255;
250}
251
252std::optional<uint32_t>
253AMDGPUMCCodeEmitter::getLitEncoding(const MCOperand &MO,
254 const MCOperandInfo &OpInfo,
255 const MCSubtargetInfo &STI) const {
256 int64_t Imm;
257 if (MO.isExpr()) {
258 if (!MO.getExpr()->evaluateAsAbsolute(Res&: Imm))
259 return 255;
260 } else {
261 assert(!MO.isDFPImm());
262
263 if (!MO.isImm())
264 return {};
265
266 Imm = MO.getImm();
267 }
268
269 switch (OpInfo.OperandType) {
270 case AMDGPU::OPERAND_REG_IMM_INT32:
271 case AMDGPU::OPERAND_REG_IMM_FP32:
272 case AMDGPU::OPERAND_REG_INLINE_C_INT32:
273 case AMDGPU::OPERAND_REG_INLINE_C_FP32:
274 case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
275 case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
276 case AMDGPU::OPERAND_REG_IMM_V2INT32:
277 case AMDGPU::OPERAND_REG_IMM_V2FP32:
278 case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32:
279 return getLit32Encoding(Val: static_cast<uint32_t>(Imm), STI);
280
281 case AMDGPU::OPERAND_REG_IMM_INT64:
282 case AMDGPU::OPERAND_REG_IMM_FP64:
283 case AMDGPU::OPERAND_REG_INLINE_C_INT64:
284 case AMDGPU::OPERAND_REG_INLINE_C_FP64:
285 case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
286 return getLit64Encoding(Val: static_cast<uint64_t>(Imm), STI);
287
288 case AMDGPU::OPERAND_REG_IMM_INT16:
289 case AMDGPU::OPERAND_REG_INLINE_C_INT16:
290 return getLit16IntEncoding(Val: static_cast<uint32_t>(Imm), STI);
291
292 case AMDGPU::OPERAND_REG_IMM_FP16:
293 case AMDGPU::OPERAND_REG_INLINE_C_FP16:
294 // FIXME Is this correct? What do inline immediates do on SI for f16 src
295 // which does not have f16 support?
296 return getLit16Encoding(Val: static_cast<uint16_t>(Imm), STI);
297
298 case AMDGPU::OPERAND_REG_IMM_BF16:
299 case AMDGPU::OPERAND_REG_INLINE_C_BF16:
300 // We don't actually need to check Inv2Pi here because BF16 instructions can
301 // only be emitted for targets that already support the feature.
302 return getLitBF16Encoding(Val: static_cast<uint16_t>(Imm));
303
304 case AMDGPU::OPERAND_REG_IMM_V2INT16:
305 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
306 return AMDGPU::getInlineEncodingV2I16(Literal: static_cast<uint32_t>(Imm))
307 .value_or(u: 255);
308
309 case AMDGPU::OPERAND_REG_IMM_V2FP16:
310 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
311 return AMDGPU::getInlineEncodingV2F16(Literal: static_cast<uint32_t>(Imm))
312 .value_or(u: 255);
313
314 case AMDGPU::OPERAND_REG_IMM_V2BF16:
315 case AMDGPU::OPERAND_REG_INLINE_C_V2BF16:
316 return AMDGPU::getInlineEncodingV2BF16(Literal: static_cast<uint32_t>(Imm))
317 .value_or(u: 255);
318
319 case AMDGPU::OPERAND_KIMM32:
320 case AMDGPU::OPERAND_KIMM16:
321 return MO.getImm();
322 default:
323 llvm_unreachable("invalid operand size");
324 }
325}
326
327uint64_t AMDGPUMCCodeEmitter::getImplicitOpSelHiEncoding(int Opcode) const {
328 using namespace AMDGPU::VOP3PEncoding;
329
330 if (AMDGPU::hasNamedOperand(Opcode, NamedIdx: AMDGPU::OpName::op_sel_hi)) {
331 if (AMDGPU::hasNamedOperand(Opcode, NamedIdx: AMDGPU::OpName::src2))
332 return 0;
333 if (AMDGPU::hasNamedOperand(Opcode, NamedIdx: AMDGPU::OpName::src1))
334 return OP_SEL_HI_2;
335 if (AMDGPU::hasNamedOperand(Opcode, NamedIdx: AMDGPU::OpName::src0))
336 return OP_SEL_HI_1 | OP_SEL_HI_2;
337 }
338 return OP_SEL_HI_0 | OP_SEL_HI_1 | OP_SEL_HI_2;
339}
340
341static bool isVCMPX64(const MCInstrDesc &Desc) {
342 return (Desc.TSFlags & SIInstrFlags::VOP3) &&
343 Desc.hasImplicitDefOfPhysReg(Reg: AMDGPU::EXEC);
344}
345
346void AMDGPUMCCodeEmitter::encodeInstruction(const MCInst &MI,
347 SmallVectorImpl<char> &CB,
348 SmallVectorImpl<MCFixup> &Fixups,
349 const MCSubtargetInfo &STI) const {
350 int Opcode = MI.getOpcode();
351 APInt Encoding, Scratch;
352 getBinaryCodeForInstr(MI, Fixups, Inst&: Encoding, Scratch, STI);
353 const MCInstrDesc &Desc = MCII.get(Opcode: MI.getOpcode());
354 unsigned bytes = Desc.getSize();
355
356 // Set unused op_sel_hi bits to 1 for VOP3P and MAI instructions.
357 // Note that accvgpr_read/write are MAI, have src0, but do not use op_sel.
358 if ((Desc.TSFlags & SIInstrFlags::VOP3P) ||
359 Opcode == AMDGPU::V_ACCVGPR_READ_B32_vi ||
360 Opcode == AMDGPU::V_ACCVGPR_WRITE_B32_vi) {
361 Encoding |= getImplicitOpSelHiEncoding(Opcode);
362 }
363
364 // GFX10+ v_cmpx opcodes promoted to VOP3 have implied dst=EXEC.
365 // Documentation requires dst to be encoded as EXEC (0x7E),
366 // but it looks like the actual value encoded for dst operand
367 // is ignored by HW. It was decided to define dst as "do not care"
368 // in td files to allow disassembler accept any dst value.
369 // However, dst is encoded as EXEC for compatibility with SP3.
370 if (AMDGPU::isGFX10Plus(STI) && isVCMPX64(Desc)) {
371 assert((Encoding & 0xFF) == 0);
372 Encoding |= MRI.getEncodingValue(Reg: AMDGPU::EXEC_LO) &
373 AMDGPU::HWEncoding::REG_IDX_MASK;
374 }
375
376 for (unsigned i = 0; i < bytes; i++) {
377 CB.push_back(Elt: (uint8_t)Encoding.extractBitsAsZExtValue(numBits: 8, bitPosition: 8 * i));
378 }
379
380 // NSA encoding.
381 if (AMDGPU::isGFX10Plus(STI) && Desc.TSFlags & SIInstrFlags::MIMG) {
382 int vaddr0 = AMDGPU::getNamedOperandIdx(Opcode: MI.getOpcode(),
383 Name: AMDGPU::OpName::vaddr0);
384 int srsrc = AMDGPU::getNamedOperandIdx(Opcode: MI.getOpcode(),
385 Name: AMDGPU::OpName::srsrc);
386 assert(vaddr0 >= 0 && srsrc > vaddr0);
387 unsigned NumExtraAddrs = srsrc - vaddr0 - 1;
388 unsigned NumPadding = (-NumExtraAddrs) & 3;
389
390 for (unsigned i = 0; i < NumExtraAddrs; ++i) {
391 getMachineOpValue(MI, MO: MI.getOperand(i: vaddr0 + 1 + i), Op&: Encoding, Fixups,
392 STI);
393 CB.push_back(Elt: (uint8_t)Encoding.getLimitedValue());
394 }
395 CB.append(NumInputs: NumPadding, Elt: 0);
396 }
397
398 if ((bytes > 8 && STI.hasFeature(Feature: AMDGPU::FeatureVOP3Literal)) ||
399 (bytes > 4 && !STI.hasFeature(Feature: AMDGPU::FeatureVOP3Literal)))
400 return;
401
402 // Do not print literals from SISrc Operands for insts with mandatory literals
403 if (AMDGPU::hasNamedOperand(Opcode: MI.getOpcode(), NamedIdx: AMDGPU::OpName::imm))
404 return;
405
406 // Check for additional literals
407 for (unsigned i = 0, e = Desc.getNumOperands(); i < e; ++i) {
408
409 // Check if this operand should be encoded as [SV]Src
410 if (!AMDGPU::isSISrcOperand(Desc, OpNo: i))
411 continue;
412
413 // Is this operand a literal immediate?
414 const MCOperand &Op = MI.getOperand(i);
415 auto Enc = getLitEncoding(MO: Op, OpInfo: Desc.operands()[i], STI);
416 if (!Enc || *Enc != 255)
417 continue;
418
419 // Yes! Encode it
420 int64_t Imm = 0;
421
422 if (Op.isImm())
423 Imm = Op.getImm();
424 else if (Op.isExpr()) {
425 if (const auto *C = dyn_cast<MCConstantExpr>(Val: Op.getExpr()))
426 Imm = C->getValue();
427 } else // Exprs will be replaced with a fixup value.
428 llvm_unreachable("Must be immediate or expr");
429
430 if (Desc.operands()[i].OperandType == AMDGPU::OPERAND_REG_IMM_FP64)
431 Imm = Hi_32(Value: Imm);
432
433 support::endian::write<uint32_t>(Out&: CB, V: Imm, E: llvm::endianness::little);
434
435 // Only one literal value allowed
436 break;
437 }
438}
439
440void AMDGPUMCCodeEmitter::getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
441 APInt &Op,
442 SmallVectorImpl<MCFixup> &Fixups,
443 const MCSubtargetInfo &STI) const {
444 const MCOperand &MO = MI.getOperand(i: OpNo);
445
446 if (MO.isExpr()) {
447 const MCExpr *Expr = MO.getExpr();
448 MCFixupKind Kind = (MCFixupKind)AMDGPU::fixup_si_sopp_br;
449 Fixups.push_back(Elt: MCFixup::create(Offset: 0, Value: Expr, Kind, Loc: MI.getLoc()));
450 Op = APInt::getZero(numBits: 96);
451 } else {
452 getMachineOpValue(MI, MO, Op, Fixups, STI);
453 }
454}
455
456void AMDGPUMCCodeEmitter::getSMEMOffsetEncoding(
457 const MCInst &MI, unsigned OpNo, APInt &Op,
458 SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
459 auto Offset = MI.getOperand(i: OpNo).getImm();
460 // VI only supports 20-bit unsigned offsets.
461 assert(!AMDGPU::isVI(STI) || isUInt<20>(Offset));
462 Op = Offset;
463}
464
465void AMDGPUMCCodeEmitter::getSDWASrcEncoding(const MCInst &MI, unsigned OpNo,
466 APInt &Op,
467 SmallVectorImpl<MCFixup> &Fixups,
468 const MCSubtargetInfo &STI) const {
469 using namespace AMDGPU::SDWA;
470
471 uint64_t RegEnc = 0;
472
473 const MCOperand &MO = MI.getOperand(i: OpNo);
474
475 if (MO.isReg()) {
476 MCRegister Reg = MO.getReg();
477 RegEnc |= MRI.getEncodingValue(Reg);
478 RegEnc &= SDWA9EncValues::SRC_VGPR_MASK;
479 if (AMDGPU::isSGPR(Reg: AMDGPU::mc2PseudoReg(Reg), TRI: &MRI)) {
480 RegEnc |= SDWA9EncValues::SRC_SGPR_MASK;
481 }
482 Op = RegEnc;
483 return;
484 } else {
485 const MCInstrDesc &Desc = MCII.get(Opcode: MI.getOpcode());
486 auto Enc = getLitEncoding(MO, OpInfo: Desc.operands()[OpNo], STI);
487 if (Enc && *Enc != 255) {
488 Op = *Enc | SDWA9EncValues::SRC_SGPR_MASK;
489 return;
490 }
491 }
492
493 llvm_unreachable("Unsupported operand kind");
494}
495
496void AMDGPUMCCodeEmitter::getSDWAVopcDstEncoding(
497 const MCInst &MI, unsigned OpNo, APInt &Op,
498 SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
499 using namespace AMDGPU::SDWA;
500
501 uint64_t RegEnc = 0;
502
503 const MCOperand &MO = MI.getOperand(i: OpNo);
504
505 MCRegister Reg = MO.getReg();
506 if (Reg != AMDGPU::VCC && Reg != AMDGPU::VCC_LO) {
507 RegEnc |= MRI.getEncodingValue(Reg);
508 RegEnc &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
509 RegEnc |= SDWA9EncValues::VOPC_DST_VCC_MASK;
510 }
511 Op = RegEnc;
512}
513
514void AMDGPUMCCodeEmitter::getAVOperandEncoding(
515 const MCInst &MI, unsigned OpNo, APInt &Op,
516 SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
517 MCRegister Reg = MI.getOperand(i: OpNo).getReg();
518 unsigned Enc = MRI.getEncodingValue(Reg);
519 unsigned Idx = Enc & AMDGPU::HWEncoding::REG_IDX_MASK;
520 bool IsVGPROrAGPR =
521 Enc & (AMDGPU::HWEncoding::IS_VGPR | AMDGPU::HWEncoding::IS_AGPR);
522
523 // VGPR and AGPR have the same encoding, but SrcA and SrcB operands of mfma
524 // instructions use acc[0:1] modifier bits to distinguish. These bits are
525 // encoded as a virtual 9th bit of the register for these operands.
526 bool IsAGPR = Enc & AMDGPU::HWEncoding::IS_AGPR;
527
528 Op = Idx | (IsVGPROrAGPR << 8) | (IsAGPR << 9);
529}
530
531static bool needsPCRel(const MCExpr *Expr) {
532 switch (Expr->getKind()) {
533 case MCExpr::SymbolRef: {
534 auto *SE = cast<MCSymbolRefExpr>(Val: Expr);
535 auto Spec = AMDGPU::getSpecifier(SRE: SE);
536 return Spec != AMDGPUMCExpr::S_ABS32_LO && Spec != AMDGPUMCExpr::S_ABS32_HI;
537 }
538 case MCExpr::Binary: {
539 auto *BE = cast<MCBinaryExpr>(Val: Expr);
540 if (BE->getOpcode() == MCBinaryExpr::Sub)
541 return false;
542 return needsPCRel(Expr: BE->getLHS()) || needsPCRel(Expr: BE->getRHS());
543 }
544 case MCExpr::Unary:
545 return needsPCRel(Expr: cast<MCUnaryExpr>(Val: Expr)->getSubExpr());
546 case MCExpr::Specifier:
547 case MCExpr::Target:
548 case MCExpr::Constant:
549 return false;
550 }
551 llvm_unreachable("invalid kind");
552}
553
554void AMDGPUMCCodeEmitter::getMachineOpValue(const MCInst &MI,
555 const MCOperand &MO, APInt &Op,
556 SmallVectorImpl<MCFixup> &Fixups,
557 const MCSubtargetInfo &STI) const {
558 if (MO.isReg()){
559 unsigned Enc = MRI.getEncodingValue(Reg: MO.getReg());
560 unsigned Idx = Enc & AMDGPU::HWEncoding::REG_IDX_MASK;
561 bool IsVGPROrAGPR =
562 Enc & (AMDGPU::HWEncoding::IS_VGPR | AMDGPU::HWEncoding::IS_AGPR);
563 Op = Idx | (IsVGPROrAGPR << 8);
564 return;
565 }
566 unsigned OpNo = &MO - MI.begin();
567 getMachineOpValueCommon(MI, MO, OpNo, Op, Fixups, STI);
568}
569
570void AMDGPUMCCodeEmitter::getMachineOpValueT16(
571 const MCInst &MI, unsigned OpNo, APInt &Op,
572 SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
573 const MCOperand &MO = MI.getOperand(i: OpNo);
574 if (MO.isReg()) {
575 unsigned Enc = MRI.getEncodingValue(Reg: MO.getReg());
576 unsigned Idx = Enc & AMDGPU::HWEncoding::REG_IDX_MASK;
577 bool IsVGPR = Enc & AMDGPU::HWEncoding::IS_VGPR;
578 Op = Idx | (IsVGPR << 8);
579 return;
580 }
581 getMachineOpValueCommon(MI, MO, OpNo, Op, Fixups, STI);
582 // VGPRs include the suffix/op_sel bit in the register encoding, but
583 // immediates and SGPRs include it in src_modifiers. Therefore, copy the
584 // op_sel bit from the src operands into src_modifier operands if Op is
585 // src_modifiers and the corresponding src is a VGPR
586 int SrcMOIdx = -1;
587 assert(OpNo < INT_MAX);
588 if ((int)OpNo == AMDGPU::getNamedOperandIdx(Opcode: MI.getOpcode(),
589 Name: AMDGPU::OpName::src0_modifiers)) {
590 SrcMOIdx = AMDGPU::getNamedOperandIdx(Opcode: MI.getOpcode(), Name: AMDGPU::OpName::src0);
591 int VDstMOIdx =
592 AMDGPU::getNamedOperandIdx(Opcode: MI.getOpcode(), Name: AMDGPU::OpName::vdst);
593 if (VDstMOIdx != -1) {
594 auto DstReg = MI.getOperand(i: VDstMOIdx).getReg();
595 if (AMDGPU::isHi16Reg(Reg: DstReg, MRI))
596 Op |= SISrcMods::DST_OP_SEL;
597 }
598 } else if ((int)OpNo == AMDGPU::getNamedOperandIdx(
599 Opcode: MI.getOpcode(), Name: AMDGPU::OpName::src1_modifiers))
600 SrcMOIdx = AMDGPU::getNamedOperandIdx(Opcode: MI.getOpcode(), Name: AMDGPU::OpName::src1);
601 else if ((int)OpNo == AMDGPU::getNamedOperandIdx(
602 Opcode: MI.getOpcode(), Name: AMDGPU::OpName::src2_modifiers))
603 SrcMOIdx = AMDGPU::getNamedOperandIdx(Opcode: MI.getOpcode(), Name: AMDGPU::OpName::src2);
604 if (SrcMOIdx == -1)
605 return;
606
607 const MCOperand &SrcMO = MI.getOperand(i: SrcMOIdx);
608 if (!SrcMO.isReg())
609 return;
610 auto SrcReg = SrcMO.getReg();
611 if (AMDGPU::isSGPR(Reg: SrcReg, TRI: &MRI))
612 return;
613 if (AMDGPU::isHi16Reg(Reg: SrcReg, MRI))
614 Op |= SISrcMods::OP_SEL_0;
615}
616
617void AMDGPUMCCodeEmitter::getMachineOpValueT16Lo128(
618 const MCInst &MI, unsigned OpNo, APInt &Op,
619 SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
620 const MCOperand &MO = MI.getOperand(i: OpNo);
621 if (MO.isReg()) {
622 uint16_t Encoding = MRI.getEncodingValue(Reg: MO.getReg());
623 unsigned RegIdx = Encoding & AMDGPU::HWEncoding::REG_IDX_MASK;
624 bool IsHi = Encoding & AMDGPU::HWEncoding::IS_HI16;
625 bool IsVGPR = Encoding & AMDGPU::HWEncoding::IS_VGPR;
626 assert((!IsVGPR || isUInt<7>(RegIdx)) && "VGPR0-VGPR127 expected!");
627 Op = (IsVGPR ? 0x100 : 0) | (IsHi ? 0x80 : 0) | RegIdx;
628 return;
629 }
630 getMachineOpValueCommon(MI, MO, OpNo, Op, Fixups, STI);
631}
632
633void AMDGPUMCCodeEmitter::getMachineOpValueCommon(
634 const MCInst &MI, const MCOperand &MO, unsigned OpNo, APInt &Op,
635 SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
636 bool isLikeImm = false;
637 int64_t Val;
638
639 if (MO.isImm()) {
640 Val = MO.getImm();
641 isLikeImm = true;
642 } else if (MO.isExpr() && MO.getExpr()->evaluateAsAbsolute(Res&: Val)) {
643 isLikeImm = true;
644 } else if (MO.isExpr()) {
645 // FIXME: If this is expression is PCRel or not should not depend on what
646 // the expression looks like. Given that this is just a general expression,
647 // it should probably be FK_Data_4 and whatever is producing
648 //
649 // s_add_u32 s2, s2, (extern_const_addrspace+16
650 //
651 // And expecting a PCRel should instead produce
652 //
653 // .Ltmp1:
654 // s_add_u32 s2, s2, (extern_const_addrspace+16)-.Ltmp1
655 MCFixupKind Kind;
656 if (needsPCRel(Expr: MO.getExpr()))
657 Kind = FK_PCRel_4;
658 else
659 Kind = FK_Data_4;
660
661 const MCInstrDesc &Desc = MCII.get(Opcode: MI.getOpcode());
662 uint32_t Offset = Desc.getSize();
663 assert(Offset == 4 || Offset == 8);
664
665 Fixups.push_back(Elt: MCFixup::create(Offset, Value: MO.getExpr(), Kind, Loc: MI.getLoc()));
666 }
667
668 const MCInstrDesc &Desc = MCII.get(Opcode: MI.getOpcode());
669 if (AMDGPU::isSISrcOperand(Desc, OpNo)) {
670 if (auto Enc = getLitEncoding(MO, OpInfo: Desc.operands()[OpNo], STI)) {
671 Op = *Enc;
672 return;
673 }
674
675 llvm_unreachable("Operand not supported for SISrc");
676 }
677
678 if (isLikeImm) {
679 Op = Val;
680 return;
681 }
682
683 llvm_unreachable("Encoding of this operand type is not supported yet.");
684}
685
686#include "AMDGPUGenMCCodeEmitter.inc"
687