1//===-- MipsMCTargetDesc.cpp - Mips Target Descriptions -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides Mips specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MipsMCTargetDesc.h"
14#include "MipsAsmBackend.h"
15#include "MipsBaseInfo.h"
16#include "MipsELFStreamer.h"
17#include "MipsInstPrinter.h"
18#include "MipsMCAsmInfo.h"
19#include "MipsMCNaCl.h"
20#include "MipsTargetStreamer.h"
21#include "TargetInfo/MipsTargetInfo.h"
22#include "llvm/DebugInfo/CodeView/CodeView.h"
23#include "llvm/MC/MCCodeEmitter.h"
24#include "llvm/MC/MCELFStreamer.h"
25#include "llvm/MC/MCInstrAnalysis.h"
26#include "llvm/MC/MCInstrInfo.h"
27#include "llvm/MC/MCObjectWriter.h"
28#include "llvm/MC/MCRegisterInfo.h"
29#include "llvm/MC/MCSubtargetInfo.h"
30#include "llvm/MC/MCSymbol.h"
31#include "llvm/MC/TargetRegistry.h"
32#include "llvm/Support/Compiler.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/FormattedStream.h"
35#include "llvm/TargetParser/Triple.h"
36
37using namespace llvm;
38
39#define GET_INSTRINFO_MC_DESC
40#define ENABLE_INSTR_PREDICATE_VERIFIER
41#include "MipsGenInstrInfo.inc"
42
43#define GET_SUBTARGETINFO_MC_DESC
44#include "MipsGenSubtargetInfo.inc"
45
46#define GET_REGINFO_MC_DESC
47#include "MipsGenRegisterInfo.inc"
48
49void MIPS_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
50 // Mapping from CodeView to MC register id.
51 static const struct {
52 codeview::RegisterId CVReg;
53 MCPhysReg Reg;
54 } RegMap[] = {
55 {.CVReg: codeview::RegisterId::MIPS_ZERO, .Reg: Mips::ZERO},
56 {.CVReg: codeview::RegisterId::MIPS_AT, .Reg: Mips::AT},
57 {.CVReg: codeview::RegisterId::MIPS_V0, .Reg: Mips::V0},
58 {.CVReg: codeview::RegisterId::MIPS_V1, .Reg: Mips::V1},
59 {.CVReg: codeview::RegisterId::MIPS_A0, .Reg: Mips::A0},
60 {.CVReg: codeview::RegisterId::MIPS_A1, .Reg: Mips::A1},
61 {.CVReg: codeview::RegisterId::MIPS_A2, .Reg: Mips::A2},
62 {.CVReg: codeview::RegisterId::MIPS_A3, .Reg: Mips::A3},
63 {.CVReg: codeview::RegisterId::MIPS_T0, .Reg: Mips::T0},
64 {.CVReg: codeview::RegisterId::MIPS_T1, .Reg: Mips::T1},
65 {.CVReg: codeview::RegisterId::MIPS_T2, .Reg: Mips::T2},
66 {.CVReg: codeview::RegisterId::MIPS_T3, .Reg: Mips::T3},
67 {.CVReg: codeview::RegisterId::MIPS_T4, .Reg: Mips::T4},
68 {.CVReg: codeview::RegisterId::MIPS_T5, .Reg: Mips::T5},
69 {.CVReg: codeview::RegisterId::MIPS_T6, .Reg: Mips::T6},
70 {.CVReg: codeview::RegisterId::MIPS_T7, .Reg: Mips::T7},
71 {.CVReg: codeview::RegisterId::MIPS_S0, .Reg: Mips::S0},
72 {.CVReg: codeview::RegisterId::MIPS_S1, .Reg: Mips::S1},
73 {.CVReg: codeview::RegisterId::MIPS_S2, .Reg: Mips::S2},
74 {.CVReg: codeview::RegisterId::MIPS_S3, .Reg: Mips::S3},
75 {.CVReg: codeview::RegisterId::MIPS_S4, .Reg: Mips::S4},
76 {.CVReg: codeview::RegisterId::MIPS_S5, .Reg: Mips::S5},
77 {.CVReg: codeview::RegisterId::MIPS_S6, .Reg: Mips::S6},
78 {.CVReg: codeview::RegisterId::MIPS_S7, .Reg: Mips::S7},
79 {.CVReg: codeview::RegisterId::MIPS_T8, .Reg: Mips::T8},
80 {.CVReg: codeview::RegisterId::MIPS_T9, .Reg: Mips::T9},
81 {.CVReg: codeview::RegisterId::MIPS_K0, .Reg: Mips::K0},
82 {.CVReg: codeview::RegisterId::MIPS_K1, .Reg: Mips::K1},
83 {.CVReg: codeview::RegisterId::MIPS_GP, .Reg: Mips::GP},
84 {.CVReg: codeview::RegisterId::MIPS_SP, .Reg: Mips::SP},
85 {.CVReg: codeview::RegisterId::MIPS_S8, .Reg: Mips::FP},
86 {.CVReg: codeview::RegisterId::MIPS_RA, .Reg: Mips::RA},
87 {.CVReg: codeview::RegisterId::MIPS_LO, .Reg: Mips::HI0},
88 {.CVReg: codeview::RegisterId::MIPS_HI, .Reg: Mips::LO0},
89 {.CVReg: codeview::RegisterId::MIPS_Fir, .Reg: Mips::FCR0},
90 {.CVReg: codeview::RegisterId::MIPS_Psr, .Reg: Mips::COP012}, // CP0.Status
91 {.CVReg: codeview::RegisterId::MIPS_F0, .Reg: Mips::F0},
92 {.CVReg: codeview::RegisterId::MIPS_F1, .Reg: Mips::F1},
93 {.CVReg: codeview::RegisterId::MIPS_F2, .Reg: Mips::F2},
94 {.CVReg: codeview::RegisterId::MIPS_F3, .Reg: Mips::F3},
95 {.CVReg: codeview::RegisterId::MIPS_F4, .Reg: Mips::F4},
96 {.CVReg: codeview::RegisterId::MIPS_F5, .Reg: Mips::F5},
97 {.CVReg: codeview::RegisterId::MIPS_F6, .Reg: Mips::F6},
98 {.CVReg: codeview::RegisterId::MIPS_F7, .Reg: Mips::F7},
99 {.CVReg: codeview::RegisterId::MIPS_F8, .Reg: Mips::F8},
100 {.CVReg: codeview::RegisterId::MIPS_F9, .Reg: Mips::F9},
101 {.CVReg: codeview::RegisterId::MIPS_F10, .Reg: Mips::F10},
102 {.CVReg: codeview::RegisterId::MIPS_F11, .Reg: Mips::F11},
103 {.CVReg: codeview::RegisterId::MIPS_F12, .Reg: Mips::F12},
104 {.CVReg: codeview::RegisterId::MIPS_F13, .Reg: Mips::F13},
105 {.CVReg: codeview::RegisterId::MIPS_F14, .Reg: Mips::F14},
106 {.CVReg: codeview::RegisterId::MIPS_F15, .Reg: Mips::F15},
107 {.CVReg: codeview::RegisterId::MIPS_F16, .Reg: Mips::F16},
108 {.CVReg: codeview::RegisterId::MIPS_F17, .Reg: Mips::F17},
109 {.CVReg: codeview::RegisterId::MIPS_F18, .Reg: Mips::F18},
110 {.CVReg: codeview::RegisterId::MIPS_F19, .Reg: Mips::F19},
111 {.CVReg: codeview::RegisterId::MIPS_F20, .Reg: Mips::F20},
112 {.CVReg: codeview::RegisterId::MIPS_F21, .Reg: Mips::F21},
113 {.CVReg: codeview::RegisterId::MIPS_F22, .Reg: Mips::F22},
114 {.CVReg: codeview::RegisterId::MIPS_F23, .Reg: Mips::F23},
115 {.CVReg: codeview::RegisterId::MIPS_F24, .Reg: Mips::F24},
116 {.CVReg: codeview::RegisterId::MIPS_F25, .Reg: Mips::F25},
117 {.CVReg: codeview::RegisterId::MIPS_F26, .Reg: Mips::F26},
118 {.CVReg: codeview::RegisterId::MIPS_F27, .Reg: Mips::F27},
119 {.CVReg: codeview::RegisterId::MIPS_F28, .Reg: Mips::F28},
120 {.CVReg: codeview::RegisterId::MIPS_F29, .Reg: Mips::F29},
121 {.CVReg: codeview::RegisterId::MIPS_F30, .Reg: Mips::F30},
122 {.CVReg: codeview::RegisterId::MIPS_F31, .Reg: Mips::F31},
123 {.CVReg: codeview::RegisterId::MIPS_Fsr, .Reg: Mips::FCR31},
124 };
125 for (const auto &I : RegMap)
126 MRI->mapLLVMRegToCVReg(LLVMReg: I.Reg, CVReg: static_cast<int>(I.CVReg));
127}
128
129namespace {
130class MipsWinCOFFTargetStreamer : public MipsTargetStreamer {
131public:
132 MipsWinCOFFTargetStreamer(MCStreamer &S) : MipsTargetStreamer(S) {}
133};
134} // end namespace
135
136/// Select the Mips CPU for the given triple and cpu name.
137StringRef MIPS_MC::selectMipsCPU(const Triple &TT, StringRef CPU) {
138 if (CPU.empty() || CPU == "generic") {
139 if (TT.getSubArch() == llvm::Triple::MipsSubArch_r6) {
140 if (TT.isMIPS32())
141 CPU = "mips32r6";
142 else
143 CPU = "mips64r6";
144 } else {
145 if (TT.isMIPS32())
146 CPU = "mips32";
147 else
148 CPU = "mips64";
149 }
150 }
151 return CPU;
152}
153
154static MCInstrInfo *createMipsMCInstrInfo() {
155 MCInstrInfo *X = new MCInstrInfo();
156 InitMipsMCInstrInfo(II: X);
157 return X;
158}
159
160static MCRegisterInfo *createMipsMCRegisterInfo(const Triple &TT) {
161 MCRegisterInfo *X = new MCRegisterInfo();
162 InitMipsMCRegisterInfo(RI: X, RA: Mips::RA);
163 return X;
164}
165
166static MCSubtargetInfo *createMipsMCSubtargetInfo(const Triple &TT,
167 StringRef CPU, StringRef FS) {
168 CPU = MIPS_MC::selectMipsCPU(TT, CPU);
169 return createMipsMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
170}
171
172static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI,
173 const Triple &TT,
174 const MCTargetOptions &Options) {
175 MCAsmInfo *MAI;
176
177 if (TT.isOSWindows())
178 MAI = new MipsCOFFMCAsmInfo();
179 else
180 MAI = new MipsELFMCAsmInfo(TT, Options);
181
182 unsigned SP = MRI.getDwarfRegNum(RegNum: Mips::SP, isEH: true);
183 MCCFIInstruction Inst = MCCFIInstruction::createDefCfaRegister(L: nullptr, Register: SP);
184 MAI->addInitialFrameState(Inst);
185
186 return MAI;
187}
188
189static MCInstPrinter *createMipsMCInstPrinter(const Triple &T,
190 unsigned SyntaxVariant,
191 const MCAsmInfo &MAI,
192 const MCInstrInfo &MII,
193 const MCRegisterInfo &MRI) {
194 return new MipsInstPrinter(MAI, MII, MRI);
195}
196
197static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
198 std::unique_ptr<MCAsmBackend> &&MAB,
199 std::unique_ptr<MCObjectWriter> &&OW,
200 std::unique_ptr<MCCodeEmitter> &&Emitter) {
201 MCStreamer *S;
202 if (!T.isOSNaCl())
203 S = createMipsELFStreamer(Context, MAB: std::move(MAB), OW: std::move(OW),
204 Emitter: std::move(Emitter));
205 else
206 S = createMipsNaClELFStreamer(Context, TAB: std::move(MAB), OW: std::move(OW),
207 Emitter: std::move(Emitter));
208 return S;
209}
210
211static MCTargetStreamer *createMipsAsmTargetStreamer(MCStreamer &S,
212 formatted_raw_ostream &OS,
213 MCInstPrinter *InstPrint) {
214 return new MipsTargetAsmStreamer(S, OS);
215}
216
217static MCTargetStreamer *createMipsNullTargetStreamer(MCStreamer &S) {
218 return new MipsTargetStreamer(S);
219}
220
221static MCTargetStreamer *
222createMipsObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
223 if (STI.getTargetTriple().isOSBinFormatCOFF())
224 return new MipsWinCOFFTargetStreamer(S);
225 return new MipsTargetELFStreamer(S, STI);
226}
227
228namespace {
229
230class MipsMCInstrAnalysis : public MCInstrAnalysis {
231public:
232 MipsMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
233
234 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
235 uint64_t &Target) const override {
236 unsigned NumOps = Inst.getNumOperands();
237 if (NumOps == 0)
238 return false;
239 switch (Info->get(Opcode: Inst.getOpcode()).operands()[NumOps - 1].OperandType) {
240 case MCOI::OPERAND_UNKNOWN:
241 case MCOI::OPERAND_IMMEDIATE: {
242 // j, jal, jalx, jals
243 // Absolute branch within the current 256 MB-aligned region
244 uint64_t Region = Addr & ~uint64_t(0xfffffff);
245 Target = Region + Inst.getOperand(i: NumOps - 1).getImm();
246 return true;
247 }
248 case MCOI::OPERAND_PCREL:
249 // b, beq ...
250 Target = Addr + Inst.getOperand(i: NumOps - 1).getImm();
251 return true;
252 default:
253 return false;
254 }
255 }
256};
257}
258
259static MCInstrAnalysis *createMipsMCInstrAnalysis(const MCInstrInfo *Info) {
260 return new MipsMCInstrAnalysis(Info);
261}
262
263extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTargetMC() {
264 for (Target *T : {&getTheMipsTarget(), &getTheMipselTarget(),
265 &getTheMips64Target(), &getTheMips64elTarget()}) {
266 // Register the MC asm info.
267 RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo);
268
269 // Register the MC instruction info.
270 TargetRegistry::RegisterMCInstrInfo(T&: *T, Fn: createMipsMCInstrInfo);
271
272 // Register the MC register info.
273 TargetRegistry::RegisterMCRegInfo(T&: *T, Fn: createMipsMCRegisterInfo);
274
275 // Register the elf streamer.
276 TargetRegistry::RegisterELFStreamer(T&: *T, Fn: createMCStreamer);
277
278 // Register the asm target streamer.
279 TargetRegistry::RegisterAsmTargetStreamer(T&: *T, Fn: createMipsAsmTargetStreamer);
280
281 TargetRegistry::RegisterNullTargetStreamer(T&: *T,
282 Fn: createMipsNullTargetStreamer);
283
284 TargetRegistry::RegisterCOFFStreamer(T&: *T, Fn: createMipsWinCOFFStreamer);
285
286 // Register the MC subtarget info.
287 TargetRegistry::RegisterMCSubtargetInfo(T&: *T, Fn: createMipsMCSubtargetInfo);
288
289 // Register the MC instruction analyzer.
290 TargetRegistry::RegisterMCInstrAnalysis(T&: *T, Fn: createMipsMCInstrAnalysis);
291
292 // Register the MCInstPrinter.
293 TargetRegistry::RegisterMCInstPrinter(T&: *T, Fn: createMipsMCInstPrinter);
294
295 TargetRegistry::RegisterObjectTargetStreamer(
296 T&: *T, Fn: createMipsObjectTargetStreamer);
297
298 // Register the asm backend.
299 TargetRegistry::RegisterMCAsmBackend(T&: *T, Fn: createMipsAsmBackend);
300 }
301
302 // Register the MC Code Emitter
303 for (Target *T : {&getTheMipsTarget(), &getTheMips64Target()})
304 TargetRegistry::RegisterMCCodeEmitter(T&: *T, Fn: createMipsMCCodeEmitterEB);
305
306 for (Target *T : {&getTheMipselTarget(), &getTheMips64elTarget()})
307 TargetRegistry::RegisterMCCodeEmitter(T&: *T, Fn: createMipsMCCodeEmitterEL);
308}
309