1//===- NVPTXInstrInfo.cpp - NVPTX Instruction Information -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the NVPTX implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "NVPTXInstrInfo.h"
14#include "NVPTX.h"
15#include "llvm/CodeGen/MachineFunction.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
17#include "llvm/CodeGen/MachineRegisterInfo.h"
18
19using namespace llvm;
20
21#define GET_INSTRINFO_CTOR_DTOR
22#include "NVPTXGenInstrInfo.inc"
23
24// Pin the vtable to this file.
25void NVPTXInstrInfo::anchor() {}
26
27NVPTXInstrInfo::NVPTXInstrInfo() : RegInfo() {}
28
29void NVPTXInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
30 MachineBasicBlock::iterator I,
31 const DebugLoc &DL, Register DestReg,
32 Register SrcReg, bool KillSrc,
33 bool RenamableDest, bool RenamableSrc) const {
34 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
35 const TargetRegisterClass *DestRC = MRI.getRegClass(Reg: DestReg);
36 const TargetRegisterClass *SrcRC = MRI.getRegClass(Reg: SrcReg);
37
38 if (RegInfo.getRegSizeInBits(RC: *DestRC) != RegInfo.getRegSizeInBits(RC: *SrcRC))
39 report_fatal_error(reason: "Copy one register into another with a different width");
40
41 unsigned Op;
42 if (DestRC == &NVPTX::B1RegClass) {
43 Op = NVPTX::IMOV1r;
44 } else if (DestRC == &NVPTX::B16RegClass) {
45 Op = NVPTX::MOV16r;
46 } else if (DestRC == &NVPTX::B32RegClass) {
47 Op = NVPTX::IMOV32r;
48 } else if (DestRC == &NVPTX::B64RegClass) {
49 Op = NVPTX::IMOV64r;
50 } else if (DestRC == &NVPTX::B128RegClass) {
51 Op = NVPTX::IMOV128r;
52 } else {
53 llvm_unreachable("Bad register copy");
54 }
55 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Op), DestReg)
56 .addReg(RegNo: SrcReg, flags: getKillRegState(B: KillSrc));
57}
58
59/// analyzeBranch - Analyze the branching code at the end of MBB, returning
60/// true if it cannot be understood (e.g. it's a switch dispatch or isn't
61/// implemented for a target). Upon success, this returns false and returns
62/// with the following information in various cases:
63///
64/// 1. If this block ends with no branches (it just falls through to its succ)
65/// just return false, leaving TBB/FBB null.
66/// 2. If this block ends with only an unconditional branch, it sets TBB to be
67/// the destination block.
68/// 3. If this block ends with an conditional branch and it falls through to
69/// an successor block, it sets TBB to be the branch destination block and a
70/// list of operands that evaluate the condition. These
71/// operands can be passed to other TargetInstrInfo methods to create new
72/// branches.
73/// 4. If this block ends with an conditional branch and an unconditional
74/// block, it returns the 'true' destination in TBB, the 'false' destination
75/// in FBB, and a list of operands that evaluate the condition. These
76/// operands can be passed to other TargetInstrInfo methods to create new
77/// branches.
78///
79/// Note that removeBranch and insertBranch must be implemented to support
80/// cases where this method returns success.
81///
82bool NVPTXInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
83 MachineBasicBlock *&TBB,
84 MachineBasicBlock *&FBB,
85 SmallVectorImpl<MachineOperand> &Cond,
86 bool AllowModify) const {
87 // If the block has no terminators, it just falls into the block after it.
88 MachineBasicBlock::iterator I = MBB.end();
89 if (I == MBB.begin() || !isUnpredicatedTerminator(MI: *--I))
90 return false;
91
92 // Get the last instruction in the block.
93 MachineInstr &LastInst = *I;
94
95 // If there is only one terminator instruction, process it.
96 if (I == MBB.begin() || !isUnpredicatedTerminator(MI: *--I)) {
97 if (LastInst.getOpcode() == NVPTX::GOTO) {
98 TBB = LastInst.getOperand(i: 0).getMBB();
99 return false;
100 } else if (LastInst.getOpcode() == NVPTX::CBranch) {
101 // Block ends with fall-through condbranch.
102 TBB = LastInst.getOperand(i: 1).getMBB();
103 Cond.push_back(Elt: LastInst.getOperand(i: 0));
104 return false;
105 }
106 // Otherwise, don't know what this is.
107 return true;
108 }
109
110 // Get the instruction before it if it's a terminator.
111 MachineInstr &SecondLastInst = *I;
112
113 // If there are three terminators, we don't know what sort of block this is.
114 if (I != MBB.begin() && isUnpredicatedTerminator(MI: *--I))
115 return true;
116
117 // If the block ends with NVPTX::GOTO and NVPTX:CBranch, handle it.
118 if (SecondLastInst.getOpcode() == NVPTX::CBranch &&
119 LastInst.getOpcode() == NVPTX::GOTO) {
120 TBB = SecondLastInst.getOperand(i: 1).getMBB();
121 Cond.push_back(Elt: SecondLastInst.getOperand(i: 0));
122 FBB = LastInst.getOperand(i: 0).getMBB();
123 return false;
124 }
125
126 // If the block ends with two NVPTX:GOTOs, handle it. The second one is not
127 // executed, so remove it.
128 if (SecondLastInst.getOpcode() == NVPTX::GOTO &&
129 LastInst.getOpcode() == NVPTX::GOTO) {
130 TBB = SecondLastInst.getOperand(i: 0).getMBB();
131 I = LastInst;
132 if (AllowModify)
133 I->eraseFromParent();
134 return false;
135 }
136
137 // Otherwise, can't handle this.
138 return true;
139}
140
141unsigned NVPTXInstrInfo::removeBranch(MachineBasicBlock &MBB,
142 int *BytesRemoved) const {
143 assert(!BytesRemoved && "code size not handled");
144 MachineBasicBlock::iterator I = MBB.end();
145 if (I == MBB.begin())
146 return 0;
147 --I;
148 if (I->getOpcode() != NVPTX::GOTO && I->getOpcode() != NVPTX::CBranch)
149 return 0;
150
151 // Remove the branch.
152 I->eraseFromParent();
153
154 I = MBB.end();
155
156 if (I == MBB.begin())
157 return 1;
158 --I;
159 if (I->getOpcode() != NVPTX::CBranch)
160 return 1;
161
162 // Remove the branch.
163 I->eraseFromParent();
164 return 2;
165}
166
167unsigned NVPTXInstrInfo::insertBranch(MachineBasicBlock &MBB,
168 MachineBasicBlock *TBB,
169 MachineBasicBlock *FBB,
170 ArrayRef<MachineOperand> Cond,
171 const DebugLoc &DL,
172 int *BytesAdded) const {
173 assert(!BytesAdded && "code size not handled");
174
175 // Shouldn't be a fall through.
176 assert(TBB && "insertBranch must not be told to insert a fallthrough");
177 assert((Cond.size() == 1 || Cond.size() == 0) &&
178 "NVPTX branch conditions have two components!");
179
180 // One-way branch.
181 if (!FBB) {
182 if (Cond.empty()) // Unconditional branch
183 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: NVPTX::GOTO)).addMBB(MBB: TBB);
184 else // Conditional branch
185 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: NVPTX::CBranch)).add(MO: Cond[0]).addMBB(MBB: TBB);
186 return 1;
187 }
188
189 // Two-way Conditional Branch.
190 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: NVPTX::CBranch)).add(MO: Cond[0]).addMBB(MBB: TBB);
191 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: NVPTX::GOTO)).addMBB(MBB: FBB);
192 return 2;
193}