1//===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the X86MCCodeEmitter class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MCTargetDesc/X86BaseInfo.h"
14#include "MCTargetDesc/X86FixupKinds.h"
15#include "MCTargetDesc/X86MCAsmInfo.h"
16#include "MCTargetDesc/X86MCTargetDesc.h"
17#include "llvm/ADT/SmallVector.h"
18#include "llvm/BinaryFormat/ELF.h"
19#include "llvm/MC/MCCodeEmitter.h"
20#include "llvm/MC/MCContext.h"
21#include "llvm/MC/MCExpr.h"
22#include "llvm/MC/MCFixup.h"
23#include "llvm/MC/MCInst.h"
24#include "llvm/MC/MCInstrDesc.h"
25#include "llvm/MC/MCInstrInfo.h"
26#include "llvm/MC/MCRegisterInfo.h"
27#include "llvm/MC/MCSubtargetInfo.h"
28#include "llvm/MC/MCSymbol.h"
29#include "llvm/Support/Casting.h"
30#include "llvm/Support/ErrorHandling.h"
31#include <cassert>
32#include <cstdint>
33#include <cstdlib>
34
35using namespace llvm;
36
37#define DEBUG_TYPE "mccodeemitter"
38
39namespace {
40
41enum PrefixKind { None, REX, REX2, XOP, VEX2, VEX3, EVEX };
42
43static void emitByte(uint8_t C, SmallVectorImpl<char> &CB) { CB.push_back(Elt: C); }
44
45class X86OpcodePrefixHelper {
46 // REX (1 byte)
47 // +-----+ +------+
48 // | 40H | | WRXB |
49 // +-----+ +------+
50
51 // REX2 (2 bytes)
52 // +-----+ +-------------------+
53 // | D5H | | M | R'X'B' | WRXB |
54 // +-----+ +-------------------+
55
56 // XOP (3-byte)
57 // +-----+ +--------------+ +-------------------+
58 // | 8Fh | | RXB | m-mmmm | | W | vvvv | L | pp |
59 // +-----+ +--------------+ +-------------------+
60
61 // VEX2 (2 bytes)
62 // +-----+ +-------------------+
63 // | C5h | | R | vvvv | L | pp |
64 // +-----+ +-------------------+
65
66 // VEX3 (3 bytes)
67 // +-----+ +--------------+ +-------------------+
68 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
69 // +-----+ +--------------+ +-------------------+
70
71 // VEX_R: opcode externsion equivalent to REX.R in
72 // 1's complement (inverted) form
73 //
74 // 1: Same as REX_R=0 (must be 1 in 32-bit mode)
75 // 0: Same as REX_R=1 (64 bit mode only)
76
77 // VEX_X: equivalent to REX.X, only used when a
78 // register is used for index in SIB Byte.
79 //
80 // 1: Same as REX.X=0 (must be 1 in 32-bit mode)
81 // 0: Same as REX.X=1 (64-bit mode only)
82
83 // VEX_B:
84 // 1: Same as REX_B=0 (ignored in 32-bit mode)
85 // 0: Same as REX_B=1 (64 bit mode only)
86
87 // VEX_W: opcode specific (use like REX.W, or used for
88 // opcode extension, or ignored, depending on the opcode byte)
89
90 // VEX_5M (VEX m-mmmmm field):
91 //
92 // 0b00000: Reserved for future use
93 // 0b00001: implied 0F leading opcode
94 // 0b00010: implied 0F 38 leading opcode bytes
95 // 0b00011: implied 0F 3A leading opcode bytes
96 // 0b00100: Reserved for future use
97 // 0b00101: VEX MAP5
98 // 0b00110: VEX MAP6
99 // 0b00111: VEX MAP7
100 // 0b00111-0b11111: Reserved for future use
101 // 0b01000: XOP map select - 08h instructions with imm byte
102 // 0b01001: XOP map select - 09h instructions with no imm byte
103 // 0b01010: XOP map select - 0Ah instructions with imm dword
104
105 // VEX_4V (VEX vvvv field): a register specifier
106 // (in 1's complement form) or 1111 if unused.
107
108 // VEX_PP: opcode extension providing equivalent
109 // functionality of a SIMD prefix
110 // 0b00: None
111 // 0b01: 66
112 // 0b10: F3
113 // 0b11: F2
114
115 // EVEX (4 bytes)
116 // +-----+ +---------------+ +-------------------+ +------------------------+
117 // | 62h | | RXBR' | B'mmm | | W | vvvv | U | pp | | z | L'L | b | v' | aaa |
118 // +-----+ +---------------+ +-------------------+ +------------------------+
119
120 // EVEX_L2/VEX_L (Vector Length):
121 // L2 L
122 // 0 0: scalar or 128-bit vector
123 // 0 1: 256-bit vector
124 // 1 0: 512-bit vector
125
126 // 32-Register Support in 64-bit Mode Using EVEX with Embedded REX/REX2 Bits:
127 //
128 // +----------+---------+--------+-----------+---------+--------------+
129 // | | 4 | 3 | [2:0] | Type | Common Usage |
130 // +----------+---------+--------+-----------+---------+--------------+
131 // | REG | EVEX_R' | EVEX_R | modrm.reg | GPR, VR | Dest or Src |
132 // | VVVV | EVEX_v' | EVEX.vvvv | GPR, VR | Dest or Src |
133 // | RM (VR) | EVEX_X | EVEX_B | modrm.r/m | VR | Dest or Src |
134 // | RM (GPR) | EVEX_B' | EVEX_B | modrm.r/m | GPR | Dest or Src |
135 // | BASE | EVEX_B' | EVEX_B | modrm.r/m | GPR | MA |
136 // | INDEX | EVEX_U | EVEX_X | sib.index | GPR | MA |
137 // | VIDX | EVEX_v' | EVEX_X | sib.index | VR | VSIB MA |
138 // +----------+---------+--------+-----------+---------+--------------+
139 //
140 // * GPR - General-purpose register
141 // * VR - Vector register
142 // * VIDX - Vector index
143 // * VSIB - Vector SIB
144 // * MA - Memory addressing
145
146private:
147 unsigned W : 1;
148 unsigned R : 1;
149 unsigned X : 1;
150 unsigned B : 1;
151 unsigned M : 1;
152 unsigned R2 : 1;
153 unsigned X2 : 1;
154 unsigned B2 : 1;
155 unsigned VEX_4V : 4;
156 unsigned VEX_L : 1;
157 unsigned VEX_PP : 2;
158 unsigned VEX_5M : 5;
159 unsigned EVEX_z : 1;
160 unsigned EVEX_L2 : 1;
161 unsigned EVEX_b : 1;
162 unsigned EVEX_V2 : 1;
163 unsigned EVEX_aaa : 3;
164 PrefixKind Kind = None;
165 const MCRegisterInfo &MRI;
166
167 unsigned getRegEncoding(const MCInst &MI, unsigned OpNum) const {
168 return MRI.getEncodingValue(Reg: MI.getOperand(i: OpNum).getReg());
169 }
170
171 void setR(unsigned Encoding) { R = Encoding >> 3 & 1; }
172 void setR2(unsigned Encoding) {
173 R2 = Encoding >> 4 & 1;
174 assert((!R2 || (Kind <= REX2 || Kind == EVEX)) && "invalid setting");
175 }
176 void setX(unsigned Encoding) { X = Encoding >> 3 & 1; }
177 void setX2(unsigned Encoding) {
178 assert((Kind <= REX2 || Kind == EVEX) && "invalid setting");
179 X2 = Encoding >> 4 & 1;
180 }
181 void setB(unsigned Encoding) { B = Encoding >> 3 & 1; }
182 void setB2(unsigned Encoding) {
183 assert((Kind <= REX2 || Kind == EVEX) && "invalid setting");
184 B2 = Encoding >> 4 & 1;
185 }
186 void set4V(unsigned Encoding) { VEX_4V = Encoding & 0xf; }
187 void setV2(unsigned Encoding) { EVEX_V2 = Encoding >> 4 & 1; }
188
189public:
190 void setW(bool V) { W = V; }
191 void setR(const MCInst &MI, unsigned OpNum) {
192 setR(getRegEncoding(MI, OpNum));
193 }
194 void setX(const MCInst &MI, unsigned OpNum, unsigned Shift = 3) {
195 MCRegister Reg = MI.getOperand(i: OpNum).getReg();
196 // X is used to extend vector register only when shift is not 3.
197 if (Shift != 3 && X86II::isApxExtendedReg(Reg))
198 return;
199 unsigned Encoding = MRI.getEncodingValue(Reg);
200 X = Encoding >> Shift & 1;
201 }
202 void setB(const MCInst &MI, unsigned OpNum) {
203 B = getRegEncoding(MI, OpNum) >> 3 & 1;
204 }
205 void set4V(const MCInst &MI, unsigned OpNum, bool IsImm = false) {
206 // OF, SF, ZF and CF reuse VEX_4V bits but are not reversed
207 if (IsImm)
208 set4V(~(MI.getOperand(i: OpNum).getImm()));
209 else
210 set4V(getRegEncoding(MI, OpNum));
211 }
212 void setL(bool V) { VEX_L = V; }
213 void setPP(unsigned V) { VEX_PP = V; }
214 void set5M(unsigned V) { VEX_5M = V; }
215 void setR2(const MCInst &MI, unsigned OpNum) {
216 setR2(getRegEncoding(MI, OpNum));
217 }
218 void setRR2(const MCInst &MI, unsigned OpNum) {
219 unsigned Encoding = getRegEncoding(MI, OpNum);
220 setR(Encoding);
221 setR2(Encoding);
222 }
223 void setM(bool V) { M = V; }
224 void setXX2(const MCInst &MI, unsigned OpNum) {
225 MCRegister Reg = MI.getOperand(i: OpNum).getReg();
226 unsigned Encoding = MRI.getEncodingValue(Reg);
227 setX(Encoding);
228 // Index can be a vector register while X2 is used to extend GPR only.
229 if (Kind <= REX2 || X86II::isApxExtendedReg(Reg))
230 setX2(Encoding);
231 }
232 void setBB2(const MCInst &MI, unsigned OpNum) {
233 MCRegister Reg = MI.getOperand(i: OpNum).getReg();
234 unsigned Encoding = MRI.getEncodingValue(Reg);
235 setB(Encoding);
236 // Base can be a vector register while B2 is used to extend GPR only
237 if (Kind <= REX2 || X86II::isApxExtendedReg(Reg))
238 setB2(Encoding);
239 }
240 void setZ(bool V) { EVEX_z = V; }
241 void setL2(bool V) { EVEX_L2 = V; }
242 void setEVEX_b(bool V) { EVEX_b = V; }
243 void setEVEX_U(bool V) { X2 = V; }
244 void setV2(const MCInst &MI, unsigned OpNum, bool HasVEX_4V) {
245 // Only needed with VSIB which don't use VVVV.
246 if (HasVEX_4V)
247 return;
248 MCRegister Reg = MI.getOperand(i: OpNum).getReg();
249 if (X86II::isApxExtendedReg(Reg))
250 return;
251 setV2(MRI.getEncodingValue(Reg));
252 }
253 void set4VV2(const MCInst &MI, unsigned OpNum) {
254 unsigned Encoding = getRegEncoding(MI, OpNum);
255 set4V(Encoding);
256 setV2(Encoding);
257 }
258 void setAAA(const MCInst &MI, unsigned OpNum) {
259 EVEX_aaa = getRegEncoding(MI, OpNum);
260 }
261 void setNF(bool V) { EVEX_aaa |= V << 2; }
262 void setSC(const MCInst &MI, unsigned OpNum) {
263 unsigned Encoding = MI.getOperand(i: OpNum).getImm();
264 EVEX_V2 = ~(Encoding >> 3) & 0x1;
265 EVEX_aaa = Encoding & 0x7;
266 }
267
268 X86OpcodePrefixHelper(const MCRegisterInfo &MRI)
269 : W(0), R(0), X(0), B(0), M(0), R2(0), X2(0), B2(0), VEX_4V(0), VEX_L(0),
270 VEX_PP(0), VEX_5M(0), EVEX_z(0), EVEX_L2(0), EVEX_b(0), EVEX_V2(0),
271 EVEX_aaa(0), MRI(MRI) {}
272
273 void setLowerBound(PrefixKind K) { Kind = K; }
274
275 PrefixKind determineOptimalKind() {
276 switch (Kind) {
277 case None:
278 // Not M bit here by intention b/c
279 // 1. No guarantee that REX2 is supported by arch w/o explict EGPR
280 // 2. REX2 is longer than 0FH
281 Kind = (R2 | X2 | B2) ? REX2 : (W | R | X | B) ? REX : None;
282 break;
283 case REX:
284 Kind = (R2 | X2 | B2) ? REX2 : REX;
285 break;
286 case REX2:
287 case XOP:
288 case VEX3:
289 case EVEX:
290 break;
291 case VEX2:
292 Kind = (W | X | B | (VEX_5M != 1)) ? VEX3 : VEX2;
293 break;
294 }
295 return Kind;
296 }
297
298 void emit(SmallVectorImpl<char> &CB) const {
299 uint8_t FirstPayload =
300 ((~R) & 0x1) << 7 | ((~X) & 0x1) << 6 | ((~B) & 0x1) << 5;
301 uint8_t LastPayload = ((~VEX_4V) & 0xf) << 3 | VEX_L << 2 | VEX_PP;
302 switch (Kind) {
303 case None:
304 return;
305 case REX:
306 emitByte(C: 0x40 | W << 3 | R << 2 | X << 1 | B, CB);
307 return;
308 case REX2:
309 emitByte(C: 0xD5, CB);
310 emitByte(C: M << 7 | R2 << 6 | X2 << 5 | B2 << 4 | W << 3 | R << 2 | X << 1 |
311 B,
312 CB);
313 return;
314 case VEX2:
315 emitByte(C: 0xC5, CB);
316 emitByte(C: ((~R) & 1) << 7 | LastPayload, CB);
317 return;
318 case VEX3:
319 case XOP:
320 emitByte(C: Kind == VEX3 ? 0xC4 : 0x8F, CB);
321 emitByte(C: FirstPayload | VEX_5M, CB);
322 emitByte(C: W << 7 | LastPayload, CB);
323 return;
324 case EVEX:
325 assert(VEX_5M && !(VEX_5M & 0x8) && "invalid mmm fields for EVEX!");
326 emitByte(C: 0x62, CB);
327 emitByte(C: FirstPayload | ((~R2) & 0x1) << 4 | B2 << 3 | VEX_5M, CB);
328 emitByte(C: W << 7 | ((~VEX_4V) & 0xf) << 3 | ((~X2) & 0x1) << 2 | VEX_PP,
329 CB);
330 emitByte(C: EVEX_z << 7 | EVEX_L2 << 6 | VEX_L << 5 | EVEX_b << 4 |
331 ((~EVEX_V2) & 0x1) << 3 | EVEX_aaa,
332 CB);
333 return;
334 }
335 }
336};
337
338class X86MCCodeEmitter : public MCCodeEmitter {
339 const MCInstrInfo &MCII;
340 MCContext &Ctx;
341
342public:
343 X86MCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
344 : MCII(mcii), Ctx(ctx) {}
345 X86MCCodeEmitter(const X86MCCodeEmitter &) = delete;
346 X86MCCodeEmitter &operator=(const X86MCCodeEmitter &) = delete;
347 ~X86MCCodeEmitter() override = default;
348
349 void emitPrefix(const MCInst &MI, SmallVectorImpl<char> &CB,
350 const MCSubtargetInfo &STI) const;
351
352 void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
353 SmallVectorImpl<MCFixup> &Fixups,
354 const MCSubtargetInfo &STI) const override;
355
356private:
357 unsigned getX86RegNum(const MCOperand &MO) const;
358
359 unsigned getX86RegEncoding(const MCInst &MI, unsigned OpNum) const;
360
361 void emitImmediate(const MCOperand &Disp, SMLoc Loc, unsigned ImmSize,
362 MCFixupKind FixupKind, uint64_t StartByte,
363 SmallVectorImpl<char> &CB,
364 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset = 0) const;
365
366 void emitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
367 SmallVectorImpl<char> &CB) const;
368
369 void emitSIBByte(unsigned SS, unsigned Index, unsigned Base,
370 SmallVectorImpl<char> &CB) const;
371
372 void emitMemModRMByte(const MCInst &MI, unsigned Op, unsigned RegOpcodeField,
373 uint64_t TSFlags, PrefixKind Kind, uint64_t StartByte,
374 SmallVectorImpl<char> &CB,
375 SmallVectorImpl<MCFixup> &Fixups,
376 const MCSubtargetInfo &STI,
377 bool ForceSIB = false) const;
378
379 PrefixKind emitPrefixImpl(unsigned &CurOp, const MCInst &MI,
380 const MCSubtargetInfo &STI,
381 SmallVectorImpl<char> &CB) const;
382
383 PrefixKind emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,
384 const MCSubtargetInfo &STI,
385 SmallVectorImpl<char> &CB) const;
386
387 void emitSegmentOverridePrefix(unsigned SegOperand, const MCInst &MI,
388 SmallVectorImpl<char> &CB) const;
389
390 PrefixKind emitOpcodePrefix(int MemOperand, const MCInst &MI,
391 const MCSubtargetInfo &STI,
392 SmallVectorImpl<char> &CB) const;
393
394 PrefixKind emitREXPrefix(int MemOperand, const MCInst &MI,
395 const MCSubtargetInfo &STI,
396 SmallVectorImpl<char> &CB) const;
397};
398
399} // end anonymous namespace
400
401static uint8_t modRMByte(unsigned Mod, unsigned RegOpcode, unsigned RM) {
402 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
403 return RM | (RegOpcode << 3) | (Mod << 6);
404}
405
406static void emitConstant(uint64_t Val, unsigned Size,
407 SmallVectorImpl<char> &CB) {
408 // Output the constant in little endian byte order.
409 for (unsigned i = 0; i != Size; ++i) {
410 emitByte(C: Val & 255, CB);
411 Val >>= 8;
412 }
413}
414
415/// Determine if this immediate can fit in a disp8 or a compressed disp8 for
416/// EVEX instructions. \p will be set to the value to pass to the ImmOffset
417/// parameter of emitImmediate.
418static bool isDispOrCDisp8(uint64_t TSFlags, int Value, int &ImmOffset) {
419 bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX;
420
421 unsigned CD8_Scale =
422 (TSFlags & X86II::CD8_Scale_Mask) >> X86II::CD8_Scale_Shift;
423 CD8_Scale = CD8_Scale ? 1U << (CD8_Scale - 1) : 0U;
424 if (!HasEVEX || !CD8_Scale)
425 return isInt<8>(x: Value);
426
427 assert(isPowerOf2_32(CD8_Scale) && "Unexpected CD8 scale!");
428 if (Value & (CD8_Scale - 1)) // Unaligned offset
429 return false;
430
431 int CDisp8 = Value / static_cast<int>(CD8_Scale);
432 if (!isInt<8>(x: CDisp8))
433 return false;
434
435 // ImmOffset will be added to Value in emitImmediate leaving just CDisp8.
436 ImmOffset = CDisp8 - Value;
437 return true;
438}
439
440/// \returns the appropriate fixup kind to use for an immediate in an
441/// instruction with the specified TSFlags.
442static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
443 unsigned Size = X86II::getSizeOfImm(TSFlags);
444 bool isPCRel = X86II::isImmPCRel(TSFlags);
445
446 if (X86II::isImmSigned(TSFlags)) {
447 switch (Size) {
448 default:
449 llvm_unreachable("Unsupported signed fixup size!");
450 case 4:
451 return MCFixupKind(X86::reloc_signed_4byte);
452 }
453 }
454 switch (Size) {
455 default:
456 llvm_unreachable("Invalid generic fixup size!");
457 case 1:
458 return isPCRel ? FK_PCRel_1 : FK_Data_1;
459 case 2:
460 return isPCRel ? FK_PCRel_2 : FK_Data_2;
461 case 4:
462 return isPCRel ? FK_PCRel_4 : FK_Data_4;
463 case 8:
464 return isPCRel ? FK_PCRel_8 : FK_Data_8;
465 }
466}
467
468enum GlobalOffsetTableExprKind { GOT_None, GOT_Normal, GOT_SymDiff };
469
470/// Check if this expression starts with _GLOBAL_OFFSET_TABLE_ and if it is
471/// of the form _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on
472/// ELF i386 as _GLOBAL_OFFSET_TABLE_ is magical. We check only simple case that
473/// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start of a
474/// binary expression.
475static GlobalOffsetTableExprKind
476startsWithGlobalOffsetTable(const MCExpr *Expr) {
477 const MCExpr *RHS = nullptr;
478 if (Expr->getKind() == MCExpr::Binary) {
479 const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr);
480 Expr = BE->getLHS();
481 RHS = BE->getRHS();
482 }
483
484 if (Expr->getKind() != MCExpr::SymbolRef)
485 return GOT_None;
486
487 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr *>(Expr);
488 const MCSymbol &S = Ref->getSymbol();
489 if (S.getName() != "_GLOBAL_OFFSET_TABLE_")
490 return GOT_None;
491 if (RHS && RHS->getKind() == MCExpr::SymbolRef)
492 return GOT_SymDiff;
493 return GOT_Normal;
494}
495
496static bool hasSecRelSymbolRef(const MCExpr *Expr) {
497 if (Expr->getKind() == MCExpr::SymbolRef) {
498 auto *Ref = static_cast<const MCSymbolRefExpr *>(Expr);
499 return Ref->getSpecifier() == X86::S_COFF_SECREL;
500 }
501 return false;
502}
503
504static bool isPCRel32Branch(const MCInst &MI, const MCInstrInfo &MCII) {
505 unsigned Opcode = MI.getOpcode();
506 const MCInstrDesc &Desc = MCII.get(Opcode);
507 if ((Opcode != X86::CALL64pcrel32 && Opcode != X86::JMP_4 &&
508 Opcode != X86::JCC_4) ||
509 getImmFixupKind(TSFlags: Desc.TSFlags) != FK_PCRel_4)
510 return false;
511
512 unsigned CurOp = X86II::getOperandBias(Desc);
513 const MCOperand &Op = MI.getOperand(i: CurOp);
514 if (!Op.isExpr())
515 return false;
516
517 auto *Ref = dyn_cast<MCSymbolRefExpr>(Val: Op.getExpr());
518 return Ref && Ref->getSpecifier() == X86::S_None;
519}
520
521unsigned X86MCCodeEmitter::getX86RegNum(const MCOperand &MO) const {
522 return Ctx.getRegisterInfo()->getEncodingValue(Reg: MO.getReg()) & 0x7;
523}
524
525unsigned X86MCCodeEmitter::getX86RegEncoding(const MCInst &MI,
526 unsigned OpNum) const {
527 return Ctx.getRegisterInfo()->getEncodingValue(Reg: MI.getOperand(i: OpNum).getReg());
528}
529
530void X86MCCodeEmitter::emitImmediate(const MCOperand &DispOp, SMLoc Loc,
531 unsigned Size, MCFixupKind FixupKind,
532 uint64_t StartByte,
533 SmallVectorImpl<char> &CB,
534 SmallVectorImpl<MCFixup> &Fixups,
535 int ImmOffset) const {
536 const MCExpr *Expr = nullptr;
537 if (DispOp.isImm()) {
538 // If this is a simple integer displacement that doesn't require a
539 // relocation, emit it now.
540 if (FixupKind != FK_PCRel_1 && FixupKind != FK_PCRel_2 &&
541 FixupKind != FK_PCRel_4) {
542 emitConstant(Val: DispOp.getImm() + ImmOffset, Size, CB);
543 return;
544 }
545 Expr = MCConstantExpr::create(Value: DispOp.getImm(), Ctx);
546 } else {
547 Expr = DispOp.getExpr();
548 }
549
550 // If we have an immoffset, add it to the expression.
551 if ((FixupKind == FK_Data_4 || FixupKind == FK_Data_8 ||
552 FixupKind == MCFixupKind(X86::reloc_signed_4byte))) {
553 GlobalOffsetTableExprKind Kind = startsWithGlobalOffsetTable(Expr);
554 if (Kind != GOT_None) {
555 assert(ImmOffset == 0);
556
557 if (Size == 8) {
558 FixupKind =
559 MCFixupKind(FirstLiteralRelocationKind + ELF::R_X86_64_GOTPC64);
560 } else {
561 assert(Size == 4);
562 FixupKind = MCFixupKind(X86::reloc_global_offset_table);
563 }
564
565 if (Kind == GOT_Normal)
566 ImmOffset = static_cast<int>(CB.size() - StartByte);
567 } else if (Expr->getKind() == MCExpr::SymbolRef) {
568 if (hasSecRelSymbolRef(Expr)) {
569 FixupKind = MCFixupKind(FK_SecRel_4);
570 }
571 } else if (Expr->getKind() == MCExpr::Binary) {
572 const MCBinaryExpr *Bin = static_cast<const MCBinaryExpr *>(Expr);
573 if (hasSecRelSymbolRef(Expr: Bin->getLHS()) ||
574 hasSecRelSymbolRef(Expr: Bin->getRHS())) {
575 FixupKind = MCFixupKind(FK_SecRel_4);
576 }
577 }
578 }
579
580 // If the fixup is pc-relative, we need to bias the value to be relative to
581 // the start of the field, not the end of the field.
582 if (FixupKind == FK_PCRel_4 ||
583 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
584 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load) ||
585 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load_rex2) ||
586 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_relax) ||
587 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_relax_rex) ||
588 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_relax_rex2) ||
589 FixupKind == MCFixupKind(X86::reloc_branch_4byte_pcrel) ||
590 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_relax_evex)) {
591 ImmOffset -= 4;
592 // If this is a pc-relative load off _GLOBAL_OFFSET_TABLE_:
593 // leaq _GLOBAL_OFFSET_TABLE_(%rip), %r15
594 // this needs to be a GOTPC32 relocation.
595 if (startsWithGlobalOffsetTable(Expr) != GOT_None)
596 FixupKind = MCFixupKind(X86::reloc_global_offset_table);
597 }
598
599 if (FixupKind == FK_PCRel_2)
600 ImmOffset -= 2;
601 if (FixupKind == FK_PCRel_1)
602 ImmOffset -= 1;
603
604 if (ImmOffset)
605 Expr = MCBinaryExpr::createAdd(LHS: Expr, RHS: MCConstantExpr::create(Value: ImmOffset, Ctx),
606 Ctx, Loc: Expr->getLoc());
607
608 // Emit a symbolic constant as a fixup and 4 zeros.
609 Fixups.push_back(Elt: MCFixup::create(Offset: static_cast<uint32_t>(CB.size() - StartByte),
610 Value: Expr, Kind: FixupKind, Loc));
611 emitConstant(Val: 0, Size, CB);
612}
613
614void X86MCCodeEmitter::emitRegModRMByte(const MCOperand &ModRMReg,
615 unsigned RegOpcodeFld,
616 SmallVectorImpl<char> &CB) const {
617 emitByte(C: modRMByte(Mod: 3, RegOpcode: RegOpcodeFld, RM: getX86RegNum(MO: ModRMReg)), CB);
618}
619
620void X86MCCodeEmitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base,
621 SmallVectorImpl<char> &CB) const {
622 // SIB byte is in the same format as the modRMByte.
623 emitByte(C: modRMByte(Mod: SS, RegOpcode: Index, RM: Base), CB);
624}
625
626void X86MCCodeEmitter::emitMemModRMByte(
627 const MCInst &MI, unsigned Op, unsigned RegOpcodeField, uint64_t TSFlags,
628 PrefixKind Kind, uint64_t StartByte, SmallVectorImpl<char> &CB,
629 SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI,
630 bool ForceSIB) const {
631 const MCOperand &Disp = MI.getOperand(i: Op + X86::AddrDisp);
632 const MCOperand &Base = MI.getOperand(i: Op + X86::AddrBaseReg);
633 const MCOperand &Scale = MI.getOperand(i: Op + X86::AddrScaleAmt);
634 const MCOperand &IndexReg = MI.getOperand(i: Op + X86::AddrIndexReg);
635 MCRegister BaseReg = Base.getReg();
636
637 // Handle %rip relative addressing.
638 if (BaseReg == X86::RIP ||
639 BaseReg == X86::EIP) { // [disp32+rIP] in X86-64 mode
640 assert(STI.hasFeature(X86::Is64Bit) &&
641 "Rip-relative addressing requires 64-bit mode");
642 assert(!IndexReg.getReg() && !ForceSIB && "Invalid rip-relative address");
643 emitByte(C: modRMByte(Mod: 0, RegOpcode: RegOpcodeField, RM: 5), CB);
644
645 unsigned Opcode = MI.getOpcode();
646 unsigned FixupKind = [&]() {
647 // Enable relaxed relocation only for a MCSymbolRefExpr. We cannot use a
648 // relaxed relocation if an offset is present (e.g. x@GOTPCREL+4).
649 if (!(Disp.isExpr() && isa<MCSymbolRefExpr>(Val: Disp.getExpr())))
650 return X86::reloc_riprel_4byte;
651
652 // Certain loads for GOT references can be relocated against the symbol
653 // directly if the symbol ends up in the same linkage unit.
654 switch (Opcode) {
655 default:
656 return X86::reloc_riprel_4byte;
657 case X86::MOV64rm:
658 // movq loads is a subset of reloc_riprel_4byte_relax_rex/rex2. It is a
659 // special case because COFF and Mach-O don't support ELF's more
660 // flexible R_X86_64_REX_GOTPCRELX/R_X86_64_CODE_4_GOTPCRELX relaxation.
661 return Kind == REX2 ? X86::reloc_riprel_4byte_movq_load_rex2
662 : X86::reloc_riprel_4byte_movq_load;
663 case X86::ADC32rm:
664 case X86::ADD32rm:
665 case X86::AND32rm:
666 case X86::CMP32rm:
667 case X86::MOV32rm:
668 case X86::OR32rm:
669 case X86::SBB32rm:
670 case X86::SUB32rm:
671 case X86::TEST32mr:
672 case X86::XOR32rm:
673 case X86::CALL64m:
674 case X86::JMP64m:
675 case X86::TAILJMPm64:
676 case X86::TEST64mr:
677 case X86::ADC64rm:
678 case X86::ADD64rm:
679 case X86::AND64rm:
680 case X86::CMP64rm:
681 case X86::OR64rm:
682 case X86::SBB64rm:
683 case X86::SUB64rm:
684 case X86::XOR64rm:
685 case X86::LEA64r:
686 return Kind == REX2 ? X86::reloc_riprel_4byte_relax_rex2
687 : Kind == REX ? X86::reloc_riprel_4byte_relax_rex
688 : X86::reloc_riprel_4byte_relax;
689 case X86::ADD64rm_NF:
690 case X86::ADD64rm_ND:
691 case X86::ADD64mr_ND:
692 case X86::ADD64mr_NF_ND:
693 case X86::ADD64rm_NF_ND:
694 return X86::reloc_riprel_4byte_relax_evex;
695 }
696 }();
697
698 // rip-relative addressing is actually relative to the *next* instruction.
699 // Since an immediate can follow the mod/rm byte for an instruction, this
700 // means that we need to bias the displacement field of the instruction with
701 // the size of the immediate field. If we have this case, add it into the
702 // expression to emit.
703 // Note: rip-relative addressing using immediate displacement values should
704 // not be adjusted, assuming it was the user's intent.
705 int ImmSize = !Disp.isImm() && X86II::hasImm(TSFlags)
706 ? X86II::getSizeOfImm(TSFlags)
707 : 0;
708
709 emitImmediate(DispOp: Disp, Loc: MI.getLoc(), Size: 4, FixupKind: MCFixupKind(FixupKind), StartByte, CB,
710 Fixups, ImmOffset: -ImmSize);
711 return;
712 }
713
714 unsigned BaseRegNo = BaseReg ? getX86RegNum(MO: Base) : -1U;
715
716 bool IsAdSize16 = STI.hasFeature(Feature: X86::Is32Bit) &&
717 (TSFlags & X86II::AdSizeMask) == X86II::AdSize16;
718
719 // 16-bit addressing forms of the ModR/M byte have a different encoding for
720 // the R/M field and are far more limited in which registers can be used.
721 if (IsAdSize16 || X86_MC::is16BitMemOperand(MI, Op, STI)) {
722 if (BaseReg) {
723 // For 32-bit addressing, the row and column values in Table 2-2 are
724 // basically the same. It's AX/CX/DX/BX/SP/BP/SI/DI in that order, with
725 // some special cases. And getX86RegNum reflects that numbering.
726 // For 16-bit addressing it's more fun, as shown in the SDM Vol 2A,
727 // Table 2-1 "16-Bit Addressing Forms with the ModR/M byte". We can only
728 // use SI/DI/BP/BX, which have "row" values 4-7 in no particular order,
729 // while values 0-3 indicate the allowed combinations (base+index) of
730 // those: 0 for BX+SI, 1 for BX+DI, 2 for BP+SI, 3 for BP+DI.
731 //
732 // R16Table[] is a lookup from the normal RegNo, to the row values from
733 // Table 2-1 for 16-bit addressing modes. Where zero means disallowed.
734 static const unsigned R16Table[] = {0, 0, 0, 7, 0, 6, 4, 5};
735 unsigned RMfield = R16Table[BaseRegNo];
736
737 assert(RMfield && "invalid 16-bit base register");
738
739 if (IndexReg.getReg()) {
740 unsigned IndexReg16 = R16Table[getX86RegNum(MO: IndexReg)];
741
742 assert(IndexReg16 && "invalid 16-bit index register");
743 // We must have one of SI/DI (4,5), and one of BP/BX (6,7).
744 assert(((IndexReg16 ^ RMfield) & 2) &&
745 "invalid 16-bit base/index register combination");
746 assert(Scale.getImm() == 1 &&
747 "invalid scale for 16-bit memory reference");
748
749 // Allow base/index to appear in either order (although GAS doesn't).
750 if (IndexReg16 & 2)
751 RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1);
752 else
753 RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1);
754 }
755
756 if (Disp.isImm() && isInt<8>(x: Disp.getImm())) {
757 if (Disp.getImm() == 0 && RMfield != 6) {
758 // There is no displacement; just the register.
759 emitByte(C: modRMByte(Mod: 0, RegOpcode: RegOpcodeField, RM: RMfield), CB);
760 return;
761 }
762 // Use the [REG]+disp8 form, including for [BP] which cannot be encoded.
763 emitByte(C: modRMByte(Mod: 1, RegOpcode: RegOpcodeField, RM: RMfield), CB);
764 emitImmediate(DispOp: Disp, Loc: MI.getLoc(), Size: 1, FixupKind: FK_Data_1, StartByte, CB, Fixups);
765 return;
766 }
767 // This is the [REG]+disp16 case.
768 emitByte(C: modRMByte(Mod: 2, RegOpcode: RegOpcodeField, RM: RMfield), CB);
769 } else {
770 assert(!IndexReg.getReg() && "Unexpected index register!");
771 // There is no BaseReg; this is the plain [disp16] case.
772 emitByte(C: modRMByte(Mod: 0, RegOpcode: RegOpcodeField, RM: 6), CB);
773 }
774
775 // Emit 16-bit displacement for plain disp16 or [REG]+disp16 cases.
776 emitImmediate(DispOp: Disp, Loc: MI.getLoc(), Size: 2, FixupKind: FK_Data_2, StartByte, CB, Fixups);
777 return;
778 }
779
780 // Check for presence of {disp8} or {disp32} pseudo prefixes.
781 bool UseDisp8 = MI.getFlags() & X86::IP_USE_DISP8;
782 bool UseDisp32 = MI.getFlags() & X86::IP_USE_DISP32;
783
784 // We only allow no displacement if no pseudo prefix is present.
785 bool AllowNoDisp = !UseDisp8 && !UseDisp32;
786 // Disp8 is allowed unless the {disp32} prefix is present.
787 bool AllowDisp8 = !UseDisp32;
788
789 // Determine whether a SIB byte is needed.
790 if (!ForceSIB && !X86II::needSIB(BaseReg, IndexReg: IndexReg.getReg(),
791 In64BitMode: STI.hasFeature(Feature: X86::Is64Bit))) {
792 if (!BaseReg) { // [disp32] in X86-32 mode
793 emitByte(C: modRMByte(Mod: 0, RegOpcode: RegOpcodeField, RM: 5), CB);
794 emitImmediate(DispOp: Disp, Loc: MI.getLoc(), Size: 4, FixupKind: FK_Data_4, StartByte, CB, Fixups);
795 return;
796 }
797
798 // If the base is not EBP/ESP/R12/R13/R20/R21/R28/R29 and there is no
799 // displacement, use simple indirect register encoding, this handles
800 // addresses like [EAX]. The encoding for [EBP], [R13], [R20], [R21], [R28]
801 // or [R29] with no displacement means [disp32] so we handle it by emitting
802 // a displacement of 0 later.
803 if (BaseRegNo != N86::EBP) {
804 if (Disp.isImm() && Disp.getImm() == 0 && AllowNoDisp) {
805 emitByte(C: modRMByte(Mod: 0, RegOpcode: RegOpcodeField, RM: BaseRegNo), CB);
806 return;
807 }
808
809 // If the displacement is @tlscall, treat it as a zero.
810 if (Disp.isExpr()) {
811 auto *Sym = dyn_cast<MCSymbolRefExpr>(Val: Disp.getExpr());
812 if (Sym && Sym->getSpecifier() == X86::S_TLSCALL) {
813 // This is exclusively used by call *a@tlscall(base). The relocation
814 // (R_386_TLSCALL or R_X86_64_TLSCALL) applies to the beginning.
815 Fixups.push_back(Elt: MCFixup::create(Offset: 0, Value: Sym, Kind: FK_NONE, Loc: MI.getLoc()));
816 emitByte(C: modRMByte(Mod: 0, RegOpcode: RegOpcodeField, RM: BaseRegNo), CB);
817 return;
818 }
819 }
820 }
821
822 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
823 // Including a compressed disp8 for EVEX instructions that support it.
824 // This also handles the 0 displacement for [EBP], [R13], [R21] or [R29]. We
825 // can't use disp8 if the {disp32} pseudo prefix is present.
826 if (Disp.isImm() && AllowDisp8) {
827 int ImmOffset = 0;
828 if (isDispOrCDisp8(TSFlags, Value: Disp.getImm(), ImmOffset)) {
829 emitByte(C: modRMByte(Mod: 1, RegOpcode: RegOpcodeField, RM: BaseRegNo), CB);
830 emitImmediate(DispOp: Disp, Loc: MI.getLoc(), Size: 1, FixupKind: FK_Data_1, StartByte, CB, Fixups,
831 ImmOffset);
832 return;
833 }
834 }
835
836 // Otherwise, emit the most general non-SIB encoding: [REG+disp32].
837 // Displacement may be 0 for [EBP], [R13], [R21], [R29] case if {disp32}
838 // pseudo prefix prevented using disp8 above.
839 emitByte(C: modRMByte(Mod: 2, RegOpcode: RegOpcodeField, RM: BaseRegNo), CB);
840 unsigned Opcode = MI.getOpcode();
841 unsigned FixupKind = Opcode == X86::MOV32rm ? X86::reloc_signed_4byte_relax
842 : X86::reloc_signed_4byte;
843 emitImmediate(DispOp: Disp, Loc: MI.getLoc(), Size: 4, FixupKind: MCFixupKind(FixupKind), StartByte, CB,
844 Fixups);
845 return;
846 }
847
848 // We need a SIB byte, so start by outputting the ModR/M byte first
849 assert(IndexReg.getReg() != X86::ESP && IndexReg.getReg() != X86::RSP &&
850 "Cannot use ESP as index reg!");
851
852 bool ForceDisp32 = false;
853 bool ForceDisp8 = false;
854 int ImmOffset = 0;
855 if (!BaseReg) {
856 // If there is no base register, we emit the special case SIB byte with
857 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
858 BaseRegNo = 5;
859 emitByte(C: modRMByte(Mod: 0, RegOpcode: RegOpcodeField, RM: 4), CB);
860 ForceDisp32 = true;
861 } else if (Disp.isImm() && Disp.getImm() == 0 && AllowNoDisp &&
862 // Base reg can't be EBP/RBP/R13/R21/R29 as that would end up with
863 // '5' as the base field, but that is the magic [*] nomenclature
864 // that indicates no base when mod=0. For these cases we'll emit a
865 // 0 displacement instead.
866 BaseRegNo != N86::EBP) {
867 // Emit no displacement ModR/M byte
868 emitByte(C: modRMByte(Mod: 0, RegOpcode: RegOpcodeField, RM: 4), CB);
869 } else if (Disp.isImm() && AllowDisp8 &&
870 isDispOrCDisp8(TSFlags, Value: Disp.getImm(), ImmOffset)) {
871 // Displacement fits in a byte or matches an EVEX compressed disp8, use
872 // disp8 encoding. This also handles EBP/R13/R21/R29 base with 0
873 // displacement unless {disp32} pseudo prefix was used.
874 emitByte(C: modRMByte(Mod: 1, RegOpcode: RegOpcodeField, RM: 4), CB);
875 ForceDisp8 = true;
876 } else {
877 // Otherwise, emit the normal disp32 encoding.
878 emitByte(C: modRMByte(Mod: 2, RegOpcode: RegOpcodeField, RM: 4), CB);
879 ForceDisp32 = true;
880 }
881
882 // Calculate what the SS field value should be...
883 static const unsigned SSTable[] = {~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3};
884 unsigned SS = SSTable[Scale.getImm()];
885
886 unsigned IndexRegNo = IndexReg.getReg() ? getX86RegNum(MO: IndexReg) : 4;
887
888 emitSIBByte(SS, Index: IndexRegNo, Base: BaseRegNo, CB);
889
890 // Do we need to output a displacement?
891 if (ForceDisp8)
892 emitImmediate(DispOp: Disp, Loc: MI.getLoc(), Size: 1, FixupKind: FK_Data_1, StartByte, CB, Fixups,
893 ImmOffset);
894 else if (ForceDisp32)
895 emitImmediate(DispOp: Disp, Loc: MI.getLoc(), Size: 4, FixupKind: MCFixupKind(X86::reloc_signed_4byte),
896 StartByte, CB, Fixups);
897}
898
899/// Emit all instruction prefixes.
900///
901/// \returns one of the REX, XOP, VEX2, VEX3, EVEX if any of them is used,
902/// otherwise returns None.
903PrefixKind X86MCCodeEmitter::emitPrefixImpl(unsigned &CurOp, const MCInst &MI,
904 const MCSubtargetInfo &STI,
905 SmallVectorImpl<char> &CB) const {
906 uint64_t TSFlags = MCII.get(Opcode: MI.getOpcode()).TSFlags;
907 // Determine where the memory operand starts, if present.
908 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags);
909 // Emit segment override opcode prefix as needed.
910 if (MemoryOperand != -1) {
911 MemoryOperand += CurOp;
912 emitSegmentOverridePrefix(SegOperand: MemoryOperand + X86::AddrSegmentReg, MI, CB);
913 }
914
915 // Emit the repeat opcode prefix as needed.
916 unsigned Flags = MI.getFlags();
917 if (TSFlags & X86II::REP || Flags & X86::IP_HAS_REPEAT)
918 emitByte(C: 0xF3, CB);
919 if (Flags & X86::IP_HAS_REPEAT_NE)
920 emitByte(C: 0xF2, CB);
921
922 // Emit the address size opcode prefix as needed.
923 if (X86_MC::needsAddressSizeOverride(MI, STI, MemoryOperand, TSFlags) ||
924 Flags & X86::IP_HAS_AD_SIZE)
925 emitByte(C: 0x67, CB);
926
927 uint64_t Form = TSFlags & X86II::FormMask;
928 switch (Form) {
929 default:
930 break;
931 case X86II::RawFrmDstSrc: {
932 // Emit segment override opcode prefix as needed (not for %ds).
933 if (MI.getOperand(i: 2).getReg() != X86::DS)
934 emitSegmentOverridePrefix(SegOperand: 2, MI, CB);
935 CurOp += 3; // Consume operands.
936 break;
937 }
938 case X86II::RawFrmSrc: {
939 // Emit segment override opcode prefix as needed (not for %ds).
940 if (MI.getOperand(i: 1).getReg() != X86::DS)
941 emitSegmentOverridePrefix(SegOperand: 1, MI, CB);
942 CurOp += 2; // Consume operands.
943 break;
944 }
945 case X86II::RawFrmDst: {
946 ++CurOp; // Consume operand.
947 break;
948 }
949 case X86II::RawFrmMemOffs: {
950 // Emit segment override opcode prefix as needed.
951 emitSegmentOverridePrefix(SegOperand: 1, MI, CB);
952 break;
953 }
954 }
955
956 // REX prefix is optional, but if used must be immediately before the opcode
957 // Encoding type for this instruction.
958 return (TSFlags & X86II::EncodingMask)
959 ? emitVEXOpcodePrefix(MemOperand: MemoryOperand, MI, STI, CB)
960 : emitOpcodePrefix(MemOperand: MemoryOperand, MI, STI, CB);
961}
962
963// AVX instructions are encoded using an encoding scheme that combines
964// prefix bytes, opcode extension field, operand encoding fields, and vector
965// length encoding capability into a new prefix, referred to as VEX.
966
967// The majority of the AVX-512 family of instructions (operating on
968// 512/256/128-bit vector register operands) are encoded using a new prefix
969// (called EVEX).
970
971// XOP is a revised subset of what was originally intended as SSE5. It was
972// changed to be similar but not overlapping with AVX.
973
974/// Emit XOP, VEX2, VEX3 or EVEX prefix.
975/// \returns the used prefix.
976PrefixKind
977X86MCCodeEmitter::emitVEXOpcodePrefix(int MemOperand, const MCInst &MI,
978 const MCSubtargetInfo &STI,
979 SmallVectorImpl<char> &CB) const {
980 const MCInstrDesc &Desc = MCII.get(Opcode: MI.getOpcode());
981 uint64_t TSFlags = Desc.TSFlags;
982
983 assert(!(TSFlags & X86II::LOCK) && "Can't have LOCK VEX.");
984
985#ifndef NDEBUG
986 unsigned NumOps = MI.getNumOperands();
987 for (unsigned I = NumOps ? X86II::getOperandBias(Desc) : 0; I != NumOps;
988 ++I) {
989 const MCOperand &MO = MI.getOperand(I);
990 if (!MO.isReg())
991 continue;
992 MCRegister Reg = MO.getReg();
993 if (Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH)
994 report_fatal_error(
995 "Cannot encode high byte register in VEX/EVEX-prefixed instruction");
996 }
997#endif
998
999 X86OpcodePrefixHelper Prefix(*Ctx.getRegisterInfo());
1000 switch (TSFlags & X86II::EncodingMask) {
1001 default:
1002 break;
1003 case X86II::XOP:
1004 Prefix.setLowerBound(XOP);
1005 break;
1006 case X86II::VEX:
1007 // VEX can be 2 byte or 3 byte, not determined yet if not explicit
1008 Prefix.setLowerBound((MI.getFlags() & X86::IP_USE_VEX3) ? VEX3 : VEX2);
1009 break;
1010 case X86II::EVEX:
1011 Prefix.setLowerBound(EVEX);
1012 break;
1013 }
1014
1015 Prefix.setW(TSFlags & X86II::REX_W);
1016 Prefix.setNF(TSFlags & X86II::EVEX_NF);
1017
1018 bool HasEVEX_K = TSFlags & X86II::EVEX_K;
1019 bool HasVEX_4V = TSFlags & X86II::VEX_4V;
1020 bool IsND = X86II::hasNewDataDest(TSFlags); // IsND implies HasVEX_4V
1021 bool HasEVEX_RC = TSFlags & X86II::EVEX_RC;
1022
1023 switch (TSFlags & X86II::OpMapMask) {
1024 default:
1025 llvm_unreachable("Invalid prefix!");
1026 case X86II::TB:
1027 Prefix.set5M(0x1); // 0F
1028 break;
1029 case X86II::T8:
1030 Prefix.set5M(0x2); // 0F 38
1031 break;
1032 case X86II::TA:
1033 Prefix.set5M(0x3); // 0F 3A
1034 break;
1035 case X86II::XOP8:
1036 Prefix.set5M(0x8);
1037 break;
1038 case X86II::XOP9:
1039 Prefix.set5M(0x9);
1040 break;
1041 case X86II::XOPA:
1042 Prefix.set5M(0xA);
1043 break;
1044 case X86II::T_MAP4:
1045 Prefix.set5M(0x4);
1046 break;
1047 case X86II::T_MAP5:
1048 Prefix.set5M(0x5);
1049 break;
1050 case X86II::T_MAP6:
1051 Prefix.set5M(0x6);
1052 break;
1053 case X86II::T_MAP7:
1054 Prefix.set5M(0x7);
1055 break;
1056 }
1057
1058 Prefix.setL(TSFlags & X86II::VEX_L);
1059 Prefix.setL2(TSFlags & X86II::EVEX_L2);
1060 if ((TSFlags & X86II::EVEX_L2) && STI.hasFeature(Feature: X86::FeatureAVX512) &&
1061 !STI.hasFeature(Feature: X86::FeatureEVEX512))
1062 report_fatal_error(reason: "ZMM registers are not supported without EVEX512");
1063 switch (TSFlags & X86II::OpPrefixMask) {
1064 case X86II::PD:
1065 Prefix.setPP(0x1); // 66
1066 break;
1067 case X86II::XS:
1068 Prefix.setPP(0x2); // F3
1069 break;
1070 case X86II::XD:
1071 Prefix.setPP(0x3); // F2
1072 break;
1073 }
1074
1075 Prefix.setZ(HasEVEX_K && (TSFlags & X86II::EVEX_Z));
1076 Prefix.setEVEX_b(TSFlags & X86II::EVEX_B);
1077 Prefix.setEVEX_U(TSFlags & X86II::EVEX_U);
1078
1079 bool EncodeRC = false;
1080 uint8_t EVEX_rc = 0;
1081
1082 unsigned CurOp = X86II::getOperandBias(Desc);
1083 bool HasTwoConditionalOps = TSFlags & X86II::TwoConditionalOps;
1084
1085 switch (TSFlags & X86II::FormMask) {
1086 default:
1087 llvm_unreachable("Unexpected form in emitVEXOpcodePrefix!");
1088 case X86II::MRMDestMem4VOp3CC: {
1089 // src1(ModR/M), MemAddr, src2(VEX_4V)
1090 Prefix.setRR2(MI, OpNum: CurOp++);
1091 Prefix.setBB2(MI, OpNum: MemOperand + X86::AddrBaseReg);
1092 Prefix.setXX2(MI, OpNum: MemOperand + X86::AddrIndexReg);
1093 CurOp += X86::AddrNumOperands;
1094 Prefix.set4VV2(MI, OpNum: CurOp++);
1095 break;
1096 }
1097 case X86II::MRM_C0:
1098 case X86II::RawFrm:
1099 break;
1100 case X86II::MRMDestMemCC:
1101 case X86II::MRMDestMemFSIB:
1102 case X86II::MRMDestMem: {
1103 // MRMDestMem instructions forms:
1104 // MemAddr, src1(ModR/M)
1105 // MemAddr, src1(VEX_4V), src2(ModR/M)
1106 // MemAddr, src1(ModR/M), imm8
1107 //
1108 // NDD:
1109 // dst(VEX_4V), MemAddr, src1(ModR/M)
1110 Prefix.setBB2(MI, OpNum: MemOperand + X86::AddrBaseReg);
1111 Prefix.setXX2(MI, OpNum: MemOperand + X86::AddrIndexReg);
1112 Prefix.setV2(MI, OpNum: MemOperand + X86::AddrIndexReg, HasVEX_4V);
1113
1114 if (IsND)
1115 Prefix.set4VV2(MI, OpNum: CurOp++);
1116
1117 CurOp += X86::AddrNumOperands;
1118
1119 if (HasEVEX_K)
1120 Prefix.setAAA(MI, OpNum: CurOp++);
1121
1122 if (!IsND && HasVEX_4V)
1123 Prefix.set4VV2(MI, OpNum: CurOp++);
1124
1125 Prefix.setRR2(MI, OpNum: CurOp++);
1126 if (HasTwoConditionalOps) {
1127 Prefix.set4V(MI, OpNum: CurOp++, /*IsImm=*/true);
1128 Prefix.setSC(MI, OpNum: CurOp++);
1129 }
1130 break;
1131 }
1132 case X86II::MRMSrcMemCC:
1133 case X86II::MRMSrcMemFSIB:
1134 case X86II::MRMSrcMem: {
1135 // MRMSrcMem instructions forms:
1136 // src1(ModR/M), MemAddr
1137 // src1(ModR/M), src2(VEX_4V), MemAddr
1138 // src1(ModR/M), MemAddr, imm8
1139 // src1(ModR/M), MemAddr, src2(Imm[7:4])
1140 //
1141 // FMA4:
1142 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(Imm[7:4])
1143 //
1144 // NDD:
1145 // dst(VEX_4V), src1(ModR/M), MemAddr
1146 if (IsND)
1147 Prefix.set4VV2(MI, OpNum: CurOp++);
1148
1149 Prefix.setRR2(MI, OpNum: CurOp++);
1150
1151 if (HasEVEX_K)
1152 Prefix.setAAA(MI, OpNum: CurOp++);
1153
1154 if (!IsND && HasVEX_4V)
1155 Prefix.set4VV2(MI, OpNum: CurOp++);
1156
1157 Prefix.setBB2(MI, OpNum: MemOperand + X86::AddrBaseReg);
1158 Prefix.setXX2(MI, OpNum: MemOperand + X86::AddrIndexReg);
1159 Prefix.setV2(MI, OpNum: MemOperand + X86::AddrIndexReg, HasVEX_4V);
1160 CurOp += X86::AddrNumOperands;
1161 if (HasTwoConditionalOps) {
1162 Prefix.set4V(MI, OpNum: CurOp++, /*IsImm=*/true);
1163 Prefix.setSC(MI, OpNum: CurOp++);
1164 }
1165 break;
1166 }
1167 case X86II::MRMSrcMem4VOp3: {
1168 // Instruction format for 4VOp3:
1169 // src1(ModR/M), MemAddr, src3(VEX_4V)
1170 Prefix.setRR2(MI, OpNum: CurOp++);
1171 Prefix.setBB2(MI, OpNum: MemOperand + X86::AddrBaseReg);
1172 Prefix.setXX2(MI, OpNum: MemOperand + X86::AddrIndexReg);
1173 Prefix.set4VV2(MI, OpNum: CurOp + X86::AddrNumOperands);
1174 break;
1175 }
1176 case X86II::MRMSrcMemOp4: {
1177 // dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M),
1178 Prefix.setR(MI, OpNum: CurOp++);
1179 Prefix.set4V(MI, OpNum: CurOp++);
1180 Prefix.setBB2(MI, OpNum: MemOperand + X86::AddrBaseReg);
1181 Prefix.setXX2(MI, OpNum: MemOperand + X86::AddrIndexReg);
1182 break;
1183 }
1184 case X86II::MRMXmCC:
1185 case X86II::MRM0m:
1186 case X86II::MRM1m:
1187 case X86II::MRM2m:
1188 case X86II::MRM3m:
1189 case X86II::MRM4m:
1190 case X86II::MRM5m:
1191 case X86II::MRM6m:
1192 case X86II::MRM7m: {
1193 // MRM[0-9]m instructions forms:
1194 // MemAddr
1195 // src1(VEX_4V), MemAddr
1196 if (HasVEX_4V)
1197 Prefix.set4VV2(MI, OpNum: CurOp++);
1198
1199 if (HasEVEX_K)
1200 Prefix.setAAA(MI, OpNum: CurOp++);
1201
1202 Prefix.setBB2(MI, OpNum: MemOperand + X86::AddrBaseReg);
1203 Prefix.setXX2(MI, OpNum: MemOperand + X86::AddrIndexReg);
1204 Prefix.setV2(MI, OpNum: MemOperand + X86::AddrIndexReg, HasVEX_4V);
1205 CurOp += X86::AddrNumOperands + 1; // Skip first imm.
1206 if (HasTwoConditionalOps) {
1207 Prefix.set4V(MI, OpNum: CurOp++, /*IsImm=*/true);
1208 Prefix.setSC(MI, OpNum: CurOp++);
1209 }
1210 break;
1211 }
1212 case X86II::MRMSrcRegCC:
1213 case X86II::MRMSrcReg: {
1214 // MRMSrcReg instructions forms:
1215 // dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(Imm[7:4])
1216 // dst(ModR/M), src1(ModR/M)
1217 // dst(ModR/M), src1(ModR/M), imm8
1218 //
1219 // FMA4:
1220 // dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M),
1221 //
1222 // NDD:
1223 // dst(VEX_4V), src1(ModR/M.reg), src2(ModR/M)
1224 if (IsND)
1225 Prefix.set4VV2(MI, OpNum: CurOp++);
1226 Prefix.setRR2(MI, OpNum: CurOp++);
1227
1228 if (HasEVEX_K)
1229 Prefix.setAAA(MI, OpNum: CurOp++);
1230
1231 if (!IsND && HasVEX_4V)
1232 Prefix.set4VV2(MI, OpNum: CurOp++);
1233
1234 Prefix.setBB2(MI, OpNum: CurOp);
1235 Prefix.setX(MI, OpNum: CurOp, Shift: 4);
1236 ++CurOp;
1237
1238 if (HasTwoConditionalOps) {
1239 Prefix.set4V(MI, OpNum: CurOp++, /*IsImm=*/true);
1240 Prefix.setSC(MI, OpNum: CurOp++);
1241 }
1242
1243 if (TSFlags & X86II::EVEX_B) {
1244 if (HasEVEX_RC) {
1245 unsigned NumOps = Desc.getNumOperands();
1246 unsigned RcOperand = NumOps - 1;
1247 assert(RcOperand >= CurOp);
1248 EVEX_rc = MI.getOperand(i: RcOperand).getImm();
1249 assert(EVEX_rc <= 3 && "Invalid rounding control!");
1250 }
1251 EncodeRC = true;
1252 }
1253 break;
1254 }
1255 case X86II::MRMSrcReg4VOp3: {
1256 // Instruction format for 4VOp3:
1257 // src1(ModR/M), src2(ModR/M), src3(VEX_4V)
1258 Prefix.setRR2(MI, OpNum: CurOp++);
1259 Prefix.setBB2(MI, OpNum: CurOp++);
1260 Prefix.set4VV2(MI, OpNum: CurOp++);
1261 break;
1262 }
1263 case X86II::MRMSrcRegOp4: {
1264 // dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M),
1265 Prefix.setR(MI, OpNum: CurOp++);
1266 Prefix.set4V(MI, OpNum: CurOp++);
1267 // Skip second register source (encoded in Imm[7:4])
1268 ++CurOp;
1269
1270 Prefix.setB(MI, OpNum: CurOp);
1271 Prefix.setX(MI, OpNum: CurOp, Shift: 4);
1272 ++CurOp;
1273 break;
1274 }
1275 case X86II::MRMDestRegCC:
1276 case X86II::MRMDestReg: {
1277 // MRMDestReg instructions forms:
1278 // dst(ModR/M), src(ModR/M)
1279 // dst(ModR/M), src(ModR/M), imm8
1280 // dst(ModR/M), src1(VEX_4V), src2(ModR/M)
1281 //
1282 // NDD:
1283 // dst(VEX_4V), src1(ModR/M), src2(ModR/M)
1284 if (IsND)
1285 Prefix.set4VV2(MI, OpNum: CurOp++);
1286 Prefix.setBB2(MI, OpNum: CurOp);
1287 Prefix.setX(MI, OpNum: CurOp, Shift: 4);
1288 ++CurOp;
1289
1290 if (HasEVEX_K)
1291 Prefix.setAAA(MI, OpNum: CurOp++);
1292
1293 if (!IsND && HasVEX_4V)
1294 Prefix.set4VV2(MI, OpNum: CurOp++);
1295
1296 Prefix.setRR2(MI, OpNum: CurOp++);
1297 if (HasTwoConditionalOps) {
1298 Prefix.set4V(MI, OpNum: CurOp++, /*IsImm=*/true);
1299 Prefix.setSC(MI, OpNum: CurOp++);
1300 }
1301 if (TSFlags & X86II::EVEX_B)
1302 EncodeRC = true;
1303 break;
1304 }
1305 case X86II::MRMr0: {
1306 // MRMr0 instructions forms:
1307 // 11:rrr:000
1308 // dst(ModR/M)
1309 Prefix.setRR2(MI, OpNum: CurOp++);
1310 break;
1311 }
1312 case X86II::MRMXrCC:
1313 case X86II::MRM0r:
1314 case X86II::MRM1r:
1315 case X86II::MRM2r:
1316 case X86II::MRM3r:
1317 case X86II::MRM4r:
1318 case X86II::MRM5r:
1319 case X86II::MRM6r:
1320 case X86II::MRM7r: {
1321 // MRM0r-MRM7r instructions forms:
1322 // dst(VEX_4V), src(ModR/M), imm8
1323 if (HasVEX_4V)
1324 Prefix.set4VV2(MI, OpNum: CurOp++);
1325
1326 if (HasEVEX_K)
1327 Prefix.setAAA(MI, OpNum: CurOp++);
1328
1329 Prefix.setBB2(MI, OpNum: CurOp);
1330 Prefix.setX(MI, OpNum: CurOp, Shift: 4);
1331 ++CurOp;
1332 if (HasTwoConditionalOps) {
1333 Prefix.set4V(MI, OpNum: ++CurOp, /*IsImm=*/true);
1334 Prefix.setSC(MI, OpNum: ++CurOp);
1335 }
1336 break;
1337 }
1338 }
1339 if (EncodeRC) {
1340 Prefix.setL(EVEX_rc & 0x1);
1341 Prefix.setL2(EVEX_rc & 0x2);
1342 }
1343 PrefixKind Kind = Prefix.determineOptimalKind();
1344 Prefix.emit(CB);
1345 return Kind;
1346}
1347
1348/// Emit REX prefix which specifies
1349/// 1) 64-bit instructions,
1350/// 2) non-default operand size, and
1351/// 3) use of X86-64 extended registers.
1352///
1353/// \returns the used prefix (REX or None).
1354PrefixKind X86MCCodeEmitter::emitREXPrefix(int MemOperand, const MCInst &MI,
1355 const MCSubtargetInfo &STI,
1356 SmallVectorImpl<char> &CB) const {
1357 if (!STI.hasFeature(Feature: X86::Is64Bit))
1358 return None;
1359 X86OpcodePrefixHelper Prefix(*Ctx.getRegisterInfo());
1360 const MCInstrDesc &Desc = MCII.get(Opcode: MI.getOpcode());
1361 uint64_t TSFlags = Desc.TSFlags;
1362 Prefix.setW(TSFlags & X86II::REX_W);
1363 unsigned NumOps = MI.getNumOperands();
1364 bool UsesHighByteReg = false;
1365#ifndef NDEBUG
1366 bool HasRegOp = false;
1367#endif
1368 unsigned CurOp = NumOps ? X86II::getOperandBias(Desc) : 0;
1369 for (unsigned i = CurOp; i != NumOps; ++i) {
1370 const MCOperand &MO = MI.getOperand(i);
1371 if (MO.isReg()) {
1372#ifndef NDEBUG
1373 HasRegOp = true;
1374#endif
1375 MCRegister Reg = MO.getReg();
1376 if (Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH)
1377 UsesHighByteReg = true;
1378 // If it accesses SPL, BPL, SIL, or DIL, then it requires a REX prefix.
1379 if (X86II::isX86_64NonExtLowByteReg(Reg))
1380 Prefix.setLowerBound(REX);
1381 } else if (MO.isExpr() && STI.getTargetTriple().isX32()) {
1382 // GOTTPOFF and TLSDESC relocations require a REX prefix to allow
1383 // linker optimizations: even if the instructions we see may not require
1384 // any prefix, they may be replaced by instructions that do. This is
1385 // handled as a special case here so that it also works for hand-written
1386 // assembly without the user needing to write REX, as with GNU as.
1387 const auto *Ref = dyn_cast<MCSymbolRefExpr>(Val: MO.getExpr());
1388 if (Ref && (Ref->getSpecifier() == X86::S_GOTTPOFF ||
1389 Ref->getSpecifier() == X86::S_TLSDESC)) {
1390 Prefix.setLowerBound(REX);
1391 }
1392 }
1393 }
1394 if (MI.getFlags() & X86::IP_USE_REX)
1395 Prefix.setLowerBound(REX);
1396 if ((TSFlags & X86II::ExplicitOpPrefixMask) == X86II::ExplicitREX2Prefix ||
1397 MI.getFlags() & X86::IP_USE_REX2)
1398 Prefix.setLowerBound(REX2);
1399 switch (TSFlags & X86II::FormMask) {
1400 default:
1401 assert(!HasRegOp && "Unexpected form in emitREXPrefix!");
1402 break;
1403 case X86II::RawFrm:
1404 case X86II::RawFrmMemOffs:
1405 case X86II::RawFrmSrc:
1406 case X86II::RawFrmDst:
1407 case X86II::RawFrmDstSrc:
1408 break;
1409 case X86II::AddRegFrm:
1410 Prefix.setBB2(MI, OpNum: CurOp++);
1411 break;
1412 case X86II::MRMSrcReg:
1413 case X86II::MRMSrcRegCC:
1414 Prefix.setRR2(MI, OpNum: CurOp++);
1415 Prefix.setBB2(MI, OpNum: CurOp++);
1416 break;
1417 case X86II::MRMSrcMem:
1418 case X86II::MRMSrcMemCC:
1419 Prefix.setRR2(MI, OpNum: CurOp++);
1420 Prefix.setBB2(MI, OpNum: MemOperand + X86::AddrBaseReg);
1421 Prefix.setXX2(MI, OpNum: MemOperand + X86::AddrIndexReg);
1422 CurOp += X86::AddrNumOperands;
1423 break;
1424 case X86II::MRMDestReg:
1425 Prefix.setBB2(MI, OpNum: CurOp++);
1426 Prefix.setRR2(MI, OpNum: CurOp++);
1427 break;
1428 case X86II::MRMDestMem:
1429 Prefix.setBB2(MI, OpNum: MemOperand + X86::AddrBaseReg);
1430 Prefix.setXX2(MI, OpNum: MemOperand + X86::AddrIndexReg);
1431 CurOp += X86::AddrNumOperands;
1432 Prefix.setRR2(MI, OpNum: CurOp++);
1433 break;
1434 case X86II::MRMXmCC:
1435 case X86II::MRMXm:
1436 case X86II::MRM0m:
1437 case X86II::MRM1m:
1438 case X86II::MRM2m:
1439 case X86II::MRM3m:
1440 case X86II::MRM4m:
1441 case X86II::MRM5m:
1442 case X86II::MRM6m:
1443 case X86II::MRM7m:
1444 Prefix.setBB2(MI, OpNum: MemOperand + X86::AddrBaseReg);
1445 Prefix.setXX2(MI, OpNum: MemOperand + X86::AddrIndexReg);
1446 break;
1447 case X86II::MRMXrCC:
1448 case X86II::MRMXr:
1449 case X86II::MRM0r:
1450 case X86II::MRM1r:
1451 case X86II::MRM2r:
1452 case X86II::MRM3r:
1453 case X86II::MRM4r:
1454 case X86II::MRM5r:
1455 case X86II::MRM6r:
1456 case X86II::MRM7r:
1457 Prefix.setBB2(MI, OpNum: CurOp++);
1458 break;
1459 }
1460 Prefix.setM((TSFlags & X86II::OpMapMask) == X86II::TB);
1461 PrefixKind Kind = Prefix.determineOptimalKind();
1462 if (Kind && UsesHighByteReg)
1463 report_fatal_error(
1464 reason: "Cannot encode high byte register in REX-prefixed instruction");
1465 Prefix.emit(CB);
1466 return Kind;
1467}
1468
1469/// Emit segment override opcode prefix as needed.
1470void X86MCCodeEmitter::emitSegmentOverridePrefix(
1471 unsigned SegOperand, const MCInst &MI, SmallVectorImpl<char> &CB) const {
1472 // Check for explicit segment override on memory operand.
1473 if (MCRegister Reg = MI.getOperand(i: SegOperand).getReg())
1474 emitByte(C: X86::getSegmentOverridePrefixForReg(Reg), CB);
1475}
1476
1477/// Emit all instruction prefixes prior to the opcode.
1478///
1479/// \param MemOperand the operand # of the start of a memory operand if present.
1480/// If not present, it is -1.
1481///
1482/// \returns the used prefix (REX or None).
1483PrefixKind X86MCCodeEmitter::emitOpcodePrefix(int MemOperand, const MCInst &MI,
1484 const MCSubtargetInfo &STI,
1485 SmallVectorImpl<char> &CB) const {
1486 const MCInstrDesc &Desc = MCII.get(Opcode: MI.getOpcode());
1487 uint64_t TSFlags = Desc.TSFlags;
1488
1489 // Emit the operand size opcode prefix as needed.
1490 if ((TSFlags & X86II::OpSizeMask) ==
1491 (STI.hasFeature(Feature: X86::Is16Bit) ? X86II::OpSize32 : X86II::OpSize16))
1492 emitByte(C: 0x66, CB);
1493
1494 // Emit the LOCK opcode prefix.
1495 if (TSFlags & X86II::LOCK || MI.getFlags() & X86::IP_HAS_LOCK)
1496 emitByte(C: 0xF0, CB);
1497
1498 // Emit the NOTRACK opcode prefix.
1499 if (TSFlags & X86II::NOTRACK || MI.getFlags() & X86::IP_HAS_NOTRACK)
1500 emitByte(C: 0x3E, CB);
1501
1502 switch (TSFlags & X86II::OpPrefixMask) {
1503 case X86II::PD: // 66
1504 emitByte(C: 0x66, CB);
1505 break;
1506 case X86II::XS: // F3
1507 emitByte(C: 0xF3, CB);
1508 break;
1509 case X86II::XD: // F2
1510 emitByte(C: 0xF2, CB);
1511 break;
1512 }
1513
1514 // Handle REX prefix.
1515 assert((STI.hasFeature(X86::Is64Bit) || !(TSFlags & X86II::REX_W)) &&
1516 "REX.W requires 64bit mode.");
1517 PrefixKind Kind = emitREXPrefix(MemOperand, MI, STI, CB);
1518
1519 // 0x0F escape code must be emitted just before the opcode.
1520 switch (TSFlags & X86II::OpMapMask) {
1521 case X86II::TB: // Two-byte opcode map
1522 // Encoded by M bit in REX2
1523 if (Kind == REX2)
1524 break;
1525 [[fallthrough]];
1526 case X86II::T8: // 0F 38
1527 case X86II::TA: // 0F 3A
1528 case X86II::ThreeDNow: // 0F 0F, second 0F emitted by caller.
1529 emitByte(C: 0x0F, CB);
1530 break;
1531 }
1532
1533 switch (TSFlags & X86II::OpMapMask) {
1534 case X86II::T8: // 0F 38
1535 emitByte(C: 0x38, CB);
1536 break;
1537 case X86II::TA: // 0F 3A
1538 emitByte(C: 0x3A, CB);
1539 break;
1540 }
1541
1542 return Kind;
1543}
1544
1545void X86MCCodeEmitter::emitPrefix(const MCInst &MI, SmallVectorImpl<char> &CB,
1546 const MCSubtargetInfo &STI) const {
1547 unsigned Opcode = MI.getOpcode();
1548 const MCInstrDesc &Desc = MCII.get(Opcode);
1549 uint64_t TSFlags = Desc.TSFlags;
1550
1551 // Pseudo instructions don't get encoded.
1552 if (X86II::isPseudo(TSFlags))
1553 return;
1554
1555 unsigned CurOp = X86II::getOperandBias(Desc);
1556
1557 emitPrefixImpl(CurOp, MI, STI, CB);
1558}
1559
1560void X86_MC::emitPrefix(MCCodeEmitter &MCE, const MCInst &MI,
1561 SmallVectorImpl<char> &CB, const MCSubtargetInfo &STI) {
1562 static_cast<X86MCCodeEmitter &>(MCE).emitPrefix(MI, CB, STI);
1563}
1564
1565void X86MCCodeEmitter::encodeInstruction(const MCInst &MI,
1566 SmallVectorImpl<char> &CB,
1567 SmallVectorImpl<MCFixup> &Fixups,
1568 const MCSubtargetInfo &STI) const {
1569 unsigned Opcode = MI.getOpcode();
1570 const MCInstrDesc &Desc = MCII.get(Opcode);
1571 uint64_t TSFlags = Desc.TSFlags;
1572
1573 // Pseudo instructions don't get encoded.
1574 if (X86II::isPseudo(TSFlags))
1575 return;
1576
1577 unsigned NumOps = Desc.getNumOperands();
1578 unsigned CurOp = X86II::getOperandBias(Desc);
1579
1580 uint64_t StartByte = CB.size();
1581
1582 PrefixKind Kind = emitPrefixImpl(CurOp, MI, STI, CB);
1583
1584 // It uses the VEX.VVVV field?
1585 bool HasVEX_4V = TSFlags & X86II::VEX_4V;
1586 bool HasVEX_I8Reg = (TSFlags & X86II::ImmMask) == X86II::Imm8Reg;
1587
1588 // It uses the EVEX.aaa field?
1589 bool HasEVEX_K = TSFlags & X86II::EVEX_K;
1590 bool HasEVEX_RC = TSFlags & X86II::EVEX_RC;
1591
1592 // Used if a register is encoded in 7:4 of immediate.
1593 unsigned I8RegNum = 0;
1594
1595 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
1596
1597 if ((TSFlags & X86II::OpMapMask) == X86II::ThreeDNow)
1598 BaseOpcode = 0x0F; // Weird 3DNow! encoding.
1599
1600 unsigned OpcodeOffset = 0;
1601
1602 bool IsND = X86II::hasNewDataDest(TSFlags);
1603 bool HasTwoConditionalOps = TSFlags & X86II::TwoConditionalOps;
1604
1605 uint64_t Form = TSFlags & X86II::FormMask;
1606 switch (Form) {
1607 default:
1608 errs() << "FORM: " << Form << "\n";
1609 llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!");
1610 case X86II::Pseudo:
1611 llvm_unreachable("Pseudo instruction shouldn't be emitted");
1612 case X86II::RawFrmDstSrc:
1613 case X86II::RawFrmSrc:
1614 case X86II::RawFrmDst:
1615 case X86II::PrefixByte:
1616 emitByte(C: BaseOpcode, CB);
1617 break;
1618 case X86II::AddCCFrm: {
1619 // This will be added to the opcode in the fallthrough.
1620 OpcodeOffset = MI.getOperand(i: NumOps - 1).getImm();
1621 assert(OpcodeOffset < 16 && "Unexpected opcode offset!");
1622 --NumOps; // Drop the operand from the end.
1623 [[fallthrough]];
1624 case X86II::RawFrm:
1625 emitByte(C: BaseOpcode + OpcodeOffset, CB);
1626
1627 if (!STI.hasFeature(Feature: X86::Is64Bit) || !isPCRel32Branch(MI, MCII))
1628 break;
1629
1630 const MCOperand &Op = MI.getOperand(i: CurOp++);
1631 emitImmediate(DispOp: Op, Loc: MI.getLoc(), Size: X86II::getSizeOfImm(TSFlags),
1632 FixupKind: MCFixupKind(X86::reloc_branch_4byte_pcrel), StartByte, CB,
1633 Fixups);
1634 break;
1635 }
1636 case X86II::RawFrmMemOffs:
1637 emitByte(C: BaseOpcode, CB);
1638 emitImmediate(DispOp: MI.getOperand(i: CurOp++), Loc: MI.getLoc(),
1639 Size: X86II::getSizeOfImm(TSFlags), FixupKind: getImmFixupKind(TSFlags),
1640 StartByte, CB, Fixups);
1641 ++CurOp; // skip segment operand
1642 break;
1643 case X86II::RawFrmImm8:
1644 emitByte(C: BaseOpcode, CB);
1645 emitImmediate(DispOp: MI.getOperand(i: CurOp++), Loc: MI.getLoc(),
1646 Size: X86II::getSizeOfImm(TSFlags), FixupKind: getImmFixupKind(TSFlags),
1647 StartByte, CB, Fixups);
1648 emitImmediate(DispOp: MI.getOperand(i: CurOp++), Loc: MI.getLoc(), Size: 1, FixupKind: FK_Data_1, StartByte,
1649 CB, Fixups);
1650 break;
1651 case X86II::RawFrmImm16:
1652 emitByte(C: BaseOpcode, CB);
1653 emitImmediate(DispOp: MI.getOperand(i: CurOp++), Loc: MI.getLoc(),
1654 Size: X86II::getSizeOfImm(TSFlags), FixupKind: getImmFixupKind(TSFlags),
1655 StartByte, CB, Fixups);
1656 emitImmediate(DispOp: MI.getOperand(i: CurOp++), Loc: MI.getLoc(), Size: 2, FixupKind: FK_Data_2, StartByte,
1657 CB, Fixups);
1658 break;
1659
1660 case X86II::AddRegFrm:
1661 emitByte(C: BaseOpcode + getX86RegNum(MO: MI.getOperand(i: CurOp++)), CB);
1662 break;
1663
1664 case X86II::MRMDestReg: {
1665 emitByte(C: BaseOpcode, CB);
1666 unsigned SrcRegNum = CurOp + 1;
1667
1668 if (HasEVEX_K) // Skip writemask
1669 ++SrcRegNum;
1670
1671 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1672 ++SrcRegNum;
1673 if (IsND) // Skip the NDD operand encoded in EVEX_VVVV
1674 ++CurOp;
1675
1676 emitRegModRMByte(ModRMReg: MI.getOperand(i: CurOp),
1677 RegOpcodeFld: getX86RegNum(MO: MI.getOperand(i: SrcRegNum)), CB);
1678 CurOp = SrcRegNum + 1;
1679 break;
1680 }
1681 case X86II::MRMDestRegCC: {
1682 unsigned FirstOp = CurOp++;
1683 unsigned SecondOp = CurOp++;
1684 unsigned CC = MI.getOperand(i: CurOp++).getImm();
1685 emitByte(C: BaseOpcode + CC, CB);
1686 emitRegModRMByte(ModRMReg: MI.getOperand(i: FirstOp),
1687 RegOpcodeFld: getX86RegNum(MO: MI.getOperand(i: SecondOp)), CB);
1688 break;
1689 }
1690 case X86II::MRMDestMem4VOp3CC: {
1691 unsigned CC = MI.getOperand(i: 8).getImm();
1692 emitByte(C: BaseOpcode + CC, CB);
1693 unsigned SrcRegNum = CurOp + X86::AddrNumOperands;
1694 emitMemModRMByte(MI, Op: CurOp + 1, RegOpcodeField: getX86RegNum(MO: MI.getOperand(i: 0)), TSFlags,
1695 Kind, StartByte, CB, Fixups, STI, ForceSIB: false);
1696 CurOp = SrcRegNum + 3; // skip reg, VEX_V4 and CC
1697 break;
1698 }
1699 case X86II::MRMDestMemFSIB:
1700 case X86II::MRMDestMem: {
1701 emitByte(C: BaseOpcode, CB);
1702 unsigned SrcRegNum = CurOp + X86::AddrNumOperands;
1703
1704 if (HasEVEX_K) // Skip writemask
1705 ++SrcRegNum;
1706
1707 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1708 ++SrcRegNum;
1709
1710 if (IsND) // Skip new data destination
1711 ++CurOp;
1712
1713 bool ForceSIB = (Form == X86II::MRMDestMemFSIB);
1714 emitMemModRMByte(MI, Op: CurOp, RegOpcodeField: getX86RegNum(MO: MI.getOperand(i: SrcRegNum)), TSFlags,
1715 Kind, StartByte, CB, Fixups, STI, ForceSIB);
1716 CurOp = SrcRegNum + 1;
1717 break;
1718 }
1719 case X86II::MRMDestMemCC: {
1720 unsigned MemOp = CurOp;
1721 CurOp = MemOp + X86::AddrNumOperands;
1722 unsigned RegOp = CurOp++;
1723 unsigned CC = MI.getOperand(i: CurOp++).getImm();
1724 emitByte(C: BaseOpcode + CC, CB);
1725 emitMemModRMByte(MI, Op: MemOp, RegOpcodeField: getX86RegNum(MO: MI.getOperand(i: RegOp)), TSFlags,
1726 Kind, StartByte, CB, Fixups, STI);
1727 break;
1728 }
1729 case X86II::MRMSrcReg: {
1730 emitByte(C: BaseOpcode, CB);
1731 unsigned SrcRegNum = CurOp + 1;
1732
1733 if (HasEVEX_K) // Skip writemask
1734 ++SrcRegNum;
1735
1736 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
1737 ++SrcRegNum;
1738
1739 if (IsND) // Skip new data destination
1740 ++CurOp;
1741
1742 emitRegModRMByte(ModRMReg: MI.getOperand(i: SrcRegNum),
1743 RegOpcodeFld: getX86RegNum(MO: MI.getOperand(i: CurOp)), CB);
1744 CurOp = SrcRegNum + 1;
1745 if (HasVEX_I8Reg)
1746 I8RegNum = getX86RegEncoding(MI, OpNum: CurOp++);
1747 // do not count the rounding control operand
1748 if (HasEVEX_RC)
1749 --NumOps;
1750 break;
1751 }
1752 case X86II::MRMSrcReg4VOp3: {
1753 emitByte(C: BaseOpcode, CB);
1754 unsigned SrcRegNum = CurOp + 1;
1755
1756 emitRegModRMByte(ModRMReg: MI.getOperand(i: SrcRegNum),
1757 RegOpcodeFld: getX86RegNum(MO: MI.getOperand(i: CurOp)), CB);
1758 CurOp = SrcRegNum + 1;
1759 ++CurOp; // Encoded in VEX.VVVV
1760 break;
1761 }
1762 case X86II::MRMSrcRegOp4: {
1763 emitByte(C: BaseOpcode, CB);
1764 unsigned SrcRegNum = CurOp + 1;
1765
1766 // Skip 1st src (which is encoded in VEX_VVVV)
1767 ++SrcRegNum;
1768
1769 // Capture 2nd src (which is encoded in Imm[7:4])
1770 assert(HasVEX_I8Reg && "MRMSrcRegOp4 should imply VEX_I8Reg");
1771 I8RegNum = getX86RegEncoding(MI, OpNum: SrcRegNum++);
1772
1773 emitRegModRMByte(ModRMReg: MI.getOperand(i: SrcRegNum),
1774 RegOpcodeFld: getX86RegNum(MO: MI.getOperand(i: CurOp)), CB);
1775 CurOp = SrcRegNum + 1;
1776 break;
1777 }
1778 case X86II::MRMSrcRegCC: {
1779 if (IsND) // Skip new data destination
1780 ++CurOp;
1781 unsigned FirstOp = CurOp++;
1782 unsigned SecondOp = CurOp++;
1783
1784 unsigned CC = MI.getOperand(i: CurOp++).getImm();
1785 emitByte(C: BaseOpcode + CC, CB);
1786
1787 emitRegModRMByte(ModRMReg: MI.getOperand(i: SecondOp),
1788 RegOpcodeFld: getX86RegNum(MO: MI.getOperand(i: FirstOp)), CB);
1789 break;
1790 }
1791 case X86II::MRMSrcMemFSIB:
1792 case X86II::MRMSrcMem: {
1793 unsigned FirstMemOp = CurOp + 1;
1794
1795 if (IsND) // Skip new data destination
1796 CurOp++;
1797
1798 if (HasEVEX_K) // Skip writemask
1799 ++FirstMemOp;
1800
1801 if (HasVEX_4V)
1802 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
1803
1804 emitByte(C: BaseOpcode, CB);
1805
1806 bool ForceSIB = (Form == X86II::MRMSrcMemFSIB);
1807 emitMemModRMByte(MI, Op: FirstMemOp, RegOpcodeField: getX86RegNum(MO: MI.getOperand(i: CurOp)),
1808 TSFlags, Kind, StartByte, CB, Fixups, STI, ForceSIB);
1809 CurOp = FirstMemOp + X86::AddrNumOperands;
1810 if (HasVEX_I8Reg)
1811 I8RegNum = getX86RegEncoding(MI, OpNum: CurOp++);
1812 break;
1813 }
1814 case X86II::MRMSrcMem4VOp3: {
1815 unsigned FirstMemOp = CurOp + 1;
1816
1817 emitByte(C: BaseOpcode, CB);
1818
1819 emitMemModRMByte(MI, Op: FirstMemOp, RegOpcodeField: getX86RegNum(MO: MI.getOperand(i: CurOp)),
1820 TSFlags, Kind, StartByte, CB, Fixups, STI);
1821 CurOp = FirstMemOp + X86::AddrNumOperands;
1822 ++CurOp; // Encoded in VEX.VVVV.
1823 break;
1824 }
1825 case X86II::MRMSrcMemOp4: {
1826 unsigned FirstMemOp = CurOp + 1;
1827
1828 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
1829
1830 // Capture second register source (encoded in Imm[7:4])
1831 assert(HasVEX_I8Reg && "MRMSrcRegOp4 should imply VEX_I8Reg");
1832 I8RegNum = getX86RegEncoding(MI, OpNum: FirstMemOp++);
1833
1834 emitByte(C: BaseOpcode, CB);
1835
1836 emitMemModRMByte(MI, Op: FirstMemOp, RegOpcodeField: getX86RegNum(MO: MI.getOperand(i: CurOp)),
1837 TSFlags, Kind, StartByte, CB, Fixups, STI);
1838 CurOp = FirstMemOp + X86::AddrNumOperands;
1839 break;
1840 }
1841 case X86II::MRMSrcMemCC: {
1842 if (IsND) // Skip new data destination
1843 ++CurOp;
1844 unsigned RegOp = CurOp++;
1845 unsigned FirstMemOp = CurOp;
1846 CurOp = FirstMemOp + X86::AddrNumOperands;
1847
1848 unsigned CC = MI.getOperand(i: CurOp++).getImm();
1849 emitByte(C: BaseOpcode + CC, CB);
1850
1851 emitMemModRMByte(MI, Op: FirstMemOp, RegOpcodeField: getX86RegNum(MO: MI.getOperand(i: RegOp)),
1852 TSFlags, Kind, StartByte, CB, Fixups, STI);
1853 break;
1854 }
1855
1856 case X86II::MRMXrCC: {
1857 unsigned RegOp = CurOp++;
1858
1859 unsigned CC = MI.getOperand(i: CurOp++).getImm();
1860 emitByte(C: BaseOpcode + CC, CB);
1861 emitRegModRMByte(ModRMReg: MI.getOperand(i: RegOp), RegOpcodeFld: 0, CB);
1862 break;
1863 }
1864
1865 case X86II::MRMXr:
1866 case X86II::MRM0r:
1867 case X86II::MRM1r:
1868 case X86II::MRM2r:
1869 case X86II::MRM3r:
1870 case X86II::MRM4r:
1871 case X86II::MRM5r:
1872 case X86II::MRM6r:
1873 case X86II::MRM7r:
1874 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1875 ++CurOp;
1876 if (HasEVEX_K) // Skip writemask
1877 ++CurOp;
1878 emitByte(C: BaseOpcode, CB);
1879 emitRegModRMByte(ModRMReg: MI.getOperand(i: CurOp++),
1880 RegOpcodeFld: (Form == X86II::MRMXr) ? 0 : Form - X86II::MRM0r, CB);
1881 break;
1882 case X86II::MRMr0:
1883 emitByte(C: BaseOpcode, CB);
1884 emitByte(C: modRMByte(Mod: 3, RegOpcode: getX86RegNum(MO: MI.getOperand(i: CurOp++)), RM: 0), CB);
1885 break;
1886
1887 case X86II::MRMXmCC: {
1888 unsigned FirstMemOp = CurOp;
1889 CurOp = FirstMemOp + X86::AddrNumOperands;
1890
1891 unsigned CC = MI.getOperand(i: CurOp++).getImm();
1892 emitByte(C: BaseOpcode + CC, CB);
1893
1894 emitMemModRMByte(MI, Op: FirstMemOp, RegOpcodeField: 0, TSFlags, Kind, StartByte, CB, Fixups,
1895 STI);
1896 break;
1897 }
1898
1899 case X86II::MRMXm:
1900 case X86II::MRM0m:
1901 case X86II::MRM1m:
1902 case X86II::MRM2m:
1903 case X86II::MRM3m:
1904 case X86II::MRM4m:
1905 case X86II::MRM5m:
1906 case X86II::MRM6m:
1907 case X86II::MRM7m:
1908 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
1909 ++CurOp;
1910 if (HasEVEX_K) // Skip writemask
1911 ++CurOp;
1912 emitByte(C: BaseOpcode, CB);
1913 emitMemModRMByte(MI, Op: CurOp,
1914 RegOpcodeField: (Form == X86II::MRMXm) ? 0 : Form - X86II::MRM0m, TSFlags,
1915 Kind, StartByte, CB, Fixups, STI);
1916 CurOp += X86::AddrNumOperands;
1917 break;
1918
1919 case X86II::MRM0X:
1920 case X86II::MRM1X:
1921 case X86II::MRM2X:
1922 case X86II::MRM3X:
1923 case X86II::MRM4X:
1924 case X86II::MRM5X:
1925 case X86II::MRM6X:
1926 case X86II::MRM7X:
1927 emitByte(C: BaseOpcode, CB);
1928 emitByte(C: 0xC0 + ((Form - X86II::MRM0X) << 3), CB);
1929 break;
1930
1931 case X86II::MRM_C0:
1932 case X86II::MRM_C1:
1933 case X86II::MRM_C2:
1934 case X86II::MRM_C3:
1935 case X86II::MRM_C4:
1936 case X86II::MRM_C5:
1937 case X86II::MRM_C6:
1938 case X86II::MRM_C7:
1939 case X86II::MRM_C8:
1940 case X86II::MRM_C9:
1941 case X86II::MRM_CA:
1942 case X86II::MRM_CB:
1943 case X86II::MRM_CC:
1944 case X86II::MRM_CD:
1945 case X86II::MRM_CE:
1946 case X86II::MRM_CF:
1947 case X86II::MRM_D0:
1948 case X86II::MRM_D1:
1949 case X86II::MRM_D2:
1950 case X86II::MRM_D3:
1951 case X86II::MRM_D4:
1952 case X86II::MRM_D5:
1953 case X86II::MRM_D6:
1954 case X86II::MRM_D7:
1955 case X86II::MRM_D8:
1956 case X86II::MRM_D9:
1957 case X86II::MRM_DA:
1958 case X86II::MRM_DB:
1959 case X86II::MRM_DC:
1960 case X86II::MRM_DD:
1961 case X86II::MRM_DE:
1962 case X86II::MRM_DF:
1963 case X86II::MRM_E0:
1964 case X86II::MRM_E1:
1965 case X86II::MRM_E2:
1966 case X86II::MRM_E3:
1967 case X86II::MRM_E4:
1968 case X86II::MRM_E5:
1969 case X86II::MRM_E6:
1970 case X86II::MRM_E7:
1971 case X86II::MRM_E8:
1972 case X86II::MRM_E9:
1973 case X86II::MRM_EA:
1974 case X86II::MRM_EB:
1975 case X86II::MRM_EC:
1976 case X86II::MRM_ED:
1977 case X86II::MRM_EE:
1978 case X86II::MRM_EF:
1979 case X86II::MRM_F0:
1980 case X86II::MRM_F1:
1981 case X86II::MRM_F2:
1982 case X86II::MRM_F3:
1983 case X86II::MRM_F4:
1984 case X86II::MRM_F5:
1985 case X86II::MRM_F6:
1986 case X86II::MRM_F7:
1987 case X86II::MRM_F8:
1988 case X86II::MRM_F9:
1989 case X86II::MRM_FA:
1990 case X86II::MRM_FB:
1991 case X86II::MRM_FC:
1992 case X86II::MRM_FD:
1993 case X86II::MRM_FE:
1994 case X86II::MRM_FF:
1995 emitByte(C: BaseOpcode, CB);
1996 emitByte(C: 0xC0 + Form - X86II::MRM_C0, CB);
1997 break;
1998 }
1999
2000 if (HasVEX_I8Reg) {
2001 // The last source register of a 4 operand instruction in AVX is encoded
2002 // in bits[7:4] of a immediate byte.
2003 assert(I8RegNum < 16 && "Register encoding out of range");
2004 I8RegNum <<= 4;
2005 if (CurOp != NumOps) {
2006 unsigned Val = MI.getOperand(i: CurOp++).getImm();
2007 assert(Val < 16 && "Immediate operand value out of range");
2008 I8RegNum |= Val;
2009 }
2010 emitImmediate(DispOp: MCOperand::createImm(Val: I8RegNum), Loc: MI.getLoc(), Size: 1, FixupKind: FK_Data_1,
2011 StartByte, CB, Fixups);
2012 } else {
2013 // If there is a remaining operand, it must be a trailing immediate. Emit it
2014 // according to the right size for the instruction. Some instructions
2015 // (SSE4a extrq and insertq) have two trailing immediates.
2016
2017 // Skip two trainling conditional operands encoded in EVEX prefix
2018 unsigned RemaningOps = NumOps - CurOp - 2 * HasTwoConditionalOps;
2019 while (RemaningOps) {
2020 emitImmediate(DispOp: MI.getOperand(i: CurOp++), Loc: MI.getLoc(),
2021 Size: X86II::getSizeOfImm(TSFlags), FixupKind: getImmFixupKind(TSFlags),
2022 StartByte, CB, Fixups);
2023 --RemaningOps;
2024 }
2025 CurOp += 2 * HasTwoConditionalOps;
2026 }
2027
2028 if ((TSFlags & X86II::OpMapMask) == X86II::ThreeDNow)
2029 emitByte(C: X86II::getBaseOpcodeFor(TSFlags), CB);
2030
2031 if (CB.size() - StartByte > 15)
2032 Ctx.reportError(L: MI.getLoc(), Msg: "instruction length exceeds the limit of 15");
2033#ifndef NDEBUG
2034 // FIXME: Verify.
2035 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
2036 errs() << "Cannot encode all operands of: ";
2037 MI.dump();
2038 errs() << '\n';
2039 abort();
2040 }
2041#endif
2042}
2043
2044MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII,
2045 MCContext &Ctx) {
2046 return new X86MCCodeEmitter(MCII, Ctx);
2047}
2048