1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* "Fast" Instruction Selector for the Mips target *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10// FastEmit Immediate Predicate functions.
11static bool Predicate_immZExt5(int64_t Imm) {
12return Imm == (Imm & 0x1f);
13}
14static bool Predicate_immZExt6(int64_t Imm) {
15return Imm == (Imm & 0x3f);
16}
17static bool Predicate_immSExt6(int64_t Imm) {
18return isInt<6>(x: Imm);
19}
20static bool Predicate_immZExt4Ptr(int64_t Imm) {
21return isUInt<4>(x: Imm);
22}
23static bool Predicate_immZExt3Ptr(int64_t Imm) {
24return isUInt<3>(x: Imm);
25}
26static bool Predicate_immZExt2Ptr(int64_t Imm) {
27return isUInt<2>(x: Imm);
28}
29static bool Predicate_immZExt1Ptr(int64_t Imm) {
30return isUInt<1>(x: Imm);
31}
32static bool Predicate_immZExt4(int64_t Imm) {
33return isUInt<4>(x: Imm);
34}
35static bool Predicate_immSExtAddiur2(int64_t Imm) {
36return Imm == 1 || Imm == -1 ||
37 ((Imm % 4 == 0) &&
38 Imm < 28 && Imm > 0);
39}
40static bool Predicate_immSExtAddius5(int64_t Imm) {
41return Imm >= -8 && Imm <= 7;
42}
43static bool Predicate_immZExtAndi16(int64_t Imm) {
44return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
45 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
46 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
47}
48static bool Predicate_immZExt2Shift(int64_t Imm) {
49return Imm >= 1 && Imm <= 8;
50}
51
52
53// FastEmit functions for ISD::BITCAST.
54
55Register fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, Register Op0) {
56 if (RetVT.SimpleTy != MVT::f32)
57 return Register();
58 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
59 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_MMR6, RC: &Mips::FGR32RegClass, Op0);
60 }
61 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
62 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_MM, RC: &Mips::FGR32RegClass, Op0);
63 }
64 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
65 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1, RC: &Mips::FGR32RegClass, Op0);
66 }
67 return Register();
68}
69
70Register fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, Register Op0) {
71 if (RetVT.SimpleTy != MVT::f64)
72 return Register();
73 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
74 return fastEmitInst_r(MachineInstOpcode: Mips::DMTC1, RC: &Mips::FGR64RegClass, Op0);
75 }
76 return Register();
77}
78
79Register fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, Register Op0) {
80 if (RetVT.SimpleTy != MVT::i32)
81 return Register();
82 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
83 return fastEmitInst_r(MachineInstOpcode: Mips::MFC1_MMR6, RC: &Mips::GPR32RegClass, Op0);
84 }
85 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
86 return fastEmitInst_r(MachineInstOpcode: Mips::MFC1_MM, RC: &Mips::GPR32RegClass, Op0);
87 }
88 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
89 return fastEmitInst_r(MachineInstOpcode: Mips::MFC1, RC: &Mips::GPR32RegClass, Op0);
90 }
91 return Register();
92}
93
94Register fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, Register Op0) {
95 if (RetVT.SimpleTy != MVT::i64)
96 return Register();
97 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
98 return fastEmitInst_r(MachineInstOpcode: Mips::DMFC1, RC: &Mips::GPR64RegClass, Op0);
99 }
100 return Register();
101}
102
103Register fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, Register Op0) {
104 switch (VT.SimpleTy) {
105 case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0);
106 case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0);
107 case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0);
108 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0);
109 default: return Register();
110 }
111}
112
113// FastEmit functions for ISD::BRIND.
114
115Register fastEmit_ISD_BRIND_MVT_i32_r(MVT RetVT, Register Op0) {
116 if (RetVT.SimpleTy != MVT::isVoid)
117 return Register();
118 if ((Subtarget->inMips16Mode())) {
119 return fastEmitInst_r(MachineInstOpcode: Mips::JrcRx16, RC: &Mips::CPU16RegsRegClass, Op0);
120 }
121 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
122 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranch_MMR6, RC: &Mips::GPR32RegClass, Op0);
123 }
124 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
125 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranch_MM, RC: &Mips::GPR32RegClass, Op0);
126 }
127 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
128 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndrectHazardBranchR6, RC: &Mips::GPR32RegClass, Op0);
129 }
130 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
131 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranchR6, RC: &Mips::GPR32RegClass, Op0);
132 }
133 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
134 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectHazardBranch, RC: &Mips::GPR32RegClass, Op0);
135 }
136 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
137 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranch, RC: &Mips::GPR32RegClass, Op0);
138 }
139 return Register();
140}
141
142Register fastEmit_ISD_BRIND_MVT_i64_r(MVT RetVT, Register Op0) {
143 if (RetVT.SimpleTy != MVT::isVoid)
144 return Register();
145 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
146 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndrectHazardBranch64R6, RC: &Mips::GPR64RegClass, Op0);
147 }
148 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
149 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranch64R6, RC: &Mips::GPR64RegClass, Op0);
150 }
151 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
152 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectHazardBranch64, RC: &Mips::GPR64RegClass, Op0);
153 }
154 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
155 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranch64, RC: &Mips::GPR64RegClass, Op0);
156 }
157 return Register();
158}
159
160Register fastEmit_ISD_BRIND_r(MVT VT, MVT RetVT, Register Op0) {
161 switch (VT.SimpleTy) {
162 case MVT::i32: return fastEmit_ISD_BRIND_MVT_i32_r(RetVT, Op0);
163 case MVT::i64: return fastEmit_ISD_BRIND_MVT_i64_r(RetVT, Op0);
164 default: return Register();
165 }
166}
167
168// FastEmit functions for ISD::CTLZ.
169
170Register fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, Register Op0) {
171 if (RetVT.SimpleTy != MVT::i32)
172 return Register();
173 if ((Subtarget->inMicroMipsMode())) {
174 return fastEmitInst_r(MachineInstOpcode: Mips::CLZ_MM, RC: &Mips::GPR32RegClass, Op0);
175 }
176 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding())) {
177 return fastEmitInst_r(MachineInstOpcode: Mips::CLZ_R6, RC: &Mips::GPR32RegClass, Op0);
178 }
179 if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
180 return fastEmitInst_r(MachineInstOpcode: Mips::CLZ, RC: &Mips::GPR32RegClass, Op0);
181 }
182 return Register();
183}
184
185Register fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, Register Op0) {
186 if (RetVT.SimpleTy != MVT::i64)
187 return Register();
188 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
189 return fastEmitInst_r(MachineInstOpcode: Mips::DCLZ_R6, RC: &Mips::GPR64RegClass, Op0);
190 }
191 if ((Subtarget->hasMips64()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips64r6())) {
192 return fastEmitInst_r(MachineInstOpcode: Mips::DCLZ, RC: &Mips::GPR64RegClass, Op0);
193 }
194 return Register();
195}
196
197Register fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, Register Op0) {
198 if (RetVT.SimpleTy != MVT::v16i8)
199 return Register();
200 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
201 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_B, RC: &Mips::MSA128BRegClass, Op0);
202 }
203 return Register();
204}
205
206Register fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, Register Op0) {
207 if (RetVT.SimpleTy != MVT::v8i16)
208 return Register();
209 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
210 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_H, RC: &Mips::MSA128HRegClass, Op0);
211 }
212 return Register();
213}
214
215Register fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, Register Op0) {
216 if (RetVT.SimpleTy != MVT::v4i32)
217 return Register();
218 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
219 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_W, RC: &Mips::MSA128WRegClass, Op0);
220 }
221 return Register();
222}
223
224Register fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, Register Op0) {
225 if (RetVT.SimpleTy != MVT::v2i64)
226 return Register();
227 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
228 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_D, RC: &Mips::MSA128DRegClass, Op0);
229 }
230 return Register();
231}
232
233Register fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, Register Op0) {
234 switch (VT.SimpleTy) {
235 case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0);
236 case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0);
237 case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0);
238 case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0);
239 case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0);
240 case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0);
241 default: return Register();
242 }
243}
244
245// FastEmit functions for ISD::CTPOP.
246
247Register fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, Register Op0) {
248 if (RetVT.SimpleTy != MVT::i32)
249 return Register();
250 if ((Subtarget->hasCnMips())) {
251 return fastEmitInst_r(MachineInstOpcode: Mips::POP, RC: &Mips::GPR32RegClass, Op0);
252 }
253 return Register();
254}
255
256Register fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, Register Op0) {
257 if (RetVT.SimpleTy != MVT::i64)
258 return Register();
259 if ((Subtarget->hasCnMips())) {
260 return fastEmitInst_r(MachineInstOpcode: Mips::DPOP, RC: &Mips::GPR64RegClass, Op0);
261 }
262 return Register();
263}
264
265Register fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, Register Op0) {
266 if (RetVT.SimpleTy != MVT::v16i8)
267 return Register();
268 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
269 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_B, RC: &Mips::MSA128BRegClass, Op0);
270 }
271 return Register();
272}
273
274Register fastEmit_ISD_CTPOP_MVT_v8i16_r(MVT RetVT, Register Op0) {
275 if (RetVT.SimpleTy != MVT::v8i16)
276 return Register();
277 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
278 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_H, RC: &Mips::MSA128HRegClass, Op0);
279 }
280 return Register();
281}
282
283Register fastEmit_ISD_CTPOP_MVT_v4i32_r(MVT RetVT, Register Op0) {
284 if (RetVT.SimpleTy != MVT::v4i32)
285 return Register();
286 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
287 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_W, RC: &Mips::MSA128WRegClass, Op0);
288 }
289 return Register();
290}
291
292Register fastEmit_ISD_CTPOP_MVT_v2i64_r(MVT RetVT, Register Op0) {
293 if (RetVT.SimpleTy != MVT::v2i64)
294 return Register();
295 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
296 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_D, RC: &Mips::MSA128DRegClass, Op0);
297 }
298 return Register();
299}
300
301Register fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, Register Op0) {
302 switch (VT.SimpleTy) {
303 case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0);
304 case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0);
305 case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0);
306 case MVT::v8i16: return fastEmit_ISD_CTPOP_MVT_v8i16_r(RetVT, Op0);
307 case MVT::v4i32: return fastEmit_ISD_CTPOP_MVT_v4i32_r(RetVT, Op0);
308 case MVT::v2i64: return fastEmit_ISD_CTPOP_MVT_v2i64_r(RetVT, Op0);
309 default: return Register();
310 }
311}
312
313// FastEmit functions for ISD::FABS.
314
315Register fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, Register Op0) {
316 if (RetVT.SimpleTy != MVT::f64)
317 return Register();
318 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
319 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D64_MM, RC: &Mips::FGR64RegClass, Op0);
320 }
321 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
322 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D32_MM, RC: &Mips::AFGR64RegClass, Op0);
323 }
324 return Register();
325}
326
327Register fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, Register Op0) {
328 if (RetVT.SimpleTy != MVT::v4f32)
329 return Register();
330 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
331 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_W, RC: &Mips::MSA128WRegClass, Op0);
332 }
333 return Register();
334}
335
336Register fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, Register Op0) {
337 if (RetVT.SimpleTy != MVT::v2f64)
338 return Register();
339 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
340 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D, RC: &Mips::MSA128DRegClass, Op0);
341 }
342 return Register();
343}
344
345Register fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, Register Op0) {
346 switch (VT.SimpleTy) {
347 case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0);
348 case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0);
349 case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0);
350 default: return Register();
351 }
352}
353
354// FastEmit functions for ISD::FEXP2.
355
356Register fastEmit_ISD_FEXP2_MVT_v4f32_r(MVT RetVT, Register Op0) {
357 if (RetVT.SimpleTy != MVT::v4f32)
358 return Register();
359 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
360 return fastEmitInst_r(MachineInstOpcode: Mips::FEXP2_W_1_PSEUDO, RC: &Mips::MSA128WRegClass, Op0);
361 }
362 return Register();
363}
364
365Register fastEmit_ISD_FEXP2_MVT_v2f64_r(MVT RetVT, Register Op0) {
366 if (RetVT.SimpleTy != MVT::v2f64)
367 return Register();
368 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
369 return fastEmitInst_r(MachineInstOpcode: Mips::FEXP2_D_1_PSEUDO, RC: &Mips::MSA128DRegClass, Op0);
370 }
371 return Register();
372}
373
374Register fastEmit_ISD_FEXP2_r(MVT VT, MVT RetVT, Register Op0) {
375 switch (VT.SimpleTy) {
376 case MVT::v4f32: return fastEmit_ISD_FEXP2_MVT_v4f32_r(RetVT, Op0);
377 case MVT::v2f64: return fastEmit_ISD_FEXP2_MVT_v2f64_r(RetVT, Op0);
378 default: return Register();
379 }
380}
381
382// FastEmit functions for ISD::FLOG2.
383
384Register fastEmit_ISD_FLOG2_MVT_v4f32_r(MVT RetVT, Register Op0) {
385 if (RetVT.SimpleTy != MVT::v4f32)
386 return Register();
387 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
388 return fastEmitInst_r(MachineInstOpcode: Mips::FLOG2_W, RC: &Mips::MSA128WRegClass, Op0);
389 }
390 return Register();
391}
392
393Register fastEmit_ISD_FLOG2_MVT_v2f64_r(MVT RetVT, Register Op0) {
394 if (RetVT.SimpleTy != MVT::v2f64)
395 return Register();
396 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
397 return fastEmitInst_r(MachineInstOpcode: Mips::FLOG2_D, RC: &Mips::MSA128DRegClass, Op0);
398 }
399 return Register();
400}
401
402Register fastEmit_ISD_FLOG2_r(MVT VT, MVT RetVT, Register Op0) {
403 switch (VT.SimpleTy) {
404 case MVT::v4f32: return fastEmit_ISD_FLOG2_MVT_v4f32_r(RetVT, Op0);
405 case MVT::v2f64: return fastEmit_ISD_FLOG2_MVT_v2f64_r(RetVT, Op0);
406 default: return Register();
407 }
408}
409
410// FastEmit functions for ISD::FNEG.
411
412Register fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, Register Op0) {
413 if (RetVT.SimpleTy != MVT::f32)
414 return Register();
415 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
416 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_S_MMR6, RC: &Mips::FGR32RegClass, Op0);
417 }
418 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
419 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_S_MM, RC: &Mips::FGR32RegClass, Op0);
420 }
421 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
422 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_S, RC: &Mips::FGR32RegClass, Op0);
423 }
424 return Register();
425}
426
427Register fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, Register Op0) {
428 if (RetVT.SimpleTy != MVT::f64)
429 return Register();
430 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
431 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D64_MM, RC: &Mips::FGR64RegClass, Op0);
432 }
433 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
434 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D32_MM, RC: &Mips::AFGR64RegClass, Op0);
435 }
436 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
437 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D64, RC: &Mips::FGR64RegClass, Op0);
438 }
439 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
440 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D32, RC: &Mips::AFGR64RegClass, Op0);
441 }
442 return Register();
443}
444
445Register fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, Register Op0) {
446 switch (VT.SimpleTy) {
447 case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0);
448 case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0);
449 default: return Register();
450 }
451}
452
453// FastEmit functions for ISD::FP_EXTEND.
454
455Register fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(Register Op0) {
456 if ((Subtarget->hasMSA())) {
457 return fastEmitInst_r(MachineInstOpcode: Mips::MSA_FP_EXTEND_W_PSEUDO, RC: &Mips::FGR32RegClass, Op0);
458 }
459 return Register();
460}
461
462Register fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(Register Op0) {
463 if ((Subtarget->hasMSA())) {
464 return fastEmitInst_r(MachineInstOpcode: Mips::MSA_FP_EXTEND_D_PSEUDO, RC: &Mips::FGR64RegClass, Op0);
465 }
466 return Register();
467}
468
469Register fastEmit_ISD_FP_EXTEND_MVT_f16_r(MVT RetVT, Register Op0) {
470switch (RetVT.SimpleTy) {
471 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(Op0);
472 case MVT::f64: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(Op0);
473 default: return Register();
474}
475}
476
477Register fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, Register Op0) {
478 if (RetVT.SimpleTy != MVT::f64)
479 return Register();
480 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) {
481 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D32_S_MM, RC: &Mips::AFGR64RegClass, Op0);
482 }
483 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
484 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D64_S_MM, RC: &Mips::FGR64RegClass, Op0);
485 }
486 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->inMicroMipsMode())) {
487 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D64_S, RC: &Mips::FGR64RegClass, Op0);
488 }
489 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
490 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D32_S, RC: &Mips::AFGR64RegClass, Op0);
491 }
492 return Register();
493}
494
495Register fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
496 switch (VT.SimpleTy) {
497 case MVT::f16: return fastEmit_ISD_FP_EXTEND_MVT_f16_r(RetVT, Op0);
498 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0);
499 default: return Register();
500 }
501}
502
503// FastEmit functions for ISD::FP_ROUND.
504
505Register fastEmit_ISD_FP_ROUND_MVT_f32_r(MVT RetVT, Register Op0) {
506 if (RetVT.SimpleTy != MVT::f16)
507 return Register();
508 if ((Subtarget->hasMSA())) {
509 return fastEmitInst_r(MachineInstOpcode: Mips::MSA_FP_ROUND_W_PSEUDO, RC: &Mips::MSA128F16RegClass, Op0);
510 }
511 return Register();
512}
513
514Register fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(Register Op0) {
515 if ((Subtarget->hasMSA())) {
516 return fastEmitInst_r(MachineInstOpcode: Mips::MSA_FP_ROUND_D_PSEUDO, RC: &Mips::MSA128F16RegClass, Op0);
517 }
518 return Register();
519}
520
521Register fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(Register Op0) {
522 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) {
523 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D32_MM, RC: &Mips::FGR32RegClass, Op0);
524 }
525 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
526 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D64_MM, RC: &Mips::FGR32RegClass, Op0);
527 }
528 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->inMicroMipsMode())) {
529 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D64, RC: &Mips::FGR32RegClass, Op0);
530 }
531 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
532 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D32, RC: &Mips::FGR32RegClass, Op0);
533 }
534 return Register();
535}
536
537Register fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, Register Op0) {
538switch (RetVT.SimpleTy) {
539 case MVT::f16: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(Op0);
540 case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(Op0);
541 default: return Register();
542}
543}
544
545Register fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, Register Op0) {
546 switch (VT.SimpleTy) {
547 case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f32_r(RetVT, Op0);
548 case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0);
549 default: return Register();
550 }
551}
552
553// FastEmit functions for ISD::FP_TO_SINT.
554
555Register fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
556 if (RetVT.SimpleTy != MVT::v4i32)
557 return Register();
558 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
559 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_S_W, RC: &Mips::MSA128WRegClass, Op0);
560 }
561 return Register();
562}
563
564Register fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
565 if (RetVT.SimpleTy != MVT::v2i64)
566 return Register();
567 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
568 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_S_D, RC: &Mips::MSA128DRegClass, Op0);
569 }
570 return Register();
571}
572
573Register fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, Register Op0) {
574 switch (VT.SimpleTy) {
575 case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0);
576 case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0);
577 default: return Register();
578 }
579}
580
581// FastEmit functions for ISD::FP_TO_UINT.
582
583Register fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
584 if (RetVT.SimpleTy != MVT::v4i32)
585 return Register();
586 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
587 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_U_W, RC: &Mips::MSA128WRegClass, Op0);
588 }
589 return Register();
590}
591
592Register fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
593 if (RetVT.SimpleTy != MVT::v2i64)
594 return Register();
595 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
596 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_U_D, RC: &Mips::MSA128DRegClass, Op0);
597 }
598 return Register();
599}
600
601Register fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, Register Op0) {
602 switch (VT.SimpleTy) {
603 case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0);
604 case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0);
605 default: return Register();
606 }
607}
608
609// FastEmit functions for ISD::FRINT.
610
611Register fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
612 if (RetVT.SimpleTy != MVT::v4f32)
613 return Register();
614 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
615 return fastEmitInst_r(MachineInstOpcode: Mips::FRINT_W, RC: &Mips::MSA128WRegClass, Op0);
616 }
617 return Register();
618}
619
620Register fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
621 if (RetVT.SimpleTy != MVT::v2f64)
622 return Register();
623 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
624 return fastEmitInst_r(MachineInstOpcode: Mips::FRINT_D, RC: &Mips::MSA128DRegClass, Op0);
625 }
626 return Register();
627}
628
629Register fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, Register Op0) {
630 switch (VT.SimpleTy) {
631 case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0);
632 case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0);
633 default: return Register();
634 }
635}
636
637// FastEmit functions for ISD::FSQRT.
638
639Register fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, Register Op0) {
640 if (RetVT.SimpleTy != MVT::f32)
641 return Register();
642 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
643 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_S_MM, RC: &Mips::FGR32RegClass, Op0);
644 }
645 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
646 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_S, RC: &Mips::FGR32RegClass, Op0);
647 }
648 return Register();
649}
650
651Register fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, Register Op0) {
652 if (RetVT.SimpleTy != MVT::f64)
653 return Register();
654 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
655 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D64_MM, RC: &Mips::FGR64RegClass, Op0);
656 }
657 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
658 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D32_MM, RC: &Mips::AFGR64RegClass, Op0);
659 }
660 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
661 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D64, RC: &Mips::FGR64RegClass, Op0);
662 }
663 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
664 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D32, RC: &Mips::AFGR64RegClass, Op0);
665 }
666 return Register();
667}
668
669Register fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, Register Op0) {
670 if (RetVT.SimpleTy != MVT::v4f32)
671 return Register();
672 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
673 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_W, RC: &Mips::MSA128WRegClass, Op0);
674 }
675 return Register();
676}
677
678Register fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, Register Op0) {
679 if (RetVT.SimpleTy != MVT::v2f64)
680 return Register();
681 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
682 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D, RC: &Mips::MSA128DRegClass, Op0);
683 }
684 return Register();
685}
686
687Register fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, Register Op0) {
688 switch (VT.SimpleTy) {
689 case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0);
690 case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0);
691 case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0);
692 case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0);
693 default: return Register();
694 }
695}
696
697// FastEmit functions for ISD::SIGN_EXTEND.
698
699Register fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, Register Op0) {
700 if (RetVT.SimpleTy != MVT::i64)
701 return Register();
702 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())) {
703 return fastEmitInst_r(MachineInstOpcode: Mips::SLL64_32, RC: &Mips::GPR64RegClass, Op0);
704 }
705 return Register();
706}
707
708Register fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
709 switch (VT.SimpleTy) {
710 case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0);
711 default: return Register();
712 }
713}
714
715// FastEmit functions for ISD::SINT_TO_FP.
716
717Register fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
718 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_S_W, RC: &Mips::FGR32RegClass, Op0);
719}
720
721Register fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
722 if ((Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
723 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D64_W, RC: &Mips::FGR64RegClass, Op0);
724 }
725 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) {
726 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D32_W, RC: &Mips::AFGR64RegClass, Op0);
727 }
728 return Register();
729}
730
731Register fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
732switch (RetVT.SimpleTy) {
733 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
734 case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
735 default: return Register();
736}
737}
738
739Register fastEmit_ISD_SINT_TO_FP_MVT_i64_r(MVT RetVT, Register Op0) {
740 if (RetVT.SimpleTy != MVT::f64)
741 return Register();
742 if ((Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
743 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D64_L, RC: &Mips::FGR64RegClass, Op0);
744 }
745 return Register();
746}
747
748Register fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
749 if (RetVT.SimpleTy != MVT::v4f32)
750 return Register();
751 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
752 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_S_W, RC: &Mips::MSA128WRegClass, Op0);
753 }
754 return Register();
755}
756
757Register fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, Register Op0) {
758 if (RetVT.SimpleTy != MVT::v2f64)
759 return Register();
760 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
761 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_S_D, RC: &Mips::MSA128DRegClass, Op0);
762 }
763 return Register();
764}
765
766Register fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
767 switch (VT.SimpleTy) {
768 case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0);
769 case MVT::i64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_r(RetVT, Op0);
770 case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
771 case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
772 default: return Register();
773 }
774}
775
776// FastEmit functions for ISD::STRICT_FP_EXTEND.
777
778Register fastEmit_ISD_STRICT_FP_EXTEND_MVT_f32_r(MVT RetVT, Register Op0) {
779 if (RetVT.SimpleTy != MVT::f64)
780 return Register();
781 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->inMicroMipsMode())) {
782 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D64_S, RC: &Mips::FGR64RegClass, Op0);
783 }
784 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
785 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D32_S, RC: &Mips::AFGR64RegClass, Op0);
786 }
787 return Register();
788}
789
790Register fastEmit_ISD_STRICT_FP_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
791 switch (VT.SimpleTy) {
792 case MVT::f32: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_f32_r(RetVT, Op0);
793 default: return Register();
794 }
795}
796
797// FastEmit functions for ISD::STRICT_FP_ROUND.
798
799Register fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(MVT RetVT, Register Op0) {
800 if (RetVT.SimpleTy != MVT::f32)
801 return Register();
802 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->inMicroMipsMode())) {
803 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D64, RC: &Mips::FGR32RegClass, Op0);
804 }
805 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
806 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D32, RC: &Mips::FGR32RegClass, Op0);
807 }
808 return Register();
809}
810
811Register fastEmit_ISD_STRICT_FP_ROUND_r(MVT VT, MVT RetVT, Register Op0) {
812 switch (VT.SimpleTy) {
813 case MVT::f64: return fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(RetVT, Op0);
814 default: return Register();
815 }
816}
817
818// FastEmit functions for ISD::STRICT_FSQRT.
819
820Register fastEmit_ISD_STRICT_FSQRT_MVT_f32_r(MVT RetVT, Register Op0) {
821 if (RetVT.SimpleTy != MVT::f32)
822 return Register();
823 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
824 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_S, RC: &Mips::FGR32RegClass, Op0);
825 }
826 return Register();
827}
828
829Register fastEmit_ISD_STRICT_FSQRT_MVT_f64_r(MVT RetVT, Register Op0) {
830 if (RetVT.SimpleTy != MVT::f64)
831 return Register();
832 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
833 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D64, RC: &Mips::FGR64RegClass, Op0);
834 }
835 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
836 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D32, RC: &Mips::AFGR64RegClass, Op0);
837 }
838 return Register();
839}
840
841Register fastEmit_ISD_STRICT_FSQRT_r(MVT VT, MVT RetVT, Register Op0) {
842 switch (VT.SimpleTy) {
843 case MVT::f32: return fastEmit_ISD_STRICT_FSQRT_MVT_f32_r(RetVT, Op0);
844 case MVT::f64: return fastEmit_ISD_STRICT_FSQRT_MVT_f64_r(RetVT, Op0);
845 default: return Register();
846 }
847}
848
849// FastEmit functions for ISD::STRICT_SINT_TO_FP.
850
851Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
852 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_S_W, RC: &Mips::FGR32RegClass, Op0);
853}
854
855Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
856 if ((Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
857 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D64_W, RC: &Mips::FGR64RegClass, Op0);
858 }
859 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) {
860 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D32_W, RC: &Mips::AFGR64RegClass, Op0);
861 }
862 return Register();
863}
864
865Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
866switch (RetVT.SimpleTy) {
867 case MVT::f32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
868 case MVT::f64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
869 default: return Register();
870}
871}
872
873Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_r(MVT RetVT, Register Op0) {
874 if (RetVT.SimpleTy != MVT::f64)
875 return Register();
876 if ((Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
877 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D64_L, RC: &Mips::FGR64RegClass, Op0);
878 }
879 return Register();
880}
881
882Register fastEmit_ISD_STRICT_SINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
883 switch (VT.SimpleTy) {
884 case MVT::i32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(RetVT, Op0);
885 case MVT::i64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_r(RetVT, Op0);
886 default: return Register();
887 }
888}
889
890// FastEmit functions for ISD::UINT_TO_FP.
891
892Register fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
893 if (RetVT.SimpleTy != MVT::v4f32)
894 return Register();
895 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
896 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_U_W, RC: &Mips::MSA128WRegClass, Op0);
897 }
898 return Register();
899}
900
901Register fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, Register Op0) {
902 if (RetVT.SimpleTy != MVT::v2f64)
903 return Register();
904 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
905 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_U_D, RC: &Mips::MSA128DRegClass, Op0);
906 }
907 return Register();
908}
909
910Register fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
911 switch (VT.SimpleTy) {
912 case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
913 case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
914 default: return Register();
915 }
916}
917
918// FastEmit functions for MipsISD::JmpLink.
919
920Register fastEmit_MipsISD_JmpLink_MVT_i32_r(MVT RetVT, Register Op0) {
921 if (RetVT.SimpleTy != MVT::isVoid)
922 return Register();
923 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
924 return fastEmitInst_r(MachineInstOpcode: Mips::JALR16_MM, RC: &Mips::GPR32RegClass, Op0);
925 }
926 if ((Subtarget->inMips16Mode())) {
927 return fastEmitInst_r(MachineInstOpcode: Mips::JumpLinkReg16, RC: &Mips::CPU16RegsRegClass, Op0);
928 }
929 if ((!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
930 return fastEmitInst_r(MachineInstOpcode: Mips::JALRHBPseudo, RC: &Mips::GPR32RegClass, Op0);
931 }
932 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode())) {
933 return fastEmitInst_r(MachineInstOpcode: Mips::JALRPseudo, RC: &Mips::GPR32RegClass, Op0);
934 }
935 return Register();
936}
937
938Register fastEmit_MipsISD_JmpLink_MVT_i64_r(MVT RetVT, Register Op0) {
939 if (RetVT.SimpleTy != MVT::isVoid)
940 return Register();
941 if ((Subtarget->isABI_N64()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
942 return fastEmitInst_r(MachineInstOpcode: Mips::JALRHB64Pseudo, RC: &Mips::GPR64RegClass, Op0);
943 }
944 if ((Subtarget->isABI_N64()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMips16Mode())) {
945 return fastEmitInst_r(MachineInstOpcode: Mips::JALR64Pseudo, RC: &Mips::GPR64RegClass, Op0);
946 }
947 return Register();
948}
949
950Register fastEmit_MipsISD_JmpLink_r(MVT VT, MVT RetVT, Register Op0) {
951 switch (VT.SimpleTy) {
952 case MVT::i32: return fastEmit_MipsISD_JmpLink_MVT_i32_r(RetVT, Op0);
953 case MVT::i64: return fastEmit_MipsISD_JmpLink_MVT_i64_r(RetVT, Op0);
954 default: return Register();
955 }
956}
957
958// FastEmit functions for MipsISD::MFHI.
959
960Register fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(Register Op0) {
961 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
962 return fastEmitInst_r(MachineInstOpcode: Mips::MFHI_DSP_MM, RC: &Mips::GPR32RegClass, Op0);
963 }
964 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
965 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFHI_MM, RC: &Mips::GPR32RegClass, Op0);
966 }
967 if ((Subtarget->hasDSP())) {
968 return fastEmitInst_r(MachineInstOpcode: Mips::MFHI_DSP, RC: &Mips::GPR32RegClass, Op0);
969 }
970 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
971 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFHI, RC: &Mips::GPR32RegClass, Op0);
972 }
973 return Register();
974}
975
976Register fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(Register Op0) {
977 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
978 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFHI64, RC: &Mips::GPR64RegClass, Op0);
979 }
980 return Register();
981}
982
983Register fastEmit_MipsISD_MFHI_MVT_Untyped_r(MVT RetVT, Register Op0) {
984switch (RetVT.SimpleTy) {
985 case MVT::i32: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(Op0);
986 case MVT::i64: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(Op0);
987 default: return Register();
988}
989}
990
991Register fastEmit_MipsISD_MFHI_r(MVT VT, MVT RetVT, Register Op0) {
992 switch (VT.SimpleTy) {
993 case MVT::Untyped: return fastEmit_MipsISD_MFHI_MVT_Untyped_r(RetVT, Op0);
994 default: return Register();
995 }
996}
997
998// FastEmit functions for MipsISD::MFLO.
999
1000Register fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(Register Op0) {
1001 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
1002 return fastEmitInst_r(MachineInstOpcode: Mips::MFLO_DSP_MM, RC: &Mips::GPR32RegClass, Op0);
1003 }
1004 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
1005 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFLO_MM, RC: &Mips::GPR32RegClass, Op0);
1006 }
1007 if ((Subtarget->hasDSP())) {
1008 return fastEmitInst_r(MachineInstOpcode: Mips::MFLO_DSP, RC: &Mips::GPR32RegClass, Op0);
1009 }
1010 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
1011 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFLO, RC: &Mips::GPR32RegClass, Op0);
1012 }
1013 return Register();
1014}
1015
1016Register fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(Register Op0) {
1017 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
1018 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFLO64, RC: &Mips::GPR64RegClass, Op0);
1019 }
1020 return Register();
1021}
1022
1023Register fastEmit_MipsISD_MFLO_MVT_Untyped_r(MVT RetVT, Register Op0) {
1024switch (RetVT.SimpleTy) {
1025 case MVT::i32: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(Op0);
1026 case MVT::i64: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(Op0);
1027 default: return Register();
1028}
1029}
1030
1031Register fastEmit_MipsISD_MFLO_r(MVT VT, MVT RetVT, Register Op0) {
1032 switch (VT.SimpleTy) {
1033 case MVT::Untyped: return fastEmit_MipsISD_MFLO_MVT_Untyped_r(RetVT, Op0);
1034 default: return Register();
1035 }
1036}
1037
1038// FastEmit functions for MipsISD::MTC1_D64.
1039
1040Register fastEmit_MipsISD_MTC1_D64_MVT_i32_r(MVT RetVT, Register Op0) {
1041 if (RetVT.SimpleTy != MVT::f64)
1042 return Register();
1043 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
1044 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_D64_MM, RC: &Mips::FGR64RegClass, Op0);
1045 }
1046 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
1047 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_D64, RC: &Mips::FGR64RegClass, Op0);
1048 }
1049 return Register();
1050}
1051
1052Register fastEmit_MipsISD_MTC1_D64_r(MVT VT, MVT RetVT, Register Op0) {
1053 switch (VT.SimpleTy) {
1054 case MVT::i32: return fastEmit_MipsISD_MTC1_D64_MVT_i32_r(RetVT, Op0);
1055 default: return Register();
1056 }
1057}
1058
1059// FastEmit functions for MipsISD::TailCall.
1060
1061Register fastEmit_MipsISD_TailCall_MVT_i32_r(MVT RetVT, Register Op0) {
1062 if (RetVT.SimpleTy != MVT::isVoid)
1063 return Register();
1064 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1065 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREG_MMR6, RC: &Mips::GPR32RegClass, Op0);
1066 }
1067 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1068 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREG_MM, RC: &Mips::GPR32RegClass, Op0);
1069 }
1070 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
1071 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLHBR6REG, RC: &Mips::GPR32RegClass, Op0);
1072 }
1073 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
1074 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLR6REG, RC: &Mips::GPR32RegClass, Op0);
1075 }
1076 if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
1077 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREGHB, RC: &Mips::GPR32RegClass, Op0);
1078 }
1079 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
1080 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREG, RC: &Mips::GPR32RegClass, Op0);
1081 }
1082 return Register();
1083}
1084
1085Register fastEmit_MipsISD_TailCall_MVT_i64_r(MVT RetVT, Register Op0) {
1086 if (RetVT.SimpleTy != MVT::isVoid)
1087 return Register();
1088 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
1089 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLHB64R6REG, RC: &Mips::GPR64RegClass, Op0);
1090 }
1091 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
1092 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALL64R6REG, RC: &Mips::GPR64RegClass, Op0);
1093 }
1094 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
1095 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREGHB64, RC: &Mips::GPR64RegClass, Op0);
1096 }
1097 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
1098 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREG64, RC: &Mips::GPR64RegClass, Op0);
1099 }
1100 return Register();
1101}
1102
1103Register fastEmit_MipsISD_TailCall_r(MVT VT, MVT RetVT, Register Op0) {
1104 switch (VT.SimpleTy) {
1105 case MVT::i32: return fastEmit_MipsISD_TailCall_MVT_i32_r(RetVT, Op0);
1106 case MVT::i64: return fastEmit_MipsISD_TailCall_MVT_i64_r(RetVT, Op0);
1107 default: return Register();
1108 }
1109}
1110
1111// FastEmit functions for MipsISD::TruncIntFP.
1112
1113Register fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(Register Op0) {
1114 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1115 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_S_MMR6, RC: &Mips::FGR32RegClass, Op0);
1116 }
1117 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1118 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_S_MM, RC: &Mips::FGR32RegClass, Op0);
1119 }
1120 if ((Subtarget->hasStandardEncoding())) {
1121 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_S, RC: &Mips::FGR32RegClass, Op0);
1122 }
1123 if ((Subtarget->isR5900())) {
1124 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_W_S, RC: &Mips::FGR32RegClass, Op0);
1125 }
1126 return Register();
1127}
1128
1129Register fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(Register Op0) {
1130 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
1131 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_L_S, RC: &Mips::FGR64RegClass, Op0);
1132 }
1133 return Register();
1134}
1135
1136Register fastEmit_MipsISD_TruncIntFP_MVT_f32_r(MVT RetVT, Register Op0) {
1137switch (RetVT.SimpleTy) {
1138 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(Op0);
1139 case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(Op0);
1140 default: return Register();
1141}
1142}
1143
1144Register fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(Register Op0) {
1145 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1146 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_D_MMR6, RC: &Mips::FGR32RegClass, Op0);
1147 }
1148 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->hasMips32r6())) {
1149 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_W_D64_MM, RC: &Mips::FGR32RegClass, Op0);
1150 }
1151 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())) {
1152 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_MM, RC: &Mips::FGR32RegClass, Op0);
1153 }
1154 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
1155 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_D64, RC: &Mips::FGR32RegClass, Op0);
1156 }
1157 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1158 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_D32, RC: &Mips::FGR32RegClass, Op0);
1159 }
1160 return Register();
1161}
1162
1163Register fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(Register Op0) {
1164 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
1165 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_L_D64, RC: &Mips::FGR64RegClass, Op0);
1166 }
1167 return Register();
1168}
1169
1170Register fastEmit_MipsISD_TruncIntFP_MVT_f64_r(MVT RetVT, Register Op0) {
1171switch (RetVT.SimpleTy) {
1172 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(Op0);
1173 case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(Op0);
1174 default: return Register();
1175}
1176}
1177
1178Register fastEmit_MipsISD_TruncIntFP_r(MVT VT, MVT RetVT, Register Op0) {
1179 switch (VT.SimpleTy) {
1180 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_r(RetVT, Op0);
1181 case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_r(RetVT, Op0);
1182 default: return Register();
1183 }
1184}
1185
1186// FastEmit functions for MipsISD::VALL_NONZERO.
1187
1188Register fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(MVT RetVT, Register Op0) {
1189 if (RetVT.SimpleTy != MVT::i32)
1190 return Register();
1191 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_B_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1192}
1193
1194Register fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(MVT RetVT, Register Op0) {
1195 if (RetVT.SimpleTy != MVT::i32)
1196 return Register();
1197 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_H_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1198}
1199
1200Register fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(MVT RetVT, Register Op0) {
1201 if (RetVT.SimpleTy != MVT::i32)
1202 return Register();
1203 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_W_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1204}
1205
1206Register fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(MVT RetVT, Register Op0) {
1207 if (RetVT.SimpleTy != MVT::i32)
1208 return Register();
1209 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_D_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1210}
1211
1212Register fastEmit_MipsISD_VALL_NONZERO_r(MVT VT, MVT RetVT, Register Op0) {
1213 switch (VT.SimpleTy) {
1214 case MVT::v16i8: return fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(RetVT, Op0);
1215 case MVT::v8i16: return fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(RetVT, Op0);
1216 case MVT::v4i32: return fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(RetVT, Op0);
1217 case MVT::v2i64: return fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(RetVT, Op0);
1218 default: return Register();
1219 }
1220}
1221
1222// FastEmit functions for MipsISD::VALL_ZERO.
1223
1224Register fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(MVT RetVT, Register Op0) {
1225 if (RetVT.SimpleTy != MVT::i32)
1226 return Register();
1227 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_B_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1228}
1229
1230Register fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(MVT RetVT, Register Op0) {
1231 if (RetVT.SimpleTy != MVT::i32)
1232 return Register();
1233 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_H_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1234}
1235
1236Register fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(MVT RetVT, Register Op0) {
1237 if (RetVT.SimpleTy != MVT::i32)
1238 return Register();
1239 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_W_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1240}
1241
1242Register fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(MVT RetVT, Register Op0) {
1243 if (RetVT.SimpleTy != MVT::i32)
1244 return Register();
1245 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_D_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1246}
1247
1248Register fastEmit_MipsISD_VALL_ZERO_r(MVT VT, MVT RetVT, Register Op0) {
1249 switch (VT.SimpleTy) {
1250 case MVT::v16i8: return fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(RetVT, Op0);
1251 case MVT::v8i16: return fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(RetVT, Op0);
1252 case MVT::v4i32: return fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(RetVT, Op0);
1253 case MVT::v2i64: return fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(RetVT, Op0);
1254 default: return Register();
1255 }
1256}
1257
1258// FastEmit functions for MipsISD::VANY_NONZERO.
1259
1260Register fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(MVT RetVT, Register Op0) {
1261 if (RetVT.SimpleTy != MVT::i32)
1262 return Register();
1263 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_V_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1264}
1265
1266Register fastEmit_MipsISD_VANY_NONZERO_r(MVT VT, MVT RetVT, Register Op0) {
1267 switch (VT.SimpleTy) {
1268 case MVT::v16i8: return fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(RetVT, Op0);
1269 default: return Register();
1270 }
1271}
1272
1273// FastEmit functions for MipsISD::VANY_ZERO.
1274
1275Register fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(MVT RetVT, Register Op0) {
1276 if (RetVT.SimpleTy != MVT::i32)
1277 return Register();
1278 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_V_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1279}
1280
1281Register fastEmit_MipsISD_VANY_ZERO_r(MVT VT, MVT RetVT, Register Op0) {
1282 switch (VT.SimpleTy) {
1283 case MVT::v16i8: return fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(RetVT, Op0);
1284 default: return Register();
1285 }
1286}
1287
1288// Top-level FastEmit function.
1289
1290Register fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, Register Op0) override {
1291 switch (Opcode) {
1292 case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0);
1293 case ISD::BRIND: return fastEmit_ISD_BRIND_r(VT, RetVT, Op0);
1294 case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0);
1295 case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0);
1296 case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0);
1297 case ISD::FEXP2: return fastEmit_ISD_FEXP2_r(VT, RetVT, Op0);
1298 case ISD::FLOG2: return fastEmit_ISD_FLOG2_r(VT, RetVT, Op0);
1299 case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0);
1300 case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0);
1301 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0);
1302 case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0);
1303 case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0);
1304 case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0);
1305 case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0);
1306 case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0);
1307 case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0);
1308 case ISD::STRICT_FP_EXTEND: return fastEmit_ISD_STRICT_FP_EXTEND_r(VT, RetVT, Op0);
1309 case ISD::STRICT_FP_ROUND: return fastEmit_ISD_STRICT_FP_ROUND_r(VT, RetVT, Op0);
1310 case ISD::STRICT_FSQRT: return fastEmit_ISD_STRICT_FSQRT_r(VT, RetVT, Op0);
1311 case ISD::STRICT_SINT_TO_FP: return fastEmit_ISD_STRICT_SINT_TO_FP_r(VT, RetVT, Op0);
1312 case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0);
1313 case MipsISD::JmpLink: return fastEmit_MipsISD_JmpLink_r(VT, RetVT, Op0);
1314 case MipsISD::MFHI: return fastEmit_MipsISD_MFHI_r(VT, RetVT, Op0);
1315 case MipsISD::MFLO: return fastEmit_MipsISD_MFLO_r(VT, RetVT, Op0);
1316 case MipsISD::MTC1_D64: return fastEmit_MipsISD_MTC1_D64_r(VT, RetVT, Op0);
1317 case MipsISD::TailCall: return fastEmit_MipsISD_TailCall_r(VT, RetVT, Op0);
1318 case MipsISD::TruncIntFP: return fastEmit_MipsISD_TruncIntFP_r(VT, RetVT, Op0);
1319 case MipsISD::VALL_NONZERO: return fastEmit_MipsISD_VALL_NONZERO_r(VT, RetVT, Op0);
1320 case MipsISD::VALL_ZERO: return fastEmit_MipsISD_VALL_ZERO_r(VT, RetVT, Op0);
1321 case MipsISD::VANY_NONZERO: return fastEmit_MipsISD_VANY_NONZERO_r(VT, RetVT, Op0);
1322 case MipsISD::VANY_ZERO: return fastEmit_MipsISD_VANY_ZERO_r(VT, RetVT, Op0);
1323 default: return Register();
1324 }
1325}
1326
1327// FastEmit functions for ISD::ADD.
1328
1329Register fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1330 if (RetVT.SimpleTy != MVT::i32)
1331 return Register();
1332 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1333 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDU16_MMR6, RC: &Mips::GPRMM16RegClass, Op0, Op1);
1334 }
1335 if ((Subtarget->inMips16Mode())) {
1336 return fastEmitInst_rr(MachineInstOpcode: Mips::AdduRxRyRz16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
1337 }
1338 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1339 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDu_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
1340 }
1341 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1342 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDu, RC: &Mips::GPR32RegClass, Op0, Op1);
1343 }
1344 return Register();
1345}
1346
1347Register fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1348 if (RetVT.SimpleTy != MVT::i64)
1349 return Register();
1350 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1351 return fastEmitInst_rr(MachineInstOpcode: Mips::DADDu, RC: &Mips::GPR64RegClass, Op0, Op1);
1352 }
1353 return Register();
1354}
1355
1356Register fastEmit_ISD_ADD_MVT_v4i8_rr(MVT RetVT, Register Op0, Register Op1) {
1357 if (RetVT.SimpleTy != MVT::v4i8)
1358 return Register();
1359 if ((Subtarget->hasDSP())) {
1360 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDU_QB, RC: &Mips::DSPRRegClass, Op0, Op1);
1361 }
1362 return Register();
1363}
1364
1365Register fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1366 if (RetVT.SimpleTy != MVT::v16i8)
1367 return Register();
1368 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1369 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
1370 }
1371 return Register();
1372}
1373
1374Register fastEmit_ISD_ADD_MVT_v2i16_rr(MVT RetVT, Register Op0, Register Op1) {
1375 if (RetVT.SimpleTy != MVT::v2i16)
1376 return Register();
1377 if ((Subtarget->hasDSP())) {
1378 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDQ_PH, RC: &Mips::DSPRRegClass, Op0, Op1);
1379 }
1380 return Register();
1381}
1382
1383Register fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1384 if (RetVT.SimpleTy != MVT::v8i16)
1385 return Register();
1386 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1387 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
1388 }
1389 return Register();
1390}
1391
1392Register fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
1393 if (RetVT.SimpleTy != MVT::v4i32)
1394 return Register();
1395 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1396 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1397 }
1398 return Register();
1399}
1400
1401Register fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
1402 if (RetVT.SimpleTy != MVT::v2i64)
1403 return Register();
1404 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1405 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1406 }
1407 return Register();
1408}
1409
1410Register fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1411 switch (VT.SimpleTy) {
1412 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op1);
1413 case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op1);
1414 case MVT::v4i8: return fastEmit_ISD_ADD_MVT_v4i8_rr(RetVT, Op0, Op1);
1415 case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op1);
1416 case MVT::v2i16: return fastEmit_ISD_ADD_MVT_v2i16_rr(RetVT, Op0, Op1);
1417 case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op1);
1418 case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op1);
1419 case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op1);
1420 default: return Register();
1421 }
1422}
1423
1424// FastEmit functions for ISD::ADDC.
1425
1426Register fastEmit_ISD_ADDC_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1427 if (RetVT.SimpleTy != MVT::i32)
1428 return Register();
1429 if ((Subtarget->hasDSP())) {
1430 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDSC, RC: &Mips::GPR32RegClass, Op0, Op1);
1431 }
1432 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP())) {
1433 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDu, RC: &Mips::GPR32RegClass, Op0, Op1);
1434 }
1435 return Register();
1436}
1437
1438Register fastEmit_ISD_ADDC_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1439 if (RetVT.SimpleTy != MVT::i64)
1440 return Register();
1441 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->hasDSP()) && (!Subtarget->inMicroMipsMode())) {
1442 return fastEmitInst_rr(MachineInstOpcode: Mips::DADDu, RC: &Mips::GPR64RegClass, Op0, Op1);
1443 }
1444 return Register();
1445}
1446
1447Register fastEmit_ISD_ADDC_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1448 switch (VT.SimpleTy) {
1449 case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_rr(RetVT, Op0, Op1);
1450 case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_rr(RetVT, Op0, Op1);
1451 default: return Register();
1452 }
1453}
1454
1455// FastEmit functions for ISD::ADDE.
1456
1457Register fastEmit_ISD_ADDE_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1458 if (RetVT.SimpleTy != MVT::i32)
1459 return Register();
1460 if ((Subtarget->hasDSP())) {
1461 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDWC, RC: &Mips::GPR32RegClass, Op0, Op1);
1462 }
1463 return Register();
1464}
1465
1466Register fastEmit_ISD_ADDE_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1467 switch (VT.SimpleTy) {
1468 case MVT::i32: return fastEmit_ISD_ADDE_MVT_i32_rr(RetVT, Op0, Op1);
1469 default: return Register();
1470 }
1471}
1472
1473// FastEmit functions for ISD::AND.
1474
1475Register fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1476 if (RetVT.SimpleTy != MVT::i32)
1477 return Register();
1478 if ((Subtarget->inMips16Mode())) {
1479 return fastEmitInst_rr(MachineInstOpcode: Mips::AndRxRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
1480 }
1481 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1482 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
1483 }
1484 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1485 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
1486 }
1487 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1488 return fastEmitInst_rr(MachineInstOpcode: Mips::AND, RC: &Mips::GPR32RegClass, Op0, Op1);
1489 }
1490 return Register();
1491}
1492
1493Register fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1494 if (RetVT.SimpleTy != MVT::i64)
1495 return Register();
1496 if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
1497 return fastEmitInst_rr(MachineInstOpcode: Mips::AND64, RC: &Mips::GPR64RegClass, Op0, Op1);
1498 }
1499 return Register();
1500}
1501
1502Register fastEmit_ISD_AND_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1503 if (RetVT.SimpleTy != MVT::v16i8)
1504 return Register();
1505 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1506 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
1507 }
1508 return Register();
1509}
1510
1511Register fastEmit_ISD_AND_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1512 if (RetVT.SimpleTy != MVT::v8i16)
1513 return Register();
1514 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1515 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
1516 }
1517 return Register();
1518}
1519
1520Register fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
1521 if (RetVT.SimpleTy != MVT::v4i32)
1522 return Register();
1523 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1524 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
1525 }
1526 return Register();
1527}
1528
1529Register fastEmit_ISD_AND_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
1530 if (RetVT.SimpleTy != MVT::v2i64)
1531 return Register();
1532 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1533 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
1534 }
1535 return Register();
1536}
1537
1538Register fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1539 switch (VT.SimpleTy) {
1540 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op1);
1541 case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op1);
1542 case MVT::v16i8: return fastEmit_ISD_AND_MVT_v16i8_rr(RetVT, Op0, Op1);
1543 case MVT::v8i16: return fastEmit_ISD_AND_MVT_v8i16_rr(RetVT, Op0, Op1);
1544 case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op1);
1545 case MVT::v2i64: return fastEmit_ISD_AND_MVT_v2i64_rr(RetVT, Op0, Op1);
1546 default: return Register();
1547 }
1548}
1549
1550// FastEmit functions for ISD::FADD.
1551
1552Register fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1553 if (RetVT.SimpleTy != MVT::f32)
1554 return Register();
1555 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1556 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1557 }
1558 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1559 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1560 }
1561 return Register();
1562}
1563
1564Register fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1565 if (RetVT.SimpleTy != MVT::f64)
1566 return Register();
1567 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
1568 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1569 }
1570 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1571 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1572 }
1573 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1574 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1575 }
1576 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1577 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1578 }
1579 return Register();
1580}
1581
1582Register fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1583 if (RetVT.SimpleTy != MVT::v4f32)
1584 return Register();
1585 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1586 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1587 }
1588 return Register();
1589}
1590
1591Register fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1592 if (RetVT.SimpleTy != MVT::v2f64)
1593 return Register();
1594 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1595 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1596 }
1597 return Register();
1598}
1599
1600Register fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1601 switch (VT.SimpleTy) {
1602 case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op1);
1603 case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op1);
1604 case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op1);
1605 case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op1);
1606 default: return Register();
1607 }
1608}
1609
1610// FastEmit functions for ISD::FDIV.
1611
1612Register fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1613 if (RetVT.SimpleTy != MVT::f32)
1614 return Register();
1615 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1616 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1617 }
1618 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1619 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1620 }
1621 return Register();
1622}
1623
1624Register fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1625 if (RetVT.SimpleTy != MVT::f64)
1626 return Register();
1627 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
1628 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1629 }
1630 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1631 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1632 }
1633 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1634 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1635 }
1636 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1637 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1638 }
1639 return Register();
1640}
1641
1642Register fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1643 if (RetVT.SimpleTy != MVT::v4f32)
1644 return Register();
1645 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1646 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1647 }
1648 return Register();
1649}
1650
1651Register fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1652 if (RetVT.SimpleTy != MVT::v2f64)
1653 return Register();
1654 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1655 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1656 }
1657 return Register();
1658}
1659
1660Register fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1661 switch (VT.SimpleTy) {
1662 case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op1);
1663 case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op1);
1664 case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op1);
1665 case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op1);
1666 default: return Register();
1667 }
1668}
1669
1670// FastEmit functions for ISD::FMAXNUM.
1671
1672Register fastEmit_ISD_FMAXNUM_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1673 if (RetVT.SimpleTy != MVT::f32)
1674 return Register();
1675 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1676 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1677 }
1678 return Register();
1679}
1680
1681Register fastEmit_ISD_FMAXNUM_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1682 if (RetVT.SimpleTy != MVT::f64)
1683 return Register();
1684 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1685 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_D, RC: &Mips::FGR64RegClass, Op0, Op1);
1686 }
1687 return Register();
1688}
1689
1690Register fastEmit_ISD_FMAXNUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1691 switch (VT.SimpleTy) {
1692 case MVT::f32: return fastEmit_ISD_FMAXNUM_MVT_f32_rr(RetVT, Op0, Op1);
1693 case MVT::f64: return fastEmit_ISD_FMAXNUM_MVT_f64_rr(RetVT, Op0, Op1);
1694 default: return Register();
1695 }
1696}
1697
1698// FastEmit functions for ISD::FMAXNUM_IEEE.
1699
1700Register fastEmit_ISD_FMAXNUM_IEEE_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1701 if (RetVT.SimpleTy != MVT::f32)
1702 return Register();
1703 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1704 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1705 }
1706 return Register();
1707}
1708
1709Register fastEmit_ISD_FMAXNUM_IEEE_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1710 if (RetVT.SimpleTy != MVT::f64)
1711 return Register();
1712 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1713 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_D, RC: &Mips::FGR64RegClass, Op0, Op1);
1714 }
1715 return Register();
1716}
1717
1718Register fastEmit_ISD_FMAXNUM_IEEE_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1719 switch (VT.SimpleTy) {
1720 case MVT::f32: return fastEmit_ISD_FMAXNUM_IEEE_MVT_f32_rr(RetVT, Op0, Op1);
1721 case MVT::f64: return fastEmit_ISD_FMAXNUM_IEEE_MVT_f64_rr(RetVT, Op0, Op1);
1722 default: return Register();
1723 }
1724}
1725
1726// FastEmit functions for ISD::FMINNUM.
1727
1728Register fastEmit_ISD_FMINNUM_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1729 if (RetVT.SimpleTy != MVT::f32)
1730 return Register();
1731 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1732 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1733 }
1734 return Register();
1735}
1736
1737Register fastEmit_ISD_FMINNUM_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1738 if (RetVT.SimpleTy != MVT::f64)
1739 return Register();
1740 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1741 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_D, RC: &Mips::FGR64RegClass, Op0, Op1);
1742 }
1743 return Register();
1744}
1745
1746Register fastEmit_ISD_FMINNUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1747 switch (VT.SimpleTy) {
1748 case MVT::f32: return fastEmit_ISD_FMINNUM_MVT_f32_rr(RetVT, Op0, Op1);
1749 case MVT::f64: return fastEmit_ISD_FMINNUM_MVT_f64_rr(RetVT, Op0, Op1);
1750 default: return Register();
1751 }
1752}
1753
1754// FastEmit functions for ISD::FMINNUM_IEEE.
1755
1756Register fastEmit_ISD_FMINNUM_IEEE_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1757 if (RetVT.SimpleTy != MVT::f32)
1758 return Register();
1759 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1760 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1761 }
1762 return Register();
1763}
1764
1765Register fastEmit_ISD_FMINNUM_IEEE_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1766 if (RetVT.SimpleTy != MVT::f64)
1767 return Register();
1768 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1769 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_D, RC: &Mips::FGR64RegClass, Op0, Op1);
1770 }
1771 return Register();
1772}
1773
1774Register fastEmit_ISD_FMINNUM_IEEE_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1775 switch (VT.SimpleTy) {
1776 case MVT::f32: return fastEmit_ISD_FMINNUM_IEEE_MVT_f32_rr(RetVT, Op0, Op1);
1777 case MVT::f64: return fastEmit_ISD_FMINNUM_IEEE_MVT_f64_rr(RetVT, Op0, Op1);
1778 default: return Register();
1779 }
1780}
1781
1782// FastEmit functions for ISD::FMUL.
1783
1784Register fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1785 if (RetVT.SimpleTy != MVT::f32)
1786 return Register();
1787 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1788 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1789 }
1790 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1791 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1792 }
1793 return Register();
1794}
1795
1796Register fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1797 if (RetVT.SimpleTy != MVT::f64)
1798 return Register();
1799 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
1800 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1801 }
1802 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1803 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1804 }
1805 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1806 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1807 }
1808 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1809 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1810 }
1811 return Register();
1812}
1813
1814Register fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1815 if (RetVT.SimpleTy != MVT::v4f32)
1816 return Register();
1817 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1818 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1819 }
1820 return Register();
1821}
1822
1823Register fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1824 if (RetVT.SimpleTy != MVT::v2f64)
1825 return Register();
1826 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1827 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1828 }
1829 return Register();
1830}
1831
1832Register fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1833 switch (VT.SimpleTy) {
1834 case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op1);
1835 case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op1);
1836 case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op1);
1837 case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op1);
1838 default: return Register();
1839 }
1840}
1841
1842// FastEmit functions for ISD::FSUB.
1843
1844Register fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1845 if (RetVT.SimpleTy != MVT::f32)
1846 return Register();
1847 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1848 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1849 }
1850 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1851 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1852 }
1853 return Register();
1854}
1855
1856Register fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1857 if (RetVT.SimpleTy != MVT::f64)
1858 return Register();
1859 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
1860 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1861 }
1862 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1863 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1864 }
1865 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1866 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1867 }
1868 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1869 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1870 }
1871 return Register();
1872}
1873
1874Register fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1875 if (RetVT.SimpleTy != MVT::v4f32)
1876 return Register();
1877 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1878 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1879 }
1880 return Register();
1881}
1882
1883Register fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1884 if (RetVT.SimpleTy != MVT::v2f64)
1885 return Register();
1886 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1887 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1888 }
1889 return Register();
1890}
1891
1892Register fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1893 switch (VT.SimpleTy) {
1894 case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op1);
1895 case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op1);
1896 case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op1);
1897 case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op1);
1898 default: return Register();
1899 }
1900}
1901
1902// FastEmit functions for ISD::MUL.
1903
1904Register fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1905 if (RetVT.SimpleTy != MVT::i32)
1906 return Register();
1907 if ((Subtarget->inMips16Mode())) {
1908 return fastEmitInst_rr(MachineInstOpcode: Mips::MultRxRyRz16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
1909 }
1910 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1911 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
1912 }
1913 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1914 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
1915 }
1916 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1917 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_R6, RC: &Mips::GPR32RegClass, Op0, Op1);
1918 }
1919 if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
1920 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL, RC: &Mips::GPR32RegClass, Op0, Op1);
1921 }
1922 return Register();
1923}
1924
1925Register fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1926 if (RetVT.SimpleTy != MVT::i64)
1927 return Register();
1928 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1929 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUL_R6, RC: &Mips::GPR64RegClass, Op0, Op1);
1930 }
1931 if ((Subtarget->hasCnMips())) {
1932 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUL, RC: &Mips::GPR64RegClass, Op0, Op1);
1933 }
1934 return Register();
1935}
1936
1937Register fastEmit_ISD_MUL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1938 if (RetVT.SimpleTy != MVT::v16i8)
1939 return Register();
1940 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1941 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
1942 }
1943 return Register();
1944}
1945
1946Register fastEmit_ISD_MUL_MVT_v2i16_rr(MVT RetVT, Register Op0, Register Op1) {
1947 if (RetVT.SimpleTy != MVT::v2i16)
1948 return Register();
1949 if ((Subtarget->hasDSPR2())) {
1950 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_PH, RC: &Mips::DSPRRegClass, Op0, Op1);
1951 }
1952 return Register();
1953}
1954
1955Register fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1956 if (RetVT.SimpleTy != MVT::v8i16)
1957 return Register();
1958 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1959 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
1960 }
1961 return Register();
1962}
1963
1964Register fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
1965 if (RetVT.SimpleTy != MVT::v4i32)
1966 return Register();
1967 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1968 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1969 }
1970 return Register();
1971}
1972
1973Register fastEmit_ISD_MUL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
1974 if (RetVT.SimpleTy != MVT::v2i64)
1975 return Register();
1976 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1977 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1978 }
1979 return Register();
1980}
1981
1982Register fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1983 switch (VT.SimpleTy) {
1984 case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op1);
1985 case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op1);
1986 case MVT::v16i8: return fastEmit_ISD_MUL_MVT_v16i8_rr(RetVT, Op0, Op1);
1987 case MVT::v2i16: return fastEmit_ISD_MUL_MVT_v2i16_rr(RetVT, Op0, Op1);
1988 case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op1);
1989 case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op1);
1990 case MVT::v2i64: return fastEmit_ISD_MUL_MVT_v2i64_rr(RetVT, Op0, Op1);
1991 default: return Register();
1992 }
1993}
1994
1995// FastEmit functions for ISD::MULHS.
1996
1997Register fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1998 if (RetVT.SimpleTy != MVT::i32)
1999 return Register();
2000 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2001 return fastEmitInst_rr(MachineInstOpcode: Mips::MUH_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2002 }
2003 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2004 return fastEmitInst_rr(MachineInstOpcode: Mips::MUH, RC: &Mips::GPR32RegClass, Op0, Op1);
2005 }
2006 return Register();
2007}
2008
2009Register fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2010 if (RetVT.SimpleTy != MVT::i64)
2011 return Register();
2012 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2013 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUH, RC: &Mips::GPR64RegClass, Op0, Op1);
2014 }
2015 return Register();
2016}
2017
2018Register fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2019 switch (VT.SimpleTy) {
2020 case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op1);
2021 case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op1);
2022 default: return Register();
2023 }
2024}
2025
2026// FastEmit functions for ISD::MULHU.
2027
2028Register fastEmit_ISD_MULHU_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2029 if (RetVT.SimpleTy != MVT::i32)
2030 return Register();
2031 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2032 return fastEmitInst_rr(MachineInstOpcode: Mips::MUHU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2033 }
2034 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2035 return fastEmitInst_rr(MachineInstOpcode: Mips::MUHU, RC: &Mips::GPR32RegClass, Op0, Op1);
2036 }
2037 return Register();
2038}
2039
2040Register fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2041 if (RetVT.SimpleTy != MVT::i64)
2042 return Register();
2043 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2044 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUHU, RC: &Mips::GPR64RegClass, Op0, Op1);
2045 }
2046 return Register();
2047}
2048
2049Register fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2050 switch (VT.SimpleTy) {
2051 case MVT::i32: return fastEmit_ISD_MULHU_MVT_i32_rr(RetVT, Op0, Op1);
2052 case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op1);
2053 default: return Register();
2054 }
2055}
2056
2057// FastEmit functions for ISD::OR.
2058
2059Register fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2060 if (RetVT.SimpleTy != MVT::i32)
2061 return Register();
2062 if ((Subtarget->inMips16Mode())) {
2063 return fastEmitInst_rr(MachineInstOpcode: Mips::OrRxRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2064 }
2065 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2066 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2067 }
2068 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
2069 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2070 }
2071 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2072 return fastEmitInst_rr(MachineInstOpcode: Mips::OR, RC: &Mips::GPR32RegClass, Op0, Op1);
2073 }
2074 return Register();
2075}
2076
2077Register fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2078 if (RetVT.SimpleTy != MVT::i64)
2079 return Register();
2080 if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
2081 return fastEmitInst_rr(MachineInstOpcode: Mips::OR64, RC: &Mips::GPR64RegClass, Op0, Op1);
2082 }
2083 return Register();
2084}
2085
2086Register fastEmit_ISD_OR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2087 if (RetVT.SimpleTy != MVT::v16i8)
2088 return Register();
2089 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2090 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
2091 }
2092 return Register();
2093}
2094
2095Register fastEmit_ISD_OR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2096 if (RetVT.SimpleTy != MVT::v8i16)
2097 return Register();
2098 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2099 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
2100 }
2101 return Register();
2102}
2103
2104Register fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2105 if (RetVT.SimpleTy != MVT::v4i32)
2106 return Register();
2107 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2108 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
2109 }
2110 return Register();
2111}
2112
2113Register fastEmit_ISD_OR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2114 if (RetVT.SimpleTy != MVT::v2i64)
2115 return Register();
2116 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2117 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
2118 }
2119 return Register();
2120}
2121
2122Register fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2123 switch (VT.SimpleTy) {
2124 case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op1);
2125 case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op1);
2126 case MVT::v16i8: return fastEmit_ISD_OR_MVT_v16i8_rr(RetVT, Op0, Op1);
2127 case MVT::v8i16: return fastEmit_ISD_OR_MVT_v8i16_rr(RetVT, Op0, Op1);
2128 case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op1);
2129 case MVT::v2i64: return fastEmit_ISD_OR_MVT_v2i64_rr(RetVT, Op0, Op1);
2130 default: return Register();
2131 }
2132}
2133
2134// FastEmit functions for ISD::ROTR.
2135
2136Register fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2137 if (RetVT.SimpleTy != MVT::i32)
2138 return Register();
2139 if ((Subtarget->inMicroMipsMode())) {
2140 return fastEmitInst_rr(MachineInstOpcode: Mips::ROTRV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2141 }
2142 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2143 return fastEmitInst_rr(MachineInstOpcode: Mips::ROTRV, RC: &Mips::GPR32RegClass, Op0, Op1);
2144 }
2145 return Register();
2146}
2147
2148Register fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2149 switch (VT.SimpleTy) {
2150 case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op1);
2151 default: return Register();
2152 }
2153}
2154
2155// FastEmit functions for ISD::SDIV.
2156
2157Register fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2158 if (RetVT.SimpleTy != MVT::i32)
2159 return Register();
2160 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2161 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2162 }
2163 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2164 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV, RC: &Mips::GPR32RegClass, Op0, Op1);
2165 }
2166 return Register();
2167}
2168
2169Register fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2170 if (RetVT.SimpleTy != MVT::i64)
2171 return Register();
2172 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2173 return fastEmitInst_rr(MachineInstOpcode: Mips::DDIV, RC: &Mips::GPR64RegClass, Op0, Op1);
2174 }
2175 return Register();
2176}
2177
2178Register fastEmit_ISD_SDIV_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2179 if (RetVT.SimpleTy != MVT::v16i8)
2180 return Register();
2181 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2182 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2183 }
2184 return Register();
2185}
2186
2187Register fastEmit_ISD_SDIV_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2188 if (RetVT.SimpleTy != MVT::v8i16)
2189 return Register();
2190 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2191 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2192 }
2193 return Register();
2194}
2195
2196Register fastEmit_ISD_SDIV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2197 if (RetVT.SimpleTy != MVT::v4i32)
2198 return Register();
2199 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2200 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2201 }
2202 return Register();
2203}
2204
2205Register fastEmit_ISD_SDIV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2206 if (RetVT.SimpleTy != MVT::v2i64)
2207 return Register();
2208 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2209 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2210 }
2211 return Register();
2212}
2213
2214Register fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2215 switch (VT.SimpleTy) {
2216 case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op1);
2217 case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op1);
2218 case MVT::v16i8: return fastEmit_ISD_SDIV_MVT_v16i8_rr(RetVT, Op0, Op1);
2219 case MVT::v8i16: return fastEmit_ISD_SDIV_MVT_v8i16_rr(RetVT, Op0, Op1);
2220 case MVT::v4i32: return fastEmit_ISD_SDIV_MVT_v4i32_rr(RetVT, Op0, Op1);
2221 case MVT::v2i64: return fastEmit_ISD_SDIV_MVT_v2i64_rr(RetVT, Op0, Op1);
2222 default: return Register();
2223 }
2224}
2225
2226// FastEmit functions for ISD::SHL.
2227
2228Register fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2229 if (RetVT.SimpleTy != MVT::i32)
2230 return Register();
2231 if ((Subtarget->inMicroMipsMode())) {
2232 return fastEmitInst_rr(MachineInstOpcode: Mips::SLLV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2233 }
2234 if ((Subtarget->inMips16Mode())) {
2235 return fastEmitInst_rr(MachineInstOpcode: Mips::SllvRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2236 }
2237 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2238 return fastEmitInst_rr(MachineInstOpcode: Mips::SLLV, RC: &Mips::GPR32RegClass, Op0, Op1);
2239 }
2240 return Register();
2241}
2242
2243Register fastEmit_ISD_SHL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2244 if (RetVT.SimpleTy != MVT::v16i8)
2245 return Register();
2246 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2247 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2248 }
2249 return Register();
2250}
2251
2252Register fastEmit_ISD_SHL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2253 if (RetVT.SimpleTy != MVT::v8i16)
2254 return Register();
2255 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2256 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2257 }
2258 return Register();
2259}
2260
2261Register fastEmit_ISD_SHL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2262 if (RetVT.SimpleTy != MVT::v4i32)
2263 return Register();
2264 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2265 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2266 }
2267 return Register();
2268}
2269
2270Register fastEmit_ISD_SHL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2271 if (RetVT.SimpleTy != MVT::v2i64)
2272 return Register();
2273 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2274 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2275 }
2276 return Register();
2277}
2278
2279Register fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2280 switch (VT.SimpleTy) {
2281 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op1);
2282 case MVT::v16i8: return fastEmit_ISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op1);
2283 case MVT::v8i16: return fastEmit_ISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op1);
2284 case MVT::v4i32: return fastEmit_ISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op1);
2285 case MVT::v2i64: return fastEmit_ISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op1);
2286 default: return Register();
2287 }
2288}
2289
2290// FastEmit functions for ISD::SMAX.
2291
2292Register fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2293 if (RetVT.SimpleTy != MVT::v16i8)
2294 return Register();
2295 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2296 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2297 }
2298 return Register();
2299}
2300
2301Register fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2302 if (RetVT.SimpleTy != MVT::v8i16)
2303 return Register();
2304 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2305 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2306 }
2307 return Register();
2308}
2309
2310Register fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2311 if (RetVT.SimpleTy != MVT::v4i32)
2312 return Register();
2313 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2314 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2315 }
2316 return Register();
2317}
2318
2319Register fastEmit_ISD_SMAX_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2320 if (RetVT.SimpleTy != MVT::v2i64)
2321 return Register();
2322 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2323 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2324 }
2325 return Register();
2326}
2327
2328Register fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2329 switch (VT.SimpleTy) {
2330 case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
2331 case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
2332 case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
2333 case MVT::v2i64: return fastEmit_ISD_SMAX_MVT_v2i64_rr(RetVT, Op0, Op1);
2334 default: return Register();
2335 }
2336}
2337
2338// FastEmit functions for ISD::SMIN.
2339
2340Register fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2341 if (RetVT.SimpleTy != MVT::v16i8)
2342 return Register();
2343 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2344 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2345 }
2346 return Register();
2347}
2348
2349Register fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2350 if (RetVT.SimpleTy != MVT::v8i16)
2351 return Register();
2352 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2353 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2354 }
2355 return Register();
2356}
2357
2358Register fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2359 if (RetVT.SimpleTy != MVT::v4i32)
2360 return Register();
2361 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2362 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2363 }
2364 return Register();
2365}
2366
2367Register fastEmit_ISD_SMIN_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2368 if (RetVT.SimpleTy != MVT::v2i64)
2369 return Register();
2370 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2371 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2372 }
2373 return Register();
2374}
2375
2376Register fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2377 switch (VT.SimpleTy) {
2378 case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
2379 case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
2380 case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
2381 case MVT::v2i64: return fastEmit_ISD_SMIN_MVT_v2i64_rr(RetVT, Op0, Op1);
2382 default: return Register();
2383 }
2384}
2385
2386// FastEmit functions for ISD::SRA.
2387
2388Register fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2389 if (RetVT.SimpleTy != MVT::i32)
2390 return Register();
2391 if ((Subtarget->inMicroMipsMode())) {
2392 return fastEmitInst_rr(MachineInstOpcode: Mips::SRAV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2393 }
2394 if ((Subtarget->inMips16Mode())) {
2395 return fastEmitInst_rr(MachineInstOpcode: Mips::SravRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2396 }
2397 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2398 return fastEmitInst_rr(MachineInstOpcode: Mips::SRAV, RC: &Mips::GPR32RegClass, Op0, Op1);
2399 }
2400 return Register();
2401}
2402
2403Register fastEmit_ISD_SRA_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2404 if (RetVT.SimpleTy != MVT::v16i8)
2405 return Register();
2406 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2407 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2408 }
2409 return Register();
2410}
2411
2412Register fastEmit_ISD_SRA_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2413 if (RetVT.SimpleTy != MVT::v8i16)
2414 return Register();
2415 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2416 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2417 }
2418 return Register();
2419}
2420
2421Register fastEmit_ISD_SRA_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2422 if (RetVT.SimpleTy != MVT::v4i32)
2423 return Register();
2424 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2425 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2426 }
2427 return Register();
2428}
2429
2430Register fastEmit_ISD_SRA_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2431 if (RetVT.SimpleTy != MVT::v2i64)
2432 return Register();
2433 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2434 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2435 }
2436 return Register();
2437}
2438
2439Register fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2440 switch (VT.SimpleTy) {
2441 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op1);
2442 case MVT::v16i8: return fastEmit_ISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op1);
2443 case MVT::v8i16: return fastEmit_ISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op1);
2444 case MVT::v4i32: return fastEmit_ISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op1);
2445 case MVT::v2i64: return fastEmit_ISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op1);
2446 default: return Register();
2447 }
2448}
2449
2450// FastEmit functions for ISD::SREM.
2451
2452Register fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2453 if (RetVT.SimpleTy != MVT::i32)
2454 return Register();
2455 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2456 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2457 }
2458 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2459 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD, RC: &Mips::GPR32RegClass, Op0, Op1);
2460 }
2461 return Register();
2462}
2463
2464Register fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2465 if (RetVT.SimpleTy != MVT::i64)
2466 return Register();
2467 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2468 return fastEmitInst_rr(MachineInstOpcode: Mips::DMOD, RC: &Mips::GPR64RegClass, Op0, Op1);
2469 }
2470 return Register();
2471}
2472
2473Register fastEmit_ISD_SREM_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2474 if (RetVT.SimpleTy != MVT::v16i8)
2475 return Register();
2476 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2477 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2478 }
2479 return Register();
2480}
2481
2482Register fastEmit_ISD_SREM_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2483 if (RetVT.SimpleTy != MVT::v8i16)
2484 return Register();
2485 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2486 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2487 }
2488 return Register();
2489}
2490
2491Register fastEmit_ISD_SREM_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2492 if (RetVT.SimpleTy != MVT::v4i32)
2493 return Register();
2494 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2495 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2496 }
2497 return Register();
2498}
2499
2500Register fastEmit_ISD_SREM_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2501 if (RetVT.SimpleTy != MVT::v2i64)
2502 return Register();
2503 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2504 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2505 }
2506 return Register();
2507}
2508
2509Register fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2510 switch (VT.SimpleTy) {
2511 case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op1);
2512 case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op1);
2513 case MVT::v16i8: return fastEmit_ISD_SREM_MVT_v16i8_rr(RetVT, Op0, Op1);
2514 case MVT::v8i16: return fastEmit_ISD_SREM_MVT_v8i16_rr(RetVT, Op0, Op1);
2515 case MVT::v4i32: return fastEmit_ISD_SREM_MVT_v4i32_rr(RetVT, Op0, Op1);
2516 case MVT::v2i64: return fastEmit_ISD_SREM_MVT_v2i64_rr(RetVT, Op0, Op1);
2517 default: return Register();
2518 }
2519}
2520
2521// FastEmit functions for ISD::SRL.
2522
2523Register fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2524 if (RetVT.SimpleTy != MVT::i32)
2525 return Register();
2526 if ((Subtarget->inMicroMipsMode())) {
2527 return fastEmitInst_rr(MachineInstOpcode: Mips::SRLV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2528 }
2529 if ((Subtarget->inMips16Mode())) {
2530 return fastEmitInst_rr(MachineInstOpcode: Mips::SrlvRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2531 }
2532 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2533 return fastEmitInst_rr(MachineInstOpcode: Mips::SRLV, RC: &Mips::GPR32RegClass, Op0, Op1);
2534 }
2535 return Register();
2536}
2537
2538Register fastEmit_ISD_SRL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2539 if (RetVT.SimpleTy != MVT::v16i8)
2540 return Register();
2541 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2542 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2543 }
2544 return Register();
2545}
2546
2547Register fastEmit_ISD_SRL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2548 if (RetVT.SimpleTy != MVT::v8i16)
2549 return Register();
2550 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2551 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2552 }
2553 return Register();
2554}
2555
2556Register fastEmit_ISD_SRL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2557 if (RetVT.SimpleTy != MVT::v4i32)
2558 return Register();
2559 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2560 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2561 }
2562 return Register();
2563}
2564
2565Register fastEmit_ISD_SRL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2566 if (RetVT.SimpleTy != MVT::v2i64)
2567 return Register();
2568 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2569 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2570 }
2571 return Register();
2572}
2573
2574Register fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2575 switch (VT.SimpleTy) {
2576 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op1);
2577 case MVT::v16i8: return fastEmit_ISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op1);
2578 case MVT::v8i16: return fastEmit_ISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op1);
2579 case MVT::v4i32: return fastEmit_ISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op1);
2580 case MVT::v2i64: return fastEmit_ISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op1);
2581 default: return Register();
2582 }
2583}
2584
2585// FastEmit functions for ISD::STRICT_FADD.
2586
2587Register fastEmit_ISD_STRICT_FADD_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
2588 if (RetVT.SimpleTy != MVT::f32)
2589 return Register();
2590 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2591 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_S, RC: &Mips::FGR32RegClass, Op0, Op1);
2592 }
2593 return Register();
2594}
2595
2596Register fastEmit_ISD_STRICT_FADD_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
2597 if (RetVT.SimpleTy != MVT::f64)
2598 return Register();
2599 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2600 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
2601 }
2602 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
2603 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
2604 }
2605 return Register();
2606}
2607
2608Register fastEmit_ISD_STRICT_FADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2609 switch (VT.SimpleTy) {
2610 case MVT::f32: return fastEmit_ISD_STRICT_FADD_MVT_f32_rr(RetVT, Op0, Op1);
2611 case MVT::f64: return fastEmit_ISD_STRICT_FADD_MVT_f64_rr(RetVT, Op0, Op1);
2612 default: return Register();
2613 }
2614}
2615
2616// FastEmit functions for ISD::STRICT_FDIV.
2617
2618Register fastEmit_ISD_STRICT_FDIV_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
2619 if (RetVT.SimpleTy != MVT::f32)
2620 return Register();
2621 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2622 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_S, RC: &Mips::FGR32RegClass, Op0, Op1);
2623 }
2624 return Register();
2625}
2626
2627Register fastEmit_ISD_STRICT_FDIV_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
2628 if (RetVT.SimpleTy != MVT::f64)
2629 return Register();
2630 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2631 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
2632 }
2633 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
2634 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
2635 }
2636 return Register();
2637}
2638
2639Register fastEmit_ISD_STRICT_FDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2640 switch (VT.SimpleTy) {
2641 case MVT::f32: return fastEmit_ISD_STRICT_FDIV_MVT_f32_rr(RetVT, Op0, Op1);
2642 case MVT::f64: return fastEmit_ISD_STRICT_FDIV_MVT_f64_rr(RetVT, Op0, Op1);
2643 default: return Register();
2644 }
2645}
2646
2647// FastEmit functions for ISD::STRICT_FMUL.
2648
2649Register fastEmit_ISD_STRICT_FMUL_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
2650 if (RetVT.SimpleTy != MVT::f32)
2651 return Register();
2652 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2653 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_S, RC: &Mips::FGR32RegClass, Op0, Op1);
2654 }
2655 return Register();
2656}
2657
2658Register fastEmit_ISD_STRICT_FMUL_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
2659 if (RetVT.SimpleTy != MVT::f64)
2660 return Register();
2661 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2662 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
2663 }
2664 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
2665 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
2666 }
2667 return Register();
2668}
2669
2670Register fastEmit_ISD_STRICT_FMUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2671 switch (VT.SimpleTy) {
2672 case MVT::f32: return fastEmit_ISD_STRICT_FMUL_MVT_f32_rr(RetVT, Op0, Op1);
2673 case MVT::f64: return fastEmit_ISD_STRICT_FMUL_MVT_f64_rr(RetVT, Op0, Op1);
2674 default: return Register();
2675 }
2676}
2677
2678// FastEmit functions for ISD::STRICT_FSUB.
2679
2680Register fastEmit_ISD_STRICT_FSUB_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
2681 if (RetVT.SimpleTy != MVT::f32)
2682 return Register();
2683 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2684 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_S, RC: &Mips::FGR32RegClass, Op0, Op1);
2685 }
2686 return Register();
2687}
2688
2689Register fastEmit_ISD_STRICT_FSUB_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
2690 if (RetVT.SimpleTy != MVT::f64)
2691 return Register();
2692 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2693 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
2694 }
2695 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
2696 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
2697 }
2698 return Register();
2699}
2700
2701Register fastEmit_ISD_STRICT_FSUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2702 switch (VT.SimpleTy) {
2703 case MVT::f32: return fastEmit_ISD_STRICT_FSUB_MVT_f32_rr(RetVT, Op0, Op1);
2704 case MVT::f64: return fastEmit_ISD_STRICT_FSUB_MVT_f64_rr(RetVT, Op0, Op1);
2705 default: return Register();
2706 }
2707}
2708
2709// FastEmit functions for ISD::SUB.
2710
2711Register fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2712 if (RetVT.SimpleTy != MVT::i32)
2713 return Register();
2714 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2715 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBU16_MMR6, RC: &Mips::GPRMM16RegClass, Op0, Op1);
2716 }
2717 if ((Subtarget->inMips16Mode())) {
2718 return fastEmitInst_rr(MachineInstOpcode: Mips::SubuRxRyRz16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2719 }
2720 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
2721 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2722 }
2723 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2724 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu, RC: &Mips::GPR32RegClass, Op0, Op1);
2725 }
2726 return Register();
2727}
2728
2729Register fastEmit_ISD_SUB_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2730 if (RetVT.SimpleTy != MVT::i64)
2731 return Register();
2732 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2733 return fastEmitInst_rr(MachineInstOpcode: Mips::DSUBu, RC: &Mips::GPR64RegClass, Op0, Op1);
2734 }
2735 return Register();
2736}
2737
2738Register fastEmit_ISD_SUB_MVT_v4i8_rr(MVT RetVT, Register Op0, Register Op1) {
2739 if (RetVT.SimpleTy != MVT::v4i8)
2740 return Register();
2741 if ((Subtarget->hasDSP())) {
2742 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBU_QB, RC: &Mips::DSPRRegClass, Op0, Op1);
2743 }
2744 return Register();
2745}
2746
2747Register fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2748 if (RetVT.SimpleTy != MVT::v16i8)
2749 return Register();
2750 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2751 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2752 }
2753 return Register();
2754}
2755
2756Register fastEmit_ISD_SUB_MVT_v2i16_rr(MVT RetVT, Register Op0, Register Op1) {
2757 if (RetVT.SimpleTy != MVT::v2i16)
2758 return Register();
2759 if ((Subtarget->hasDSP())) {
2760 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBQ_PH, RC: &Mips::DSPRRegClass, Op0, Op1);
2761 }
2762 return Register();
2763}
2764
2765Register fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2766 if (RetVT.SimpleTy != MVT::v8i16)
2767 return Register();
2768 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2769 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2770 }
2771 return Register();
2772}
2773
2774Register fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2775 if (RetVT.SimpleTy != MVT::v4i32)
2776 return Register();
2777 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2778 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2779 }
2780 return Register();
2781}
2782
2783Register fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2784 if (RetVT.SimpleTy != MVT::v2i64)
2785 return Register();
2786 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2787 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2788 }
2789 return Register();
2790}
2791
2792Register fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2793 switch (VT.SimpleTy) {
2794 case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op1);
2795 case MVT::i64: return fastEmit_ISD_SUB_MVT_i64_rr(RetVT, Op0, Op1);
2796 case MVT::v4i8: return fastEmit_ISD_SUB_MVT_v4i8_rr(RetVT, Op0, Op1);
2797 case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op1);
2798 case MVT::v2i16: return fastEmit_ISD_SUB_MVT_v2i16_rr(RetVT, Op0, Op1);
2799 case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op1);
2800 case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op1);
2801 case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op1);
2802 default: return Register();
2803 }
2804}
2805
2806// FastEmit functions for ISD::SUBC.
2807
2808Register fastEmit_ISD_SUBC_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2809 if (RetVT.SimpleTy != MVT::i32)
2810 return Register();
2811 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2812 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2813 }
2814 if ((Subtarget->inMicroMipsMode())) {
2815 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2816 }
2817 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2818 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu, RC: &Mips::GPR32RegClass, Op0, Op1);
2819 }
2820 return Register();
2821}
2822
2823Register fastEmit_ISD_SUBC_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2824 if (RetVT.SimpleTy != MVT::i64)
2825 return Register();
2826 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())) {
2827 return fastEmitInst_rr(MachineInstOpcode: Mips::DSUBu, RC: &Mips::GPR64RegClass, Op0, Op1);
2828 }
2829 return Register();
2830}
2831
2832Register fastEmit_ISD_SUBC_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2833 switch (VT.SimpleTy) {
2834 case MVT::i32: return fastEmit_ISD_SUBC_MVT_i32_rr(RetVT, Op0, Op1);
2835 case MVT::i64: return fastEmit_ISD_SUBC_MVT_i64_rr(RetVT, Op0, Op1);
2836 default: return Register();
2837 }
2838}
2839
2840// FastEmit functions for ISD::UDIV.
2841
2842Register fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2843 if (RetVT.SimpleTy != MVT::i32)
2844 return Register();
2845 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2846 return fastEmitInst_rr(MachineInstOpcode: Mips::DIVU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2847 }
2848 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2849 return fastEmitInst_rr(MachineInstOpcode: Mips::DIVU, RC: &Mips::GPR32RegClass, Op0, Op1);
2850 }
2851 return Register();
2852}
2853
2854Register fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2855 if (RetVT.SimpleTy != MVT::i64)
2856 return Register();
2857 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2858 return fastEmitInst_rr(MachineInstOpcode: Mips::DDIVU, RC: &Mips::GPR64RegClass, Op0, Op1);
2859 }
2860 return Register();
2861}
2862
2863Register fastEmit_ISD_UDIV_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2864 if (RetVT.SimpleTy != MVT::v16i8)
2865 return Register();
2866 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2867 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2868 }
2869 return Register();
2870}
2871
2872Register fastEmit_ISD_UDIV_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2873 if (RetVT.SimpleTy != MVT::v8i16)
2874 return Register();
2875 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2876 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2877 }
2878 return Register();
2879}
2880
2881Register fastEmit_ISD_UDIV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2882 if (RetVT.SimpleTy != MVT::v4i32)
2883 return Register();
2884 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2885 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2886 }
2887 return Register();
2888}
2889
2890Register fastEmit_ISD_UDIV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2891 if (RetVT.SimpleTy != MVT::v2i64)
2892 return Register();
2893 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2894 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2895 }
2896 return Register();
2897}
2898
2899Register fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2900 switch (VT.SimpleTy) {
2901 case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op1);
2902 case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op1);
2903 case MVT::v16i8: return fastEmit_ISD_UDIV_MVT_v16i8_rr(RetVT, Op0, Op1);
2904 case MVT::v8i16: return fastEmit_ISD_UDIV_MVT_v8i16_rr(RetVT, Op0, Op1);
2905 case MVT::v4i32: return fastEmit_ISD_UDIV_MVT_v4i32_rr(RetVT, Op0, Op1);
2906 case MVT::v2i64: return fastEmit_ISD_UDIV_MVT_v2i64_rr(RetVT, Op0, Op1);
2907 default: return Register();
2908 }
2909}
2910
2911// FastEmit functions for ISD::UMAX.
2912
2913Register fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2914 if (RetVT.SimpleTy != MVT::v16i8)
2915 return Register();
2916 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2917 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2918 }
2919 return Register();
2920}
2921
2922Register fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2923 if (RetVT.SimpleTy != MVT::v8i16)
2924 return Register();
2925 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2926 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2927 }
2928 return Register();
2929}
2930
2931Register fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2932 if (RetVT.SimpleTy != MVT::v4i32)
2933 return Register();
2934 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2935 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2936 }
2937 return Register();
2938}
2939
2940Register fastEmit_ISD_UMAX_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2941 if (RetVT.SimpleTy != MVT::v2i64)
2942 return Register();
2943 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2944 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2945 }
2946 return Register();
2947}
2948
2949Register fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2950 switch (VT.SimpleTy) {
2951 case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
2952 case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
2953 case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
2954 case MVT::v2i64: return fastEmit_ISD_UMAX_MVT_v2i64_rr(RetVT, Op0, Op1);
2955 default: return Register();
2956 }
2957}
2958
2959// FastEmit functions for ISD::UMIN.
2960
2961Register fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2962 if (RetVT.SimpleTy != MVT::v16i8)
2963 return Register();
2964 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2965 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2966 }
2967 return Register();
2968}
2969
2970Register fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2971 if (RetVT.SimpleTy != MVT::v8i16)
2972 return Register();
2973 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2974 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2975 }
2976 return Register();
2977}
2978
2979Register fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2980 if (RetVT.SimpleTy != MVT::v4i32)
2981 return Register();
2982 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2983 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2984 }
2985 return Register();
2986}
2987
2988Register fastEmit_ISD_UMIN_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2989 if (RetVT.SimpleTy != MVT::v2i64)
2990 return Register();
2991 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2992 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2993 }
2994 return Register();
2995}
2996
2997Register fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2998 switch (VT.SimpleTy) {
2999 case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
3000 case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
3001 case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
3002 case MVT::v2i64: return fastEmit_ISD_UMIN_MVT_v2i64_rr(RetVT, Op0, Op1);
3003 default: return Register();
3004 }
3005}
3006
3007// FastEmit functions for ISD::UREM.
3008
3009Register fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3010 if (RetVT.SimpleTy != MVT::i32)
3011 return Register();
3012 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
3013 return fastEmitInst_rr(MachineInstOpcode: Mips::MODU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
3014 }
3015 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3016 return fastEmitInst_rr(MachineInstOpcode: Mips::MODU, RC: &Mips::GPR32RegClass, Op0, Op1);
3017 }
3018 return Register();
3019}
3020
3021Register fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3022 if (RetVT.SimpleTy != MVT::i64)
3023 return Register();
3024 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3025 return fastEmitInst_rr(MachineInstOpcode: Mips::DMODU, RC: &Mips::GPR64RegClass, Op0, Op1);
3026 }
3027 return Register();
3028}
3029
3030Register fastEmit_ISD_UREM_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3031 if (RetVT.SimpleTy != MVT::v16i8)
3032 return Register();
3033 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3034 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3035 }
3036 return Register();
3037}
3038
3039Register fastEmit_ISD_UREM_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3040 if (RetVT.SimpleTy != MVT::v8i16)
3041 return Register();
3042 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3043 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3044 }
3045 return Register();
3046}
3047
3048Register fastEmit_ISD_UREM_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3049 if (RetVT.SimpleTy != MVT::v4i32)
3050 return Register();
3051 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3052 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3053 }
3054 return Register();
3055}
3056
3057Register fastEmit_ISD_UREM_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3058 if (RetVT.SimpleTy != MVT::v2i64)
3059 return Register();
3060 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3061 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3062 }
3063 return Register();
3064}
3065
3066Register fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3067 switch (VT.SimpleTy) {
3068 case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op1);
3069 case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op1);
3070 case MVT::v16i8: return fastEmit_ISD_UREM_MVT_v16i8_rr(RetVT, Op0, Op1);
3071 case MVT::v8i16: return fastEmit_ISD_UREM_MVT_v8i16_rr(RetVT, Op0, Op1);
3072 case MVT::v4i32: return fastEmit_ISD_UREM_MVT_v4i32_rr(RetVT, Op0, Op1);
3073 case MVT::v2i64: return fastEmit_ISD_UREM_MVT_v2i64_rr(RetVT, Op0, Op1);
3074 default: return Register();
3075 }
3076}
3077
3078// FastEmit functions for ISD::XOR.
3079
3080Register fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3081 if (RetVT.SimpleTy != MVT::i32)
3082 return Register();
3083 if ((Subtarget->inMips16Mode())) {
3084 return fastEmitInst_rr(MachineInstOpcode: Mips::XorRxRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
3085 }
3086 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
3087 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
3088 }
3089 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
3090 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
3091 }
3092 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3093 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR, RC: &Mips::GPR32RegClass, Op0, Op1);
3094 }
3095 return Register();
3096}
3097
3098Register fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3099 if (RetVT.SimpleTy != MVT::i64)
3100 return Register();
3101 if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
3102 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR64, RC: &Mips::GPR64RegClass, Op0, Op1);
3103 }
3104 return Register();
3105}
3106
3107Register fastEmit_ISD_XOR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3108 if (RetVT.SimpleTy != MVT::v16i8)
3109 return Register();
3110 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3111 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
3112 }
3113 return Register();
3114}
3115
3116Register fastEmit_ISD_XOR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3117 if (RetVT.SimpleTy != MVT::v8i16)
3118 return Register();
3119 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3120 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
3121 }
3122 return Register();
3123}
3124
3125Register fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3126 if (RetVT.SimpleTy != MVT::v4i32)
3127 return Register();
3128 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3129 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
3130 }
3131 return Register();
3132}
3133
3134Register fastEmit_ISD_XOR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3135 if (RetVT.SimpleTy != MVT::v2i64)
3136 return Register();
3137 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3138 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
3139 }
3140 return Register();
3141}
3142
3143Register fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3144 switch (VT.SimpleTy) {
3145 case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op1);
3146 case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op1);
3147 case MVT::v16i8: return fastEmit_ISD_XOR_MVT_v16i8_rr(RetVT, Op0, Op1);
3148 case MVT::v8i16: return fastEmit_ISD_XOR_MVT_v8i16_rr(RetVT, Op0, Op1);
3149 case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op1);
3150 case MVT::v2i64: return fastEmit_ISD_XOR_MVT_v2i64_rr(RetVT, Op0, Op1);
3151 default: return Register();
3152 }
3153}
3154
3155// FastEmit functions for MipsISD::BuildPairF64.
3156
3157Register fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3158 if (RetVT.SimpleTy != MVT::f64)
3159 return Register();
3160 if ((Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMips16Mode())) {
3161 return fastEmitInst_rr(MachineInstOpcode: Mips::BuildPairF64_64, RC: &Mips::FGR64RegClass, Op0, Op1);
3162 }
3163 if ((!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode())) {
3164 return fastEmitInst_rr(MachineInstOpcode: Mips::BuildPairF64, RC: &Mips::AFGR64RegClass, Op0, Op1);
3165 }
3166 return Register();
3167}
3168
3169Register fastEmit_MipsISD_BuildPairF64_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3170 switch (VT.SimpleTy) {
3171 case MVT::i32: return fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(RetVT, Op0, Op1);
3172 default: return Register();
3173 }
3174}
3175
3176// FastEmit functions for MipsISD::DivRem.
3177
3178Register fastEmit_MipsISD_DivRem_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3179 if (RetVT.SimpleTy != MVT::Untyped)
3180 return Register();
3181 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3182 return fastEmitInst_rr(MachineInstOpcode: Mips::SDIV_MM_Pseudo, RC: &Mips::ACC64RegClass, Op0, Op1);
3183 }
3184 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3185 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoSDIV, RC: &Mips::ACC64RegClass, Op0, Op1);
3186 }
3187 return Register();
3188}
3189
3190Register fastEmit_MipsISD_DivRem_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3191 if (RetVT.SimpleTy != MVT::Untyped)
3192 return Register();
3193 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (!Subtarget->isR5900())) {
3194 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDSDIV, RC: &Mips::ACC128RegClass, Op0, Op1);
3195 }
3196 return Register();
3197}
3198
3199Register fastEmit_MipsISD_DivRem_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3200 switch (VT.SimpleTy) {
3201 case MVT::i32: return fastEmit_MipsISD_DivRem_MVT_i32_rr(RetVT, Op0, Op1);
3202 case MVT::i64: return fastEmit_MipsISD_DivRem_MVT_i64_rr(RetVT, Op0, Op1);
3203 default: return Register();
3204 }
3205}
3206
3207// FastEmit functions for MipsISD::DivRem16.
3208
3209Register fastEmit_MipsISD_DivRem16_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3210 if (RetVT.SimpleTy != MVT::isVoid)
3211 return Register();
3212 if ((Subtarget->inMips16Mode())) {
3213 return fastEmitInst_rr(MachineInstOpcode: Mips::DivRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
3214 }
3215 return Register();
3216}
3217
3218Register fastEmit_MipsISD_DivRem16_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3219 switch (VT.SimpleTy) {
3220 case MVT::i32: return fastEmit_MipsISD_DivRem16_MVT_i32_rr(RetVT, Op0, Op1);
3221 default: return Register();
3222 }
3223}
3224
3225// FastEmit functions for MipsISD::DivRemU.
3226
3227Register fastEmit_MipsISD_DivRemU_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3228 if (RetVT.SimpleTy != MVT::Untyped)
3229 return Register();
3230 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3231 return fastEmitInst_rr(MachineInstOpcode: Mips::UDIV_MM_Pseudo, RC: &Mips::ACC64RegClass, Op0, Op1);
3232 }
3233 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3234 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoUDIV, RC: &Mips::ACC64RegClass, Op0, Op1);
3235 }
3236 return Register();
3237}
3238
3239Register fastEmit_MipsISD_DivRemU_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3240 if (RetVT.SimpleTy != MVT::Untyped)
3241 return Register();
3242 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (!Subtarget->isR5900())) {
3243 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDUDIV, RC: &Mips::ACC128RegClass, Op0, Op1);
3244 }
3245 return Register();
3246}
3247
3248Register fastEmit_MipsISD_DivRemU_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3249 switch (VT.SimpleTy) {
3250 case MVT::i32: return fastEmit_MipsISD_DivRemU_MVT_i32_rr(RetVT, Op0, Op1);
3251 case MVT::i64: return fastEmit_MipsISD_DivRemU_MVT_i64_rr(RetVT, Op0, Op1);
3252 default: return Register();
3253 }
3254}
3255
3256// FastEmit functions for MipsISD::DivRemU16.
3257
3258Register fastEmit_MipsISD_DivRemU16_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3259 if (RetVT.SimpleTy != MVT::isVoid)
3260 return Register();
3261 if ((Subtarget->inMips16Mode())) {
3262 return fastEmitInst_rr(MachineInstOpcode: Mips::DivuRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
3263 }
3264 return Register();
3265}
3266
3267Register fastEmit_MipsISD_DivRemU16_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3268 switch (VT.SimpleTy) {
3269 case MVT::i32: return fastEmit_MipsISD_DivRemU16_MVT_i32_rr(RetVT, Op0, Op1);
3270 default: return Register();
3271 }
3272}
3273
3274// FastEmit functions for MipsISD::EH_RETURN.
3275
3276Register fastEmit_MipsISD_EH_RETURN_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3277 if (RetVT.SimpleTy != MVT::isVoid)
3278 return Register();
3279 return fastEmitInst_rr(MachineInstOpcode: Mips::MIPSeh_return32, RC: &Mips::GPR32RegClass, Op0, Op1);
3280}
3281
3282Register fastEmit_MipsISD_EH_RETURN_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3283 if (RetVT.SimpleTy != MVT::isVoid)
3284 return Register();
3285 return fastEmitInst_rr(MachineInstOpcode: Mips::MIPSeh_return64, RC: &Mips::GPR64RegClass, Op0, Op1);
3286}
3287
3288Register fastEmit_MipsISD_EH_RETURN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3289 switch (VT.SimpleTy) {
3290 case MVT::i32: return fastEmit_MipsISD_EH_RETURN_MVT_i32_rr(RetVT, Op0, Op1);
3291 case MVT::i64: return fastEmit_MipsISD_EH_RETURN_MVT_i64_rr(RetVT, Op0, Op1);
3292 default: return Register();
3293 }
3294}
3295
3296// FastEmit functions for MipsISD::ILVEV.
3297
3298Register fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3299 if (RetVT.SimpleTy != MVT::v16i8)
3300 return Register();
3301 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3302 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3303 }
3304 return Register();
3305}
3306
3307Register fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3308 if (RetVT.SimpleTy != MVT::v8i16)
3309 return Register();
3310 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3311 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3312 }
3313 return Register();
3314}
3315
3316Register fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3317 if (RetVT.SimpleTy != MVT::v4i32)
3318 return Register();
3319 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3320 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3321 }
3322 return Register();
3323}
3324
3325Register fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3326 if (RetVT.SimpleTy != MVT::v2i64)
3327 return Register();
3328 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3329 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3330 }
3331 return Register();
3332}
3333
3334Register fastEmit_MipsISD_ILVEV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3335 switch (VT.SimpleTy) {
3336 case MVT::v16i8: return fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(RetVT, Op0, Op1);
3337 case MVT::v8i16: return fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(RetVT, Op0, Op1);
3338 case MVT::v4i32: return fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(RetVT, Op0, Op1);
3339 case MVT::v2i64: return fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(RetVT, Op0, Op1);
3340 default: return Register();
3341 }
3342}
3343
3344// FastEmit functions for MipsISD::ILVL.
3345
3346Register fastEmit_MipsISD_ILVL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3347 if (RetVT.SimpleTy != MVT::v16i8)
3348 return Register();
3349 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3350 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3351 }
3352 return Register();
3353}
3354
3355Register fastEmit_MipsISD_ILVL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3356 if (RetVT.SimpleTy != MVT::v8i16)
3357 return Register();
3358 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3359 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3360 }
3361 return Register();
3362}
3363
3364Register fastEmit_MipsISD_ILVL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3365 if (RetVT.SimpleTy != MVT::v4i32)
3366 return Register();
3367 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3368 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3369 }
3370 return Register();
3371}
3372
3373Register fastEmit_MipsISD_ILVL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3374 if (RetVT.SimpleTy != MVT::v2i64)
3375 return Register();
3376 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3377 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3378 }
3379 return Register();
3380}
3381
3382Register fastEmit_MipsISD_ILVL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3383 switch (VT.SimpleTy) {
3384 case MVT::v16i8: return fastEmit_MipsISD_ILVL_MVT_v16i8_rr(RetVT, Op0, Op1);
3385 case MVT::v8i16: return fastEmit_MipsISD_ILVL_MVT_v8i16_rr(RetVT, Op0, Op1);
3386 case MVT::v4i32: return fastEmit_MipsISD_ILVL_MVT_v4i32_rr(RetVT, Op0, Op1);
3387 case MVT::v2i64: return fastEmit_MipsISD_ILVL_MVT_v2i64_rr(RetVT, Op0, Op1);
3388 default: return Register();
3389 }
3390}
3391
3392// FastEmit functions for MipsISD::ILVOD.
3393
3394Register fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3395 if (RetVT.SimpleTy != MVT::v16i8)
3396 return Register();
3397 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3398 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3399 }
3400 return Register();
3401}
3402
3403Register fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3404 if (RetVT.SimpleTy != MVT::v8i16)
3405 return Register();
3406 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3407 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3408 }
3409 return Register();
3410}
3411
3412Register fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3413 if (RetVT.SimpleTy != MVT::v4i32)
3414 return Register();
3415 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3416 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3417 }
3418 return Register();
3419}
3420
3421Register fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3422 if (RetVT.SimpleTy != MVT::v2i64)
3423 return Register();
3424 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3425 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3426 }
3427 return Register();
3428}
3429
3430Register fastEmit_MipsISD_ILVOD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3431 switch (VT.SimpleTy) {
3432 case MVT::v16i8: return fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(RetVT, Op0, Op1);
3433 case MVT::v8i16: return fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(RetVT, Op0, Op1);
3434 case MVT::v4i32: return fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(RetVT, Op0, Op1);
3435 case MVT::v2i64: return fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(RetVT, Op0, Op1);
3436 default: return Register();
3437 }
3438}
3439
3440// FastEmit functions for MipsISD::ILVR.
3441
3442Register fastEmit_MipsISD_ILVR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3443 if (RetVT.SimpleTy != MVT::v16i8)
3444 return Register();
3445 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3446 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3447 }
3448 return Register();
3449}
3450
3451Register fastEmit_MipsISD_ILVR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3452 if (RetVT.SimpleTy != MVT::v8i16)
3453 return Register();
3454 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3455 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3456 }
3457 return Register();
3458}
3459
3460Register fastEmit_MipsISD_ILVR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3461 if (RetVT.SimpleTy != MVT::v4i32)
3462 return Register();
3463 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3464 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3465 }
3466 return Register();
3467}
3468
3469Register fastEmit_MipsISD_ILVR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3470 if (RetVT.SimpleTy != MVT::v2i64)
3471 return Register();
3472 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3473 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3474 }
3475 return Register();
3476}
3477
3478Register fastEmit_MipsISD_ILVR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3479 switch (VT.SimpleTy) {
3480 case MVT::v16i8: return fastEmit_MipsISD_ILVR_MVT_v16i8_rr(RetVT, Op0, Op1);
3481 case MVT::v8i16: return fastEmit_MipsISD_ILVR_MVT_v8i16_rr(RetVT, Op0, Op1);
3482 case MVT::v4i32: return fastEmit_MipsISD_ILVR_MVT_v4i32_rr(RetVT, Op0, Op1);
3483 case MVT::v2i64: return fastEmit_MipsISD_ILVR_MVT_v2i64_rr(RetVT, Op0, Op1);
3484 default: return Register();
3485 }
3486}
3487
3488// FastEmit functions for MipsISD::MTLOHI.
3489
3490Register fastEmit_MipsISD_MTLOHI_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3491 if (RetVT.SimpleTy != MVT::Untyped)
3492 return Register();
3493 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
3494 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI_MM, RC: &Mips::ACC64RegClass, Op0, Op1);
3495 }
3496 if ((Subtarget->hasDSP()) && (!Subtarget->inMips16Mode())) {
3497 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI_DSP, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3498 }
3499 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3500 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI, RC: &Mips::ACC64RegClass, Op0, Op1);
3501 }
3502 return Register();
3503}
3504
3505Register fastEmit_MipsISD_MTLOHI_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3506 if (RetVT.SimpleTy != MVT::Untyped)
3507 return Register();
3508 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3509 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI64, RC: &Mips::ACC128RegClass, Op0, Op1);
3510 }
3511 return Register();
3512}
3513
3514Register fastEmit_MipsISD_MTLOHI_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3515 switch (VT.SimpleTy) {
3516 case MVT::i32: return fastEmit_MipsISD_MTLOHI_MVT_i32_rr(RetVT, Op0, Op1);
3517 case MVT::i64: return fastEmit_MipsISD_MTLOHI_MVT_i64_rr(RetVT, Op0, Op1);
3518 default: return Register();
3519 }
3520}
3521
3522// FastEmit functions for MipsISD::Mult.
3523
3524Register fastEmit_MipsISD_Mult_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3525 if (RetVT.SimpleTy != MVT::Untyped)
3526 return Register();
3527 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
3528 return fastEmitInst_rr(MachineInstOpcode: Mips::MULT_DSP_MM, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3529 }
3530 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
3531 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULT_MM, RC: &Mips::ACC64RegClass, Op0, Op1);
3532 }
3533 if ((Subtarget->hasDSP())) {
3534 return fastEmitInst_rr(MachineInstOpcode: Mips::MULT_DSP, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3535 }
3536 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3537 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULT, RC: &Mips::ACC64RegClass, Op0, Op1);
3538 }
3539 return Register();
3540}
3541
3542Register fastEmit_MipsISD_Mult_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3543 if (RetVT.SimpleTy != MVT::Untyped)
3544 return Register();
3545 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (!Subtarget->isR5900())) {
3546 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDMULT, RC: &Mips::ACC128RegClass, Op0, Op1);
3547 }
3548 return Register();
3549}
3550
3551Register fastEmit_MipsISD_Mult_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3552 switch (VT.SimpleTy) {
3553 case MVT::i32: return fastEmit_MipsISD_Mult_MVT_i32_rr(RetVT, Op0, Op1);
3554 case MVT::i64: return fastEmit_MipsISD_Mult_MVT_i64_rr(RetVT, Op0, Op1);
3555 default: return Register();
3556 }
3557}
3558
3559// FastEmit functions for MipsISD::Multu.
3560
3561Register fastEmit_MipsISD_Multu_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3562 if (RetVT.SimpleTy != MVT::Untyped)
3563 return Register();
3564 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
3565 return fastEmitInst_rr(MachineInstOpcode: Mips::MULTU_DSP_MM, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3566 }
3567 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
3568 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULTu_MM, RC: &Mips::ACC64RegClass, Op0, Op1);
3569 }
3570 if ((Subtarget->hasDSP())) {
3571 return fastEmitInst_rr(MachineInstOpcode: Mips::MULTU_DSP, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3572 }
3573 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3574 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULTu, RC: &Mips::ACC64RegClass, Op0, Op1);
3575 }
3576 return Register();
3577}
3578
3579Register fastEmit_MipsISD_Multu_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3580 if (RetVT.SimpleTy != MVT::Untyped)
3581 return Register();
3582 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (!Subtarget->isR5900())) {
3583 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDMULTu, RC: &Mips::ACC128RegClass, Op0, Op1);
3584 }
3585 return Register();
3586}
3587
3588Register fastEmit_MipsISD_Multu_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3589 switch (VT.SimpleTy) {
3590 case MVT::i32: return fastEmit_MipsISD_Multu_MVT_i32_rr(RetVT, Op0, Op1);
3591 case MVT::i64: return fastEmit_MipsISD_Multu_MVT_i64_rr(RetVT, Op0, Op1);
3592 default: return Register();
3593 }
3594}
3595
3596// FastEmit functions for MipsISD::PCKEV.
3597
3598Register fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3599 if (RetVT.SimpleTy != MVT::v16i8)
3600 return Register();
3601 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3602 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3603 }
3604 return Register();
3605}
3606
3607Register fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3608 if (RetVT.SimpleTy != MVT::v8i16)
3609 return Register();
3610 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3611 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3612 }
3613 return Register();
3614}
3615
3616Register fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3617 if (RetVT.SimpleTy != MVT::v4i32)
3618 return Register();
3619 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3620 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3621 }
3622 return Register();
3623}
3624
3625Register fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3626 if (RetVT.SimpleTy != MVT::v2i64)
3627 return Register();
3628 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3629 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3630 }
3631 return Register();
3632}
3633
3634Register fastEmit_MipsISD_PCKEV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3635 switch (VT.SimpleTy) {
3636 case MVT::v16i8: return fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(RetVT, Op0, Op1);
3637 case MVT::v8i16: return fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(RetVT, Op0, Op1);
3638 case MVT::v4i32: return fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(RetVT, Op0, Op1);
3639 case MVT::v2i64: return fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(RetVT, Op0, Op1);
3640 default: return Register();
3641 }
3642}
3643
3644// FastEmit functions for MipsISD::PCKOD.
3645
3646Register fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3647 if (RetVT.SimpleTy != MVT::v16i8)
3648 return Register();
3649 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3650 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3651 }
3652 return Register();
3653}
3654
3655Register fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3656 if (RetVT.SimpleTy != MVT::v8i16)
3657 return Register();
3658 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3659 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3660 }
3661 return Register();
3662}
3663
3664Register fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3665 if (RetVT.SimpleTy != MVT::v4i32)
3666 return Register();
3667 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3668 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3669 }
3670 return Register();
3671}
3672
3673Register fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3674 if (RetVT.SimpleTy != MVT::v2i64)
3675 return Register();
3676 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3677 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3678 }
3679 return Register();
3680}
3681
3682Register fastEmit_MipsISD_PCKOD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3683 switch (VT.SimpleTy) {
3684 case MVT::v16i8: return fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(RetVT, Op0, Op1);
3685 case MVT::v8i16: return fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(RetVT, Op0, Op1);
3686 case MVT::v4i32: return fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(RetVT, Op0, Op1);
3687 case MVT::v2i64: return fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(RetVT, Op0, Op1);
3688 default: return Register();
3689 }
3690}
3691
3692// FastEmit functions for MipsISD::VNOR.
3693
3694Register fastEmit_MipsISD_VNOR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3695 if (RetVT.SimpleTy != MVT::v16i8)
3696 return Register();
3697 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3698 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
3699 }
3700 return Register();
3701}
3702
3703Register fastEmit_MipsISD_VNOR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3704 if (RetVT.SimpleTy != MVT::v8i16)
3705 return Register();
3706 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3707 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
3708 }
3709 return Register();
3710}
3711
3712Register fastEmit_MipsISD_VNOR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3713 if (RetVT.SimpleTy != MVT::v4i32)
3714 return Register();
3715 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3716 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
3717 }
3718 return Register();
3719}
3720
3721Register fastEmit_MipsISD_VNOR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3722 if (RetVT.SimpleTy != MVT::v2i64)
3723 return Register();
3724 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3725 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
3726 }
3727 return Register();
3728}
3729
3730Register fastEmit_MipsISD_VNOR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3731 switch (VT.SimpleTy) {
3732 case MVT::v16i8: return fastEmit_MipsISD_VNOR_MVT_v16i8_rr(RetVT, Op0, Op1);
3733 case MVT::v8i16: return fastEmit_MipsISD_VNOR_MVT_v8i16_rr(RetVT, Op0, Op1);
3734 case MVT::v4i32: return fastEmit_MipsISD_VNOR_MVT_v4i32_rr(RetVT, Op0, Op1);
3735 case MVT::v2i64: return fastEmit_MipsISD_VNOR_MVT_v2i64_rr(RetVT, Op0, Op1);
3736 default: return Register();
3737 }
3738}
3739
3740// Top-level FastEmit function.
3741
3742Register fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, Register Op1) override {
3743 switch (Opcode) {
3744 case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op1);
3745 case ISD::ADDC: return fastEmit_ISD_ADDC_rr(VT, RetVT, Op0, Op1);
3746 case ISD::ADDE: return fastEmit_ISD_ADDE_rr(VT, RetVT, Op0, Op1);
3747 case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op1);
3748 case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op1);
3749 case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op1);
3750 case ISD::FMAXNUM: return fastEmit_ISD_FMAXNUM_rr(VT, RetVT, Op0, Op1);
3751 case ISD::FMAXNUM_IEEE: return fastEmit_ISD_FMAXNUM_IEEE_rr(VT, RetVT, Op0, Op1);
3752 case ISD::FMINNUM: return fastEmit_ISD_FMINNUM_rr(VT, RetVT, Op0, Op1);
3753 case ISD::FMINNUM_IEEE: return fastEmit_ISD_FMINNUM_IEEE_rr(VT, RetVT, Op0, Op1);
3754 case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op1);
3755 case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op1);
3756 case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op1);
3757 case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op1);
3758 case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op1);
3759 case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op1);
3760 case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op1);
3761 case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op1);
3762 case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op1);
3763 case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op1);
3764 case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op1);
3765 case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op1);
3766 case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op1);
3767 case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op1);
3768 case ISD::STRICT_FADD: return fastEmit_ISD_STRICT_FADD_rr(VT, RetVT, Op0, Op1);
3769 case ISD::STRICT_FDIV: return fastEmit_ISD_STRICT_FDIV_rr(VT, RetVT, Op0, Op1);
3770 case ISD::STRICT_FMUL: return fastEmit_ISD_STRICT_FMUL_rr(VT, RetVT, Op0, Op1);
3771 case ISD::STRICT_FSUB: return fastEmit_ISD_STRICT_FSUB_rr(VT, RetVT, Op0, Op1);
3772 case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op1);
3773 case ISD::SUBC: return fastEmit_ISD_SUBC_rr(VT, RetVT, Op0, Op1);
3774 case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op1);
3775 case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op1);
3776 case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op1);
3777 case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op1);
3778 case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op1);
3779 case MipsISD::BuildPairF64: return fastEmit_MipsISD_BuildPairF64_rr(VT, RetVT, Op0, Op1);
3780 case MipsISD::DivRem: return fastEmit_MipsISD_DivRem_rr(VT, RetVT, Op0, Op1);
3781 case MipsISD::DivRem16: return fastEmit_MipsISD_DivRem16_rr(VT, RetVT, Op0, Op1);
3782 case MipsISD::DivRemU: return fastEmit_MipsISD_DivRemU_rr(VT, RetVT, Op0, Op1);
3783 case MipsISD::DivRemU16: return fastEmit_MipsISD_DivRemU16_rr(VT, RetVT, Op0, Op1);
3784 case MipsISD::EH_RETURN: return fastEmit_MipsISD_EH_RETURN_rr(VT, RetVT, Op0, Op1);
3785 case MipsISD::ILVEV: return fastEmit_MipsISD_ILVEV_rr(VT, RetVT, Op0, Op1);
3786 case MipsISD::ILVL: return fastEmit_MipsISD_ILVL_rr(VT, RetVT, Op0, Op1);
3787 case MipsISD::ILVOD: return fastEmit_MipsISD_ILVOD_rr(VT, RetVT, Op0, Op1);
3788 case MipsISD::ILVR: return fastEmit_MipsISD_ILVR_rr(VT, RetVT, Op0, Op1);
3789 case MipsISD::MTLOHI: return fastEmit_MipsISD_MTLOHI_rr(VT, RetVT, Op0, Op1);
3790 case MipsISD::Mult: return fastEmit_MipsISD_Mult_rr(VT, RetVT, Op0, Op1);
3791 case MipsISD::Multu: return fastEmit_MipsISD_Multu_rr(VT, RetVT, Op0, Op1);
3792 case MipsISD::PCKEV: return fastEmit_MipsISD_PCKEV_rr(VT, RetVT, Op0, Op1);
3793 case MipsISD::PCKOD: return fastEmit_MipsISD_PCKOD_rr(VT, RetVT, Op0, Op1);
3794 case MipsISD::VNOR: return fastEmit_MipsISD_VNOR_rr(VT, RetVT, Op0, Op1);
3795 default: return Register();
3796 }
3797}
3798
3799// FastEmit functions for MipsISD::ExtractElementF64.
3800
3801Register fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3802 if (RetVT.SimpleTy != MVT::i32)
3803 return Register();
3804 if ((Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMips16Mode())) {
3805 return fastEmitInst_ri(MachineInstOpcode: Mips::ExtractElementF64_64, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3806 }
3807 if ((!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode())) {
3808 return fastEmitInst_ri(MachineInstOpcode: Mips::ExtractElementF64, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3809 }
3810 return Register();
3811}
3812
3813Register fastEmit_MipsISD_ExtractElementF64_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3814 switch (VT.SimpleTy) {
3815 case MVT::f64: return fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(RetVT, Op0, imm1);
3816 default: return Register();
3817 }
3818}
3819
3820// FastEmit functions for MipsISD::SHLL_DSP.
3821
3822Register fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3823 if (RetVT.SimpleTy != MVT::v4i8)
3824 return Register();
3825 if ((Subtarget->hasDSP())) {
3826 return fastEmitInst_ri(MachineInstOpcode: Mips::SHLL_QB, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3827 }
3828 return Register();
3829}
3830
3831Register fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3832 if (RetVT.SimpleTy != MVT::v2i16)
3833 return Register();
3834 if ((Subtarget->hasDSP())) {
3835 return fastEmitInst_ri(MachineInstOpcode: Mips::SHLL_PH, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3836 }
3837 return Register();
3838}
3839
3840Register fastEmit_MipsISD_SHLL_DSP_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3841 switch (VT.SimpleTy) {
3842 case MVT::v4i8: return fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(RetVT, Op0, imm1);
3843 case MVT::v2i16: return fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(RetVT, Op0, imm1);
3844 default: return Register();
3845 }
3846}
3847
3848// FastEmit functions for MipsISD::SHRA_DSP.
3849
3850Register fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3851 if (RetVT.SimpleTy != MVT::v4i8)
3852 return Register();
3853 if ((Subtarget->hasDSPR2())) {
3854 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRA_QB, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3855 }
3856 return Register();
3857}
3858
3859Register fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3860 if (RetVT.SimpleTy != MVT::v2i16)
3861 return Register();
3862 if ((Subtarget->hasDSP())) {
3863 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRA_PH, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3864 }
3865 return Register();
3866}
3867
3868Register fastEmit_MipsISD_SHRA_DSP_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3869 switch (VT.SimpleTy) {
3870 case MVT::v4i8: return fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(RetVT, Op0, imm1);
3871 case MVT::v2i16: return fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(RetVT, Op0, imm1);
3872 default: return Register();
3873 }
3874}
3875
3876// FastEmit functions for MipsISD::SHRL_DSP.
3877
3878Register fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3879 if (RetVT.SimpleTy != MVT::v4i8)
3880 return Register();
3881 if ((Subtarget->hasDSP())) {
3882 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRL_QB, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3883 }
3884 return Register();
3885}
3886
3887Register fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3888 if (RetVT.SimpleTy != MVT::v2i16)
3889 return Register();
3890 if ((Subtarget->hasDSPR2())) {
3891 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRL_PH, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3892 }
3893 return Register();
3894}
3895
3896Register fastEmit_MipsISD_SHRL_DSP_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3897 switch (VT.SimpleTy) {
3898 case MVT::v4i8: return fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(RetVT, Op0, imm1);
3899 case MVT::v2i16: return fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(RetVT, Op0, imm1);
3900 default: return Register();
3901 }
3902}
3903
3904// Top-level FastEmit function.
3905
3906Register fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) override {
3907 if (VT == MVT::i32 && Predicate_immZExt5(Imm: imm1))
3908 if (Register Reg = fastEmit_ri_Predicate_immZExt5(VT, RetVT, Opcode, Op0, imm1))
3909 return Reg;
3910
3911 if (VT == MVT::i32 && Predicate_immZExt6(Imm: imm1))
3912 if (Register Reg = fastEmit_ri_Predicate_immZExt6(VT, RetVT, Opcode, Op0, imm1))
3913 return Reg;
3914
3915 if (VT == MVT::iPTR && Predicate_immZExt2Ptr(Imm: imm1))
3916 if (Register Reg = fastEmit_ri_Predicate_immZExt2Ptr(VT, RetVT, Opcode, Op0, imm1))
3917 return Reg;
3918
3919 if (VT == MVT::iPTR && Predicate_immZExt1Ptr(Imm: imm1))
3920 if (Register Reg = fastEmit_ri_Predicate_immZExt1Ptr(VT, RetVT, Opcode, Op0, imm1))
3921 return Reg;
3922
3923 if (VT == MVT::i32 && Predicate_immZExt4(Imm: imm1))
3924 if (Register Reg = fastEmit_ri_Predicate_immZExt4(VT, RetVT, Opcode, Op0, imm1))
3925 return Reg;
3926
3927 if (VT == MVT::i32 && Predicate_immSExtAddiur2(Imm: imm1))
3928 if (Register Reg = fastEmit_ri_Predicate_immSExtAddiur2(VT, RetVT, Opcode, Op0, imm1))
3929 return Reg;
3930
3931 if (VT == MVT::i32 && Predicate_immSExtAddius5(Imm: imm1))
3932 if (Register Reg = fastEmit_ri_Predicate_immSExtAddius5(VT, RetVT, Opcode, Op0, imm1))
3933 return Reg;
3934
3935 if (VT == MVT::i32 && Predicate_immZExtAndi16(Imm: imm1))
3936 if (Register Reg = fastEmit_ri_Predicate_immZExtAndi16(VT, RetVT, Opcode, Op0, imm1))
3937 return Reg;
3938
3939 if (VT == MVT::i32 && Predicate_immZExt2Shift(Imm: imm1))
3940 if (Register Reg = fastEmit_ri_Predicate_immZExt2Shift(VT, RetVT, Opcode, Op0, imm1))
3941 return Reg;
3942
3943 switch (Opcode) {
3944 case MipsISD::ExtractElementF64: return fastEmit_MipsISD_ExtractElementF64_ri(VT, RetVT, Op0, imm1);
3945 case MipsISD::SHLL_DSP: return fastEmit_MipsISD_SHLL_DSP_ri(VT, RetVT, Op0, imm1);
3946 case MipsISD::SHRA_DSP: return fastEmit_MipsISD_SHRA_DSP_ri(VT, RetVT, Op0, imm1);
3947 case MipsISD::SHRL_DSP: return fastEmit_MipsISD_SHRL_DSP_ri(VT, RetVT, Op0, imm1);
3948 default: return Register();
3949 }
3950}
3951
3952// FastEmit functions for ISD::ROTR.
3953
3954Register fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, Register Op0, uint64_t imm1) {
3955 if (RetVT.SimpleTy != MVT::i32)
3956 return Register();
3957 if ((Subtarget->inMicroMipsMode())) {
3958 return fastEmitInst_ri(MachineInstOpcode: Mips::ROTR_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3959 }
3960 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3961 return fastEmitInst_ri(MachineInstOpcode: Mips::ROTR, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3962 }
3963 return Register();
3964}
3965
3966Register fastEmit_ISD_ROTR_ri_Predicate_immZExt5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3967 switch (VT.SimpleTy) {
3968 case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
3969 default: return Register();
3970 }
3971}
3972
3973// FastEmit functions for ISD::SHL.
3974
3975Register fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, Register Op0, uint64_t imm1) {
3976 if (RetVT.SimpleTy != MVT::i32)
3977 return Register();
3978 if ((Subtarget->inMicroMipsMode())) {
3979 return fastEmitInst_ri(MachineInstOpcode: Mips::SLL_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3980 }
3981 if ((Subtarget->inMips16Mode())) {
3982 return fastEmitInst_ri(MachineInstOpcode: Mips::SllX16, RC: &Mips::CPU16RegsRegClass, Op0, Imm: imm1);
3983 }
3984 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3985 return fastEmitInst_ri(MachineInstOpcode: Mips::SLL, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3986 }
3987 return Register();
3988}
3989
3990Register fastEmit_ISD_SHL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3991 switch (VT.SimpleTy) {
3992 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
3993 default: return Register();
3994 }
3995}
3996
3997// FastEmit functions for ISD::SRA.
3998
3999Register fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, Register Op0, uint64_t imm1) {
4000 if (RetVT.SimpleTy != MVT::i32)
4001 return Register();
4002 if ((Subtarget->inMicroMipsMode())) {
4003 return fastEmitInst_ri(MachineInstOpcode: Mips::SRA_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
4004 }
4005 if ((Subtarget->inMips16Mode())) {
4006 return fastEmitInst_ri(MachineInstOpcode: Mips::SraX16, RC: &Mips::CPU16RegsRegClass, Op0, Imm: imm1);
4007 }
4008 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
4009 return fastEmitInst_ri(MachineInstOpcode: Mips::SRA, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
4010 }
4011 return Register();
4012}
4013
4014Register fastEmit_ISD_SRA_ri_Predicate_immZExt5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4015 switch (VT.SimpleTy) {
4016 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
4017 default: return Register();
4018 }
4019}
4020
4021// FastEmit functions for ISD::SRL.
4022
4023Register fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, Register Op0, uint64_t imm1) {
4024 if (RetVT.SimpleTy != MVT::i32)
4025 return Register();
4026 if ((Subtarget->inMicroMipsMode())) {
4027 return fastEmitInst_ri(MachineInstOpcode: Mips::SRL_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
4028 }
4029 if ((Subtarget->inMips16Mode())) {
4030 return fastEmitInst_ri(MachineInstOpcode: Mips::SrlX16, RC: &Mips::CPU16RegsRegClass, Op0, Imm: imm1);
4031 }
4032 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
4033 return fastEmitInst_ri(MachineInstOpcode: Mips::SRL, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
4034 }
4035 return Register();
4036}
4037
4038Register fastEmit_ISD_SRL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4039 switch (VT.SimpleTy) {
4040 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
4041 default: return Register();
4042 }
4043}
4044
4045// Top-level FastEmit function.
4046
4047Register fastEmit_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4048 switch (Opcode) {
4049 case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
4050 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
4051 case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
4052 case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
4053 default: return Register();
4054 }
4055}
4056
4057// FastEmit functions for ISD::ROTR.
4058
4059Register fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, Register Op0, uint64_t imm1) {
4060 if (RetVT.SimpleTy != MVT::i64)
4061 return Register();
4062 if ((Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
4063 return fastEmitInst_ri(MachineInstOpcode: Mips::DROTR, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
4064 }
4065 return Register();
4066}
4067
4068Register fastEmit_ISD_ROTR_ri_Predicate_immZExt6(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4069 switch (VT.SimpleTy) {
4070 case MVT::i64: return fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
4071 default: return Register();
4072 }
4073}
4074
4075// FastEmit functions for ISD::SHL.
4076
4077Register fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, Register Op0, uint64_t imm1) {
4078 if (RetVT.SimpleTy != MVT::i64)
4079 return Register();
4080 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
4081 return fastEmitInst_ri(MachineInstOpcode: Mips::DSLL, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
4082 }
4083 return Register();
4084}
4085
4086Register fastEmit_ISD_SHL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4087 switch (VT.SimpleTy) {
4088 case MVT::i64: return fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
4089 default: return Register();
4090 }
4091}
4092
4093// FastEmit functions for ISD::SRA.
4094
4095Register fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, Register Op0, uint64_t imm1) {
4096 if (RetVT.SimpleTy != MVT::i64)
4097 return Register();
4098 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
4099 return fastEmitInst_ri(MachineInstOpcode: Mips::DSRA, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
4100 }
4101 return Register();
4102}
4103
4104Register fastEmit_ISD_SRA_ri_Predicate_immZExt6(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4105 switch (VT.SimpleTy) {
4106 case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
4107 default: return Register();
4108 }
4109}
4110
4111// FastEmit functions for ISD::SRL.
4112
4113Register fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, Register Op0, uint64_t imm1) {
4114 if (RetVT.SimpleTy != MVT::i64)
4115 return Register();
4116 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
4117 return fastEmitInst_ri(MachineInstOpcode: Mips::DSRL, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
4118 }
4119 return Register();
4120}
4121
4122Register fastEmit_ISD_SRL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4123 switch (VT.SimpleTy) {
4124 case MVT::i64: return fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
4125 default: return Register();
4126 }
4127}
4128
4129// Top-level FastEmit function.
4130
4131Register fastEmit_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4132 switch (Opcode) {
4133 case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
4134 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
4135 case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
4136 case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
4137 default: return Register();
4138 }
4139}
4140
4141// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
4142
4143Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(MVT RetVT, Register Op0, uint64_t imm1) {
4144 if (RetVT.SimpleTy != MVT::f32)
4145 return Register();
4146 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
4147 return fastEmitInst_ri(MachineInstOpcode: Mips::COPY_FW_PSEUDO, RC: &Mips::FGR32RegClass, Op0, Imm: imm1);
4148 }
4149 return Register();
4150}
4151
4152Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4153 switch (VT.SimpleTy) {
4154 case MVT::v4f32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(RetVT, Op0, imm1);
4155 default: return Register();
4156 }
4157}
4158
4159// Top-level FastEmit function.
4160
4161Register fastEmit_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4162 switch (Opcode) {
4163 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(VT, RetVT, Op0, imm1);
4164 default: return Register();
4165 }
4166}
4167
4168// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
4169
4170Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(MVT RetVT, Register Op0, uint64_t imm1) {
4171 if (RetVT.SimpleTy != MVT::f64)
4172 return Register();
4173 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
4174 return fastEmitInst_ri(MachineInstOpcode: Mips::COPY_FD_PSEUDO, RC: &Mips::FGR64RegClass, Op0, Imm: imm1);
4175 }
4176 return Register();
4177}
4178
4179Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4180 switch (VT.SimpleTy) {
4181 case MVT::v2f64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(RetVT, Op0, imm1);
4182 default: return Register();
4183 }
4184}
4185
4186// Top-level FastEmit function.
4187
4188Register fastEmit_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4189 switch (Opcode) {
4190 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(VT, RetVT, Op0, imm1);
4191 default: return Register();
4192 }
4193}
4194
4195// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
4196
4197Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(MVT RetVT, Register Op0, uint64_t imm1) {
4198 if (RetVT.SimpleTy != MVT::i32)
4199 return Register();
4200 if ((Subtarget->hasMSA())) {
4201 return fastEmitInst_ri(MachineInstOpcode: Mips::COPY_S_W, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
4202 }
4203 return Register();
4204}
4205
4206Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4207 switch (VT.SimpleTy) {
4208 case MVT::v4i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(RetVT, Op0, imm1);
4209 default: return Register();
4210 }
4211}
4212
4213// Top-level FastEmit function.
4214
4215Register fastEmit_ri_Predicate_immZExt4(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4216 switch (Opcode) {
4217 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(VT, RetVT, Op0, imm1);
4218 default: return Register();
4219 }
4220}
4221
4222// FastEmit functions for ISD::ADD.
4223
4224Register fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(MVT RetVT, Register Op0, uint64_t imm1) {
4225 if (RetVT.SimpleTy != MVT::i32)
4226 return Register();
4227 if ((Subtarget->inMicroMipsMode())) {
4228 return fastEmitInst_ri(MachineInstOpcode: Mips::ADDIUR2_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4229 }
4230 return Register();
4231}
4232
4233Register fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4234 switch (VT.SimpleTy) {
4235 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(RetVT, Op0, imm1);
4236 default: return Register();
4237 }
4238}
4239
4240// Top-level FastEmit function.
4241
4242Register fastEmit_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4243 switch (Opcode) {
4244 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(VT, RetVT, Op0, imm1);
4245 default: return Register();
4246 }
4247}
4248
4249// FastEmit functions for ISD::ADD.
4250
4251Register fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(MVT RetVT, Register Op0, uint64_t imm1) {
4252 if (RetVT.SimpleTy != MVT::i32)
4253 return Register();
4254 if ((Subtarget->inMicroMipsMode())) {
4255 return fastEmitInst_ri(MachineInstOpcode: Mips::ADDIUS5_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
4256 }
4257 return Register();
4258}
4259
4260Register fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4261 switch (VT.SimpleTy) {
4262 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(RetVT, Op0, imm1);
4263 default: return Register();
4264 }
4265}
4266
4267// Top-level FastEmit function.
4268
4269Register fastEmit_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4270 switch (Opcode) {
4271 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(VT, RetVT, Op0, imm1);
4272 default: return Register();
4273 }
4274}
4275
4276// FastEmit functions for ISD::AND.
4277
4278Register fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(MVT RetVT, Register Op0, uint64_t imm1) {
4279 if (RetVT.SimpleTy != MVT::i32)
4280 return Register();
4281 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
4282 return fastEmitInst_ri(MachineInstOpcode: Mips::ANDI16_MMR6, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4283 }
4284 if ((Subtarget->inMicroMipsMode())) {
4285 return fastEmitInst_ri(MachineInstOpcode: Mips::ANDI16_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4286 }
4287 return Register();
4288}
4289
4290Register fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4291 switch (VT.SimpleTy) {
4292 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(RetVT, Op0, imm1);
4293 default: return Register();
4294 }
4295}
4296
4297// Top-level FastEmit function.
4298
4299Register fastEmit_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4300 switch (Opcode) {
4301 case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(VT, RetVT, Op0, imm1);
4302 default: return Register();
4303 }
4304}
4305
4306// FastEmit functions for ISD::SHL.
4307
4308Register fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, Register Op0, uint64_t imm1) {
4309 if (RetVT.SimpleTy != MVT::i32)
4310 return Register();
4311 if ((Subtarget->inMicroMipsMode())) {
4312 return fastEmitInst_ri(MachineInstOpcode: Mips::SLL16_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4313 }
4314 return Register();
4315}
4316
4317Register fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4318 switch (VT.SimpleTy) {
4319 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, imm1);
4320 default: return Register();
4321 }
4322}
4323
4324// FastEmit functions for ISD::SRL.
4325
4326Register fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, Register Op0, uint64_t imm1) {
4327 if (RetVT.SimpleTy != MVT::i32)
4328 return Register();
4329 if ((Subtarget->inMicroMipsMode())) {
4330 return fastEmitInst_ri(MachineInstOpcode: Mips::SRL16_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4331 }
4332 return Register();
4333}
4334
4335Register fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4336 switch (VT.SimpleTy) {
4337 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, imm1);
4338 default: return Register();
4339 }
4340}
4341
4342// Top-level FastEmit function.
4343
4344Register fastEmit_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4345 switch (Opcode) {
4346 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, imm1);
4347 case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, imm1);
4348 default: return Register();
4349 }
4350}
4351
4352// FastEmit functions for ISD::Constant.
4353
4354Register fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) {
4355 if (RetVT.SimpleTy != MVT::i32)
4356 return Register();
4357 if ((Subtarget->inMips16Mode())) {
4358 return fastEmitInst_i(MachineInstOpcode: Mips::LwConstant32, RC: &Mips::CPU16RegsRegClass, Imm: imm0);
4359 }
4360 return Register();
4361}
4362
4363Register fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) {
4364 switch (VT.SimpleTy) {
4365 case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0);
4366 default: return Register();
4367 }
4368}
4369
4370// Top-level FastEmit function.
4371
4372Register fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override {
4373 switch (Opcode) {
4374 case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0);
4375 default: return Register();
4376 }
4377}
4378
4379