1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* "Fast" Instruction Selector for the Mips target *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10// FastEmit Immediate Predicate functions.
11static bool Predicate_immZExt5(int64_t Imm) {
12return Imm == (Imm & 0x1f);
13}
14static bool Predicate_immZExt6(int64_t Imm) {
15return Imm == (Imm & 0x3f);
16}
17static bool Predicate_immSExt6(int64_t Imm) {
18return isInt<6>(x: Imm);
19}
20static bool Predicate_immZExt4Ptr(int64_t Imm) {
21return isUInt<4>(x: Imm);
22}
23static bool Predicate_immZExt3Ptr(int64_t Imm) {
24return isUInt<3>(x: Imm);
25}
26static bool Predicate_immZExt2Ptr(int64_t Imm) {
27return isUInt<2>(x: Imm);
28}
29static bool Predicate_immZExt1Ptr(int64_t Imm) {
30return isUInt<1>(x: Imm);
31}
32static bool Predicate_immZExt4(int64_t Imm) {
33return isUInt<4>(x: Imm);
34}
35static bool Predicate_immSExtAddiur2(int64_t Imm) {
36return Imm == 1 || Imm == -1 ||
37 ((Imm % 4 == 0) &&
38 Imm < 28 && Imm > 0);
39}
40static bool Predicate_immSExtAddius5(int64_t Imm) {
41return Imm >= -8 && Imm <= 7;
42}
43static bool Predicate_immZExtAndi16(int64_t Imm) {
44return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
45 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
46 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
47}
48static bool Predicate_immZExt2Shift(int64_t Imm) {
49return Imm >= 1 && Imm <= 8;
50}
51
52
53// FastEmit functions for ISD::BITCAST.
54
55Register fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, Register Op0) {
56 if (RetVT.SimpleTy != MVT::f32)
57 return Register();
58 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
59 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_MMR6, RC: &Mips::FGR32RegClass, Op0);
60 }
61 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
62 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_MM, RC: &Mips::FGR32RegClass, Op0);
63 }
64 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
65 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1, RC: &Mips::FGR32RegClass, Op0);
66 }
67 return Register();
68}
69
70Register fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, Register Op0) {
71 if (RetVT.SimpleTy != MVT::f64)
72 return Register();
73 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
74 return fastEmitInst_r(MachineInstOpcode: Mips::DMTC1, RC: &Mips::FGR64RegClass, Op0);
75 }
76 return Register();
77}
78
79Register fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, Register Op0) {
80 if (RetVT.SimpleTy != MVT::i32)
81 return Register();
82 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
83 return fastEmitInst_r(MachineInstOpcode: Mips::MFC1_MMR6, RC: &Mips::GPR32RegClass, Op0);
84 }
85 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
86 return fastEmitInst_r(MachineInstOpcode: Mips::MFC1_MM, RC: &Mips::GPR32RegClass, Op0);
87 }
88 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
89 return fastEmitInst_r(MachineInstOpcode: Mips::MFC1, RC: &Mips::GPR32RegClass, Op0);
90 }
91 return Register();
92}
93
94Register fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, Register Op0) {
95 if (RetVT.SimpleTy != MVT::i64)
96 return Register();
97 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
98 return fastEmitInst_r(MachineInstOpcode: Mips::DMFC1, RC: &Mips::GPR64RegClass, Op0);
99 }
100 return Register();
101}
102
103Register fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, Register Op0) {
104 switch (VT.SimpleTy) {
105 case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0);
106 case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0);
107 case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0);
108 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0);
109 default: return Register();
110 }
111}
112
113// FastEmit functions for ISD::CTLZ.
114
115Register fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, Register Op0) {
116 if (RetVT.SimpleTy != MVT::i32)
117 return Register();
118 if ((Subtarget->inMicroMipsMode())) {
119 return fastEmitInst_r(MachineInstOpcode: Mips::CLZ_MM, RC: &Mips::GPR32RegClass, Op0);
120 }
121 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding())) {
122 return fastEmitInst_r(MachineInstOpcode: Mips::CLZ_R6, RC: &Mips::GPR32RegClass, Op0);
123 }
124 if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
125 return fastEmitInst_r(MachineInstOpcode: Mips::CLZ, RC: &Mips::GPR32RegClass, Op0);
126 }
127 return Register();
128}
129
130Register fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, Register Op0) {
131 if (RetVT.SimpleTy != MVT::i64)
132 return Register();
133 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
134 return fastEmitInst_r(MachineInstOpcode: Mips::DCLZ_R6, RC: &Mips::GPR64RegClass, Op0);
135 }
136 if ((Subtarget->hasMips64()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips64r6())) {
137 return fastEmitInst_r(MachineInstOpcode: Mips::DCLZ, RC: &Mips::GPR64RegClass, Op0);
138 }
139 return Register();
140}
141
142Register fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, Register Op0) {
143 if (RetVT.SimpleTy != MVT::v16i8)
144 return Register();
145 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
146 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_B, RC: &Mips::MSA128BRegClass, Op0);
147 }
148 return Register();
149}
150
151Register fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, Register Op0) {
152 if (RetVT.SimpleTy != MVT::v8i16)
153 return Register();
154 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
155 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_H, RC: &Mips::MSA128HRegClass, Op0);
156 }
157 return Register();
158}
159
160Register fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, Register Op0) {
161 if (RetVT.SimpleTy != MVT::v4i32)
162 return Register();
163 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
164 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_W, RC: &Mips::MSA128WRegClass, Op0);
165 }
166 return Register();
167}
168
169Register fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, Register Op0) {
170 if (RetVT.SimpleTy != MVT::v2i64)
171 return Register();
172 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
173 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_D, RC: &Mips::MSA128DRegClass, Op0);
174 }
175 return Register();
176}
177
178Register fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, Register Op0) {
179 switch (VT.SimpleTy) {
180 case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0);
181 case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0);
182 case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0);
183 case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0);
184 case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0);
185 case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0);
186 default: return Register();
187 }
188}
189
190// FastEmit functions for ISD::CTPOP.
191
192Register fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, Register Op0) {
193 if (RetVT.SimpleTy != MVT::i32)
194 return Register();
195 if ((Subtarget->hasCnMips())) {
196 return fastEmitInst_r(MachineInstOpcode: Mips::POP, RC: &Mips::GPR32RegClass, Op0);
197 }
198 return Register();
199}
200
201Register fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, Register Op0) {
202 if (RetVT.SimpleTy != MVT::i64)
203 return Register();
204 if ((Subtarget->hasCnMips())) {
205 return fastEmitInst_r(MachineInstOpcode: Mips::DPOP, RC: &Mips::GPR64RegClass, Op0);
206 }
207 return Register();
208}
209
210Register fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, Register Op0) {
211 if (RetVT.SimpleTy != MVT::v16i8)
212 return Register();
213 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
214 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_B, RC: &Mips::MSA128BRegClass, Op0);
215 }
216 return Register();
217}
218
219Register fastEmit_ISD_CTPOP_MVT_v8i16_r(MVT RetVT, Register Op0) {
220 if (RetVT.SimpleTy != MVT::v8i16)
221 return Register();
222 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
223 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_H, RC: &Mips::MSA128HRegClass, Op0);
224 }
225 return Register();
226}
227
228Register fastEmit_ISD_CTPOP_MVT_v4i32_r(MVT RetVT, Register Op0) {
229 if (RetVT.SimpleTy != MVT::v4i32)
230 return Register();
231 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
232 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_W, RC: &Mips::MSA128WRegClass, Op0);
233 }
234 return Register();
235}
236
237Register fastEmit_ISD_CTPOP_MVT_v2i64_r(MVT RetVT, Register Op0) {
238 if (RetVT.SimpleTy != MVT::v2i64)
239 return Register();
240 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
241 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_D, RC: &Mips::MSA128DRegClass, Op0);
242 }
243 return Register();
244}
245
246Register fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, Register Op0) {
247 switch (VT.SimpleTy) {
248 case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0);
249 case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0);
250 case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0);
251 case MVT::v8i16: return fastEmit_ISD_CTPOP_MVT_v8i16_r(RetVT, Op0);
252 case MVT::v4i32: return fastEmit_ISD_CTPOP_MVT_v4i32_r(RetVT, Op0);
253 case MVT::v2i64: return fastEmit_ISD_CTPOP_MVT_v2i64_r(RetVT, Op0);
254 default: return Register();
255 }
256}
257
258// FastEmit functions for ISD::FABS.
259
260Register fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, Register Op0) {
261 if (RetVT.SimpleTy != MVT::f32)
262 return Register();
263 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
264 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_S_MM, RC: &Mips::FGR32RegClass, Op0);
265 }
266 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
267 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_S, RC: &Mips::FGR32RegClass, Op0);
268 }
269 return Register();
270}
271
272Register fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, Register Op0) {
273 if (RetVT.SimpleTy != MVT::f64)
274 return Register();
275 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
276 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D64_MM, RC: &Mips::FGR64RegClass, Op0);
277 }
278 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
279 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D32_MM, RC: &Mips::AFGR64RegClass, Op0);
280 }
281 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
282 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D64, RC: &Mips::FGR64RegClass, Op0);
283 }
284 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
285 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D32, RC: &Mips::AFGR64RegClass, Op0);
286 }
287 return Register();
288}
289
290Register fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, Register Op0) {
291 if (RetVT.SimpleTy != MVT::v4f32)
292 return Register();
293 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
294 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_W, RC: &Mips::MSA128WRegClass, Op0);
295 }
296 return Register();
297}
298
299Register fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, Register Op0) {
300 if (RetVT.SimpleTy != MVT::v2f64)
301 return Register();
302 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
303 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D, RC: &Mips::MSA128DRegClass, Op0);
304 }
305 return Register();
306}
307
308Register fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, Register Op0) {
309 switch (VT.SimpleTy) {
310 case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0);
311 case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0);
312 case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0);
313 case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0);
314 default: return Register();
315 }
316}
317
318// FastEmit functions for ISD::FEXP2.
319
320Register fastEmit_ISD_FEXP2_MVT_v4f32_r(MVT RetVT, Register Op0) {
321 if (RetVT.SimpleTy != MVT::v4f32)
322 return Register();
323 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
324 return fastEmitInst_r(MachineInstOpcode: Mips::FEXP2_W_1_PSEUDO, RC: &Mips::MSA128WRegClass, Op0);
325 }
326 return Register();
327}
328
329Register fastEmit_ISD_FEXP2_MVT_v2f64_r(MVT RetVT, Register Op0) {
330 if (RetVT.SimpleTy != MVT::v2f64)
331 return Register();
332 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
333 return fastEmitInst_r(MachineInstOpcode: Mips::FEXP2_D_1_PSEUDO, RC: &Mips::MSA128DRegClass, Op0);
334 }
335 return Register();
336}
337
338Register fastEmit_ISD_FEXP2_r(MVT VT, MVT RetVT, Register Op0) {
339 switch (VT.SimpleTy) {
340 case MVT::v4f32: return fastEmit_ISD_FEXP2_MVT_v4f32_r(RetVT, Op0);
341 case MVT::v2f64: return fastEmit_ISD_FEXP2_MVT_v2f64_r(RetVT, Op0);
342 default: return Register();
343 }
344}
345
346// FastEmit functions for ISD::FLOG2.
347
348Register fastEmit_ISD_FLOG2_MVT_v4f32_r(MVT RetVT, Register Op0) {
349 if (RetVT.SimpleTy != MVT::v4f32)
350 return Register();
351 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
352 return fastEmitInst_r(MachineInstOpcode: Mips::FLOG2_W, RC: &Mips::MSA128WRegClass, Op0);
353 }
354 return Register();
355}
356
357Register fastEmit_ISD_FLOG2_MVT_v2f64_r(MVT RetVT, Register Op0) {
358 if (RetVT.SimpleTy != MVT::v2f64)
359 return Register();
360 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
361 return fastEmitInst_r(MachineInstOpcode: Mips::FLOG2_D, RC: &Mips::MSA128DRegClass, Op0);
362 }
363 return Register();
364}
365
366Register fastEmit_ISD_FLOG2_r(MVT VT, MVT RetVT, Register Op0) {
367 switch (VT.SimpleTy) {
368 case MVT::v4f32: return fastEmit_ISD_FLOG2_MVT_v4f32_r(RetVT, Op0);
369 case MVT::v2f64: return fastEmit_ISD_FLOG2_MVT_v2f64_r(RetVT, Op0);
370 default: return Register();
371 }
372}
373
374// FastEmit functions for ISD::FNEG.
375
376Register fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, Register Op0) {
377 if (RetVT.SimpleTy != MVT::f32)
378 return Register();
379 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
380 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_S_MMR6, RC: &Mips::FGR32RegClass, Op0);
381 }
382 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
383 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_S_MM, RC: &Mips::FGR32RegClass, Op0);
384 }
385 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
386 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_S, RC: &Mips::FGR32RegClass, Op0);
387 }
388 return Register();
389}
390
391Register fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, Register Op0) {
392 if (RetVT.SimpleTy != MVT::f64)
393 return Register();
394 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
395 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D64_MM, RC: &Mips::FGR64RegClass, Op0);
396 }
397 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
398 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D32_MM, RC: &Mips::AFGR64RegClass, Op0);
399 }
400 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
401 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D64, RC: &Mips::FGR64RegClass, Op0);
402 }
403 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
404 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D32, RC: &Mips::AFGR64RegClass, Op0);
405 }
406 return Register();
407}
408
409Register fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, Register Op0) {
410 switch (VT.SimpleTy) {
411 case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0);
412 case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0);
413 default: return Register();
414 }
415}
416
417// FastEmit functions for ISD::FP_EXTEND.
418
419Register fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, Register Op0) {
420 if (RetVT.SimpleTy != MVT::f64)
421 return Register();
422 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) {
423 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D32_S_MM, RC: &Mips::AFGR64RegClass, Op0);
424 }
425 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
426 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D64_S_MM, RC: &Mips::FGR64RegClass, Op0);
427 }
428 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->inMicroMipsMode())) {
429 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D64_S, RC: &Mips::FGR64RegClass, Op0);
430 }
431 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
432 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D32_S, RC: &Mips::AFGR64RegClass, Op0);
433 }
434 return Register();
435}
436
437Register fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
438 switch (VT.SimpleTy) {
439 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0);
440 default: return Register();
441 }
442}
443
444// FastEmit functions for ISD::FP_ROUND.
445
446Register fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, Register Op0) {
447 if (RetVT.SimpleTy != MVT::f32)
448 return Register();
449 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) {
450 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D32_MM, RC: &Mips::FGR32RegClass, Op0);
451 }
452 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
453 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D64_MM, RC: &Mips::FGR32RegClass, Op0);
454 }
455 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->inMicroMipsMode())) {
456 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D64, RC: &Mips::FGR32RegClass, Op0);
457 }
458 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
459 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D32, RC: &Mips::FGR32RegClass, Op0);
460 }
461 return Register();
462}
463
464Register fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, Register Op0) {
465 switch (VT.SimpleTy) {
466 case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0);
467 default: return Register();
468 }
469}
470
471// FastEmit functions for ISD::FP_TO_SINT.
472
473Register fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
474 if (RetVT.SimpleTy != MVT::v4i32)
475 return Register();
476 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
477 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_S_W, RC: &Mips::MSA128WRegClass, Op0);
478 }
479 return Register();
480}
481
482Register fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
483 if (RetVT.SimpleTy != MVT::v2i64)
484 return Register();
485 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
486 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_S_D, RC: &Mips::MSA128DRegClass, Op0);
487 }
488 return Register();
489}
490
491Register fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, Register Op0) {
492 switch (VT.SimpleTy) {
493 case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0);
494 case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0);
495 default: return Register();
496 }
497}
498
499// FastEmit functions for ISD::FP_TO_UINT.
500
501Register fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
502 if (RetVT.SimpleTy != MVT::v4i32)
503 return Register();
504 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
505 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_U_W, RC: &Mips::MSA128WRegClass, Op0);
506 }
507 return Register();
508}
509
510Register fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
511 if (RetVT.SimpleTy != MVT::v2i64)
512 return Register();
513 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
514 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_U_D, RC: &Mips::MSA128DRegClass, Op0);
515 }
516 return Register();
517}
518
519Register fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, Register Op0) {
520 switch (VT.SimpleTy) {
521 case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0);
522 case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0);
523 default: return Register();
524 }
525}
526
527// FastEmit functions for ISD::FRINT.
528
529Register fastEmit_ISD_FRINT_MVT_f32_r(MVT RetVT, Register Op0) {
530 if (RetVT.SimpleTy != MVT::f32)
531 return Register();
532 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
533 return fastEmitInst_r(MachineInstOpcode: Mips::RINT_S, RC: &Mips::FGR32RegClass, Op0);
534 }
535 return Register();
536}
537
538Register fastEmit_ISD_FRINT_MVT_f64_r(MVT RetVT, Register Op0) {
539 if (RetVT.SimpleTy != MVT::f64)
540 return Register();
541 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
542 return fastEmitInst_r(MachineInstOpcode: Mips::RINT_D, RC: &Mips::FGR64RegClass, Op0);
543 }
544 return Register();
545}
546
547Register fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
548 if (RetVT.SimpleTy != MVT::v4f32)
549 return Register();
550 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
551 return fastEmitInst_r(MachineInstOpcode: Mips::FRINT_W, RC: &Mips::MSA128WRegClass, Op0);
552 }
553 return Register();
554}
555
556Register fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
557 if (RetVT.SimpleTy != MVT::v2f64)
558 return Register();
559 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
560 return fastEmitInst_r(MachineInstOpcode: Mips::FRINT_D, RC: &Mips::MSA128DRegClass, Op0);
561 }
562 return Register();
563}
564
565Register fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, Register Op0) {
566 switch (VT.SimpleTy) {
567 case MVT::f32: return fastEmit_ISD_FRINT_MVT_f32_r(RetVT, Op0);
568 case MVT::f64: return fastEmit_ISD_FRINT_MVT_f64_r(RetVT, Op0);
569 case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0);
570 case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0);
571 default: return Register();
572 }
573}
574
575// FastEmit functions for ISD::FSQRT.
576
577Register fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, Register Op0) {
578 if (RetVT.SimpleTy != MVT::f32)
579 return Register();
580 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
581 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_S_MM, RC: &Mips::FGR32RegClass, Op0);
582 }
583 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
584 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_S, RC: &Mips::FGR32RegClass, Op0);
585 }
586 return Register();
587}
588
589Register fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, Register Op0) {
590 if (RetVT.SimpleTy != MVT::f64)
591 return Register();
592 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
593 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D64_MM, RC: &Mips::FGR64RegClass, Op0);
594 }
595 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
596 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D32_MM, RC: &Mips::AFGR64RegClass, Op0);
597 }
598 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
599 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D64, RC: &Mips::FGR64RegClass, Op0);
600 }
601 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
602 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D32, RC: &Mips::AFGR64RegClass, Op0);
603 }
604 return Register();
605}
606
607Register fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, Register Op0) {
608 if (RetVT.SimpleTy != MVT::v4f32)
609 return Register();
610 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
611 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_W, RC: &Mips::MSA128WRegClass, Op0);
612 }
613 return Register();
614}
615
616Register fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, Register Op0) {
617 if (RetVT.SimpleTy != MVT::v2f64)
618 return Register();
619 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
620 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D, RC: &Mips::MSA128DRegClass, Op0);
621 }
622 return Register();
623}
624
625Register fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, Register Op0) {
626 switch (VT.SimpleTy) {
627 case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0);
628 case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0);
629 case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0);
630 case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0);
631 default: return Register();
632 }
633}
634
635// FastEmit functions for ISD::SIGN_EXTEND.
636
637Register fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, Register Op0) {
638 if (RetVT.SimpleTy != MVT::i64)
639 return Register();
640 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())) {
641 return fastEmitInst_r(MachineInstOpcode: Mips::SLL64_32, RC: &Mips::GPR64RegClass, Op0);
642 }
643 return Register();
644}
645
646Register fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
647 switch (VT.SimpleTy) {
648 case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0);
649 default: return Register();
650 }
651}
652
653// FastEmit functions for ISD::SINT_TO_FP.
654
655Register fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
656 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_S_W, RC: &Mips::FGR32RegClass, Op0);
657}
658
659Register fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
660 if ((Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
661 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D64_W, RC: &Mips::FGR64RegClass, Op0);
662 }
663 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) {
664 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D32_W, RC: &Mips::AFGR64RegClass, Op0);
665 }
666 return Register();
667}
668
669Register fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
670switch (RetVT.SimpleTy) {
671 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
672 case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
673 default: return Register();
674}
675}
676
677Register fastEmit_ISD_SINT_TO_FP_MVT_i64_r(MVT RetVT, Register Op0) {
678 if (RetVT.SimpleTy != MVT::f64)
679 return Register();
680 if ((Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
681 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D64_L, RC: &Mips::FGR64RegClass, Op0);
682 }
683 return Register();
684}
685
686Register fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
687 if (RetVT.SimpleTy != MVT::v4f32)
688 return Register();
689 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
690 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_S_W, RC: &Mips::MSA128WRegClass, Op0);
691 }
692 return Register();
693}
694
695Register fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, Register Op0) {
696 if (RetVT.SimpleTy != MVT::v2f64)
697 return Register();
698 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
699 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_S_D, RC: &Mips::MSA128DRegClass, Op0);
700 }
701 return Register();
702}
703
704Register fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
705 switch (VT.SimpleTy) {
706 case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0);
707 case MVT::i64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_r(RetVT, Op0);
708 case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
709 case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
710 default: return Register();
711 }
712}
713
714// FastEmit functions for ISD::STRICT_FP_EXTEND.
715
716Register fastEmit_ISD_STRICT_FP_EXTEND_MVT_f32_r(MVT RetVT, Register Op0) {
717 if (RetVT.SimpleTy != MVT::f64)
718 return Register();
719 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->inMicroMipsMode())) {
720 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D64_S, RC: &Mips::FGR64RegClass, Op0);
721 }
722 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
723 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D32_S, RC: &Mips::AFGR64RegClass, Op0);
724 }
725 return Register();
726}
727
728Register fastEmit_ISD_STRICT_FP_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
729 switch (VT.SimpleTy) {
730 case MVT::f32: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_f32_r(RetVT, Op0);
731 default: return Register();
732 }
733}
734
735// FastEmit functions for ISD::STRICT_FP_ROUND.
736
737Register fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(MVT RetVT, Register Op0) {
738 if (RetVT.SimpleTy != MVT::f32)
739 return Register();
740 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->inMicroMipsMode())) {
741 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D64, RC: &Mips::FGR32RegClass, Op0);
742 }
743 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
744 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D32, RC: &Mips::FGR32RegClass, Op0);
745 }
746 return Register();
747}
748
749Register fastEmit_ISD_STRICT_FP_ROUND_r(MVT VT, MVT RetVT, Register Op0) {
750 switch (VT.SimpleTy) {
751 case MVT::f64: return fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(RetVT, Op0);
752 default: return Register();
753 }
754}
755
756// FastEmit functions for ISD::STRICT_FRINT.
757
758Register fastEmit_ISD_STRICT_FRINT_MVT_f32_r(MVT RetVT, Register Op0) {
759 if (RetVT.SimpleTy != MVT::f32)
760 return Register();
761 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
762 return fastEmitInst_r(MachineInstOpcode: Mips::RINT_S, RC: &Mips::FGR32RegClass, Op0);
763 }
764 return Register();
765}
766
767Register fastEmit_ISD_STRICT_FRINT_MVT_f64_r(MVT RetVT, Register Op0) {
768 if (RetVT.SimpleTy != MVT::f64)
769 return Register();
770 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
771 return fastEmitInst_r(MachineInstOpcode: Mips::RINT_D, RC: &Mips::FGR64RegClass, Op0);
772 }
773 return Register();
774}
775
776Register fastEmit_ISD_STRICT_FRINT_r(MVT VT, MVT RetVT, Register Op0) {
777 switch (VT.SimpleTy) {
778 case MVT::f32: return fastEmit_ISD_STRICT_FRINT_MVT_f32_r(RetVT, Op0);
779 case MVT::f64: return fastEmit_ISD_STRICT_FRINT_MVT_f64_r(RetVT, Op0);
780 default: return Register();
781 }
782}
783
784// FastEmit functions for ISD::STRICT_FSQRT.
785
786Register fastEmit_ISD_STRICT_FSQRT_MVT_f32_r(MVT RetVT, Register Op0) {
787 if (RetVT.SimpleTy != MVT::f32)
788 return Register();
789 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
790 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_S, RC: &Mips::FGR32RegClass, Op0);
791 }
792 return Register();
793}
794
795Register fastEmit_ISD_STRICT_FSQRT_MVT_f64_r(MVT RetVT, Register Op0) {
796 if (RetVT.SimpleTy != MVT::f64)
797 return Register();
798 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
799 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D64, RC: &Mips::FGR64RegClass, Op0);
800 }
801 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
802 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D32, RC: &Mips::AFGR64RegClass, Op0);
803 }
804 return Register();
805}
806
807Register fastEmit_ISD_STRICT_FSQRT_r(MVT VT, MVT RetVT, Register Op0) {
808 switch (VT.SimpleTy) {
809 case MVT::f32: return fastEmit_ISD_STRICT_FSQRT_MVT_f32_r(RetVT, Op0);
810 case MVT::f64: return fastEmit_ISD_STRICT_FSQRT_MVT_f64_r(RetVT, Op0);
811 default: return Register();
812 }
813}
814
815// FastEmit functions for ISD::STRICT_SINT_TO_FP.
816
817Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
818 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_S_W, RC: &Mips::FGR32RegClass, Op0);
819}
820
821Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
822 if ((Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
823 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D64_W, RC: &Mips::FGR64RegClass, Op0);
824 }
825 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) {
826 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D32_W, RC: &Mips::AFGR64RegClass, Op0);
827 }
828 return Register();
829}
830
831Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
832switch (RetVT.SimpleTy) {
833 case MVT::f32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
834 case MVT::f64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
835 default: return Register();
836}
837}
838
839Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_r(MVT RetVT, Register Op0) {
840 if (RetVT.SimpleTy != MVT::f64)
841 return Register();
842 if ((Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
843 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D64_L, RC: &Mips::FGR64RegClass, Op0);
844 }
845 return Register();
846}
847
848Register fastEmit_ISD_STRICT_SINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
849 switch (VT.SimpleTy) {
850 case MVT::i32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(RetVT, Op0);
851 case MVT::i64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_r(RetVT, Op0);
852 default: return Register();
853 }
854}
855
856// FastEmit functions for ISD::UINT_TO_FP.
857
858Register fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
859 if (RetVT.SimpleTy != MVT::v4f32)
860 return Register();
861 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
862 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_U_W, RC: &Mips::MSA128WRegClass, Op0);
863 }
864 return Register();
865}
866
867Register fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, Register Op0) {
868 if (RetVT.SimpleTy != MVT::v2f64)
869 return Register();
870 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
871 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_U_D, RC: &Mips::MSA128DRegClass, Op0);
872 }
873 return Register();
874}
875
876Register fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
877 switch (VT.SimpleTy) {
878 case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
879 case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
880 default: return Register();
881 }
882}
883
884// FastEmit functions for MipsISD::MFHI.
885
886Register fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(Register Op0) {
887 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
888 return fastEmitInst_r(MachineInstOpcode: Mips::MFHI_DSP_MM, RC: &Mips::GPR32RegClass, Op0);
889 }
890 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
891 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFHI_MM, RC: &Mips::GPR32RegClass, Op0);
892 }
893 if ((Subtarget->hasDSP())) {
894 return fastEmitInst_r(MachineInstOpcode: Mips::MFHI_DSP, RC: &Mips::GPR32RegClass, Op0);
895 }
896 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
897 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFHI, RC: &Mips::GPR32RegClass, Op0);
898 }
899 return Register();
900}
901
902Register fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(Register Op0) {
903 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
904 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFHI64, RC: &Mips::GPR64RegClass, Op0);
905 }
906 return Register();
907}
908
909Register fastEmit_MipsISD_MFHI_MVT_Untyped_r(MVT RetVT, Register Op0) {
910switch (RetVT.SimpleTy) {
911 case MVT::i32: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(Op0);
912 case MVT::i64: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(Op0);
913 default: return Register();
914}
915}
916
917Register fastEmit_MipsISD_MFHI_r(MVT VT, MVT RetVT, Register Op0) {
918 switch (VT.SimpleTy) {
919 case MVT::Untyped: return fastEmit_MipsISD_MFHI_MVT_Untyped_r(RetVT, Op0);
920 default: return Register();
921 }
922}
923
924// FastEmit functions for MipsISD::MFLO.
925
926Register fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(Register Op0) {
927 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
928 return fastEmitInst_r(MachineInstOpcode: Mips::MFLO_DSP_MM, RC: &Mips::GPR32RegClass, Op0);
929 }
930 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
931 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFLO_MM, RC: &Mips::GPR32RegClass, Op0);
932 }
933 if ((Subtarget->hasDSP())) {
934 return fastEmitInst_r(MachineInstOpcode: Mips::MFLO_DSP, RC: &Mips::GPR32RegClass, Op0);
935 }
936 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
937 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFLO, RC: &Mips::GPR32RegClass, Op0);
938 }
939 return Register();
940}
941
942Register fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(Register Op0) {
943 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
944 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFLO64, RC: &Mips::GPR64RegClass, Op0);
945 }
946 return Register();
947}
948
949Register fastEmit_MipsISD_MFLO_MVT_Untyped_r(MVT RetVT, Register Op0) {
950switch (RetVT.SimpleTy) {
951 case MVT::i32: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(Op0);
952 case MVT::i64: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(Op0);
953 default: return Register();
954}
955}
956
957Register fastEmit_MipsISD_MFLO_r(MVT VT, MVT RetVT, Register Op0) {
958 switch (VT.SimpleTy) {
959 case MVT::Untyped: return fastEmit_MipsISD_MFLO_MVT_Untyped_r(RetVT, Op0);
960 default: return Register();
961 }
962}
963
964// FastEmit functions for MipsISD::MTC1_D64.
965
966Register fastEmit_MipsISD_MTC1_D64_MVT_i32_r(MVT RetVT, Register Op0) {
967 if (RetVT.SimpleTy != MVT::f64)
968 return Register();
969 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
970 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_D64_MM, RC: &Mips::FGR64RegClass, Op0);
971 }
972 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
973 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_D64, RC: &Mips::FGR64RegClass, Op0);
974 }
975 return Register();
976}
977
978Register fastEmit_MipsISD_MTC1_D64_r(MVT VT, MVT RetVT, Register Op0) {
979 switch (VT.SimpleTy) {
980 case MVT::i32: return fastEmit_MipsISD_MTC1_D64_MVT_i32_r(RetVT, Op0);
981 default: return Register();
982 }
983}
984
985// FastEmit functions for MipsISD::TruncIntFP.
986
987Register fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(Register Op0) {
988 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
989 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_S_MMR6, RC: &Mips::FGR32RegClass, Op0);
990 }
991 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
992 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_S_MM, RC: &Mips::FGR32RegClass, Op0);
993 }
994 if ((Subtarget->hasStandardEncoding())) {
995 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_S, RC: &Mips::FGR32RegClass, Op0);
996 }
997 if ((Subtarget->isR5900())) {
998 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_W_S, RC: &Mips::FGR32RegClass, Op0);
999 }
1000 return Register();
1001}
1002
1003Register fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(Register Op0) {
1004 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
1005 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_L_S, RC: &Mips::FGR64RegClass, Op0);
1006 }
1007 return Register();
1008}
1009
1010Register fastEmit_MipsISD_TruncIntFP_MVT_f32_r(MVT RetVT, Register Op0) {
1011switch (RetVT.SimpleTy) {
1012 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(Op0);
1013 case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(Op0);
1014 default: return Register();
1015}
1016}
1017
1018Register fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(Register Op0) {
1019 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1020 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_D_MMR6, RC: &Mips::FGR32RegClass, Op0);
1021 }
1022 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->hasMips32r6())) {
1023 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_W_D64_MM, RC: &Mips::FGR32RegClass, Op0);
1024 }
1025 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())) {
1026 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_MM, RC: &Mips::FGR32RegClass, Op0);
1027 }
1028 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
1029 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_D64, RC: &Mips::FGR32RegClass, Op0);
1030 }
1031 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1032 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_D32, RC: &Mips::FGR32RegClass, Op0);
1033 }
1034 return Register();
1035}
1036
1037Register fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(Register Op0) {
1038 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
1039 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_L_D64, RC: &Mips::FGR64RegClass, Op0);
1040 }
1041 return Register();
1042}
1043
1044Register fastEmit_MipsISD_TruncIntFP_MVT_f64_r(MVT RetVT, Register Op0) {
1045switch (RetVT.SimpleTy) {
1046 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(Op0);
1047 case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(Op0);
1048 default: return Register();
1049}
1050}
1051
1052Register fastEmit_MipsISD_TruncIntFP_r(MVT VT, MVT RetVT, Register Op0) {
1053 switch (VT.SimpleTy) {
1054 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_r(RetVT, Op0);
1055 case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_r(RetVT, Op0);
1056 default: return Register();
1057 }
1058}
1059
1060// FastEmit functions for MipsISD::VALL_NONZERO.
1061
1062Register fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(MVT RetVT, Register Op0) {
1063 if (RetVT.SimpleTy != MVT::i32)
1064 return Register();
1065 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_B_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1066}
1067
1068Register fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(MVT RetVT, Register Op0) {
1069 if (RetVT.SimpleTy != MVT::i32)
1070 return Register();
1071 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_H_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1072}
1073
1074Register fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(MVT RetVT, Register Op0) {
1075 if (RetVT.SimpleTy != MVT::i32)
1076 return Register();
1077 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_W_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1078}
1079
1080Register fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(MVT RetVT, Register Op0) {
1081 if (RetVT.SimpleTy != MVT::i32)
1082 return Register();
1083 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_D_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1084}
1085
1086Register fastEmit_MipsISD_VALL_NONZERO_r(MVT VT, MVT RetVT, Register Op0) {
1087 switch (VT.SimpleTy) {
1088 case MVT::v16i8: return fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(RetVT, Op0);
1089 case MVT::v8i16: return fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(RetVT, Op0);
1090 case MVT::v4i32: return fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(RetVT, Op0);
1091 case MVT::v2i64: return fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(RetVT, Op0);
1092 default: return Register();
1093 }
1094}
1095
1096// FastEmit functions for MipsISD::VALL_ZERO.
1097
1098Register fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(MVT RetVT, Register Op0) {
1099 if (RetVT.SimpleTy != MVT::i32)
1100 return Register();
1101 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_B_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1102}
1103
1104Register fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(MVT RetVT, Register Op0) {
1105 if (RetVT.SimpleTy != MVT::i32)
1106 return Register();
1107 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_H_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1108}
1109
1110Register fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(MVT RetVT, Register Op0) {
1111 if (RetVT.SimpleTy != MVT::i32)
1112 return Register();
1113 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_W_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1114}
1115
1116Register fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(MVT RetVT, Register Op0) {
1117 if (RetVT.SimpleTy != MVT::i32)
1118 return Register();
1119 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_D_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1120}
1121
1122Register fastEmit_MipsISD_VALL_ZERO_r(MVT VT, MVT RetVT, Register Op0) {
1123 switch (VT.SimpleTy) {
1124 case MVT::v16i8: return fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(RetVT, Op0);
1125 case MVT::v8i16: return fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(RetVT, Op0);
1126 case MVT::v4i32: return fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(RetVT, Op0);
1127 case MVT::v2i64: return fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(RetVT, Op0);
1128 default: return Register();
1129 }
1130}
1131
1132// FastEmit functions for MipsISD::VANY_NONZERO.
1133
1134Register fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(MVT RetVT, Register Op0) {
1135 if (RetVT.SimpleTy != MVT::i32)
1136 return Register();
1137 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_V_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1138}
1139
1140Register fastEmit_MipsISD_VANY_NONZERO_r(MVT VT, MVT RetVT, Register Op0) {
1141 switch (VT.SimpleTy) {
1142 case MVT::v16i8: return fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(RetVT, Op0);
1143 default: return Register();
1144 }
1145}
1146
1147// FastEmit functions for MipsISD::VANY_ZERO.
1148
1149Register fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(MVT RetVT, Register Op0) {
1150 if (RetVT.SimpleTy != MVT::i32)
1151 return Register();
1152 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_V_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1153}
1154
1155Register fastEmit_MipsISD_VANY_ZERO_r(MVT VT, MVT RetVT, Register Op0) {
1156 switch (VT.SimpleTy) {
1157 case MVT::v16i8: return fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(RetVT, Op0);
1158 default: return Register();
1159 }
1160}
1161
1162// Top-level FastEmit function.
1163
1164Register fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, Register Op0) override {
1165 switch (Opcode) {
1166 case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0);
1167 case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0);
1168 case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0);
1169 case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0);
1170 case ISD::FEXP2: return fastEmit_ISD_FEXP2_r(VT, RetVT, Op0);
1171 case ISD::FLOG2: return fastEmit_ISD_FLOG2_r(VT, RetVT, Op0);
1172 case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0);
1173 case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0);
1174 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0);
1175 case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0);
1176 case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0);
1177 case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0);
1178 case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0);
1179 case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0);
1180 case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0);
1181 case ISD::STRICT_FP_EXTEND: return fastEmit_ISD_STRICT_FP_EXTEND_r(VT, RetVT, Op0);
1182 case ISD::STRICT_FP_ROUND: return fastEmit_ISD_STRICT_FP_ROUND_r(VT, RetVT, Op0);
1183 case ISD::STRICT_FRINT: return fastEmit_ISD_STRICT_FRINT_r(VT, RetVT, Op0);
1184 case ISD::STRICT_FSQRT: return fastEmit_ISD_STRICT_FSQRT_r(VT, RetVT, Op0);
1185 case ISD::STRICT_SINT_TO_FP: return fastEmit_ISD_STRICT_SINT_TO_FP_r(VT, RetVT, Op0);
1186 case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0);
1187 case MipsISD::MFHI: return fastEmit_MipsISD_MFHI_r(VT, RetVT, Op0);
1188 case MipsISD::MFLO: return fastEmit_MipsISD_MFLO_r(VT, RetVT, Op0);
1189 case MipsISD::MTC1_D64: return fastEmit_MipsISD_MTC1_D64_r(VT, RetVT, Op0);
1190 case MipsISD::TruncIntFP: return fastEmit_MipsISD_TruncIntFP_r(VT, RetVT, Op0);
1191 case MipsISD::VALL_NONZERO: return fastEmit_MipsISD_VALL_NONZERO_r(VT, RetVT, Op0);
1192 case MipsISD::VALL_ZERO: return fastEmit_MipsISD_VALL_ZERO_r(VT, RetVT, Op0);
1193 case MipsISD::VANY_NONZERO: return fastEmit_MipsISD_VANY_NONZERO_r(VT, RetVT, Op0);
1194 case MipsISD::VANY_ZERO: return fastEmit_MipsISD_VANY_ZERO_r(VT, RetVT, Op0);
1195 default: return Register();
1196 }
1197}
1198
1199// FastEmit functions for ISD::ADD.
1200
1201Register fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1202 if (RetVT.SimpleTy != MVT::i32)
1203 return Register();
1204 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1205 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDU16_MMR6, RC: &Mips::GPRMM16RegClass, Op0, Op1);
1206 }
1207 if ((Subtarget->inMips16Mode())) {
1208 return fastEmitInst_rr(MachineInstOpcode: Mips::AdduRxRyRz16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
1209 }
1210 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1211 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDu_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
1212 }
1213 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1214 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDu, RC: &Mips::GPR32RegClass, Op0, Op1);
1215 }
1216 return Register();
1217}
1218
1219Register fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1220 if (RetVT.SimpleTy != MVT::i64)
1221 return Register();
1222 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1223 return fastEmitInst_rr(MachineInstOpcode: Mips::DADDu, RC: &Mips::GPR64RegClass, Op0, Op1);
1224 }
1225 return Register();
1226}
1227
1228Register fastEmit_ISD_ADD_MVT_v4i8_rr(MVT RetVT, Register Op0, Register Op1) {
1229 if (RetVT.SimpleTy != MVT::v4i8)
1230 return Register();
1231 if ((Subtarget->hasDSP())) {
1232 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDU_QB, RC: &Mips::DSPRRegClass, Op0, Op1);
1233 }
1234 return Register();
1235}
1236
1237Register fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1238 if (RetVT.SimpleTy != MVT::v16i8)
1239 return Register();
1240 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1241 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
1242 }
1243 return Register();
1244}
1245
1246Register fastEmit_ISD_ADD_MVT_v2i16_rr(MVT RetVT, Register Op0, Register Op1) {
1247 if (RetVT.SimpleTy != MVT::v2i16)
1248 return Register();
1249 if ((Subtarget->hasDSP())) {
1250 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDQ_PH, RC: &Mips::DSPRRegClass, Op0, Op1);
1251 }
1252 return Register();
1253}
1254
1255Register fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1256 if (RetVT.SimpleTy != MVT::v8i16)
1257 return Register();
1258 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1259 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
1260 }
1261 return Register();
1262}
1263
1264Register fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
1265 if (RetVT.SimpleTy != MVT::v4i32)
1266 return Register();
1267 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1268 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1269 }
1270 return Register();
1271}
1272
1273Register fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
1274 if (RetVT.SimpleTy != MVT::v2i64)
1275 return Register();
1276 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1277 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1278 }
1279 return Register();
1280}
1281
1282Register fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1283 switch (VT.SimpleTy) {
1284 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op1);
1285 case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op1);
1286 case MVT::v4i8: return fastEmit_ISD_ADD_MVT_v4i8_rr(RetVT, Op0, Op1);
1287 case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op1);
1288 case MVT::v2i16: return fastEmit_ISD_ADD_MVT_v2i16_rr(RetVT, Op0, Op1);
1289 case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op1);
1290 case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op1);
1291 case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op1);
1292 default: return Register();
1293 }
1294}
1295
1296// FastEmit functions for ISD::ADDC.
1297
1298Register fastEmit_ISD_ADDC_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1299 if (RetVT.SimpleTy != MVT::i32)
1300 return Register();
1301 if ((Subtarget->hasDSP())) {
1302 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDSC, RC: &Mips::GPR32RegClass, Op0, Op1);
1303 }
1304 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP())) {
1305 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDu, RC: &Mips::GPR32RegClass, Op0, Op1);
1306 }
1307 return Register();
1308}
1309
1310Register fastEmit_ISD_ADDC_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1311 if (RetVT.SimpleTy != MVT::i64)
1312 return Register();
1313 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->hasDSP()) && (!Subtarget->inMicroMipsMode())) {
1314 return fastEmitInst_rr(MachineInstOpcode: Mips::DADDu, RC: &Mips::GPR64RegClass, Op0, Op1);
1315 }
1316 return Register();
1317}
1318
1319Register fastEmit_ISD_ADDC_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1320 switch (VT.SimpleTy) {
1321 case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_rr(RetVT, Op0, Op1);
1322 case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_rr(RetVT, Op0, Op1);
1323 default: return Register();
1324 }
1325}
1326
1327// FastEmit functions for ISD::ADDE.
1328
1329Register fastEmit_ISD_ADDE_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1330 if (RetVT.SimpleTy != MVT::i32)
1331 return Register();
1332 if ((Subtarget->hasDSP())) {
1333 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDWC, RC: &Mips::GPR32RegClass, Op0, Op1);
1334 }
1335 return Register();
1336}
1337
1338Register fastEmit_ISD_ADDE_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1339 switch (VT.SimpleTy) {
1340 case MVT::i32: return fastEmit_ISD_ADDE_MVT_i32_rr(RetVT, Op0, Op1);
1341 default: return Register();
1342 }
1343}
1344
1345// FastEmit functions for ISD::AND.
1346
1347Register fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1348 if (RetVT.SimpleTy != MVT::i32)
1349 return Register();
1350 if ((Subtarget->inMips16Mode())) {
1351 return fastEmitInst_rr(MachineInstOpcode: Mips::AndRxRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
1352 }
1353 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1354 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
1355 }
1356 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1357 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
1358 }
1359 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1360 return fastEmitInst_rr(MachineInstOpcode: Mips::AND, RC: &Mips::GPR32RegClass, Op0, Op1);
1361 }
1362 return Register();
1363}
1364
1365Register fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1366 if (RetVT.SimpleTy != MVT::i64)
1367 return Register();
1368 if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
1369 return fastEmitInst_rr(MachineInstOpcode: Mips::AND64, RC: &Mips::GPR64RegClass, Op0, Op1);
1370 }
1371 return Register();
1372}
1373
1374Register fastEmit_ISD_AND_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1375 if (RetVT.SimpleTy != MVT::v16i8)
1376 return Register();
1377 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1378 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
1379 }
1380 return Register();
1381}
1382
1383Register fastEmit_ISD_AND_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1384 if (RetVT.SimpleTy != MVT::v8i16)
1385 return Register();
1386 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1387 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
1388 }
1389 return Register();
1390}
1391
1392Register fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
1393 if (RetVT.SimpleTy != MVT::v4i32)
1394 return Register();
1395 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1396 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
1397 }
1398 return Register();
1399}
1400
1401Register fastEmit_ISD_AND_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
1402 if (RetVT.SimpleTy != MVT::v2i64)
1403 return Register();
1404 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1405 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
1406 }
1407 return Register();
1408}
1409
1410Register fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1411 switch (VT.SimpleTy) {
1412 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op1);
1413 case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op1);
1414 case MVT::v16i8: return fastEmit_ISD_AND_MVT_v16i8_rr(RetVT, Op0, Op1);
1415 case MVT::v8i16: return fastEmit_ISD_AND_MVT_v8i16_rr(RetVT, Op0, Op1);
1416 case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op1);
1417 case MVT::v2i64: return fastEmit_ISD_AND_MVT_v2i64_rr(RetVT, Op0, Op1);
1418 default: return Register();
1419 }
1420}
1421
1422// FastEmit functions for ISD::FADD.
1423
1424Register fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1425 if (RetVT.SimpleTy != MVT::f32)
1426 return Register();
1427 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1428 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1429 }
1430 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1431 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1432 }
1433 return Register();
1434}
1435
1436Register fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1437 if (RetVT.SimpleTy != MVT::f64)
1438 return Register();
1439 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
1440 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1441 }
1442 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1443 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1444 }
1445 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1446 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1447 }
1448 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1449 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1450 }
1451 return Register();
1452}
1453
1454Register fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1455 if (RetVT.SimpleTy != MVT::v4f32)
1456 return Register();
1457 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1458 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1459 }
1460 return Register();
1461}
1462
1463Register fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1464 if (RetVT.SimpleTy != MVT::v2f64)
1465 return Register();
1466 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1467 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1468 }
1469 return Register();
1470}
1471
1472Register fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1473 switch (VT.SimpleTy) {
1474 case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op1);
1475 case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op1);
1476 case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op1);
1477 case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op1);
1478 default: return Register();
1479 }
1480}
1481
1482// FastEmit functions for ISD::FDIV.
1483
1484Register fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1485 if (RetVT.SimpleTy != MVT::f32)
1486 return Register();
1487 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1488 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1489 }
1490 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1491 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1492 }
1493 return Register();
1494}
1495
1496Register fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1497 if (RetVT.SimpleTy != MVT::f64)
1498 return Register();
1499 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
1500 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1501 }
1502 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1503 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1504 }
1505 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1506 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1507 }
1508 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1509 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1510 }
1511 return Register();
1512}
1513
1514Register fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1515 if (RetVT.SimpleTy != MVT::v4f32)
1516 return Register();
1517 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1518 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1519 }
1520 return Register();
1521}
1522
1523Register fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1524 if (RetVT.SimpleTy != MVT::v2f64)
1525 return Register();
1526 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1527 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1528 }
1529 return Register();
1530}
1531
1532Register fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1533 switch (VT.SimpleTy) {
1534 case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op1);
1535 case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op1);
1536 case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op1);
1537 case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op1);
1538 default: return Register();
1539 }
1540}
1541
1542// FastEmit functions for ISD::FMAXNUM.
1543
1544Register fastEmit_ISD_FMAXNUM_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1545 if (RetVT.SimpleTy != MVT::f32)
1546 return Register();
1547 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1548 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1549 }
1550 return Register();
1551}
1552
1553Register fastEmit_ISD_FMAXNUM_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1554 if (RetVT.SimpleTy != MVT::f64)
1555 return Register();
1556 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1557 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_D, RC: &Mips::FGR64RegClass, Op0, Op1);
1558 }
1559 return Register();
1560}
1561
1562Register fastEmit_ISD_FMAXNUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1563 switch (VT.SimpleTy) {
1564 case MVT::f32: return fastEmit_ISD_FMAXNUM_MVT_f32_rr(RetVT, Op0, Op1);
1565 case MVT::f64: return fastEmit_ISD_FMAXNUM_MVT_f64_rr(RetVT, Op0, Op1);
1566 default: return Register();
1567 }
1568}
1569
1570// FastEmit functions for ISD::FMAXNUM_IEEE.
1571
1572Register fastEmit_ISD_FMAXNUM_IEEE_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1573 if (RetVT.SimpleTy != MVT::f32)
1574 return Register();
1575 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1576 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1577 }
1578 return Register();
1579}
1580
1581Register fastEmit_ISD_FMAXNUM_IEEE_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1582 if (RetVT.SimpleTy != MVT::f64)
1583 return Register();
1584 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1585 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_D, RC: &Mips::FGR64RegClass, Op0, Op1);
1586 }
1587 return Register();
1588}
1589
1590Register fastEmit_ISD_FMAXNUM_IEEE_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1591 switch (VT.SimpleTy) {
1592 case MVT::f32: return fastEmit_ISD_FMAXNUM_IEEE_MVT_f32_rr(RetVT, Op0, Op1);
1593 case MVT::f64: return fastEmit_ISD_FMAXNUM_IEEE_MVT_f64_rr(RetVT, Op0, Op1);
1594 default: return Register();
1595 }
1596}
1597
1598// FastEmit functions for ISD::FMINNUM.
1599
1600Register fastEmit_ISD_FMINNUM_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1601 if (RetVT.SimpleTy != MVT::f32)
1602 return Register();
1603 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1604 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1605 }
1606 return Register();
1607}
1608
1609Register fastEmit_ISD_FMINNUM_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1610 if (RetVT.SimpleTy != MVT::f64)
1611 return Register();
1612 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1613 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_D, RC: &Mips::FGR64RegClass, Op0, Op1);
1614 }
1615 return Register();
1616}
1617
1618Register fastEmit_ISD_FMINNUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1619 switch (VT.SimpleTy) {
1620 case MVT::f32: return fastEmit_ISD_FMINNUM_MVT_f32_rr(RetVT, Op0, Op1);
1621 case MVT::f64: return fastEmit_ISD_FMINNUM_MVT_f64_rr(RetVT, Op0, Op1);
1622 default: return Register();
1623 }
1624}
1625
1626// FastEmit functions for ISD::FMINNUM_IEEE.
1627
1628Register fastEmit_ISD_FMINNUM_IEEE_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1629 if (RetVT.SimpleTy != MVT::f32)
1630 return Register();
1631 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1632 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1633 }
1634 return Register();
1635}
1636
1637Register fastEmit_ISD_FMINNUM_IEEE_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1638 if (RetVT.SimpleTy != MVT::f64)
1639 return Register();
1640 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1641 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_D, RC: &Mips::FGR64RegClass, Op0, Op1);
1642 }
1643 return Register();
1644}
1645
1646Register fastEmit_ISD_FMINNUM_IEEE_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1647 switch (VT.SimpleTy) {
1648 case MVT::f32: return fastEmit_ISD_FMINNUM_IEEE_MVT_f32_rr(RetVT, Op0, Op1);
1649 case MVT::f64: return fastEmit_ISD_FMINNUM_IEEE_MVT_f64_rr(RetVT, Op0, Op1);
1650 default: return Register();
1651 }
1652}
1653
1654// FastEmit functions for ISD::FMUL.
1655
1656Register fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1657 if (RetVT.SimpleTy != MVT::f32)
1658 return Register();
1659 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1660 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1661 }
1662 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1663 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1664 }
1665 return Register();
1666}
1667
1668Register fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1669 if (RetVT.SimpleTy != MVT::f64)
1670 return Register();
1671 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
1672 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1673 }
1674 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1675 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1676 }
1677 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1678 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1679 }
1680 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1681 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1682 }
1683 return Register();
1684}
1685
1686Register fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1687 if (RetVT.SimpleTy != MVT::v4f32)
1688 return Register();
1689 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1690 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1691 }
1692 return Register();
1693}
1694
1695Register fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1696 if (RetVT.SimpleTy != MVT::v2f64)
1697 return Register();
1698 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1699 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1700 }
1701 return Register();
1702}
1703
1704Register fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1705 switch (VT.SimpleTy) {
1706 case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op1);
1707 case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op1);
1708 case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op1);
1709 case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op1);
1710 default: return Register();
1711 }
1712}
1713
1714// FastEmit functions for ISD::FSUB.
1715
1716Register fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1717 if (RetVT.SimpleTy != MVT::f32)
1718 return Register();
1719 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1720 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1721 }
1722 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1723 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1724 }
1725 return Register();
1726}
1727
1728Register fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1729 if (RetVT.SimpleTy != MVT::f64)
1730 return Register();
1731 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
1732 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1733 }
1734 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1735 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1736 }
1737 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1738 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1739 }
1740 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1741 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1742 }
1743 return Register();
1744}
1745
1746Register fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1747 if (RetVT.SimpleTy != MVT::v4f32)
1748 return Register();
1749 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1750 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1751 }
1752 return Register();
1753}
1754
1755Register fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1756 if (RetVT.SimpleTy != MVT::v2f64)
1757 return Register();
1758 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1759 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1760 }
1761 return Register();
1762}
1763
1764Register fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1765 switch (VT.SimpleTy) {
1766 case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op1);
1767 case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op1);
1768 case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op1);
1769 case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op1);
1770 default: return Register();
1771 }
1772}
1773
1774// FastEmit functions for ISD::MUL.
1775
1776Register fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1777 if (RetVT.SimpleTy != MVT::i32)
1778 return Register();
1779 if ((Subtarget->inMips16Mode())) {
1780 return fastEmitInst_rr(MachineInstOpcode: Mips::MultRxRyRz16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
1781 }
1782 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1783 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
1784 }
1785 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1786 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
1787 }
1788 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1789 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_R6, RC: &Mips::GPR32RegClass, Op0, Op1);
1790 }
1791 if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
1792 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL, RC: &Mips::GPR32RegClass, Op0, Op1);
1793 }
1794 return Register();
1795}
1796
1797Register fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1798 if (RetVT.SimpleTy != MVT::i64)
1799 return Register();
1800 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1801 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUL_R6, RC: &Mips::GPR64RegClass, Op0, Op1);
1802 }
1803 if ((Subtarget->hasCnMips())) {
1804 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUL, RC: &Mips::GPR64RegClass, Op0, Op1);
1805 }
1806 return Register();
1807}
1808
1809Register fastEmit_ISD_MUL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1810 if (RetVT.SimpleTy != MVT::v16i8)
1811 return Register();
1812 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1813 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
1814 }
1815 return Register();
1816}
1817
1818Register fastEmit_ISD_MUL_MVT_v2i16_rr(MVT RetVT, Register Op0, Register Op1) {
1819 if (RetVT.SimpleTy != MVT::v2i16)
1820 return Register();
1821 if ((Subtarget->hasDSPR2())) {
1822 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_PH, RC: &Mips::DSPRRegClass, Op0, Op1);
1823 }
1824 return Register();
1825}
1826
1827Register fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1828 if (RetVT.SimpleTy != MVT::v8i16)
1829 return Register();
1830 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1831 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
1832 }
1833 return Register();
1834}
1835
1836Register fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
1837 if (RetVT.SimpleTy != MVT::v4i32)
1838 return Register();
1839 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1840 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1841 }
1842 return Register();
1843}
1844
1845Register fastEmit_ISD_MUL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
1846 if (RetVT.SimpleTy != MVT::v2i64)
1847 return Register();
1848 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1849 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1850 }
1851 return Register();
1852}
1853
1854Register fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1855 switch (VT.SimpleTy) {
1856 case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op1);
1857 case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op1);
1858 case MVT::v16i8: return fastEmit_ISD_MUL_MVT_v16i8_rr(RetVT, Op0, Op1);
1859 case MVT::v2i16: return fastEmit_ISD_MUL_MVT_v2i16_rr(RetVT, Op0, Op1);
1860 case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op1);
1861 case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op1);
1862 case MVT::v2i64: return fastEmit_ISD_MUL_MVT_v2i64_rr(RetVT, Op0, Op1);
1863 default: return Register();
1864 }
1865}
1866
1867// FastEmit functions for ISD::MULHS.
1868
1869Register fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1870 if (RetVT.SimpleTy != MVT::i32)
1871 return Register();
1872 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1873 return fastEmitInst_rr(MachineInstOpcode: Mips::MUH_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
1874 }
1875 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1876 return fastEmitInst_rr(MachineInstOpcode: Mips::MUH, RC: &Mips::GPR32RegClass, Op0, Op1);
1877 }
1878 return Register();
1879}
1880
1881Register fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1882 if (RetVT.SimpleTy != MVT::i64)
1883 return Register();
1884 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1885 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUH, RC: &Mips::GPR64RegClass, Op0, Op1);
1886 }
1887 return Register();
1888}
1889
1890Register fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1891 switch (VT.SimpleTy) {
1892 case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op1);
1893 case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op1);
1894 default: return Register();
1895 }
1896}
1897
1898// FastEmit functions for ISD::MULHU.
1899
1900Register fastEmit_ISD_MULHU_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1901 if (RetVT.SimpleTy != MVT::i32)
1902 return Register();
1903 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1904 return fastEmitInst_rr(MachineInstOpcode: Mips::MUHU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
1905 }
1906 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1907 return fastEmitInst_rr(MachineInstOpcode: Mips::MUHU, RC: &Mips::GPR32RegClass, Op0, Op1);
1908 }
1909 return Register();
1910}
1911
1912Register fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1913 if (RetVT.SimpleTy != MVT::i64)
1914 return Register();
1915 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1916 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUHU, RC: &Mips::GPR64RegClass, Op0, Op1);
1917 }
1918 return Register();
1919}
1920
1921Register fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1922 switch (VT.SimpleTy) {
1923 case MVT::i32: return fastEmit_ISD_MULHU_MVT_i32_rr(RetVT, Op0, Op1);
1924 case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op1);
1925 default: return Register();
1926 }
1927}
1928
1929// FastEmit functions for ISD::OR.
1930
1931Register fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1932 if (RetVT.SimpleTy != MVT::i32)
1933 return Register();
1934 if ((Subtarget->inMips16Mode())) {
1935 return fastEmitInst_rr(MachineInstOpcode: Mips::OrRxRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
1936 }
1937 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1938 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
1939 }
1940 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1941 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
1942 }
1943 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1944 return fastEmitInst_rr(MachineInstOpcode: Mips::OR, RC: &Mips::GPR32RegClass, Op0, Op1);
1945 }
1946 return Register();
1947}
1948
1949Register fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1950 if (RetVT.SimpleTy != MVT::i64)
1951 return Register();
1952 if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
1953 return fastEmitInst_rr(MachineInstOpcode: Mips::OR64, RC: &Mips::GPR64RegClass, Op0, Op1);
1954 }
1955 return Register();
1956}
1957
1958Register fastEmit_ISD_OR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1959 if (RetVT.SimpleTy != MVT::v16i8)
1960 return Register();
1961 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1962 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
1963 }
1964 return Register();
1965}
1966
1967Register fastEmit_ISD_OR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1968 if (RetVT.SimpleTy != MVT::v8i16)
1969 return Register();
1970 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1971 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
1972 }
1973 return Register();
1974}
1975
1976Register fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
1977 if (RetVT.SimpleTy != MVT::v4i32)
1978 return Register();
1979 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1980 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
1981 }
1982 return Register();
1983}
1984
1985Register fastEmit_ISD_OR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
1986 if (RetVT.SimpleTy != MVT::v2i64)
1987 return Register();
1988 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1989 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
1990 }
1991 return Register();
1992}
1993
1994Register fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1995 switch (VT.SimpleTy) {
1996 case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op1);
1997 case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op1);
1998 case MVT::v16i8: return fastEmit_ISD_OR_MVT_v16i8_rr(RetVT, Op0, Op1);
1999 case MVT::v8i16: return fastEmit_ISD_OR_MVT_v8i16_rr(RetVT, Op0, Op1);
2000 case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op1);
2001 case MVT::v2i64: return fastEmit_ISD_OR_MVT_v2i64_rr(RetVT, Op0, Op1);
2002 default: return Register();
2003 }
2004}
2005
2006// FastEmit functions for ISD::ROTR.
2007
2008Register fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2009 if (RetVT.SimpleTy != MVT::i32)
2010 return Register();
2011 if ((Subtarget->inMicroMipsMode())) {
2012 return fastEmitInst_rr(MachineInstOpcode: Mips::ROTRV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2013 }
2014 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2015 return fastEmitInst_rr(MachineInstOpcode: Mips::ROTRV, RC: &Mips::GPR32RegClass, Op0, Op1);
2016 }
2017 return Register();
2018}
2019
2020Register fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2021 switch (VT.SimpleTy) {
2022 case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op1);
2023 default: return Register();
2024 }
2025}
2026
2027// FastEmit functions for ISD::SDIV.
2028
2029Register fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2030 if (RetVT.SimpleTy != MVT::i32)
2031 return Register();
2032 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2033 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2034 }
2035 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2036 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV, RC: &Mips::GPR32RegClass, Op0, Op1);
2037 }
2038 return Register();
2039}
2040
2041Register fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2042 if (RetVT.SimpleTy != MVT::i64)
2043 return Register();
2044 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2045 return fastEmitInst_rr(MachineInstOpcode: Mips::DDIV, RC: &Mips::GPR64RegClass, Op0, Op1);
2046 }
2047 return Register();
2048}
2049
2050Register fastEmit_ISD_SDIV_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2051 if (RetVT.SimpleTy != MVT::v16i8)
2052 return Register();
2053 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2054 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2055 }
2056 return Register();
2057}
2058
2059Register fastEmit_ISD_SDIV_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2060 if (RetVT.SimpleTy != MVT::v8i16)
2061 return Register();
2062 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2063 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2064 }
2065 return Register();
2066}
2067
2068Register fastEmit_ISD_SDIV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2069 if (RetVT.SimpleTy != MVT::v4i32)
2070 return Register();
2071 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2072 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2073 }
2074 return Register();
2075}
2076
2077Register fastEmit_ISD_SDIV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2078 if (RetVT.SimpleTy != MVT::v2i64)
2079 return Register();
2080 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2081 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2082 }
2083 return Register();
2084}
2085
2086Register fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2087 switch (VT.SimpleTy) {
2088 case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op1);
2089 case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op1);
2090 case MVT::v16i8: return fastEmit_ISD_SDIV_MVT_v16i8_rr(RetVT, Op0, Op1);
2091 case MVT::v8i16: return fastEmit_ISD_SDIV_MVT_v8i16_rr(RetVT, Op0, Op1);
2092 case MVT::v4i32: return fastEmit_ISD_SDIV_MVT_v4i32_rr(RetVT, Op0, Op1);
2093 case MVT::v2i64: return fastEmit_ISD_SDIV_MVT_v2i64_rr(RetVT, Op0, Op1);
2094 default: return Register();
2095 }
2096}
2097
2098// FastEmit functions for ISD::SHL.
2099
2100Register fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2101 if (RetVT.SimpleTy != MVT::i32)
2102 return Register();
2103 if ((Subtarget->inMicroMipsMode())) {
2104 return fastEmitInst_rr(MachineInstOpcode: Mips::SLLV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2105 }
2106 if ((Subtarget->inMips16Mode())) {
2107 return fastEmitInst_rr(MachineInstOpcode: Mips::SllvRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2108 }
2109 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2110 return fastEmitInst_rr(MachineInstOpcode: Mips::SLLV, RC: &Mips::GPR32RegClass, Op0, Op1);
2111 }
2112 return Register();
2113}
2114
2115Register fastEmit_ISD_SHL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2116 if (RetVT.SimpleTy != MVT::v16i8)
2117 return Register();
2118 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2119 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2120 }
2121 return Register();
2122}
2123
2124Register fastEmit_ISD_SHL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2125 if (RetVT.SimpleTy != MVT::v8i16)
2126 return Register();
2127 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2128 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2129 }
2130 return Register();
2131}
2132
2133Register fastEmit_ISD_SHL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2134 if (RetVT.SimpleTy != MVT::v4i32)
2135 return Register();
2136 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2137 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2138 }
2139 return Register();
2140}
2141
2142Register fastEmit_ISD_SHL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2143 if (RetVT.SimpleTy != MVT::v2i64)
2144 return Register();
2145 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2146 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2147 }
2148 return Register();
2149}
2150
2151Register fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2152 switch (VT.SimpleTy) {
2153 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op1);
2154 case MVT::v16i8: return fastEmit_ISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op1);
2155 case MVT::v8i16: return fastEmit_ISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op1);
2156 case MVT::v4i32: return fastEmit_ISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op1);
2157 case MVT::v2i64: return fastEmit_ISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op1);
2158 default: return Register();
2159 }
2160}
2161
2162// FastEmit functions for ISD::SMAX.
2163
2164Register fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2165 if (RetVT.SimpleTy != MVT::v16i8)
2166 return Register();
2167 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2168 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2169 }
2170 return Register();
2171}
2172
2173Register fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2174 if (RetVT.SimpleTy != MVT::v8i16)
2175 return Register();
2176 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2177 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2178 }
2179 return Register();
2180}
2181
2182Register fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2183 if (RetVT.SimpleTy != MVT::v4i32)
2184 return Register();
2185 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2186 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2187 }
2188 return Register();
2189}
2190
2191Register fastEmit_ISD_SMAX_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2192 if (RetVT.SimpleTy != MVT::v2i64)
2193 return Register();
2194 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2195 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2196 }
2197 return Register();
2198}
2199
2200Register fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2201 switch (VT.SimpleTy) {
2202 case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
2203 case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
2204 case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
2205 case MVT::v2i64: return fastEmit_ISD_SMAX_MVT_v2i64_rr(RetVT, Op0, Op1);
2206 default: return Register();
2207 }
2208}
2209
2210// FastEmit functions for ISD::SMIN.
2211
2212Register fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2213 if (RetVT.SimpleTy != MVT::v16i8)
2214 return Register();
2215 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2216 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2217 }
2218 return Register();
2219}
2220
2221Register fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2222 if (RetVT.SimpleTy != MVT::v8i16)
2223 return Register();
2224 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2225 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2226 }
2227 return Register();
2228}
2229
2230Register fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2231 if (RetVT.SimpleTy != MVT::v4i32)
2232 return Register();
2233 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2234 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2235 }
2236 return Register();
2237}
2238
2239Register fastEmit_ISD_SMIN_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2240 if (RetVT.SimpleTy != MVT::v2i64)
2241 return Register();
2242 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2243 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2244 }
2245 return Register();
2246}
2247
2248Register fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2249 switch (VT.SimpleTy) {
2250 case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
2251 case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
2252 case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
2253 case MVT::v2i64: return fastEmit_ISD_SMIN_MVT_v2i64_rr(RetVT, Op0, Op1);
2254 default: return Register();
2255 }
2256}
2257
2258// FastEmit functions for ISD::SRA.
2259
2260Register fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2261 if (RetVT.SimpleTy != MVT::i32)
2262 return Register();
2263 if ((Subtarget->inMicroMipsMode())) {
2264 return fastEmitInst_rr(MachineInstOpcode: Mips::SRAV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2265 }
2266 if ((Subtarget->inMips16Mode())) {
2267 return fastEmitInst_rr(MachineInstOpcode: Mips::SravRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2268 }
2269 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2270 return fastEmitInst_rr(MachineInstOpcode: Mips::SRAV, RC: &Mips::GPR32RegClass, Op0, Op1);
2271 }
2272 return Register();
2273}
2274
2275Register fastEmit_ISD_SRA_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2276 if (RetVT.SimpleTy != MVT::v16i8)
2277 return Register();
2278 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2279 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2280 }
2281 return Register();
2282}
2283
2284Register fastEmit_ISD_SRA_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2285 if (RetVT.SimpleTy != MVT::v8i16)
2286 return Register();
2287 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2288 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2289 }
2290 return Register();
2291}
2292
2293Register fastEmit_ISD_SRA_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2294 if (RetVT.SimpleTy != MVT::v4i32)
2295 return Register();
2296 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2297 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2298 }
2299 return Register();
2300}
2301
2302Register fastEmit_ISD_SRA_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2303 if (RetVT.SimpleTy != MVT::v2i64)
2304 return Register();
2305 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2306 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2307 }
2308 return Register();
2309}
2310
2311Register fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2312 switch (VT.SimpleTy) {
2313 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op1);
2314 case MVT::v16i8: return fastEmit_ISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op1);
2315 case MVT::v8i16: return fastEmit_ISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op1);
2316 case MVT::v4i32: return fastEmit_ISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op1);
2317 case MVT::v2i64: return fastEmit_ISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op1);
2318 default: return Register();
2319 }
2320}
2321
2322// FastEmit functions for ISD::SREM.
2323
2324Register fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2325 if (RetVT.SimpleTy != MVT::i32)
2326 return Register();
2327 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2328 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2329 }
2330 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2331 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD, RC: &Mips::GPR32RegClass, Op0, Op1);
2332 }
2333 return Register();
2334}
2335
2336Register fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2337 if (RetVT.SimpleTy != MVT::i64)
2338 return Register();
2339 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2340 return fastEmitInst_rr(MachineInstOpcode: Mips::DMOD, RC: &Mips::GPR64RegClass, Op0, Op1);
2341 }
2342 return Register();
2343}
2344
2345Register fastEmit_ISD_SREM_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2346 if (RetVT.SimpleTy != MVT::v16i8)
2347 return Register();
2348 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2349 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2350 }
2351 return Register();
2352}
2353
2354Register fastEmit_ISD_SREM_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2355 if (RetVT.SimpleTy != MVT::v8i16)
2356 return Register();
2357 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2358 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2359 }
2360 return Register();
2361}
2362
2363Register fastEmit_ISD_SREM_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2364 if (RetVT.SimpleTy != MVT::v4i32)
2365 return Register();
2366 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2367 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2368 }
2369 return Register();
2370}
2371
2372Register fastEmit_ISD_SREM_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2373 if (RetVT.SimpleTy != MVT::v2i64)
2374 return Register();
2375 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2376 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2377 }
2378 return Register();
2379}
2380
2381Register fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2382 switch (VT.SimpleTy) {
2383 case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op1);
2384 case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op1);
2385 case MVT::v16i8: return fastEmit_ISD_SREM_MVT_v16i8_rr(RetVT, Op0, Op1);
2386 case MVT::v8i16: return fastEmit_ISD_SREM_MVT_v8i16_rr(RetVT, Op0, Op1);
2387 case MVT::v4i32: return fastEmit_ISD_SREM_MVT_v4i32_rr(RetVT, Op0, Op1);
2388 case MVT::v2i64: return fastEmit_ISD_SREM_MVT_v2i64_rr(RetVT, Op0, Op1);
2389 default: return Register();
2390 }
2391}
2392
2393// FastEmit functions for ISD::SRL.
2394
2395Register fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2396 if (RetVT.SimpleTy != MVT::i32)
2397 return Register();
2398 if ((Subtarget->inMicroMipsMode())) {
2399 return fastEmitInst_rr(MachineInstOpcode: Mips::SRLV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2400 }
2401 if ((Subtarget->inMips16Mode())) {
2402 return fastEmitInst_rr(MachineInstOpcode: Mips::SrlvRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2403 }
2404 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2405 return fastEmitInst_rr(MachineInstOpcode: Mips::SRLV, RC: &Mips::GPR32RegClass, Op0, Op1);
2406 }
2407 return Register();
2408}
2409
2410Register fastEmit_ISD_SRL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2411 if (RetVT.SimpleTy != MVT::v16i8)
2412 return Register();
2413 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2414 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2415 }
2416 return Register();
2417}
2418
2419Register fastEmit_ISD_SRL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2420 if (RetVT.SimpleTy != MVT::v8i16)
2421 return Register();
2422 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2423 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2424 }
2425 return Register();
2426}
2427
2428Register fastEmit_ISD_SRL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2429 if (RetVT.SimpleTy != MVT::v4i32)
2430 return Register();
2431 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2432 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2433 }
2434 return Register();
2435}
2436
2437Register fastEmit_ISD_SRL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2438 if (RetVT.SimpleTy != MVT::v2i64)
2439 return Register();
2440 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2441 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2442 }
2443 return Register();
2444}
2445
2446Register fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2447 switch (VT.SimpleTy) {
2448 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op1);
2449 case MVT::v16i8: return fastEmit_ISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op1);
2450 case MVT::v8i16: return fastEmit_ISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op1);
2451 case MVT::v4i32: return fastEmit_ISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op1);
2452 case MVT::v2i64: return fastEmit_ISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op1);
2453 default: return Register();
2454 }
2455}
2456
2457// FastEmit functions for ISD::STRICT_FADD.
2458
2459Register fastEmit_ISD_STRICT_FADD_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
2460 if (RetVT.SimpleTy != MVT::f32)
2461 return Register();
2462 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2463 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_S, RC: &Mips::FGR32RegClass, Op0, Op1);
2464 }
2465 return Register();
2466}
2467
2468Register fastEmit_ISD_STRICT_FADD_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
2469 if (RetVT.SimpleTy != MVT::f64)
2470 return Register();
2471 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2472 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
2473 }
2474 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
2475 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
2476 }
2477 return Register();
2478}
2479
2480Register fastEmit_ISD_STRICT_FADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2481 switch (VT.SimpleTy) {
2482 case MVT::f32: return fastEmit_ISD_STRICT_FADD_MVT_f32_rr(RetVT, Op0, Op1);
2483 case MVT::f64: return fastEmit_ISD_STRICT_FADD_MVT_f64_rr(RetVT, Op0, Op1);
2484 default: return Register();
2485 }
2486}
2487
2488// FastEmit functions for ISD::STRICT_FDIV.
2489
2490Register fastEmit_ISD_STRICT_FDIV_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
2491 if (RetVT.SimpleTy != MVT::f32)
2492 return Register();
2493 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2494 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_S, RC: &Mips::FGR32RegClass, Op0, Op1);
2495 }
2496 return Register();
2497}
2498
2499Register fastEmit_ISD_STRICT_FDIV_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
2500 if (RetVT.SimpleTy != MVT::f64)
2501 return Register();
2502 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2503 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
2504 }
2505 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
2506 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
2507 }
2508 return Register();
2509}
2510
2511Register fastEmit_ISD_STRICT_FDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2512 switch (VT.SimpleTy) {
2513 case MVT::f32: return fastEmit_ISD_STRICT_FDIV_MVT_f32_rr(RetVT, Op0, Op1);
2514 case MVT::f64: return fastEmit_ISD_STRICT_FDIV_MVT_f64_rr(RetVT, Op0, Op1);
2515 default: return Register();
2516 }
2517}
2518
2519// FastEmit functions for ISD::STRICT_FMUL.
2520
2521Register fastEmit_ISD_STRICT_FMUL_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
2522 if (RetVT.SimpleTy != MVT::f32)
2523 return Register();
2524 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2525 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_S, RC: &Mips::FGR32RegClass, Op0, Op1);
2526 }
2527 return Register();
2528}
2529
2530Register fastEmit_ISD_STRICT_FMUL_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
2531 if (RetVT.SimpleTy != MVT::f64)
2532 return Register();
2533 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2534 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
2535 }
2536 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
2537 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
2538 }
2539 return Register();
2540}
2541
2542Register fastEmit_ISD_STRICT_FMUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2543 switch (VT.SimpleTy) {
2544 case MVT::f32: return fastEmit_ISD_STRICT_FMUL_MVT_f32_rr(RetVT, Op0, Op1);
2545 case MVT::f64: return fastEmit_ISD_STRICT_FMUL_MVT_f64_rr(RetVT, Op0, Op1);
2546 default: return Register();
2547 }
2548}
2549
2550// FastEmit functions for ISD::STRICT_FSUB.
2551
2552Register fastEmit_ISD_STRICT_FSUB_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
2553 if (RetVT.SimpleTy != MVT::f32)
2554 return Register();
2555 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2556 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_S, RC: &Mips::FGR32RegClass, Op0, Op1);
2557 }
2558 return Register();
2559}
2560
2561Register fastEmit_ISD_STRICT_FSUB_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
2562 if (RetVT.SimpleTy != MVT::f64)
2563 return Register();
2564 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2565 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
2566 }
2567 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
2568 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
2569 }
2570 return Register();
2571}
2572
2573Register fastEmit_ISD_STRICT_FSUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2574 switch (VT.SimpleTy) {
2575 case MVT::f32: return fastEmit_ISD_STRICT_FSUB_MVT_f32_rr(RetVT, Op0, Op1);
2576 case MVT::f64: return fastEmit_ISD_STRICT_FSUB_MVT_f64_rr(RetVT, Op0, Op1);
2577 default: return Register();
2578 }
2579}
2580
2581// FastEmit functions for ISD::SUB.
2582
2583Register fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2584 if (RetVT.SimpleTy != MVT::i32)
2585 return Register();
2586 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2587 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBU16_MMR6, RC: &Mips::GPRMM16RegClass, Op0, Op1);
2588 }
2589 if ((Subtarget->inMips16Mode())) {
2590 return fastEmitInst_rr(MachineInstOpcode: Mips::SubuRxRyRz16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2591 }
2592 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
2593 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2594 }
2595 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2596 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu, RC: &Mips::GPR32RegClass, Op0, Op1);
2597 }
2598 return Register();
2599}
2600
2601Register fastEmit_ISD_SUB_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2602 if (RetVT.SimpleTy != MVT::i64)
2603 return Register();
2604 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2605 return fastEmitInst_rr(MachineInstOpcode: Mips::DSUBu, RC: &Mips::GPR64RegClass, Op0, Op1);
2606 }
2607 return Register();
2608}
2609
2610Register fastEmit_ISD_SUB_MVT_v4i8_rr(MVT RetVT, Register Op0, Register Op1) {
2611 if (RetVT.SimpleTy != MVT::v4i8)
2612 return Register();
2613 if ((Subtarget->hasDSP())) {
2614 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBU_QB, RC: &Mips::DSPRRegClass, Op0, Op1);
2615 }
2616 return Register();
2617}
2618
2619Register fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2620 if (RetVT.SimpleTy != MVT::v16i8)
2621 return Register();
2622 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2623 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2624 }
2625 return Register();
2626}
2627
2628Register fastEmit_ISD_SUB_MVT_v2i16_rr(MVT RetVT, Register Op0, Register Op1) {
2629 if (RetVT.SimpleTy != MVT::v2i16)
2630 return Register();
2631 if ((Subtarget->hasDSP())) {
2632 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBQ_PH, RC: &Mips::DSPRRegClass, Op0, Op1);
2633 }
2634 return Register();
2635}
2636
2637Register fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2638 if (RetVT.SimpleTy != MVT::v8i16)
2639 return Register();
2640 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2641 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2642 }
2643 return Register();
2644}
2645
2646Register fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2647 if (RetVT.SimpleTy != MVT::v4i32)
2648 return Register();
2649 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2650 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2651 }
2652 return Register();
2653}
2654
2655Register fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2656 if (RetVT.SimpleTy != MVT::v2i64)
2657 return Register();
2658 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2659 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2660 }
2661 return Register();
2662}
2663
2664Register fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2665 switch (VT.SimpleTy) {
2666 case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op1);
2667 case MVT::i64: return fastEmit_ISD_SUB_MVT_i64_rr(RetVT, Op0, Op1);
2668 case MVT::v4i8: return fastEmit_ISD_SUB_MVT_v4i8_rr(RetVT, Op0, Op1);
2669 case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op1);
2670 case MVT::v2i16: return fastEmit_ISD_SUB_MVT_v2i16_rr(RetVT, Op0, Op1);
2671 case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op1);
2672 case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op1);
2673 case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op1);
2674 default: return Register();
2675 }
2676}
2677
2678// FastEmit functions for ISD::SUBC.
2679
2680Register fastEmit_ISD_SUBC_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2681 if (RetVT.SimpleTy != MVT::i32)
2682 return Register();
2683 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2684 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2685 }
2686 if ((Subtarget->inMicroMipsMode())) {
2687 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2688 }
2689 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2690 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu, RC: &Mips::GPR32RegClass, Op0, Op1);
2691 }
2692 return Register();
2693}
2694
2695Register fastEmit_ISD_SUBC_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2696 if (RetVT.SimpleTy != MVT::i64)
2697 return Register();
2698 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())) {
2699 return fastEmitInst_rr(MachineInstOpcode: Mips::DSUBu, RC: &Mips::GPR64RegClass, Op0, Op1);
2700 }
2701 return Register();
2702}
2703
2704Register fastEmit_ISD_SUBC_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2705 switch (VT.SimpleTy) {
2706 case MVT::i32: return fastEmit_ISD_SUBC_MVT_i32_rr(RetVT, Op0, Op1);
2707 case MVT::i64: return fastEmit_ISD_SUBC_MVT_i64_rr(RetVT, Op0, Op1);
2708 default: return Register();
2709 }
2710}
2711
2712// FastEmit functions for ISD::UDIV.
2713
2714Register fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2715 if (RetVT.SimpleTy != MVT::i32)
2716 return Register();
2717 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2718 return fastEmitInst_rr(MachineInstOpcode: Mips::DIVU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2719 }
2720 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2721 return fastEmitInst_rr(MachineInstOpcode: Mips::DIVU, RC: &Mips::GPR32RegClass, Op0, Op1);
2722 }
2723 return Register();
2724}
2725
2726Register fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2727 if (RetVT.SimpleTy != MVT::i64)
2728 return Register();
2729 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2730 return fastEmitInst_rr(MachineInstOpcode: Mips::DDIVU, RC: &Mips::GPR64RegClass, Op0, Op1);
2731 }
2732 return Register();
2733}
2734
2735Register fastEmit_ISD_UDIV_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2736 if (RetVT.SimpleTy != MVT::v16i8)
2737 return Register();
2738 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2739 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2740 }
2741 return Register();
2742}
2743
2744Register fastEmit_ISD_UDIV_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2745 if (RetVT.SimpleTy != MVT::v8i16)
2746 return Register();
2747 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2748 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2749 }
2750 return Register();
2751}
2752
2753Register fastEmit_ISD_UDIV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2754 if (RetVT.SimpleTy != MVT::v4i32)
2755 return Register();
2756 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2757 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2758 }
2759 return Register();
2760}
2761
2762Register fastEmit_ISD_UDIV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2763 if (RetVT.SimpleTy != MVT::v2i64)
2764 return Register();
2765 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2766 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2767 }
2768 return Register();
2769}
2770
2771Register fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2772 switch (VT.SimpleTy) {
2773 case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op1);
2774 case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op1);
2775 case MVT::v16i8: return fastEmit_ISD_UDIV_MVT_v16i8_rr(RetVT, Op0, Op1);
2776 case MVT::v8i16: return fastEmit_ISD_UDIV_MVT_v8i16_rr(RetVT, Op0, Op1);
2777 case MVT::v4i32: return fastEmit_ISD_UDIV_MVT_v4i32_rr(RetVT, Op0, Op1);
2778 case MVT::v2i64: return fastEmit_ISD_UDIV_MVT_v2i64_rr(RetVT, Op0, Op1);
2779 default: return Register();
2780 }
2781}
2782
2783// FastEmit functions for ISD::UMAX.
2784
2785Register fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2786 if (RetVT.SimpleTy != MVT::v16i8)
2787 return Register();
2788 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2789 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2790 }
2791 return Register();
2792}
2793
2794Register fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2795 if (RetVT.SimpleTy != MVT::v8i16)
2796 return Register();
2797 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2798 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2799 }
2800 return Register();
2801}
2802
2803Register fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2804 if (RetVT.SimpleTy != MVT::v4i32)
2805 return Register();
2806 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2807 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2808 }
2809 return Register();
2810}
2811
2812Register fastEmit_ISD_UMAX_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2813 if (RetVT.SimpleTy != MVT::v2i64)
2814 return Register();
2815 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2816 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2817 }
2818 return Register();
2819}
2820
2821Register fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2822 switch (VT.SimpleTy) {
2823 case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
2824 case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
2825 case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
2826 case MVT::v2i64: return fastEmit_ISD_UMAX_MVT_v2i64_rr(RetVT, Op0, Op1);
2827 default: return Register();
2828 }
2829}
2830
2831// FastEmit functions for ISD::UMIN.
2832
2833Register fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2834 if (RetVT.SimpleTy != MVT::v16i8)
2835 return Register();
2836 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2837 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2838 }
2839 return Register();
2840}
2841
2842Register fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2843 if (RetVT.SimpleTy != MVT::v8i16)
2844 return Register();
2845 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2846 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2847 }
2848 return Register();
2849}
2850
2851Register fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2852 if (RetVT.SimpleTy != MVT::v4i32)
2853 return Register();
2854 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2855 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2856 }
2857 return Register();
2858}
2859
2860Register fastEmit_ISD_UMIN_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2861 if (RetVT.SimpleTy != MVT::v2i64)
2862 return Register();
2863 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2864 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2865 }
2866 return Register();
2867}
2868
2869Register fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2870 switch (VT.SimpleTy) {
2871 case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
2872 case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
2873 case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
2874 case MVT::v2i64: return fastEmit_ISD_UMIN_MVT_v2i64_rr(RetVT, Op0, Op1);
2875 default: return Register();
2876 }
2877}
2878
2879// FastEmit functions for ISD::UREM.
2880
2881Register fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2882 if (RetVT.SimpleTy != MVT::i32)
2883 return Register();
2884 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2885 return fastEmitInst_rr(MachineInstOpcode: Mips::MODU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2886 }
2887 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2888 return fastEmitInst_rr(MachineInstOpcode: Mips::MODU, RC: &Mips::GPR32RegClass, Op0, Op1);
2889 }
2890 return Register();
2891}
2892
2893Register fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2894 if (RetVT.SimpleTy != MVT::i64)
2895 return Register();
2896 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2897 return fastEmitInst_rr(MachineInstOpcode: Mips::DMODU, RC: &Mips::GPR64RegClass, Op0, Op1);
2898 }
2899 return Register();
2900}
2901
2902Register fastEmit_ISD_UREM_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2903 if (RetVT.SimpleTy != MVT::v16i8)
2904 return Register();
2905 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2906 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2907 }
2908 return Register();
2909}
2910
2911Register fastEmit_ISD_UREM_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2912 if (RetVT.SimpleTy != MVT::v8i16)
2913 return Register();
2914 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2915 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2916 }
2917 return Register();
2918}
2919
2920Register fastEmit_ISD_UREM_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2921 if (RetVT.SimpleTy != MVT::v4i32)
2922 return Register();
2923 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2924 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2925 }
2926 return Register();
2927}
2928
2929Register fastEmit_ISD_UREM_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2930 if (RetVT.SimpleTy != MVT::v2i64)
2931 return Register();
2932 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2933 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2934 }
2935 return Register();
2936}
2937
2938Register fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2939 switch (VT.SimpleTy) {
2940 case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op1);
2941 case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op1);
2942 case MVT::v16i8: return fastEmit_ISD_UREM_MVT_v16i8_rr(RetVT, Op0, Op1);
2943 case MVT::v8i16: return fastEmit_ISD_UREM_MVT_v8i16_rr(RetVT, Op0, Op1);
2944 case MVT::v4i32: return fastEmit_ISD_UREM_MVT_v4i32_rr(RetVT, Op0, Op1);
2945 case MVT::v2i64: return fastEmit_ISD_UREM_MVT_v2i64_rr(RetVT, Op0, Op1);
2946 default: return Register();
2947 }
2948}
2949
2950// FastEmit functions for ISD::XOR.
2951
2952Register fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2953 if (RetVT.SimpleTy != MVT::i32)
2954 return Register();
2955 if ((Subtarget->inMips16Mode())) {
2956 return fastEmitInst_rr(MachineInstOpcode: Mips::XorRxRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2957 }
2958 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2959 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2960 }
2961 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
2962 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2963 }
2964 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2965 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR, RC: &Mips::GPR32RegClass, Op0, Op1);
2966 }
2967 return Register();
2968}
2969
2970Register fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2971 if (RetVT.SimpleTy != MVT::i64)
2972 return Register();
2973 if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
2974 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR64, RC: &Mips::GPR64RegClass, Op0, Op1);
2975 }
2976 return Register();
2977}
2978
2979Register fastEmit_ISD_XOR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2980 if (RetVT.SimpleTy != MVT::v16i8)
2981 return Register();
2982 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2983 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
2984 }
2985 return Register();
2986}
2987
2988Register fastEmit_ISD_XOR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2989 if (RetVT.SimpleTy != MVT::v8i16)
2990 return Register();
2991 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2992 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
2993 }
2994 return Register();
2995}
2996
2997Register fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2998 if (RetVT.SimpleTy != MVT::v4i32)
2999 return Register();
3000 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3001 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
3002 }
3003 return Register();
3004}
3005
3006Register fastEmit_ISD_XOR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3007 if (RetVT.SimpleTy != MVT::v2i64)
3008 return Register();
3009 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3010 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
3011 }
3012 return Register();
3013}
3014
3015Register fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3016 switch (VT.SimpleTy) {
3017 case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op1);
3018 case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op1);
3019 case MVT::v16i8: return fastEmit_ISD_XOR_MVT_v16i8_rr(RetVT, Op0, Op1);
3020 case MVT::v8i16: return fastEmit_ISD_XOR_MVT_v8i16_rr(RetVT, Op0, Op1);
3021 case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op1);
3022 case MVT::v2i64: return fastEmit_ISD_XOR_MVT_v2i64_rr(RetVT, Op0, Op1);
3023 default: return Register();
3024 }
3025}
3026
3027// FastEmit functions for MipsISD::BuildPairF64.
3028
3029Register fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3030 if (RetVT.SimpleTy != MVT::f64)
3031 return Register();
3032 if ((Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMips16Mode())) {
3033 return fastEmitInst_rr(MachineInstOpcode: Mips::BuildPairF64_64, RC: &Mips::FGR64RegClass, Op0, Op1);
3034 }
3035 if ((!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode())) {
3036 return fastEmitInst_rr(MachineInstOpcode: Mips::BuildPairF64, RC: &Mips::AFGR64RegClass, Op0, Op1);
3037 }
3038 return Register();
3039}
3040
3041Register fastEmit_MipsISD_BuildPairF64_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3042 switch (VT.SimpleTy) {
3043 case MVT::i32: return fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(RetVT, Op0, Op1);
3044 default: return Register();
3045 }
3046}
3047
3048// FastEmit functions for MipsISD::BuildPairF64_FPR.
3049
3050Register fastEmit_MipsISD_BuildPairF64_FPR_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
3051 if (RetVT.SimpleTy != MVT::f64)
3052 return Register();
3053 if ((!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode())) {
3054 return fastEmitInst_rr(MachineInstOpcode: Mips::BuildPairF64_FPR, RC: &Mips::AFGR64RegClass, Op0, Op1);
3055 }
3056 return Register();
3057}
3058
3059Register fastEmit_MipsISD_BuildPairF64_FPR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3060 switch (VT.SimpleTy) {
3061 case MVT::f32: return fastEmit_MipsISD_BuildPairF64_FPR_MVT_f32_rr(RetVT, Op0, Op1);
3062 default: return Register();
3063 }
3064}
3065
3066// FastEmit functions for MipsISD::DivRem.
3067
3068Register fastEmit_MipsISD_DivRem_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3069 if (RetVT.SimpleTy != MVT::Untyped)
3070 return Register();
3071 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3072 return fastEmitInst_rr(MachineInstOpcode: Mips::SDIV_MM_Pseudo, RC: &Mips::ACC64RegClass, Op0, Op1);
3073 }
3074 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3075 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoSDIV, RC: &Mips::ACC64RegClass, Op0, Op1);
3076 }
3077 return Register();
3078}
3079
3080Register fastEmit_MipsISD_DivRem_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3081 if (RetVT.SimpleTy != MVT::Untyped)
3082 return Register();
3083 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (!Subtarget->isR5900())) {
3084 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDSDIV, RC: &Mips::ACC128RegClass, Op0, Op1);
3085 }
3086 return Register();
3087}
3088
3089Register fastEmit_MipsISD_DivRem_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3090 switch (VT.SimpleTy) {
3091 case MVT::i32: return fastEmit_MipsISD_DivRem_MVT_i32_rr(RetVT, Op0, Op1);
3092 case MVT::i64: return fastEmit_MipsISD_DivRem_MVT_i64_rr(RetVT, Op0, Op1);
3093 default: return Register();
3094 }
3095}
3096
3097// FastEmit functions for MipsISD::DivRemU.
3098
3099Register fastEmit_MipsISD_DivRemU_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3100 if (RetVT.SimpleTy != MVT::Untyped)
3101 return Register();
3102 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3103 return fastEmitInst_rr(MachineInstOpcode: Mips::UDIV_MM_Pseudo, RC: &Mips::ACC64RegClass, Op0, Op1);
3104 }
3105 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3106 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoUDIV, RC: &Mips::ACC64RegClass, Op0, Op1);
3107 }
3108 return Register();
3109}
3110
3111Register fastEmit_MipsISD_DivRemU_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3112 if (RetVT.SimpleTy != MVT::Untyped)
3113 return Register();
3114 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (!Subtarget->isR5900())) {
3115 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDUDIV, RC: &Mips::ACC128RegClass, Op0, Op1);
3116 }
3117 return Register();
3118}
3119
3120Register fastEmit_MipsISD_DivRemU_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3121 switch (VT.SimpleTy) {
3122 case MVT::i32: return fastEmit_MipsISD_DivRemU_MVT_i32_rr(RetVT, Op0, Op1);
3123 case MVT::i64: return fastEmit_MipsISD_DivRemU_MVT_i64_rr(RetVT, Op0, Op1);
3124 default: return Register();
3125 }
3126}
3127
3128// FastEmit functions for MipsISD::ILVEV.
3129
3130Register fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3131 if (RetVT.SimpleTy != MVT::v16i8)
3132 return Register();
3133 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3134 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3135 }
3136 return Register();
3137}
3138
3139Register fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3140 if (RetVT.SimpleTy != MVT::v8i16)
3141 return Register();
3142 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3143 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3144 }
3145 return Register();
3146}
3147
3148Register fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3149 if (RetVT.SimpleTy != MVT::v4i32)
3150 return Register();
3151 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3152 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3153 }
3154 return Register();
3155}
3156
3157Register fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3158 if (RetVT.SimpleTy != MVT::v2i64)
3159 return Register();
3160 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3161 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3162 }
3163 return Register();
3164}
3165
3166Register fastEmit_MipsISD_ILVEV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3167 switch (VT.SimpleTy) {
3168 case MVT::v16i8: return fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(RetVT, Op0, Op1);
3169 case MVT::v8i16: return fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(RetVT, Op0, Op1);
3170 case MVT::v4i32: return fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(RetVT, Op0, Op1);
3171 case MVT::v2i64: return fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(RetVT, Op0, Op1);
3172 default: return Register();
3173 }
3174}
3175
3176// FastEmit functions for MipsISD::ILVL.
3177
3178Register fastEmit_MipsISD_ILVL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3179 if (RetVT.SimpleTy != MVT::v16i8)
3180 return Register();
3181 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3182 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3183 }
3184 return Register();
3185}
3186
3187Register fastEmit_MipsISD_ILVL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3188 if (RetVT.SimpleTy != MVT::v8i16)
3189 return Register();
3190 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3191 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3192 }
3193 return Register();
3194}
3195
3196Register fastEmit_MipsISD_ILVL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3197 if (RetVT.SimpleTy != MVT::v4i32)
3198 return Register();
3199 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3200 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3201 }
3202 return Register();
3203}
3204
3205Register fastEmit_MipsISD_ILVL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3206 if (RetVT.SimpleTy != MVT::v2i64)
3207 return Register();
3208 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3209 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3210 }
3211 return Register();
3212}
3213
3214Register fastEmit_MipsISD_ILVL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3215 switch (VT.SimpleTy) {
3216 case MVT::v16i8: return fastEmit_MipsISD_ILVL_MVT_v16i8_rr(RetVT, Op0, Op1);
3217 case MVT::v8i16: return fastEmit_MipsISD_ILVL_MVT_v8i16_rr(RetVT, Op0, Op1);
3218 case MVT::v4i32: return fastEmit_MipsISD_ILVL_MVT_v4i32_rr(RetVT, Op0, Op1);
3219 case MVT::v2i64: return fastEmit_MipsISD_ILVL_MVT_v2i64_rr(RetVT, Op0, Op1);
3220 default: return Register();
3221 }
3222}
3223
3224// FastEmit functions for MipsISD::ILVOD.
3225
3226Register fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3227 if (RetVT.SimpleTy != MVT::v16i8)
3228 return Register();
3229 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3230 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3231 }
3232 return Register();
3233}
3234
3235Register fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3236 if (RetVT.SimpleTy != MVT::v8i16)
3237 return Register();
3238 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3239 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3240 }
3241 return Register();
3242}
3243
3244Register fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3245 if (RetVT.SimpleTy != MVT::v4i32)
3246 return Register();
3247 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3248 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3249 }
3250 return Register();
3251}
3252
3253Register fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3254 if (RetVT.SimpleTy != MVT::v2i64)
3255 return Register();
3256 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3257 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3258 }
3259 return Register();
3260}
3261
3262Register fastEmit_MipsISD_ILVOD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3263 switch (VT.SimpleTy) {
3264 case MVT::v16i8: return fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(RetVT, Op0, Op1);
3265 case MVT::v8i16: return fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(RetVT, Op0, Op1);
3266 case MVT::v4i32: return fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(RetVT, Op0, Op1);
3267 case MVT::v2i64: return fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(RetVT, Op0, Op1);
3268 default: return Register();
3269 }
3270}
3271
3272// FastEmit functions for MipsISD::ILVR.
3273
3274Register fastEmit_MipsISD_ILVR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3275 if (RetVT.SimpleTy != MVT::v16i8)
3276 return Register();
3277 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3278 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3279 }
3280 return Register();
3281}
3282
3283Register fastEmit_MipsISD_ILVR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3284 if (RetVT.SimpleTy != MVT::v8i16)
3285 return Register();
3286 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3287 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3288 }
3289 return Register();
3290}
3291
3292Register fastEmit_MipsISD_ILVR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3293 if (RetVT.SimpleTy != MVT::v4i32)
3294 return Register();
3295 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3296 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3297 }
3298 return Register();
3299}
3300
3301Register fastEmit_MipsISD_ILVR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3302 if (RetVT.SimpleTy != MVT::v2i64)
3303 return Register();
3304 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3305 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3306 }
3307 return Register();
3308}
3309
3310Register fastEmit_MipsISD_ILVR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3311 switch (VT.SimpleTy) {
3312 case MVT::v16i8: return fastEmit_MipsISD_ILVR_MVT_v16i8_rr(RetVT, Op0, Op1);
3313 case MVT::v8i16: return fastEmit_MipsISD_ILVR_MVT_v8i16_rr(RetVT, Op0, Op1);
3314 case MVT::v4i32: return fastEmit_MipsISD_ILVR_MVT_v4i32_rr(RetVT, Op0, Op1);
3315 case MVT::v2i64: return fastEmit_MipsISD_ILVR_MVT_v2i64_rr(RetVT, Op0, Op1);
3316 default: return Register();
3317 }
3318}
3319
3320// FastEmit functions for MipsISD::MTLOHI.
3321
3322Register fastEmit_MipsISD_MTLOHI_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3323 if (RetVT.SimpleTy != MVT::Untyped)
3324 return Register();
3325 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
3326 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI_MM, RC: &Mips::ACC64RegClass, Op0, Op1);
3327 }
3328 if ((Subtarget->hasDSP()) && (!Subtarget->inMips16Mode())) {
3329 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI_DSP, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3330 }
3331 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3332 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI, RC: &Mips::ACC64RegClass, Op0, Op1);
3333 }
3334 return Register();
3335}
3336
3337Register fastEmit_MipsISD_MTLOHI_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3338 if (RetVT.SimpleTy != MVT::Untyped)
3339 return Register();
3340 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3341 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI64, RC: &Mips::ACC128RegClass, Op0, Op1);
3342 }
3343 return Register();
3344}
3345
3346Register fastEmit_MipsISD_MTLOHI_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3347 switch (VT.SimpleTy) {
3348 case MVT::i32: return fastEmit_MipsISD_MTLOHI_MVT_i32_rr(RetVT, Op0, Op1);
3349 case MVT::i64: return fastEmit_MipsISD_MTLOHI_MVT_i64_rr(RetVT, Op0, Op1);
3350 default: return Register();
3351 }
3352}
3353
3354// FastEmit functions for MipsISD::Mult.
3355
3356Register fastEmit_MipsISD_Mult_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3357 if (RetVT.SimpleTy != MVT::Untyped)
3358 return Register();
3359 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
3360 return fastEmitInst_rr(MachineInstOpcode: Mips::MULT_DSP_MM, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3361 }
3362 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
3363 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULT_MM, RC: &Mips::ACC64RegClass, Op0, Op1);
3364 }
3365 if ((Subtarget->hasDSP())) {
3366 return fastEmitInst_rr(MachineInstOpcode: Mips::MULT_DSP, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3367 }
3368 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3369 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULT, RC: &Mips::ACC64RegClass, Op0, Op1);
3370 }
3371 return Register();
3372}
3373
3374Register fastEmit_MipsISD_Mult_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3375 if (RetVT.SimpleTy != MVT::Untyped)
3376 return Register();
3377 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (!Subtarget->isR5900())) {
3378 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDMULT, RC: &Mips::ACC128RegClass, Op0, Op1);
3379 }
3380 return Register();
3381}
3382
3383Register fastEmit_MipsISD_Mult_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3384 switch (VT.SimpleTy) {
3385 case MVT::i32: return fastEmit_MipsISD_Mult_MVT_i32_rr(RetVT, Op0, Op1);
3386 case MVT::i64: return fastEmit_MipsISD_Mult_MVT_i64_rr(RetVT, Op0, Op1);
3387 default: return Register();
3388 }
3389}
3390
3391// FastEmit functions for MipsISD::Multu.
3392
3393Register fastEmit_MipsISD_Multu_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3394 if (RetVT.SimpleTy != MVT::Untyped)
3395 return Register();
3396 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
3397 return fastEmitInst_rr(MachineInstOpcode: Mips::MULTU_DSP_MM, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3398 }
3399 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
3400 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULTu_MM, RC: &Mips::ACC64RegClass, Op0, Op1);
3401 }
3402 if ((Subtarget->hasDSP())) {
3403 return fastEmitInst_rr(MachineInstOpcode: Mips::MULTU_DSP, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3404 }
3405 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3406 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULTu, RC: &Mips::ACC64RegClass, Op0, Op1);
3407 }
3408 return Register();
3409}
3410
3411Register fastEmit_MipsISD_Multu_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3412 if (RetVT.SimpleTy != MVT::Untyped)
3413 return Register();
3414 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (!Subtarget->isR5900())) {
3415 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDMULTu, RC: &Mips::ACC128RegClass, Op0, Op1);
3416 }
3417 return Register();
3418}
3419
3420Register fastEmit_MipsISD_Multu_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3421 switch (VT.SimpleTy) {
3422 case MVT::i32: return fastEmit_MipsISD_Multu_MVT_i32_rr(RetVT, Op0, Op1);
3423 case MVT::i64: return fastEmit_MipsISD_Multu_MVT_i64_rr(RetVT, Op0, Op1);
3424 default: return Register();
3425 }
3426}
3427
3428// FastEmit functions for MipsISD::PCKEV.
3429
3430Register fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3431 if (RetVT.SimpleTy != MVT::v16i8)
3432 return Register();
3433 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3434 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3435 }
3436 return Register();
3437}
3438
3439Register fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3440 if (RetVT.SimpleTy != MVT::v8i16)
3441 return Register();
3442 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3443 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3444 }
3445 return Register();
3446}
3447
3448Register fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3449 if (RetVT.SimpleTy != MVT::v4i32)
3450 return Register();
3451 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3452 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3453 }
3454 return Register();
3455}
3456
3457Register fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3458 if (RetVT.SimpleTy != MVT::v2i64)
3459 return Register();
3460 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3461 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3462 }
3463 return Register();
3464}
3465
3466Register fastEmit_MipsISD_PCKEV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3467 switch (VT.SimpleTy) {
3468 case MVT::v16i8: return fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(RetVT, Op0, Op1);
3469 case MVT::v8i16: return fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(RetVT, Op0, Op1);
3470 case MVT::v4i32: return fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(RetVT, Op0, Op1);
3471 case MVT::v2i64: return fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(RetVT, Op0, Op1);
3472 default: return Register();
3473 }
3474}
3475
3476// FastEmit functions for MipsISD::PCKOD.
3477
3478Register fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3479 if (RetVT.SimpleTy != MVT::v16i8)
3480 return Register();
3481 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3482 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3483 }
3484 return Register();
3485}
3486
3487Register fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3488 if (RetVT.SimpleTy != MVT::v8i16)
3489 return Register();
3490 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3491 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3492 }
3493 return Register();
3494}
3495
3496Register fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3497 if (RetVT.SimpleTy != MVT::v4i32)
3498 return Register();
3499 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3500 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3501 }
3502 return Register();
3503}
3504
3505Register fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3506 if (RetVT.SimpleTy != MVT::v2i64)
3507 return Register();
3508 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3509 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3510 }
3511 return Register();
3512}
3513
3514Register fastEmit_MipsISD_PCKOD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3515 switch (VT.SimpleTy) {
3516 case MVT::v16i8: return fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(RetVT, Op0, Op1);
3517 case MVT::v8i16: return fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(RetVT, Op0, Op1);
3518 case MVT::v4i32: return fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(RetVT, Op0, Op1);
3519 case MVT::v2i64: return fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(RetVT, Op0, Op1);
3520 default: return Register();
3521 }
3522}
3523
3524// FastEmit functions for MipsISD::VNOR.
3525
3526Register fastEmit_MipsISD_VNOR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3527 if (RetVT.SimpleTy != MVT::v16i8)
3528 return Register();
3529 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3530 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
3531 }
3532 return Register();
3533}
3534
3535Register fastEmit_MipsISD_VNOR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3536 if (RetVT.SimpleTy != MVT::v8i16)
3537 return Register();
3538 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3539 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
3540 }
3541 return Register();
3542}
3543
3544Register fastEmit_MipsISD_VNOR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3545 if (RetVT.SimpleTy != MVT::v4i32)
3546 return Register();
3547 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3548 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
3549 }
3550 return Register();
3551}
3552
3553Register fastEmit_MipsISD_VNOR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3554 if (RetVT.SimpleTy != MVT::v2i64)
3555 return Register();
3556 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3557 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
3558 }
3559 return Register();
3560}
3561
3562Register fastEmit_MipsISD_VNOR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3563 switch (VT.SimpleTy) {
3564 case MVT::v16i8: return fastEmit_MipsISD_VNOR_MVT_v16i8_rr(RetVT, Op0, Op1);
3565 case MVT::v8i16: return fastEmit_MipsISD_VNOR_MVT_v8i16_rr(RetVT, Op0, Op1);
3566 case MVT::v4i32: return fastEmit_MipsISD_VNOR_MVT_v4i32_rr(RetVT, Op0, Op1);
3567 case MVT::v2i64: return fastEmit_MipsISD_VNOR_MVT_v2i64_rr(RetVT, Op0, Op1);
3568 default: return Register();
3569 }
3570}
3571
3572// Top-level FastEmit function.
3573
3574Register fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, Register Op1) override {
3575 switch (Opcode) {
3576 case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op1);
3577 case ISD::ADDC: return fastEmit_ISD_ADDC_rr(VT, RetVT, Op0, Op1);
3578 case ISD::ADDE: return fastEmit_ISD_ADDE_rr(VT, RetVT, Op0, Op1);
3579 case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op1);
3580 case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op1);
3581 case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op1);
3582 case ISD::FMAXNUM: return fastEmit_ISD_FMAXNUM_rr(VT, RetVT, Op0, Op1);
3583 case ISD::FMAXNUM_IEEE: return fastEmit_ISD_FMAXNUM_IEEE_rr(VT, RetVT, Op0, Op1);
3584 case ISD::FMINNUM: return fastEmit_ISD_FMINNUM_rr(VT, RetVT, Op0, Op1);
3585 case ISD::FMINNUM_IEEE: return fastEmit_ISD_FMINNUM_IEEE_rr(VT, RetVT, Op0, Op1);
3586 case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op1);
3587 case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op1);
3588 case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op1);
3589 case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op1);
3590 case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op1);
3591 case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op1);
3592 case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op1);
3593 case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op1);
3594 case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op1);
3595 case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op1);
3596 case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op1);
3597 case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op1);
3598 case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op1);
3599 case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op1);
3600 case ISD::STRICT_FADD: return fastEmit_ISD_STRICT_FADD_rr(VT, RetVT, Op0, Op1);
3601 case ISD::STRICT_FDIV: return fastEmit_ISD_STRICT_FDIV_rr(VT, RetVT, Op0, Op1);
3602 case ISD::STRICT_FMUL: return fastEmit_ISD_STRICT_FMUL_rr(VT, RetVT, Op0, Op1);
3603 case ISD::STRICT_FSUB: return fastEmit_ISD_STRICT_FSUB_rr(VT, RetVT, Op0, Op1);
3604 case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op1);
3605 case ISD::SUBC: return fastEmit_ISD_SUBC_rr(VT, RetVT, Op0, Op1);
3606 case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op1);
3607 case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op1);
3608 case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op1);
3609 case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op1);
3610 case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op1);
3611 case MipsISD::BuildPairF64: return fastEmit_MipsISD_BuildPairF64_rr(VT, RetVT, Op0, Op1);
3612 case MipsISD::BuildPairF64_FPR: return fastEmit_MipsISD_BuildPairF64_FPR_rr(VT, RetVT, Op0, Op1);
3613 case MipsISD::DivRem: return fastEmit_MipsISD_DivRem_rr(VT, RetVT, Op0, Op1);
3614 case MipsISD::DivRemU: return fastEmit_MipsISD_DivRemU_rr(VT, RetVT, Op0, Op1);
3615 case MipsISD::ILVEV: return fastEmit_MipsISD_ILVEV_rr(VT, RetVT, Op0, Op1);
3616 case MipsISD::ILVL: return fastEmit_MipsISD_ILVL_rr(VT, RetVT, Op0, Op1);
3617 case MipsISD::ILVOD: return fastEmit_MipsISD_ILVOD_rr(VT, RetVT, Op0, Op1);
3618 case MipsISD::ILVR: return fastEmit_MipsISD_ILVR_rr(VT, RetVT, Op0, Op1);
3619 case MipsISD::MTLOHI: return fastEmit_MipsISD_MTLOHI_rr(VT, RetVT, Op0, Op1);
3620 case MipsISD::Mult: return fastEmit_MipsISD_Mult_rr(VT, RetVT, Op0, Op1);
3621 case MipsISD::Multu: return fastEmit_MipsISD_Multu_rr(VT, RetVT, Op0, Op1);
3622 case MipsISD::PCKEV: return fastEmit_MipsISD_PCKEV_rr(VT, RetVT, Op0, Op1);
3623 case MipsISD::PCKOD: return fastEmit_MipsISD_PCKOD_rr(VT, RetVT, Op0, Op1);
3624 case MipsISD::VNOR: return fastEmit_MipsISD_VNOR_rr(VT, RetVT, Op0, Op1);
3625 default: return Register();
3626 }
3627}
3628
3629// FastEmit functions for MipsISD::ExtractElementF64.
3630
3631Register fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3632 if (RetVT.SimpleTy != MVT::i32)
3633 return Register();
3634 if ((Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMips16Mode())) {
3635 return fastEmitInst_ri(MachineInstOpcode: Mips::ExtractElementF64_64, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3636 }
3637 if ((!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode())) {
3638 return fastEmitInst_ri(MachineInstOpcode: Mips::ExtractElementF64, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3639 }
3640 return Register();
3641}
3642
3643Register fastEmit_MipsISD_ExtractElementF64_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3644 switch (VT.SimpleTy) {
3645 case MVT::f64: return fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(RetVT, Op0, imm1);
3646 default: return Register();
3647 }
3648}
3649
3650// FastEmit functions for MipsISD::SHLL_DSP.
3651
3652Register fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3653 if (RetVT.SimpleTy != MVT::v4i8)
3654 return Register();
3655 if ((Subtarget->hasDSP())) {
3656 return fastEmitInst_ri(MachineInstOpcode: Mips::SHLL_QB, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3657 }
3658 return Register();
3659}
3660
3661Register fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3662 if (RetVT.SimpleTy != MVT::v2i16)
3663 return Register();
3664 if ((Subtarget->hasDSP())) {
3665 return fastEmitInst_ri(MachineInstOpcode: Mips::SHLL_PH, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3666 }
3667 return Register();
3668}
3669
3670Register fastEmit_MipsISD_SHLL_DSP_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3671 switch (VT.SimpleTy) {
3672 case MVT::v4i8: return fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(RetVT, Op0, imm1);
3673 case MVT::v2i16: return fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(RetVT, Op0, imm1);
3674 default: return Register();
3675 }
3676}
3677
3678// FastEmit functions for MipsISD::SHRA_DSP.
3679
3680Register fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3681 if (RetVT.SimpleTy != MVT::v4i8)
3682 return Register();
3683 if ((Subtarget->hasDSPR2())) {
3684 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRA_QB, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3685 }
3686 return Register();
3687}
3688
3689Register fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3690 if (RetVT.SimpleTy != MVT::v2i16)
3691 return Register();
3692 if ((Subtarget->hasDSP())) {
3693 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRA_PH, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3694 }
3695 return Register();
3696}
3697
3698Register fastEmit_MipsISD_SHRA_DSP_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3699 switch (VT.SimpleTy) {
3700 case MVT::v4i8: return fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(RetVT, Op0, imm1);
3701 case MVT::v2i16: return fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(RetVT, Op0, imm1);
3702 default: return Register();
3703 }
3704}
3705
3706// FastEmit functions for MipsISD::SHRL_DSP.
3707
3708Register fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3709 if (RetVT.SimpleTy != MVT::v4i8)
3710 return Register();
3711 if ((Subtarget->hasDSP())) {
3712 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRL_QB, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3713 }
3714 return Register();
3715}
3716
3717Register fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3718 if (RetVT.SimpleTy != MVT::v2i16)
3719 return Register();
3720 if ((Subtarget->hasDSPR2())) {
3721 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRL_PH, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3722 }
3723 return Register();
3724}
3725
3726Register fastEmit_MipsISD_SHRL_DSP_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3727 switch (VT.SimpleTy) {
3728 case MVT::v4i8: return fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(RetVT, Op0, imm1);
3729 case MVT::v2i16: return fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(RetVT, Op0, imm1);
3730 default: return Register();
3731 }
3732}
3733
3734// Top-level FastEmit function.
3735
3736Register fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) override {
3737 if (VT == MVT::i32 && Predicate_immZExt5(Imm: imm1))
3738 if (Register Reg = fastEmit_ri_Predicate_immZExt5(VT, RetVT, Opcode, Op0, imm1))
3739 return Reg;
3740
3741 if (VT == MVT::i32 && Predicate_immZExt6(Imm: imm1))
3742 if (Register Reg = fastEmit_ri_Predicate_immZExt6(VT, RetVT, Opcode, Op0, imm1))
3743 return Reg;
3744
3745 if (VT == MVT::iPTR && Predicate_immZExt2Ptr(Imm: imm1))
3746 if (Register Reg = fastEmit_ri_Predicate_immZExt2Ptr(VT, RetVT, Opcode, Op0, imm1))
3747 return Reg;
3748
3749 if (VT == MVT::iPTR && Predicate_immZExt1Ptr(Imm: imm1))
3750 if (Register Reg = fastEmit_ri_Predicate_immZExt1Ptr(VT, RetVT, Opcode, Op0, imm1))
3751 return Reg;
3752
3753 if (VT == MVT::i32 && Predicate_immZExt4(Imm: imm1))
3754 if (Register Reg = fastEmit_ri_Predicate_immZExt4(VT, RetVT, Opcode, Op0, imm1))
3755 return Reg;
3756
3757 if (VT == MVT::i32 && Predicate_immSExtAddiur2(Imm: imm1))
3758 if (Register Reg = fastEmit_ri_Predicate_immSExtAddiur2(VT, RetVT, Opcode, Op0, imm1))
3759 return Reg;
3760
3761 if (VT == MVT::i32 && Predicate_immSExtAddius5(Imm: imm1))
3762 if (Register Reg = fastEmit_ri_Predicate_immSExtAddius5(VT, RetVT, Opcode, Op0, imm1))
3763 return Reg;
3764
3765 if (VT == MVT::i32 && Predicate_immZExtAndi16(Imm: imm1))
3766 if (Register Reg = fastEmit_ri_Predicate_immZExtAndi16(VT, RetVT, Opcode, Op0, imm1))
3767 return Reg;
3768
3769 if (VT == MVT::i32 && Predicate_immZExt2Shift(Imm: imm1))
3770 if (Register Reg = fastEmit_ri_Predicate_immZExt2Shift(VT, RetVT, Opcode, Op0, imm1))
3771 return Reg;
3772
3773 switch (Opcode) {
3774 case MipsISD::ExtractElementF64: return fastEmit_MipsISD_ExtractElementF64_ri(VT, RetVT, Op0, imm1);
3775 case MipsISD::SHLL_DSP: return fastEmit_MipsISD_SHLL_DSP_ri(VT, RetVT, Op0, imm1);
3776 case MipsISD::SHRA_DSP: return fastEmit_MipsISD_SHRA_DSP_ri(VT, RetVT, Op0, imm1);
3777 case MipsISD::SHRL_DSP: return fastEmit_MipsISD_SHRL_DSP_ri(VT, RetVT, Op0, imm1);
3778 default: return Register();
3779 }
3780}
3781
3782// FastEmit functions for ISD::ROTR.
3783
3784Register fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, Register Op0, uint64_t imm1) {
3785 if (RetVT.SimpleTy != MVT::i32)
3786 return Register();
3787 if ((Subtarget->inMicroMipsMode())) {
3788 return fastEmitInst_ri(MachineInstOpcode: Mips::ROTR_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3789 }
3790 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3791 return fastEmitInst_ri(MachineInstOpcode: Mips::ROTR, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3792 }
3793 return Register();
3794}
3795
3796Register fastEmit_ISD_ROTR_ri_Predicate_immZExt5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3797 switch (VT.SimpleTy) {
3798 case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
3799 default: return Register();
3800 }
3801}
3802
3803// FastEmit functions for ISD::SHL.
3804
3805Register fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, Register Op0, uint64_t imm1) {
3806 if (RetVT.SimpleTy != MVT::i32)
3807 return Register();
3808 if ((Subtarget->inMicroMipsMode())) {
3809 return fastEmitInst_ri(MachineInstOpcode: Mips::SLL_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3810 }
3811 if ((Subtarget->inMips16Mode())) {
3812 return fastEmitInst_ri(MachineInstOpcode: Mips::SllX16, RC: &Mips::CPU16RegsRegClass, Op0, Imm: imm1);
3813 }
3814 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3815 return fastEmitInst_ri(MachineInstOpcode: Mips::SLL, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3816 }
3817 return Register();
3818}
3819
3820Register fastEmit_ISD_SHL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3821 switch (VT.SimpleTy) {
3822 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
3823 default: return Register();
3824 }
3825}
3826
3827// FastEmit functions for ISD::SRA.
3828
3829Register fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, Register Op0, uint64_t imm1) {
3830 if (RetVT.SimpleTy != MVT::i32)
3831 return Register();
3832 if ((Subtarget->inMicroMipsMode())) {
3833 return fastEmitInst_ri(MachineInstOpcode: Mips::SRA_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3834 }
3835 if ((Subtarget->inMips16Mode())) {
3836 return fastEmitInst_ri(MachineInstOpcode: Mips::SraX16, RC: &Mips::CPU16RegsRegClass, Op0, Imm: imm1);
3837 }
3838 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3839 return fastEmitInst_ri(MachineInstOpcode: Mips::SRA, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3840 }
3841 return Register();
3842}
3843
3844Register fastEmit_ISD_SRA_ri_Predicate_immZExt5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3845 switch (VT.SimpleTy) {
3846 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
3847 default: return Register();
3848 }
3849}
3850
3851// FastEmit functions for ISD::SRL.
3852
3853Register fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, Register Op0, uint64_t imm1) {
3854 if (RetVT.SimpleTy != MVT::i32)
3855 return Register();
3856 if ((Subtarget->inMicroMipsMode())) {
3857 return fastEmitInst_ri(MachineInstOpcode: Mips::SRL_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3858 }
3859 if ((Subtarget->inMips16Mode())) {
3860 return fastEmitInst_ri(MachineInstOpcode: Mips::SrlX16, RC: &Mips::CPU16RegsRegClass, Op0, Imm: imm1);
3861 }
3862 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3863 return fastEmitInst_ri(MachineInstOpcode: Mips::SRL, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3864 }
3865 return Register();
3866}
3867
3868Register fastEmit_ISD_SRL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3869 switch (VT.SimpleTy) {
3870 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
3871 default: return Register();
3872 }
3873}
3874
3875// Top-level FastEmit function.
3876
3877Register fastEmit_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
3878 switch (Opcode) {
3879 case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
3880 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
3881 case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
3882 case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
3883 default: return Register();
3884 }
3885}
3886
3887// FastEmit functions for ISD::ROTR.
3888
3889Register fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, Register Op0, uint64_t imm1) {
3890 if (RetVT.SimpleTy != MVT::i64)
3891 return Register();
3892 if ((Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3893 return fastEmitInst_ri(MachineInstOpcode: Mips::DROTR, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
3894 }
3895 return Register();
3896}
3897
3898Register fastEmit_ISD_ROTR_ri_Predicate_immZExt6(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3899 switch (VT.SimpleTy) {
3900 case MVT::i64: return fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
3901 default: return Register();
3902 }
3903}
3904
3905// FastEmit functions for ISD::SHL.
3906
3907Register fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, Register Op0, uint64_t imm1) {
3908 if (RetVT.SimpleTy != MVT::i64)
3909 return Register();
3910 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3911 return fastEmitInst_ri(MachineInstOpcode: Mips::DSLL, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
3912 }
3913 return Register();
3914}
3915
3916Register fastEmit_ISD_SHL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3917 switch (VT.SimpleTy) {
3918 case MVT::i64: return fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
3919 default: return Register();
3920 }
3921}
3922
3923// FastEmit functions for ISD::SRA.
3924
3925Register fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, Register Op0, uint64_t imm1) {
3926 if (RetVT.SimpleTy != MVT::i64)
3927 return Register();
3928 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3929 return fastEmitInst_ri(MachineInstOpcode: Mips::DSRA, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
3930 }
3931 return Register();
3932}
3933
3934Register fastEmit_ISD_SRA_ri_Predicate_immZExt6(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3935 switch (VT.SimpleTy) {
3936 case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
3937 default: return Register();
3938 }
3939}
3940
3941// FastEmit functions for ISD::SRL.
3942
3943Register fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, Register Op0, uint64_t imm1) {
3944 if (RetVT.SimpleTy != MVT::i64)
3945 return Register();
3946 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3947 return fastEmitInst_ri(MachineInstOpcode: Mips::DSRL, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
3948 }
3949 return Register();
3950}
3951
3952Register fastEmit_ISD_SRL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3953 switch (VT.SimpleTy) {
3954 case MVT::i64: return fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
3955 default: return Register();
3956 }
3957}
3958
3959// Top-level FastEmit function.
3960
3961Register fastEmit_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
3962 switch (Opcode) {
3963 case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
3964 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
3965 case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
3966 case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
3967 default: return Register();
3968 }
3969}
3970
3971// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
3972
3973Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(MVT RetVT, Register Op0, uint64_t imm1) {
3974 if (RetVT.SimpleTy != MVT::f32)
3975 return Register();
3976 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3977 return fastEmitInst_ri(MachineInstOpcode: Mips::COPY_FW_PSEUDO, RC: &Mips::FGR32RegClass, Op0, Imm: imm1);
3978 }
3979 return Register();
3980}
3981
3982Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3983 switch (VT.SimpleTy) {
3984 case MVT::v4f32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(RetVT, Op0, imm1);
3985 default: return Register();
3986 }
3987}
3988
3989// Top-level FastEmit function.
3990
3991Register fastEmit_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
3992 switch (Opcode) {
3993 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(VT, RetVT, Op0, imm1);
3994 default: return Register();
3995 }
3996}
3997
3998// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
3999
4000Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(MVT RetVT, Register Op0, uint64_t imm1) {
4001 if (RetVT.SimpleTy != MVT::f64)
4002 return Register();
4003 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
4004 return fastEmitInst_ri(MachineInstOpcode: Mips::COPY_FD_PSEUDO, RC: &Mips::FGR64RegClass, Op0, Imm: imm1);
4005 }
4006 return Register();
4007}
4008
4009Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4010 switch (VT.SimpleTy) {
4011 case MVT::v2f64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(RetVT, Op0, imm1);
4012 default: return Register();
4013 }
4014}
4015
4016// Top-level FastEmit function.
4017
4018Register fastEmit_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4019 switch (Opcode) {
4020 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(VT, RetVT, Op0, imm1);
4021 default: return Register();
4022 }
4023}
4024
4025// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
4026
4027Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(MVT RetVT, Register Op0, uint64_t imm1) {
4028 if (RetVT.SimpleTy != MVT::i32)
4029 return Register();
4030 if ((Subtarget->hasMSA())) {
4031 return fastEmitInst_ri(MachineInstOpcode: Mips::COPY_S_W, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
4032 }
4033 return Register();
4034}
4035
4036Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4037 switch (VT.SimpleTy) {
4038 case MVT::v4i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(RetVT, Op0, imm1);
4039 default: return Register();
4040 }
4041}
4042
4043// Top-level FastEmit function.
4044
4045Register fastEmit_ri_Predicate_immZExt4(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4046 switch (Opcode) {
4047 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(VT, RetVT, Op0, imm1);
4048 default: return Register();
4049 }
4050}
4051
4052// FastEmit functions for ISD::ADD.
4053
4054Register fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(MVT RetVT, Register Op0, uint64_t imm1) {
4055 if (RetVT.SimpleTy != MVT::i32)
4056 return Register();
4057 if ((Subtarget->inMicroMipsMode())) {
4058 return fastEmitInst_ri(MachineInstOpcode: Mips::ADDIUR2_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4059 }
4060 return Register();
4061}
4062
4063Register fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4064 switch (VT.SimpleTy) {
4065 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(RetVT, Op0, imm1);
4066 default: return Register();
4067 }
4068}
4069
4070// Top-level FastEmit function.
4071
4072Register fastEmit_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4073 switch (Opcode) {
4074 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(VT, RetVT, Op0, imm1);
4075 default: return Register();
4076 }
4077}
4078
4079// FastEmit functions for ISD::ADD.
4080
4081Register fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(MVT RetVT, Register Op0, uint64_t imm1) {
4082 if (RetVT.SimpleTy != MVT::i32)
4083 return Register();
4084 if ((Subtarget->inMicroMipsMode())) {
4085 return fastEmitInst_ri(MachineInstOpcode: Mips::ADDIUS5_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
4086 }
4087 return Register();
4088}
4089
4090Register fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4091 switch (VT.SimpleTy) {
4092 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(RetVT, Op0, imm1);
4093 default: return Register();
4094 }
4095}
4096
4097// Top-level FastEmit function.
4098
4099Register fastEmit_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4100 switch (Opcode) {
4101 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(VT, RetVT, Op0, imm1);
4102 default: return Register();
4103 }
4104}
4105
4106// FastEmit functions for ISD::AND.
4107
4108Register fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(MVT RetVT, Register Op0, uint64_t imm1) {
4109 if (RetVT.SimpleTy != MVT::i32)
4110 return Register();
4111 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
4112 return fastEmitInst_ri(MachineInstOpcode: Mips::ANDI16_MMR6, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4113 }
4114 if ((Subtarget->inMicroMipsMode())) {
4115 return fastEmitInst_ri(MachineInstOpcode: Mips::ANDI16_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4116 }
4117 return Register();
4118}
4119
4120Register fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4121 switch (VT.SimpleTy) {
4122 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(RetVT, Op0, imm1);
4123 default: return Register();
4124 }
4125}
4126
4127// Top-level FastEmit function.
4128
4129Register fastEmit_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4130 switch (Opcode) {
4131 case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(VT, RetVT, Op0, imm1);
4132 default: return Register();
4133 }
4134}
4135
4136// FastEmit functions for ISD::SHL.
4137
4138Register fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, Register Op0, uint64_t imm1) {
4139 if (RetVT.SimpleTy != MVT::i32)
4140 return Register();
4141 if ((Subtarget->inMicroMipsMode())) {
4142 return fastEmitInst_ri(MachineInstOpcode: Mips::SLL16_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4143 }
4144 return Register();
4145}
4146
4147Register fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4148 switch (VT.SimpleTy) {
4149 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, imm1);
4150 default: return Register();
4151 }
4152}
4153
4154// FastEmit functions for ISD::SRL.
4155
4156Register fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, Register Op0, uint64_t imm1) {
4157 if (RetVT.SimpleTy != MVT::i32)
4158 return Register();
4159 if ((Subtarget->inMicroMipsMode())) {
4160 return fastEmitInst_ri(MachineInstOpcode: Mips::SRL16_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4161 }
4162 return Register();
4163}
4164
4165Register fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4166 switch (VT.SimpleTy) {
4167 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, imm1);
4168 default: return Register();
4169 }
4170}
4171
4172// Top-level FastEmit function.
4173
4174Register fastEmit_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4175 switch (Opcode) {
4176 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, imm1);
4177 case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, imm1);
4178 default: return Register();
4179 }
4180}
4181
4182// FastEmit functions for ISD::Constant.
4183
4184Register fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) {
4185 if (RetVT.SimpleTy != MVT::i32)
4186 return Register();
4187 if ((Subtarget->inMips16Mode())) {
4188 return fastEmitInst_i(MachineInstOpcode: Mips::LwConstant32, RC: &Mips::CPU16RegsRegClass, Imm: imm0);
4189 }
4190 return Register();
4191}
4192
4193Register fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) {
4194 switch (VT.SimpleTy) {
4195 case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0);
4196 default: return Register();
4197 }
4198}
4199
4200// Top-level FastEmit function.
4201
4202Register fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override {
4203 switch (Opcode) {
4204 case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0);
4205 default: return Register();
4206 }
4207}
4208
4209