1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* "Fast" Instruction Selector for the Mips target *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10// FastEmit Immediate Predicate functions.
11static bool Predicate_immZExt5(int64_t Imm) {
12return Imm == (Imm & 0x1f);
13}
14static bool Predicate_immZExt6(int64_t Imm) {
15return Imm == (Imm & 0x3f);
16}
17static bool Predicate_immSExt6(int64_t Imm) {
18return isInt<6>(x: Imm);
19}
20static bool Predicate_immZExt4Ptr(int64_t Imm) {
21return isUInt<4>(x: Imm);
22}
23static bool Predicate_immZExt3Ptr(int64_t Imm) {
24return isUInt<3>(x: Imm);
25}
26static bool Predicate_immZExt2Ptr(int64_t Imm) {
27return isUInt<2>(x: Imm);
28}
29static bool Predicate_immZExt1Ptr(int64_t Imm) {
30return isUInt<1>(x: Imm);
31}
32static bool Predicate_immZExt4(int64_t Imm) {
33return isUInt<4>(x: Imm);
34}
35static bool Predicate_immSExtAddiur2(int64_t Imm) {
36return Imm == 1 || Imm == -1 ||
37 ((Imm % 4 == 0) &&
38 Imm < 28 && Imm > 0);
39}
40static bool Predicate_immSExtAddius5(int64_t Imm) {
41return Imm >= -8 && Imm <= 7;
42}
43static bool Predicate_immZExtAndi16(int64_t Imm) {
44return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
45 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
46 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
47}
48static bool Predicate_immZExt2Shift(int64_t Imm) {
49return Imm >= 1 && Imm <= 8;
50}
51
52
53// FastEmit functions for ISD::BITCAST.
54
55Register fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, Register Op0) {
56 if (RetVT.SimpleTy != MVT::f32)
57 return Register();
58 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
59 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_MMR6, RC: &Mips::FGR32RegClass, Op0);
60 }
61 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
62 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_MM, RC: &Mips::FGR32RegClass, Op0);
63 }
64 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
65 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1, RC: &Mips::FGR32RegClass, Op0);
66 }
67 return Register();
68}
69
70Register fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, Register Op0) {
71 if (RetVT.SimpleTy != MVT::f64)
72 return Register();
73 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
74 return fastEmitInst_r(MachineInstOpcode: Mips::DMTC1, RC: &Mips::FGR64RegClass, Op0);
75 }
76 return Register();
77}
78
79Register fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, Register Op0) {
80 if (RetVT.SimpleTy != MVT::i32)
81 return Register();
82 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
83 return fastEmitInst_r(MachineInstOpcode: Mips::MFC1_MMR6, RC: &Mips::GPR32RegClass, Op0);
84 }
85 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
86 return fastEmitInst_r(MachineInstOpcode: Mips::MFC1_MM, RC: &Mips::GPR32RegClass, Op0);
87 }
88 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
89 return fastEmitInst_r(MachineInstOpcode: Mips::MFC1, RC: &Mips::GPR32RegClass, Op0);
90 }
91 return Register();
92}
93
94Register fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, Register Op0) {
95 if (RetVT.SimpleTy != MVT::i64)
96 return Register();
97 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
98 return fastEmitInst_r(MachineInstOpcode: Mips::DMFC1, RC: &Mips::GPR64RegClass, Op0);
99 }
100 return Register();
101}
102
103Register fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, Register Op0) {
104 switch (VT.SimpleTy) {
105 case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0);
106 case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0);
107 case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0);
108 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0);
109 default: return Register();
110 }
111}
112
113// FastEmit functions for ISD::BRIND.
114
115Register fastEmit_ISD_BRIND_MVT_i32_r(MVT RetVT, Register Op0) {
116 if (RetVT.SimpleTy != MVT::isVoid)
117 return Register();
118 if ((Subtarget->inMips16Mode())) {
119 return fastEmitInst_r(MachineInstOpcode: Mips::JrcRx16, RC: &Mips::CPU16RegsRegClass, Op0);
120 }
121 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
122 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranch_MMR6, RC: &Mips::GPR32RegClass, Op0);
123 }
124 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
125 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranch_MM, RC: &Mips::GPR32RegClass, Op0);
126 }
127 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
128 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndrectHazardBranchR6, RC: &Mips::GPR32RegClass, Op0);
129 }
130 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
131 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranchR6, RC: &Mips::GPR32RegClass, Op0);
132 }
133 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
134 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectHazardBranch, RC: &Mips::GPR32RegClass, Op0);
135 }
136 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
137 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranch, RC: &Mips::GPR32RegClass, Op0);
138 }
139 return Register();
140}
141
142Register fastEmit_ISD_BRIND_MVT_i64_r(MVT RetVT, Register Op0) {
143 if (RetVT.SimpleTy != MVT::isVoid)
144 return Register();
145 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
146 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndrectHazardBranch64R6, RC: &Mips::GPR64RegClass, Op0);
147 }
148 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
149 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranch64R6, RC: &Mips::GPR64RegClass, Op0);
150 }
151 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
152 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectHazardBranch64, RC: &Mips::GPR64RegClass, Op0);
153 }
154 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
155 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranch64, RC: &Mips::GPR64RegClass, Op0);
156 }
157 return Register();
158}
159
160Register fastEmit_ISD_BRIND_r(MVT VT, MVT RetVT, Register Op0) {
161 switch (VT.SimpleTy) {
162 case MVT::i32: return fastEmit_ISD_BRIND_MVT_i32_r(RetVT, Op0);
163 case MVT::i64: return fastEmit_ISD_BRIND_MVT_i64_r(RetVT, Op0);
164 default: return Register();
165 }
166}
167
168// FastEmit functions for ISD::CTLZ.
169
170Register fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, Register Op0) {
171 if (RetVT.SimpleTy != MVT::i32)
172 return Register();
173 if ((Subtarget->inMicroMipsMode())) {
174 return fastEmitInst_r(MachineInstOpcode: Mips::CLZ_MM, RC: &Mips::GPR32RegClass, Op0);
175 }
176 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding())) {
177 return fastEmitInst_r(MachineInstOpcode: Mips::CLZ_R6, RC: &Mips::GPR32RegClass, Op0);
178 }
179 if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
180 return fastEmitInst_r(MachineInstOpcode: Mips::CLZ, RC: &Mips::GPR32RegClass, Op0);
181 }
182 return Register();
183}
184
185Register fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, Register Op0) {
186 if (RetVT.SimpleTy != MVT::i64)
187 return Register();
188 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
189 return fastEmitInst_r(MachineInstOpcode: Mips::DCLZ_R6, RC: &Mips::GPR64RegClass, Op0);
190 }
191 if ((Subtarget->hasMips64()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips64r6())) {
192 return fastEmitInst_r(MachineInstOpcode: Mips::DCLZ, RC: &Mips::GPR64RegClass, Op0);
193 }
194 return Register();
195}
196
197Register fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, Register Op0) {
198 if (RetVT.SimpleTy != MVT::v16i8)
199 return Register();
200 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
201 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_B, RC: &Mips::MSA128BRegClass, Op0);
202 }
203 return Register();
204}
205
206Register fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, Register Op0) {
207 if (RetVT.SimpleTy != MVT::v8i16)
208 return Register();
209 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
210 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_H, RC: &Mips::MSA128HRegClass, Op0);
211 }
212 return Register();
213}
214
215Register fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, Register Op0) {
216 if (RetVT.SimpleTy != MVT::v4i32)
217 return Register();
218 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
219 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_W, RC: &Mips::MSA128WRegClass, Op0);
220 }
221 return Register();
222}
223
224Register fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, Register Op0) {
225 if (RetVT.SimpleTy != MVT::v2i64)
226 return Register();
227 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
228 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_D, RC: &Mips::MSA128DRegClass, Op0);
229 }
230 return Register();
231}
232
233Register fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, Register Op0) {
234 switch (VT.SimpleTy) {
235 case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0);
236 case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0);
237 case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0);
238 case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0);
239 case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0);
240 case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0);
241 default: return Register();
242 }
243}
244
245// FastEmit functions for ISD::CTPOP.
246
247Register fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, Register Op0) {
248 if (RetVT.SimpleTy != MVT::i32)
249 return Register();
250 if ((Subtarget->hasCnMips())) {
251 return fastEmitInst_r(MachineInstOpcode: Mips::POP, RC: &Mips::GPR32RegClass, Op0);
252 }
253 return Register();
254}
255
256Register fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, Register Op0) {
257 if (RetVT.SimpleTy != MVT::i64)
258 return Register();
259 if ((Subtarget->hasCnMips())) {
260 return fastEmitInst_r(MachineInstOpcode: Mips::DPOP, RC: &Mips::GPR64RegClass, Op0);
261 }
262 return Register();
263}
264
265Register fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, Register Op0) {
266 if (RetVT.SimpleTy != MVT::v16i8)
267 return Register();
268 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
269 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_B, RC: &Mips::MSA128BRegClass, Op0);
270 }
271 return Register();
272}
273
274Register fastEmit_ISD_CTPOP_MVT_v8i16_r(MVT RetVT, Register Op0) {
275 if (RetVT.SimpleTy != MVT::v8i16)
276 return Register();
277 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
278 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_H, RC: &Mips::MSA128HRegClass, Op0);
279 }
280 return Register();
281}
282
283Register fastEmit_ISD_CTPOP_MVT_v4i32_r(MVT RetVT, Register Op0) {
284 if (RetVT.SimpleTy != MVT::v4i32)
285 return Register();
286 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
287 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_W, RC: &Mips::MSA128WRegClass, Op0);
288 }
289 return Register();
290}
291
292Register fastEmit_ISD_CTPOP_MVT_v2i64_r(MVT RetVT, Register Op0) {
293 if (RetVT.SimpleTy != MVT::v2i64)
294 return Register();
295 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
296 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_D, RC: &Mips::MSA128DRegClass, Op0);
297 }
298 return Register();
299}
300
301Register fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, Register Op0) {
302 switch (VT.SimpleTy) {
303 case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0);
304 case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0);
305 case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0);
306 case MVT::v8i16: return fastEmit_ISD_CTPOP_MVT_v8i16_r(RetVT, Op0);
307 case MVT::v4i32: return fastEmit_ISD_CTPOP_MVT_v4i32_r(RetVT, Op0);
308 case MVT::v2i64: return fastEmit_ISD_CTPOP_MVT_v2i64_r(RetVT, Op0);
309 default: return Register();
310 }
311}
312
313// FastEmit functions for ISD::FABS.
314
315Register fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, Register Op0) {
316 if (RetVT.SimpleTy != MVT::f64)
317 return Register();
318 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
319 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D64_MM, RC: &Mips::FGR64RegClass, Op0);
320 }
321 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
322 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D32_MM, RC: &Mips::AFGR64RegClass, Op0);
323 }
324 return Register();
325}
326
327Register fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, Register Op0) {
328 if (RetVT.SimpleTy != MVT::v4f32)
329 return Register();
330 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
331 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_W, RC: &Mips::MSA128WRegClass, Op0);
332 }
333 return Register();
334}
335
336Register fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, Register Op0) {
337 if (RetVT.SimpleTy != MVT::v2f64)
338 return Register();
339 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
340 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D, RC: &Mips::MSA128DRegClass, Op0);
341 }
342 return Register();
343}
344
345Register fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, Register Op0) {
346 switch (VT.SimpleTy) {
347 case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0);
348 case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0);
349 case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0);
350 default: return Register();
351 }
352}
353
354// FastEmit functions for ISD::FEXP2.
355
356Register fastEmit_ISD_FEXP2_MVT_v4f32_r(MVT RetVT, Register Op0) {
357 if (RetVT.SimpleTy != MVT::v4f32)
358 return Register();
359 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
360 return fastEmitInst_r(MachineInstOpcode: Mips::FEXP2_W_1_PSEUDO, RC: &Mips::MSA128WRegClass, Op0);
361 }
362 return Register();
363}
364
365Register fastEmit_ISD_FEXP2_MVT_v2f64_r(MVT RetVT, Register Op0) {
366 if (RetVT.SimpleTy != MVT::v2f64)
367 return Register();
368 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
369 return fastEmitInst_r(MachineInstOpcode: Mips::FEXP2_D_1_PSEUDO, RC: &Mips::MSA128DRegClass, Op0);
370 }
371 return Register();
372}
373
374Register fastEmit_ISD_FEXP2_r(MVT VT, MVT RetVT, Register Op0) {
375 switch (VT.SimpleTy) {
376 case MVT::v4f32: return fastEmit_ISD_FEXP2_MVT_v4f32_r(RetVT, Op0);
377 case MVT::v2f64: return fastEmit_ISD_FEXP2_MVT_v2f64_r(RetVT, Op0);
378 default: return Register();
379 }
380}
381
382// FastEmit functions for ISD::FLOG2.
383
384Register fastEmit_ISD_FLOG2_MVT_v4f32_r(MVT RetVT, Register Op0) {
385 if (RetVT.SimpleTy != MVT::v4f32)
386 return Register();
387 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
388 return fastEmitInst_r(MachineInstOpcode: Mips::FLOG2_W, RC: &Mips::MSA128WRegClass, Op0);
389 }
390 return Register();
391}
392
393Register fastEmit_ISD_FLOG2_MVT_v2f64_r(MVT RetVT, Register Op0) {
394 if (RetVT.SimpleTy != MVT::v2f64)
395 return Register();
396 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
397 return fastEmitInst_r(MachineInstOpcode: Mips::FLOG2_D, RC: &Mips::MSA128DRegClass, Op0);
398 }
399 return Register();
400}
401
402Register fastEmit_ISD_FLOG2_r(MVT VT, MVT RetVT, Register Op0) {
403 switch (VT.SimpleTy) {
404 case MVT::v4f32: return fastEmit_ISD_FLOG2_MVT_v4f32_r(RetVT, Op0);
405 case MVT::v2f64: return fastEmit_ISD_FLOG2_MVT_v2f64_r(RetVT, Op0);
406 default: return Register();
407 }
408}
409
410// FastEmit functions for ISD::FNEG.
411
412Register fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, Register Op0) {
413 if (RetVT.SimpleTy != MVT::f32)
414 return Register();
415 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
416 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_S_MMR6, RC: &Mips::FGR32RegClass, Op0);
417 }
418 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
419 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_S_MM, RC: &Mips::FGR32RegClass, Op0);
420 }
421 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
422 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_S, RC: &Mips::FGR32RegClass, Op0);
423 }
424 return Register();
425}
426
427Register fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, Register Op0) {
428 if (RetVT.SimpleTy != MVT::f64)
429 return Register();
430 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
431 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D64_MM, RC: &Mips::FGR64RegClass, Op0);
432 }
433 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
434 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D32_MM, RC: &Mips::AFGR64RegClass, Op0);
435 }
436 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
437 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D64, RC: &Mips::FGR64RegClass, Op0);
438 }
439 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
440 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D32, RC: &Mips::AFGR64RegClass, Op0);
441 }
442 return Register();
443}
444
445Register fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, Register Op0) {
446 switch (VT.SimpleTy) {
447 case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0);
448 case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0);
449 default: return Register();
450 }
451}
452
453// FastEmit functions for ISD::FP_EXTEND.
454
455Register fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(Register Op0) {
456 if ((Subtarget->hasMSA())) {
457 return fastEmitInst_r(MachineInstOpcode: Mips::MSA_FP_EXTEND_W_PSEUDO, RC: &Mips::FGR32RegClass, Op0);
458 }
459 return Register();
460}
461
462Register fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(Register Op0) {
463 if ((Subtarget->hasMSA())) {
464 return fastEmitInst_r(MachineInstOpcode: Mips::MSA_FP_EXTEND_D_PSEUDO, RC: &Mips::FGR64RegClass, Op0);
465 }
466 return Register();
467}
468
469Register fastEmit_ISD_FP_EXTEND_MVT_f16_r(MVT RetVT, Register Op0) {
470switch (RetVT.SimpleTy) {
471 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(Op0);
472 case MVT::f64: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(Op0);
473 default: return Register();
474}
475}
476
477Register fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, Register Op0) {
478 if (RetVT.SimpleTy != MVT::f64)
479 return Register();
480 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit())) {
481 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D32_S_MM, RC: &Mips::AFGR64RegClass, Op0);
482 }
483 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())) {
484 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D64_S_MM, RC: &Mips::FGR64RegClass, Op0);
485 }
486 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
487 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D64_S, RC: &Mips::FGR64RegClass, Op0);
488 }
489 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
490 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D32_S, RC: &Mips::AFGR64RegClass, Op0);
491 }
492 return Register();
493}
494
495Register fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
496 switch (VT.SimpleTy) {
497 case MVT::f16: return fastEmit_ISD_FP_EXTEND_MVT_f16_r(RetVT, Op0);
498 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0);
499 default: return Register();
500 }
501}
502
503// FastEmit functions for ISD::FP_ROUND.
504
505Register fastEmit_ISD_FP_ROUND_MVT_f32_r(MVT RetVT, Register Op0) {
506 if (RetVT.SimpleTy != MVT::f16)
507 return Register();
508 if ((Subtarget->hasMSA())) {
509 return fastEmitInst_r(MachineInstOpcode: Mips::MSA_FP_ROUND_W_PSEUDO, RC: &Mips::MSA128F16RegClass, Op0);
510 }
511 return Register();
512}
513
514Register fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(Register Op0) {
515 if ((Subtarget->hasMSA())) {
516 return fastEmitInst_r(MachineInstOpcode: Mips::MSA_FP_ROUND_D_PSEUDO, RC: &Mips::MSA128F16RegClass, Op0);
517 }
518 return Register();
519}
520
521Register fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(Register Op0) {
522 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit())) {
523 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D32_MM, RC: &Mips::FGR32RegClass, Op0);
524 }
525 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())) {
526 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D64_MM, RC: &Mips::FGR32RegClass, Op0);
527 }
528 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
529 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D64, RC: &Mips::FGR32RegClass, Op0);
530 }
531 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
532 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D32, RC: &Mips::FGR32RegClass, Op0);
533 }
534 return Register();
535}
536
537Register fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, Register Op0) {
538switch (RetVT.SimpleTy) {
539 case MVT::f16: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(Op0);
540 case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(Op0);
541 default: return Register();
542}
543}
544
545Register fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, Register Op0) {
546 switch (VT.SimpleTy) {
547 case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f32_r(RetVT, Op0);
548 case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0);
549 default: return Register();
550 }
551}
552
553// FastEmit functions for ISD::FP_TO_SINT.
554
555Register fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
556 if (RetVT.SimpleTy != MVT::v4i32)
557 return Register();
558 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
559 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_S_W, RC: &Mips::MSA128WRegClass, Op0);
560 }
561 return Register();
562}
563
564Register fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
565 if (RetVT.SimpleTy != MVT::v2i64)
566 return Register();
567 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
568 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_S_D, RC: &Mips::MSA128DRegClass, Op0);
569 }
570 return Register();
571}
572
573Register fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, Register Op0) {
574 switch (VT.SimpleTy) {
575 case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0);
576 case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0);
577 default: return Register();
578 }
579}
580
581// FastEmit functions for ISD::FP_TO_UINT.
582
583Register fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
584 if (RetVT.SimpleTy != MVT::v4i32)
585 return Register();
586 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
587 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_U_W, RC: &Mips::MSA128WRegClass, Op0);
588 }
589 return Register();
590}
591
592Register fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
593 if (RetVT.SimpleTy != MVT::v2i64)
594 return Register();
595 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
596 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_U_D, RC: &Mips::MSA128DRegClass, Op0);
597 }
598 return Register();
599}
600
601Register fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, Register Op0) {
602 switch (VT.SimpleTy) {
603 case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0);
604 case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0);
605 default: return Register();
606 }
607}
608
609// FastEmit functions for ISD::FRINT.
610
611Register fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
612 if (RetVT.SimpleTy != MVT::v4f32)
613 return Register();
614 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
615 return fastEmitInst_r(MachineInstOpcode: Mips::FRINT_W, RC: &Mips::MSA128WRegClass, Op0);
616 }
617 return Register();
618}
619
620Register fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
621 if (RetVT.SimpleTy != MVT::v2f64)
622 return Register();
623 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
624 return fastEmitInst_r(MachineInstOpcode: Mips::FRINT_D, RC: &Mips::MSA128DRegClass, Op0);
625 }
626 return Register();
627}
628
629Register fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, Register Op0) {
630 switch (VT.SimpleTy) {
631 case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0);
632 case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0);
633 default: return Register();
634 }
635}
636
637// FastEmit functions for ISD::FSQRT.
638
639Register fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, Register Op0) {
640 if (RetVT.SimpleTy != MVT::f32)
641 return Register();
642 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
643 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_S_MM, RC: &Mips::FGR32RegClass, Op0);
644 }
645 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
646 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_S, RC: &Mips::FGR32RegClass, Op0);
647 }
648 return Register();
649}
650
651Register fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, Register Op0) {
652 if (RetVT.SimpleTy != MVT::f64)
653 return Register();
654 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
655 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D64_MM, RC: &Mips::FGR64RegClass, Op0);
656 }
657 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
658 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D32_MM, RC: &Mips::AFGR64RegClass, Op0);
659 }
660 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
661 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D64, RC: &Mips::FGR64RegClass, Op0);
662 }
663 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
664 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D32, RC: &Mips::AFGR64RegClass, Op0);
665 }
666 return Register();
667}
668
669Register fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, Register Op0) {
670 if (RetVT.SimpleTy != MVT::v4f32)
671 return Register();
672 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
673 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_W, RC: &Mips::MSA128WRegClass, Op0);
674 }
675 return Register();
676}
677
678Register fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, Register Op0) {
679 if (RetVT.SimpleTy != MVT::v2f64)
680 return Register();
681 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
682 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D, RC: &Mips::MSA128DRegClass, Op0);
683 }
684 return Register();
685}
686
687Register fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, Register Op0) {
688 switch (VT.SimpleTy) {
689 case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0);
690 case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0);
691 case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0);
692 case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0);
693 default: return Register();
694 }
695}
696
697// FastEmit functions for ISD::SIGN_EXTEND.
698
699Register fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, Register Op0) {
700 if (RetVT.SimpleTy != MVT::i64)
701 return Register();
702 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())) {
703 return fastEmitInst_r(MachineInstOpcode: Mips::SLL64_32, RC: &Mips::GPR64RegClass, Op0);
704 }
705 return Register();
706}
707
708Register fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
709 switch (VT.SimpleTy) {
710 case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0);
711 default: return Register();
712 }
713}
714
715// FastEmit functions for ISD::SINT_TO_FP.
716
717Register fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
718 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_S_W, RC: &Mips::FGR32RegClass, Op0);
719}
720
721Register fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
722 if ((Subtarget->isFP64bit())) {
723 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D64_W, RC: &Mips::FGR64RegClass, Op0);
724 }
725 if ((!Subtarget->isFP64bit())) {
726 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D32_W, RC: &Mips::AFGR64RegClass, Op0);
727 }
728 return Register();
729}
730
731Register fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
732switch (RetVT.SimpleTy) {
733 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
734 case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
735 default: return Register();
736}
737}
738
739Register fastEmit_ISD_SINT_TO_FP_MVT_i64_r(MVT RetVT, Register Op0) {
740 if (RetVT.SimpleTy != MVT::f64)
741 return Register();
742 if ((Subtarget->isFP64bit())) {
743 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D64_L, RC: &Mips::FGR64RegClass, Op0);
744 }
745 return Register();
746}
747
748Register fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
749 if (RetVT.SimpleTy != MVT::v4f32)
750 return Register();
751 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
752 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_S_W, RC: &Mips::MSA128WRegClass, Op0);
753 }
754 return Register();
755}
756
757Register fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, Register Op0) {
758 if (RetVT.SimpleTy != MVT::v2f64)
759 return Register();
760 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
761 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_S_D, RC: &Mips::MSA128DRegClass, Op0);
762 }
763 return Register();
764}
765
766Register fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
767 switch (VT.SimpleTy) {
768 case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0);
769 case MVT::i64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_r(RetVT, Op0);
770 case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
771 case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
772 default: return Register();
773 }
774}
775
776// FastEmit functions for ISD::STRICT_FP_EXTEND.
777
778Register fastEmit_ISD_STRICT_FP_EXTEND_MVT_f32_r(MVT RetVT, Register Op0) {
779 if (RetVT.SimpleTy != MVT::f64)
780 return Register();
781 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
782 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D64_S, RC: &Mips::FGR64RegClass, Op0);
783 }
784 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
785 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D32_S, RC: &Mips::AFGR64RegClass, Op0);
786 }
787 return Register();
788}
789
790Register fastEmit_ISD_STRICT_FP_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
791 switch (VT.SimpleTy) {
792 case MVT::f32: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_f32_r(RetVT, Op0);
793 default: return Register();
794 }
795}
796
797// FastEmit functions for ISD::STRICT_FP_ROUND.
798
799Register fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(MVT RetVT, Register Op0) {
800 if (RetVT.SimpleTy != MVT::f32)
801 return Register();
802 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
803 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D64, RC: &Mips::FGR32RegClass, Op0);
804 }
805 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
806 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D32, RC: &Mips::FGR32RegClass, Op0);
807 }
808 return Register();
809}
810
811Register fastEmit_ISD_STRICT_FP_ROUND_r(MVT VT, MVT RetVT, Register Op0) {
812 switch (VT.SimpleTy) {
813 case MVT::f64: return fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(RetVT, Op0);
814 default: return Register();
815 }
816}
817
818// FastEmit functions for ISD::STRICT_FSQRT.
819
820Register fastEmit_ISD_STRICT_FSQRT_MVT_f32_r(MVT RetVT, Register Op0) {
821 if (RetVT.SimpleTy != MVT::f32)
822 return Register();
823 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
824 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_S, RC: &Mips::FGR32RegClass, Op0);
825 }
826 return Register();
827}
828
829Register fastEmit_ISD_STRICT_FSQRT_MVT_f64_r(MVT RetVT, Register Op0) {
830 if (RetVT.SimpleTy != MVT::f64)
831 return Register();
832 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
833 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D64, RC: &Mips::FGR64RegClass, Op0);
834 }
835 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
836 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D32, RC: &Mips::AFGR64RegClass, Op0);
837 }
838 return Register();
839}
840
841Register fastEmit_ISD_STRICT_FSQRT_r(MVT VT, MVT RetVT, Register Op0) {
842 switch (VT.SimpleTy) {
843 case MVT::f32: return fastEmit_ISD_STRICT_FSQRT_MVT_f32_r(RetVT, Op0);
844 case MVT::f64: return fastEmit_ISD_STRICT_FSQRT_MVT_f64_r(RetVT, Op0);
845 default: return Register();
846 }
847}
848
849// FastEmit functions for ISD::STRICT_SINT_TO_FP.
850
851Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
852 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_S_W, RC: &Mips::FGR32RegClass, Op0);
853}
854
855Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
856 if ((Subtarget->isFP64bit())) {
857 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D64_W, RC: &Mips::FGR64RegClass, Op0);
858 }
859 if ((!Subtarget->isFP64bit())) {
860 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D32_W, RC: &Mips::AFGR64RegClass, Op0);
861 }
862 return Register();
863}
864
865Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
866switch (RetVT.SimpleTy) {
867 case MVT::f32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
868 case MVT::f64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
869 default: return Register();
870}
871}
872
873Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_r(MVT RetVT, Register Op0) {
874 if (RetVT.SimpleTy != MVT::f64)
875 return Register();
876 if ((Subtarget->isFP64bit())) {
877 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D64_L, RC: &Mips::FGR64RegClass, Op0);
878 }
879 return Register();
880}
881
882Register fastEmit_ISD_STRICT_SINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
883 switch (VT.SimpleTy) {
884 case MVT::i32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(RetVT, Op0);
885 case MVT::i64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_r(RetVT, Op0);
886 default: return Register();
887 }
888}
889
890// FastEmit functions for ISD::UINT_TO_FP.
891
892Register fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
893 if (RetVT.SimpleTy != MVT::v4f32)
894 return Register();
895 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
896 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_U_W, RC: &Mips::MSA128WRegClass, Op0);
897 }
898 return Register();
899}
900
901Register fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, Register Op0) {
902 if (RetVT.SimpleTy != MVT::v2f64)
903 return Register();
904 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
905 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_U_D, RC: &Mips::MSA128DRegClass, Op0);
906 }
907 return Register();
908}
909
910Register fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
911 switch (VT.SimpleTy) {
912 case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
913 case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
914 default: return Register();
915 }
916}
917
918// FastEmit functions for MipsISD::JmpLink.
919
920Register fastEmit_MipsISD_JmpLink_MVT_i32_r(MVT RetVT, Register Op0) {
921 if (RetVT.SimpleTy != MVT::isVoid)
922 return Register();
923 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
924 return fastEmitInst_r(MachineInstOpcode: Mips::JALR16_MM, RC: &Mips::GPR32RegClass, Op0);
925 }
926 if ((Subtarget->inMips16Mode())) {
927 return fastEmitInst_r(MachineInstOpcode: Mips::JumpLinkReg16, RC: &Mips::CPU16RegsRegClass, Op0);
928 }
929 if ((!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
930 return fastEmitInst_r(MachineInstOpcode: Mips::JALRHBPseudo, RC: &Mips::GPR32RegClass, Op0);
931 }
932 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode())) {
933 return fastEmitInst_r(MachineInstOpcode: Mips::JALRPseudo, RC: &Mips::GPR32RegClass, Op0);
934 }
935 return Register();
936}
937
938Register fastEmit_MipsISD_JmpLink_MVT_i64_r(MVT RetVT, Register Op0) {
939 if (RetVT.SimpleTy != MVT::isVoid)
940 return Register();
941 if ((Subtarget->isABI_N64()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
942 return fastEmitInst_r(MachineInstOpcode: Mips::JALRHB64Pseudo, RC: &Mips::GPR64RegClass, Op0);
943 }
944 if ((Subtarget->isABI_N64()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMips16Mode())) {
945 return fastEmitInst_r(MachineInstOpcode: Mips::JALR64Pseudo, RC: &Mips::GPR64RegClass, Op0);
946 }
947 return Register();
948}
949
950Register fastEmit_MipsISD_JmpLink_r(MVT VT, MVT RetVT, Register Op0) {
951 switch (VT.SimpleTy) {
952 case MVT::i32: return fastEmit_MipsISD_JmpLink_MVT_i32_r(RetVT, Op0);
953 case MVT::i64: return fastEmit_MipsISD_JmpLink_MVT_i64_r(RetVT, Op0);
954 default: return Register();
955 }
956}
957
958// FastEmit functions for MipsISD::MFHI.
959
960Register fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(Register Op0) {
961 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
962 return fastEmitInst_r(MachineInstOpcode: Mips::MFHI_DSP_MM, RC: &Mips::GPR32RegClass, Op0);
963 }
964 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
965 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFHI_MM, RC: &Mips::GPR32RegClass, Op0);
966 }
967 if ((Subtarget->hasDSP())) {
968 return fastEmitInst_r(MachineInstOpcode: Mips::MFHI_DSP, RC: &Mips::GPR32RegClass, Op0);
969 }
970 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
971 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFHI, RC: &Mips::GPR32RegClass, Op0);
972 }
973 return Register();
974}
975
976Register fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(Register Op0) {
977 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
978 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFHI64, RC: &Mips::GPR64RegClass, Op0);
979 }
980 return Register();
981}
982
983Register fastEmit_MipsISD_MFHI_MVT_Untyped_r(MVT RetVT, Register Op0) {
984switch (RetVT.SimpleTy) {
985 case MVT::i32: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(Op0);
986 case MVT::i64: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(Op0);
987 default: return Register();
988}
989}
990
991Register fastEmit_MipsISD_MFHI_r(MVT VT, MVT RetVT, Register Op0) {
992 switch (VT.SimpleTy) {
993 case MVT::Untyped: return fastEmit_MipsISD_MFHI_MVT_Untyped_r(RetVT, Op0);
994 default: return Register();
995 }
996}
997
998// FastEmit functions for MipsISD::MFLO.
999
1000Register fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(Register Op0) {
1001 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
1002 return fastEmitInst_r(MachineInstOpcode: Mips::MFLO_DSP_MM, RC: &Mips::GPR32RegClass, Op0);
1003 }
1004 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
1005 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFLO_MM, RC: &Mips::GPR32RegClass, Op0);
1006 }
1007 if ((Subtarget->hasDSP())) {
1008 return fastEmitInst_r(MachineInstOpcode: Mips::MFLO_DSP, RC: &Mips::GPR32RegClass, Op0);
1009 }
1010 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
1011 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFLO, RC: &Mips::GPR32RegClass, Op0);
1012 }
1013 return Register();
1014}
1015
1016Register fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(Register Op0) {
1017 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
1018 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFLO64, RC: &Mips::GPR64RegClass, Op0);
1019 }
1020 return Register();
1021}
1022
1023Register fastEmit_MipsISD_MFLO_MVT_Untyped_r(MVT RetVT, Register Op0) {
1024switch (RetVT.SimpleTy) {
1025 case MVT::i32: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(Op0);
1026 case MVT::i64: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(Op0);
1027 default: return Register();
1028}
1029}
1030
1031Register fastEmit_MipsISD_MFLO_r(MVT VT, MVT RetVT, Register Op0) {
1032 switch (VT.SimpleTy) {
1033 case MVT::Untyped: return fastEmit_MipsISD_MFLO_MVT_Untyped_r(RetVT, Op0);
1034 default: return Register();
1035 }
1036}
1037
1038// FastEmit functions for MipsISD::MTC1_D64.
1039
1040Register fastEmit_MipsISD_MTC1_D64_MVT_i32_r(MVT RetVT, Register Op0) {
1041 if (RetVT.SimpleTy != MVT::f64)
1042 return Register();
1043 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())) {
1044 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_D64_MM, RC: &Mips::FGR64RegClass, Op0);
1045 }
1046 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
1047 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_D64, RC: &Mips::FGR64RegClass, Op0);
1048 }
1049 return Register();
1050}
1051
1052Register fastEmit_MipsISD_MTC1_D64_r(MVT VT, MVT RetVT, Register Op0) {
1053 switch (VT.SimpleTy) {
1054 case MVT::i32: return fastEmit_MipsISD_MTC1_D64_MVT_i32_r(RetVT, Op0);
1055 default: return Register();
1056 }
1057}
1058
1059// FastEmit functions for MipsISD::TailCall.
1060
1061Register fastEmit_MipsISD_TailCall_MVT_i32_r(MVT RetVT, Register Op0) {
1062 if (RetVT.SimpleTy != MVT::isVoid)
1063 return Register();
1064 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1065 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREG_MMR6, RC: &Mips::GPR32RegClass, Op0);
1066 }
1067 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1068 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREG_MM, RC: &Mips::GPR32RegClass, Op0);
1069 }
1070 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
1071 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLHBR6REG, RC: &Mips::GPR32RegClass, Op0);
1072 }
1073 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
1074 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLR6REG, RC: &Mips::GPR32RegClass, Op0);
1075 }
1076 if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
1077 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREGHB, RC: &Mips::GPR32RegClass, Op0);
1078 }
1079 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
1080 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREG, RC: &Mips::GPR32RegClass, Op0);
1081 }
1082 return Register();
1083}
1084
1085Register fastEmit_MipsISD_TailCall_MVT_i64_r(MVT RetVT, Register Op0) {
1086 if (RetVT.SimpleTy != MVT::isVoid)
1087 return Register();
1088 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
1089 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLHB64R6REG, RC: &Mips::GPR64RegClass, Op0);
1090 }
1091 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
1092 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALL64R6REG, RC: &Mips::GPR64RegClass, Op0);
1093 }
1094 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
1095 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREGHB64, RC: &Mips::GPR64RegClass, Op0);
1096 }
1097 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
1098 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREG64, RC: &Mips::GPR64RegClass, Op0);
1099 }
1100 return Register();
1101}
1102
1103Register fastEmit_MipsISD_TailCall_r(MVT VT, MVT RetVT, Register Op0) {
1104 switch (VT.SimpleTy) {
1105 case MVT::i32: return fastEmit_MipsISD_TailCall_MVT_i32_r(RetVT, Op0);
1106 case MVT::i64: return fastEmit_MipsISD_TailCall_MVT_i64_r(RetVT, Op0);
1107 default: return Register();
1108 }
1109}
1110
1111// FastEmit functions for MipsISD::TruncIntFP.
1112
1113Register fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(Register Op0) {
1114 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1115 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_S_MMR6, RC: &Mips::FGR32RegClass, Op0);
1116 }
1117 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1118 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_S_MM, RC: &Mips::FGR32RegClass, Op0);
1119 }
1120 if ((Subtarget->hasStandardEncoding())) {
1121 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_S, RC: &Mips::FGR32RegClass, Op0);
1122 }
1123 return Register();
1124}
1125
1126Register fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(Register Op0) {
1127 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
1128 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_L_S, RC: &Mips::FGR64RegClass, Op0);
1129 }
1130 return Register();
1131}
1132
1133Register fastEmit_MipsISD_TruncIntFP_MVT_f32_r(MVT RetVT, Register Op0) {
1134switch (RetVT.SimpleTy) {
1135 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(Op0);
1136 case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(Op0);
1137 default: return Register();
1138}
1139}
1140
1141Register fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(Register Op0) {
1142 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1143 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_D_MMR6, RC: &Mips::FGR32RegClass, Op0);
1144 }
1145 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())) {
1146 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_W_D64_MM, RC: &Mips::FGR32RegClass, Op0);
1147 }
1148 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())) {
1149 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_MM, RC: &Mips::FGR32RegClass, Op0);
1150 }
1151 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
1152 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_D64, RC: &Mips::FGR32RegClass, Op0);
1153 }
1154 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1155 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_D32, RC: &Mips::FGR32RegClass, Op0);
1156 }
1157 return Register();
1158}
1159
1160Register fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(Register Op0) {
1161 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
1162 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_L_D64, RC: &Mips::FGR64RegClass, Op0);
1163 }
1164 return Register();
1165}
1166
1167Register fastEmit_MipsISD_TruncIntFP_MVT_f64_r(MVT RetVT, Register Op0) {
1168switch (RetVT.SimpleTy) {
1169 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(Op0);
1170 case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(Op0);
1171 default: return Register();
1172}
1173}
1174
1175Register fastEmit_MipsISD_TruncIntFP_r(MVT VT, MVT RetVT, Register Op0) {
1176 switch (VT.SimpleTy) {
1177 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_r(RetVT, Op0);
1178 case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_r(RetVT, Op0);
1179 default: return Register();
1180 }
1181}
1182
1183// FastEmit functions for MipsISD::VALL_NONZERO.
1184
1185Register fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(MVT RetVT, Register Op0) {
1186 if (RetVT.SimpleTy != MVT::i32)
1187 return Register();
1188 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_B_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1189}
1190
1191Register fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(MVT RetVT, Register Op0) {
1192 if (RetVT.SimpleTy != MVT::i32)
1193 return Register();
1194 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_H_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1195}
1196
1197Register fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(MVT RetVT, Register Op0) {
1198 if (RetVT.SimpleTy != MVT::i32)
1199 return Register();
1200 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_W_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1201}
1202
1203Register fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(MVT RetVT, Register Op0) {
1204 if (RetVT.SimpleTy != MVT::i32)
1205 return Register();
1206 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_D_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1207}
1208
1209Register fastEmit_MipsISD_VALL_NONZERO_r(MVT VT, MVT RetVT, Register Op0) {
1210 switch (VT.SimpleTy) {
1211 case MVT::v16i8: return fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(RetVT, Op0);
1212 case MVT::v8i16: return fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(RetVT, Op0);
1213 case MVT::v4i32: return fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(RetVT, Op0);
1214 case MVT::v2i64: return fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(RetVT, Op0);
1215 default: return Register();
1216 }
1217}
1218
1219// FastEmit functions for MipsISD::VALL_ZERO.
1220
1221Register fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(MVT RetVT, Register Op0) {
1222 if (RetVT.SimpleTy != MVT::i32)
1223 return Register();
1224 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_B_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1225}
1226
1227Register fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(MVT RetVT, Register Op0) {
1228 if (RetVT.SimpleTy != MVT::i32)
1229 return Register();
1230 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_H_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1231}
1232
1233Register fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(MVT RetVT, Register Op0) {
1234 if (RetVT.SimpleTy != MVT::i32)
1235 return Register();
1236 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_W_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1237}
1238
1239Register fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(MVT RetVT, Register Op0) {
1240 if (RetVT.SimpleTy != MVT::i32)
1241 return Register();
1242 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_D_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1243}
1244
1245Register fastEmit_MipsISD_VALL_ZERO_r(MVT VT, MVT RetVT, Register Op0) {
1246 switch (VT.SimpleTy) {
1247 case MVT::v16i8: return fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(RetVT, Op0);
1248 case MVT::v8i16: return fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(RetVT, Op0);
1249 case MVT::v4i32: return fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(RetVT, Op0);
1250 case MVT::v2i64: return fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(RetVT, Op0);
1251 default: return Register();
1252 }
1253}
1254
1255// FastEmit functions for MipsISD::VANY_NONZERO.
1256
1257Register fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(MVT RetVT, Register Op0) {
1258 if (RetVT.SimpleTy != MVT::i32)
1259 return Register();
1260 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_V_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1261}
1262
1263Register fastEmit_MipsISD_VANY_NONZERO_r(MVT VT, MVT RetVT, Register Op0) {
1264 switch (VT.SimpleTy) {
1265 case MVT::v16i8: return fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(RetVT, Op0);
1266 default: return Register();
1267 }
1268}
1269
1270// FastEmit functions for MipsISD::VANY_ZERO.
1271
1272Register fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(MVT RetVT, Register Op0) {
1273 if (RetVT.SimpleTy != MVT::i32)
1274 return Register();
1275 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_V_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1276}
1277
1278Register fastEmit_MipsISD_VANY_ZERO_r(MVT VT, MVT RetVT, Register Op0) {
1279 switch (VT.SimpleTy) {
1280 case MVT::v16i8: return fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(RetVT, Op0);
1281 default: return Register();
1282 }
1283}
1284
1285// Top-level FastEmit function.
1286
1287Register fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, Register Op0) override {
1288 switch (Opcode) {
1289 case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0);
1290 case ISD::BRIND: return fastEmit_ISD_BRIND_r(VT, RetVT, Op0);
1291 case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0);
1292 case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0);
1293 case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0);
1294 case ISD::FEXP2: return fastEmit_ISD_FEXP2_r(VT, RetVT, Op0);
1295 case ISD::FLOG2: return fastEmit_ISD_FLOG2_r(VT, RetVT, Op0);
1296 case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0);
1297 case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0);
1298 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0);
1299 case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0);
1300 case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0);
1301 case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0);
1302 case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0);
1303 case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0);
1304 case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0);
1305 case ISD::STRICT_FP_EXTEND: return fastEmit_ISD_STRICT_FP_EXTEND_r(VT, RetVT, Op0);
1306 case ISD::STRICT_FP_ROUND: return fastEmit_ISD_STRICT_FP_ROUND_r(VT, RetVT, Op0);
1307 case ISD::STRICT_FSQRT: return fastEmit_ISD_STRICT_FSQRT_r(VT, RetVT, Op0);
1308 case ISD::STRICT_SINT_TO_FP: return fastEmit_ISD_STRICT_SINT_TO_FP_r(VT, RetVT, Op0);
1309 case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0);
1310 case MipsISD::JmpLink: return fastEmit_MipsISD_JmpLink_r(VT, RetVT, Op0);
1311 case MipsISD::MFHI: return fastEmit_MipsISD_MFHI_r(VT, RetVT, Op0);
1312 case MipsISD::MFLO: return fastEmit_MipsISD_MFLO_r(VT, RetVT, Op0);
1313 case MipsISD::MTC1_D64: return fastEmit_MipsISD_MTC1_D64_r(VT, RetVT, Op0);
1314 case MipsISD::TailCall: return fastEmit_MipsISD_TailCall_r(VT, RetVT, Op0);
1315 case MipsISD::TruncIntFP: return fastEmit_MipsISD_TruncIntFP_r(VT, RetVT, Op0);
1316 case MipsISD::VALL_NONZERO: return fastEmit_MipsISD_VALL_NONZERO_r(VT, RetVT, Op0);
1317 case MipsISD::VALL_ZERO: return fastEmit_MipsISD_VALL_ZERO_r(VT, RetVT, Op0);
1318 case MipsISD::VANY_NONZERO: return fastEmit_MipsISD_VANY_NONZERO_r(VT, RetVT, Op0);
1319 case MipsISD::VANY_ZERO: return fastEmit_MipsISD_VANY_ZERO_r(VT, RetVT, Op0);
1320 default: return Register();
1321 }
1322}
1323
1324// FastEmit functions for ISD::ADD.
1325
1326Register fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1327 if (RetVT.SimpleTy != MVT::i32)
1328 return Register();
1329 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1330 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDU16_MMR6, RC: &Mips::GPRMM16RegClass, Op0, Op1);
1331 }
1332 if ((Subtarget->inMips16Mode())) {
1333 return fastEmitInst_rr(MachineInstOpcode: Mips::AdduRxRyRz16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
1334 }
1335 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1336 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDu_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
1337 }
1338 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1339 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDu, RC: &Mips::GPR32RegClass, Op0, Op1);
1340 }
1341 return Register();
1342}
1343
1344Register fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1345 if (RetVT.SimpleTy != MVT::i64)
1346 return Register();
1347 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1348 return fastEmitInst_rr(MachineInstOpcode: Mips::DADDu, RC: &Mips::GPR64RegClass, Op0, Op1);
1349 }
1350 return Register();
1351}
1352
1353Register fastEmit_ISD_ADD_MVT_v4i8_rr(MVT RetVT, Register Op0, Register Op1) {
1354 if (RetVT.SimpleTy != MVT::v4i8)
1355 return Register();
1356 if ((Subtarget->hasDSP())) {
1357 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDU_QB, RC: &Mips::DSPRRegClass, Op0, Op1);
1358 }
1359 return Register();
1360}
1361
1362Register fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1363 if (RetVT.SimpleTy != MVT::v16i8)
1364 return Register();
1365 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1366 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
1367 }
1368 return Register();
1369}
1370
1371Register fastEmit_ISD_ADD_MVT_v2i16_rr(MVT RetVT, Register Op0, Register Op1) {
1372 if (RetVT.SimpleTy != MVT::v2i16)
1373 return Register();
1374 if ((Subtarget->hasDSP())) {
1375 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDQ_PH, RC: &Mips::DSPRRegClass, Op0, Op1);
1376 }
1377 return Register();
1378}
1379
1380Register fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1381 if (RetVT.SimpleTy != MVT::v8i16)
1382 return Register();
1383 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1384 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
1385 }
1386 return Register();
1387}
1388
1389Register fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
1390 if (RetVT.SimpleTy != MVT::v4i32)
1391 return Register();
1392 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1393 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1394 }
1395 return Register();
1396}
1397
1398Register fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
1399 if (RetVT.SimpleTy != MVT::v2i64)
1400 return Register();
1401 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1402 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1403 }
1404 return Register();
1405}
1406
1407Register fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1408 switch (VT.SimpleTy) {
1409 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op1);
1410 case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op1);
1411 case MVT::v4i8: return fastEmit_ISD_ADD_MVT_v4i8_rr(RetVT, Op0, Op1);
1412 case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op1);
1413 case MVT::v2i16: return fastEmit_ISD_ADD_MVT_v2i16_rr(RetVT, Op0, Op1);
1414 case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op1);
1415 case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op1);
1416 case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op1);
1417 default: return Register();
1418 }
1419}
1420
1421// FastEmit functions for ISD::ADDC.
1422
1423Register fastEmit_ISD_ADDC_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1424 if (RetVT.SimpleTy != MVT::i32)
1425 return Register();
1426 if ((Subtarget->hasDSP())) {
1427 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDSC, RC: &Mips::GPR32RegClass, Op0, Op1);
1428 }
1429 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP())) {
1430 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDu, RC: &Mips::GPR32RegClass, Op0, Op1);
1431 }
1432 return Register();
1433}
1434
1435Register fastEmit_ISD_ADDC_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1436 if (RetVT.SimpleTy != MVT::i64)
1437 return Register();
1438 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->hasDSP()) && (!Subtarget->inMicroMipsMode())) {
1439 return fastEmitInst_rr(MachineInstOpcode: Mips::DADDu, RC: &Mips::GPR64RegClass, Op0, Op1);
1440 }
1441 return Register();
1442}
1443
1444Register fastEmit_ISD_ADDC_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1445 switch (VT.SimpleTy) {
1446 case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_rr(RetVT, Op0, Op1);
1447 case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_rr(RetVT, Op0, Op1);
1448 default: return Register();
1449 }
1450}
1451
1452// FastEmit functions for ISD::ADDE.
1453
1454Register fastEmit_ISD_ADDE_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1455 if (RetVT.SimpleTy != MVT::i32)
1456 return Register();
1457 if ((Subtarget->hasDSP())) {
1458 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDWC, RC: &Mips::GPR32RegClass, Op0, Op1);
1459 }
1460 return Register();
1461}
1462
1463Register fastEmit_ISD_ADDE_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1464 switch (VT.SimpleTy) {
1465 case MVT::i32: return fastEmit_ISD_ADDE_MVT_i32_rr(RetVT, Op0, Op1);
1466 default: return Register();
1467 }
1468}
1469
1470// FastEmit functions for ISD::AND.
1471
1472Register fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1473 if (RetVT.SimpleTy != MVT::i32)
1474 return Register();
1475 if ((Subtarget->inMips16Mode())) {
1476 return fastEmitInst_rr(MachineInstOpcode: Mips::AndRxRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
1477 }
1478 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1479 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
1480 }
1481 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1482 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
1483 }
1484 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1485 return fastEmitInst_rr(MachineInstOpcode: Mips::AND, RC: &Mips::GPR32RegClass, Op0, Op1);
1486 }
1487 return Register();
1488}
1489
1490Register fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1491 if (RetVT.SimpleTy != MVT::i64)
1492 return Register();
1493 if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
1494 return fastEmitInst_rr(MachineInstOpcode: Mips::AND64, RC: &Mips::GPR64RegClass, Op0, Op1);
1495 }
1496 return Register();
1497}
1498
1499Register fastEmit_ISD_AND_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1500 if (RetVT.SimpleTy != MVT::v16i8)
1501 return Register();
1502 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1503 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
1504 }
1505 return Register();
1506}
1507
1508Register fastEmit_ISD_AND_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1509 if (RetVT.SimpleTy != MVT::v8i16)
1510 return Register();
1511 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1512 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
1513 }
1514 return Register();
1515}
1516
1517Register fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
1518 if (RetVT.SimpleTy != MVT::v4i32)
1519 return Register();
1520 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1521 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
1522 }
1523 return Register();
1524}
1525
1526Register fastEmit_ISD_AND_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
1527 if (RetVT.SimpleTy != MVT::v2i64)
1528 return Register();
1529 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1530 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
1531 }
1532 return Register();
1533}
1534
1535Register fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1536 switch (VT.SimpleTy) {
1537 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op1);
1538 case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op1);
1539 case MVT::v16i8: return fastEmit_ISD_AND_MVT_v16i8_rr(RetVT, Op0, Op1);
1540 case MVT::v8i16: return fastEmit_ISD_AND_MVT_v8i16_rr(RetVT, Op0, Op1);
1541 case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op1);
1542 case MVT::v2i64: return fastEmit_ISD_AND_MVT_v2i64_rr(RetVT, Op0, Op1);
1543 default: return Register();
1544 }
1545}
1546
1547// FastEmit functions for ISD::FADD.
1548
1549Register fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1550 if (RetVT.SimpleTy != MVT::f32)
1551 return Register();
1552 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1553 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1554 }
1555 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1556 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1557 }
1558 return Register();
1559}
1560
1561Register fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1562 if (RetVT.SimpleTy != MVT::f64)
1563 return Register();
1564 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
1565 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1566 }
1567 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1568 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1569 }
1570 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1571 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1572 }
1573 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1574 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1575 }
1576 return Register();
1577}
1578
1579Register fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1580 if (RetVT.SimpleTy != MVT::v4f32)
1581 return Register();
1582 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1583 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1584 }
1585 return Register();
1586}
1587
1588Register fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1589 if (RetVT.SimpleTy != MVT::v2f64)
1590 return Register();
1591 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1592 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1593 }
1594 return Register();
1595}
1596
1597Register fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1598 switch (VT.SimpleTy) {
1599 case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op1);
1600 case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op1);
1601 case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op1);
1602 case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op1);
1603 default: return Register();
1604 }
1605}
1606
1607// FastEmit functions for ISD::FDIV.
1608
1609Register fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1610 if (RetVT.SimpleTy != MVT::f32)
1611 return Register();
1612 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1613 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1614 }
1615 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1616 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1617 }
1618 return Register();
1619}
1620
1621Register fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1622 if (RetVT.SimpleTy != MVT::f64)
1623 return Register();
1624 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
1625 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1626 }
1627 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1628 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1629 }
1630 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1631 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1632 }
1633 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1634 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1635 }
1636 return Register();
1637}
1638
1639Register fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1640 if (RetVT.SimpleTy != MVT::v4f32)
1641 return Register();
1642 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1643 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1644 }
1645 return Register();
1646}
1647
1648Register fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1649 if (RetVT.SimpleTy != MVT::v2f64)
1650 return Register();
1651 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1652 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1653 }
1654 return Register();
1655}
1656
1657Register fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1658 switch (VT.SimpleTy) {
1659 case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op1);
1660 case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op1);
1661 case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op1);
1662 case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op1);
1663 default: return Register();
1664 }
1665}
1666
1667// FastEmit functions for ISD::FMAXNUM.
1668
1669Register fastEmit_ISD_FMAXNUM_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1670 if (RetVT.SimpleTy != MVT::f32)
1671 return Register();
1672 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1673 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1674 }
1675 return Register();
1676}
1677
1678Register fastEmit_ISD_FMAXNUM_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1679 if (RetVT.SimpleTy != MVT::f64)
1680 return Register();
1681 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1682 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_D, RC: &Mips::FGR64RegClass, Op0, Op1);
1683 }
1684 return Register();
1685}
1686
1687Register fastEmit_ISD_FMAXNUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1688 switch (VT.SimpleTy) {
1689 case MVT::f32: return fastEmit_ISD_FMAXNUM_MVT_f32_rr(RetVT, Op0, Op1);
1690 case MVT::f64: return fastEmit_ISD_FMAXNUM_MVT_f64_rr(RetVT, Op0, Op1);
1691 default: return Register();
1692 }
1693}
1694
1695// FastEmit functions for ISD::FMAXNUM_IEEE.
1696
1697Register fastEmit_ISD_FMAXNUM_IEEE_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1698 if (RetVT.SimpleTy != MVT::f32)
1699 return Register();
1700 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1701 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1702 }
1703 return Register();
1704}
1705
1706Register fastEmit_ISD_FMAXNUM_IEEE_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1707 if (RetVT.SimpleTy != MVT::f64)
1708 return Register();
1709 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1710 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_D, RC: &Mips::FGR64RegClass, Op0, Op1);
1711 }
1712 return Register();
1713}
1714
1715Register fastEmit_ISD_FMAXNUM_IEEE_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1716 switch (VT.SimpleTy) {
1717 case MVT::f32: return fastEmit_ISD_FMAXNUM_IEEE_MVT_f32_rr(RetVT, Op0, Op1);
1718 case MVT::f64: return fastEmit_ISD_FMAXNUM_IEEE_MVT_f64_rr(RetVT, Op0, Op1);
1719 default: return Register();
1720 }
1721}
1722
1723// FastEmit functions for ISD::FMINNUM.
1724
1725Register fastEmit_ISD_FMINNUM_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1726 if (RetVT.SimpleTy != MVT::f32)
1727 return Register();
1728 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1729 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1730 }
1731 return Register();
1732}
1733
1734Register fastEmit_ISD_FMINNUM_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1735 if (RetVT.SimpleTy != MVT::f64)
1736 return Register();
1737 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1738 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_D, RC: &Mips::FGR64RegClass, Op0, Op1);
1739 }
1740 return Register();
1741}
1742
1743Register fastEmit_ISD_FMINNUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1744 switch (VT.SimpleTy) {
1745 case MVT::f32: return fastEmit_ISD_FMINNUM_MVT_f32_rr(RetVT, Op0, Op1);
1746 case MVT::f64: return fastEmit_ISD_FMINNUM_MVT_f64_rr(RetVT, Op0, Op1);
1747 default: return Register();
1748 }
1749}
1750
1751// FastEmit functions for ISD::FMINNUM_IEEE.
1752
1753Register fastEmit_ISD_FMINNUM_IEEE_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1754 if (RetVT.SimpleTy != MVT::f32)
1755 return Register();
1756 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1757 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1758 }
1759 return Register();
1760}
1761
1762Register fastEmit_ISD_FMINNUM_IEEE_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1763 if (RetVT.SimpleTy != MVT::f64)
1764 return Register();
1765 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1766 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_D, RC: &Mips::FGR64RegClass, Op0, Op1);
1767 }
1768 return Register();
1769}
1770
1771Register fastEmit_ISD_FMINNUM_IEEE_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1772 switch (VT.SimpleTy) {
1773 case MVT::f32: return fastEmit_ISD_FMINNUM_IEEE_MVT_f32_rr(RetVT, Op0, Op1);
1774 case MVT::f64: return fastEmit_ISD_FMINNUM_IEEE_MVT_f64_rr(RetVT, Op0, Op1);
1775 default: return Register();
1776 }
1777}
1778
1779// FastEmit functions for ISD::FMUL.
1780
1781Register fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1782 if (RetVT.SimpleTy != MVT::f32)
1783 return Register();
1784 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1785 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1786 }
1787 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1788 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1789 }
1790 return Register();
1791}
1792
1793Register fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1794 if (RetVT.SimpleTy != MVT::f64)
1795 return Register();
1796 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
1797 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1798 }
1799 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1800 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1801 }
1802 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1803 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1804 }
1805 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1806 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1807 }
1808 return Register();
1809}
1810
1811Register fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1812 if (RetVT.SimpleTy != MVT::v4f32)
1813 return Register();
1814 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1815 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1816 }
1817 return Register();
1818}
1819
1820Register fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1821 if (RetVT.SimpleTy != MVT::v2f64)
1822 return Register();
1823 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1824 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1825 }
1826 return Register();
1827}
1828
1829Register fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1830 switch (VT.SimpleTy) {
1831 case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op1);
1832 case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op1);
1833 case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op1);
1834 case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op1);
1835 default: return Register();
1836 }
1837}
1838
1839// FastEmit functions for ISD::FSUB.
1840
1841Register fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1842 if (RetVT.SimpleTy != MVT::f32)
1843 return Register();
1844 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1845 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1846 }
1847 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1848 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1849 }
1850 return Register();
1851}
1852
1853Register fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1854 if (RetVT.SimpleTy != MVT::f64)
1855 return Register();
1856 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
1857 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1858 }
1859 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1860 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1861 }
1862 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1863 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1864 }
1865 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1866 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1867 }
1868 return Register();
1869}
1870
1871Register fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1872 if (RetVT.SimpleTy != MVT::v4f32)
1873 return Register();
1874 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1875 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1876 }
1877 return Register();
1878}
1879
1880Register fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1881 if (RetVT.SimpleTy != MVT::v2f64)
1882 return Register();
1883 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1884 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1885 }
1886 return Register();
1887}
1888
1889Register fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1890 switch (VT.SimpleTy) {
1891 case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op1);
1892 case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op1);
1893 case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op1);
1894 case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op1);
1895 default: return Register();
1896 }
1897}
1898
1899// FastEmit functions for ISD::MUL.
1900
1901Register fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1902 if (RetVT.SimpleTy != MVT::i32)
1903 return Register();
1904 if ((Subtarget->inMips16Mode())) {
1905 return fastEmitInst_rr(MachineInstOpcode: Mips::MultRxRyRz16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
1906 }
1907 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1908 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
1909 }
1910 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1911 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
1912 }
1913 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1914 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_R6, RC: &Mips::GPR32RegClass, Op0, Op1);
1915 }
1916 if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
1917 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL, RC: &Mips::GPR32RegClass, Op0, Op1);
1918 }
1919 return Register();
1920}
1921
1922Register fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1923 if (RetVT.SimpleTy != MVT::i64)
1924 return Register();
1925 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1926 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUL_R6, RC: &Mips::GPR64RegClass, Op0, Op1);
1927 }
1928 if ((Subtarget->hasCnMips())) {
1929 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUL, RC: &Mips::GPR64RegClass, Op0, Op1);
1930 }
1931 return Register();
1932}
1933
1934Register fastEmit_ISD_MUL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1935 if (RetVT.SimpleTy != MVT::v16i8)
1936 return Register();
1937 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1938 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
1939 }
1940 return Register();
1941}
1942
1943Register fastEmit_ISD_MUL_MVT_v2i16_rr(MVT RetVT, Register Op0, Register Op1) {
1944 if (RetVT.SimpleTy != MVT::v2i16)
1945 return Register();
1946 if ((Subtarget->hasDSPR2())) {
1947 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_PH, RC: &Mips::DSPRRegClass, Op0, Op1);
1948 }
1949 return Register();
1950}
1951
1952Register fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1953 if (RetVT.SimpleTy != MVT::v8i16)
1954 return Register();
1955 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1956 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
1957 }
1958 return Register();
1959}
1960
1961Register fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
1962 if (RetVT.SimpleTy != MVT::v4i32)
1963 return Register();
1964 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1965 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1966 }
1967 return Register();
1968}
1969
1970Register fastEmit_ISD_MUL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
1971 if (RetVT.SimpleTy != MVT::v2i64)
1972 return Register();
1973 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1974 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1975 }
1976 return Register();
1977}
1978
1979Register fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1980 switch (VT.SimpleTy) {
1981 case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op1);
1982 case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op1);
1983 case MVT::v16i8: return fastEmit_ISD_MUL_MVT_v16i8_rr(RetVT, Op0, Op1);
1984 case MVT::v2i16: return fastEmit_ISD_MUL_MVT_v2i16_rr(RetVT, Op0, Op1);
1985 case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op1);
1986 case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op1);
1987 case MVT::v2i64: return fastEmit_ISD_MUL_MVT_v2i64_rr(RetVT, Op0, Op1);
1988 default: return Register();
1989 }
1990}
1991
1992// FastEmit functions for ISD::MULHS.
1993
1994Register fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1995 if (RetVT.SimpleTy != MVT::i32)
1996 return Register();
1997 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1998 return fastEmitInst_rr(MachineInstOpcode: Mips::MUH_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
1999 }
2000 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2001 return fastEmitInst_rr(MachineInstOpcode: Mips::MUH, RC: &Mips::GPR32RegClass, Op0, Op1);
2002 }
2003 return Register();
2004}
2005
2006Register fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2007 if (RetVT.SimpleTy != MVT::i64)
2008 return Register();
2009 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2010 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUH, RC: &Mips::GPR64RegClass, Op0, Op1);
2011 }
2012 return Register();
2013}
2014
2015Register fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2016 switch (VT.SimpleTy) {
2017 case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op1);
2018 case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op1);
2019 default: return Register();
2020 }
2021}
2022
2023// FastEmit functions for ISD::MULHU.
2024
2025Register fastEmit_ISD_MULHU_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2026 if (RetVT.SimpleTy != MVT::i32)
2027 return Register();
2028 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2029 return fastEmitInst_rr(MachineInstOpcode: Mips::MUHU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2030 }
2031 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2032 return fastEmitInst_rr(MachineInstOpcode: Mips::MUHU, RC: &Mips::GPR32RegClass, Op0, Op1);
2033 }
2034 return Register();
2035}
2036
2037Register fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2038 if (RetVT.SimpleTy != MVT::i64)
2039 return Register();
2040 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2041 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUHU, RC: &Mips::GPR64RegClass, Op0, Op1);
2042 }
2043 return Register();
2044}
2045
2046Register fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2047 switch (VT.SimpleTy) {
2048 case MVT::i32: return fastEmit_ISD_MULHU_MVT_i32_rr(RetVT, Op0, Op1);
2049 case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op1);
2050 default: return Register();
2051 }
2052}
2053
2054// FastEmit functions for ISD::OR.
2055
2056Register fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2057 if (RetVT.SimpleTy != MVT::i32)
2058 return Register();
2059 if ((Subtarget->inMips16Mode())) {
2060 return fastEmitInst_rr(MachineInstOpcode: Mips::OrRxRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2061 }
2062 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2063 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2064 }
2065 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
2066 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2067 }
2068 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2069 return fastEmitInst_rr(MachineInstOpcode: Mips::OR, RC: &Mips::GPR32RegClass, Op0, Op1);
2070 }
2071 return Register();
2072}
2073
2074Register fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2075 if (RetVT.SimpleTy != MVT::i64)
2076 return Register();
2077 if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
2078 return fastEmitInst_rr(MachineInstOpcode: Mips::OR64, RC: &Mips::GPR64RegClass, Op0, Op1);
2079 }
2080 return Register();
2081}
2082
2083Register fastEmit_ISD_OR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2084 if (RetVT.SimpleTy != MVT::v16i8)
2085 return Register();
2086 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2087 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
2088 }
2089 return Register();
2090}
2091
2092Register fastEmit_ISD_OR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2093 if (RetVT.SimpleTy != MVT::v8i16)
2094 return Register();
2095 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2096 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
2097 }
2098 return Register();
2099}
2100
2101Register fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2102 if (RetVT.SimpleTy != MVT::v4i32)
2103 return Register();
2104 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2105 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
2106 }
2107 return Register();
2108}
2109
2110Register fastEmit_ISD_OR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2111 if (RetVT.SimpleTy != MVT::v2i64)
2112 return Register();
2113 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2114 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
2115 }
2116 return Register();
2117}
2118
2119Register fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2120 switch (VT.SimpleTy) {
2121 case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op1);
2122 case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op1);
2123 case MVT::v16i8: return fastEmit_ISD_OR_MVT_v16i8_rr(RetVT, Op0, Op1);
2124 case MVT::v8i16: return fastEmit_ISD_OR_MVT_v8i16_rr(RetVT, Op0, Op1);
2125 case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op1);
2126 case MVT::v2i64: return fastEmit_ISD_OR_MVT_v2i64_rr(RetVT, Op0, Op1);
2127 default: return Register();
2128 }
2129}
2130
2131// FastEmit functions for ISD::ROTR.
2132
2133Register fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2134 if (RetVT.SimpleTy != MVT::i32)
2135 return Register();
2136 if ((Subtarget->inMicroMipsMode())) {
2137 return fastEmitInst_rr(MachineInstOpcode: Mips::ROTRV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2138 }
2139 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2140 return fastEmitInst_rr(MachineInstOpcode: Mips::ROTRV, RC: &Mips::GPR32RegClass, Op0, Op1);
2141 }
2142 return Register();
2143}
2144
2145Register fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2146 switch (VT.SimpleTy) {
2147 case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op1);
2148 default: return Register();
2149 }
2150}
2151
2152// FastEmit functions for ISD::SDIV.
2153
2154Register fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2155 if (RetVT.SimpleTy != MVT::i32)
2156 return Register();
2157 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2158 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2159 }
2160 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2161 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV, RC: &Mips::GPR32RegClass, Op0, Op1);
2162 }
2163 return Register();
2164}
2165
2166Register fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2167 if (RetVT.SimpleTy != MVT::i64)
2168 return Register();
2169 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2170 return fastEmitInst_rr(MachineInstOpcode: Mips::DDIV, RC: &Mips::GPR64RegClass, Op0, Op1);
2171 }
2172 return Register();
2173}
2174
2175Register fastEmit_ISD_SDIV_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2176 if (RetVT.SimpleTy != MVT::v16i8)
2177 return Register();
2178 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2179 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2180 }
2181 return Register();
2182}
2183
2184Register fastEmit_ISD_SDIV_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2185 if (RetVT.SimpleTy != MVT::v8i16)
2186 return Register();
2187 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2188 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2189 }
2190 return Register();
2191}
2192
2193Register fastEmit_ISD_SDIV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2194 if (RetVT.SimpleTy != MVT::v4i32)
2195 return Register();
2196 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2197 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2198 }
2199 return Register();
2200}
2201
2202Register fastEmit_ISD_SDIV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2203 if (RetVT.SimpleTy != MVT::v2i64)
2204 return Register();
2205 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2206 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2207 }
2208 return Register();
2209}
2210
2211Register fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2212 switch (VT.SimpleTy) {
2213 case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op1);
2214 case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op1);
2215 case MVT::v16i8: return fastEmit_ISD_SDIV_MVT_v16i8_rr(RetVT, Op0, Op1);
2216 case MVT::v8i16: return fastEmit_ISD_SDIV_MVT_v8i16_rr(RetVT, Op0, Op1);
2217 case MVT::v4i32: return fastEmit_ISD_SDIV_MVT_v4i32_rr(RetVT, Op0, Op1);
2218 case MVT::v2i64: return fastEmit_ISD_SDIV_MVT_v2i64_rr(RetVT, Op0, Op1);
2219 default: return Register();
2220 }
2221}
2222
2223// FastEmit functions for ISD::SHL.
2224
2225Register fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2226 if (RetVT.SimpleTy != MVT::i32)
2227 return Register();
2228 if ((Subtarget->inMicroMipsMode())) {
2229 return fastEmitInst_rr(MachineInstOpcode: Mips::SLLV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2230 }
2231 if ((Subtarget->inMips16Mode())) {
2232 return fastEmitInst_rr(MachineInstOpcode: Mips::SllvRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2233 }
2234 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2235 return fastEmitInst_rr(MachineInstOpcode: Mips::SLLV, RC: &Mips::GPR32RegClass, Op0, Op1);
2236 }
2237 return Register();
2238}
2239
2240Register fastEmit_ISD_SHL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2241 if (RetVT.SimpleTy != MVT::v16i8)
2242 return Register();
2243 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2244 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2245 }
2246 return Register();
2247}
2248
2249Register fastEmit_ISD_SHL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2250 if (RetVT.SimpleTy != MVT::v8i16)
2251 return Register();
2252 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2253 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2254 }
2255 return Register();
2256}
2257
2258Register fastEmit_ISD_SHL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2259 if (RetVT.SimpleTy != MVT::v4i32)
2260 return Register();
2261 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2262 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2263 }
2264 return Register();
2265}
2266
2267Register fastEmit_ISD_SHL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2268 if (RetVT.SimpleTy != MVT::v2i64)
2269 return Register();
2270 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2271 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2272 }
2273 return Register();
2274}
2275
2276Register fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2277 switch (VT.SimpleTy) {
2278 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op1);
2279 case MVT::v16i8: return fastEmit_ISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op1);
2280 case MVT::v8i16: return fastEmit_ISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op1);
2281 case MVT::v4i32: return fastEmit_ISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op1);
2282 case MVT::v2i64: return fastEmit_ISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op1);
2283 default: return Register();
2284 }
2285}
2286
2287// FastEmit functions for ISD::SMAX.
2288
2289Register fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2290 if (RetVT.SimpleTy != MVT::v16i8)
2291 return Register();
2292 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2293 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2294 }
2295 return Register();
2296}
2297
2298Register fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2299 if (RetVT.SimpleTy != MVT::v8i16)
2300 return Register();
2301 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2302 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2303 }
2304 return Register();
2305}
2306
2307Register fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2308 if (RetVT.SimpleTy != MVT::v4i32)
2309 return Register();
2310 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2311 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2312 }
2313 return Register();
2314}
2315
2316Register fastEmit_ISD_SMAX_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2317 if (RetVT.SimpleTy != MVT::v2i64)
2318 return Register();
2319 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2320 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2321 }
2322 return Register();
2323}
2324
2325Register fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2326 switch (VT.SimpleTy) {
2327 case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
2328 case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
2329 case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
2330 case MVT::v2i64: return fastEmit_ISD_SMAX_MVT_v2i64_rr(RetVT, Op0, Op1);
2331 default: return Register();
2332 }
2333}
2334
2335// FastEmit functions for ISD::SMIN.
2336
2337Register fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2338 if (RetVT.SimpleTy != MVT::v16i8)
2339 return Register();
2340 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2341 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2342 }
2343 return Register();
2344}
2345
2346Register fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2347 if (RetVT.SimpleTy != MVT::v8i16)
2348 return Register();
2349 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2350 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2351 }
2352 return Register();
2353}
2354
2355Register fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2356 if (RetVT.SimpleTy != MVT::v4i32)
2357 return Register();
2358 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2359 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2360 }
2361 return Register();
2362}
2363
2364Register fastEmit_ISD_SMIN_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2365 if (RetVT.SimpleTy != MVT::v2i64)
2366 return Register();
2367 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2368 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2369 }
2370 return Register();
2371}
2372
2373Register fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2374 switch (VT.SimpleTy) {
2375 case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
2376 case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
2377 case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
2378 case MVT::v2i64: return fastEmit_ISD_SMIN_MVT_v2i64_rr(RetVT, Op0, Op1);
2379 default: return Register();
2380 }
2381}
2382
2383// FastEmit functions for ISD::SRA.
2384
2385Register fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2386 if (RetVT.SimpleTy != MVT::i32)
2387 return Register();
2388 if ((Subtarget->inMicroMipsMode())) {
2389 return fastEmitInst_rr(MachineInstOpcode: Mips::SRAV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2390 }
2391 if ((Subtarget->inMips16Mode())) {
2392 return fastEmitInst_rr(MachineInstOpcode: Mips::SravRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2393 }
2394 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2395 return fastEmitInst_rr(MachineInstOpcode: Mips::SRAV, RC: &Mips::GPR32RegClass, Op0, Op1);
2396 }
2397 return Register();
2398}
2399
2400Register fastEmit_ISD_SRA_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2401 if (RetVT.SimpleTy != MVT::v16i8)
2402 return Register();
2403 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2404 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2405 }
2406 return Register();
2407}
2408
2409Register fastEmit_ISD_SRA_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2410 if (RetVT.SimpleTy != MVT::v8i16)
2411 return Register();
2412 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2413 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2414 }
2415 return Register();
2416}
2417
2418Register fastEmit_ISD_SRA_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2419 if (RetVT.SimpleTy != MVT::v4i32)
2420 return Register();
2421 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2422 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2423 }
2424 return Register();
2425}
2426
2427Register fastEmit_ISD_SRA_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2428 if (RetVT.SimpleTy != MVT::v2i64)
2429 return Register();
2430 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2431 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2432 }
2433 return Register();
2434}
2435
2436Register fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2437 switch (VT.SimpleTy) {
2438 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op1);
2439 case MVT::v16i8: return fastEmit_ISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op1);
2440 case MVT::v8i16: return fastEmit_ISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op1);
2441 case MVT::v4i32: return fastEmit_ISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op1);
2442 case MVT::v2i64: return fastEmit_ISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op1);
2443 default: return Register();
2444 }
2445}
2446
2447// FastEmit functions for ISD::SREM.
2448
2449Register fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2450 if (RetVT.SimpleTy != MVT::i32)
2451 return Register();
2452 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2453 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2454 }
2455 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2456 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD, RC: &Mips::GPR32RegClass, Op0, Op1);
2457 }
2458 return Register();
2459}
2460
2461Register fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2462 if (RetVT.SimpleTy != MVT::i64)
2463 return Register();
2464 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2465 return fastEmitInst_rr(MachineInstOpcode: Mips::DMOD, RC: &Mips::GPR64RegClass, Op0, Op1);
2466 }
2467 return Register();
2468}
2469
2470Register fastEmit_ISD_SREM_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2471 if (RetVT.SimpleTy != MVT::v16i8)
2472 return Register();
2473 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2474 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2475 }
2476 return Register();
2477}
2478
2479Register fastEmit_ISD_SREM_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2480 if (RetVT.SimpleTy != MVT::v8i16)
2481 return Register();
2482 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2483 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2484 }
2485 return Register();
2486}
2487
2488Register fastEmit_ISD_SREM_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2489 if (RetVT.SimpleTy != MVT::v4i32)
2490 return Register();
2491 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2492 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2493 }
2494 return Register();
2495}
2496
2497Register fastEmit_ISD_SREM_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2498 if (RetVT.SimpleTy != MVT::v2i64)
2499 return Register();
2500 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2501 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2502 }
2503 return Register();
2504}
2505
2506Register fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2507 switch (VT.SimpleTy) {
2508 case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op1);
2509 case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op1);
2510 case MVT::v16i8: return fastEmit_ISD_SREM_MVT_v16i8_rr(RetVT, Op0, Op1);
2511 case MVT::v8i16: return fastEmit_ISD_SREM_MVT_v8i16_rr(RetVT, Op0, Op1);
2512 case MVT::v4i32: return fastEmit_ISD_SREM_MVT_v4i32_rr(RetVT, Op0, Op1);
2513 case MVT::v2i64: return fastEmit_ISD_SREM_MVT_v2i64_rr(RetVT, Op0, Op1);
2514 default: return Register();
2515 }
2516}
2517
2518// FastEmit functions for ISD::SRL.
2519
2520Register fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2521 if (RetVT.SimpleTy != MVT::i32)
2522 return Register();
2523 if ((Subtarget->inMicroMipsMode())) {
2524 return fastEmitInst_rr(MachineInstOpcode: Mips::SRLV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2525 }
2526 if ((Subtarget->inMips16Mode())) {
2527 return fastEmitInst_rr(MachineInstOpcode: Mips::SrlvRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2528 }
2529 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2530 return fastEmitInst_rr(MachineInstOpcode: Mips::SRLV, RC: &Mips::GPR32RegClass, Op0, Op1);
2531 }
2532 return Register();
2533}
2534
2535Register fastEmit_ISD_SRL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2536 if (RetVT.SimpleTy != MVT::v16i8)
2537 return Register();
2538 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2539 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2540 }
2541 return Register();
2542}
2543
2544Register fastEmit_ISD_SRL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2545 if (RetVT.SimpleTy != MVT::v8i16)
2546 return Register();
2547 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2548 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2549 }
2550 return Register();
2551}
2552
2553Register fastEmit_ISD_SRL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2554 if (RetVT.SimpleTy != MVT::v4i32)
2555 return Register();
2556 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2557 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2558 }
2559 return Register();
2560}
2561
2562Register fastEmit_ISD_SRL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2563 if (RetVT.SimpleTy != MVT::v2i64)
2564 return Register();
2565 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2566 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2567 }
2568 return Register();
2569}
2570
2571Register fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2572 switch (VT.SimpleTy) {
2573 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op1);
2574 case MVT::v16i8: return fastEmit_ISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op1);
2575 case MVT::v8i16: return fastEmit_ISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op1);
2576 case MVT::v4i32: return fastEmit_ISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op1);
2577 case MVT::v2i64: return fastEmit_ISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op1);
2578 default: return Register();
2579 }
2580}
2581
2582// FastEmit functions for ISD::STRICT_FADD.
2583
2584Register fastEmit_ISD_STRICT_FADD_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
2585 if (RetVT.SimpleTy != MVT::f32)
2586 return Register();
2587 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2588 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_S, RC: &Mips::FGR32RegClass, Op0, Op1);
2589 }
2590 return Register();
2591}
2592
2593Register fastEmit_ISD_STRICT_FADD_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
2594 if (RetVT.SimpleTy != MVT::f64)
2595 return Register();
2596 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2597 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
2598 }
2599 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
2600 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
2601 }
2602 return Register();
2603}
2604
2605Register fastEmit_ISD_STRICT_FADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2606 switch (VT.SimpleTy) {
2607 case MVT::f32: return fastEmit_ISD_STRICT_FADD_MVT_f32_rr(RetVT, Op0, Op1);
2608 case MVT::f64: return fastEmit_ISD_STRICT_FADD_MVT_f64_rr(RetVT, Op0, Op1);
2609 default: return Register();
2610 }
2611}
2612
2613// FastEmit functions for ISD::STRICT_FDIV.
2614
2615Register fastEmit_ISD_STRICT_FDIV_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
2616 if (RetVT.SimpleTy != MVT::f32)
2617 return Register();
2618 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2619 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_S, RC: &Mips::FGR32RegClass, Op0, Op1);
2620 }
2621 return Register();
2622}
2623
2624Register fastEmit_ISD_STRICT_FDIV_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
2625 if (RetVT.SimpleTy != MVT::f64)
2626 return Register();
2627 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2628 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
2629 }
2630 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
2631 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
2632 }
2633 return Register();
2634}
2635
2636Register fastEmit_ISD_STRICT_FDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2637 switch (VT.SimpleTy) {
2638 case MVT::f32: return fastEmit_ISD_STRICT_FDIV_MVT_f32_rr(RetVT, Op0, Op1);
2639 case MVT::f64: return fastEmit_ISD_STRICT_FDIV_MVT_f64_rr(RetVT, Op0, Op1);
2640 default: return Register();
2641 }
2642}
2643
2644// FastEmit functions for ISD::STRICT_FMUL.
2645
2646Register fastEmit_ISD_STRICT_FMUL_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
2647 if (RetVT.SimpleTy != MVT::f32)
2648 return Register();
2649 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2650 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_S, RC: &Mips::FGR32RegClass, Op0, Op1);
2651 }
2652 return Register();
2653}
2654
2655Register fastEmit_ISD_STRICT_FMUL_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
2656 if (RetVT.SimpleTy != MVT::f64)
2657 return Register();
2658 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2659 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
2660 }
2661 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
2662 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
2663 }
2664 return Register();
2665}
2666
2667Register fastEmit_ISD_STRICT_FMUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2668 switch (VT.SimpleTy) {
2669 case MVT::f32: return fastEmit_ISD_STRICT_FMUL_MVT_f32_rr(RetVT, Op0, Op1);
2670 case MVT::f64: return fastEmit_ISD_STRICT_FMUL_MVT_f64_rr(RetVT, Op0, Op1);
2671 default: return Register();
2672 }
2673}
2674
2675// FastEmit functions for ISD::STRICT_FSUB.
2676
2677Register fastEmit_ISD_STRICT_FSUB_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
2678 if (RetVT.SimpleTy != MVT::f32)
2679 return Register();
2680 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2681 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_S, RC: &Mips::FGR32RegClass, Op0, Op1);
2682 }
2683 return Register();
2684}
2685
2686Register fastEmit_ISD_STRICT_FSUB_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
2687 if (RetVT.SimpleTy != MVT::f64)
2688 return Register();
2689 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2690 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
2691 }
2692 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
2693 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
2694 }
2695 return Register();
2696}
2697
2698Register fastEmit_ISD_STRICT_FSUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2699 switch (VT.SimpleTy) {
2700 case MVT::f32: return fastEmit_ISD_STRICT_FSUB_MVT_f32_rr(RetVT, Op0, Op1);
2701 case MVT::f64: return fastEmit_ISD_STRICT_FSUB_MVT_f64_rr(RetVT, Op0, Op1);
2702 default: return Register();
2703 }
2704}
2705
2706// FastEmit functions for ISD::SUB.
2707
2708Register fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2709 if (RetVT.SimpleTy != MVT::i32)
2710 return Register();
2711 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2712 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBU16_MMR6, RC: &Mips::GPRMM16RegClass, Op0, Op1);
2713 }
2714 if ((Subtarget->inMips16Mode())) {
2715 return fastEmitInst_rr(MachineInstOpcode: Mips::SubuRxRyRz16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2716 }
2717 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
2718 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2719 }
2720 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2721 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu, RC: &Mips::GPR32RegClass, Op0, Op1);
2722 }
2723 return Register();
2724}
2725
2726Register fastEmit_ISD_SUB_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2727 if (RetVT.SimpleTy != MVT::i64)
2728 return Register();
2729 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2730 return fastEmitInst_rr(MachineInstOpcode: Mips::DSUBu, RC: &Mips::GPR64RegClass, Op0, Op1);
2731 }
2732 return Register();
2733}
2734
2735Register fastEmit_ISD_SUB_MVT_v4i8_rr(MVT RetVT, Register Op0, Register Op1) {
2736 if (RetVT.SimpleTy != MVT::v4i8)
2737 return Register();
2738 if ((Subtarget->hasDSP())) {
2739 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBU_QB, RC: &Mips::DSPRRegClass, Op0, Op1);
2740 }
2741 return Register();
2742}
2743
2744Register fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2745 if (RetVT.SimpleTy != MVT::v16i8)
2746 return Register();
2747 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2748 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2749 }
2750 return Register();
2751}
2752
2753Register fastEmit_ISD_SUB_MVT_v2i16_rr(MVT RetVT, Register Op0, Register Op1) {
2754 if (RetVT.SimpleTy != MVT::v2i16)
2755 return Register();
2756 if ((Subtarget->hasDSP())) {
2757 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBQ_PH, RC: &Mips::DSPRRegClass, Op0, Op1);
2758 }
2759 return Register();
2760}
2761
2762Register fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2763 if (RetVT.SimpleTy != MVT::v8i16)
2764 return Register();
2765 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2766 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2767 }
2768 return Register();
2769}
2770
2771Register fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2772 if (RetVT.SimpleTy != MVT::v4i32)
2773 return Register();
2774 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2775 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2776 }
2777 return Register();
2778}
2779
2780Register fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2781 if (RetVT.SimpleTy != MVT::v2i64)
2782 return Register();
2783 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2784 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2785 }
2786 return Register();
2787}
2788
2789Register fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2790 switch (VT.SimpleTy) {
2791 case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op1);
2792 case MVT::i64: return fastEmit_ISD_SUB_MVT_i64_rr(RetVT, Op0, Op1);
2793 case MVT::v4i8: return fastEmit_ISD_SUB_MVT_v4i8_rr(RetVT, Op0, Op1);
2794 case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op1);
2795 case MVT::v2i16: return fastEmit_ISD_SUB_MVT_v2i16_rr(RetVT, Op0, Op1);
2796 case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op1);
2797 case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op1);
2798 case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op1);
2799 default: return Register();
2800 }
2801}
2802
2803// FastEmit functions for ISD::SUBC.
2804
2805Register fastEmit_ISD_SUBC_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2806 if (RetVT.SimpleTy != MVT::i32)
2807 return Register();
2808 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2809 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2810 }
2811 if ((Subtarget->inMicroMipsMode())) {
2812 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2813 }
2814 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2815 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu, RC: &Mips::GPR32RegClass, Op0, Op1);
2816 }
2817 return Register();
2818}
2819
2820Register fastEmit_ISD_SUBC_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2821 if (RetVT.SimpleTy != MVT::i64)
2822 return Register();
2823 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())) {
2824 return fastEmitInst_rr(MachineInstOpcode: Mips::DSUBu, RC: &Mips::GPR64RegClass, Op0, Op1);
2825 }
2826 return Register();
2827}
2828
2829Register fastEmit_ISD_SUBC_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2830 switch (VT.SimpleTy) {
2831 case MVT::i32: return fastEmit_ISD_SUBC_MVT_i32_rr(RetVT, Op0, Op1);
2832 case MVT::i64: return fastEmit_ISD_SUBC_MVT_i64_rr(RetVT, Op0, Op1);
2833 default: return Register();
2834 }
2835}
2836
2837// FastEmit functions for ISD::UDIV.
2838
2839Register fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2840 if (RetVT.SimpleTy != MVT::i32)
2841 return Register();
2842 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2843 return fastEmitInst_rr(MachineInstOpcode: Mips::DIVU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2844 }
2845 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2846 return fastEmitInst_rr(MachineInstOpcode: Mips::DIVU, RC: &Mips::GPR32RegClass, Op0, Op1);
2847 }
2848 return Register();
2849}
2850
2851Register fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2852 if (RetVT.SimpleTy != MVT::i64)
2853 return Register();
2854 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2855 return fastEmitInst_rr(MachineInstOpcode: Mips::DDIVU, RC: &Mips::GPR64RegClass, Op0, Op1);
2856 }
2857 return Register();
2858}
2859
2860Register fastEmit_ISD_UDIV_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2861 if (RetVT.SimpleTy != MVT::v16i8)
2862 return Register();
2863 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2864 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2865 }
2866 return Register();
2867}
2868
2869Register fastEmit_ISD_UDIV_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2870 if (RetVT.SimpleTy != MVT::v8i16)
2871 return Register();
2872 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2873 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2874 }
2875 return Register();
2876}
2877
2878Register fastEmit_ISD_UDIV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2879 if (RetVT.SimpleTy != MVT::v4i32)
2880 return Register();
2881 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2882 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2883 }
2884 return Register();
2885}
2886
2887Register fastEmit_ISD_UDIV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2888 if (RetVT.SimpleTy != MVT::v2i64)
2889 return Register();
2890 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2891 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2892 }
2893 return Register();
2894}
2895
2896Register fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2897 switch (VT.SimpleTy) {
2898 case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op1);
2899 case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op1);
2900 case MVT::v16i8: return fastEmit_ISD_UDIV_MVT_v16i8_rr(RetVT, Op0, Op1);
2901 case MVT::v8i16: return fastEmit_ISD_UDIV_MVT_v8i16_rr(RetVT, Op0, Op1);
2902 case MVT::v4i32: return fastEmit_ISD_UDIV_MVT_v4i32_rr(RetVT, Op0, Op1);
2903 case MVT::v2i64: return fastEmit_ISD_UDIV_MVT_v2i64_rr(RetVT, Op0, Op1);
2904 default: return Register();
2905 }
2906}
2907
2908// FastEmit functions for ISD::UMAX.
2909
2910Register fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2911 if (RetVT.SimpleTy != MVT::v16i8)
2912 return Register();
2913 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2914 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2915 }
2916 return Register();
2917}
2918
2919Register fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2920 if (RetVT.SimpleTy != MVT::v8i16)
2921 return Register();
2922 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2923 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2924 }
2925 return Register();
2926}
2927
2928Register fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2929 if (RetVT.SimpleTy != MVT::v4i32)
2930 return Register();
2931 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2932 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2933 }
2934 return Register();
2935}
2936
2937Register fastEmit_ISD_UMAX_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2938 if (RetVT.SimpleTy != MVT::v2i64)
2939 return Register();
2940 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2941 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2942 }
2943 return Register();
2944}
2945
2946Register fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2947 switch (VT.SimpleTy) {
2948 case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
2949 case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
2950 case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
2951 case MVT::v2i64: return fastEmit_ISD_UMAX_MVT_v2i64_rr(RetVT, Op0, Op1);
2952 default: return Register();
2953 }
2954}
2955
2956// FastEmit functions for ISD::UMIN.
2957
2958Register fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2959 if (RetVT.SimpleTy != MVT::v16i8)
2960 return Register();
2961 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2962 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2963 }
2964 return Register();
2965}
2966
2967Register fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2968 if (RetVT.SimpleTy != MVT::v8i16)
2969 return Register();
2970 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2971 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2972 }
2973 return Register();
2974}
2975
2976Register fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2977 if (RetVT.SimpleTy != MVT::v4i32)
2978 return Register();
2979 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2980 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2981 }
2982 return Register();
2983}
2984
2985Register fastEmit_ISD_UMIN_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2986 if (RetVT.SimpleTy != MVT::v2i64)
2987 return Register();
2988 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2989 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2990 }
2991 return Register();
2992}
2993
2994Register fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2995 switch (VT.SimpleTy) {
2996 case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
2997 case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
2998 case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
2999 case MVT::v2i64: return fastEmit_ISD_UMIN_MVT_v2i64_rr(RetVT, Op0, Op1);
3000 default: return Register();
3001 }
3002}
3003
3004// FastEmit functions for ISD::UREM.
3005
3006Register fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3007 if (RetVT.SimpleTy != MVT::i32)
3008 return Register();
3009 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
3010 return fastEmitInst_rr(MachineInstOpcode: Mips::MODU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
3011 }
3012 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3013 return fastEmitInst_rr(MachineInstOpcode: Mips::MODU, RC: &Mips::GPR32RegClass, Op0, Op1);
3014 }
3015 return Register();
3016}
3017
3018Register fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3019 if (RetVT.SimpleTy != MVT::i64)
3020 return Register();
3021 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3022 return fastEmitInst_rr(MachineInstOpcode: Mips::DMODU, RC: &Mips::GPR64RegClass, Op0, Op1);
3023 }
3024 return Register();
3025}
3026
3027Register fastEmit_ISD_UREM_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3028 if (RetVT.SimpleTy != MVT::v16i8)
3029 return Register();
3030 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3031 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3032 }
3033 return Register();
3034}
3035
3036Register fastEmit_ISD_UREM_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3037 if (RetVT.SimpleTy != MVT::v8i16)
3038 return Register();
3039 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3040 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3041 }
3042 return Register();
3043}
3044
3045Register fastEmit_ISD_UREM_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3046 if (RetVT.SimpleTy != MVT::v4i32)
3047 return Register();
3048 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3049 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3050 }
3051 return Register();
3052}
3053
3054Register fastEmit_ISD_UREM_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3055 if (RetVT.SimpleTy != MVT::v2i64)
3056 return Register();
3057 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3058 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3059 }
3060 return Register();
3061}
3062
3063Register fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3064 switch (VT.SimpleTy) {
3065 case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op1);
3066 case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op1);
3067 case MVT::v16i8: return fastEmit_ISD_UREM_MVT_v16i8_rr(RetVT, Op0, Op1);
3068 case MVT::v8i16: return fastEmit_ISD_UREM_MVT_v8i16_rr(RetVT, Op0, Op1);
3069 case MVT::v4i32: return fastEmit_ISD_UREM_MVT_v4i32_rr(RetVT, Op0, Op1);
3070 case MVT::v2i64: return fastEmit_ISD_UREM_MVT_v2i64_rr(RetVT, Op0, Op1);
3071 default: return Register();
3072 }
3073}
3074
3075// FastEmit functions for ISD::XOR.
3076
3077Register fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3078 if (RetVT.SimpleTy != MVT::i32)
3079 return Register();
3080 if ((Subtarget->inMips16Mode())) {
3081 return fastEmitInst_rr(MachineInstOpcode: Mips::XorRxRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
3082 }
3083 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
3084 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
3085 }
3086 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
3087 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
3088 }
3089 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3090 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR, RC: &Mips::GPR32RegClass, Op0, Op1);
3091 }
3092 return Register();
3093}
3094
3095Register fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3096 if (RetVT.SimpleTy != MVT::i64)
3097 return Register();
3098 if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
3099 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR64, RC: &Mips::GPR64RegClass, Op0, Op1);
3100 }
3101 return Register();
3102}
3103
3104Register fastEmit_ISD_XOR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3105 if (RetVT.SimpleTy != MVT::v16i8)
3106 return Register();
3107 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3108 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
3109 }
3110 return Register();
3111}
3112
3113Register fastEmit_ISD_XOR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3114 if (RetVT.SimpleTy != MVT::v8i16)
3115 return Register();
3116 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3117 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
3118 }
3119 return Register();
3120}
3121
3122Register fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3123 if (RetVT.SimpleTy != MVT::v4i32)
3124 return Register();
3125 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3126 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
3127 }
3128 return Register();
3129}
3130
3131Register fastEmit_ISD_XOR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3132 if (RetVT.SimpleTy != MVT::v2i64)
3133 return Register();
3134 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3135 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
3136 }
3137 return Register();
3138}
3139
3140Register fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3141 switch (VT.SimpleTy) {
3142 case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op1);
3143 case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op1);
3144 case MVT::v16i8: return fastEmit_ISD_XOR_MVT_v16i8_rr(RetVT, Op0, Op1);
3145 case MVT::v8i16: return fastEmit_ISD_XOR_MVT_v8i16_rr(RetVT, Op0, Op1);
3146 case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op1);
3147 case MVT::v2i64: return fastEmit_ISD_XOR_MVT_v2i64_rr(RetVT, Op0, Op1);
3148 default: return Register();
3149 }
3150}
3151
3152// FastEmit functions for MipsISD::BuildPairF64.
3153
3154Register fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3155 if (RetVT.SimpleTy != MVT::f64)
3156 return Register();
3157 if ((Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMips16Mode())) {
3158 return fastEmitInst_rr(MachineInstOpcode: Mips::BuildPairF64_64, RC: &Mips::FGR64RegClass, Op0, Op1);
3159 }
3160 if ((!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode())) {
3161 return fastEmitInst_rr(MachineInstOpcode: Mips::BuildPairF64, RC: &Mips::AFGR64RegClass, Op0, Op1);
3162 }
3163 return Register();
3164}
3165
3166Register fastEmit_MipsISD_BuildPairF64_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3167 switch (VT.SimpleTy) {
3168 case MVT::i32: return fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(RetVT, Op0, Op1);
3169 default: return Register();
3170 }
3171}
3172
3173// FastEmit functions for MipsISD::DivRem.
3174
3175Register fastEmit_MipsISD_DivRem_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3176 if (RetVT.SimpleTy != MVT::Untyped)
3177 return Register();
3178 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3179 return fastEmitInst_rr(MachineInstOpcode: Mips::SDIV_MM_Pseudo, RC: &Mips::ACC64RegClass, Op0, Op1);
3180 }
3181 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3182 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoSDIV, RC: &Mips::ACC64RegClass, Op0, Op1);
3183 }
3184 return Register();
3185}
3186
3187Register fastEmit_MipsISD_DivRem_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3188 if (RetVT.SimpleTy != MVT::Untyped)
3189 return Register();
3190 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (!Subtarget->isR5900())) {
3191 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDSDIV, RC: &Mips::ACC128RegClass, Op0, Op1);
3192 }
3193 return Register();
3194}
3195
3196Register fastEmit_MipsISD_DivRem_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3197 switch (VT.SimpleTy) {
3198 case MVT::i32: return fastEmit_MipsISD_DivRem_MVT_i32_rr(RetVT, Op0, Op1);
3199 case MVT::i64: return fastEmit_MipsISD_DivRem_MVT_i64_rr(RetVT, Op0, Op1);
3200 default: return Register();
3201 }
3202}
3203
3204// FastEmit functions for MipsISD::DivRem16.
3205
3206Register fastEmit_MipsISD_DivRem16_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3207 if (RetVT.SimpleTy != MVT::isVoid)
3208 return Register();
3209 if ((Subtarget->inMips16Mode())) {
3210 return fastEmitInst_rr(MachineInstOpcode: Mips::DivRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
3211 }
3212 return Register();
3213}
3214
3215Register fastEmit_MipsISD_DivRem16_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3216 switch (VT.SimpleTy) {
3217 case MVT::i32: return fastEmit_MipsISD_DivRem16_MVT_i32_rr(RetVT, Op0, Op1);
3218 default: return Register();
3219 }
3220}
3221
3222// FastEmit functions for MipsISD::DivRemU.
3223
3224Register fastEmit_MipsISD_DivRemU_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3225 if (RetVT.SimpleTy != MVT::Untyped)
3226 return Register();
3227 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3228 return fastEmitInst_rr(MachineInstOpcode: Mips::UDIV_MM_Pseudo, RC: &Mips::ACC64RegClass, Op0, Op1);
3229 }
3230 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3231 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoUDIV, RC: &Mips::ACC64RegClass, Op0, Op1);
3232 }
3233 return Register();
3234}
3235
3236Register fastEmit_MipsISD_DivRemU_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3237 if (RetVT.SimpleTy != MVT::Untyped)
3238 return Register();
3239 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (!Subtarget->isR5900())) {
3240 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDUDIV, RC: &Mips::ACC128RegClass, Op0, Op1);
3241 }
3242 return Register();
3243}
3244
3245Register fastEmit_MipsISD_DivRemU_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3246 switch (VT.SimpleTy) {
3247 case MVT::i32: return fastEmit_MipsISD_DivRemU_MVT_i32_rr(RetVT, Op0, Op1);
3248 case MVT::i64: return fastEmit_MipsISD_DivRemU_MVT_i64_rr(RetVT, Op0, Op1);
3249 default: return Register();
3250 }
3251}
3252
3253// FastEmit functions for MipsISD::DivRemU16.
3254
3255Register fastEmit_MipsISD_DivRemU16_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3256 if (RetVT.SimpleTy != MVT::isVoid)
3257 return Register();
3258 if ((Subtarget->inMips16Mode())) {
3259 return fastEmitInst_rr(MachineInstOpcode: Mips::DivuRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
3260 }
3261 return Register();
3262}
3263
3264Register fastEmit_MipsISD_DivRemU16_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3265 switch (VT.SimpleTy) {
3266 case MVT::i32: return fastEmit_MipsISD_DivRemU16_MVT_i32_rr(RetVT, Op0, Op1);
3267 default: return Register();
3268 }
3269}
3270
3271// FastEmit functions for MipsISD::EH_RETURN.
3272
3273Register fastEmit_MipsISD_EH_RETURN_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3274 if (RetVT.SimpleTy != MVT::isVoid)
3275 return Register();
3276 return fastEmitInst_rr(MachineInstOpcode: Mips::MIPSeh_return32, RC: &Mips::GPR32RegClass, Op0, Op1);
3277}
3278
3279Register fastEmit_MipsISD_EH_RETURN_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3280 if (RetVT.SimpleTy != MVT::isVoid)
3281 return Register();
3282 return fastEmitInst_rr(MachineInstOpcode: Mips::MIPSeh_return64, RC: &Mips::GPR64RegClass, Op0, Op1);
3283}
3284
3285Register fastEmit_MipsISD_EH_RETURN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3286 switch (VT.SimpleTy) {
3287 case MVT::i32: return fastEmit_MipsISD_EH_RETURN_MVT_i32_rr(RetVT, Op0, Op1);
3288 case MVT::i64: return fastEmit_MipsISD_EH_RETURN_MVT_i64_rr(RetVT, Op0, Op1);
3289 default: return Register();
3290 }
3291}
3292
3293// FastEmit functions for MipsISD::ILVEV.
3294
3295Register fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3296 if (RetVT.SimpleTy != MVT::v16i8)
3297 return Register();
3298 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3299 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3300 }
3301 return Register();
3302}
3303
3304Register fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3305 if (RetVT.SimpleTy != MVT::v8i16)
3306 return Register();
3307 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3308 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3309 }
3310 return Register();
3311}
3312
3313Register fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3314 if (RetVT.SimpleTy != MVT::v4i32)
3315 return Register();
3316 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3317 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3318 }
3319 return Register();
3320}
3321
3322Register fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3323 if (RetVT.SimpleTy != MVT::v2i64)
3324 return Register();
3325 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3326 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3327 }
3328 return Register();
3329}
3330
3331Register fastEmit_MipsISD_ILVEV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3332 switch (VT.SimpleTy) {
3333 case MVT::v16i8: return fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(RetVT, Op0, Op1);
3334 case MVT::v8i16: return fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(RetVT, Op0, Op1);
3335 case MVT::v4i32: return fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(RetVT, Op0, Op1);
3336 case MVT::v2i64: return fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(RetVT, Op0, Op1);
3337 default: return Register();
3338 }
3339}
3340
3341// FastEmit functions for MipsISD::ILVL.
3342
3343Register fastEmit_MipsISD_ILVL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3344 if (RetVT.SimpleTy != MVT::v16i8)
3345 return Register();
3346 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3347 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3348 }
3349 return Register();
3350}
3351
3352Register fastEmit_MipsISD_ILVL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3353 if (RetVT.SimpleTy != MVT::v8i16)
3354 return Register();
3355 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3356 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3357 }
3358 return Register();
3359}
3360
3361Register fastEmit_MipsISD_ILVL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3362 if (RetVT.SimpleTy != MVT::v4i32)
3363 return Register();
3364 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3365 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3366 }
3367 return Register();
3368}
3369
3370Register fastEmit_MipsISD_ILVL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3371 if (RetVT.SimpleTy != MVT::v2i64)
3372 return Register();
3373 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3374 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3375 }
3376 return Register();
3377}
3378
3379Register fastEmit_MipsISD_ILVL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3380 switch (VT.SimpleTy) {
3381 case MVT::v16i8: return fastEmit_MipsISD_ILVL_MVT_v16i8_rr(RetVT, Op0, Op1);
3382 case MVT::v8i16: return fastEmit_MipsISD_ILVL_MVT_v8i16_rr(RetVT, Op0, Op1);
3383 case MVT::v4i32: return fastEmit_MipsISD_ILVL_MVT_v4i32_rr(RetVT, Op0, Op1);
3384 case MVT::v2i64: return fastEmit_MipsISD_ILVL_MVT_v2i64_rr(RetVT, Op0, Op1);
3385 default: return Register();
3386 }
3387}
3388
3389// FastEmit functions for MipsISD::ILVOD.
3390
3391Register fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3392 if (RetVT.SimpleTy != MVT::v16i8)
3393 return Register();
3394 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3395 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3396 }
3397 return Register();
3398}
3399
3400Register fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3401 if (RetVT.SimpleTy != MVT::v8i16)
3402 return Register();
3403 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3404 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3405 }
3406 return Register();
3407}
3408
3409Register fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3410 if (RetVT.SimpleTy != MVT::v4i32)
3411 return Register();
3412 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3413 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3414 }
3415 return Register();
3416}
3417
3418Register fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3419 if (RetVT.SimpleTy != MVT::v2i64)
3420 return Register();
3421 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3422 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3423 }
3424 return Register();
3425}
3426
3427Register fastEmit_MipsISD_ILVOD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3428 switch (VT.SimpleTy) {
3429 case MVT::v16i8: return fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(RetVT, Op0, Op1);
3430 case MVT::v8i16: return fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(RetVT, Op0, Op1);
3431 case MVT::v4i32: return fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(RetVT, Op0, Op1);
3432 case MVT::v2i64: return fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(RetVT, Op0, Op1);
3433 default: return Register();
3434 }
3435}
3436
3437// FastEmit functions for MipsISD::ILVR.
3438
3439Register fastEmit_MipsISD_ILVR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3440 if (RetVT.SimpleTy != MVT::v16i8)
3441 return Register();
3442 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3443 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3444 }
3445 return Register();
3446}
3447
3448Register fastEmit_MipsISD_ILVR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3449 if (RetVT.SimpleTy != MVT::v8i16)
3450 return Register();
3451 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3452 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3453 }
3454 return Register();
3455}
3456
3457Register fastEmit_MipsISD_ILVR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3458 if (RetVT.SimpleTy != MVT::v4i32)
3459 return Register();
3460 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3461 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3462 }
3463 return Register();
3464}
3465
3466Register fastEmit_MipsISD_ILVR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3467 if (RetVT.SimpleTy != MVT::v2i64)
3468 return Register();
3469 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3470 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3471 }
3472 return Register();
3473}
3474
3475Register fastEmit_MipsISD_ILVR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3476 switch (VT.SimpleTy) {
3477 case MVT::v16i8: return fastEmit_MipsISD_ILVR_MVT_v16i8_rr(RetVT, Op0, Op1);
3478 case MVT::v8i16: return fastEmit_MipsISD_ILVR_MVT_v8i16_rr(RetVT, Op0, Op1);
3479 case MVT::v4i32: return fastEmit_MipsISD_ILVR_MVT_v4i32_rr(RetVT, Op0, Op1);
3480 case MVT::v2i64: return fastEmit_MipsISD_ILVR_MVT_v2i64_rr(RetVT, Op0, Op1);
3481 default: return Register();
3482 }
3483}
3484
3485// FastEmit functions for MipsISD::MTLOHI.
3486
3487Register fastEmit_MipsISD_MTLOHI_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3488 if (RetVT.SimpleTy != MVT::Untyped)
3489 return Register();
3490 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
3491 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI_MM, RC: &Mips::ACC64RegClass, Op0, Op1);
3492 }
3493 if ((Subtarget->hasDSP()) && (!Subtarget->inMips16Mode())) {
3494 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI_DSP, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3495 }
3496 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3497 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI, RC: &Mips::ACC64RegClass, Op0, Op1);
3498 }
3499 return Register();
3500}
3501
3502Register fastEmit_MipsISD_MTLOHI_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3503 if (RetVT.SimpleTy != MVT::Untyped)
3504 return Register();
3505 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3506 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI64, RC: &Mips::ACC128RegClass, Op0, Op1);
3507 }
3508 return Register();
3509}
3510
3511Register fastEmit_MipsISD_MTLOHI_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3512 switch (VT.SimpleTy) {
3513 case MVT::i32: return fastEmit_MipsISD_MTLOHI_MVT_i32_rr(RetVT, Op0, Op1);
3514 case MVT::i64: return fastEmit_MipsISD_MTLOHI_MVT_i64_rr(RetVT, Op0, Op1);
3515 default: return Register();
3516 }
3517}
3518
3519// FastEmit functions for MipsISD::Mult.
3520
3521Register fastEmit_MipsISD_Mult_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3522 if (RetVT.SimpleTy != MVT::Untyped)
3523 return Register();
3524 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
3525 return fastEmitInst_rr(MachineInstOpcode: Mips::MULT_DSP_MM, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3526 }
3527 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
3528 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULT_MM, RC: &Mips::ACC64RegClass, Op0, Op1);
3529 }
3530 if ((Subtarget->hasDSP())) {
3531 return fastEmitInst_rr(MachineInstOpcode: Mips::MULT_DSP, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3532 }
3533 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3534 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULT, RC: &Mips::ACC64RegClass, Op0, Op1);
3535 }
3536 return Register();
3537}
3538
3539Register fastEmit_MipsISD_Mult_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3540 if (RetVT.SimpleTy != MVT::Untyped)
3541 return Register();
3542 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (!Subtarget->isR5900())) {
3543 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDMULT, RC: &Mips::ACC128RegClass, Op0, Op1);
3544 }
3545 return Register();
3546}
3547
3548Register fastEmit_MipsISD_Mult_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3549 switch (VT.SimpleTy) {
3550 case MVT::i32: return fastEmit_MipsISD_Mult_MVT_i32_rr(RetVT, Op0, Op1);
3551 case MVT::i64: return fastEmit_MipsISD_Mult_MVT_i64_rr(RetVT, Op0, Op1);
3552 default: return Register();
3553 }
3554}
3555
3556// FastEmit functions for MipsISD::Multu.
3557
3558Register fastEmit_MipsISD_Multu_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3559 if (RetVT.SimpleTy != MVT::Untyped)
3560 return Register();
3561 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
3562 return fastEmitInst_rr(MachineInstOpcode: Mips::MULTU_DSP_MM, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3563 }
3564 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
3565 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULTu_MM, RC: &Mips::ACC64RegClass, Op0, Op1);
3566 }
3567 if ((Subtarget->hasDSP())) {
3568 return fastEmitInst_rr(MachineInstOpcode: Mips::MULTU_DSP, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3569 }
3570 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3571 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULTu, RC: &Mips::ACC64RegClass, Op0, Op1);
3572 }
3573 return Register();
3574}
3575
3576Register fastEmit_MipsISD_Multu_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3577 if (RetVT.SimpleTy != MVT::Untyped)
3578 return Register();
3579 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (!Subtarget->isR5900())) {
3580 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDMULTu, RC: &Mips::ACC128RegClass, Op0, Op1);
3581 }
3582 return Register();
3583}
3584
3585Register fastEmit_MipsISD_Multu_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3586 switch (VT.SimpleTy) {
3587 case MVT::i32: return fastEmit_MipsISD_Multu_MVT_i32_rr(RetVT, Op0, Op1);
3588 case MVT::i64: return fastEmit_MipsISD_Multu_MVT_i64_rr(RetVT, Op0, Op1);
3589 default: return Register();
3590 }
3591}
3592
3593// FastEmit functions for MipsISD::PCKEV.
3594
3595Register fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3596 if (RetVT.SimpleTy != MVT::v16i8)
3597 return Register();
3598 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3599 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3600 }
3601 return Register();
3602}
3603
3604Register fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3605 if (RetVT.SimpleTy != MVT::v8i16)
3606 return Register();
3607 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3608 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3609 }
3610 return Register();
3611}
3612
3613Register fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3614 if (RetVT.SimpleTy != MVT::v4i32)
3615 return Register();
3616 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3617 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3618 }
3619 return Register();
3620}
3621
3622Register fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3623 if (RetVT.SimpleTy != MVT::v2i64)
3624 return Register();
3625 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3626 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3627 }
3628 return Register();
3629}
3630
3631Register fastEmit_MipsISD_PCKEV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3632 switch (VT.SimpleTy) {
3633 case MVT::v16i8: return fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(RetVT, Op0, Op1);
3634 case MVT::v8i16: return fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(RetVT, Op0, Op1);
3635 case MVT::v4i32: return fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(RetVT, Op0, Op1);
3636 case MVT::v2i64: return fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(RetVT, Op0, Op1);
3637 default: return Register();
3638 }
3639}
3640
3641// FastEmit functions for MipsISD::PCKOD.
3642
3643Register fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3644 if (RetVT.SimpleTy != MVT::v16i8)
3645 return Register();
3646 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3647 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3648 }
3649 return Register();
3650}
3651
3652Register fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3653 if (RetVT.SimpleTy != MVT::v8i16)
3654 return Register();
3655 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3656 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3657 }
3658 return Register();
3659}
3660
3661Register fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3662 if (RetVT.SimpleTy != MVT::v4i32)
3663 return Register();
3664 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3665 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3666 }
3667 return Register();
3668}
3669
3670Register fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3671 if (RetVT.SimpleTy != MVT::v2i64)
3672 return Register();
3673 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3674 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3675 }
3676 return Register();
3677}
3678
3679Register fastEmit_MipsISD_PCKOD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3680 switch (VT.SimpleTy) {
3681 case MVT::v16i8: return fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(RetVT, Op0, Op1);
3682 case MVT::v8i16: return fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(RetVT, Op0, Op1);
3683 case MVT::v4i32: return fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(RetVT, Op0, Op1);
3684 case MVT::v2i64: return fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(RetVT, Op0, Op1);
3685 default: return Register();
3686 }
3687}
3688
3689// FastEmit functions for MipsISD::VNOR.
3690
3691Register fastEmit_MipsISD_VNOR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3692 if (RetVT.SimpleTy != MVT::v16i8)
3693 return Register();
3694 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3695 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
3696 }
3697 return Register();
3698}
3699
3700Register fastEmit_MipsISD_VNOR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3701 if (RetVT.SimpleTy != MVT::v8i16)
3702 return Register();
3703 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3704 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
3705 }
3706 return Register();
3707}
3708
3709Register fastEmit_MipsISD_VNOR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3710 if (RetVT.SimpleTy != MVT::v4i32)
3711 return Register();
3712 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3713 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
3714 }
3715 return Register();
3716}
3717
3718Register fastEmit_MipsISD_VNOR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3719 if (RetVT.SimpleTy != MVT::v2i64)
3720 return Register();
3721 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3722 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
3723 }
3724 return Register();
3725}
3726
3727Register fastEmit_MipsISD_VNOR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3728 switch (VT.SimpleTy) {
3729 case MVT::v16i8: return fastEmit_MipsISD_VNOR_MVT_v16i8_rr(RetVT, Op0, Op1);
3730 case MVT::v8i16: return fastEmit_MipsISD_VNOR_MVT_v8i16_rr(RetVT, Op0, Op1);
3731 case MVT::v4i32: return fastEmit_MipsISD_VNOR_MVT_v4i32_rr(RetVT, Op0, Op1);
3732 case MVT::v2i64: return fastEmit_MipsISD_VNOR_MVT_v2i64_rr(RetVT, Op0, Op1);
3733 default: return Register();
3734 }
3735}
3736
3737// Top-level FastEmit function.
3738
3739Register fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, Register Op1) override {
3740 switch (Opcode) {
3741 case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op1);
3742 case ISD::ADDC: return fastEmit_ISD_ADDC_rr(VT, RetVT, Op0, Op1);
3743 case ISD::ADDE: return fastEmit_ISD_ADDE_rr(VT, RetVT, Op0, Op1);
3744 case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op1);
3745 case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op1);
3746 case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op1);
3747 case ISD::FMAXNUM: return fastEmit_ISD_FMAXNUM_rr(VT, RetVT, Op0, Op1);
3748 case ISD::FMAXNUM_IEEE: return fastEmit_ISD_FMAXNUM_IEEE_rr(VT, RetVT, Op0, Op1);
3749 case ISD::FMINNUM: return fastEmit_ISD_FMINNUM_rr(VT, RetVT, Op0, Op1);
3750 case ISD::FMINNUM_IEEE: return fastEmit_ISD_FMINNUM_IEEE_rr(VT, RetVT, Op0, Op1);
3751 case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op1);
3752 case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op1);
3753 case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op1);
3754 case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op1);
3755 case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op1);
3756 case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op1);
3757 case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op1);
3758 case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op1);
3759 case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op1);
3760 case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op1);
3761 case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op1);
3762 case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op1);
3763 case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op1);
3764 case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op1);
3765 case ISD::STRICT_FADD: return fastEmit_ISD_STRICT_FADD_rr(VT, RetVT, Op0, Op1);
3766 case ISD::STRICT_FDIV: return fastEmit_ISD_STRICT_FDIV_rr(VT, RetVT, Op0, Op1);
3767 case ISD::STRICT_FMUL: return fastEmit_ISD_STRICT_FMUL_rr(VT, RetVT, Op0, Op1);
3768 case ISD::STRICT_FSUB: return fastEmit_ISD_STRICT_FSUB_rr(VT, RetVT, Op0, Op1);
3769 case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op1);
3770 case ISD::SUBC: return fastEmit_ISD_SUBC_rr(VT, RetVT, Op0, Op1);
3771 case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op1);
3772 case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op1);
3773 case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op1);
3774 case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op1);
3775 case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op1);
3776 case MipsISD::BuildPairF64: return fastEmit_MipsISD_BuildPairF64_rr(VT, RetVT, Op0, Op1);
3777 case MipsISD::DivRem: return fastEmit_MipsISD_DivRem_rr(VT, RetVT, Op0, Op1);
3778 case MipsISD::DivRem16: return fastEmit_MipsISD_DivRem16_rr(VT, RetVT, Op0, Op1);
3779 case MipsISD::DivRemU: return fastEmit_MipsISD_DivRemU_rr(VT, RetVT, Op0, Op1);
3780 case MipsISD::DivRemU16: return fastEmit_MipsISD_DivRemU16_rr(VT, RetVT, Op0, Op1);
3781 case MipsISD::EH_RETURN: return fastEmit_MipsISD_EH_RETURN_rr(VT, RetVT, Op0, Op1);
3782 case MipsISD::ILVEV: return fastEmit_MipsISD_ILVEV_rr(VT, RetVT, Op0, Op1);
3783 case MipsISD::ILVL: return fastEmit_MipsISD_ILVL_rr(VT, RetVT, Op0, Op1);
3784 case MipsISD::ILVOD: return fastEmit_MipsISD_ILVOD_rr(VT, RetVT, Op0, Op1);
3785 case MipsISD::ILVR: return fastEmit_MipsISD_ILVR_rr(VT, RetVT, Op0, Op1);
3786 case MipsISD::MTLOHI: return fastEmit_MipsISD_MTLOHI_rr(VT, RetVT, Op0, Op1);
3787 case MipsISD::Mult: return fastEmit_MipsISD_Mult_rr(VT, RetVT, Op0, Op1);
3788 case MipsISD::Multu: return fastEmit_MipsISD_Multu_rr(VT, RetVT, Op0, Op1);
3789 case MipsISD::PCKEV: return fastEmit_MipsISD_PCKEV_rr(VT, RetVT, Op0, Op1);
3790 case MipsISD::PCKOD: return fastEmit_MipsISD_PCKOD_rr(VT, RetVT, Op0, Op1);
3791 case MipsISD::VNOR: return fastEmit_MipsISD_VNOR_rr(VT, RetVT, Op0, Op1);
3792 default: return Register();
3793 }
3794}
3795
3796// FastEmit functions for MipsISD::ExtractElementF64.
3797
3798Register fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3799 if (RetVT.SimpleTy != MVT::i32)
3800 return Register();
3801 if ((Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMips16Mode())) {
3802 return fastEmitInst_ri(MachineInstOpcode: Mips::ExtractElementF64_64, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3803 }
3804 if ((!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode())) {
3805 return fastEmitInst_ri(MachineInstOpcode: Mips::ExtractElementF64, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3806 }
3807 return Register();
3808}
3809
3810Register fastEmit_MipsISD_ExtractElementF64_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3811 switch (VT.SimpleTy) {
3812 case MVT::f64: return fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(RetVT, Op0, imm1);
3813 default: return Register();
3814 }
3815}
3816
3817// FastEmit functions for MipsISD::SHLL_DSP.
3818
3819Register fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3820 if (RetVT.SimpleTy != MVT::v4i8)
3821 return Register();
3822 if ((Subtarget->hasDSP())) {
3823 return fastEmitInst_ri(MachineInstOpcode: Mips::SHLL_QB, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3824 }
3825 return Register();
3826}
3827
3828Register fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3829 if (RetVT.SimpleTy != MVT::v2i16)
3830 return Register();
3831 if ((Subtarget->hasDSP())) {
3832 return fastEmitInst_ri(MachineInstOpcode: Mips::SHLL_PH, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3833 }
3834 return Register();
3835}
3836
3837Register fastEmit_MipsISD_SHLL_DSP_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3838 switch (VT.SimpleTy) {
3839 case MVT::v4i8: return fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(RetVT, Op0, imm1);
3840 case MVT::v2i16: return fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(RetVT, Op0, imm1);
3841 default: return Register();
3842 }
3843}
3844
3845// FastEmit functions for MipsISD::SHRA_DSP.
3846
3847Register fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3848 if (RetVT.SimpleTy != MVT::v4i8)
3849 return Register();
3850 if ((Subtarget->hasDSPR2())) {
3851 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRA_QB, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3852 }
3853 return Register();
3854}
3855
3856Register fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3857 if (RetVT.SimpleTy != MVT::v2i16)
3858 return Register();
3859 if ((Subtarget->hasDSP())) {
3860 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRA_PH, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3861 }
3862 return Register();
3863}
3864
3865Register fastEmit_MipsISD_SHRA_DSP_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3866 switch (VT.SimpleTy) {
3867 case MVT::v4i8: return fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(RetVT, Op0, imm1);
3868 case MVT::v2i16: return fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(RetVT, Op0, imm1);
3869 default: return Register();
3870 }
3871}
3872
3873// FastEmit functions for MipsISD::SHRL_DSP.
3874
3875Register fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3876 if (RetVT.SimpleTy != MVT::v4i8)
3877 return Register();
3878 if ((Subtarget->hasDSP())) {
3879 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRL_QB, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3880 }
3881 return Register();
3882}
3883
3884Register fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3885 if (RetVT.SimpleTy != MVT::v2i16)
3886 return Register();
3887 if ((Subtarget->hasDSPR2())) {
3888 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRL_PH, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3889 }
3890 return Register();
3891}
3892
3893Register fastEmit_MipsISD_SHRL_DSP_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3894 switch (VT.SimpleTy) {
3895 case MVT::v4i8: return fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(RetVT, Op0, imm1);
3896 case MVT::v2i16: return fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(RetVT, Op0, imm1);
3897 default: return Register();
3898 }
3899}
3900
3901// Top-level FastEmit function.
3902
3903Register fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) override {
3904 if (VT == MVT::i32 && Predicate_immZExt5(Imm: imm1))
3905 if (Register Reg = fastEmit_ri_Predicate_immZExt5(VT, RetVT, Opcode, Op0, imm1))
3906 return Reg;
3907
3908 if (VT == MVT::i32 && Predicate_immZExt6(Imm: imm1))
3909 if (Register Reg = fastEmit_ri_Predicate_immZExt6(VT, RetVT, Opcode, Op0, imm1))
3910 return Reg;
3911
3912 if (VT == MVT::iPTR && Predicate_immZExt2Ptr(Imm: imm1))
3913 if (Register Reg = fastEmit_ri_Predicate_immZExt2Ptr(VT, RetVT, Opcode, Op0, imm1))
3914 return Reg;
3915
3916 if (VT == MVT::iPTR && Predicate_immZExt1Ptr(Imm: imm1))
3917 if (Register Reg = fastEmit_ri_Predicate_immZExt1Ptr(VT, RetVT, Opcode, Op0, imm1))
3918 return Reg;
3919
3920 if (VT == MVT::i32 && Predicate_immZExt4(Imm: imm1))
3921 if (Register Reg = fastEmit_ri_Predicate_immZExt4(VT, RetVT, Opcode, Op0, imm1))
3922 return Reg;
3923
3924 if (VT == MVT::i32 && Predicate_immSExtAddiur2(Imm: imm1))
3925 if (Register Reg = fastEmit_ri_Predicate_immSExtAddiur2(VT, RetVT, Opcode, Op0, imm1))
3926 return Reg;
3927
3928 if (VT == MVT::i32 && Predicate_immSExtAddius5(Imm: imm1))
3929 if (Register Reg = fastEmit_ri_Predicate_immSExtAddius5(VT, RetVT, Opcode, Op0, imm1))
3930 return Reg;
3931
3932 if (VT == MVT::i32 && Predicate_immZExtAndi16(Imm: imm1))
3933 if (Register Reg = fastEmit_ri_Predicate_immZExtAndi16(VT, RetVT, Opcode, Op0, imm1))
3934 return Reg;
3935
3936 if (VT == MVT::i32 && Predicate_immZExt2Shift(Imm: imm1))
3937 if (Register Reg = fastEmit_ri_Predicate_immZExt2Shift(VT, RetVT, Opcode, Op0, imm1))
3938 return Reg;
3939
3940 switch (Opcode) {
3941 case MipsISD::ExtractElementF64: return fastEmit_MipsISD_ExtractElementF64_ri(VT, RetVT, Op0, imm1);
3942 case MipsISD::SHLL_DSP: return fastEmit_MipsISD_SHLL_DSP_ri(VT, RetVT, Op0, imm1);
3943 case MipsISD::SHRA_DSP: return fastEmit_MipsISD_SHRA_DSP_ri(VT, RetVT, Op0, imm1);
3944 case MipsISD::SHRL_DSP: return fastEmit_MipsISD_SHRL_DSP_ri(VT, RetVT, Op0, imm1);
3945 default: return Register();
3946 }
3947}
3948
3949// FastEmit functions for ISD::ROTR.
3950
3951Register fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, Register Op0, uint64_t imm1) {
3952 if (RetVT.SimpleTy != MVT::i32)
3953 return Register();
3954 if ((Subtarget->inMicroMipsMode())) {
3955 return fastEmitInst_ri(MachineInstOpcode: Mips::ROTR_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3956 }
3957 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3958 return fastEmitInst_ri(MachineInstOpcode: Mips::ROTR, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3959 }
3960 return Register();
3961}
3962
3963Register fastEmit_ISD_ROTR_ri_Predicate_immZExt5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3964 switch (VT.SimpleTy) {
3965 case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
3966 default: return Register();
3967 }
3968}
3969
3970// FastEmit functions for ISD::SHL.
3971
3972Register fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, Register Op0, uint64_t imm1) {
3973 if (RetVT.SimpleTy != MVT::i32)
3974 return Register();
3975 if ((Subtarget->inMicroMipsMode())) {
3976 return fastEmitInst_ri(MachineInstOpcode: Mips::SLL_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3977 }
3978 if ((Subtarget->inMips16Mode())) {
3979 return fastEmitInst_ri(MachineInstOpcode: Mips::SllX16, RC: &Mips::CPU16RegsRegClass, Op0, Imm: imm1);
3980 }
3981 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3982 return fastEmitInst_ri(MachineInstOpcode: Mips::SLL, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3983 }
3984 return Register();
3985}
3986
3987Register fastEmit_ISD_SHL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3988 switch (VT.SimpleTy) {
3989 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
3990 default: return Register();
3991 }
3992}
3993
3994// FastEmit functions for ISD::SRA.
3995
3996Register fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, Register Op0, uint64_t imm1) {
3997 if (RetVT.SimpleTy != MVT::i32)
3998 return Register();
3999 if ((Subtarget->inMicroMipsMode())) {
4000 return fastEmitInst_ri(MachineInstOpcode: Mips::SRA_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
4001 }
4002 if ((Subtarget->inMips16Mode())) {
4003 return fastEmitInst_ri(MachineInstOpcode: Mips::SraX16, RC: &Mips::CPU16RegsRegClass, Op0, Imm: imm1);
4004 }
4005 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
4006 return fastEmitInst_ri(MachineInstOpcode: Mips::SRA, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
4007 }
4008 return Register();
4009}
4010
4011Register fastEmit_ISD_SRA_ri_Predicate_immZExt5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4012 switch (VT.SimpleTy) {
4013 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
4014 default: return Register();
4015 }
4016}
4017
4018// FastEmit functions for ISD::SRL.
4019
4020Register fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, Register Op0, uint64_t imm1) {
4021 if (RetVT.SimpleTy != MVT::i32)
4022 return Register();
4023 if ((Subtarget->inMicroMipsMode())) {
4024 return fastEmitInst_ri(MachineInstOpcode: Mips::SRL_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
4025 }
4026 if ((Subtarget->inMips16Mode())) {
4027 return fastEmitInst_ri(MachineInstOpcode: Mips::SrlX16, RC: &Mips::CPU16RegsRegClass, Op0, Imm: imm1);
4028 }
4029 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
4030 return fastEmitInst_ri(MachineInstOpcode: Mips::SRL, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
4031 }
4032 return Register();
4033}
4034
4035Register fastEmit_ISD_SRL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4036 switch (VT.SimpleTy) {
4037 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
4038 default: return Register();
4039 }
4040}
4041
4042// Top-level FastEmit function.
4043
4044Register fastEmit_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4045 switch (Opcode) {
4046 case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
4047 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
4048 case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
4049 case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
4050 default: return Register();
4051 }
4052}
4053
4054// FastEmit functions for ISD::ROTR.
4055
4056Register fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, Register Op0, uint64_t imm1) {
4057 if (RetVT.SimpleTy != MVT::i64)
4058 return Register();
4059 if ((Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
4060 return fastEmitInst_ri(MachineInstOpcode: Mips::DROTR, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
4061 }
4062 return Register();
4063}
4064
4065Register fastEmit_ISD_ROTR_ri_Predicate_immZExt6(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4066 switch (VT.SimpleTy) {
4067 case MVT::i64: return fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
4068 default: return Register();
4069 }
4070}
4071
4072// FastEmit functions for ISD::SHL.
4073
4074Register fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, Register Op0, uint64_t imm1) {
4075 if (RetVT.SimpleTy != MVT::i64)
4076 return Register();
4077 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
4078 return fastEmitInst_ri(MachineInstOpcode: Mips::DSLL, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
4079 }
4080 return Register();
4081}
4082
4083Register fastEmit_ISD_SHL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4084 switch (VT.SimpleTy) {
4085 case MVT::i64: return fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
4086 default: return Register();
4087 }
4088}
4089
4090// FastEmit functions for ISD::SRA.
4091
4092Register fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, Register Op0, uint64_t imm1) {
4093 if (RetVT.SimpleTy != MVT::i64)
4094 return Register();
4095 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
4096 return fastEmitInst_ri(MachineInstOpcode: Mips::DSRA, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
4097 }
4098 return Register();
4099}
4100
4101Register fastEmit_ISD_SRA_ri_Predicate_immZExt6(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4102 switch (VT.SimpleTy) {
4103 case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
4104 default: return Register();
4105 }
4106}
4107
4108// FastEmit functions for ISD::SRL.
4109
4110Register fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, Register Op0, uint64_t imm1) {
4111 if (RetVT.SimpleTy != MVT::i64)
4112 return Register();
4113 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
4114 return fastEmitInst_ri(MachineInstOpcode: Mips::DSRL, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
4115 }
4116 return Register();
4117}
4118
4119Register fastEmit_ISD_SRL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4120 switch (VT.SimpleTy) {
4121 case MVT::i64: return fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
4122 default: return Register();
4123 }
4124}
4125
4126// Top-level FastEmit function.
4127
4128Register fastEmit_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4129 switch (Opcode) {
4130 case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
4131 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
4132 case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
4133 case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
4134 default: return Register();
4135 }
4136}
4137
4138// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
4139
4140Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(MVT RetVT, Register Op0, uint64_t imm1) {
4141 if (RetVT.SimpleTy != MVT::f32)
4142 return Register();
4143 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
4144 return fastEmitInst_ri(MachineInstOpcode: Mips::COPY_FW_PSEUDO, RC: &Mips::FGR32RegClass, Op0, Imm: imm1);
4145 }
4146 return Register();
4147}
4148
4149Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4150 switch (VT.SimpleTy) {
4151 case MVT::v4f32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(RetVT, Op0, imm1);
4152 default: return Register();
4153 }
4154}
4155
4156// Top-level FastEmit function.
4157
4158Register fastEmit_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4159 switch (Opcode) {
4160 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(VT, RetVT, Op0, imm1);
4161 default: return Register();
4162 }
4163}
4164
4165// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
4166
4167Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(MVT RetVT, Register Op0, uint64_t imm1) {
4168 if (RetVT.SimpleTy != MVT::f64)
4169 return Register();
4170 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
4171 return fastEmitInst_ri(MachineInstOpcode: Mips::COPY_FD_PSEUDO, RC: &Mips::FGR64RegClass, Op0, Imm: imm1);
4172 }
4173 return Register();
4174}
4175
4176Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4177 switch (VT.SimpleTy) {
4178 case MVT::v2f64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(RetVT, Op0, imm1);
4179 default: return Register();
4180 }
4181}
4182
4183// Top-level FastEmit function.
4184
4185Register fastEmit_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4186 switch (Opcode) {
4187 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(VT, RetVT, Op0, imm1);
4188 default: return Register();
4189 }
4190}
4191
4192// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
4193
4194Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(MVT RetVT, Register Op0, uint64_t imm1) {
4195 if (RetVT.SimpleTy != MVT::i32)
4196 return Register();
4197 if ((Subtarget->hasMSA())) {
4198 return fastEmitInst_ri(MachineInstOpcode: Mips::COPY_S_W, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
4199 }
4200 return Register();
4201}
4202
4203Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4204 switch (VT.SimpleTy) {
4205 case MVT::v4i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(RetVT, Op0, imm1);
4206 default: return Register();
4207 }
4208}
4209
4210// Top-level FastEmit function.
4211
4212Register fastEmit_ri_Predicate_immZExt4(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4213 switch (Opcode) {
4214 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(VT, RetVT, Op0, imm1);
4215 default: return Register();
4216 }
4217}
4218
4219// FastEmit functions for ISD::ADD.
4220
4221Register fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(MVT RetVT, Register Op0, uint64_t imm1) {
4222 if (RetVT.SimpleTy != MVT::i32)
4223 return Register();
4224 if ((Subtarget->inMicroMipsMode())) {
4225 return fastEmitInst_ri(MachineInstOpcode: Mips::ADDIUR2_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4226 }
4227 return Register();
4228}
4229
4230Register fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4231 switch (VT.SimpleTy) {
4232 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(RetVT, Op0, imm1);
4233 default: return Register();
4234 }
4235}
4236
4237// Top-level FastEmit function.
4238
4239Register fastEmit_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4240 switch (Opcode) {
4241 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(VT, RetVT, Op0, imm1);
4242 default: return Register();
4243 }
4244}
4245
4246// FastEmit functions for ISD::ADD.
4247
4248Register fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(MVT RetVT, Register Op0, uint64_t imm1) {
4249 if (RetVT.SimpleTy != MVT::i32)
4250 return Register();
4251 if ((Subtarget->inMicroMipsMode())) {
4252 return fastEmitInst_ri(MachineInstOpcode: Mips::ADDIUS5_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
4253 }
4254 return Register();
4255}
4256
4257Register fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4258 switch (VT.SimpleTy) {
4259 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(RetVT, Op0, imm1);
4260 default: return Register();
4261 }
4262}
4263
4264// Top-level FastEmit function.
4265
4266Register fastEmit_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4267 switch (Opcode) {
4268 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(VT, RetVT, Op0, imm1);
4269 default: return Register();
4270 }
4271}
4272
4273// FastEmit functions for ISD::AND.
4274
4275Register fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(MVT RetVT, Register Op0, uint64_t imm1) {
4276 if (RetVT.SimpleTy != MVT::i32)
4277 return Register();
4278 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
4279 return fastEmitInst_ri(MachineInstOpcode: Mips::ANDI16_MMR6, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4280 }
4281 if ((Subtarget->inMicroMipsMode())) {
4282 return fastEmitInst_ri(MachineInstOpcode: Mips::ANDI16_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4283 }
4284 return Register();
4285}
4286
4287Register fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4288 switch (VT.SimpleTy) {
4289 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(RetVT, Op0, imm1);
4290 default: return Register();
4291 }
4292}
4293
4294// Top-level FastEmit function.
4295
4296Register fastEmit_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4297 switch (Opcode) {
4298 case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(VT, RetVT, Op0, imm1);
4299 default: return Register();
4300 }
4301}
4302
4303// FastEmit functions for ISD::SHL.
4304
4305Register fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, Register Op0, uint64_t imm1) {
4306 if (RetVT.SimpleTy != MVT::i32)
4307 return Register();
4308 if ((Subtarget->inMicroMipsMode())) {
4309 return fastEmitInst_ri(MachineInstOpcode: Mips::SLL16_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4310 }
4311 return Register();
4312}
4313
4314Register fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4315 switch (VT.SimpleTy) {
4316 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, imm1);
4317 default: return Register();
4318 }
4319}
4320
4321// FastEmit functions for ISD::SRL.
4322
4323Register fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, Register Op0, uint64_t imm1) {
4324 if (RetVT.SimpleTy != MVT::i32)
4325 return Register();
4326 if ((Subtarget->inMicroMipsMode())) {
4327 return fastEmitInst_ri(MachineInstOpcode: Mips::SRL16_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4328 }
4329 return Register();
4330}
4331
4332Register fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4333 switch (VT.SimpleTy) {
4334 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, imm1);
4335 default: return Register();
4336 }
4337}
4338
4339// Top-level FastEmit function.
4340
4341Register fastEmit_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4342 switch (Opcode) {
4343 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, imm1);
4344 case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, imm1);
4345 default: return Register();
4346 }
4347}
4348
4349// FastEmit functions for ISD::Constant.
4350
4351Register fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) {
4352 if (RetVT.SimpleTy != MVT::i32)
4353 return Register();
4354 if ((Subtarget->inMips16Mode())) {
4355 return fastEmitInst_i(MachineInstOpcode: Mips::LwConstant32, RC: &Mips::CPU16RegsRegClass, Imm: imm0);
4356 }
4357 return Register();
4358}
4359
4360Register fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) {
4361 switch (VT.SimpleTy) {
4362 case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0);
4363 default: return Register();
4364 }
4365}
4366
4367// Top-level FastEmit function.
4368
4369Register fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override {
4370 switch (Opcode) {
4371 case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0);
4372 default: return Register();
4373 }
4374}
4375
4376