1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* "Fast" Instruction Selector for the Mips target *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10// FastEmit Immediate Predicate functions.
11static bool Predicate_immZExt5(int64_t Imm) {
12return Imm == (Imm & 0x1f);
13}
14static bool Predicate_immZExt6(int64_t Imm) {
15return Imm == (Imm & 0x3f);
16}
17static bool Predicate_immSExt6(int64_t Imm) {
18return isInt<6>(x: Imm);
19}
20static bool Predicate_immZExt4Ptr(int64_t Imm) {
21return isUInt<4>(x: Imm);
22}
23static bool Predicate_immZExt3Ptr(int64_t Imm) {
24return isUInt<3>(x: Imm);
25}
26static bool Predicate_immZExt2Ptr(int64_t Imm) {
27return isUInt<2>(x: Imm);
28}
29static bool Predicate_immZExt1Ptr(int64_t Imm) {
30return isUInt<1>(x: Imm);
31}
32static bool Predicate_immZExt4(int64_t Imm) {
33return isUInt<4>(x: Imm);
34}
35static bool Predicate_immSExtAddiur2(int64_t Imm) {
36return Imm == 1 || Imm == -1 ||
37 ((Imm % 4 == 0) &&
38 Imm < 28 && Imm > 0);
39}
40static bool Predicate_immSExtAddius5(int64_t Imm) {
41return Imm >= -8 && Imm <= 7;
42}
43static bool Predicate_immZExtAndi16(int64_t Imm) {
44return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
45 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
46 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
47}
48static bool Predicate_immZExt2Shift(int64_t Imm) {
49return Imm >= 1 && Imm <= 8;
50}
51
52
53// FastEmit functions for ISD::BITCAST.
54
55Register fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, Register Op0) {
56 if (RetVT.SimpleTy != MVT::f32)
57 return Register();
58 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
59 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_MMR6, RC: &Mips::FGR32RegClass, Op0);
60 }
61 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
62 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_MM, RC: &Mips::FGR32RegClass, Op0);
63 }
64 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
65 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1, RC: &Mips::FGR32RegClass, Op0);
66 }
67 return Register();
68}
69
70Register fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, Register Op0) {
71 if (RetVT.SimpleTy != MVT::f64)
72 return Register();
73 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
74 return fastEmitInst_r(MachineInstOpcode: Mips::DMTC1, RC: &Mips::FGR64RegClass, Op0);
75 }
76 return Register();
77}
78
79Register fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, Register Op0) {
80 if (RetVT.SimpleTy != MVT::i32)
81 return Register();
82 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
83 return fastEmitInst_r(MachineInstOpcode: Mips::MFC1_MMR6, RC: &Mips::GPR32RegClass, Op0);
84 }
85 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
86 return fastEmitInst_r(MachineInstOpcode: Mips::MFC1_MM, RC: &Mips::GPR32RegClass, Op0);
87 }
88 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
89 return fastEmitInst_r(MachineInstOpcode: Mips::MFC1, RC: &Mips::GPR32RegClass, Op0);
90 }
91 return Register();
92}
93
94Register fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, Register Op0) {
95 if (RetVT.SimpleTy != MVT::i64)
96 return Register();
97 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
98 return fastEmitInst_r(MachineInstOpcode: Mips::DMFC1, RC: &Mips::GPR64RegClass, Op0);
99 }
100 return Register();
101}
102
103Register fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, Register Op0) {
104 switch (VT.SimpleTy) {
105 case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0);
106 case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0);
107 case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0);
108 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0);
109 default: return Register();
110 }
111}
112
113// FastEmit functions for ISD::BRIND.
114
115Register fastEmit_ISD_BRIND_MVT_i32_r(MVT RetVT, Register Op0) {
116 if (RetVT.SimpleTy != MVT::isVoid)
117 return Register();
118 if ((Subtarget->inMips16Mode())) {
119 return fastEmitInst_r(MachineInstOpcode: Mips::JrcRx16, RC: &Mips::CPU16RegsRegClass, Op0);
120 }
121 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
122 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranch_MMR6, RC: &Mips::GPR32RegClass, Op0);
123 }
124 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
125 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranch_MM, RC: &Mips::GPR32RegClass, Op0);
126 }
127 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
128 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndrectHazardBranchR6, RC: &Mips::GPR32RegClass, Op0);
129 }
130 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
131 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranchR6, RC: &Mips::GPR32RegClass, Op0);
132 }
133 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
134 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectHazardBranch, RC: &Mips::GPR32RegClass, Op0);
135 }
136 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
137 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranch, RC: &Mips::GPR32RegClass, Op0);
138 }
139 return Register();
140}
141
142Register fastEmit_ISD_BRIND_MVT_i64_r(MVT RetVT, Register Op0) {
143 if (RetVT.SimpleTy != MVT::isVoid)
144 return Register();
145 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
146 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndrectHazardBranch64R6, RC: &Mips::GPR64RegClass, Op0);
147 }
148 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
149 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranch64R6, RC: &Mips::GPR64RegClass, Op0);
150 }
151 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
152 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectHazardBranch64, RC: &Mips::GPR64RegClass, Op0);
153 }
154 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
155 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranch64, RC: &Mips::GPR64RegClass, Op0);
156 }
157 return Register();
158}
159
160Register fastEmit_ISD_BRIND_r(MVT VT, MVT RetVT, Register Op0) {
161 switch (VT.SimpleTy) {
162 case MVT::i32: return fastEmit_ISD_BRIND_MVT_i32_r(RetVT, Op0);
163 case MVT::i64: return fastEmit_ISD_BRIND_MVT_i64_r(RetVT, Op0);
164 default: return Register();
165 }
166}
167
168// FastEmit functions for ISD::CTLZ.
169
170Register fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, Register Op0) {
171 if (RetVT.SimpleTy != MVT::i32)
172 return Register();
173 if ((Subtarget->inMicroMipsMode())) {
174 return fastEmitInst_r(MachineInstOpcode: Mips::CLZ_MM, RC: &Mips::GPR32RegClass, Op0);
175 }
176 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding())) {
177 return fastEmitInst_r(MachineInstOpcode: Mips::CLZ_R6, RC: &Mips::GPR32RegClass, Op0);
178 }
179 if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
180 return fastEmitInst_r(MachineInstOpcode: Mips::CLZ, RC: &Mips::GPR32RegClass, Op0);
181 }
182 return Register();
183}
184
185Register fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, Register Op0) {
186 if (RetVT.SimpleTy != MVT::i64)
187 return Register();
188 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
189 return fastEmitInst_r(MachineInstOpcode: Mips::DCLZ_R6, RC: &Mips::GPR64RegClass, Op0);
190 }
191 if ((Subtarget->hasMips64()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips64r6())) {
192 return fastEmitInst_r(MachineInstOpcode: Mips::DCLZ, RC: &Mips::GPR64RegClass, Op0);
193 }
194 return Register();
195}
196
197Register fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, Register Op0) {
198 if (RetVT.SimpleTy != MVT::v16i8)
199 return Register();
200 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
201 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_B, RC: &Mips::MSA128BRegClass, Op0);
202 }
203 return Register();
204}
205
206Register fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, Register Op0) {
207 if (RetVT.SimpleTy != MVT::v8i16)
208 return Register();
209 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
210 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_H, RC: &Mips::MSA128HRegClass, Op0);
211 }
212 return Register();
213}
214
215Register fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, Register Op0) {
216 if (RetVT.SimpleTy != MVT::v4i32)
217 return Register();
218 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
219 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_W, RC: &Mips::MSA128WRegClass, Op0);
220 }
221 return Register();
222}
223
224Register fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, Register Op0) {
225 if (RetVT.SimpleTy != MVT::v2i64)
226 return Register();
227 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
228 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_D, RC: &Mips::MSA128DRegClass, Op0);
229 }
230 return Register();
231}
232
233Register fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, Register Op0) {
234 switch (VT.SimpleTy) {
235 case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0);
236 case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0);
237 case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0);
238 case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0);
239 case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0);
240 case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0);
241 default: return Register();
242 }
243}
244
245// FastEmit functions for ISD::CTPOP.
246
247Register fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, Register Op0) {
248 if (RetVT.SimpleTy != MVT::i32)
249 return Register();
250 if ((Subtarget->hasCnMips())) {
251 return fastEmitInst_r(MachineInstOpcode: Mips::POP, RC: &Mips::GPR32RegClass, Op0);
252 }
253 return Register();
254}
255
256Register fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, Register Op0) {
257 if (RetVT.SimpleTy != MVT::i64)
258 return Register();
259 if ((Subtarget->hasCnMips())) {
260 return fastEmitInst_r(MachineInstOpcode: Mips::DPOP, RC: &Mips::GPR64RegClass, Op0);
261 }
262 return Register();
263}
264
265Register fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, Register Op0) {
266 if (RetVT.SimpleTy != MVT::v16i8)
267 return Register();
268 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
269 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_B, RC: &Mips::MSA128BRegClass, Op0);
270 }
271 return Register();
272}
273
274Register fastEmit_ISD_CTPOP_MVT_v8i16_r(MVT RetVT, Register Op0) {
275 if (RetVT.SimpleTy != MVT::v8i16)
276 return Register();
277 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
278 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_H, RC: &Mips::MSA128HRegClass, Op0);
279 }
280 return Register();
281}
282
283Register fastEmit_ISD_CTPOP_MVT_v4i32_r(MVT RetVT, Register Op0) {
284 if (RetVT.SimpleTy != MVT::v4i32)
285 return Register();
286 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
287 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_W, RC: &Mips::MSA128WRegClass, Op0);
288 }
289 return Register();
290}
291
292Register fastEmit_ISD_CTPOP_MVT_v2i64_r(MVT RetVT, Register Op0) {
293 if (RetVT.SimpleTy != MVT::v2i64)
294 return Register();
295 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
296 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_D, RC: &Mips::MSA128DRegClass, Op0);
297 }
298 return Register();
299}
300
301Register fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, Register Op0) {
302 switch (VT.SimpleTy) {
303 case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0);
304 case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0);
305 case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0);
306 case MVT::v8i16: return fastEmit_ISD_CTPOP_MVT_v8i16_r(RetVT, Op0);
307 case MVT::v4i32: return fastEmit_ISD_CTPOP_MVT_v4i32_r(RetVT, Op0);
308 case MVT::v2i64: return fastEmit_ISD_CTPOP_MVT_v2i64_r(RetVT, Op0);
309 default: return Register();
310 }
311}
312
313// FastEmit functions for ISD::FABS.
314
315Register fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, Register Op0) {
316 if (RetVT.SimpleTy != MVT::f32)
317 return Register();
318 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
319 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_S_MM, RC: &Mips::FGR32RegClass, Op0);
320 }
321 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
322 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_S, RC: &Mips::FGR32RegClass, Op0);
323 }
324 return Register();
325}
326
327Register fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, Register Op0) {
328 if (RetVT.SimpleTy != MVT::f64)
329 return Register();
330 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
331 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D64_MM, RC: &Mips::FGR64RegClass, Op0);
332 }
333 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
334 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D32_MM, RC: &Mips::AFGR64RegClass, Op0);
335 }
336 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
337 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D64, RC: &Mips::FGR64RegClass, Op0);
338 }
339 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
340 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D32, RC: &Mips::AFGR64RegClass, Op0);
341 }
342 return Register();
343}
344
345Register fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, Register Op0) {
346 if (RetVT.SimpleTy != MVT::v4f32)
347 return Register();
348 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
349 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_W, RC: &Mips::MSA128WRegClass, Op0);
350 }
351 return Register();
352}
353
354Register fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, Register Op0) {
355 if (RetVT.SimpleTy != MVT::v2f64)
356 return Register();
357 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
358 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D, RC: &Mips::MSA128DRegClass, Op0);
359 }
360 return Register();
361}
362
363Register fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, Register Op0) {
364 switch (VT.SimpleTy) {
365 case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0);
366 case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0);
367 case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0);
368 case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0);
369 default: return Register();
370 }
371}
372
373// FastEmit functions for ISD::FEXP2.
374
375Register fastEmit_ISD_FEXP2_MVT_v4f32_r(MVT RetVT, Register Op0) {
376 if (RetVT.SimpleTy != MVT::v4f32)
377 return Register();
378 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
379 return fastEmitInst_r(MachineInstOpcode: Mips::FEXP2_W_1_PSEUDO, RC: &Mips::MSA128WRegClass, Op0);
380 }
381 return Register();
382}
383
384Register fastEmit_ISD_FEXP2_MVT_v2f64_r(MVT RetVT, Register Op0) {
385 if (RetVT.SimpleTy != MVT::v2f64)
386 return Register();
387 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
388 return fastEmitInst_r(MachineInstOpcode: Mips::FEXP2_D_1_PSEUDO, RC: &Mips::MSA128DRegClass, Op0);
389 }
390 return Register();
391}
392
393Register fastEmit_ISD_FEXP2_r(MVT VT, MVT RetVT, Register Op0) {
394 switch (VT.SimpleTy) {
395 case MVT::v4f32: return fastEmit_ISD_FEXP2_MVT_v4f32_r(RetVT, Op0);
396 case MVT::v2f64: return fastEmit_ISD_FEXP2_MVT_v2f64_r(RetVT, Op0);
397 default: return Register();
398 }
399}
400
401// FastEmit functions for ISD::FLOG2.
402
403Register fastEmit_ISD_FLOG2_MVT_v4f32_r(MVT RetVT, Register Op0) {
404 if (RetVT.SimpleTy != MVT::v4f32)
405 return Register();
406 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
407 return fastEmitInst_r(MachineInstOpcode: Mips::FLOG2_W, RC: &Mips::MSA128WRegClass, Op0);
408 }
409 return Register();
410}
411
412Register fastEmit_ISD_FLOG2_MVT_v2f64_r(MVT RetVT, Register Op0) {
413 if (RetVT.SimpleTy != MVT::v2f64)
414 return Register();
415 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
416 return fastEmitInst_r(MachineInstOpcode: Mips::FLOG2_D, RC: &Mips::MSA128DRegClass, Op0);
417 }
418 return Register();
419}
420
421Register fastEmit_ISD_FLOG2_r(MVT VT, MVT RetVT, Register Op0) {
422 switch (VT.SimpleTy) {
423 case MVT::v4f32: return fastEmit_ISD_FLOG2_MVT_v4f32_r(RetVT, Op0);
424 case MVT::v2f64: return fastEmit_ISD_FLOG2_MVT_v2f64_r(RetVT, Op0);
425 default: return Register();
426 }
427}
428
429// FastEmit functions for ISD::FNEG.
430
431Register fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, Register Op0) {
432 if (RetVT.SimpleTy != MVT::f32)
433 return Register();
434 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
435 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_S_MMR6, RC: &Mips::FGR32RegClass, Op0);
436 }
437 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
438 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_S_MM, RC: &Mips::FGR32RegClass, Op0);
439 }
440 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
441 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_S, RC: &Mips::FGR32RegClass, Op0);
442 }
443 return Register();
444}
445
446Register fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, Register Op0) {
447 if (RetVT.SimpleTy != MVT::f64)
448 return Register();
449 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
450 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D64_MM, RC: &Mips::FGR64RegClass, Op0);
451 }
452 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
453 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D32_MM, RC: &Mips::AFGR64RegClass, Op0);
454 }
455 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
456 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D64, RC: &Mips::FGR64RegClass, Op0);
457 }
458 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
459 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D32, RC: &Mips::AFGR64RegClass, Op0);
460 }
461 return Register();
462}
463
464Register fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, Register Op0) {
465 switch (VT.SimpleTy) {
466 case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0);
467 case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0);
468 default: return Register();
469 }
470}
471
472// FastEmit functions for ISD::FP_EXTEND.
473
474Register fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, Register Op0) {
475 if (RetVT.SimpleTy != MVT::f64)
476 return Register();
477 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) {
478 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D32_S_MM, RC: &Mips::AFGR64RegClass, Op0);
479 }
480 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
481 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D64_S_MM, RC: &Mips::FGR64RegClass, Op0);
482 }
483 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->inMicroMipsMode())) {
484 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D64_S, RC: &Mips::FGR64RegClass, Op0);
485 }
486 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
487 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D32_S, RC: &Mips::AFGR64RegClass, Op0);
488 }
489 return Register();
490}
491
492Register fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
493 switch (VT.SimpleTy) {
494 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0);
495 default: return Register();
496 }
497}
498
499// FastEmit functions for ISD::FP_ROUND.
500
501Register fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, Register Op0) {
502 if (RetVT.SimpleTy != MVT::f32)
503 return Register();
504 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) {
505 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D32_MM, RC: &Mips::FGR32RegClass, Op0);
506 }
507 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
508 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D64_MM, RC: &Mips::FGR32RegClass, Op0);
509 }
510 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->inMicroMipsMode())) {
511 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D64, RC: &Mips::FGR32RegClass, Op0);
512 }
513 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
514 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D32, RC: &Mips::FGR32RegClass, Op0);
515 }
516 return Register();
517}
518
519Register fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, Register Op0) {
520 switch (VT.SimpleTy) {
521 case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0);
522 default: return Register();
523 }
524}
525
526// FastEmit functions for ISD::FP_TO_SINT.
527
528Register fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
529 if (RetVT.SimpleTy != MVT::v4i32)
530 return Register();
531 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
532 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_S_W, RC: &Mips::MSA128WRegClass, Op0);
533 }
534 return Register();
535}
536
537Register fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
538 if (RetVT.SimpleTy != MVT::v2i64)
539 return Register();
540 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
541 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_S_D, RC: &Mips::MSA128DRegClass, Op0);
542 }
543 return Register();
544}
545
546Register fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, Register Op0) {
547 switch (VT.SimpleTy) {
548 case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0);
549 case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0);
550 default: return Register();
551 }
552}
553
554// FastEmit functions for ISD::FP_TO_UINT.
555
556Register fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
557 if (RetVT.SimpleTy != MVT::v4i32)
558 return Register();
559 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
560 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_U_W, RC: &Mips::MSA128WRegClass, Op0);
561 }
562 return Register();
563}
564
565Register fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
566 if (RetVT.SimpleTy != MVT::v2i64)
567 return Register();
568 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
569 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_U_D, RC: &Mips::MSA128DRegClass, Op0);
570 }
571 return Register();
572}
573
574Register fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, Register Op0) {
575 switch (VT.SimpleTy) {
576 case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0);
577 case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0);
578 default: return Register();
579 }
580}
581
582// FastEmit functions for ISD::FRINT.
583
584Register fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
585 if (RetVT.SimpleTy != MVT::v4f32)
586 return Register();
587 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
588 return fastEmitInst_r(MachineInstOpcode: Mips::FRINT_W, RC: &Mips::MSA128WRegClass, Op0);
589 }
590 return Register();
591}
592
593Register fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
594 if (RetVT.SimpleTy != MVT::v2f64)
595 return Register();
596 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
597 return fastEmitInst_r(MachineInstOpcode: Mips::FRINT_D, RC: &Mips::MSA128DRegClass, Op0);
598 }
599 return Register();
600}
601
602Register fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, Register Op0) {
603 switch (VT.SimpleTy) {
604 case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0);
605 case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0);
606 default: return Register();
607 }
608}
609
610// FastEmit functions for ISD::FSQRT.
611
612Register fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, Register Op0) {
613 if (RetVT.SimpleTy != MVT::f32)
614 return Register();
615 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
616 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_S_MM, RC: &Mips::FGR32RegClass, Op0);
617 }
618 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
619 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_S, RC: &Mips::FGR32RegClass, Op0);
620 }
621 return Register();
622}
623
624Register fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, Register Op0) {
625 if (RetVT.SimpleTy != MVT::f64)
626 return Register();
627 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
628 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D64_MM, RC: &Mips::FGR64RegClass, Op0);
629 }
630 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
631 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D32_MM, RC: &Mips::AFGR64RegClass, Op0);
632 }
633 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
634 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D64, RC: &Mips::FGR64RegClass, Op0);
635 }
636 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
637 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D32, RC: &Mips::AFGR64RegClass, Op0);
638 }
639 return Register();
640}
641
642Register fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, Register Op0) {
643 if (RetVT.SimpleTy != MVT::v4f32)
644 return Register();
645 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
646 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_W, RC: &Mips::MSA128WRegClass, Op0);
647 }
648 return Register();
649}
650
651Register fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, Register Op0) {
652 if (RetVT.SimpleTy != MVT::v2f64)
653 return Register();
654 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
655 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D, RC: &Mips::MSA128DRegClass, Op0);
656 }
657 return Register();
658}
659
660Register fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, Register Op0) {
661 switch (VT.SimpleTy) {
662 case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0);
663 case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0);
664 case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0);
665 case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0);
666 default: return Register();
667 }
668}
669
670// FastEmit functions for ISD::SIGN_EXTEND.
671
672Register fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, Register Op0) {
673 if (RetVT.SimpleTy != MVT::i64)
674 return Register();
675 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())) {
676 return fastEmitInst_r(MachineInstOpcode: Mips::SLL64_32, RC: &Mips::GPR64RegClass, Op0);
677 }
678 return Register();
679}
680
681Register fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
682 switch (VT.SimpleTy) {
683 case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0);
684 default: return Register();
685 }
686}
687
688// FastEmit functions for ISD::SINT_TO_FP.
689
690Register fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
691 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_S_W, RC: &Mips::FGR32RegClass, Op0);
692}
693
694Register fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
695 if ((Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
696 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D64_W, RC: &Mips::FGR64RegClass, Op0);
697 }
698 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) {
699 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D32_W, RC: &Mips::AFGR64RegClass, Op0);
700 }
701 return Register();
702}
703
704Register fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
705switch (RetVT.SimpleTy) {
706 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
707 case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
708 default: return Register();
709}
710}
711
712Register fastEmit_ISD_SINT_TO_FP_MVT_i64_r(MVT RetVT, Register Op0) {
713 if (RetVT.SimpleTy != MVT::f64)
714 return Register();
715 if ((Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
716 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D64_L, RC: &Mips::FGR64RegClass, Op0);
717 }
718 return Register();
719}
720
721Register fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
722 if (RetVT.SimpleTy != MVT::v4f32)
723 return Register();
724 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
725 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_S_W, RC: &Mips::MSA128WRegClass, Op0);
726 }
727 return Register();
728}
729
730Register fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, Register Op0) {
731 if (RetVT.SimpleTy != MVT::v2f64)
732 return Register();
733 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
734 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_S_D, RC: &Mips::MSA128DRegClass, Op0);
735 }
736 return Register();
737}
738
739Register fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
740 switch (VT.SimpleTy) {
741 case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0);
742 case MVT::i64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_r(RetVT, Op0);
743 case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
744 case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
745 default: return Register();
746 }
747}
748
749// FastEmit functions for ISD::STRICT_FP_EXTEND.
750
751Register fastEmit_ISD_STRICT_FP_EXTEND_MVT_f32_r(MVT RetVT, Register Op0) {
752 if (RetVT.SimpleTy != MVT::f64)
753 return Register();
754 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->inMicroMipsMode())) {
755 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D64_S, RC: &Mips::FGR64RegClass, Op0);
756 }
757 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
758 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D32_S, RC: &Mips::AFGR64RegClass, Op0);
759 }
760 return Register();
761}
762
763Register fastEmit_ISD_STRICT_FP_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
764 switch (VT.SimpleTy) {
765 case MVT::f32: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_f32_r(RetVT, Op0);
766 default: return Register();
767 }
768}
769
770// FastEmit functions for ISD::STRICT_FP_ROUND.
771
772Register fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(MVT RetVT, Register Op0) {
773 if (RetVT.SimpleTy != MVT::f32)
774 return Register();
775 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->inMicroMipsMode())) {
776 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D64, RC: &Mips::FGR32RegClass, Op0);
777 }
778 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
779 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D32, RC: &Mips::FGR32RegClass, Op0);
780 }
781 return Register();
782}
783
784Register fastEmit_ISD_STRICT_FP_ROUND_r(MVT VT, MVT RetVT, Register Op0) {
785 switch (VT.SimpleTy) {
786 case MVT::f64: return fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(RetVT, Op0);
787 default: return Register();
788 }
789}
790
791// FastEmit functions for ISD::STRICT_FSQRT.
792
793Register fastEmit_ISD_STRICT_FSQRT_MVT_f32_r(MVT RetVT, Register Op0) {
794 if (RetVT.SimpleTy != MVT::f32)
795 return Register();
796 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
797 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_S, RC: &Mips::FGR32RegClass, Op0);
798 }
799 return Register();
800}
801
802Register fastEmit_ISD_STRICT_FSQRT_MVT_f64_r(MVT RetVT, Register Op0) {
803 if (RetVT.SimpleTy != MVT::f64)
804 return Register();
805 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
806 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D64, RC: &Mips::FGR64RegClass, Op0);
807 }
808 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
809 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D32, RC: &Mips::AFGR64RegClass, Op0);
810 }
811 return Register();
812}
813
814Register fastEmit_ISD_STRICT_FSQRT_r(MVT VT, MVT RetVT, Register Op0) {
815 switch (VT.SimpleTy) {
816 case MVT::f32: return fastEmit_ISD_STRICT_FSQRT_MVT_f32_r(RetVT, Op0);
817 case MVT::f64: return fastEmit_ISD_STRICT_FSQRT_MVT_f64_r(RetVT, Op0);
818 default: return Register();
819 }
820}
821
822// FastEmit functions for ISD::STRICT_SINT_TO_FP.
823
824Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
825 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_S_W, RC: &Mips::FGR32RegClass, Op0);
826}
827
828Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
829 if ((Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
830 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D64_W, RC: &Mips::FGR64RegClass, Op0);
831 }
832 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) {
833 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D32_W, RC: &Mips::AFGR64RegClass, Op0);
834 }
835 return Register();
836}
837
838Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
839switch (RetVT.SimpleTy) {
840 case MVT::f32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
841 case MVT::f64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
842 default: return Register();
843}
844}
845
846Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_r(MVT RetVT, Register Op0) {
847 if (RetVT.SimpleTy != MVT::f64)
848 return Register();
849 if ((Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
850 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D64_L, RC: &Mips::FGR64RegClass, Op0);
851 }
852 return Register();
853}
854
855Register fastEmit_ISD_STRICT_SINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
856 switch (VT.SimpleTy) {
857 case MVT::i32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(RetVT, Op0);
858 case MVT::i64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_r(RetVT, Op0);
859 default: return Register();
860 }
861}
862
863// FastEmit functions for ISD::UINT_TO_FP.
864
865Register fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
866 if (RetVT.SimpleTy != MVT::v4f32)
867 return Register();
868 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
869 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_U_W, RC: &Mips::MSA128WRegClass, Op0);
870 }
871 return Register();
872}
873
874Register fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, Register Op0) {
875 if (RetVT.SimpleTy != MVT::v2f64)
876 return Register();
877 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
878 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_U_D, RC: &Mips::MSA128DRegClass, Op0);
879 }
880 return Register();
881}
882
883Register fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
884 switch (VT.SimpleTy) {
885 case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
886 case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
887 default: return Register();
888 }
889}
890
891// FastEmit functions for MipsISD::JmpLink.
892
893Register fastEmit_MipsISD_JmpLink_MVT_i32_r(MVT RetVT, Register Op0) {
894 if (RetVT.SimpleTy != MVT::isVoid)
895 return Register();
896 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
897 return fastEmitInst_r(MachineInstOpcode: Mips::JALR16_MM, RC: &Mips::GPR32RegClass, Op0);
898 }
899 if ((Subtarget->inMips16Mode())) {
900 return fastEmitInst_r(MachineInstOpcode: Mips::JumpLinkReg16, RC: &Mips::CPU16RegsRegClass, Op0);
901 }
902 if ((!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
903 return fastEmitInst_r(MachineInstOpcode: Mips::JALRHBPseudo, RC: &Mips::GPR32RegClass, Op0);
904 }
905 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode())) {
906 return fastEmitInst_r(MachineInstOpcode: Mips::JALRPseudo, RC: &Mips::GPR32RegClass, Op0);
907 }
908 return Register();
909}
910
911Register fastEmit_MipsISD_JmpLink_MVT_i64_r(MVT RetVT, Register Op0) {
912 if (RetVT.SimpleTy != MVT::isVoid)
913 return Register();
914 if ((Subtarget->isABI_N64()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
915 return fastEmitInst_r(MachineInstOpcode: Mips::JALRHB64Pseudo, RC: &Mips::GPR64RegClass, Op0);
916 }
917 if ((Subtarget->isABI_N64()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMips16Mode())) {
918 return fastEmitInst_r(MachineInstOpcode: Mips::JALR64Pseudo, RC: &Mips::GPR64RegClass, Op0);
919 }
920 return Register();
921}
922
923Register fastEmit_MipsISD_JmpLink_r(MVT VT, MVT RetVT, Register Op0) {
924 switch (VT.SimpleTy) {
925 case MVT::i32: return fastEmit_MipsISD_JmpLink_MVT_i32_r(RetVT, Op0);
926 case MVT::i64: return fastEmit_MipsISD_JmpLink_MVT_i64_r(RetVT, Op0);
927 default: return Register();
928 }
929}
930
931// FastEmit functions for MipsISD::MFHI.
932
933Register fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(Register Op0) {
934 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
935 return fastEmitInst_r(MachineInstOpcode: Mips::MFHI_DSP_MM, RC: &Mips::GPR32RegClass, Op0);
936 }
937 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
938 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFHI_MM, RC: &Mips::GPR32RegClass, Op0);
939 }
940 if ((Subtarget->hasDSP())) {
941 return fastEmitInst_r(MachineInstOpcode: Mips::MFHI_DSP, RC: &Mips::GPR32RegClass, Op0);
942 }
943 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
944 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFHI, RC: &Mips::GPR32RegClass, Op0);
945 }
946 return Register();
947}
948
949Register fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(Register Op0) {
950 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
951 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFHI64, RC: &Mips::GPR64RegClass, Op0);
952 }
953 return Register();
954}
955
956Register fastEmit_MipsISD_MFHI_MVT_Untyped_r(MVT RetVT, Register Op0) {
957switch (RetVT.SimpleTy) {
958 case MVT::i32: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(Op0);
959 case MVT::i64: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(Op0);
960 default: return Register();
961}
962}
963
964Register fastEmit_MipsISD_MFHI_r(MVT VT, MVT RetVT, Register Op0) {
965 switch (VT.SimpleTy) {
966 case MVT::Untyped: return fastEmit_MipsISD_MFHI_MVT_Untyped_r(RetVT, Op0);
967 default: return Register();
968 }
969}
970
971// FastEmit functions for MipsISD::MFLO.
972
973Register fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(Register Op0) {
974 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
975 return fastEmitInst_r(MachineInstOpcode: Mips::MFLO_DSP_MM, RC: &Mips::GPR32RegClass, Op0);
976 }
977 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
978 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFLO_MM, RC: &Mips::GPR32RegClass, Op0);
979 }
980 if ((Subtarget->hasDSP())) {
981 return fastEmitInst_r(MachineInstOpcode: Mips::MFLO_DSP, RC: &Mips::GPR32RegClass, Op0);
982 }
983 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
984 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFLO, RC: &Mips::GPR32RegClass, Op0);
985 }
986 return Register();
987}
988
989Register fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(Register Op0) {
990 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
991 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFLO64, RC: &Mips::GPR64RegClass, Op0);
992 }
993 return Register();
994}
995
996Register fastEmit_MipsISD_MFLO_MVT_Untyped_r(MVT RetVT, Register Op0) {
997switch (RetVT.SimpleTy) {
998 case MVT::i32: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(Op0);
999 case MVT::i64: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(Op0);
1000 default: return Register();
1001}
1002}
1003
1004Register fastEmit_MipsISD_MFLO_r(MVT VT, MVT RetVT, Register Op0) {
1005 switch (VT.SimpleTy) {
1006 case MVT::Untyped: return fastEmit_MipsISD_MFLO_MVT_Untyped_r(RetVT, Op0);
1007 default: return Register();
1008 }
1009}
1010
1011// FastEmit functions for MipsISD::MTC1_D64.
1012
1013Register fastEmit_MipsISD_MTC1_D64_MVT_i32_r(MVT RetVT, Register Op0) {
1014 if (RetVT.SimpleTy != MVT::f64)
1015 return Register();
1016 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
1017 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_D64_MM, RC: &Mips::FGR64RegClass, Op0);
1018 }
1019 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
1020 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_D64, RC: &Mips::FGR64RegClass, Op0);
1021 }
1022 return Register();
1023}
1024
1025Register fastEmit_MipsISD_MTC1_D64_r(MVT VT, MVT RetVT, Register Op0) {
1026 switch (VT.SimpleTy) {
1027 case MVT::i32: return fastEmit_MipsISD_MTC1_D64_MVT_i32_r(RetVT, Op0);
1028 default: return Register();
1029 }
1030}
1031
1032// FastEmit functions for MipsISD::TailCall.
1033
1034Register fastEmit_MipsISD_TailCall_MVT_i32_r(MVT RetVT, Register Op0) {
1035 if (RetVT.SimpleTy != MVT::isVoid)
1036 return Register();
1037 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1038 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREG_MMR6, RC: &Mips::GPR32RegClass, Op0);
1039 }
1040 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1041 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREG_MM, RC: &Mips::GPR32RegClass, Op0);
1042 }
1043 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
1044 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLHBR6REG, RC: &Mips::GPR32RegClass, Op0);
1045 }
1046 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
1047 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLR6REG, RC: &Mips::GPR32RegClass, Op0);
1048 }
1049 if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
1050 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREGHB, RC: &Mips::GPR32RegClass, Op0);
1051 }
1052 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
1053 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREG, RC: &Mips::GPR32RegClass, Op0);
1054 }
1055 return Register();
1056}
1057
1058Register fastEmit_MipsISD_TailCall_MVT_i64_r(MVT RetVT, Register Op0) {
1059 if (RetVT.SimpleTy != MVT::isVoid)
1060 return Register();
1061 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
1062 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLHB64R6REG, RC: &Mips::GPR64RegClass, Op0);
1063 }
1064 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
1065 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALL64R6REG, RC: &Mips::GPR64RegClass, Op0);
1066 }
1067 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
1068 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREGHB64, RC: &Mips::GPR64RegClass, Op0);
1069 }
1070 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
1071 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREG64, RC: &Mips::GPR64RegClass, Op0);
1072 }
1073 return Register();
1074}
1075
1076Register fastEmit_MipsISD_TailCall_r(MVT VT, MVT RetVT, Register Op0) {
1077 switch (VT.SimpleTy) {
1078 case MVT::i32: return fastEmit_MipsISD_TailCall_MVT_i32_r(RetVT, Op0);
1079 case MVT::i64: return fastEmit_MipsISD_TailCall_MVT_i64_r(RetVT, Op0);
1080 default: return Register();
1081 }
1082}
1083
1084// FastEmit functions for MipsISD::TruncIntFP.
1085
1086Register fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(Register Op0) {
1087 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1088 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_S_MMR6, RC: &Mips::FGR32RegClass, Op0);
1089 }
1090 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1091 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_S_MM, RC: &Mips::FGR32RegClass, Op0);
1092 }
1093 if ((Subtarget->hasStandardEncoding())) {
1094 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_S, RC: &Mips::FGR32RegClass, Op0);
1095 }
1096 if ((Subtarget->isR5900())) {
1097 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_W_S, RC: &Mips::FGR32RegClass, Op0);
1098 }
1099 return Register();
1100}
1101
1102Register fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(Register Op0) {
1103 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
1104 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_L_S, RC: &Mips::FGR64RegClass, Op0);
1105 }
1106 return Register();
1107}
1108
1109Register fastEmit_MipsISD_TruncIntFP_MVT_f32_r(MVT RetVT, Register Op0) {
1110switch (RetVT.SimpleTy) {
1111 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(Op0);
1112 case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(Op0);
1113 default: return Register();
1114}
1115}
1116
1117Register fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(Register Op0) {
1118 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1119 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_D_MMR6, RC: &Mips::FGR32RegClass, Op0);
1120 }
1121 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->hasMips32r6())) {
1122 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_W_D64_MM, RC: &Mips::FGR32RegClass, Op0);
1123 }
1124 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())) {
1125 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_MM, RC: &Mips::FGR32RegClass, Op0);
1126 }
1127 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
1128 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_D64, RC: &Mips::FGR32RegClass, Op0);
1129 }
1130 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1131 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_D32, RC: &Mips::FGR32RegClass, Op0);
1132 }
1133 return Register();
1134}
1135
1136Register fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(Register Op0) {
1137 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
1138 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_L_D64, RC: &Mips::FGR64RegClass, Op0);
1139 }
1140 return Register();
1141}
1142
1143Register fastEmit_MipsISD_TruncIntFP_MVT_f64_r(MVT RetVT, Register Op0) {
1144switch (RetVT.SimpleTy) {
1145 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(Op0);
1146 case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(Op0);
1147 default: return Register();
1148}
1149}
1150
1151Register fastEmit_MipsISD_TruncIntFP_r(MVT VT, MVT RetVT, Register Op0) {
1152 switch (VT.SimpleTy) {
1153 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_r(RetVT, Op0);
1154 case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_r(RetVT, Op0);
1155 default: return Register();
1156 }
1157}
1158
1159// FastEmit functions for MipsISD::VALL_NONZERO.
1160
1161Register fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(MVT RetVT, Register Op0) {
1162 if (RetVT.SimpleTy != MVT::i32)
1163 return Register();
1164 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_B_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1165}
1166
1167Register fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(MVT RetVT, Register Op0) {
1168 if (RetVT.SimpleTy != MVT::i32)
1169 return Register();
1170 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_H_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1171}
1172
1173Register fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(MVT RetVT, Register Op0) {
1174 if (RetVT.SimpleTy != MVT::i32)
1175 return Register();
1176 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_W_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1177}
1178
1179Register fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(MVT RetVT, Register Op0) {
1180 if (RetVT.SimpleTy != MVT::i32)
1181 return Register();
1182 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_D_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1183}
1184
1185Register fastEmit_MipsISD_VALL_NONZERO_r(MVT VT, MVT RetVT, Register Op0) {
1186 switch (VT.SimpleTy) {
1187 case MVT::v16i8: return fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(RetVT, Op0);
1188 case MVT::v8i16: return fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(RetVT, Op0);
1189 case MVT::v4i32: return fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(RetVT, Op0);
1190 case MVT::v2i64: return fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(RetVT, Op0);
1191 default: return Register();
1192 }
1193}
1194
1195// FastEmit functions for MipsISD::VALL_ZERO.
1196
1197Register fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(MVT RetVT, Register Op0) {
1198 if (RetVT.SimpleTy != MVT::i32)
1199 return Register();
1200 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_B_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1201}
1202
1203Register fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(MVT RetVT, Register Op0) {
1204 if (RetVT.SimpleTy != MVT::i32)
1205 return Register();
1206 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_H_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1207}
1208
1209Register fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(MVT RetVT, Register Op0) {
1210 if (RetVT.SimpleTy != MVT::i32)
1211 return Register();
1212 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_W_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1213}
1214
1215Register fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(MVT RetVT, Register Op0) {
1216 if (RetVT.SimpleTy != MVT::i32)
1217 return Register();
1218 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_D_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1219}
1220
1221Register fastEmit_MipsISD_VALL_ZERO_r(MVT VT, MVT RetVT, Register Op0) {
1222 switch (VT.SimpleTy) {
1223 case MVT::v16i8: return fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(RetVT, Op0);
1224 case MVT::v8i16: return fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(RetVT, Op0);
1225 case MVT::v4i32: return fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(RetVT, Op0);
1226 case MVT::v2i64: return fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(RetVT, Op0);
1227 default: return Register();
1228 }
1229}
1230
1231// FastEmit functions for MipsISD::VANY_NONZERO.
1232
1233Register fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(MVT RetVT, Register Op0) {
1234 if (RetVT.SimpleTy != MVT::i32)
1235 return Register();
1236 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_V_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1237}
1238
1239Register fastEmit_MipsISD_VANY_NONZERO_r(MVT VT, MVT RetVT, Register Op0) {
1240 switch (VT.SimpleTy) {
1241 case MVT::v16i8: return fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(RetVT, Op0);
1242 default: return Register();
1243 }
1244}
1245
1246// FastEmit functions for MipsISD::VANY_ZERO.
1247
1248Register fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(MVT RetVT, Register Op0) {
1249 if (RetVT.SimpleTy != MVT::i32)
1250 return Register();
1251 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_V_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1252}
1253
1254Register fastEmit_MipsISD_VANY_ZERO_r(MVT VT, MVT RetVT, Register Op0) {
1255 switch (VT.SimpleTy) {
1256 case MVT::v16i8: return fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(RetVT, Op0);
1257 default: return Register();
1258 }
1259}
1260
1261// Top-level FastEmit function.
1262
1263Register fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, Register Op0) override {
1264 switch (Opcode) {
1265 case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0);
1266 case ISD::BRIND: return fastEmit_ISD_BRIND_r(VT, RetVT, Op0);
1267 case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0);
1268 case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0);
1269 case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0);
1270 case ISD::FEXP2: return fastEmit_ISD_FEXP2_r(VT, RetVT, Op0);
1271 case ISD::FLOG2: return fastEmit_ISD_FLOG2_r(VT, RetVT, Op0);
1272 case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0);
1273 case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0);
1274 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0);
1275 case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0);
1276 case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0);
1277 case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0);
1278 case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0);
1279 case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0);
1280 case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0);
1281 case ISD::STRICT_FP_EXTEND: return fastEmit_ISD_STRICT_FP_EXTEND_r(VT, RetVT, Op0);
1282 case ISD::STRICT_FP_ROUND: return fastEmit_ISD_STRICT_FP_ROUND_r(VT, RetVT, Op0);
1283 case ISD::STRICT_FSQRT: return fastEmit_ISD_STRICT_FSQRT_r(VT, RetVT, Op0);
1284 case ISD::STRICT_SINT_TO_FP: return fastEmit_ISD_STRICT_SINT_TO_FP_r(VT, RetVT, Op0);
1285 case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0);
1286 case MipsISD::JmpLink: return fastEmit_MipsISD_JmpLink_r(VT, RetVT, Op0);
1287 case MipsISD::MFHI: return fastEmit_MipsISD_MFHI_r(VT, RetVT, Op0);
1288 case MipsISD::MFLO: return fastEmit_MipsISD_MFLO_r(VT, RetVT, Op0);
1289 case MipsISD::MTC1_D64: return fastEmit_MipsISD_MTC1_D64_r(VT, RetVT, Op0);
1290 case MipsISD::TailCall: return fastEmit_MipsISD_TailCall_r(VT, RetVT, Op0);
1291 case MipsISD::TruncIntFP: return fastEmit_MipsISD_TruncIntFP_r(VT, RetVT, Op0);
1292 case MipsISD::VALL_NONZERO: return fastEmit_MipsISD_VALL_NONZERO_r(VT, RetVT, Op0);
1293 case MipsISD::VALL_ZERO: return fastEmit_MipsISD_VALL_ZERO_r(VT, RetVT, Op0);
1294 case MipsISD::VANY_NONZERO: return fastEmit_MipsISD_VANY_NONZERO_r(VT, RetVT, Op0);
1295 case MipsISD::VANY_ZERO: return fastEmit_MipsISD_VANY_ZERO_r(VT, RetVT, Op0);
1296 default: return Register();
1297 }
1298}
1299
1300// FastEmit functions for ISD::ADD.
1301
1302Register fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1303 if (RetVT.SimpleTy != MVT::i32)
1304 return Register();
1305 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1306 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDU16_MMR6, RC: &Mips::GPRMM16RegClass, Op0, Op1);
1307 }
1308 if ((Subtarget->inMips16Mode())) {
1309 return fastEmitInst_rr(MachineInstOpcode: Mips::AdduRxRyRz16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
1310 }
1311 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1312 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDu_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
1313 }
1314 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1315 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDu, RC: &Mips::GPR32RegClass, Op0, Op1);
1316 }
1317 return Register();
1318}
1319
1320Register fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1321 if (RetVT.SimpleTy != MVT::i64)
1322 return Register();
1323 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1324 return fastEmitInst_rr(MachineInstOpcode: Mips::DADDu, RC: &Mips::GPR64RegClass, Op0, Op1);
1325 }
1326 return Register();
1327}
1328
1329Register fastEmit_ISD_ADD_MVT_v4i8_rr(MVT RetVT, Register Op0, Register Op1) {
1330 if (RetVT.SimpleTy != MVT::v4i8)
1331 return Register();
1332 if ((Subtarget->hasDSP())) {
1333 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDU_QB, RC: &Mips::DSPRRegClass, Op0, Op1);
1334 }
1335 return Register();
1336}
1337
1338Register fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1339 if (RetVT.SimpleTy != MVT::v16i8)
1340 return Register();
1341 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1342 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
1343 }
1344 return Register();
1345}
1346
1347Register fastEmit_ISD_ADD_MVT_v2i16_rr(MVT RetVT, Register Op0, Register Op1) {
1348 if (RetVT.SimpleTy != MVT::v2i16)
1349 return Register();
1350 if ((Subtarget->hasDSP())) {
1351 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDQ_PH, RC: &Mips::DSPRRegClass, Op0, Op1);
1352 }
1353 return Register();
1354}
1355
1356Register fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1357 if (RetVT.SimpleTy != MVT::v8i16)
1358 return Register();
1359 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1360 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
1361 }
1362 return Register();
1363}
1364
1365Register fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
1366 if (RetVT.SimpleTy != MVT::v4i32)
1367 return Register();
1368 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1369 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1370 }
1371 return Register();
1372}
1373
1374Register fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
1375 if (RetVT.SimpleTy != MVT::v2i64)
1376 return Register();
1377 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1378 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1379 }
1380 return Register();
1381}
1382
1383Register fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1384 switch (VT.SimpleTy) {
1385 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op1);
1386 case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op1);
1387 case MVT::v4i8: return fastEmit_ISD_ADD_MVT_v4i8_rr(RetVT, Op0, Op1);
1388 case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op1);
1389 case MVT::v2i16: return fastEmit_ISD_ADD_MVT_v2i16_rr(RetVT, Op0, Op1);
1390 case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op1);
1391 case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op1);
1392 case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op1);
1393 default: return Register();
1394 }
1395}
1396
1397// FastEmit functions for ISD::ADDC.
1398
1399Register fastEmit_ISD_ADDC_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1400 if (RetVT.SimpleTy != MVT::i32)
1401 return Register();
1402 if ((Subtarget->hasDSP())) {
1403 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDSC, RC: &Mips::GPR32RegClass, Op0, Op1);
1404 }
1405 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP())) {
1406 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDu, RC: &Mips::GPR32RegClass, Op0, Op1);
1407 }
1408 return Register();
1409}
1410
1411Register fastEmit_ISD_ADDC_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1412 if (RetVT.SimpleTy != MVT::i64)
1413 return Register();
1414 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->hasDSP()) && (!Subtarget->inMicroMipsMode())) {
1415 return fastEmitInst_rr(MachineInstOpcode: Mips::DADDu, RC: &Mips::GPR64RegClass, Op0, Op1);
1416 }
1417 return Register();
1418}
1419
1420Register fastEmit_ISD_ADDC_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1421 switch (VT.SimpleTy) {
1422 case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_rr(RetVT, Op0, Op1);
1423 case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_rr(RetVT, Op0, Op1);
1424 default: return Register();
1425 }
1426}
1427
1428// FastEmit functions for ISD::ADDE.
1429
1430Register fastEmit_ISD_ADDE_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1431 if (RetVT.SimpleTy != MVT::i32)
1432 return Register();
1433 if ((Subtarget->hasDSP())) {
1434 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDWC, RC: &Mips::GPR32RegClass, Op0, Op1);
1435 }
1436 return Register();
1437}
1438
1439Register fastEmit_ISD_ADDE_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1440 switch (VT.SimpleTy) {
1441 case MVT::i32: return fastEmit_ISD_ADDE_MVT_i32_rr(RetVT, Op0, Op1);
1442 default: return Register();
1443 }
1444}
1445
1446// FastEmit functions for ISD::AND.
1447
1448Register fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1449 if (RetVT.SimpleTy != MVT::i32)
1450 return Register();
1451 if ((Subtarget->inMips16Mode())) {
1452 return fastEmitInst_rr(MachineInstOpcode: Mips::AndRxRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
1453 }
1454 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1455 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
1456 }
1457 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1458 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
1459 }
1460 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1461 return fastEmitInst_rr(MachineInstOpcode: Mips::AND, RC: &Mips::GPR32RegClass, Op0, Op1);
1462 }
1463 return Register();
1464}
1465
1466Register fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1467 if (RetVT.SimpleTy != MVT::i64)
1468 return Register();
1469 if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
1470 return fastEmitInst_rr(MachineInstOpcode: Mips::AND64, RC: &Mips::GPR64RegClass, Op0, Op1);
1471 }
1472 return Register();
1473}
1474
1475Register fastEmit_ISD_AND_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1476 if (RetVT.SimpleTy != MVT::v16i8)
1477 return Register();
1478 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1479 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
1480 }
1481 return Register();
1482}
1483
1484Register fastEmit_ISD_AND_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1485 if (RetVT.SimpleTy != MVT::v8i16)
1486 return Register();
1487 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1488 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
1489 }
1490 return Register();
1491}
1492
1493Register fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
1494 if (RetVT.SimpleTy != MVT::v4i32)
1495 return Register();
1496 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1497 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
1498 }
1499 return Register();
1500}
1501
1502Register fastEmit_ISD_AND_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
1503 if (RetVT.SimpleTy != MVT::v2i64)
1504 return Register();
1505 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1506 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
1507 }
1508 return Register();
1509}
1510
1511Register fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1512 switch (VT.SimpleTy) {
1513 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op1);
1514 case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op1);
1515 case MVT::v16i8: return fastEmit_ISD_AND_MVT_v16i8_rr(RetVT, Op0, Op1);
1516 case MVT::v8i16: return fastEmit_ISD_AND_MVT_v8i16_rr(RetVT, Op0, Op1);
1517 case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op1);
1518 case MVT::v2i64: return fastEmit_ISD_AND_MVT_v2i64_rr(RetVT, Op0, Op1);
1519 default: return Register();
1520 }
1521}
1522
1523// FastEmit functions for ISD::FADD.
1524
1525Register fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1526 if (RetVT.SimpleTy != MVT::f32)
1527 return Register();
1528 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1529 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1530 }
1531 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1532 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1533 }
1534 return Register();
1535}
1536
1537Register fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1538 if (RetVT.SimpleTy != MVT::f64)
1539 return Register();
1540 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
1541 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1542 }
1543 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1544 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1545 }
1546 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1547 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1548 }
1549 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1550 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1551 }
1552 return Register();
1553}
1554
1555Register fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1556 if (RetVT.SimpleTy != MVT::v4f32)
1557 return Register();
1558 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1559 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1560 }
1561 return Register();
1562}
1563
1564Register fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1565 if (RetVT.SimpleTy != MVT::v2f64)
1566 return Register();
1567 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1568 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1569 }
1570 return Register();
1571}
1572
1573Register fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1574 switch (VT.SimpleTy) {
1575 case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op1);
1576 case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op1);
1577 case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op1);
1578 case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op1);
1579 default: return Register();
1580 }
1581}
1582
1583// FastEmit functions for ISD::FDIV.
1584
1585Register fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1586 if (RetVT.SimpleTy != MVT::f32)
1587 return Register();
1588 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1589 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1590 }
1591 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1592 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1593 }
1594 return Register();
1595}
1596
1597Register fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1598 if (RetVT.SimpleTy != MVT::f64)
1599 return Register();
1600 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
1601 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1602 }
1603 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1604 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1605 }
1606 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1607 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1608 }
1609 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1610 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1611 }
1612 return Register();
1613}
1614
1615Register fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1616 if (RetVT.SimpleTy != MVT::v4f32)
1617 return Register();
1618 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1619 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1620 }
1621 return Register();
1622}
1623
1624Register fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1625 if (RetVT.SimpleTy != MVT::v2f64)
1626 return Register();
1627 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1628 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1629 }
1630 return Register();
1631}
1632
1633Register fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1634 switch (VT.SimpleTy) {
1635 case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op1);
1636 case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op1);
1637 case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op1);
1638 case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op1);
1639 default: return Register();
1640 }
1641}
1642
1643// FastEmit functions for ISD::FMAXNUM.
1644
1645Register fastEmit_ISD_FMAXNUM_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1646 if (RetVT.SimpleTy != MVT::f32)
1647 return Register();
1648 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1649 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1650 }
1651 return Register();
1652}
1653
1654Register fastEmit_ISD_FMAXNUM_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1655 if (RetVT.SimpleTy != MVT::f64)
1656 return Register();
1657 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1658 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_D, RC: &Mips::FGR64RegClass, Op0, Op1);
1659 }
1660 return Register();
1661}
1662
1663Register fastEmit_ISD_FMAXNUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1664 switch (VT.SimpleTy) {
1665 case MVT::f32: return fastEmit_ISD_FMAXNUM_MVT_f32_rr(RetVT, Op0, Op1);
1666 case MVT::f64: return fastEmit_ISD_FMAXNUM_MVT_f64_rr(RetVT, Op0, Op1);
1667 default: return Register();
1668 }
1669}
1670
1671// FastEmit functions for ISD::FMAXNUM_IEEE.
1672
1673Register fastEmit_ISD_FMAXNUM_IEEE_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1674 if (RetVT.SimpleTy != MVT::f32)
1675 return Register();
1676 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1677 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1678 }
1679 return Register();
1680}
1681
1682Register fastEmit_ISD_FMAXNUM_IEEE_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1683 if (RetVT.SimpleTy != MVT::f64)
1684 return Register();
1685 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1686 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_D, RC: &Mips::FGR64RegClass, Op0, Op1);
1687 }
1688 return Register();
1689}
1690
1691Register fastEmit_ISD_FMAXNUM_IEEE_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1692 switch (VT.SimpleTy) {
1693 case MVT::f32: return fastEmit_ISD_FMAXNUM_IEEE_MVT_f32_rr(RetVT, Op0, Op1);
1694 case MVT::f64: return fastEmit_ISD_FMAXNUM_IEEE_MVT_f64_rr(RetVT, Op0, Op1);
1695 default: return Register();
1696 }
1697}
1698
1699// FastEmit functions for ISD::FMINNUM.
1700
1701Register fastEmit_ISD_FMINNUM_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1702 if (RetVT.SimpleTy != MVT::f32)
1703 return Register();
1704 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1705 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1706 }
1707 return Register();
1708}
1709
1710Register fastEmit_ISD_FMINNUM_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1711 if (RetVT.SimpleTy != MVT::f64)
1712 return Register();
1713 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1714 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_D, RC: &Mips::FGR64RegClass, Op0, Op1);
1715 }
1716 return Register();
1717}
1718
1719Register fastEmit_ISD_FMINNUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1720 switch (VT.SimpleTy) {
1721 case MVT::f32: return fastEmit_ISD_FMINNUM_MVT_f32_rr(RetVT, Op0, Op1);
1722 case MVT::f64: return fastEmit_ISD_FMINNUM_MVT_f64_rr(RetVT, Op0, Op1);
1723 default: return Register();
1724 }
1725}
1726
1727// FastEmit functions for ISD::FMINNUM_IEEE.
1728
1729Register fastEmit_ISD_FMINNUM_IEEE_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1730 if (RetVT.SimpleTy != MVT::f32)
1731 return Register();
1732 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1733 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1734 }
1735 return Register();
1736}
1737
1738Register fastEmit_ISD_FMINNUM_IEEE_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1739 if (RetVT.SimpleTy != MVT::f64)
1740 return Register();
1741 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1742 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_D, RC: &Mips::FGR64RegClass, Op0, Op1);
1743 }
1744 return Register();
1745}
1746
1747Register fastEmit_ISD_FMINNUM_IEEE_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1748 switch (VT.SimpleTy) {
1749 case MVT::f32: return fastEmit_ISD_FMINNUM_IEEE_MVT_f32_rr(RetVT, Op0, Op1);
1750 case MVT::f64: return fastEmit_ISD_FMINNUM_IEEE_MVT_f64_rr(RetVT, Op0, Op1);
1751 default: return Register();
1752 }
1753}
1754
1755// FastEmit functions for ISD::FMUL.
1756
1757Register fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1758 if (RetVT.SimpleTy != MVT::f32)
1759 return Register();
1760 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1761 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1762 }
1763 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1764 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1765 }
1766 return Register();
1767}
1768
1769Register fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1770 if (RetVT.SimpleTy != MVT::f64)
1771 return Register();
1772 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
1773 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1774 }
1775 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1776 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1777 }
1778 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1779 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1780 }
1781 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1782 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1783 }
1784 return Register();
1785}
1786
1787Register fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1788 if (RetVT.SimpleTy != MVT::v4f32)
1789 return Register();
1790 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1791 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1792 }
1793 return Register();
1794}
1795
1796Register fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1797 if (RetVT.SimpleTy != MVT::v2f64)
1798 return Register();
1799 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1800 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1801 }
1802 return Register();
1803}
1804
1805Register fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1806 switch (VT.SimpleTy) {
1807 case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op1);
1808 case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op1);
1809 case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op1);
1810 case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op1);
1811 default: return Register();
1812 }
1813}
1814
1815// FastEmit functions for ISD::FSUB.
1816
1817Register fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1818 if (RetVT.SimpleTy != MVT::f32)
1819 return Register();
1820 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1821 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1822 }
1823 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1824 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1825 }
1826 return Register();
1827}
1828
1829Register fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1830 if (RetVT.SimpleTy != MVT::f64)
1831 return Register();
1832 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
1833 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1834 }
1835 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1836 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1837 }
1838 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1839 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1840 }
1841 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1842 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1843 }
1844 return Register();
1845}
1846
1847Register fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1848 if (RetVT.SimpleTy != MVT::v4f32)
1849 return Register();
1850 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1851 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1852 }
1853 return Register();
1854}
1855
1856Register fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1857 if (RetVT.SimpleTy != MVT::v2f64)
1858 return Register();
1859 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1860 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1861 }
1862 return Register();
1863}
1864
1865Register fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1866 switch (VT.SimpleTy) {
1867 case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op1);
1868 case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op1);
1869 case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op1);
1870 case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op1);
1871 default: return Register();
1872 }
1873}
1874
1875// FastEmit functions for ISD::MUL.
1876
1877Register fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1878 if (RetVT.SimpleTy != MVT::i32)
1879 return Register();
1880 if ((Subtarget->inMips16Mode())) {
1881 return fastEmitInst_rr(MachineInstOpcode: Mips::MultRxRyRz16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
1882 }
1883 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1884 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
1885 }
1886 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1887 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
1888 }
1889 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1890 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_R6, RC: &Mips::GPR32RegClass, Op0, Op1);
1891 }
1892 if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
1893 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL, RC: &Mips::GPR32RegClass, Op0, Op1);
1894 }
1895 return Register();
1896}
1897
1898Register fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1899 if (RetVT.SimpleTy != MVT::i64)
1900 return Register();
1901 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1902 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUL_R6, RC: &Mips::GPR64RegClass, Op0, Op1);
1903 }
1904 if ((Subtarget->hasCnMips())) {
1905 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUL, RC: &Mips::GPR64RegClass, Op0, Op1);
1906 }
1907 return Register();
1908}
1909
1910Register fastEmit_ISD_MUL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1911 if (RetVT.SimpleTy != MVT::v16i8)
1912 return Register();
1913 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1914 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
1915 }
1916 return Register();
1917}
1918
1919Register fastEmit_ISD_MUL_MVT_v2i16_rr(MVT RetVT, Register Op0, Register Op1) {
1920 if (RetVT.SimpleTy != MVT::v2i16)
1921 return Register();
1922 if ((Subtarget->hasDSPR2())) {
1923 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_PH, RC: &Mips::DSPRRegClass, Op0, Op1);
1924 }
1925 return Register();
1926}
1927
1928Register fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1929 if (RetVT.SimpleTy != MVT::v8i16)
1930 return Register();
1931 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1932 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
1933 }
1934 return Register();
1935}
1936
1937Register fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
1938 if (RetVT.SimpleTy != MVT::v4i32)
1939 return Register();
1940 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1941 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1942 }
1943 return Register();
1944}
1945
1946Register fastEmit_ISD_MUL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
1947 if (RetVT.SimpleTy != MVT::v2i64)
1948 return Register();
1949 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1950 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1951 }
1952 return Register();
1953}
1954
1955Register fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1956 switch (VT.SimpleTy) {
1957 case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op1);
1958 case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op1);
1959 case MVT::v16i8: return fastEmit_ISD_MUL_MVT_v16i8_rr(RetVT, Op0, Op1);
1960 case MVT::v2i16: return fastEmit_ISD_MUL_MVT_v2i16_rr(RetVT, Op0, Op1);
1961 case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op1);
1962 case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op1);
1963 case MVT::v2i64: return fastEmit_ISD_MUL_MVT_v2i64_rr(RetVT, Op0, Op1);
1964 default: return Register();
1965 }
1966}
1967
1968// FastEmit functions for ISD::MULHS.
1969
1970Register fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1971 if (RetVT.SimpleTy != MVT::i32)
1972 return Register();
1973 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1974 return fastEmitInst_rr(MachineInstOpcode: Mips::MUH_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
1975 }
1976 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1977 return fastEmitInst_rr(MachineInstOpcode: Mips::MUH, RC: &Mips::GPR32RegClass, Op0, Op1);
1978 }
1979 return Register();
1980}
1981
1982Register fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1983 if (RetVT.SimpleTy != MVT::i64)
1984 return Register();
1985 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1986 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUH, RC: &Mips::GPR64RegClass, Op0, Op1);
1987 }
1988 return Register();
1989}
1990
1991Register fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1992 switch (VT.SimpleTy) {
1993 case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op1);
1994 case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op1);
1995 default: return Register();
1996 }
1997}
1998
1999// FastEmit functions for ISD::MULHU.
2000
2001Register fastEmit_ISD_MULHU_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2002 if (RetVT.SimpleTy != MVT::i32)
2003 return Register();
2004 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2005 return fastEmitInst_rr(MachineInstOpcode: Mips::MUHU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2006 }
2007 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2008 return fastEmitInst_rr(MachineInstOpcode: Mips::MUHU, RC: &Mips::GPR32RegClass, Op0, Op1);
2009 }
2010 return Register();
2011}
2012
2013Register fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2014 if (RetVT.SimpleTy != MVT::i64)
2015 return Register();
2016 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2017 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUHU, RC: &Mips::GPR64RegClass, Op0, Op1);
2018 }
2019 return Register();
2020}
2021
2022Register fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2023 switch (VT.SimpleTy) {
2024 case MVT::i32: return fastEmit_ISD_MULHU_MVT_i32_rr(RetVT, Op0, Op1);
2025 case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op1);
2026 default: return Register();
2027 }
2028}
2029
2030// FastEmit functions for ISD::OR.
2031
2032Register fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2033 if (RetVT.SimpleTy != MVT::i32)
2034 return Register();
2035 if ((Subtarget->inMips16Mode())) {
2036 return fastEmitInst_rr(MachineInstOpcode: Mips::OrRxRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2037 }
2038 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2039 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2040 }
2041 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
2042 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2043 }
2044 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2045 return fastEmitInst_rr(MachineInstOpcode: Mips::OR, RC: &Mips::GPR32RegClass, Op0, Op1);
2046 }
2047 return Register();
2048}
2049
2050Register fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2051 if (RetVT.SimpleTy != MVT::i64)
2052 return Register();
2053 if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
2054 return fastEmitInst_rr(MachineInstOpcode: Mips::OR64, RC: &Mips::GPR64RegClass, Op0, Op1);
2055 }
2056 return Register();
2057}
2058
2059Register fastEmit_ISD_OR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2060 if (RetVT.SimpleTy != MVT::v16i8)
2061 return Register();
2062 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2063 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
2064 }
2065 return Register();
2066}
2067
2068Register fastEmit_ISD_OR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2069 if (RetVT.SimpleTy != MVT::v8i16)
2070 return Register();
2071 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2072 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
2073 }
2074 return Register();
2075}
2076
2077Register fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2078 if (RetVT.SimpleTy != MVT::v4i32)
2079 return Register();
2080 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2081 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
2082 }
2083 return Register();
2084}
2085
2086Register fastEmit_ISD_OR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2087 if (RetVT.SimpleTy != MVT::v2i64)
2088 return Register();
2089 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2090 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
2091 }
2092 return Register();
2093}
2094
2095Register fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2096 switch (VT.SimpleTy) {
2097 case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op1);
2098 case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op1);
2099 case MVT::v16i8: return fastEmit_ISD_OR_MVT_v16i8_rr(RetVT, Op0, Op1);
2100 case MVT::v8i16: return fastEmit_ISD_OR_MVT_v8i16_rr(RetVT, Op0, Op1);
2101 case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op1);
2102 case MVT::v2i64: return fastEmit_ISD_OR_MVT_v2i64_rr(RetVT, Op0, Op1);
2103 default: return Register();
2104 }
2105}
2106
2107// FastEmit functions for ISD::ROTR.
2108
2109Register fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2110 if (RetVT.SimpleTy != MVT::i32)
2111 return Register();
2112 if ((Subtarget->inMicroMipsMode())) {
2113 return fastEmitInst_rr(MachineInstOpcode: Mips::ROTRV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2114 }
2115 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2116 return fastEmitInst_rr(MachineInstOpcode: Mips::ROTRV, RC: &Mips::GPR32RegClass, Op0, Op1);
2117 }
2118 return Register();
2119}
2120
2121Register fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2122 switch (VT.SimpleTy) {
2123 case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op1);
2124 default: return Register();
2125 }
2126}
2127
2128// FastEmit functions for ISD::SDIV.
2129
2130Register fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2131 if (RetVT.SimpleTy != MVT::i32)
2132 return Register();
2133 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2134 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2135 }
2136 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2137 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV, RC: &Mips::GPR32RegClass, Op0, Op1);
2138 }
2139 return Register();
2140}
2141
2142Register fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2143 if (RetVT.SimpleTy != MVT::i64)
2144 return Register();
2145 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2146 return fastEmitInst_rr(MachineInstOpcode: Mips::DDIV, RC: &Mips::GPR64RegClass, Op0, Op1);
2147 }
2148 return Register();
2149}
2150
2151Register fastEmit_ISD_SDIV_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2152 if (RetVT.SimpleTy != MVT::v16i8)
2153 return Register();
2154 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2155 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2156 }
2157 return Register();
2158}
2159
2160Register fastEmit_ISD_SDIV_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2161 if (RetVT.SimpleTy != MVT::v8i16)
2162 return Register();
2163 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2164 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2165 }
2166 return Register();
2167}
2168
2169Register fastEmit_ISD_SDIV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2170 if (RetVT.SimpleTy != MVT::v4i32)
2171 return Register();
2172 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2173 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2174 }
2175 return Register();
2176}
2177
2178Register fastEmit_ISD_SDIV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2179 if (RetVT.SimpleTy != MVT::v2i64)
2180 return Register();
2181 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2182 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2183 }
2184 return Register();
2185}
2186
2187Register fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2188 switch (VT.SimpleTy) {
2189 case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op1);
2190 case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op1);
2191 case MVT::v16i8: return fastEmit_ISD_SDIV_MVT_v16i8_rr(RetVT, Op0, Op1);
2192 case MVT::v8i16: return fastEmit_ISD_SDIV_MVT_v8i16_rr(RetVT, Op0, Op1);
2193 case MVT::v4i32: return fastEmit_ISD_SDIV_MVT_v4i32_rr(RetVT, Op0, Op1);
2194 case MVT::v2i64: return fastEmit_ISD_SDIV_MVT_v2i64_rr(RetVT, Op0, Op1);
2195 default: return Register();
2196 }
2197}
2198
2199// FastEmit functions for ISD::SHL.
2200
2201Register fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2202 if (RetVT.SimpleTy != MVT::i32)
2203 return Register();
2204 if ((Subtarget->inMicroMipsMode())) {
2205 return fastEmitInst_rr(MachineInstOpcode: Mips::SLLV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2206 }
2207 if ((Subtarget->inMips16Mode())) {
2208 return fastEmitInst_rr(MachineInstOpcode: Mips::SllvRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2209 }
2210 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2211 return fastEmitInst_rr(MachineInstOpcode: Mips::SLLV, RC: &Mips::GPR32RegClass, Op0, Op1);
2212 }
2213 return Register();
2214}
2215
2216Register fastEmit_ISD_SHL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2217 if (RetVT.SimpleTy != MVT::v16i8)
2218 return Register();
2219 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2220 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2221 }
2222 return Register();
2223}
2224
2225Register fastEmit_ISD_SHL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2226 if (RetVT.SimpleTy != MVT::v8i16)
2227 return Register();
2228 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2229 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2230 }
2231 return Register();
2232}
2233
2234Register fastEmit_ISD_SHL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2235 if (RetVT.SimpleTy != MVT::v4i32)
2236 return Register();
2237 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2238 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2239 }
2240 return Register();
2241}
2242
2243Register fastEmit_ISD_SHL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2244 if (RetVT.SimpleTy != MVT::v2i64)
2245 return Register();
2246 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2247 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2248 }
2249 return Register();
2250}
2251
2252Register fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2253 switch (VT.SimpleTy) {
2254 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op1);
2255 case MVT::v16i8: return fastEmit_ISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op1);
2256 case MVT::v8i16: return fastEmit_ISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op1);
2257 case MVT::v4i32: return fastEmit_ISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op1);
2258 case MVT::v2i64: return fastEmit_ISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op1);
2259 default: return Register();
2260 }
2261}
2262
2263// FastEmit functions for ISD::SMAX.
2264
2265Register fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2266 if (RetVT.SimpleTy != MVT::v16i8)
2267 return Register();
2268 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2269 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2270 }
2271 return Register();
2272}
2273
2274Register fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2275 if (RetVT.SimpleTy != MVT::v8i16)
2276 return Register();
2277 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2278 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2279 }
2280 return Register();
2281}
2282
2283Register fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2284 if (RetVT.SimpleTy != MVT::v4i32)
2285 return Register();
2286 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2287 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2288 }
2289 return Register();
2290}
2291
2292Register fastEmit_ISD_SMAX_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2293 if (RetVT.SimpleTy != MVT::v2i64)
2294 return Register();
2295 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2296 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2297 }
2298 return Register();
2299}
2300
2301Register fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2302 switch (VT.SimpleTy) {
2303 case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
2304 case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
2305 case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
2306 case MVT::v2i64: return fastEmit_ISD_SMAX_MVT_v2i64_rr(RetVT, Op0, Op1);
2307 default: return Register();
2308 }
2309}
2310
2311// FastEmit functions for ISD::SMIN.
2312
2313Register fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2314 if (RetVT.SimpleTy != MVT::v16i8)
2315 return Register();
2316 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2317 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2318 }
2319 return Register();
2320}
2321
2322Register fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2323 if (RetVT.SimpleTy != MVT::v8i16)
2324 return Register();
2325 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2326 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2327 }
2328 return Register();
2329}
2330
2331Register fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2332 if (RetVT.SimpleTy != MVT::v4i32)
2333 return Register();
2334 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2335 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2336 }
2337 return Register();
2338}
2339
2340Register fastEmit_ISD_SMIN_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2341 if (RetVT.SimpleTy != MVT::v2i64)
2342 return Register();
2343 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2344 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2345 }
2346 return Register();
2347}
2348
2349Register fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2350 switch (VT.SimpleTy) {
2351 case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
2352 case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
2353 case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
2354 case MVT::v2i64: return fastEmit_ISD_SMIN_MVT_v2i64_rr(RetVT, Op0, Op1);
2355 default: return Register();
2356 }
2357}
2358
2359// FastEmit functions for ISD::SRA.
2360
2361Register fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2362 if (RetVT.SimpleTy != MVT::i32)
2363 return Register();
2364 if ((Subtarget->inMicroMipsMode())) {
2365 return fastEmitInst_rr(MachineInstOpcode: Mips::SRAV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2366 }
2367 if ((Subtarget->inMips16Mode())) {
2368 return fastEmitInst_rr(MachineInstOpcode: Mips::SravRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2369 }
2370 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2371 return fastEmitInst_rr(MachineInstOpcode: Mips::SRAV, RC: &Mips::GPR32RegClass, Op0, Op1);
2372 }
2373 return Register();
2374}
2375
2376Register fastEmit_ISD_SRA_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2377 if (RetVT.SimpleTy != MVT::v16i8)
2378 return Register();
2379 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2380 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2381 }
2382 return Register();
2383}
2384
2385Register fastEmit_ISD_SRA_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2386 if (RetVT.SimpleTy != MVT::v8i16)
2387 return Register();
2388 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2389 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2390 }
2391 return Register();
2392}
2393
2394Register fastEmit_ISD_SRA_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2395 if (RetVT.SimpleTy != MVT::v4i32)
2396 return Register();
2397 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2398 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2399 }
2400 return Register();
2401}
2402
2403Register fastEmit_ISD_SRA_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2404 if (RetVT.SimpleTy != MVT::v2i64)
2405 return Register();
2406 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2407 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2408 }
2409 return Register();
2410}
2411
2412Register fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2413 switch (VT.SimpleTy) {
2414 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op1);
2415 case MVT::v16i8: return fastEmit_ISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op1);
2416 case MVT::v8i16: return fastEmit_ISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op1);
2417 case MVT::v4i32: return fastEmit_ISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op1);
2418 case MVT::v2i64: return fastEmit_ISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op1);
2419 default: return Register();
2420 }
2421}
2422
2423// FastEmit functions for ISD::SREM.
2424
2425Register fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2426 if (RetVT.SimpleTy != MVT::i32)
2427 return Register();
2428 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2429 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2430 }
2431 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2432 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD, RC: &Mips::GPR32RegClass, Op0, Op1);
2433 }
2434 return Register();
2435}
2436
2437Register fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2438 if (RetVT.SimpleTy != MVT::i64)
2439 return Register();
2440 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2441 return fastEmitInst_rr(MachineInstOpcode: Mips::DMOD, RC: &Mips::GPR64RegClass, Op0, Op1);
2442 }
2443 return Register();
2444}
2445
2446Register fastEmit_ISD_SREM_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2447 if (RetVT.SimpleTy != MVT::v16i8)
2448 return Register();
2449 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2450 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2451 }
2452 return Register();
2453}
2454
2455Register fastEmit_ISD_SREM_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2456 if (RetVT.SimpleTy != MVT::v8i16)
2457 return Register();
2458 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2459 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2460 }
2461 return Register();
2462}
2463
2464Register fastEmit_ISD_SREM_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2465 if (RetVT.SimpleTy != MVT::v4i32)
2466 return Register();
2467 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2468 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2469 }
2470 return Register();
2471}
2472
2473Register fastEmit_ISD_SREM_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2474 if (RetVT.SimpleTy != MVT::v2i64)
2475 return Register();
2476 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2477 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2478 }
2479 return Register();
2480}
2481
2482Register fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2483 switch (VT.SimpleTy) {
2484 case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op1);
2485 case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op1);
2486 case MVT::v16i8: return fastEmit_ISD_SREM_MVT_v16i8_rr(RetVT, Op0, Op1);
2487 case MVT::v8i16: return fastEmit_ISD_SREM_MVT_v8i16_rr(RetVT, Op0, Op1);
2488 case MVT::v4i32: return fastEmit_ISD_SREM_MVT_v4i32_rr(RetVT, Op0, Op1);
2489 case MVT::v2i64: return fastEmit_ISD_SREM_MVT_v2i64_rr(RetVT, Op0, Op1);
2490 default: return Register();
2491 }
2492}
2493
2494// FastEmit functions for ISD::SRL.
2495
2496Register fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2497 if (RetVT.SimpleTy != MVT::i32)
2498 return Register();
2499 if ((Subtarget->inMicroMipsMode())) {
2500 return fastEmitInst_rr(MachineInstOpcode: Mips::SRLV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2501 }
2502 if ((Subtarget->inMips16Mode())) {
2503 return fastEmitInst_rr(MachineInstOpcode: Mips::SrlvRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2504 }
2505 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2506 return fastEmitInst_rr(MachineInstOpcode: Mips::SRLV, RC: &Mips::GPR32RegClass, Op0, Op1);
2507 }
2508 return Register();
2509}
2510
2511Register fastEmit_ISD_SRL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2512 if (RetVT.SimpleTy != MVT::v16i8)
2513 return Register();
2514 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2515 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2516 }
2517 return Register();
2518}
2519
2520Register fastEmit_ISD_SRL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2521 if (RetVT.SimpleTy != MVT::v8i16)
2522 return Register();
2523 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2524 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2525 }
2526 return Register();
2527}
2528
2529Register fastEmit_ISD_SRL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2530 if (RetVT.SimpleTy != MVT::v4i32)
2531 return Register();
2532 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2533 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2534 }
2535 return Register();
2536}
2537
2538Register fastEmit_ISD_SRL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2539 if (RetVT.SimpleTy != MVT::v2i64)
2540 return Register();
2541 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2542 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2543 }
2544 return Register();
2545}
2546
2547Register fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2548 switch (VT.SimpleTy) {
2549 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op1);
2550 case MVT::v16i8: return fastEmit_ISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op1);
2551 case MVT::v8i16: return fastEmit_ISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op1);
2552 case MVT::v4i32: return fastEmit_ISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op1);
2553 case MVT::v2i64: return fastEmit_ISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op1);
2554 default: return Register();
2555 }
2556}
2557
2558// FastEmit functions for ISD::STRICT_FADD.
2559
2560Register fastEmit_ISD_STRICT_FADD_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
2561 if (RetVT.SimpleTy != MVT::f32)
2562 return Register();
2563 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2564 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_S, RC: &Mips::FGR32RegClass, Op0, Op1);
2565 }
2566 return Register();
2567}
2568
2569Register fastEmit_ISD_STRICT_FADD_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
2570 if (RetVT.SimpleTy != MVT::f64)
2571 return Register();
2572 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2573 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
2574 }
2575 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
2576 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
2577 }
2578 return Register();
2579}
2580
2581Register fastEmit_ISD_STRICT_FADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2582 switch (VT.SimpleTy) {
2583 case MVT::f32: return fastEmit_ISD_STRICT_FADD_MVT_f32_rr(RetVT, Op0, Op1);
2584 case MVT::f64: return fastEmit_ISD_STRICT_FADD_MVT_f64_rr(RetVT, Op0, Op1);
2585 default: return Register();
2586 }
2587}
2588
2589// FastEmit functions for ISD::STRICT_FDIV.
2590
2591Register fastEmit_ISD_STRICT_FDIV_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
2592 if (RetVT.SimpleTy != MVT::f32)
2593 return Register();
2594 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2595 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_S, RC: &Mips::FGR32RegClass, Op0, Op1);
2596 }
2597 return Register();
2598}
2599
2600Register fastEmit_ISD_STRICT_FDIV_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
2601 if (RetVT.SimpleTy != MVT::f64)
2602 return Register();
2603 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2604 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
2605 }
2606 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
2607 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
2608 }
2609 return Register();
2610}
2611
2612Register fastEmit_ISD_STRICT_FDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2613 switch (VT.SimpleTy) {
2614 case MVT::f32: return fastEmit_ISD_STRICT_FDIV_MVT_f32_rr(RetVT, Op0, Op1);
2615 case MVT::f64: return fastEmit_ISD_STRICT_FDIV_MVT_f64_rr(RetVT, Op0, Op1);
2616 default: return Register();
2617 }
2618}
2619
2620// FastEmit functions for ISD::STRICT_FMUL.
2621
2622Register fastEmit_ISD_STRICT_FMUL_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
2623 if (RetVT.SimpleTy != MVT::f32)
2624 return Register();
2625 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2626 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_S, RC: &Mips::FGR32RegClass, Op0, Op1);
2627 }
2628 return Register();
2629}
2630
2631Register fastEmit_ISD_STRICT_FMUL_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
2632 if (RetVT.SimpleTy != MVT::f64)
2633 return Register();
2634 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2635 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
2636 }
2637 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
2638 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
2639 }
2640 return Register();
2641}
2642
2643Register fastEmit_ISD_STRICT_FMUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2644 switch (VT.SimpleTy) {
2645 case MVT::f32: return fastEmit_ISD_STRICT_FMUL_MVT_f32_rr(RetVT, Op0, Op1);
2646 case MVT::f64: return fastEmit_ISD_STRICT_FMUL_MVT_f64_rr(RetVT, Op0, Op1);
2647 default: return Register();
2648 }
2649}
2650
2651// FastEmit functions for ISD::STRICT_FSUB.
2652
2653Register fastEmit_ISD_STRICT_FSUB_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
2654 if (RetVT.SimpleTy != MVT::f32)
2655 return Register();
2656 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2657 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_S, RC: &Mips::FGR32RegClass, Op0, Op1);
2658 }
2659 return Register();
2660}
2661
2662Register fastEmit_ISD_STRICT_FSUB_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
2663 if (RetVT.SimpleTy != MVT::f64)
2664 return Register();
2665 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2666 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
2667 }
2668 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
2669 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
2670 }
2671 return Register();
2672}
2673
2674Register fastEmit_ISD_STRICT_FSUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2675 switch (VT.SimpleTy) {
2676 case MVT::f32: return fastEmit_ISD_STRICT_FSUB_MVT_f32_rr(RetVT, Op0, Op1);
2677 case MVT::f64: return fastEmit_ISD_STRICT_FSUB_MVT_f64_rr(RetVT, Op0, Op1);
2678 default: return Register();
2679 }
2680}
2681
2682// FastEmit functions for ISD::SUB.
2683
2684Register fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2685 if (RetVT.SimpleTy != MVT::i32)
2686 return Register();
2687 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2688 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBU16_MMR6, RC: &Mips::GPRMM16RegClass, Op0, Op1);
2689 }
2690 if ((Subtarget->inMips16Mode())) {
2691 return fastEmitInst_rr(MachineInstOpcode: Mips::SubuRxRyRz16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2692 }
2693 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
2694 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2695 }
2696 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2697 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu, RC: &Mips::GPR32RegClass, Op0, Op1);
2698 }
2699 return Register();
2700}
2701
2702Register fastEmit_ISD_SUB_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2703 if (RetVT.SimpleTy != MVT::i64)
2704 return Register();
2705 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2706 return fastEmitInst_rr(MachineInstOpcode: Mips::DSUBu, RC: &Mips::GPR64RegClass, Op0, Op1);
2707 }
2708 return Register();
2709}
2710
2711Register fastEmit_ISD_SUB_MVT_v4i8_rr(MVT RetVT, Register Op0, Register Op1) {
2712 if (RetVT.SimpleTy != MVT::v4i8)
2713 return Register();
2714 if ((Subtarget->hasDSP())) {
2715 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBU_QB, RC: &Mips::DSPRRegClass, Op0, Op1);
2716 }
2717 return Register();
2718}
2719
2720Register fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2721 if (RetVT.SimpleTy != MVT::v16i8)
2722 return Register();
2723 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2724 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2725 }
2726 return Register();
2727}
2728
2729Register fastEmit_ISD_SUB_MVT_v2i16_rr(MVT RetVT, Register Op0, Register Op1) {
2730 if (RetVT.SimpleTy != MVT::v2i16)
2731 return Register();
2732 if ((Subtarget->hasDSP())) {
2733 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBQ_PH, RC: &Mips::DSPRRegClass, Op0, Op1);
2734 }
2735 return Register();
2736}
2737
2738Register fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2739 if (RetVT.SimpleTy != MVT::v8i16)
2740 return Register();
2741 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2742 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2743 }
2744 return Register();
2745}
2746
2747Register fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2748 if (RetVT.SimpleTy != MVT::v4i32)
2749 return Register();
2750 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2751 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2752 }
2753 return Register();
2754}
2755
2756Register fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2757 if (RetVT.SimpleTy != MVT::v2i64)
2758 return Register();
2759 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2760 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2761 }
2762 return Register();
2763}
2764
2765Register fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2766 switch (VT.SimpleTy) {
2767 case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op1);
2768 case MVT::i64: return fastEmit_ISD_SUB_MVT_i64_rr(RetVT, Op0, Op1);
2769 case MVT::v4i8: return fastEmit_ISD_SUB_MVT_v4i8_rr(RetVT, Op0, Op1);
2770 case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op1);
2771 case MVT::v2i16: return fastEmit_ISD_SUB_MVT_v2i16_rr(RetVT, Op0, Op1);
2772 case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op1);
2773 case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op1);
2774 case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op1);
2775 default: return Register();
2776 }
2777}
2778
2779// FastEmit functions for ISD::SUBC.
2780
2781Register fastEmit_ISD_SUBC_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2782 if (RetVT.SimpleTy != MVT::i32)
2783 return Register();
2784 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2785 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2786 }
2787 if ((Subtarget->inMicroMipsMode())) {
2788 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2789 }
2790 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2791 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu, RC: &Mips::GPR32RegClass, Op0, Op1);
2792 }
2793 return Register();
2794}
2795
2796Register fastEmit_ISD_SUBC_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2797 if (RetVT.SimpleTy != MVT::i64)
2798 return Register();
2799 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())) {
2800 return fastEmitInst_rr(MachineInstOpcode: Mips::DSUBu, RC: &Mips::GPR64RegClass, Op0, Op1);
2801 }
2802 return Register();
2803}
2804
2805Register fastEmit_ISD_SUBC_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2806 switch (VT.SimpleTy) {
2807 case MVT::i32: return fastEmit_ISD_SUBC_MVT_i32_rr(RetVT, Op0, Op1);
2808 case MVT::i64: return fastEmit_ISD_SUBC_MVT_i64_rr(RetVT, Op0, Op1);
2809 default: return Register();
2810 }
2811}
2812
2813// FastEmit functions for ISD::UDIV.
2814
2815Register fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2816 if (RetVT.SimpleTy != MVT::i32)
2817 return Register();
2818 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2819 return fastEmitInst_rr(MachineInstOpcode: Mips::DIVU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2820 }
2821 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2822 return fastEmitInst_rr(MachineInstOpcode: Mips::DIVU, RC: &Mips::GPR32RegClass, Op0, Op1);
2823 }
2824 return Register();
2825}
2826
2827Register fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2828 if (RetVT.SimpleTy != MVT::i64)
2829 return Register();
2830 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2831 return fastEmitInst_rr(MachineInstOpcode: Mips::DDIVU, RC: &Mips::GPR64RegClass, Op0, Op1);
2832 }
2833 return Register();
2834}
2835
2836Register fastEmit_ISD_UDIV_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2837 if (RetVT.SimpleTy != MVT::v16i8)
2838 return Register();
2839 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2840 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2841 }
2842 return Register();
2843}
2844
2845Register fastEmit_ISD_UDIV_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2846 if (RetVT.SimpleTy != MVT::v8i16)
2847 return Register();
2848 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2849 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2850 }
2851 return Register();
2852}
2853
2854Register fastEmit_ISD_UDIV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2855 if (RetVT.SimpleTy != MVT::v4i32)
2856 return Register();
2857 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2858 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2859 }
2860 return Register();
2861}
2862
2863Register fastEmit_ISD_UDIV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2864 if (RetVT.SimpleTy != MVT::v2i64)
2865 return Register();
2866 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2867 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2868 }
2869 return Register();
2870}
2871
2872Register fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2873 switch (VT.SimpleTy) {
2874 case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op1);
2875 case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op1);
2876 case MVT::v16i8: return fastEmit_ISD_UDIV_MVT_v16i8_rr(RetVT, Op0, Op1);
2877 case MVT::v8i16: return fastEmit_ISD_UDIV_MVT_v8i16_rr(RetVT, Op0, Op1);
2878 case MVT::v4i32: return fastEmit_ISD_UDIV_MVT_v4i32_rr(RetVT, Op0, Op1);
2879 case MVT::v2i64: return fastEmit_ISD_UDIV_MVT_v2i64_rr(RetVT, Op0, Op1);
2880 default: return Register();
2881 }
2882}
2883
2884// FastEmit functions for ISD::UMAX.
2885
2886Register fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2887 if (RetVT.SimpleTy != MVT::v16i8)
2888 return Register();
2889 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2890 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2891 }
2892 return Register();
2893}
2894
2895Register fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2896 if (RetVT.SimpleTy != MVT::v8i16)
2897 return Register();
2898 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2899 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2900 }
2901 return Register();
2902}
2903
2904Register fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2905 if (RetVT.SimpleTy != MVT::v4i32)
2906 return Register();
2907 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2908 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2909 }
2910 return Register();
2911}
2912
2913Register fastEmit_ISD_UMAX_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2914 if (RetVT.SimpleTy != MVT::v2i64)
2915 return Register();
2916 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2917 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2918 }
2919 return Register();
2920}
2921
2922Register fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2923 switch (VT.SimpleTy) {
2924 case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
2925 case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
2926 case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
2927 case MVT::v2i64: return fastEmit_ISD_UMAX_MVT_v2i64_rr(RetVT, Op0, Op1);
2928 default: return Register();
2929 }
2930}
2931
2932// FastEmit functions for ISD::UMIN.
2933
2934Register fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2935 if (RetVT.SimpleTy != MVT::v16i8)
2936 return Register();
2937 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2938 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2939 }
2940 return Register();
2941}
2942
2943Register fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2944 if (RetVT.SimpleTy != MVT::v8i16)
2945 return Register();
2946 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2947 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2948 }
2949 return Register();
2950}
2951
2952Register fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2953 if (RetVT.SimpleTy != MVT::v4i32)
2954 return Register();
2955 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2956 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2957 }
2958 return Register();
2959}
2960
2961Register fastEmit_ISD_UMIN_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2962 if (RetVT.SimpleTy != MVT::v2i64)
2963 return Register();
2964 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2965 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2966 }
2967 return Register();
2968}
2969
2970Register fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2971 switch (VT.SimpleTy) {
2972 case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
2973 case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
2974 case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
2975 case MVT::v2i64: return fastEmit_ISD_UMIN_MVT_v2i64_rr(RetVT, Op0, Op1);
2976 default: return Register();
2977 }
2978}
2979
2980// FastEmit functions for ISD::UREM.
2981
2982Register fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2983 if (RetVT.SimpleTy != MVT::i32)
2984 return Register();
2985 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2986 return fastEmitInst_rr(MachineInstOpcode: Mips::MODU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2987 }
2988 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2989 return fastEmitInst_rr(MachineInstOpcode: Mips::MODU, RC: &Mips::GPR32RegClass, Op0, Op1);
2990 }
2991 return Register();
2992}
2993
2994Register fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2995 if (RetVT.SimpleTy != MVT::i64)
2996 return Register();
2997 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2998 return fastEmitInst_rr(MachineInstOpcode: Mips::DMODU, RC: &Mips::GPR64RegClass, Op0, Op1);
2999 }
3000 return Register();
3001}
3002
3003Register fastEmit_ISD_UREM_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3004 if (RetVT.SimpleTy != MVT::v16i8)
3005 return Register();
3006 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3007 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3008 }
3009 return Register();
3010}
3011
3012Register fastEmit_ISD_UREM_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3013 if (RetVT.SimpleTy != MVT::v8i16)
3014 return Register();
3015 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3016 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3017 }
3018 return Register();
3019}
3020
3021Register fastEmit_ISD_UREM_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3022 if (RetVT.SimpleTy != MVT::v4i32)
3023 return Register();
3024 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3025 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3026 }
3027 return Register();
3028}
3029
3030Register fastEmit_ISD_UREM_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3031 if (RetVT.SimpleTy != MVT::v2i64)
3032 return Register();
3033 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3034 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3035 }
3036 return Register();
3037}
3038
3039Register fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3040 switch (VT.SimpleTy) {
3041 case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op1);
3042 case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op1);
3043 case MVT::v16i8: return fastEmit_ISD_UREM_MVT_v16i8_rr(RetVT, Op0, Op1);
3044 case MVT::v8i16: return fastEmit_ISD_UREM_MVT_v8i16_rr(RetVT, Op0, Op1);
3045 case MVT::v4i32: return fastEmit_ISD_UREM_MVT_v4i32_rr(RetVT, Op0, Op1);
3046 case MVT::v2i64: return fastEmit_ISD_UREM_MVT_v2i64_rr(RetVT, Op0, Op1);
3047 default: return Register();
3048 }
3049}
3050
3051// FastEmit functions for ISD::XOR.
3052
3053Register fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3054 if (RetVT.SimpleTy != MVT::i32)
3055 return Register();
3056 if ((Subtarget->inMips16Mode())) {
3057 return fastEmitInst_rr(MachineInstOpcode: Mips::XorRxRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
3058 }
3059 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
3060 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
3061 }
3062 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
3063 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
3064 }
3065 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3066 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR, RC: &Mips::GPR32RegClass, Op0, Op1);
3067 }
3068 return Register();
3069}
3070
3071Register fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3072 if (RetVT.SimpleTy != MVT::i64)
3073 return Register();
3074 if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
3075 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR64, RC: &Mips::GPR64RegClass, Op0, Op1);
3076 }
3077 return Register();
3078}
3079
3080Register fastEmit_ISD_XOR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3081 if (RetVT.SimpleTy != MVT::v16i8)
3082 return Register();
3083 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3084 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
3085 }
3086 return Register();
3087}
3088
3089Register fastEmit_ISD_XOR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3090 if (RetVT.SimpleTy != MVT::v8i16)
3091 return Register();
3092 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3093 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
3094 }
3095 return Register();
3096}
3097
3098Register fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3099 if (RetVT.SimpleTy != MVT::v4i32)
3100 return Register();
3101 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3102 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
3103 }
3104 return Register();
3105}
3106
3107Register fastEmit_ISD_XOR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3108 if (RetVT.SimpleTy != MVT::v2i64)
3109 return Register();
3110 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3111 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
3112 }
3113 return Register();
3114}
3115
3116Register fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3117 switch (VT.SimpleTy) {
3118 case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op1);
3119 case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op1);
3120 case MVT::v16i8: return fastEmit_ISD_XOR_MVT_v16i8_rr(RetVT, Op0, Op1);
3121 case MVT::v8i16: return fastEmit_ISD_XOR_MVT_v8i16_rr(RetVT, Op0, Op1);
3122 case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op1);
3123 case MVT::v2i64: return fastEmit_ISD_XOR_MVT_v2i64_rr(RetVT, Op0, Op1);
3124 default: return Register();
3125 }
3126}
3127
3128// FastEmit functions for MipsISD::BuildPairF64.
3129
3130Register fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3131 if (RetVT.SimpleTy != MVT::f64)
3132 return Register();
3133 if ((Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMips16Mode())) {
3134 return fastEmitInst_rr(MachineInstOpcode: Mips::BuildPairF64_64, RC: &Mips::FGR64RegClass, Op0, Op1);
3135 }
3136 if ((!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode())) {
3137 return fastEmitInst_rr(MachineInstOpcode: Mips::BuildPairF64, RC: &Mips::AFGR64RegClass, Op0, Op1);
3138 }
3139 return Register();
3140}
3141
3142Register fastEmit_MipsISD_BuildPairF64_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3143 switch (VT.SimpleTy) {
3144 case MVT::i32: return fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(RetVT, Op0, Op1);
3145 default: return Register();
3146 }
3147}
3148
3149// FastEmit functions for MipsISD::BuildPairF64_FPR.
3150
3151Register fastEmit_MipsISD_BuildPairF64_FPR_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
3152 if (RetVT.SimpleTy != MVT::f64)
3153 return Register();
3154 if ((!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode())) {
3155 return fastEmitInst_rr(MachineInstOpcode: Mips::BuildPairF64_FPR, RC: &Mips::AFGR64RegClass, Op0, Op1);
3156 }
3157 return Register();
3158}
3159
3160Register fastEmit_MipsISD_BuildPairF64_FPR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3161 switch (VT.SimpleTy) {
3162 case MVT::f32: return fastEmit_MipsISD_BuildPairF64_FPR_MVT_f32_rr(RetVT, Op0, Op1);
3163 default: return Register();
3164 }
3165}
3166
3167// FastEmit functions for MipsISD::DivRem.
3168
3169Register fastEmit_MipsISD_DivRem_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3170 if (RetVT.SimpleTy != MVT::Untyped)
3171 return Register();
3172 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3173 return fastEmitInst_rr(MachineInstOpcode: Mips::SDIV_MM_Pseudo, RC: &Mips::ACC64RegClass, Op0, Op1);
3174 }
3175 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3176 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoSDIV, RC: &Mips::ACC64RegClass, Op0, Op1);
3177 }
3178 return Register();
3179}
3180
3181Register fastEmit_MipsISD_DivRem_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3182 if (RetVT.SimpleTy != MVT::Untyped)
3183 return Register();
3184 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (!Subtarget->isR5900())) {
3185 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDSDIV, RC: &Mips::ACC128RegClass, Op0, Op1);
3186 }
3187 return Register();
3188}
3189
3190Register fastEmit_MipsISD_DivRem_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3191 switch (VT.SimpleTy) {
3192 case MVT::i32: return fastEmit_MipsISD_DivRem_MVT_i32_rr(RetVT, Op0, Op1);
3193 case MVT::i64: return fastEmit_MipsISD_DivRem_MVT_i64_rr(RetVT, Op0, Op1);
3194 default: return Register();
3195 }
3196}
3197
3198// FastEmit functions for MipsISD::DivRem16.
3199
3200Register fastEmit_MipsISD_DivRem16_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3201 if (RetVT.SimpleTy != MVT::isVoid)
3202 return Register();
3203 if ((Subtarget->inMips16Mode())) {
3204 return fastEmitInst_rr(MachineInstOpcode: Mips::DivRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
3205 }
3206 return Register();
3207}
3208
3209Register fastEmit_MipsISD_DivRem16_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3210 switch (VT.SimpleTy) {
3211 case MVT::i32: return fastEmit_MipsISD_DivRem16_MVT_i32_rr(RetVT, Op0, Op1);
3212 default: return Register();
3213 }
3214}
3215
3216// FastEmit functions for MipsISD::DivRemU.
3217
3218Register fastEmit_MipsISD_DivRemU_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3219 if (RetVT.SimpleTy != MVT::Untyped)
3220 return Register();
3221 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3222 return fastEmitInst_rr(MachineInstOpcode: Mips::UDIV_MM_Pseudo, RC: &Mips::ACC64RegClass, Op0, Op1);
3223 }
3224 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3225 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoUDIV, RC: &Mips::ACC64RegClass, Op0, Op1);
3226 }
3227 return Register();
3228}
3229
3230Register fastEmit_MipsISD_DivRemU_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3231 if (RetVT.SimpleTy != MVT::Untyped)
3232 return Register();
3233 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (!Subtarget->isR5900())) {
3234 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDUDIV, RC: &Mips::ACC128RegClass, Op0, Op1);
3235 }
3236 return Register();
3237}
3238
3239Register fastEmit_MipsISD_DivRemU_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3240 switch (VT.SimpleTy) {
3241 case MVT::i32: return fastEmit_MipsISD_DivRemU_MVT_i32_rr(RetVT, Op0, Op1);
3242 case MVT::i64: return fastEmit_MipsISD_DivRemU_MVT_i64_rr(RetVT, Op0, Op1);
3243 default: return Register();
3244 }
3245}
3246
3247// FastEmit functions for MipsISD::DivRemU16.
3248
3249Register fastEmit_MipsISD_DivRemU16_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3250 if (RetVT.SimpleTy != MVT::isVoid)
3251 return Register();
3252 if ((Subtarget->inMips16Mode())) {
3253 return fastEmitInst_rr(MachineInstOpcode: Mips::DivuRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
3254 }
3255 return Register();
3256}
3257
3258Register fastEmit_MipsISD_DivRemU16_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3259 switch (VT.SimpleTy) {
3260 case MVT::i32: return fastEmit_MipsISD_DivRemU16_MVT_i32_rr(RetVT, Op0, Op1);
3261 default: return Register();
3262 }
3263}
3264
3265// FastEmit functions for MipsISD::EH_RETURN.
3266
3267Register fastEmit_MipsISD_EH_RETURN_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3268 if (RetVT.SimpleTy != MVT::isVoid)
3269 return Register();
3270 return fastEmitInst_rr(MachineInstOpcode: Mips::MIPSeh_return32, RC: &Mips::GPR32RegClass, Op0, Op1);
3271}
3272
3273Register fastEmit_MipsISD_EH_RETURN_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3274 if (RetVT.SimpleTy != MVT::isVoid)
3275 return Register();
3276 return fastEmitInst_rr(MachineInstOpcode: Mips::MIPSeh_return64, RC: &Mips::GPR64RegClass, Op0, Op1);
3277}
3278
3279Register fastEmit_MipsISD_EH_RETURN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3280 switch (VT.SimpleTy) {
3281 case MVT::i32: return fastEmit_MipsISD_EH_RETURN_MVT_i32_rr(RetVT, Op0, Op1);
3282 case MVT::i64: return fastEmit_MipsISD_EH_RETURN_MVT_i64_rr(RetVT, Op0, Op1);
3283 default: return Register();
3284 }
3285}
3286
3287// FastEmit functions for MipsISD::ILVEV.
3288
3289Register fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3290 if (RetVT.SimpleTy != MVT::v16i8)
3291 return Register();
3292 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3293 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3294 }
3295 return Register();
3296}
3297
3298Register fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3299 if (RetVT.SimpleTy != MVT::v8i16)
3300 return Register();
3301 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3302 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3303 }
3304 return Register();
3305}
3306
3307Register fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3308 if (RetVT.SimpleTy != MVT::v4i32)
3309 return Register();
3310 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3311 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3312 }
3313 return Register();
3314}
3315
3316Register fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3317 if (RetVT.SimpleTy != MVT::v2i64)
3318 return Register();
3319 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3320 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3321 }
3322 return Register();
3323}
3324
3325Register fastEmit_MipsISD_ILVEV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3326 switch (VT.SimpleTy) {
3327 case MVT::v16i8: return fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(RetVT, Op0, Op1);
3328 case MVT::v8i16: return fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(RetVT, Op0, Op1);
3329 case MVT::v4i32: return fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(RetVT, Op0, Op1);
3330 case MVT::v2i64: return fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(RetVT, Op0, Op1);
3331 default: return Register();
3332 }
3333}
3334
3335// FastEmit functions for MipsISD::ILVL.
3336
3337Register fastEmit_MipsISD_ILVL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3338 if (RetVT.SimpleTy != MVT::v16i8)
3339 return Register();
3340 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3341 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3342 }
3343 return Register();
3344}
3345
3346Register fastEmit_MipsISD_ILVL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3347 if (RetVT.SimpleTy != MVT::v8i16)
3348 return Register();
3349 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3350 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3351 }
3352 return Register();
3353}
3354
3355Register fastEmit_MipsISD_ILVL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3356 if (RetVT.SimpleTy != MVT::v4i32)
3357 return Register();
3358 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3359 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3360 }
3361 return Register();
3362}
3363
3364Register fastEmit_MipsISD_ILVL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3365 if (RetVT.SimpleTy != MVT::v2i64)
3366 return Register();
3367 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3368 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3369 }
3370 return Register();
3371}
3372
3373Register fastEmit_MipsISD_ILVL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3374 switch (VT.SimpleTy) {
3375 case MVT::v16i8: return fastEmit_MipsISD_ILVL_MVT_v16i8_rr(RetVT, Op0, Op1);
3376 case MVT::v8i16: return fastEmit_MipsISD_ILVL_MVT_v8i16_rr(RetVT, Op0, Op1);
3377 case MVT::v4i32: return fastEmit_MipsISD_ILVL_MVT_v4i32_rr(RetVT, Op0, Op1);
3378 case MVT::v2i64: return fastEmit_MipsISD_ILVL_MVT_v2i64_rr(RetVT, Op0, Op1);
3379 default: return Register();
3380 }
3381}
3382
3383// FastEmit functions for MipsISD::ILVOD.
3384
3385Register fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3386 if (RetVT.SimpleTy != MVT::v16i8)
3387 return Register();
3388 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3389 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3390 }
3391 return Register();
3392}
3393
3394Register fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3395 if (RetVT.SimpleTy != MVT::v8i16)
3396 return Register();
3397 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3398 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3399 }
3400 return Register();
3401}
3402
3403Register fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3404 if (RetVT.SimpleTy != MVT::v4i32)
3405 return Register();
3406 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3407 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3408 }
3409 return Register();
3410}
3411
3412Register fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3413 if (RetVT.SimpleTy != MVT::v2i64)
3414 return Register();
3415 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3416 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3417 }
3418 return Register();
3419}
3420
3421Register fastEmit_MipsISD_ILVOD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3422 switch (VT.SimpleTy) {
3423 case MVT::v16i8: return fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(RetVT, Op0, Op1);
3424 case MVT::v8i16: return fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(RetVT, Op0, Op1);
3425 case MVT::v4i32: return fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(RetVT, Op0, Op1);
3426 case MVT::v2i64: return fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(RetVT, Op0, Op1);
3427 default: return Register();
3428 }
3429}
3430
3431// FastEmit functions for MipsISD::ILVR.
3432
3433Register fastEmit_MipsISD_ILVR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3434 if (RetVT.SimpleTy != MVT::v16i8)
3435 return Register();
3436 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3437 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3438 }
3439 return Register();
3440}
3441
3442Register fastEmit_MipsISD_ILVR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3443 if (RetVT.SimpleTy != MVT::v8i16)
3444 return Register();
3445 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3446 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3447 }
3448 return Register();
3449}
3450
3451Register fastEmit_MipsISD_ILVR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3452 if (RetVT.SimpleTy != MVT::v4i32)
3453 return Register();
3454 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3455 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3456 }
3457 return Register();
3458}
3459
3460Register fastEmit_MipsISD_ILVR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3461 if (RetVT.SimpleTy != MVT::v2i64)
3462 return Register();
3463 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3464 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3465 }
3466 return Register();
3467}
3468
3469Register fastEmit_MipsISD_ILVR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3470 switch (VT.SimpleTy) {
3471 case MVT::v16i8: return fastEmit_MipsISD_ILVR_MVT_v16i8_rr(RetVT, Op0, Op1);
3472 case MVT::v8i16: return fastEmit_MipsISD_ILVR_MVT_v8i16_rr(RetVT, Op0, Op1);
3473 case MVT::v4i32: return fastEmit_MipsISD_ILVR_MVT_v4i32_rr(RetVT, Op0, Op1);
3474 case MVT::v2i64: return fastEmit_MipsISD_ILVR_MVT_v2i64_rr(RetVT, Op0, Op1);
3475 default: return Register();
3476 }
3477}
3478
3479// FastEmit functions for MipsISD::MTLOHI.
3480
3481Register fastEmit_MipsISD_MTLOHI_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3482 if (RetVT.SimpleTy != MVT::Untyped)
3483 return Register();
3484 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
3485 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI_MM, RC: &Mips::ACC64RegClass, Op0, Op1);
3486 }
3487 if ((Subtarget->hasDSP()) && (!Subtarget->inMips16Mode())) {
3488 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI_DSP, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3489 }
3490 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3491 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI, RC: &Mips::ACC64RegClass, Op0, Op1);
3492 }
3493 return Register();
3494}
3495
3496Register fastEmit_MipsISD_MTLOHI_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3497 if (RetVT.SimpleTy != MVT::Untyped)
3498 return Register();
3499 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3500 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI64, RC: &Mips::ACC128RegClass, Op0, Op1);
3501 }
3502 return Register();
3503}
3504
3505Register fastEmit_MipsISD_MTLOHI_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3506 switch (VT.SimpleTy) {
3507 case MVT::i32: return fastEmit_MipsISD_MTLOHI_MVT_i32_rr(RetVT, Op0, Op1);
3508 case MVT::i64: return fastEmit_MipsISD_MTLOHI_MVT_i64_rr(RetVT, Op0, Op1);
3509 default: return Register();
3510 }
3511}
3512
3513// FastEmit functions for MipsISD::Mult.
3514
3515Register fastEmit_MipsISD_Mult_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3516 if (RetVT.SimpleTy != MVT::Untyped)
3517 return Register();
3518 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
3519 return fastEmitInst_rr(MachineInstOpcode: Mips::MULT_DSP_MM, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3520 }
3521 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
3522 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULT_MM, RC: &Mips::ACC64RegClass, Op0, Op1);
3523 }
3524 if ((Subtarget->hasDSP())) {
3525 return fastEmitInst_rr(MachineInstOpcode: Mips::MULT_DSP, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3526 }
3527 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3528 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULT, RC: &Mips::ACC64RegClass, Op0, Op1);
3529 }
3530 return Register();
3531}
3532
3533Register fastEmit_MipsISD_Mult_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3534 if (RetVT.SimpleTy != MVT::Untyped)
3535 return Register();
3536 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (!Subtarget->isR5900())) {
3537 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDMULT, RC: &Mips::ACC128RegClass, Op0, Op1);
3538 }
3539 return Register();
3540}
3541
3542Register fastEmit_MipsISD_Mult_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3543 switch (VT.SimpleTy) {
3544 case MVT::i32: return fastEmit_MipsISD_Mult_MVT_i32_rr(RetVT, Op0, Op1);
3545 case MVT::i64: return fastEmit_MipsISD_Mult_MVT_i64_rr(RetVT, Op0, Op1);
3546 default: return Register();
3547 }
3548}
3549
3550// FastEmit functions for MipsISD::Multu.
3551
3552Register fastEmit_MipsISD_Multu_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3553 if (RetVT.SimpleTy != MVT::Untyped)
3554 return Register();
3555 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
3556 return fastEmitInst_rr(MachineInstOpcode: Mips::MULTU_DSP_MM, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3557 }
3558 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
3559 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULTu_MM, RC: &Mips::ACC64RegClass, Op0, Op1);
3560 }
3561 if ((Subtarget->hasDSP())) {
3562 return fastEmitInst_rr(MachineInstOpcode: Mips::MULTU_DSP, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3563 }
3564 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3565 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULTu, RC: &Mips::ACC64RegClass, Op0, Op1);
3566 }
3567 return Register();
3568}
3569
3570Register fastEmit_MipsISD_Multu_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3571 if (RetVT.SimpleTy != MVT::Untyped)
3572 return Register();
3573 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (!Subtarget->isR5900())) {
3574 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDMULTu, RC: &Mips::ACC128RegClass, Op0, Op1);
3575 }
3576 return Register();
3577}
3578
3579Register fastEmit_MipsISD_Multu_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3580 switch (VT.SimpleTy) {
3581 case MVT::i32: return fastEmit_MipsISD_Multu_MVT_i32_rr(RetVT, Op0, Op1);
3582 case MVT::i64: return fastEmit_MipsISD_Multu_MVT_i64_rr(RetVT, Op0, Op1);
3583 default: return Register();
3584 }
3585}
3586
3587// FastEmit functions for MipsISD::PCKEV.
3588
3589Register fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3590 if (RetVT.SimpleTy != MVT::v16i8)
3591 return Register();
3592 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3593 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3594 }
3595 return Register();
3596}
3597
3598Register fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3599 if (RetVT.SimpleTy != MVT::v8i16)
3600 return Register();
3601 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3602 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3603 }
3604 return Register();
3605}
3606
3607Register fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3608 if (RetVT.SimpleTy != MVT::v4i32)
3609 return Register();
3610 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3611 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3612 }
3613 return Register();
3614}
3615
3616Register fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3617 if (RetVT.SimpleTy != MVT::v2i64)
3618 return Register();
3619 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3620 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3621 }
3622 return Register();
3623}
3624
3625Register fastEmit_MipsISD_PCKEV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3626 switch (VT.SimpleTy) {
3627 case MVT::v16i8: return fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(RetVT, Op0, Op1);
3628 case MVT::v8i16: return fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(RetVT, Op0, Op1);
3629 case MVT::v4i32: return fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(RetVT, Op0, Op1);
3630 case MVT::v2i64: return fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(RetVT, Op0, Op1);
3631 default: return Register();
3632 }
3633}
3634
3635// FastEmit functions for MipsISD::PCKOD.
3636
3637Register fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3638 if (RetVT.SimpleTy != MVT::v16i8)
3639 return Register();
3640 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3641 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3642 }
3643 return Register();
3644}
3645
3646Register fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3647 if (RetVT.SimpleTy != MVT::v8i16)
3648 return Register();
3649 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3650 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3651 }
3652 return Register();
3653}
3654
3655Register fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3656 if (RetVT.SimpleTy != MVT::v4i32)
3657 return Register();
3658 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3659 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3660 }
3661 return Register();
3662}
3663
3664Register fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3665 if (RetVT.SimpleTy != MVT::v2i64)
3666 return Register();
3667 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3668 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3669 }
3670 return Register();
3671}
3672
3673Register fastEmit_MipsISD_PCKOD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3674 switch (VT.SimpleTy) {
3675 case MVT::v16i8: return fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(RetVT, Op0, Op1);
3676 case MVT::v8i16: return fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(RetVT, Op0, Op1);
3677 case MVT::v4i32: return fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(RetVT, Op0, Op1);
3678 case MVT::v2i64: return fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(RetVT, Op0, Op1);
3679 default: return Register();
3680 }
3681}
3682
3683// FastEmit functions for MipsISD::VNOR.
3684
3685Register fastEmit_MipsISD_VNOR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3686 if (RetVT.SimpleTy != MVT::v16i8)
3687 return Register();
3688 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3689 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
3690 }
3691 return Register();
3692}
3693
3694Register fastEmit_MipsISD_VNOR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3695 if (RetVT.SimpleTy != MVT::v8i16)
3696 return Register();
3697 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3698 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
3699 }
3700 return Register();
3701}
3702
3703Register fastEmit_MipsISD_VNOR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3704 if (RetVT.SimpleTy != MVT::v4i32)
3705 return Register();
3706 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3707 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
3708 }
3709 return Register();
3710}
3711
3712Register fastEmit_MipsISD_VNOR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3713 if (RetVT.SimpleTy != MVT::v2i64)
3714 return Register();
3715 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3716 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
3717 }
3718 return Register();
3719}
3720
3721Register fastEmit_MipsISD_VNOR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3722 switch (VT.SimpleTy) {
3723 case MVT::v16i8: return fastEmit_MipsISD_VNOR_MVT_v16i8_rr(RetVT, Op0, Op1);
3724 case MVT::v8i16: return fastEmit_MipsISD_VNOR_MVT_v8i16_rr(RetVT, Op0, Op1);
3725 case MVT::v4i32: return fastEmit_MipsISD_VNOR_MVT_v4i32_rr(RetVT, Op0, Op1);
3726 case MVT::v2i64: return fastEmit_MipsISD_VNOR_MVT_v2i64_rr(RetVT, Op0, Op1);
3727 default: return Register();
3728 }
3729}
3730
3731// Top-level FastEmit function.
3732
3733Register fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, Register Op1) override {
3734 switch (Opcode) {
3735 case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op1);
3736 case ISD::ADDC: return fastEmit_ISD_ADDC_rr(VT, RetVT, Op0, Op1);
3737 case ISD::ADDE: return fastEmit_ISD_ADDE_rr(VT, RetVT, Op0, Op1);
3738 case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op1);
3739 case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op1);
3740 case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op1);
3741 case ISD::FMAXNUM: return fastEmit_ISD_FMAXNUM_rr(VT, RetVT, Op0, Op1);
3742 case ISD::FMAXNUM_IEEE: return fastEmit_ISD_FMAXNUM_IEEE_rr(VT, RetVT, Op0, Op1);
3743 case ISD::FMINNUM: return fastEmit_ISD_FMINNUM_rr(VT, RetVT, Op0, Op1);
3744 case ISD::FMINNUM_IEEE: return fastEmit_ISD_FMINNUM_IEEE_rr(VT, RetVT, Op0, Op1);
3745 case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op1);
3746 case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op1);
3747 case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op1);
3748 case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op1);
3749 case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op1);
3750 case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op1);
3751 case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op1);
3752 case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op1);
3753 case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op1);
3754 case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op1);
3755 case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op1);
3756 case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op1);
3757 case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op1);
3758 case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op1);
3759 case ISD::STRICT_FADD: return fastEmit_ISD_STRICT_FADD_rr(VT, RetVT, Op0, Op1);
3760 case ISD::STRICT_FDIV: return fastEmit_ISD_STRICT_FDIV_rr(VT, RetVT, Op0, Op1);
3761 case ISD::STRICT_FMUL: return fastEmit_ISD_STRICT_FMUL_rr(VT, RetVT, Op0, Op1);
3762 case ISD::STRICT_FSUB: return fastEmit_ISD_STRICT_FSUB_rr(VT, RetVT, Op0, Op1);
3763 case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op1);
3764 case ISD::SUBC: return fastEmit_ISD_SUBC_rr(VT, RetVT, Op0, Op1);
3765 case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op1);
3766 case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op1);
3767 case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op1);
3768 case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op1);
3769 case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op1);
3770 case MipsISD::BuildPairF64: return fastEmit_MipsISD_BuildPairF64_rr(VT, RetVT, Op0, Op1);
3771 case MipsISD::BuildPairF64_FPR: return fastEmit_MipsISD_BuildPairF64_FPR_rr(VT, RetVT, Op0, Op1);
3772 case MipsISD::DivRem: return fastEmit_MipsISD_DivRem_rr(VT, RetVT, Op0, Op1);
3773 case MipsISD::DivRem16: return fastEmit_MipsISD_DivRem16_rr(VT, RetVT, Op0, Op1);
3774 case MipsISD::DivRemU: return fastEmit_MipsISD_DivRemU_rr(VT, RetVT, Op0, Op1);
3775 case MipsISD::DivRemU16: return fastEmit_MipsISD_DivRemU16_rr(VT, RetVT, Op0, Op1);
3776 case MipsISD::EH_RETURN: return fastEmit_MipsISD_EH_RETURN_rr(VT, RetVT, Op0, Op1);
3777 case MipsISD::ILVEV: return fastEmit_MipsISD_ILVEV_rr(VT, RetVT, Op0, Op1);
3778 case MipsISD::ILVL: return fastEmit_MipsISD_ILVL_rr(VT, RetVT, Op0, Op1);
3779 case MipsISD::ILVOD: return fastEmit_MipsISD_ILVOD_rr(VT, RetVT, Op0, Op1);
3780 case MipsISD::ILVR: return fastEmit_MipsISD_ILVR_rr(VT, RetVT, Op0, Op1);
3781 case MipsISD::MTLOHI: return fastEmit_MipsISD_MTLOHI_rr(VT, RetVT, Op0, Op1);
3782 case MipsISD::Mult: return fastEmit_MipsISD_Mult_rr(VT, RetVT, Op0, Op1);
3783 case MipsISD::Multu: return fastEmit_MipsISD_Multu_rr(VT, RetVT, Op0, Op1);
3784 case MipsISD::PCKEV: return fastEmit_MipsISD_PCKEV_rr(VT, RetVT, Op0, Op1);
3785 case MipsISD::PCKOD: return fastEmit_MipsISD_PCKOD_rr(VT, RetVT, Op0, Op1);
3786 case MipsISD::VNOR: return fastEmit_MipsISD_VNOR_rr(VT, RetVT, Op0, Op1);
3787 default: return Register();
3788 }
3789}
3790
3791// FastEmit functions for MipsISD::ExtractElementF64.
3792
3793Register fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3794 if (RetVT.SimpleTy != MVT::i32)
3795 return Register();
3796 if ((Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMips16Mode())) {
3797 return fastEmitInst_ri(MachineInstOpcode: Mips::ExtractElementF64_64, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3798 }
3799 if ((!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode())) {
3800 return fastEmitInst_ri(MachineInstOpcode: Mips::ExtractElementF64, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3801 }
3802 return Register();
3803}
3804
3805Register fastEmit_MipsISD_ExtractElementF64_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3806 switch (VT.SimpleTy) {
3807 case MVT::f64: return fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(RetVT, Op0, imm1);
3808 default: return Register();
3809 }
3810}
3811
3812// FastEmit functions for MipsISD::SHLL_DSP.
3813
3814Register fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3815 if (RetVT.SimpleTy != MVT::v4i8)
3816 return Register();
3817 if ((Subtarget->hasDSP())) {
3818 return fastEmitInst_ri(MachineInstOpcode: Mips::SHLL_QB, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3819 }
3820 return Register();
3821}
3822
3823Register fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3824 if (RetVT.SimpleTy != MVT::v2i16)
3825 return Register();
3826 if ((Subtarget->hasDSP())) {
3827 return fastEmitInst_ri(MachineInstOpcode: Mips::SHLL_PH, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3828 }
3829 return Register();
3830}
3831
3832Register fastEmit_MipsISD_SHLL_DSP_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3833 switch (VT.SimpleTy) {
3834 case MVT::v4i8: return fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(RetVT, Op0, imm1);
3835 case MVT::v2i16: return fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(RetVT, Op0, imm1);
3836 default: return Register();
3837 }
3838}
3839
3840// FastEmit functions for MipsISD::SHRA_DSP.
3841
3842Register fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3843 if (RetVT.SimpleTy != MVT::v4i8)
3844 return Register();
3845 if ((Subtarget->hasDSPR2())) {
3846 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRA_QB, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3847 }
3848 return Register();
3849}
3850
3851Register fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3852 if (RetVT.SimpleTy != MVT::v2i16)
3853 return Register();
3854 if ((Subtarget->hasDSP())) {
3855 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRA_PH, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3856 }
3857 return Register();
3858}
3859
3860Register fastEmit_MipsISD_SHRA_DSP_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3861 switch (VT.SimpleTy) {
3862 case MVT::v4i8: return fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(RetVT, Op0, imm1);
3863 case MVT::v2i16: return fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(RetVT, Op0, imm1);
3864 default: return Register();
3865 }
3866}
3867
3868// FastEmit functions for MipsISD::SHRL_DSP.
3869
3870Register fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3871 if (RetVT.SimpleTy != MVT::v4i8)
3872 return Register();
3873 if ((Subtarget->hasDSP())) {
3874 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRL_QB, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3875 }
3876 return Register();
3877}
3878
3879Register fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3880 if (RetVT.SimpleTy != MVT::v2i16)
3881 return Register();
3882 if ((Subtarget->hasDSPR2())) {
3883 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRL_PH, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3884 }
3885 return Register();
3886}
3887
3888Register fastEmit_MipsISD_SHRL_DSP_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3889 switch (VT.SimpleTy) {
3890 case MVT::v4i8: return fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(RetVT, Op0, imm1);
3891 case MVT::v2i16: return fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(RetVT, Op0, imm1);
3892 default: return Register();
3893 }
3894}
3895
3896// Top-level FastEmit function.
3897
3898Register fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) override {
3899 if (VT == MVT::i32 && Predicate_immZExt5(Imm: imm1))
3900 if (Register Reg = fastEmit_ri_Predicate_immZExt5(VT, RetVT, Opcode, Op0, imm1))
3901 return Reg;
3902
3903 if (VT == MVT::i32 && Predicate_immZExt6(Imm: imm1))
3904 if (Register Reg = fastEmit_ri_Predicate_immZExt6(VT, RetVT, Opcode, Op0, imm1))
3905 return Reg;
3906
3907 if (VT == MVT::iPTR && Predicate_immZExt2Ptr(Imm: imm1))
3908 if (Register Reg = fastEmit_ri_Predicate_immZExt2Ptr(VT, RetVT, Opcode, Op0, imm1))
3909 return Reg;
3910
3911 if (VT == MVT::iPTR && Predicate_immZExt1Ptr(Imm: imm1))
3912 if (Register Reg = fastEmit_ri_Predicate_immZExt1Ptr(VT, RetVT, Opcode, Op0, imm1))
3913 return Reg;
3914
3915 if (VT == MVT::i32 && Predicate_immZExt4(Imm: imm1))
3916 if (Register Reg = fastEmit_ri_Predicate_immZExt4(VT, RetVT, Opcode, Op0, imm1))
3917 return Reg;
3918
3919 if (VT == MVT::i32 && Predicate_immSExtAddiur2(Imm: imm1))
3920 if (Register Reg = fastEmit_ri_Predicate_immSExtAddiur2(VT, RetVT, Opcode, Op0, imm1))
3921 return Reg;
3922
3923 if (VT == MVT::i32 && Predicate_immSExtAddius5(Imm: imm1))
3924 if (Register Reg = fastEmit_ri_Predicate_immSExtAddius5(VT, RetVT, Opcode, Op0, imm1))
3925 return Reg;
3926
3927 if (VT == MVT::i32 && Predicate_immZExtAndi16(Imm: imm1))
3928 if (Register Reg = fastEmit_ri_Predicate_immZExtAndi16(VT, RetVT, Opcode, Op0, imm1))
3929 return Reg;
3930
3931 if (VT == MVT::i32 && Predicate_immZExt2Shift(Imm: imm1))
3932 if (Register Reg = fastEmit_ri_Predicate_immZExt2Shift(VT, RetVT, Opcode, Op0, imm1))
3933 return Reg;
3934
3935 switch (Opcode) {
3936 case MipsISD::ExtractElementF64: return fastEmit_MipsISD_ExtractElementF64_ri(VT, RetVT, Op0, imm1);
3937 case MipsISD::SHLL_DSP: return fastEmit_MipsISD_SHLL_DSP_ri(VT, RetVT, Op0, imm1);
3938 case MipsISD::SHRA_DSP: return fastEmit_MipsISD_SHRA_DSP_ri(VT, RetVT, Op0, imm1);
3939 case MipsISD::SHRL_DSP: return fastEmit_MipsISD_SHRL_DSP_ri(VT, RetVT, Op0, imm1);
3940 default: return Register();
3941 }
3942}
3943
3944// FastEmit functions for ISD::ROTR.
3945
3946Register fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, Register Op0, uint64_t imm1) {
3947 if (RetVT.SimpleTy != MVT::i32)
3948 return Register();
3949 if ((Subtarget->inMicroMipsMode())) {
3950 return fastEmitInst_ri(MachineInstOpcode: Mips::ROTR_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3951 }
3952 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3953 return fastEmitInst_ri(MachineInstOpcode: Mips::ROTR, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3954 }
3955 return Register();
3956}
3957
3958Register fastEmit_ISD_ROTR_ri_Predicate_immZExt5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3959 switch (VT.SimpleTy) {
3960 case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
3961 default: return Register();
3962 }
3963}
3964
3965// FastEmit functions for ISD::SHL.
3966
3967Register fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, Register Op0, uint64_t imm1) {
3968 if (RetVT.SimpleTy != MVT::i32)
3969 return Register();
3970 if ((Subtarget->inMicroMipsMode())) {
3971 return fastEmitInst_ri(MachineInstOpcode: Mips::SLL_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3972 }
3973 if ((Subtarget->inMips16Mode())) {
3974 return fastEmitInst_ri(MachineInstOpcode: Mips::SllX16, RC: &Mips::CPU16RegsRegClass, Op0, Imm: imm1);
3975 }
3976 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3977 return fastEmitInst_ri(MachineInstOpcode: Mips::SLL, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3978 }
3979 return Register();
3980}
3981
3982Register fastEmit_ISD_SHL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3983 switch (VT.SimpleTy) {
3984 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
3985 default: return Register();
3986 }
3987}
3988
3989// FastEmit functions for ISD::SRA.
3990
3991Register fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, Register Op0, uint64_t imm1) {
3992 if (RetVT.SimpleTy != MVT::i32)
3993 return Register();
3994 if ((Subtarget->inMicroMipsMode())) {
3995 return fastEmitInst_ri(MachineInstOpcode: Mips::SRA_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3996 }
3997 if ((Subtarget->inMips16Mode())) {
3998 return fastEmitInst_ri(MachineInstOpcode: Mips::SraX16, RC: &Mips::CPU16RegsRegClass, Op0, Imm: imm1);
3999 }
4000 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
4001 return fastEmitInst_ri(MachineInstOpcode: Mips::SRA, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
4002 }
4003 return Register();
4004}
4005
4006Register fastEmit_ISD_SRA_ri_Predicate_immZExt5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4007 switch (VT.SimpleTy) {
4008 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
4009 default: return Register();
4010 }
4011}
4012
4013// FastEmit functions for ISD::SRL.
4014
4015Register fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, Register Op0, uint64_t imm1) {
4016 if (RetVT.SimpleTy != MVT::i32)
4017 return Register();
4018 if ((Subtarget->inMicroMipsMode())) {
4019 return fastEmitInst_ri(MachineInstOpcode: Mips::SRL_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
4020 }
4021 if ((Subtarget->inMips16Mode())) {
4022 return fastEmitInst_ri(MachineInstOpcode: Mips::SrlX16, RC: &Mips::CPU16RegsRegClass, Op0, Imm: imm1);
4023 }
4024 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
4025 return fastEmitInst_ri(MachineInstOpcode: Mips::SRL, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
4026 }
4027 return Register();
4028}
4029
4030Register fastEmit_ISD_SRL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4031 switch (VT.SimpleTy) {
4032 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
4033 default: return Register();
4034 }
4035}
4036
4037// Top-level FastEmit function.
4038
4039Register fastEmit_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4040 switch (Opcode) {
4041 case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
4042 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
4043 case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
4044 case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
4045 default: return Register();
4046 }
4047}
4048
4049// FastEmit functions for ISD::ROTR.
4050
4051Register fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, Register Op0, uint64_t imm1) {
4052 if (RetVT.SimpleTy != MVT::i64)
4053 return Register();
4054 if ((Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
4055 return fastEmitInst_ri(MachineInstOpcode: Mips::DROTR, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
4056 }
4057 return Register();
4058}
4059
4060Register fastEmit_ISD_ROTR_ri_Predicate_immZExt6(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4061 switch (VT.SimpleTy) {
4062 case MVT::i64: return fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
4063 default: return Register();
4064 }
4065}
4066
4067// FastEmit functions for ISD::SHL.
4068
4069Register fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, Register Op0, uint64_t imm1) {
4070 if (RetVT.SimpleTy != MVT::i64)
4071 return Register();
4072 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
4073 return fastEmitInst_ri(MachineInstOpcode: Mips::DSLL, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
4074 }
4075 return Register();
4076}
4077
4078Register fastEmit_ISD_SHL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4079 switch (VT.SimpleTy) {
4080 case MVT::i64: return fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
4081 default: return Register();
4082 }
4083}
4084
4085// FastEmit functions for ISD::SRA.
4086
4087Register fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, Register Op0, uint64_t imm1) {
4088 if (RetVT.SimpleTy != MVT::i64)
4089 return Register();
4090 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
4091 return fastEmitInst_ri(MachineInstOpcode: Mips::DSRA, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
4092 }
4093 return Register();
4094}
4095
4096Register fastEmit_ISD_SRA_ri_Predicate_immZExt6(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4097 switch (VT.SimpleTy) {
4098 case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
4099 default: return Register();
4100 }
4101}
4102
4103// FastEmit functions for ISD::SRL.
4104
4105Register fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, Register Op0, uint64_t imm1) {
4106 if (RetVT.SimpleTy != MVT::i64)
4107 return Register();
4108 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
4109 return fastEmitInst_ri(MachineInstOpcode: Mips::DSRL, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
4110 }
4111 return Register();
4112}
4113
4114Register fastEmit_ISD_SRL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4115 switch (VT.SimpleTy) {
4116 case MVT::i64: return fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
4117 default: return Register();
4118 }
4119}
4120
4121// Top-level FastEmit function.
4122
4123Register fastEmit_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4124 switch (Opcode) {
4125 case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
4126 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
4127 case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
4128 case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
4129 default: return Register();
4130 }
4131}
4132
4133// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
4134
4135Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(MVT RetVT, Register Op0, uint64_t imm1) {
4136 if (RetVT.SimpleTy != MVT::f32)
4137 return Register();
4138 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
4139 return fastEmitInst_ri(MachineInstOpcode: Mips::COPY_FW_PSEUDO, RC: &Mips::FGR32RegClass, Op0, Imm: imm1);
4140 }
4141 return Register();
4142}
4143
4144Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4145 switch (VT.SimpleTy) {
4146 case MVT::v4f32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(RetVT, Op0, imm1);
4147 default: return Register();
4148 }
4149}
4150
4151// Top-level FastEmit function.
4152
4153Register fastEmit_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4154 switch (Opcode) {
4155 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(VT, RetVT, Op0, imm1);
4156 default: return Register();
4157 }
4158}
4159
4160// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
4161
4162Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(MVT RetVT, Register Op0, uint64_t imm1) {
4163 if (RetVT.SimpleTy != MVT::f64)
4164 return Register();
4165 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
4166 return fastEmitInst_ri(MachineInstOpcode: Mips::COPY_FD_PSEUDO, RC: &Mips::FGR64RegClass, Op0, Imm: imm1);
4167 }
4168 return Register();
4169}
4170
4171Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4172 switch (VT.SimpleTy) {
4173 case MVT::v2f64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(RetVT, Op0, imm1);
4174 default: return Register();
4175 }
4176}
4177
4178// Top-level FastEmit function.
4179
4180Register fastEmit_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4181 switch (Opcode) {
4182 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(VT, RetVT, Op0, imm1);
4183 default: return Register();
4184 }
4185}
4186
4187// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
4188
4189Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(MVT RetVT, Register Op0, uint64_t imm1) {
4190 if (RetVT.SimpleTy != MVT::i32)
4191 return Register();
4192 if ((Subtarget->hasMSA())) {
4193 return fastEmitInst_ri(MachineInstOpcode: Mips::COPY_S_W, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
4194 }
4195 return Register();
4196}
4197
4198Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4199 switch (VT.SimpleTy) {
4200 case MVT::v4i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(RetVT, Op0, imm1);
4201 default: return Register();
4202 }
4203}
4204
4205// Top-level FastEmit function.
4206
4207Register fastEmit_ri_Predicate_immZExt4(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4208 switch (Opcode) {
4209 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(VT, RetVT, Op0, imm1);
4210 default: return Register();
4211 }
4212}
4213
4214// FastEmit functions for ISD::ADD.
4215
4216Register fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(MVT RetVT, Register Op0, uint64_t imm1) {
4217 if (RetVT.SimpleTy != MVT::i32)
4218 return Register();
4219 if ((Subtarget->inMicroMipsMode())) {
4220 return fastEmitInst_ri(MachineInstOpcode: Mips::ADDIUR2_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4221 }
4222 return Register();
4223}
4224
4225Register fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4226 switch (VT.SimpleTy) {
4227 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(RetVT, Op0, imm1);
4228 default: return Register();
4229 }
4230}
4231
4232// Top-level FastEmit function.
4233
4234Register fastEmit_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4235 switch (Opcode) {
4236 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(VT, RetVT, Op0, imm1);
4237 default: return Register();
4238 }
4239}
4240
4241// FastEmit functions for ISD::ADD.
4242
4243Register fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(MVT RetVT, Register Op0, uint64_t imm1) {
4244 if (RetVT.SimpleTy != MVT::i32)
4245 return Register();
4246 if ((Subtarget->inMicroMipsMode())) {
4247 return fastEmitInst_ri(MachineInstOpcode: Mips::ADDIUS5_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
4248 }
4249 return Register();
4250}
4251
4252Register fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4253 switch (VT.SimpleTy) {
4254 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(RetVT, Op0, imm1);
4255 default: return Register();
4256 }
4257}
4258
4259// Top-level FastEmit function.
4260
4261Register fastEmit_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4262 switch (Opcode) {
4263 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(VT, RetVT, Op0, imm1);
4264 default: return Register();
4265 }
4266}
4267
4268// FastEmit functions for ISD::AND.
4269
4270Register fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(MVT RetVT, Register Op0, uint64_t imm1) {
4271 if (RetVT.SimpleTy != MVT::i32)
4272 return Register();
4273 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
4274 return fastEmitInst_ri(MachineInstOpcode: Mips::ANDI16_MMR6, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4275 }
4276 if ((Subtarget->inMicroMipsMode())) {
4277 return fastEmitInst_ri(MachineInstOpcode: Mips::ANDI16_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4278 }
4279 return Register();
4280}
4281
4282Register fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4283 switch (VT.SimpleTy) {
4284 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(RetVT, Op0, imm1);
4285 default: return Register();
4286 }
4287}
4288
4289// Top-level FastEmit function.
4290
4291Register fastEmit_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4292 switch (Opcode) {
4293 case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(VT, RetVT, Op0, imm1);
4294 default: return Register();
4295 }
4296}
4297
4298// FastEmit functions for ISD::SHL.
4299
4300Register fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, Register Op0, uint64_t imm1) {
4301 if (RetVT.SimpleTy != MVT::i32)
4302 return Register();
4303 if ((Subtarget->inMicroMipsMode())) {
4304 return fastEmitInst_ri(MachineInstOpcode: Mips::SLL16_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4305 }
4306 return Register();
4307}
4308
4309Register fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4310 switch (VT.SimpleTy) {
4311 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, imm1);
4312 default: return Register();
4313 }
4314}
4315
4316// FastEmit functions for ISD::SRL.
4317
4318Register fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, Register Op0, uint64_t imm1) {
4319 if (RetVT.SimpleTy != MVT::i32)
4320 return Register();
4321 if ((Subtarget->inMicroMipsMode())) {
4322 return fastEmitInst_ri(MachineInstOpcode: Mips::SRL16_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4323 }
4324 return Register();
4325}
4326
4327Register fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4328 switch (VT.SimpleTy) {
4329 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, imm1);
4330 default: return Register();
4331 }
4332}
4333
4334// Top-level FastEmit function.
4335
4336Register fastEmit_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4337 switch (Opcode) {
4338 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, imm1);
4339 case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, imm1);
4340 default: return Register();
4341 }
4342}
4343
4344// FastEmit functions for ISD::Constant.
4345
4346Register fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) {
4347 if (RetVT.SimpleTy != MVT::i32)
4348 return Register();
4349 if ((Subtarget->inMips16Mode())) {
4350 return fastEmitInst_i(MachineInstOpcode: Mips::LwConstant32, RC: &Mips::CPU16RegsRegClass, Imm: imm0);
4351 }
4352 return Register();
4353}
4354
4355Register fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) {
4356 switch (VT.SimpleTy) {
4357 case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0);
4358 default: return Register();
4359 }
4360}
4361
4362// Top-level FastEmit function.
4363
4364Register fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override {
4365 switch (Opcode) {
4366 case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0);
4367 default: return Register();
4368 }
4369}
4370
4371