1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* "Fast" Instruction Selector for the Mips target *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10// FastEmit Immediate Predicate functions.
11static bool Predicate_immZExt5(int64_t Imm) {
12return Imm == (Imm & 0x1f);
13}
14static bool Predicate_immZExt6(int64_t Imm) {
15return Imm == (Imm & 0x3f);
16}
17static bool Predicate_immSExt6(int64_t Imm) {
18return isInt<6>(x: Imm);
19}
20static bool Predicate_immZExt4Ptr(int64_t Imm) {
21return isUInt<4>(x: Imm);
22}
23static bool Predicate_immZExt3Ptr(int64_t Imm) {
24return isUInt<3>(x: Imm);
25}
26static bool Predicate_immZExt2Ptr(int64_t Imm) {
27return isUInt<2>(x: Imm);
28}
29static bool Predicate_immZExt1Ptr(int64_t Imm) {
30return isUInt<1>(x: Imm);
31}
32static bool Predicate_immZExt4(int64_t Imm) {
33return isUInt<4>(x: Imm);
34}
35static bool Predicate_immSExtAddiur2(int64_t Imm) {
36return Imm == 1 || Imm == -1 ||
37 ((Imm % 4 == 0) &&
38 Imm < 28 && Imm > 0);
39}
40static bool Predicate_immSExtAddius5(int64_t Imm) {
41return Imm >= -8 && Imm <= 7;
42}
43static bool Predicate_immZExtAndi16(int64_t Imm) {
44return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
45 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
46 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
47}
48static bool Predicate_immZExt2Shift(int64_t Imm) {
49return Imm >= 1 && Imm <= 8;
50}
51
52
53// FastEmit functions for ISD::BITCAST.
54
55Register fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, Register Op0) {
56 if (RetVT.SimpleTy != MVT::f32)
57 return Register();
58 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
59 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_MMR6, RC: &Mips::FGR32RegClass, Op0);
60 }
61 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
62 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_MM, RC: &Mips::FGR32RegClass, Op0);
63 }
64 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
65 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1, RC: &Mips::FGR32RegClass, Op0);
66 }
67 return Register();
68}
69
70Register fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, Register Op0) {
71 if (RetVT.SimpleTy != MVT::f64)
72 return Register();
73 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
74 return fastEmitInst_r(MachineInstOpcode: Mips::DMTC1, RC: &Mips::FGR64RegClass, Op0);
75 }
76 return Register();
77}
78
79Register fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, Register Op0) {
80 if (RetVT.SimpleTy != MVT::i32)
81 return Register();
82 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
83 return fastEmitInst_r(MachineInstOpcode: Mips::MFC1_MMR6, RC: &Mips::GPR32RegClass, Op0);
84 }
85 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
86 return fastEmitInst_r(MachineInstOpcode: Mips::MFC1_MM, RC: &Mips::GPR32RegClass, Op0);
87 }
88 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
89 return fastEmitInst_r(MachineInstOpcode: Mips::MFC1, RC: &Mips::GPR32RegClass, Op0);
90 }
91 return Register();
92}
93
94Register fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, Register Op0) {
95 if (RetVT.SimpleTy != MVT::i64)
96 return Register();
97 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
98 return fastEmitInst_r(MachineInstOpcode: Mips::DMFC1, RC: &Mips::GPR64RegClass, Op0);
99 }
100 return Register();
101}
102
103Register fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, Register Op0) {
104 switch (VT.SimpleTy) {
105 case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0);
106 case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0);
107 case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0);
108 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0);
109 default: return Register();
110 }
111}
112
113// FastEmit functions for ISD::BRIND.
114
115Register fastEmit_ISD_BRIND_MVT_i32_r(MVT RetVT, Register Op0) {
116 if (RetVT.SimpleTy != MVT::isVoid)
117 return Register();
118 if ((Subtarget->inMips16Mode())) {
119 return fastEmitInst_r(MachineInstOpcode: Mips::JrcRx16, RC: &Mips::CPU16RegsRegClass, Op0);
120 }
121 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
122 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranch_MMR6, RC: &Mips::GPR32RegClass, Op0);
123 }
124 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
125 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranch_MM, RC: &Mips::GPR32RegClass, Op0);
126 }
127 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
128 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndrectHazardBranchR6, RC: &Mips::GPR32RegClass, Op0);
129 }
130 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
131 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranchR6, RC: &Mips::GPR32RegClass, Op0);
132 }
133 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
134 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectHazardBranch, RC: &Mips::GPR32RegClass, Op0);
135 }
136 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
137 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranch, RC: &Mips::GPR32RegClass, Op0);
138 }
139 return Register();
140}
141
142Register fastEmit_ISD_BRIND_MVT_i64_r(MVT RetVT, Register Op0) {
143 if (RetVT.SimpleTy != MVT::isVoid)
144 return Register();
145 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
146 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndrectHazardBranch64R6, RC: &Mips::GPR64RegClass, Op0);
147 }
148 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
149 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranch64R6, RC: &Mips::GPR64RegClass, Op0);
150 }
151 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
152 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectHazardBranch64, RC: &Mips::GPR64RegClass, Op0);
153 }
154 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
155 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoIndirectBranch64, RC: &Mips::GPR64RegClass, Op0);
156 }
157 return Register();
158}
159
160Register fastEmit_ISD_BRIND_r(MVT VT, MVT RetVT, Register Op0) {
161 switch (VT.SimpleTy) {
162 case MVT::i32: return fastEmit_ISD_BRIND_MVT_i32_r(RetVT, Op0);
163 case MVT::i64: return fastEmit_ISD_BRIND_MVT_i64_r(RetVT, Op0);
164 default: return Register();
165 }
166}
167
168// FastEmit functions for ISD::CTLZ.
169
170Register fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, Register Op0) {
171 if (RetVT.SimpleTy != MVT::i32)
172 return Register();
173 if ((Subtarget->inMicroMipsMode())) {
174 return fastEmitInst_r(MachineInstOpcode: Mips::CLZ_MM, RC: &Mips::GPR32RegClass, Op0);
175 }
176 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding())) {
177 return fastEmitInst_r(MachineInstOpcode: Mips::CLZ_R6, RC: &Mips::GPR32RegClass, Op0);
178 }
179 if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
180 return fastEmitInst_r(MachineInstOpcode: Mips::CLZ, RC: &Mips::GPR32RegClass, Op0);
181 }
182 return Register();
183}
184
185Register fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, Register Op0) {
186 if (RetVT.SimpleTy != MVT::i64)
187 return Register();
188 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
189 return fastEmitInst_r(MachineInstOpcode: Mips::DCLZ_R6, RC: &Mips::GPR64RegClass, Op0);
190 }
191 if ((Subtarget->hasMips64()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips64r6())) {
192 return fastEmitInst_r(MachineInstOpcode: Mips::DCLZ, RC: &Mips::GPR64RegClass, Op0);
193 }
194 return Register();
195}
196
197Register fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, Register Op0) {
198 if (RetVT.SimpleTy != MVT::v16i8)
199 return Register();
200 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
201 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_B, RC: &Mips::MSA128BRegClass, Op0);
202 }
203 return Register();
204}
205
206Register fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, Register Op0) {
207 if (RetVT.SimpleTy != MVT::v8i16)
208 return Register();
209 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
210 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_H, RC: &Mips::MSA128HRegClass, Op0);
211 }
212 return Register();
213}
214
215Register fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, Register Op0) {
216 if (RetVT.SimpleTy != MVT::v4i32)
217 return Register();
218 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
219 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_W, RC: &Mips::MSA128WRegClass, Op0);
220 }
221 return Register();
222}
223
224Register fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, Register Op0) {
225 if (RetVT.SimpleTy != MVT::v2i64)
226 return Register();
227 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
228 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_D, RC: &Mips::MSA128DRegClass, Op0);
229 }
230 return Register();
231}
232
233Register fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, Register Op0) {
234 switch (VT.SimpleTy) {
235 case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0);
236 case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0);
237 case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0);
238 case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0);
239 case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0);
240 case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0);
241 default: return Register();
242 }
243}
244
245// FastEmit functions for ISD::CTPOP.
246
247Register fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, Register Op0) {
248 if (RetVT.SimpleTy != MVT::i32)
249 return Register();
250 if ((Subtarget->hasCnMips())) {
251 return fastEmitInst_r(MachineInstOpcode: Mips::POP, RC: &Mips::GPR32RegClass, Op0);
252 }
253 return Register();
254}
255
256Register fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, Register Op0) {
257 if (RetVT.SimpleTy != MVT::i64)
258 return Register();
259 if ((Subtarget->hasCnMips())) {
260 return fastEmitInst_r(MachineInstOpcode: Mips::DPOP, RC: &Mips::GPR64RegClass, Op0);
261 }
262 return Register();
263}
264
265Register fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, Register Op0) {
266 if (RetVT.SimpleTy != MVT::v16i8)
267 return Register();
268 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
269 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_B, RC: &Mips::MSA128BRegClass, Op0);
270 }
271 return Register();
272}
273
274Register fastEmit_ISD_CTPOP_MVT_v8i16_r(MVT RetVT, Register Op0) {
275 if (RetVT.SimpleTy != MVT::v8i16)
276 return Register();
277 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
278 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_H, RC: &Mips::MSA128HRegClass, Op0);
279 }
280 return Register();
281}
282
283Register fastEmit_ISD_CTPOP_MVT_v4i32_r(MVT RetVT, Register Op0) {
284 if (RetVT.SimpleTy != MVT::v4i32)
285 return Register();
286 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
287 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_W, RC: &Mips::MSA128WRegClass, Op0);
288 }
289 return Register();
290}
291
292Register fastEmit_ISD_CTPOP_MVT_v2i64_r(MVT RetVT, Register Op0) {
293 if (RetVT.SimpleTy != MVT::v2i64)
294 return Register();
295 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
296 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_D, RC: &Mips::MSA128DRegClass, Op0);
297 }
298 return Register();
299}
300
301Register fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, Register Op0) {
302 switch (VT.SimpleTy) {
303 case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0);
304 case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0);
305 case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0);
306 case MVT::v8i16: return fastEmit_ISD_CTPOP_MVT_v8i16_r(RetVT, Op0);
307 case MVT::v4i32: return fastEmit_ISD_CTPOP_MVT_v4i32_r(RetVT, Op0);
308 case MVT::v2i64: return fastEmit_ISD_CTPOP_MVT_v2i64_r(RetVT, Op0);
309 default: return Register();
310 }
311}
312
313// FastEmit functions for ISD::FABS.
314
315Register fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, Register Op0) {
316 if (RetVT.SimpleTy != MVT::f32)
317 return Register();
318 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (Subtarget->inAbs2008Mode() ||TM.Options.NoNaNsFPMath)) {
319 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_S_MM, RC: &Mips::FGR32RegClass, Op0);
320 }
321 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode()) && (Subtarget->inAbs2008Mode() ||TM.Options.NoNaNsFPMath)) {
322 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_S, RC: &Mips::FGR32RegClass, Op0);
323 }
324 return Register();
325}
326
327Register fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, Register Op0) {
328 if (RetVT.SimpleTy != MVT::f64)
329 return Register();
330 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
331 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D64_MM, RC: &Mips::FGR64RegClass, Op0);
332 }
333 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
334 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D32_MM, RC: &Mips::AFGR64RegClass, Op0);
335 }
336 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode()) && (Subtarget->inAbs2008Mode() ||TM.Options.NoNaNsFPMath)) {
337 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D64, RC: &Mips::FGR64RegClass, Op0);
338 }
339 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode()) && (Subtarget->inAbs2008Mode() ||TM.Options.NoNaNsFPMath)) {
340 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D32, RC: &Mips::AFGR64RegClass, Op0);
341 }
342 return Register();
343}
344
345Register fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, Register Op0) {
346 if (RetVT.SimpleTy != MVT::v4f32)
347 return Register();
348 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
349 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_W, RC: &Mips::MSA128WRegClass, Op0);
350 }
351 return Register();
352}
353
354Register fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, Register Op0) {
355 if (RetVT.SimpleTy != MVT::v2f64)
356 return Register();
357 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
358 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D, RC: &Mips::MSA128DRegClass, Op0);
359 }
360 return Register();
361}
362
363Register fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, Register Op0) {
364 switch (VT.SimpleTy) {
365 case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0);
366 case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0);
367 case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0);
368 case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0);
369 default: return Register();
370 }
371}
372
373// FastEmit functions for ISD::FEXP2.
374
375Register fastEmit_ISD_FEXP2_MVT_v4f32_r(MVT RetVT, Register Op0) {
376 if (RetVT.SimpleTy != MVT::v4f32)
377 return Register();
378 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
379 return fastEmitInst_r(MachineInstOpcode: Mips::FEXP2_W_1_PSEUDO, RC: &Mips::MSA128WRegClass, Op0);
380 }
381 return Register();
382}
383
384Register fastEmit_ISD_FEXP2_MVT_v2f64_r(MVT RetVT, Register Op0) {
385 if (RetVT.SimpleTy != MVT::v2f64)
386 return Register();
387 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
388 return fastEmitInst_r(MachineInstOpcode: Mips::FEXP2_D_1_PSEUDO, RC: &Mips::MSA128DRegClass, Op0);
389 }
390 return Register();
391}
392
393Register fastEmit_ISD_FEXP2_r(MVT VT, MVT RetVT, Register Op0) {
394 switch (VT.SimpleTy) {
395 case MVT::v4f32: return fastEmit_ISD_FEXP2_MVT_v4f32_r(RetVT, Op0);
396 case MVT::v2f64: return fastEmit_ISD_FEXP2_MVT_v2f64_r(RetVT, Op0);
397 default: return Register();
398 }
399}
400
401// FastEmit functions for ISD::FLOG2.
402
403Register fastEmit_ISD_FLOG2_MVT_v4f32_r(MVT RetVT, Register Op0) {
404 if (RetVT.SimpleTy != MVT::v4f32)
405 return Register();
406 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
407 return fastEmitInst_r(MachineInstOpcode: Mips::FLOG2_W, RC: &Mips::MSA128WRegClass, Op0);
408 }
409 return Register();
410}
411
412Register fastEmit_ISD_FLOG2_MVT_v2f64_r(MVT RetVT, Register Op0) {
413 if (RetVT.SimpleTy != MVT::v2f64)
414 return Register();
415 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
416 return fastEmitInst_r(MachineInstOpcode: Mips::FLOG2_D, RC: &Mips::MSA128DRegClass, Op0);
417 }
418 return Register();
419}
420
421Register fastEmit_ISD_FLOG2_r(MVT VT, MVT RetVT, Register Op0) {
422 switch (VT.SimpleTy) {
423 case MVT::v4f32: return fastEmit_ISD_FLOG2_MVT_v4f32_r(RetVT, Op0);
424 case MVT::v2f64: return fastEmit_ISD_FLOG2_MVT_v2f64_r(RetVT, Op0);
425 default: return Register();
426 }
427}
428
429// FastEmit functions for ISD::FNEG.
430
431Register fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, Register Op0) {
432 if (RetVT.SimpleTy != MVT::f32)
433 return Register();
434 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
435 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_S_MMR6, RC: &Mips::FGR32RegClass, Op0);
436 }
437 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
438 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_S_MM, RC: &Mips::FGR32RegClass, Op0);
439 }
440 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
441 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_S, RC: &Mips::FGR32RegClass, Op0);
442 }
443 return Register();
444}
445
446Register fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, Register Op0) {
447 if (RetVT.SimpleTy != MVT::f64)
448 return Register();
449 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
450 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D64_MM, RC: &Mips::FGR64RegClass, Op0);
451 }
452 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
453 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D32_MM, RC: &Mips::AFGR64RegClass, Op0);
454 }
455 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
456 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D64, RC: &Mips::FGR64RegClass, Op0);
457 }
458 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
459 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D32, RC: &Mips::AFGR64RegClass, Op0);
460 }
461 return Register();
462}
463
464Register fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, Register Op0) {
465 switch (VT.SimpleTy) {
466 case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0);
467 case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0);
468 default: return Register();
469 }
470}
471
472// FastEmit functions for ISD::FP_EXTEND.
473
474Register fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(Register Op0) {
475 if ((Subtarget->hasMSA())) {
476 return fastEmitInst_r(MachineInstOpcode: Mips::MSA_FP_EXTEND_W_PSEUDO, RC: &Mips::FGR32RegClass, Op0);
477 }
478 return Register();
479}
480
481Register fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(Register Op0) {
482 if ((Subtarget->hasMSA())) {
483 return fastEmitInst_r(MachineInstOpcode: Mips::MSA_FP_EXTEND_D_PSEUDO, RC: &Mips::FGR64RegClass, Op0);
484 }
485 return Register();
486}
487
488Register fastEmit_ISD_FP_EXTEND_MVT_f16_r(MVT RetVT, Register Op0) {
489switch (RetVT.SimpleTy) {
490 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f32_r(Op0);
491 case MVT::f64: return fastEmit_ISD_FP_EXTEND_MVT_f16_MVT_f64_r(Op0);
492 default: return Register();
493}
494}
495
496Register fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, Register Op0) {
497 if (RetVT.SimpleTy != MVT::f64)
498 return Register();
499 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit())) {
500 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D32_S_MM, RC: &Mips::AFGR64RegClass, Op0);
501 }
502 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())) {
503 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D64_S_MM, RC: &Mips::FGR64RegClass, Op0);
504 }
505 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
506 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D64_S, RC: &Mips::FGR64RegClass, Op0);
507 }
508 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
509 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D32_S, RC: &Mips::AFGR64RegClass, Op0);
510 }
511 return Register();
512}
513
514Register fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
515 switch (VT.SimpleTy) {
516 case MVT::f16: return fastEmit_ISD_FP_EXTEND_MVT_f16_r(RetVT, Op0);
517 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0);
518 default: return Register();
519 }
520}
521
522// FastEmit functions for ISD::FP_ROUND.
523
524Register fastEmit_ISD_FP_ROUND_MVT_f32_r(MVT RetVT, Register Op0) {
525 if (RetVT.SimpleTy != MVT::f16)
526 return Register();
527 if ((Subtarget->hasMSA())) {
528 return fastEmitInst_r(MachineInstOpcode: Mips::MSA_FP_ROUND_W_PSEUDO, RC: &Mips::MSA128F16RegClass, Op0);
529 }
530 return Register();
531}
532
533Register fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(Register Op0) {
534 if ((Subtarget->hasMSA())) {
535 return fastEmitInst_r(MachineInstOpcode: Mips::MSA_FP_ROUND_D_PSEUDO, RC: &Mips::MSA128F16RegClass, Op0);
536 }
537 return Register();
538}
539
540Register fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(Register Op0) {
541 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit())) {
542 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D32_MM, RC: &Mips::FGR32RegClass, Op0);
543 }
544 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())) {
545 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D64_MM, RC: &Mips::FGR32RegClass, Op0);
546 }
547 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
548 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D64, RC: &Mips::FGR32RegClass, Op0);
549 }
550 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
551 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D32, RC: &Mips::FGR32RegClass, Op0);
552 }
553 return Register();
554}
555
556Register fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, Register Op0) {
557switch (RetVT.SimpleTy) {
558 case MVT::f16: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f16_r(Op0);
559 case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f64_MVT_f32_r(Op0);
560 default: return Register();
561}
562}
563
564Register fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, Register Op0) {
565 switch (VT.SimpleTy) {
566 case MVT::f32: return fastEmit_ISD_FP_ROUND_MVT_f32_r(RetVT, Op0);
567 case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0);
568 default: return Register();
569 }
570}
571
572// FastEmit functions for ISD::FP_TO_SINT.
573
574Register fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
575 if (RetVT.SimpleTy != MVT::v4i32)
576 return Register();
577 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
578 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_S_W, RC: &Mips::MSA128WRegClass, Op0);
579 }
580 return Register();
581}
582
583Register fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
584 if (RetVT.SimpleTy != MVT::v2i64)
585 return Register();
586 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
587 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_S_D, RC: &Mips::MSA128DRegClass, Op0);
588 }
589 return Register();
590}
591
592Register fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, Register Op0) {
593 switch (VT.SimpleTy) {
594 case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0);
595 case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0);
596 default: return Register();
597 }
598}
599
600// FastEmit functions for ISD::FP_TO_UINT.
601
602Register fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
603 if (RetVT.SimpleTy != MVT::v4i32)
604 return Register();
605 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
606 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_U_W, RC: &Mips::MSA128WRegClass, Op0);
607 }
608 return Register();
609}
610
611Register fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
612 if (RetVT.SimpleTy != MVT::v2i64)
613 return Register();
614 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
615 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_U_D, RC: &Mips::MSA128DRegClass, Op0);
616 }
617 return Register();
618}
619
620Register fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, Register Op0) {
621 switch (VT.SimpleTy) {
622 case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0);
623 case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0);
624 default: return Register();
625 }
626}
627
628// FastEmit functions for ISD::FRINT.
629
630Register fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
631 if (RetVT.SimpleTy != MVT::v4f32)
632 return Register();
633 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
634 return fastEmitInst_r(MachineInstOpcode: Mips::FRINT_W, RC: &Mips::MSA128WRegClass, Op0);
635 }
636 return Register();
637}
638
639Register fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
640 if (RetVT.SimpleTy != MVT::v2f64)
641 return Register();
642 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
643 return fastEmitInst_r(MachineInstOpcode: Mips::FRINT_D, RC: &Mips::MSA128DRegClass, Op0);
644 }
645 return Register();
646}
647
648Register fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, Register Op0) {
649 switch (VT.SimpleTy) {
650 case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0);
651 case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0);
652 default: return Register();
653 }
654}
655
656// FastEmit functions for ISD::FSQRT.
657
658Register fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, Register Op0) {
659 if (RetVT.SimpleTy != MVT::f32)
660 return Register();
661 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
662 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_S_MM, RC: &Mips::FGR32RegClass, Op0);
663 }
664 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
665 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_S, RC: &Mips::FGR32RegClass, Op0);
666 }
667 return Register();
668}
669
670Register fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, Register Op0) {
671 if (RetVT.SimpleTy != MVT::f64)
672 return Register();
673 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
674 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D64_MM, RC: &Mips::FGR64RegClass, Op0);
675 }
676 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
677 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D32_MM, RC: &Mips::AFGR64RegClass, Op0);
678 }
679 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
680 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D64, RC: &Mips::FGR64RegClass, Op0);
681 }
682 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
683 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D32, RC: &Mips::AFGR64RegClass, Op0);
684 }
685 return Register();
686}
687
688Register fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, Register Op0) {
689 if (RetVT.SimpleTy != MVT::v4f32)
690 return Register();
691 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
692 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_W, RC: &Mips::MSA128WRegClass, Op0);
693 }
694 return Register();
695}
696
697Register fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, Register Op0) {
698 if (RetVT.SimpleTy != MVT::v2f64)
699 return Register();
700 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
701 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D, RC: &Mips::MSA128DRegClass, Op0);
702 }
703 return Register();
704}
705
706Register fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, Register Op0) {
707 switch (VT.SimpleTy) {
708 case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0);
709 case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0);
710 case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0);
711 case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0);
712 default: return Register();
713 }
714}
715
716// FastEmit functions for ISD::SIGN_EXTEND.
717
718Register fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, Register Op0) {
719 if (RetVT.SimpleTy != MVT::i64)
720 return Register();
721 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())) {
722 return fastEmitInst_r(MachineInstOpcode: Mips::SLL64_32, RC: &Mips::GPR64RegClass, Op0);
723 }
724 return Register();
725}
726
727Register fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
728 switch (VT.SimpleTy) {
729 case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0);
730 default: return Register();
731 }
732}
733
734// FastEmit functions for ISD::SINT_TO_FP.
735
736Register fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
737 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_S_W, RC: &Mips::FGR32RegClass, Op0);
738}
739
740Register fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
741 if ((Subtarget->isFP64bit())) {
742 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D64_W, RC: &Mips::FGR64RegClass, Op0);
743 }
744 if ((!Subtarget->isFP64bit())) {
745 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D32_W, RC: &Mips::AFGR64RegClass, Op0);
746 }
747 return Register();
748}
749
750Register fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
751switch (RetVT.SimpleTy) {
752 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
753 case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
754 default: return Register();
755}
756}
757
758Register fastEmit_ISD_SINT_TO_FP_MVT_i64_r(MVT RetVT, Register Op0) {
759 if (RetVT.SimpleTy != MVT::f64)
760 return Register();
761 if ((Subtarget->isFP64bit())) {
762 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D64_L, RC: &Mips::FGR64RegClass, Op0);
763 }
764 return Register();
765}
766
767Register fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
768 if (RetVT.SimpleTy != MVT::v4f32)
769 return Register();
770 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
771 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_S_W, RC: &Mips::MSA128WRegClass, Op0);
772 }
773 return Register();
774}
775
776Register fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, Register Op0) {
777 if (RetVT.SimpleTy != MVT::v2f64)
778 return Register();
779 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
780 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_S_D, RC: &Mips::MSA128DRegClass, Op0);
781 }
782 return Register();
783}
784
785Register fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
786 switch (VT.SimpleTy) {
787 case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0);
788 case MVT::i64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_r(RetVT, Op0);
789 case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
790 case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
791 default: return Register();
792 }
793}
794
795// FastEmit functions for ISD::STRICT_FP_EXTEND.
796
797Register fastEmit_ISD_STRICT_FP_EXTEND_MVT_f32_r(MVT RetVT, Register Op0) {
798 if (RetVT.SimpleTy != MVT::f64)
799 return Register();
800 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
801 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D64_S, RC: &Mips::FGR64RegClass, Op0);
802 }
803 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
804 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D32_S, RC: &Mips::AFGR64RegClass, Op0);
805 }
806 return Register();
807}
808
809Register fastEmit_ISD_STRICT_FP_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
810 switch (VT.SimpleTy) {
811 case MVT::f32: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_f32_r(RetVT, Op0);
812 default: return Register();
813 }
814}
815
816// FastEmit functions for ISD::STRICT_FP_ROUND.
817
818Register fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(MVT RetVT, Register Op0) {
819 if (RetVT.SimpleTy != MVT::f32)
820 return Register();
821 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
822 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D64, RC: &Mips::FGR32RegClass, Op0);
823 }
824 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
825 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D32, RC: &Mips::FGR32RegClass, Op0);
826 }
827 return Register();
828}
829
830Register fastEmit_ISD_STRICT_FP_ROUND_r(MVT VT, MVT RetVT, Register Op0) {
831 switch (VT.SimpleTy) {
832 case MVT::f64: return fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(RetVT, Op0);
833 default: return Register();
834 }
835}
836
837// FastEmit functions for ISD::STRICT_FSQRT.
838
839Register fastEmit_ISD_STRICT_FSQRT_MVT_f32_r(MVT RetVT, Register Op0) {
840 if (RetVT.SimpleTy != MVT::f32)
841 return Register();
842 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
843 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_S, RC: &Mips::FGR32RegClass, Op0);
844 }
845 return Register();
846}
847
848Register fastEmit_ISD_STRICT_FSQRT_MVT_f64_r(MVT RetVT, Register Op0) {
849 if (RetVT.SimpleTy != MVT::f64)
850 return Register();
851 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
852 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D64, RC: &Mips::FGR64RegClass, Op0);
853 }
854 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
855 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D32, RC: &Mips::AFGR64RegClass, Op0);
856 }
857 return Register();
858}
859
860Register fastEmit_ISD_STRICT_FSQRT_r(MVT VT, MVT RetVT, Register Op0) {
861 switch (VT.SimpleTy) {
862 case MVT::f32: return fastEmit_ISD_STRICT_FSQRT_MVT_f32_r(RetVT, Op0);
863 case MVT::f64: return fastEmit_ISD_STRICT_FSQRT_MVT_f64_r(RetVT, Op0);
864 default: return Register();
865 }
866}
867
868// FastEmit functions for ISD::STRICT_SINT_TO_FP.
869
870Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
871 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_S_W, RC: &Mips::FGR32RegClass, Op0);
872}
873
874Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
875 if ((Subtarget->isFP64bit())) {
876 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D64_W, RC: &Mips::FGR64RegClass, Op0);
877 }
878 if ((!Subtarget->isFP64bit())) {
879 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D32_W, RC: &Mips::AFGR64RegClass, Op0);
880 }
881 return Register();
882}
883
884Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
885switch (RetVT.SimpleTy) {
886 case MVT::f32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
887 case MVT::f64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
888 default: return Register();
889}
890}
891
892Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_r(MVT RetVT, Register Op0) {
893 if (RetVT.SimpleTy != MVT::f64)
894 return Register();
895 if ((Subtarget->isFP64bit())) {
896 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D64_L, RC: &Mips::FGR64RegClass, Op0);
897 }
898 return Register();
899}
900
901Register fastEmit_ISD_STRICT_SINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
902 switch (VT.SimpleTy) {
903 case MVT::i32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(RetVT, Op0);
904 case MVT::i64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_r(RetVT, Op0);
905 default: return Register();
906 }
907}
908
909// FastEmit functions for ISD::UINT_TO_FP.
910
911Register fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
912 if (RetVT.SimpleTy != MVT::v4f32)
913 return Register();
914 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
915 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_U_W, RC: &Mips::MSA128WRegClass, Op0);
916 }
917 return Register();
918}
919
920Register fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, Register Op0) {
921 if (RetVT.SimpleTy != MVT::v2f64)
922 return Register();
923 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
924 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_U_D, RC: &Mips::MSA128DRegClass, Op0);
925 }
926 return Register();
927}
928
929Register fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
930 switch (VT.SimpleTy) {
931 case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
932 case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
933 default: return Register();
934 }
935}
936
937// FastEmit functions for MipsISD::JmpLink.
938
939Register fastEmit_MipsISD_JmpLink_MVT_i32_r(MVT RetVT, Register Op0) {
940 if (RetVT.SimpleTy != MVT::isVoid)
941 return Register();
942 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
943 return fastEmitInst_r(MachineInstOpcode: Mips::JALR16_MM, RC: &Mips::GPR32RegClass, Op0);
944 }
945 if ((Subtarget->inMips16Mode())) {
946 return fastEmitInst_r(MachineInstOpcode: Mips::JumpLinkReg16, RC: &Mips::CPU16RegsRegClass, Op0);
947 }
948 if ((!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
949 return fastEmitInst_r(MachineInstOpcode: Mips::JALRHBPseudo, RC: &Mips::GPR32RegClass, Op0);
950 }
951 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode())) {
952 return fastEmitInst_r(MachineInstOpcode: Mips::JALRPseudo, RC: &Mips::GPR32RegClass, Op0);
953 }
954 return Register();
955}
956
957Register fastEmit_MipsISD_JmpLink_MVT_i64_r(MVT RetVT, Register Op0) {
958 if (RetVT.SimpleTy != MVT::isVoid)
959 return Register();
960 if ((Subtarget->isABI_N64()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
961 return fastEmitInst_r(MachineInstOpcode: Mips::JALRHB64Pseudo, RC: &Mips::GPR64RegClass, Op0);
962 }
963 if ((Subtarget->isABI_N64()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMips16Mode())) {
964 return fastEmitInst_r(MachineInstOpcode: Mips::JALR64Pseudo, RC: &Mips::GPR64RegClass, Op0);
965 }
966 return Register();
967}
968
969Register fastEmit_MipsISD_JmpLink_r(MVT VT, MVT RetVT, Register Op0) {
970 switch (VT.SimpleTy) {
971 case MVT::i32: return fastEmit_MipsISD_JmpLink_MVT_i32_r(RetVT, Op0);
972 case MVT::i64: return fastEmit_MipsISD_JmpLink_MVT_i64_r(RetVT, Op0);
973 default: return Register();
974 }
975}
976
977// FastEmit functions for MipsISD::MFHI.
978
979Register fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(Register Op0) {
980 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
981 return fastEmitInst_r(MachineInstOpcode: Mips::MFHI_DSP_MM, RC: &Mips::GPR32RegClass, Op0);
982 }
983 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
984 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFHI_MM, RC: &Mips::GPR32RegClass, Op0);
985 }
986 if ((Subtarget->hasDSP())) {
987 return fastEmitInst_r(MachineInstOpcode: Mips::MFHI_DSP, RC: &Mips::GPR32RegClass, Op0);
988 }
989 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
990 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFHI, RC: &Mips::GPR32RegClass, Op0);
991 }
992 return Register();
993}
994
995Register fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(Register Op0) {
996 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
997 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFHI64, RC: &Mips::GPR64RegClass, Op0);
998 }
999 return Register();
1000}
1001
1002Register fastEmit_MipsISD_MFHI_MVT_Untyped_r(MVT RetVT, Register Op0) {
1003switch (RetVT.SimpleTy) {
1004 case MVT::i32: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(Op0);
1005 case MVT::i64: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(Op0);
1006 default: return Register();
1007}
1008}
1009
1010Register fastEmit_MipsISD_MFHI_r(MVT VT, MVT RetVT, Register Op0) {
1011 switch (VT.SimpleTy) {
1012 case MVT::Untyped: return fastEmit_MipsISD_MFHI_MVT_Untyped_r(RetVT, Op0);
1013 default: return Register();
1014 }
1015}
1016
1017// FastEmit functions for MipsISD::MFLO.
1018
1019Register fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(Register Op0) {
1020 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
1021 return fastEmitInst_r(MachineInstOpcode: Mips::MFLO_DSP_MM, RC: &Mips::GPR32RegClass, Op0);
1022 }
1023 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
1024 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFLO_MM, RC: &Mips::GPR32RegClass, Op0);
1025 }
1026 if ((Subtarget->hasDSP())) {
1027 return fastEmitInst_r(MachineInstOpcode: Mips::MFLO_DSP, RC: &Mips::GPR32RegClass, Op0);
1028 }
1029 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
1030 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFLO, RC: &Mips::GPR32RegClass, Op0);
1031 }
1032 return Register();
1033}
1034
1035Register fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(Register Op0) {
1036 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
1037 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFLO64, RC: &Mips::GPR64RegClass, Op0);
1038 }
1039 return Register();
1040}
1041
1042Register fastEmit_MipsISD_MFLO_MVT_Untyped_r(MVT RetVT, Register Op0) {
1043switch (RetVT.SimpleTy) {
1044 case MVT::i32: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(Op0);
1045 case MVT::i64: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(Op0);
1046 default: return Register();
1047}
1048}
1049
1050Register fastEmit_MipsISD_MFLO_r(MVT VT, MVT RetVT, Register Op0) {
1051 switch (VT.SimpleTy) {
1052 case MVT::Untyped: return fastEmit_MipsISD_MFLO_MVT_Untyped_r(RetVT, Op0);
1053 default: return Register();
1054 }
1055}
1056
1057// FastEmit functions for MipsISD::MTC1_D64.
1058
1059Register fastEmit_MipsISD_MTC1_D64_MVT_i32_r(MVT RetVT, Register Op0) {
1060 if (RetVT.SimpleTy != MVT::f64)
1061 return Register();
1062 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit())) {
1063 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_D64_MM, RC: &Mips::FGR64RegClass, Op0);
1064 }
1065 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
1066 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_D64, RC: &Mips::FGR64RegClass, Op0);
1067 }
1068 return Register();
1069}
1070
1071Register fastEmit_MipsISD_MTC1_D64_r(MVT VT, MVT RetVT, Register Op0) {
1072 switch (VT.SimpleTy) {
1073 case MVT::i32: return fastEmit_MipsISD_MTC1_D64_MVT_i32_r(RetVT, Op0);
1074 default: return Register();
1075 }
1076}
1077
1078// FastEmit functions for MipsISD::TailCall.
1079
1080Register fastEmit_MipsISD_TailCall_MVT_i32_r(MVT RetVT, Register Op0) {
1081 if (RetVT.SimpleTy != MVT::isVoid)
1082 return Register();
1083 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1084 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREG_MMR6, RC: &Mips::GPR32RegClass, Op0);
1085 }
1086 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1087 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREG_MM, RC: &Mips::GPR32RegClass, Op0);
1088 }
1089 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
1090 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLHBR6REG, RC: &Mips::GPR32RegClass, Op0);
1091 }
1092 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
1093 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLR6REG, RC: &Mips::GPR32RegClass, Op0);
1094 }
1095 if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
1096 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREGHB, RC: &Mips::GPR32RegClass, Op0);
1097 }
1098 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
1099 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREG, RC: &Mips::GPR32RegClass, Op0);
1100 }
1101 return Register();
1102}
1103
1104Register fastEmit_MipsISD_TailCall_MVT_i64_r(MVT RetVT, Register Op0) {
1105 if (RetVT.SimpleTy != MVT::isVoid)
1106 return Register();
1107 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (Subtarget->useIndirectJumpsHazard())) {
1108 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLHB64R6REG, RC: &Mips::GPR64RegClass, Op0);
1109 }
1110 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode())) {
1111 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALL64R6REG, RC: &Mips::GPR64RegClass, Op0);
1112 }
1113 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (Subtarget->useIndirectJumpsHazard())) {
1114 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREGHB64, RC: &Mips::GPR64RegClass, Op0);
1115 }
1116 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isABI_N64()) && (!Subtarget->useIndirectJumpsHazard()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->inMips16Mode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
1117 return fastEmitInst_r(MachineInstOpcode: Mips::TAILCALLREG64, RC: &Mips::GPR64RegClass, Op0);
1118 }
1119 return Register();
1120}
1121
1122Register fastEmit_MipsISD_TailCall_r(MVT VT, MVT RetVT, Register Op0) {
1123 switch (VT.SimpleTy) {
1124 case MVT::i32: return fastEmit_MipsISD_TailCall_MVT_i32_r(RetVT, Op0);
1125 case MVT::i64: return fastEmit_MipsISD_TailCall_MVT_i64_r(RetVT, Op0);
1126 default: return Register();
1127 }
1128}
1129
1130// FastEmit functions for MipsISD::TruncIntFP.
1131
1132Register fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(Register Op0) {
1133 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1134 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_S_MMR6, RC: &Mips::FGR32RegClass, Op0);
1135 }
1136 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1137 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_S_MM, RC: &Mips::FGR32RegClass, Op0);
1138 }
1139 if ((Subtarget->hasStandardEncoding())) {
1140 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_S, RC: &Mips::FGR32RegClass, Op0);
1141 }
1142 return Register();
1143}
1144
1145Register fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(Register Op0) {
1146 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
1147 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_L_S, RC: &Mips::FGR64RegClass, Op0);
1148 }
1149 return Register();
1150}
1151
1152Register fastEmit_MipsISD_TruncIntFP_MVT_f32_r(MVT RetVT, Register Op0) {
1153switch (RetVT.SimpleTy) {
1154 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(Op0);
1155 case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(Op0);
1156 default: return Register();
1157}
1158}
1159
1160Register fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(Register Op0) {
1161 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1162 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_D_MMR6, RC: &Mips::FGR32RegClass, Op0);
1163 }
1164 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())) {
1165 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_W_D64_MM, RC: &Mips::FGR32RegClass, Op0);
1166 }
1167 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())) {
1168 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_MM, RC: &Mips::FGR32RegClass, Op0);
1169 }
1170 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
1171 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_D64, RC: &Mips::FGR32RegClass, Op0);
1172 }
1173 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1174 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_D32, RC: &Mips::FGR32RegClass, Op0);
1175 }
1176 return Register();
1177}
1178
1179Register fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(Register Op0) {
1180 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit())) {
1181 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_L_D64, RC: &Mips::FGR64RegClass, Op0);
1182 }
1183 return Register();
1184}
1185
1186Register fastEmit_MipsISD_TruncIntFP_MVT_f64_r(MVT RetVT, Register Op0) {
1187switch (RetVT.SimpleTy) {
1188 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(Op0);
1189 case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(Op0);
1190 default: return Register();
1191}
1192}
1193
1194Register fastEmit_MipsISD_TruncIntFP_r(MVT VT, MVT RetVT, Register Op0) {
1195 switch (VT.SimpleTy) {
1196 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_r(RetVT, Op0);
1197 case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_r(RetVT, Op0);
1198 default: return Register();
1199 }
1200}
1201
1202// FastEmit functions for MipsISD::VALL_NONZERO.
1203
1204Register fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(MVT RetVT, Register Op0) {
1205 if (RetVT.SimpleTy != MVT::i32)
1206 return Register();
1207 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_B_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1208}
1209
1210Register fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(MVT RetVT, Register Op0) {
1211 if (RetVT.SimpleTy != MVT::i32)
1212 return Register();
1213 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_H_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1214}
1215
1216Register fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(MVT RetVT, Register Op0) {
1217 if (RetVT.SimpleTy != MVT::i32)
1218 return Register();
1219 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_W_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1220}
1221
1222Register fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(MVT RetVT, Register Op0) {
1223 if (RetVT.SimpleTy != MVT::i32)
1224 return Register();
1225 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_D_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1226}
1227
1228Register fastEmit_MipsISD_VALL_NONZERO_r(MVT VT, MVT RetVT, Register Op0) {
1229 switch (VT.SimpleTy) {
1230 case MVT::v16i8: return fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(RetVT, Op0);
1231 case MVT::v8i16: return fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(RetVT, Op0);
1232 case MVT::v4i32: return fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(RetVT, Op0);
1233 case MVT::v2i64: return fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(RetVT, Op0);
1234 default: return Register();
1235 }
1236}
1237
1238// FastEmit functions for MipsISD::VALL_ZERO.
1239
1240Register fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(MVT RetVT, Register Op0) {
1241 if (RetVT.SimpleTy != MVT::i32)
1242 return Register();
1243 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_B_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1244}
1245
1246Register fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(MVT RetVT, Register Op0) {
1247 if (RetVT.SimpleTy != MVT::i32)
1248 return Register();
1249 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_H_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1250}
1251
1252Register fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(MVT RetVT, Register Op0) {
1253 if (RetVT.SimpleTy != MVT::i32)
1254 return Register();
1255 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_W_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1256}
1257
1258Register fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(MVT RetVT, Register Op0) {
1259 if (RetVT.SimpleTy != MVT::i32)
1260 return Register();
1261 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_D_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1262}
1263
1264Register fastEmit_MipsISD_VALL_ZERO_r(MVT VT, MVT RetVT, Register Op0) {
1265 switch (VT.SimpleTy) {
1266 case MVT::v16i8: return fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(RetVT, Op0);
1267 case MVT::v8i16: return fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(RetVT, Op0);
1268 case MVT::v4i32: return fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(RetVT, Op0);
1269 case MVT::v2i64: return fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(RetVT, Op0);
1270 default: return Register();
1271 }
1272}
1273
1274// FastEmit functions for MipsISD::VANY_NONZERO.
1275
1276Register fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(MVT RetVT, Register Op0) {
1277 if (RetVT.SimpleTy != MVT::i32)
1278 return Register();
1279 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_V_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1280}
1281
1282Register fastEmit_MipsISD_VANY_NONZERO_r(MVT VT, MVT RetVT, Register Op0) {
1283 switch (VT.SimpleTy) {
1284 case MVT::v16i8: return fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(RetVT, Op0);
1285 default: return Register();
1286 }
1287}
1288
1289// FastEmit functions for MipsISD::VANY_ZERO.
1290
1291Register fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(MVT RetVT, Register Op0) {
1292 if (RetVT.SimpleTy != MVT::i32)
1293 return Register();
1294 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_V_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1295}
1296
1297Register fastEmit_MipsISD_VANY_ZERO_r(MVT VT, MVT RetVT, Register Op0) {
1298 switch (VT.SimpleTy) {
1299 case MVT::v16i8: return fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(RetVT, Op0);
1300 default: return Register();
1301 }
1302}
1303
1304// Top-level FastEmit function.
1305
1306Register fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, Register Op0) override {
1307 switch (Opcode) {
1308 case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0);
1309 case ISD::BRIND: return fastEmit_ISD_BRIND_r(VT, RetVT, Op0);
1310 case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0);
1311 case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0);
1312 case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0);
1313 case ISD::FEXP2: return fastEmit_ISD_FEXP2_r(VT, RetVT, Op0);
1314 case ISD::FLOG2: return fastEmit_ISD_FLOG2_r(VT, RetVT, Op0);
1315 case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0);
1316 case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0);
1317 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0);
1318 case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0);
1319 case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0);
1320 case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0);
1321 case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0);
1322 case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0);
1323 case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0);
1324 case ISD::STRICT_FP_EXTEND: return fastEmit_ISD_STRICT_FP_EXTEND_r(VT, RetVT, Op0);
1325 case ISD::STRICT_FP_ROUND: return fastEmit_ISD_STRICT_FP_ROUND_r(VT, RetVT, Op0);
1326 case ISD::STRICT_FSQRT: return fastEmit_ISD_STRICT_FSQRT_r(VT, RetVT, Op0);
1327 case ISD::STRICT_SINT_TO_FP: return fastEmit_ISD_STRICT_SINT_TO_FP_r(VT, RetVT, Op0);
1328 case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0);
1329 case MipsISD::JmpLink: return fastEmit_MipsISD_JmpLink_r(VT, RetVT, Op0);
1330 case MipsISD::MFHI: return fastEmit_MipsISD_MFHI_r(VT, RetVT, Op0);
1331 case MipsISD::MFLO: return fastEmit_MipsISD_MFLO_r(VT, RetVT, Op0);
1332 case MipsISD::MTC1_D64: return fastEmit_MipsISD_MTC1_D64_r(VT, RetVT, Op0);
1333 case MipsISD::TailCall: return fastEmit_MipsISD_TailCall_r(VT, RetVT, Op0);
1334 case MipsISD::TruncIntFP: return fastEmit_MipsISD_TruncIntFP_r(VT, RetVT, Op0);
1335 case MipsISD::VALL_NONZERO: return fastEmit_MipsISD_VALL_NONZERO_r(VT, RetVT, Op0);
1336 case MipsISD::VALL_ZERO: return fastEmit_MipsISD_VALL_ZERO_r(VT, RetVT, Op0);
1337 case MipsISD::VANY_NONZERO: return fastEmit_MipsISD_VANY_NONZERO_r(VT, RetVT, Op0);
1338 case MipsISD::VANY_ZERO: return fastEmit_MipsISD_VANY_ZERO_r(VT, RetVT, Op0);
1339 default: return Register();
1340 }
1341}
1342
1343// FastEmit functions for ISD::ADD.
1344
1345Register fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1346 if (RetVT.SimpleTy != MVT::i32)
1347 return Register();
1348 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1349 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDU16_MMR6, RC: &Mips::GPRMM16RegClass, Op0, Op1);
1350 }
1351 if ((Subtarget->inMips16Mode())) {
1352 return fastEmitInst_rr(MachineInstOpcode: Mips::AdduRxRyRz16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
1353 }
1354 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1355 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDu_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
1356 }
1357 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1358 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDu, RC: &Mips::GPR32RegClass, Op0, Op1);
1359 }
1360 return Register();
1361}
1362
1363Register fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1364 if (RetVT.SimpleTy != MVT::i64)
1365 return Register();
1366 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1367 return fastEmitInst_rr(MachineInstOpcode: Mips::DADDu, RC: &Mips::GPR64RegClass, Op0, Op1);
1368 }
1369 return Register();
1370}
1371
1372Register fastEmit_ISD_ADD_MVT_v4i8_rr(MVT RetVT, Register Op0, Register Op1) {
1373 if (RetVT.SimpleTy != MVT::v4i8)
1374 return Register();
1375 if ((Subtarget->hasDSP())) {
1376 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDU_QB, RC: &Mips::DSPRRegClass, Op0, Op1);
1377 }
1378 return Register();
1379}
1380
1381Register fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1382 if (RetVT.SimpleTy != MVT::v16i8)
1383 return Register();
1384 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1385 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
1386 }
1387 return Register();
1388}
1389
1390Register fastEmit_ISD_ADD_MVT_v2i16_rr(MVT RetVT, Register Op0, Register Op1) {
1391 if (RetVT.SimpleTy != MVT::v2i16)
1392 return Register();
1393 if ((Subtarget->hasDSP())) {
1394 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDQ_PH, RC: &Mips::DSPRRegClass, Op0, Op1);
1395 }
1396 return Register();
1397}
1398
1399Register fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1400 if (RetVT.SimpleTy != MVT::v8i16)
1401 return Register();
1402 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1403 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
1404 }
1405 return Register();
1406}
1407
1408Register fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
1409 if (RetVT.SimpleTy != MVT::v4i32)
1410 return Register();
1411 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1412 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1413 }
1414 return Register();
1415}
1416
1417Register fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
1418 if (RetVT.SimpleTy != MVT::v2i64)
1419 return Register();
1420 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1421 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1422 }
1423 return Register();
1424}
1425
1426Register fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1427 switch (VT.SimpleTy) {
1428 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op1);
1429 case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op1);
1430 case MVT::v4i8: return fastEmit_ISD_ADD_MVT_v4i8_rr(RetVT, Op0, Op1);
1431 case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op1);
1432 case MVT::v2i16: return fastEmit_ISD_ADD_MVT_v2i16_rr(RetVT, Op0, Op1);
1433 case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op1);
1434 case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op1);
1435 case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op1);
1436 default: return Register();
1437 }
1438}
1439
1440// FastEmit functions for ISD::ADDC.
1441
1442Register fastEmit_ISD_ADDC_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1443 if (RetVT.SimpleTy != MVT::i32)
1444 return Register();
1445 if ((Subtarget->hasDSP())) {
1446 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDSC, RC: &Mips::GPR32RegClass, Op0, Op1);
1447 }
1448 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP())) {
1449 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDu, RC: &Mips::GPR32RegClass, Op0, Op1);
1450 }
1451 return Register();
1452}
1453
1454Register fastEmit_ISD_ADDC_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1455 if (RetVT.SimpleTy != MVT::i64)
1456 return Register();
1457 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->hasDSP()) && (!Subtarget->inMicroMipsMode())) {
1458 return fastEmitInst_rr(MachineInstOpcode: Mips::DADDu, RC: &Mips::GPR64RegClass, Op0, Op1);
1459 }
1460 return Register();
1461}
1462
1463Register fastEmit_ISD_ADDC_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1464 switch (VT.SimpleTy) {
1465 case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_rr(RetVT, Op0, Op1);
1466 case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_rr(RetVT, Op0, Op1);
1467 default: return Register();
1468 }
1469}
1470
1471// FastEmit functions for ISD::ADDE.
1472
1473Register fastEmit_ISD_ADDE_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1474 if (RetVT.SimpleTy != MVT::i32)
1475 return Register();
1476 if ((Subtarget->hasDSP())) {
1477 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDWC, RC: &Mips::GPR32RegClass, Op0, Op1);
1478 }
1479 return Register();
1480}
1481
1482Register fastEmit_ISD_ADDE_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1483 switch (VT.SimpleTy) {
1484 case MVT::i32: return fastEmit_ISD_ADDE_MVT_i32_rr(RetVT, Op0, Op1);
1485 default: return Register();
1486 }
1487}
1488
1489// FastEmit functions for ISD::AND.
1490
1491Register fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1492 if (RetVT.SimpleTy != MVT::i32)
1493 return Register();
1494 if ((Subtarget->inMips16Mode())) {
1495 return fastEmitInst_rr(MachineInstOpcode: Mips::AndRxRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
1496 }
1497 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1498 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
1499 }
1500 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1501 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
1502 }
1503 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1504 return fastEmitInst_rr(MachineInstOpcode: Mips::AND, RC: &Mips::GPR32RegClass, Op0, Op1);
1505 }
1506 return Register();
1507}
1508
1509Register fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1510 if (RetVT.SimpleTy != MVT::i64)
1511 return Register();
1512 if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
1513 return fastEmitInst_rr(MachineInstOpcode: Mips::AND64, RC: &Mips::GPR64RegClass, Op0, Op1);
1514 }
1515 return Register();
1516}
1517
1518Register fastEmit_ISD_AND_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1519 if (RetVT.SimpleTy != MVT::v16i8)
1520 return Register();
1521 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1522 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
1523 }
1524 return Register();
1525}
1526
1527Register fastEmit_ISD_AND_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1528 if (RetVT.SimpleTy != MVT::v8i16)
1529 return Register();
1530 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1531 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
1532 }
1533 return Register();
1534}
1535
1536Register fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
1537 if (RetVT.SimpleTy != MVT::v4i32)
1538 return Register();
1539 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1540 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
1541 }
1542 return Register();
1543}
1544
1545Register fastEmit_ISD_AND_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
1546 if (RetVT.SimpleTy != MVT::v2i64)
1547 return Register();
1548 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1549 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
1550 }
1551 return Register();
1552}
1553
1554Register fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1555 switch (VT.SimpleTy) {
1556 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op1);
1557 case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op1);
1558 case MVT::v16i8: return fastEmit_ISD_AND_MVT_v16i8_rr(RetVT, Op0, Op1);
1559 case MVT::v8i16: return fastEmit_ISD_AND_MVT_v8i16_rr(RetVT, Op0, Op1);
1560 case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op1);
1561 case MVT::v2i64: return fastEmit_ISD_AND_MVT_v2i64_rr(RetVT, Op0, Op1);
1562 default: return Register();
1563 }
1564}
1565
1566// FastEmit functions for ISD::FADD.
1567
1568Register fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1569 if (RetVT.SimpleTy != MVT::f32)
1570 return Register();
1571 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1572 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1573 }
1574 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1575 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1576 }
1577 return Register();
1578}
1579
1580Register fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1581 if (RetVT.SimpleTy != MVT::f64)
1582 return Register();
1583 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
1584 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1585 }
1586 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1587 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1588 }
1589 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1590 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1591 }
1592 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1593 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1594 }
1595 return Register();
1596}
1597
1598Register fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1599 if (RetVT.SimpleTy != MVT::v4f32)
1600 return Register();
1601 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1602 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1603 }
1604 return Register();
1605}
1606
1607Register fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1608 if (RetVT.SimpleTy != MVT::v2f64)
1609 return Register();
1610 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1611 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1612 }
1613 return Register();
1614}
1615
1616Register fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1617 switch (VT.SimpleTy) {
1618 case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op1);
1619 case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op1);
1620 case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op1);
1621 case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op1);
1622 default: return Register();
1623 }
1624}
1625
1626// FastEmit functions for ISD::FDIV.
1627
1628Register fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1629 if (RetVT.SimpleTy != MVT::f32)
1630 return Register();
1631 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1632 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1633 }
1634 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1635 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1636 }
1637 return Register();
1638}
1639
1640Register fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1641 if (RetVT.SimpleTy != MVT::f64)
1642 return Register();
1643 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
1644 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1645 }
1646 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1647 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1648 }
1649 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1650 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1651 }
1652 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1653 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1654 }
1655 return Register();
1656}
1657
1658Register fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1659 if (RetVT.SimpleTy != MVT::v4f32)
1660 return Register();
1661 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1662 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1663 }
1664 return Register();
1665}
1666
1667Register fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1668 if (RetVT.SimpleTy != MVT::v2f64)
1669 return Register();
1670 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1671 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1672 }
1673 return Register();
1674}
1675
1676Register fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1677 switch (VT.SimpleTy) {
1678 case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op1);
1679 case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op1);
1680 case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op1);
1681 case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op1);
1682 default: return Register();
1683 }
1684}
1685
1686// FastEmit functions for ISD::FMAXNUM.
1687
1688Register fastEmit_ISD_FMAXNUM_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1689 if (RetVT.SimpleTy != MVT::f32)
1690 return Register();
1691 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1692 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1693 }
1694 return Register();
1695}
1696
1697Register fastEmit_ISD_FMAXNUM_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1698 if (RetVT.SimpleTy != MVT::f64)
1699 return Register();
1700 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1701 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_D, RC: &Mips::FGR64RegClass, Op0, Op1);
1702 }
1703 return Register();
1704}
1705
1706Register fastEmit_ISD_FMAXNUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1707 switch (VT.SimpleTy) {
1708 case MVT::f32: return fastEmit_ISD_FMAXNUM_MVT_f32_rr(RetVT, Op0, Op1);
1709 case MVT::f64: return fastEmit_ISD_FMAXNUM_MVT_f64_rr(RetVT, Op0, Op1);
1710 default: return Register();
1711 }
1712}
1713
1714// FastEmit functions for ISD::FMAXNUM_IEEE.
1715
1716Register fastEmit_ISD_FMAXNUM_IEEE_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1717 if (RetVT.SimpleTy != MVT::f32)
1718 return Register();
1719 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1720 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1721 }
1722 return Register();
1723}
1724
1725Register fastEmit_ISD_FMAXNUM_IEEE_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1726 if (RetVT.SimpleTy != MVT::f64)
1727 return Register();
1728 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1729 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_D, RC: &Mips::FGR64RegClass, Op0, Op1);
1730 }
1731 return Register();
1732}
1733
1734Register fastEmit_ISD_FMAXNUM_IEEE_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1735 switch (VT.SimpleTy) {
1736 case MVT::f32: return fastEmit_ISD_FMAXNUM_IEEE_MVT_f32_rr(RetVT, Op0, Op1);
1737 case MVT::f64: return fastEmit_ISD_FMAXNUM_IEEE_MVT_f64_rr(RetVT, Op0, Op1);
1738 default: return Register();
1739 }
1740}
1741
1742// FastEmit functions for ISD::FMINNUM.
1743
1744Register fastEmit_ISD_FMINNUM_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1745 if (RetVT.SimpleTy != MVT::f32)
1746 return Register();
1747 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1748 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1749 }
1750 return Register();
1751}
1752
1753Register fastEmit_ISD_FMINNUM_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1754 if (RetVT.SimpleTy != MVT::f64)
1755 return Register();
1756 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1757 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_D, RC: &Mips::FGR64RegClass, Op0, Op1);
1758 }
1759 return Register();
1760}
1761
1762Register fastEmit_ISD_FMINNUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1763 switch (VT.SimpleTy) {
1764 case MVT::f32: return fastEmit_ISD_FMINNUM_MVT_f32_rr(RetVT, Op0, Op1);
1765 case MVT::f64: return fastEmit_ISD_FMINNUM_MVT_f64_rr(RetVT, Op0, Op1);
1766 default: return Register();
1767 }
1768}
1769
1770// FastEmit functions for ISD::FMINNUM_IEEE.
1771
1772Register fastEmit_ISD_FMINNUM_IEEE_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1773 if (RetVT.SimpleTy != MVT::f32)
1774 return Register();
1775 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1776 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1777 }
1778 return Register();
1779}
1780
1781Register fastEmit_ISD_FMINNUM_IEEE_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1782 if (RetVT.SimpleTy != MVT::f64)
1783 return Register();
1784 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1785 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_D, RC: &Mips::FGR64RegClass, Op0, Op1);
1786 }
1787 return Register();
1788}
1789
1790Register fastEmit_ISD_FMINNUM_IEEE_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1791 switch (VT.SimpleTy) {
1792 case MVT::f32: return fastEmit_ISD_FMINNUM_IEEE_MVT_f32_rr(RetVT, Op0, Op1);
1793 case MVT::f64: return fastEmit_ISD_FMINNUM_IEEE_MVT_f64_rr(RetVT, Op0, Op1);
1794 default: return Register();
1795 }
1796}
1797
1798// FastEmit functions for ISD::FMUL.
1799
1800Register fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1801 if (RetVT.SimpleTy != MVT::f32)
1802 return Register();
1803 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1804 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1805 }
1806 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1807 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1808 }
1809 return Register();
1810}
1811
1812Register fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1813 if (RetVT.SimpleTy != MVT::f64)
1814 return Register();
1815 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
1816 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1817 }
1818 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1819 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1820 }
1821 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1822 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1823 }
1824 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1825 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1826 }
1827 return Register();
1828}
1829
1830Register fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1831 if (RetVT.SimpleTy != MVT::v4f32)
1832 return Register();
1833 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1834 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1835 }
1836 return Register();
1837}
1838
1839Register fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1840 if (RetVT.SimpleTy != MVT::v2f64)
1841 return Register();
1842 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1843 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1844 }
1845 return Register();
1846}
1847
1848Register fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1849 switch (VT.SimpleTy) {
1850 case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op1);
1851 case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op1);
1852 case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op1);
1853 case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op1);
1854 default: return Register();
1855 }
1856}
1857
1858// FastEmit functions for ISD::FSUB.
1859
1860Register fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1861 if (RetVT.SimpleTy != MVT::f32)
1862 return Register();
1863 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1864 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1865 }
1866 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1867 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1868 }
1869 return Register();
1870}
1871
1872Register fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1873 if (RetVT.SimpleTy != MVT::f64)
1874 return Register();
1875 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat())) {
1876 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1877 }
1878 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1879 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1880 }
1881 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1882 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1883 }
1884 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1885 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1886 }
1887 return Register();
1888}
1889
1890Register fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1891 if (RetVT.SimpleTy != MVT::v4f32)
1892 return Register();
1893 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1894 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1895 }
1896 return Register();
1897}
1898
1899Register fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1900 if (RetVT.SimpleTy != MVT::v2f64)
1901 return Register();
1902 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1903 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1904 }
1905 return Register();
1906}
1907
1908Register fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1909 switch (VT.SimpleTy) {
1910 case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op1);
1911 case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op1);
1912 case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op1);
1913 case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op1);
1914 default: return Register();
1915 }
1916}
1917
1918// FastEmit functions for ISD::MUL.
1919
1920Register fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1921 if (RetVT.SimpleTy != MVT::i32)
1922 return Register();
1923 if ((Subtarget->inMips16Mode())) {
1924 return fastEmitInst_rr(MachineInstOpcode: Mips::MultRxRyRz16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
1925 }
1926 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1927 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
1928 }
1929 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1930 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
1931 }
1932 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1933 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_R6, RC: &Mips::GPR32RegClass, Op0, Op1);
1934 }
1935 if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
1936 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL, RC: &Mips::GPR32RegClass, Op0, Op1);
1937 }
1938 return Register();
1939}
1940
1941Register fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1942 if (RetVT.SimpleTy != MVT::i64)
1943 return Register();
1944 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1945 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUL_R6, RC: &Mips::GPR64RegClass, Op0, Op1);
1946 }
1947 if ((Subtarget->hasCnMips())) {
1948 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUL, RC: &Mips::GPR64RegClass, Op0, Op1);
1949 }
1950 return Register();
1951}
1952
1953Register fastEmit_ISD_MUL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1954 if (RetVT.SimpleTy != MVT::v16i8)
1955 return Register();
1956 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1957 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
1958 }
1959 return Register();
1960}
1961
1962Register fastEmit_ISD_MUL_MVT_v2i16_rr(MVT RetVT, Register Op0, Register Op1) {
1963 if (RetVT.SimpleTy != MVT::v2i16)
1964 return Register();
1965 if ((Subtarget->hasDSPR2())) {
1966 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_PH, RC: &Mips::DSPRRegClass, Op0, Op1);
1967 }
1968 return Register();
1969}
1970
1971Register fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1972 if (RetVT.SimpleTy != MVT::v8i16)
1973 return Register();
1974 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1975 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
1976 }
1977 return Register();
1978}
1979
1980Register fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
1981 if (RetVT.SimpleTy != MVT::v4i32)
1982 return Register();
1983 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1984 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1985 }
1986 return Register();
1987}
1988
1989Register fastEmit_ISD_MUL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
1990 if (RetVT.SimpleTy != MVT::v2i64)
1991 return Register();
1992 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1993 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1994 }
1995 return Register();
1996}
1997
1998Register fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1999 switch (VT.SimpleTy) {
2000 case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op1);
2001 case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op1);
2002 case MVT::v16i8: return fastEmit_ISD_MUL_MVT_v16i8_rr(RetVT, Op0, Op1);
2003 case MVT::v2i16: return fastEmit_ISD_MUL_MVT_v2i16_rr(RetVT, Op0, Op1);
2004 case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op1);
2005 case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op1);
2006 case MVT::v2i64: return fastEmit_ISD_MUL_MVT_v2i64_rr(RetVT, Op0, Op1);
2007 default: return Register();
2008 }
2009}
2010
2011// FastEmit functions for ISD::MULHS.
2012
2013Register fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2014 if (RetVT.SimpleTy != MVT::i32)
2015 return Register();
2016 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2017 return fastEmitInst_rr(MachineInstOpcode: Mips::MUH_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2018 }
2019 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2020 return fastEmitInst_rr(MachineInstOpcode: Mips::MUH, RC: &Mips::GPR32RegClass, Op0, Op1);
2021 }
2022 return Register();
2023}
2024
2025Register fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2026 if (RetVT.SimpleTy != MVT::i64)
2027 return Register();
2028 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2029 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUH, RC: &Mips::GPR64RegClass, Op0, Op1);
2030 }
2031 return Register();
2032}
2033
2034Register fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2035 switch (VT.SimpleTy) {
2036 case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op1);
2037 case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op1);
2038 default: return Register();
2039 }
2040}
2041
2042// FastEmit functions for ISD::MULHU.
2043
2044Register fastEmit_ISD_MULHU_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2045 if (RetVT.SimpleTy != MVT::i32)
2046 return Register();
2047 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2048 return fastEmitInst_rr(MachineInstOpcode: Mips::MUHU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2049 }
2050 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2051 return fastEmitInst_rr(MachineInstOpcode: Mips::MUHU, RC: &Mips::GPR32RegClass, Op0, Op1);
2052 }
2053 return Register();
2054}
2055
2056Register fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2057 if (RetVT.SimpleTy != MVT::i64)
2058 return Register();
2059 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2060 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUHU, RC: &Mips::GPR64RegClass, Op0, Op1);
2061 }
2062 return Register();
2063}
2064
2065Register fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2066 switch (VT.SimpleTy) {
2067 case MVT::i32: return fastEmit_ISD_MULHU_MVT_i32_rr(RetVT, Op0, Op1);
2068 case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op1);
2069 default: return Register();
2070 }
2071}
2072
2073// FastEmit functions for ISD::OR.
2074
2075Register fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2076 if (RetVT.SimpleTy != MVT::i32)
2077 return Register();
2078 if ((Subtarget->inMips16Mode())) {
2079 return fastEmitInst_rr(MachineInstOpcode: Mips::OrRxRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2080 }
2081 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2082 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2083 }
2084 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
2085 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2086 }
2087 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2088 return fastEmitInst_rr(MachineInstOpcode: Mips::OR, RC: &Mips::GPR32RegClass, Op0, Op1);
2089 }
2090 return Register();
2091}
2092
2093Register fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2094 if (RetVT.SimpleTy != MVT::i64)
2095 return Register();
2096 if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
2097 return fastEmitInst_rr(MachineInstOpcode: Mips::OR64, RC: &Mips::GPR64RegClass, Op0, Op1);
2098 }
2099 return Register();
2100}
2101
2102Register fastEmit_ISD_OR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2103 if (RetVT.SimpleTy != MVT::v16i8)
2104 return Register();
2105 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2106 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
2107 }
2108 return Register();
2109}
2110
2111Register fastEmit_ISD_OR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2112 if (RetVT.SimpleTy != MVT::v8i16)
2113 return Register();
2114 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2115 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
2116 }
2117 return Register();
2118}
2119
2120Register fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2121 if (RetVT.SimpleTy != MVT::v4i32)
2122 return Register();
2123 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2124 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
2125 }
2126 return Register();
2127}
2128
2129Register fastEmit_ISD_OR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2130 if (RetVT.SimpleTy != MVT::v2i64)
2131 return Register();
2132 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2133 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
2134 }
2135 return Register();
2136}
2137
2138Register fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2139 switch (VT.SimpleTy) {
2140 case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op1);
2141 case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op1);
2142 case MVT::v16i8: return fastEmit_ISD_OR_MVT_v16i8_rr(RetVT, Op0, Op1);
2143 case MVT::v8i16: return fastEmit_ISD_OR_MVT_v8i16_rr(RetVT, Op0, Op1);
2144 case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op1);
2145 case MVT::v2i64: return fastEmit_ISD_OR_MVT_v2i64_rr(RetVT, Op0, Op1);
2146 default: return Register();
2147 }
2148}
2149
2150// FastEmit functions for ISD::ROTR.
2151
2152Register fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2153 if (RetVT.SimpleTy != MVT::i32)
2154 return Register();
2155 if ((Subtarget->inMicroMipsMode())) {
2156 return fastEmitInst_rr(MachineInstOpcode: Mips::ROTRV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2157 }
2158 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2159 return fastEmitInst_rr(MachineInstOpcode: Mips::ROTRV, RC: &Mips::GPR32RegClass, Op0, Op1);
2160 }
2161 return Register();
2162}
2163
2164Register fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2165 switch (VT.SimpleTy) {
2166 case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op1);
2167 default: return Register();
2168 }
2169}
2170
2171// FastEmit functions for ISD::SDIV.
2172
2173Register fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2174 if (RetVT.SimpleTy != MVT::i32)
2175 return Register();
2176 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2177 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2178 }
2179 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2180 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV, RC: &Mips::GPR32RegClass, Op0, Op1);
2181 }
2182 return Register();
2183}
2184
2185Register fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2186 if (RetVT.SimpleTy != MVT::i64)
2187 return Register();
2188 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2189 return fastEmitInst_rr(MachineInstOpcode: Mips::DDIV, RC: &Mips::GPR64RegClass, Op0, Op1);
2190 }
2191 return Register();
2192}
2193
2194Register fastEmit_ISD_SDIV_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2195 if (RetVT.SimpleTy != MVT::v16i8)
2196 return Register();
2197 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2198 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2199 }
2200 return Register();
2201}
2202
2203Register fastEmit_ISD_SDIV_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2204 if (RetVT.SimpleTy != MVT::v8i16)
2205 return Register();
2206 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2207 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2208 }
2209 return Register();
2210}
2211
2212Register fastEmit_ISD_SDIV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2213 if (RetVT.SimpleTy != MVT::v4i32)
2214 return Register();
2215 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2216 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2217 }
2218 return Register();
2219}
2220
2221Register fastEmit_ISD_SDIV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2222 if (RetVT.SimpleTy != MVT::v2i64)
2223 return Register();
2224 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2225 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2226 }
2227 return Register();
2228}
2229
2230Register fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2231 switch (VT.SimpleTy) {
2232 case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op1);
2233 case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op1);
2234 case MVT::v16i8: return fastEmit_ISD_SDIV_MVT_v16i8_rr(RetVT, Op0, Op1);
2235 case MVT::v8i16: return fastEmit_ISD_SDIV_MVT_v8i16_rr(RetVT, Op0, Op1);
2236 case MVT::v4i32: return fastEmit_ISD_SDIV_MVT_v4i32_rr(RetVT, Op0, Op1);
2237 case MVT::v2i64: return fastEmit_ISD_SDIV_MVT_v2i64_rr(RetVT, Op0, Op1);
2238 default: return Register();
2239 }
2240}
2241
2242// FastEmit functions for ISD::SHL.
2243
2244Register fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2245 if (RetVT.SimpleTy != MVT::i32)
2246 return Register();
2247 if ((Subtarget->inMicroMipsMode())) {
2248 return fastEmitInst_rr(MachineInstOpcode: Mips::SLLV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2249 }
2250 if ((Subtarget->inMips16Mode())) {
2251 return fastEmitInst_rr(MachineInstOpcode: Mips::SllvRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2252 }
2253 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2254 return fastEmitInst_rr(MachineInstOpcode: Mips::SLLV, RC: &Mips::GPR32RegClass, Op0, Op1);
2255 }
2256 return Register();
2257}
2258
2259Register fastEmit_ISD_SHL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2260 if (RetVT.SimpleTy != MVT::v16i8)
2261 return Register();
2262 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2263 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2264 }
2265 return Register();
2266}
2267
2268Register fastEmit_ISD_SHL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2269 if (RetVT.SimpleTy != MVT::v8i16)
2270 return Register();
2271 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2272 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2273 }
2274 return Register();
2275}
2276
2277Register fastEmit_ISD_SHL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2278 if (RetVT.SimpleTy != MVT::v4i32)
2279 return Register();
2280 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2281 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2282 }
2283 return Register();
2284}
2285
2286Register fastEmit_ISD_SHL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2287 if (RetVT.SimpleTy != MVT::v2i64)
2288 return Register();
2289 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2290 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2291 }
2292 return Register();
2293}
2294
2295Register fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2296 switch (VT.SimpleTy) {
2297 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op1);
2298 case MVT::v16i8: return fastEmit_ISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op1);
2299 case MVT::v8i16: return fastEmit_ISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op1);
2300 case MVT::v4i32: return fastEmit_ISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op1);
2301 case MVT::v2i64: return fastEmit_ISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op1);
2302 default: return Register();
2303 }
2304}
2305
2306// FastEmit functions for ISD::SMAX.
2307
2308Register fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2309 if (RetVT.SimpleTy != MVT::v16i8)
2310 return Register();
2311 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2312 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2313 }
2314 return Register();
2315}
2316
2317Register fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2318 if (RetVT.SimpleTy != MVT::v8i16)
2319 return Register();
2320 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2321 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2322 }
2323 return Register();
2324}
2325
2326Register fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2327 if (RetVT.SimpleTy != MVT::v4i32)
2328 return Register();
2329 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2330 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2331 }
2332 return Register();
2333}
2334
2335Register fastEmit_ISD_SMAX_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2336 if (RetVT.SimpleTy != MVT::v2i64)
2337 return Register();
2338 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2339 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2340 }
2341 return Register();
2342}
2343
2344Register fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2345 switch (VT.SimpleTy) {
2346 case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
2347 case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
2348 case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
2349 case MVT::v2i64: return fastEmit_ISD_SMAX_MVT_v2i64_rr(RetVT, Op0, Op1);
2350 default: return Register();
2351 }
2352}
2353
2354// FastEmit functions for ISD::SMIN.
2355
2356Register fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2357 if (RetVT.SimpleTy != MVT::v16i8)
2358 return Register();
2359 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2360 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2361 }
2362 return Register();
2363}
2364
2365Register fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2366 if (RetVT.SimpleTy != MVT::v8i16)
2367 return Register();
2368 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2369 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2370 }
2371 return Register();
2372}
2373
2374Register fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2375 if (RetVT.SimpleTy != MVT::v4i32)
2376 return Register();
2377 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2378 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2379 }
2380 return Register();
2381}
2382
2383Register fastEmit_ISD_SMIN_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2384 if (RetVT.SimpleTy != MVT::v2i64)
2385 return Register();
2386 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2387 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2388 }
2389 return Register();
2390}
2391
2392Register fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2393 switch (VT.SimpleTy) {
2394 case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
2395 case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
2396 case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
2397 case MVT::v2i64: return fastEmit_ISD_SMIN_MVT_v2i64_rr(RetVT, Op0, Op1);
2398 default: return Register();
2399 }
2400}
2401
2402// FastEmit functions for ISD::SRA.
2403
2404Register fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2405 if (RetVT.SimpleTy != MVT::i32)
2406 return Register();
2407 if ((Subtarget->inMicroMipsMode())) {
2408 return fastEmitInst_rr(MachineInstOpcode: Mips::SRAV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2409 }
2410 if ((Subtarget->inMips16Mode())) {
2411 return fastEmitInst_rr(MachineInstOpcode: Mips::SravRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2412 }
2413 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2414 return fastEmitInst_rr(MachineInstOpcode: Mips::SRAV, RC: &Mips::GPR32RegClass, Op0, Op1);
2415 }
2416 return Register();
2417}
2418
2419Register fastEmit_ISD_SRA_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2420 if (RetVT.SimpleTy != MVT::v16i8)
2421 return Register();
2422 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2423 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2424 }
2425 return Register();
2426}
2427
2428Register fastEmit_ISD_SRA_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2429 if (RetVT.SimpleTy != MVT::v8i16)
2430 return Register();
2431 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2432 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2433 }
2434 return Register();
2435}
2436
2437Register fastEmit_ISD_SRA_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2438 if (RetVT.SimpleTy != MVT::v4i32)
2439 return Register();
2440 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2441 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2442 }
2443 return Register();
2444}
2445
2446Register fastEmit_ISD_SRA_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2447 if (RetVT.SimpleTy != MVT::v2i64)
2448 return Register();
2449 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2450 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2451 }
2452 return Register();
2453}
2454
2455Register fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2456 switch (VT.SimpleTy) {
2457 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op1);
2458 case MVT::v16i8: return fastEmit_ISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op1);
2459 case MVT::v8i16: return fastEmit_ISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op1);
2460 case MVT::v4i32: return fastEmit_ISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op1);
2461 case MVT::v2i64: return fastEmit_ISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op1);
2462 default: return Register();
2463 }
2464}
2465
2466// FastEmit functions for ISD::SREM.
2467
2468Register fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2469 if (RetVT.SimpleTy != MVT::i32)
2470 return Register();
2471 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2472 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2473 }
2474 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2475 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD, RC: &Mips::GPR32RegClass, Op0, Op1);
2476 }
2477 return Register();
2478}
2479
2480Register fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2481 if (RetVT.SimpleTy != MVT::i64)
2482 return Register();
2483 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2484 return fastEmitInst_rr(MachineInstOpcode: Mips::DMOD, RC: &Mips::GPR64RegClass, Op0, Op1);
2485 }
2486 return Register();
2487}
2488
2489Register fastEmit_ISD_SREM_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2490 if (RetVT.SimpleTy != MVT::v16i8)
2491 return Register();
2492 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2493 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2494 }
2495 return Register();
2496}
2497
2498Register fastEmit_ISD_SREM_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2499 if (RetVT.SimpleTy != MVT::v8i16)
2500 return Register();
2501 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2502 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2503 }
2504 return Register();
2505}
2506
2507Register fastEmit_ISD_SREM_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2508 if (RetVT.SimpleTy != MVT::v4i32)
2509 return Register();
2510 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2511 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2512 }
2513 return Register();
2514}
2515
2516Register fastEmit_ISD_SREM_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2517 if (RetVT.SimpleTy != MVT::v2i64)
2518 return Register();
2519 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2520 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2521 }
2522 return Register();
2523}
2524
2525Register fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2526 switch (VT.SimpleTy) {
2527 case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op1);
2528 case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op1);
2529 case MVT::v16i8: return fastEmit_ISD_SREM_MVT_v16i8_rr(RetVT, Op0, Op1);
2530 case MVT::v8i16: return fastEmit_ISD_SREM_MVT_v8i16_rr(RetVT, Op0, Op1);
2531 case MVT::v4i32: return fastEmit_ISD_SREM_MVT_v4i32_rr(RetVT, Op0, Op1);
2532 case MVT::v2i64: return fastEmit_ISD_SREM_MVT_v2i64_rr(RetVT, Op0, Op1);
2533 default: return Register();
2534 }
2535}
2536
2537// FastEmit functions for ISD::SRL.
2538
2539Register fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2540 if (RetVT.SimpleTy != MVT::i32)
2541 return Register();
2542 if ((Subtarget->inMicroMipsMode())) {
2543 return fastEmitInst_rr(MachineInstOpcode: Mips::SRLV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2544 }
2545 if ((Subtarget->inMips16Mode())) {
2546 return fastEmitInst_rr(MachineInstOpcode: Mips::SrlvRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2547 }
2548 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2549 return fastEmitInst_rr(MachineInstOpcode: Mips::SRLV, RC: &Mips::GPR32RegClass, Op0, Op1);
2550 }
2551 return Register();
2552}
2553
2554Register fastEmit_ISD_SRL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2555 if (RetVT.SimpleTy != MVT::v16i8)
2556 return Register();
2557 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2558 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2559 }
2560 return Register();
2561}
2562
2563Register fastEmit_ISD_SRL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2564 if (RetVT.SimpleTy != MVT::v8i16)
2565 return Register();
2566 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2567 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2568 }
2569 return Register();
2570}
2571
2572Register fastEmit_ISD_SRL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2573 if (RetVT.SimpleTy != MVT::v4i32)
2574 return Register();
2575 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2576 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2577 }
2578 return Register();
2579}
2580
2581Register fastEmit_ISD_SRL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2582 if (RetVT.SimpleTy != MVT::v2i64)
2583 return Register();
2584 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2585 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2586 }
2587 return Register();
2588}
2589
2590Register fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2591 switch (VT.SimpleTy) {
2592 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op1);
2593 case MVT::v16i8: return fastEmit_ISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op1);
2594 case MVT::v8i16: return fastEmit_ISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op1);
2595 case MVT::v4i32: return fastEmit_ISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op1);
2596 case MVT::v2i64: return fastEmit_ISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op1);
2597 default: return Register();
2598 }
2599}
2600
2601// FastEmit functions for ISD::STRICT_FADD.
2602
2603Register fastEmit_ISD_STRICT_FADD_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
2604 if (RetVT.SimpleTy != MVT::f32)
2605 return Register();
2606 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2607 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_S, RC: &Mips::FGR32RegClass, Op0, Op1);
2608 }
2609 return Register();
2610}
2611
2612Register fastEmit_ISD_STRICT_FADD_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
2613 if (RetVT.SimpleTy != MVT::f64)
2614 return Register();
2615 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2616 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
2617 }
2618 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
2619 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
2620 }
2621 return Register();
2622}
2623
2624Register fastEmit_ISD_STRICT_FADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2625 switch (VT.SimpleTy) {
2626 case MVT::f32: return fastEmit_ISD_STRICT_FADD_MVT_f32_rr(RetVT, Op0, Op1);
2627 case MVT::f64: return fastEmit_ISD_STRICT_FADD_MVT_f64_rr(RetVT, Op0, Op1);
2628 default: return Register();
2629 }
2630}
2631
2632// FastEmit functions for ISD::STRICT_FDIV.
2633
2634Register fastEmit_ISD_STRICT_FDIV_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
2635 if (RetVT.SimpleTy != MVT::f32)
2636 return Register();
2637 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2638 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_S, RC: &Mips::FGR32RegClass, Op0, Op1);
2639 }
2640 return Register();
2641}
2642
2643Register fastEmit_ISD_STRICT_FDIV_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
2644 if (RetVT.SimpleTy != MVT::f64)
2645 return Register();
2646 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2647 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
2648 }
2649 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
2650 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
2651 }
2652 return Register();
2653}
2654
2655Register fastEmit_ISD_STRICT_FDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2656 switch (VT.SimpleTy) {
2657 case MVT::f32: return fastEmit_ISD_STRICT_FDIV_MVT_f32_rr(RetVT, Op0, Op1);
2658 case MVT::f64: return fastEmit_ISD_STRICT_FDIV_MVT_f64_rr(RetVT, Op0, Op1);
2659 default: return Register();
2660 }
2661}
2662
2663// FastEmit functions for ISD::STRICT_FMUL.
2664
2665Register fastEmit_ISD_STRICT_FMUL_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
2666 if (RetVT.SimpleTy != MVT::f32)
2667 return Register();
2668 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2669 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_S, RC: &Mips::FGR32RegClass, Op0, Op1);
2670 }
2671 return Register();
2672}
2673
2674Register fastEmit_ISD_STRICT_FMUL_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
2675 if (RetVT.SimpleTy != MVT::f64)
2676 return Register();
2677 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2678 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
2679 }
2680 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
2681 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
2682 }
2683 return Register();
2684}
2685
2686Register fastEmit_ISD_STRICT_FMUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2687 switch (VT.SimpleTy) {
2688 case MVT::f32: return fastEmit_ISD_STRICT_FMUL_MVT_f32_rr(RetVT, Op0, Op1);
2689 case MVT::f64: return fastEmit_ISD_STRICT_FMUL_MVT_f64_rr(RetVT, Op0, Op1);
2690 default: return Register();
2691 }
2692}
2693
2694// FastEmit functions for ISD::STRICT_FSUB.
2695
2696Register fastEmit_ISD_STRICT_FSUB_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
2697 if (RetVT.SimpleTy != MVT::f32)
2698 return Register();
2699 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2700 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_S, RC: &Mips::FGR32RegClass, Op0, Op1);
2701 }
2702 return Register();
2703}
2704
2705Register fastEmit_ISD_STRICT_FSUB_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
2706 if (RetVT.SimpleTy != MVT::f64)
2707 return Register();
2708 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2709 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
2710 }
2711 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
2712 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
2713 }
2714 return Register();
2715}
2716
2717Register fastEmit_ISD_STRICT_FSUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2718 switch (VT.SimpleTy) {
2719 case MVT::f32: return fastEmit_ISD_STRICT_FSUB_MVT_f32_rr(RetVT, Op0, Op1);
2720 case MVT::f64: return fastEmit_ISD_STRICT_FSUB_MVT_f64_rr(RetVT, Op0, Op1);
2721 default: return Register();
2722 }
2723}
2724
2725// FastEmit functions for ISD::SUB.
2726
2727Register fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2728 if (RetVT.SimpleTy != MVT::i32)
2729 return Register();
2730 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2731 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBU16_MMR6, RC: &Mips::GPRMM16RegClass, Op0, Op1);
2732 }
2733 if ((Subtarget->inMips16Mode())) {
2734 return fastEmitInst_rr(MachineInstOpcode: Mips::SubuRxRyRz16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2735 }
2736 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
2737 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2738 }
2739 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2740 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu, RC: &Mips::GPR32RegClass, Op0, Op1);
2741 }
2742 return Register();
2743}
2744
2745Register fastEmit_ISD_SUB_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2746 if (RetVT.SimpleTy != MVT::i64)
2747 return Register();
2748 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2749 return fastEmitInst_rr(MachineInstOpcode: Mips::DSUBu, RC: &Mips::GPR64RegClass, Op0, Op1);
2750 }
2751 return Register();
2752}
2753
2754Register fastEmit_ISD_SUB_MVT_v4i8_rr(MVT RetVT, Register Op0, Register Op1) {
2755 if (RetVT.SimpleTy != MVT::v4i8)
2756 return Register();
2757 if ((Subtarget->hasDSP())) {
2758 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBU_QB, RC: &Mips::DSPRRegClass, Op0, Op1);
2759 }
2760 return Register();
2761}
2762
2763Register fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2764 if (RetVT.SimpleTy != MVT::v16i8)
2765 return Register();
2766 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2767 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2768 }
2769 return Register();
2770}
2771
2772Register fastEmit_ISD_SUB_MVT_v2i16_rr(MVT RetVT, Register Op0, Register Op1) {
2773 if (RetVT.SimpleTy != MVT::v2i16)
2774 return Register();
2775 if ((Subtarget->hasDSP())) {
2776 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBQ_PH, RC: &Mips::DSPRRegClass, Op0, Op1);
2777 }
2778 return Register();
2779}
2780
2781Register fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2782 if (RetVT.SimpleTy != MVT::v8i16)
2783 return Register();
2784 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2785 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2786 }
2787 return Register();
2788}
2789
2790Register fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2791 if (RetVT.SimpleTy != MVT::v4i32)
2792 return Register();
2793 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2794 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2795 }
2796 return Register();
2797}
2798
2799Register fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2800 if (RetVT.SimpleTy != MVT::v2i64)
2801 return Register();
2802 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2803 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2804 }
2805 return Register();
2806}
2807
2808Register fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2809 switch (VT.SimpleTy) {
2810 case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op1);
2811 case MVT::i64: return fastEmit_ISD_SUB_MVT_i64_rr(RetVT, Op0, Op1);
2812 case MVT::v4i8: return fastEmit_ISD_SUB_MVT_v4i8_rr(RetVT, Op0, Op1);
2813 case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op1);
2814 case MVT::v2i16: return fastEmit_ISD_SUB_MVT_v2i16_rr(RetVT, Op0, Op1);
2815 case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op1);
2816 case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op1);
2817 case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op1);
2818 default: return Register();
2819 }
2820}
2821
2822// FastEmit functions for ISD::SUBC.
2823
2824Register fastEmit_ISD_SUBC_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2825 if (RetVT.SimpleTy != MVT::i32)
2826 return Register();
2827 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2828 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2829 }
2830 if ((Subtarget->inMicroMipsMode())) {
2831 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2832 }
2833 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2834 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu, RC: &Mips::GPR32RegClass, Op0, Op1);
2835 }
2836 return Register();
2837}
2838
2839Register fastEmit_ISD_SUBC_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2840 if (RetVT.SimpleTy != MVT::i64)
2841 return Register();
2842 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())) {
2843 return fastEmitInst_rr(MachineInstOpcode: Mips::DSUBu, RC: &Mips::GPR64RegClass, Op0, Op1);
2844 }
2845 return Register();
2846}
2847
2848Register fastEmit_ISD_SUBC_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2849 switch (VT.SimpleTy) {
2850 case MVT::i32: return fastEmit_ISD_SUBC_MVT_i32_rr(RetVT, Op0, Op1);
2851 case MVT::i64: return fastEmit_ISD_SUBC_MVT_i64_rr(RetVT, Op0, Op1);
2852 default: return Register();
2853 }
2854}
2855
2856// FastEmit functions for ISD::UDIV.
2857
2858Register fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2859 if (RetVT.SimpleTy != MVT::i32)
2860 return Register();
2861 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2862 return fastEmitInst_rr(MachineInstOpcode: Mips::DIVU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2863 }
2864 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2865 return fastEmitInst_rr(MachineInstOpcode: Mips::DIVU, RC: &Mips::GPR32RegClass, Op0, Op1);
2866 }
2867 return Register();
2868}
2869
2870Register fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2871 if (RetVT.SimpleTy != MVT::i64)
2872 return Register();
2873 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2874 return fastEmitInst_rr(MachineInstOpcode: Mips::DDIVU, RC: &Mips::GPR64RegClass, Op0, Op1);
2875 }
2876 return Register();
2877}
2878
2879Register fastEmit_ISD_UDIV_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2880 if (RetVT.SimpleTy != MVT::v16i8)
2881 return Register();
2882 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2883 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2884 }
2885 return Register();
2886}
2887
2888Register fastEmit_ISD_UDIV_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2889 if (RetVT.SimpleTy != MVT::v8i16)
2890 return Register();
2891 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2892 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2893 }
2894 return Register();
2895}
2896
2897Register fastEmit_ISD_UDIV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2898 if (RetVT.SimpleTy != MVT::v4i32)
2899 return Register();
2900 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2901 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2902 }
2903 return Register();
2904}
2905
2906Register fastEmit_ISD_UDIV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2907 if (RetVT.SimpleTy != MVT::v2i64)
2908 return Register();
2909 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2910 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2911 }
2912 return Register();
2913}
2914
2915Register fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2916 switch (VT.SimpleTy) {
2917 case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op1);
2918 case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op1);
2919 case MVT::v16i8: return fastEmit_ISD_UDIV_MVT_v16i8_rr(RetVT, Op0, Op1);
2920 case MVT::v8i16: return fastEmit_ISD_UDIV_MVT_v8i16_rr(RetVT, Op0, Op1);
2921 case MVT::v4i32: return fastEmit_ISD_UDIV_MVT_v4i32_rr(RetVT, Op0, Op1);
2922 case MVT::v2i64: return fastEmit_ISD_UDIV_MVT_v2i64_rr(RetVT, Op0, Op1);
2923 default: return Register();
2924 }
2925}
2926
2927// FastEmit functions for ISD::UMAX.
2928
2929Register fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2930 if (RetVT.SimpleTy != MVT::v16i8)
2931 return Register();
2932 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2933 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2934 }
2935 return Register();
2936}
2937
2938Register fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2939 if (RetVT.SimpleTy != MVT::v8i16)
2940 return Register();
2941 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2942 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2943 }
2944 return Register();
2945}
2946
2947Register fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2948 if (RetVT.SimpleTy != MVT::v4i32)
2949 return Register();
2950 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2951 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2952 }
2953 return Register();
2954}
2955
2956Register fastEmit_ISD_UMAX_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2957 if (RetVT.SimpleTy != MVT::v2i64)
2958 return Register();
2959 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2960 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2961 }
2962 return Register();
2963}
2964
2965Register fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2966 switch (VT.SimpleTy) {
2967 case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
2968 case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
2969 case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
2970 case MVT::v2i64: return fastEmit_ISD_UMAX_MVT_v2i64_rr(RetVT, Op0, Op1);
2971 default: return Register();
2972 }
2973}
2974
2975// FastEmit functions for ISD::UMIN.
2976
2977Register fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2978 if (RetVT.SimpleTy != MVT::v16i8)
2979 return Register();
2980 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2981 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2982 }
2983 return Register();
2984}
2985
2986Register fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2987 if (RetVT.SimpleTy != MVT::v8i16)
2988 return Register();
2989 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2990 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2991 }
2992 return Register();
2993}
2994
2995Register fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2996 if (RetVT.SimpleTy != MVT::v4i32)
2997 return Register();
2998 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2999 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3000 }
3001 return Register();
3002}
3003
3004Register fastEmit_ISD_UMIN_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3005 if (RetVT.SimpleTy != MVT::v2i64)
3006 return Register();
3007 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3008 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3009 }
3010 return Register();
3011}
3012
3013Register fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3014 switch (VT.SimpleTy) {
3015 case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
3016 case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
3017 case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
3018 case MVT::v2i64: return fastEmit_ISD_UMIN_MVT_v2i64_rr(RetVT, Op0, Op1);
3019 default: return Register();
3020 }
3021}
3022
3023// FastEmit functions for ISD::UREM.
3024
3025Register fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3026 if (RetVT.SimpleTy != MVT::i32)
3027 return Register();
3028 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
3029 return fastEmitInst_rr(MachineInstOpcode: Mips::MODU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
3030 }
3031 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3032 return fastEmitInst_rr(MachineInstOpcode: Mips::MODU, RC: &Mips::GPR32RegClass, Op0, Op1);
3033 }
3034 return Register();
3035}
3036
3037Register fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3038 if (RetVT.SimpleTy != MVT::i64)
3039 return Register();
3040 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3041 return fastEmitInst_rr(MachineInstOpcode: Mips::DMODU, RC: &Mips::GPR64RegClass, Op0, Op1);
3042 }
3043 return Register();
3044}
3045
3046Register fastEmit_ISD_UREM_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3047 if (RetVT.SimpleTy != MVT::v16i8)
3048 return Register();
3049 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3050 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3051 }
3052 return Register();
3053}
3054
3055Register fastEmit_ISD_UREM_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3056 if (RetVT.SimpleTy != MVT::v8i16)
3057 return Register();
3058 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3059 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3060 }
3061 return Register();
3062}
3063
3064Register fastEmit_ISD_UREM_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3065 if (RetVT.SimpleTy != MVT::v4i32)
3066 return Register();
3067 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3068 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3069 }
3070 return Register();
3071}
3072
3073Register fastEmit_ISD_UREM_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3074 if (RetVT.SimpleTy != MVT::v2i64)
3075 return Register();
3076 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3077 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3078 }
3079 return Register();
3080}
3081
3082Register fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3083 switch (VT.SimpleTy) {
3084 case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op1);
3085 case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op1);
3086 case MVT::v16i8: return fastEmit_ISD_UREM_MVT_v16i8_rr(RetVT, Op0, Op1);
3087 case MVT::v8i16: return fastEmit_ISD_UREM_MVT_v8i16_rr(RetVT, Op0, Op1);
3088 case MVT::v4i32: return fastEmit_ISD_UREM_MVT_v4i32_rr(RetVT, Op0, Op1);
3089 case MVT::v2i64: return fastEmit_ISD_UREM_MVT_v2i64_rr(RetVT, Op0, Op1);
3090 default: return Register();
3091 }
3092}
3093
3094// FastEmit functions for ISD::XOR.
3095
3096Register fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3097 if (RetVT.SimpleTy != MVT::i32)
3098 return Register();
3099 if ((Subtarget->inMips16Mode())) {
3100 return fastEmitInst_rr(MachineInstOpcode: Mips::XorRxRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
3101 }
3102 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
3103 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
3104 }
3105 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
3106 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
3107 }
3108 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3109 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR, RC: &Mips::GPR32RegClass, Op0, Op1);
3110 }
3111 return Register();
3112}
3113
3114Register fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3115 if (RetVT.SimpleTy != MVT::i64)
3116 return Register();
3117 if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
3118 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR64, RC: &Mips::GPR64RegClass, Op0, Op1);
3119 }
3120 return Register();
3121}
3122
3123Register fastEmit_ISD_XOR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3124 if (RetVT.SimpleTy != MVT::v16i8)
3125 return Register();
3126 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3127 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
3128 }
3129 return Register();
3130}
3131
3132Register fastEmit_ISD_XOR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3133 if (RetVT.SimpleTy != MVT::v8i16)
3134 return Register();
3135 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3136 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
3137 }
3138 return Register();
3139}
3140
3141Register fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3142 if (RetVT.SimpleTy != MVT::v4i32)
3143 return Register();
3144 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3145 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
3146 }
3147 return Register();
3148}
3149
3150Register fastEmit_ISD_XOR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3151 if (RetVT.SimpleTy != MVT::v2i64)
3152 return Register();
3153 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3154 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
3155 }
3156 return Register();
3157}
3158
3159Register fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3160 switch (VT.SimpleTy) {
3161 case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op1);
3162 case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op1);
3163 case MVT::v16i8: return fastEmit_ISD_XOR_MVT_v16i8_rr(RetVT, Op0, Op1);
3164 case MVT::v8i16: return fastEmit_ISD_XOR_MVT_v8i16_rr(RetVT, Op0, Op1);
3165 case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op1);
3166 case MVT::v2i64: return fastEmit_ISD_XOR_MVT_v2i64_rr(RetVT, Op0, Op1);
3167 default: return Register();
3168 }
3169}
3170
3171// FastEmit functions for MipsISD::BuildPairF64.
3172
3173Register fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3174 if (RetVT.SimpleTy != MVT::f64)
3175 return Register();
3176 if ((Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMips16Mode())) {
3177 return fastEmitInst_rr(MachineInstOpcode: Mips::BuildPairF64_64, RC: &Mips::FGR64RegClass, Op0, Op1);
3178 }
3179 if ((!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode())) {
3180 return fastEmitInst_rr(MachineInstOpcode: Mips::BuildPairF64, RC: &Mips::AFGR64RegClass, Op0, Op1);
3181 }
3182 return Register();
3183}
3184
3185Register fastEmit_MipsISD_BuildPairF64_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3186 switch (VT.SimpleTy) {
3187 case MVT::i32: return fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(RetVT, Op0, Op1);
3188 default: return Register();
3189 }
3190}
3191
3192// FastEmit functions for MipsISD::DivRem.
3193
3194Register fastEmit_MipsISD_DivRem_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3195 if (RetVT.SimpleTy != MVT::Untyped)
3196 return Register();
3197 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3198 return fastEmitInst_rr(MachineInstOpcode: Mips::SDIV_MM_Pseudo, RC: &Mips::ACC64RegClass, Op0, Op1);
3199 }
3200 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3201 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoSDIV, RC: &Mips::ACC64RegClass, Op0, Op1);
3202 }
3203 return Register();
3204}
3205
3206Register fastEmit_MipsISD_DivRem_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3207 if (RetVT.SimpleTy != MVT::Untyped)
3208 return Register();
3209 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (!Subtarget->isR5900())) {
3210 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDSDIV, RC: &Mips::ACC128RegClass, Op0, Op1);
3211 }
3212 return Register();
3213}
3214
3215Register fastEmit_MipsISD_DivRem_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3216 switch (VT.SimpleTy) {
3217 case MVT::i32: return fastEmit_MipsISD_DivRem_MVT_i32_rr(RetVT, Op0, Op1);
3218 case MVT::i64: return fastEmit_MipsISD_DivRem_MVT_i64_rr(RetVT, Op0, Op1);
3219 default: return Register();
3220 }
3221}
3222
3223// FastEmit functions for MipsISD::DivRem16.
3224
3225Register fastEmit_MipsISD_DivRem16_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3226 if (RetVT.SimpleTy != MVT::isVoid)
3227 return Register();
3228 if ((Subtarget->inMips16Mode())) {
3229 return fastEmitInst_rr(MachineInstOpcode: Mips::DivRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
3230 }
3231 return Register();
3232}
3233
3234Register fastEmit_MipsISD_DivRem16_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3235 switch (VT.SimpleTy) {
3236 case MVT::i32: return fastEmit_MipsISD_DivRem16_MVT_i32_rr(RetVT, Op0, Op1);
3237 default: return Register();
3238 }
3239}
3240
3241// FastEmit functions for MipsISD::DivRemU.
3242
3243Register fastEmit_MipsISD_DivRemU_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3244 if (RetVT.SimpleTy != MVT::Untyped)
3245 return Register();
3246 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3247 return fastEmitInst_rr(MachineInstOpcode: Mips::UDIV_MM_Pseudo, RC: &Mips::ACC64RegClass, Op0, Op1);
3248 }
3249 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3250 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoUDIV, RC: &Mips::ACC64RegClass, Op0, Op1);
3251 }
3252 return Register();
3253}
3254
3255Register fastEmit_MipsISD_DivRemU_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3256 if (RetVT.SimpleTy != MVT::Untyped)
3257 return Register();
3258 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (!Subtarget->isR5900())) {
3259 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDUDIV, RC: &Mips::ACC128RegClass, Op0, Op1);
3260 }
3261 return Register();
3262}
3263
3264Register fastEmit_MipsISD_DivRemU_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3265 switch (VT.SimpleTy) {
3266 case MVT::i32: return fastEmit_MipsISD_DivRemU_MVT_i32_rr(RetVT, Op0, Op1);
3267 case MVT::i64: return fastEmit_MipsISD_DivRemU_MVT_i64_rr(RetVT, Op0, Op1);
3268 default: return Register();
3269 }
3270}
3271
3272// FastEmit functions for MipsISD::DivRemU16.
3273
3274Register fastEmit_MipsISD_DivRemU16_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3275 if (RetVT.SimpleTy != MVT::isVoid)
3276 return Register();
3277 if ((Subtarget->inMips16Mode())) {
3278 return fastEmitInst_rr(MachineInstOpcode: Mips::DivuRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
3279 }
3280 return Register();
3281}
3282
3283Register fastEmit_MipsISD_DivRemU16_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3284 switch (VT.SimpleTy) {
3285 case MVT::i32: return fastEmit_MipsISD_DivRemU16_MVT_i32_rr(RetVT, Op0, Op1);
3286 default: return Register();
3287 }
3288}
3289
3290// FastEmit functions for MipsISD::EH_RETURN.
3291
3292Register fastEmit_MipsISD_EH_RETURN_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3293 if (RetVT.SimpleTy != MVT::isVoid)
3294 return Register();
3295 return fastEmitInst_rr(MachineInstOpcode: Mips::MIPSeh_return32, RC: &Mips::GPR32RegClass, Op0, Op1);
3296}
3297
3298Register fastEmit_MipsISD_EH_RETURN_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3299 if (RetVT.SimpleTy != MVT::isVoid)
3300 return Register();
3301 return fastEmitInst_rr(MachineInstOpcode: Mips::MIPSeh_return64, RC: &Mips::GPR64RegClass, Op0, Op1);
3302}
3303
3304Register fastEmit_MipsISD_EH_RETURN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3305 switch (VT.SimpleTy) {
3306 case MVT::i32: return fastEmit_MipsISD_EH_RETURN_MVT_i32_rr(RetVT, Op0, Op1);
3307 case MVT::i64: return fastEmit_MipsISD_EH_RETURN_MVT_i64_rr(RetVT, Op0, Op1);
3308 default: return Register();
3309 }
3310}
3311
3312// FastEmit functions for MipsISD::ILVEV.
3313
3314Register fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3315 if (RetVT.SimpleTy != MVT::v16i8)
3316 return Register();
3317 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3318 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3319 }
3320 return Register();
3321}
3322
3323Register fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3324 if (RetVT.SimpleTy != MVT::v8i16)
3325 return Register();
3326 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3327 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3328 }
3329 return Register();
3330}
3331
3332Register fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3333 if (RetVT.SimpleTy != MVT::v4i32)
3334 return Register();
3335 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3336 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3337 }
3338 return Register();
3339}
3340
3341Register fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3342 if (RetVT.SimpleTy != MVT::v2i64)
3343 return Register();
3344 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3345 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3346 }
3347 return Register();
3348}
3349
3350Register fastEmit_MipsISD_ILVEV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3351 switch (VT.SimpleTy) {
3352 case MVT::v16i8: return fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(RetVT, Op0, Op1);
3353 case MVT::v8i16: return fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(RetVT, Op0, Op1);
3354 case MVT::v4i32: return fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(RetVT, Op0, Op1);
3355 case MVT::v2i64: return fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(RetVT, Op0, Op1);
3356 default: return Register();
3357 }
3358}
3359
3360// FastEmit functions for MipsISD::ILVL.
3361
3362Register fastEmit_MipsISD_ILVL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3363 if (RetVT.SimpleTy != MVT::v16i8)
3364 return Register();
3365 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3366 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3367 }
3368 return Register();
3369}
3370
3371Register fastEmit_MipsISD_ILVL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3372 if (RetVT.SimpleTy != MVT::v8i16)
3373 return Register();
3374 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3375 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3376 }
3377 return Register();
3378}
3379
3380Register fastEmit_MipsISD_ILVL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3381 if (RetVT.SimpleTy != MVT::v4i32)
3382 return Register();
3383 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3384 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3385 }
3386 return Register();
3387}
3388
3389Register fastEmit_MipsISD_ILVL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3390 if (RetVT.SimpleTy != MVT::v2i64)
3391 return Register();
3392 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3393 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3394 }
3395 return Register();
3396}
3397
3398Register fastEmit_MipsISD_ILVL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3399 switch (VT.SimpleTy) {
3400 case MVT::v16i8: return fastEmit_MipsISD_ILVL_MVT_v16i8_rr(RetVT, Op0, Op1);
3401 case MVT::v8i16: return fastEmit_MipsISD_ILVL_MVT_v8i16_rr(RetVT, Op0, Op1);
3402 case MVT::v4i32: return fastEmit_MipsISD_ILVL_MVT_v4i32_rr(RetVT, Op0, Op1);
3403 case MVT::v2i64: return fastEmit_MipsISD_ILVL_MVT_v2i64_rr(RetVT, Op0, Op1);
3404 default: return Register();
3405 }
3406}
3407
3408// FastEmit functions for MipsISD::ILVOD.
3409
3410Register fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3411 if (RetVT.SimpleTy != MVT::v16i8)
3412 return Register();
3413 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3414 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3415 }
3416 return Register();
3417}
3418
3419Register fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3420 if (RetVT.SimpleTy != MVT::v8i16)
3421 return Register();
3422 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3423 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3424 }
3425 return Register();
3426}
3427
3428Register fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3429 if (RetVT.SimpleTy != MVT::v4i32)
3430 return Register();
3431 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3432 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3433 }
3434 return Register();
3435}
3436
3437Register fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3438 if (RetVT.SimpleTy != MVT::v2i64)
3439 return Register();
3440 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3441 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3442 }
3443 return Register();
3444}
3445
3446Register fastEmit_MipsISD_ILVOD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3447 switch (VT.SimpleTy) {
3448 case MVT::v16i8: return fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(RetVT, Op0, Op1);
3449 case MVT::v8i16: return fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(RetVT, Op0, Op1);
3450 case MVT::v4i32: return fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(RetVT, Op0, Op1);
3451 case MVT::v2i64: return fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(RetVT, Op0, Op1);
3452 default: return Register();
3453 }
3454}
3455
3456// FastEmit functions for MipsISD::ILVR.
3457
3458Register fastEmit_MipsISD_ILVR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3459 if (RetVT.SimpleTy != MVT::v16i8)
3460 return Register();
3461 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3462 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3463 }
3464 return Register();
3465}
3466
3467Register fastEmit_MipsISD_ILVR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3468 if (RetVT.SimpleTy != MVT::v8i16)
3469 return Register();
3470 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3471 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3472 }
3473 return Register();
3474}
3475
3476Register fastEmit_MipsISD_ILVR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3477 if (RetVT.SimpleTy != MVT::v4i32)
3478 return Register();
3479 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3480 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3481 }
3482 return Register();
3483}
3484
3485Register fastEmit_MipsISD_ILVR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3486 if (RetVT.SimpleTy != MVT::v2i64)
3487 return Register();
3488 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3489 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3490 }
3491 return Register();
3492}
3493
3494Register fastEmit_MipsISD_ILVR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3495 switch (VT.SimpleTy) {
3496 case MVT::v16i8: return fastEmit_MipsISD_ILVR_MVT_v16i8_rr(RetVT, Op0, Op1);
3497 case MVT::v8i16: return fastEmit_MipsISD_ILVR_MVT_v8i16_rr(RetVT, Op0, Op1);
3498 case MVT::v4i32: return fastEmit_MipsISD_ILVR_MVT_v4i32_rr(RetVT, Op0, Op1);
3499 case MVT::v2i64: return fastEmit_MipsISD_ILVR_MVT_v2i64_rr(RetVT, Op0, Op1);
3500 default: return Register();
3501 }
3502}
3503
3504// FastEmit functions for MipsISD::MTLOHI.
3505
3506Register fastEmit_MipsISD_MTLOHI_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3507 if (RetVT.SimpleTy != MVT::Untyped)
3508 return Register();
3509 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
3510 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI_MM, RC: &Mips::ACC64RegClass, Op0, Op1);
3511 }
3512 if ((Subtarget->hasDSP()) && (!Subtarget->inMips16Mode())) {
3513 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI_DSP, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3514 }
3515 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3516 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI, RC: &Mips::ACC64RegClass, Op0, Op1);
3517 }
3518 return Register();
3519}
3520
3521Register fastEmit_MipsISD_MTLOHI_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3522 if (RetVT.SimpleTy != MVT::Untyped)
3523 return Register();
3524 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3525 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI64, RC: &Mips::ACC128RegClass, Op0, Op1);
3526 }
3527 return Register();
3528}
3529
3530Register fastEmit_MipsISD_MTLOHI_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3531 switch (VT.SimpleTy) {
3532 case MVT::i32: return fastEmit_MipsISD_MTLOHI_MVT_i32_rr(RetVT, Op0, Op1);
3533 case MVT::i64: return fastEmit_MipsISD_MTLOHI_MVT_i64_rr(RetVT, Op0, Op1);
3534 default: return Register();
3535 }
3536}
3537
3538// FastEmit functions for MipsISD::Mult.
3539
3540Register fastEmit_MipsISD_Mult_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3541 if (RetVT.SimpleTy != MVT::Untyped)
3542 return Register();
3543 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
3544 return fastEmitInst_rr(MachineInstOpcode: Mips::MULT_DSP_MM, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3545 }
3546 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
3547 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULT_MM, RC: &Mips::ACC64RegClass, Op0, Op1);
3548 }
3549 if ((Subtarget->hasDSP())) {
3550 return fastEmitInst_rr(MachineInstOpcode: Mips::MULT_DSP, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3551 }
3552 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3553 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULT, RC: &Mips::ACC64RegClass, Op0, Op1);
3554 }
3555 return Register();
3556}
3557
3558Register fastEmit_MipsISD_Mult_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3559 if (RetVT.SimpleTy != MVT::Untyped)
3560 return Register();
3561 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (!Subtarget->isR5900())) {
3562 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDMULT, RC: &Mips::ACC128RegClass, Op0, Op1);
3563 }
3564 return Register();
3565}
3566
3567Register fastEmit_MipsISD_Mult_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3568 switch (VT.SimpleTy) {
3569 case MVT::i32: return fastEmit_MipsISD_Mult_MVT_i32_rr(RetVT, Op0, Op1);
3570 case MVT::i64: return fastEmit_MipsISD_Mult_MVT_i64_rr(RetVT, Op0, Op1);
3571 default: return Register();
3572 }
3573}
3574
3575// FastEmit functions for MipsISD::Multu.
3576
3577Register fastEmit_MipsISD_Multu_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3578 if (RetVT.SimpleTy != MVT::Untyped)
3579 return Register();
3580 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
3581 return fastEmitInst_rr(MachineInstOpcode: Mips::MULTU_DSP_MM, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3582 }
3583 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
3584 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULTu_MM, RC: &Mips::ACC64RegClass, Op0, Op1);
3585 }
3586 if ((Subtarget->hasDSP())) {
3587 return fastEmitInst_rr(MachineInstOpcode: Mips::MULTU_DSP, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3588 }
3589 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3590 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULTu, RC: &Mips::ACC64RegClass, Op0, Op1);
3591 }
3592 return Register();
3593}
3594
3595Register fastEmit_MipsISD_Multu_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3596 if (RetVT.SimpleTy != MVT::Untyped)
3597 return Register();
3598 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (!Subtarget->isR5900())) {
3599 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDMULTu, RC: &Mips::ACC128RegClass, Op0, Op1);
3600 }
3601 return Register();
3602}
3603
3604Register fastEmit_MipsISD_Multu_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3605 switch (VT.SimpleTy) {
3606 case MVT::i32: return fastEmit_MipsISD_Multu_MVT_i32_rr(RetVT, Op0, Op1);
3607 case MVT::i64: return fastEmit_MipsISD_Multu_MVT_i64_rr(RetVT, Op0, Op1);
3608 default: return Register();
3609 }
3610}
3611
3612// FastEmit functions for MipsISD::PCKEV.
3613
3614Register fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3615 if (RetVT.SimpleTy != MVT::v16i8)
3616 return Register();
3617 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3618 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3619 }
3620 return Register();
3621}
3622
3623Register fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3624 if (RetVT.SimpleTy != MVT::v8i16)
3625 return Register();
3626 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3627 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3628 }
3629 return Register();
3630}
3631
3632Register fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3633 if (RetVT.SimpleTy != MVT::v4i32)
3634 return Register();
3635 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3636 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3637 }
3638 return Register();
3639}
3640
3641Register fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3642 if (RetVT.SimpleTy != MVT::v2i64)
3643 return Register();
3644 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3645 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3646 }
3647 return Register();
3648}
3649
3650Register fastEmit_MipsISD_PCKEV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3651 switch (VT.SimpleTy) {
3652 case MVT::v16i8: return fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(RetVT, Op0, Op1);
3653 case MVT::v8i16: return fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(RetVT, Op0, Op1);
3654 case MVT::v4i32: return fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(RetVT, Op0, Op1);
3655 case MVT::v2i64: return fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(RetVT, Op0, Op1);
3656 default: return Register();
3657 }
3658}
3659
3660// FastEmit functions for MipsISD::PCKOD.
3661
3662Register fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3663 if (RetVT.SimpleTy != MVT::v16i8)
3664 return Register();
3665 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3666 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3667 }
3668 return Register();
3669}
3670
3671Register fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3672 if (RetVT.SimpleTy != MVT::v8i16)
3673 return Register();
3674 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3675 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3676 }
3677 return Register();
3678}
3679
3680Register fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3681 if (RetVT.SimpleTy != MVT::v4i32)
3682 return Register();
3683 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3684 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3685 }
3686 return Register();
3687}
3688
3689Register fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3690 if (RetVT.SimpleTy != MVT::v2i64)
3691 return Register();
3692 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3693 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3694 }
3695 return Register();
3696}
3697
3698Register fastEmit_MipsISD_PCKOD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3699 switch (VT.SimpleTy) {
3700 case MVT::v16i8: return fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(RetVT, Op0, Op1);
3701 case MVT::v8i16: return fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(RetVT, Op0, Op1);
3702 case MVT::v4i32: return fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(RetVT, Op0, Op1);
3703 case MVT::v2i64: return fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(RetVT, Op0, Op1);
3704 default: return Register();
3705 }
3706}
3707
3708// FastEmit functions for MipsISD::VNOR.
3709
3710Register fastEmit_MipsISD_VNOR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3711 if (RetVT.SimpleTy != MVT::v16i8)
3712 return Register();
3713 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3714 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
3715 }
3716 return Register();
3717}
3718
3719Register fastEmit_MipsISD_VNOR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3720 if (RetVT.SimpleTy != MVT::v8i16)
3721 return Register();
3722 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3723 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
3724 }
3725 return Register();
3726}
3727
3728Register fastEmit_MipsISD_VNOR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3729 if (RetVT.SimpleTy != MVT::v4i32)
3730 return Register();
3731 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3732 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
3733 }
3734 return Register();
3735}
3736
3737Register fastEmit_MipsISD_VNOR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3738 if (RetVT.SimpleTy != MVT::v2i64)
3739 return Register();
3740 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3741 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
3742 }
3743 return Register();
3744}
3745
3746Register fastEmit_MipsISD_VNOR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3747 switch (VT.SimpleTy) {
3748 case MVT::v16i8: return fastEmit_MipsISD_VNOR_MVT_v16i8_rr(RetVT, Op0, Op1);
3749 case MVT::v8i16: return fastEmit_MipsISD_VNOR_MVT_v8i16_rr(RetVT, Op0, Op1);
3750 case MVT::v4i32: return fastEmit_MipsISD_VNOR_MVT_v4i32_rr(RetVT, Op0, Op1);
3751 case MVT::v2i64: return fastEmit_MipsISD_VNOR_MVT_v2i64_rr(RetVT, Op0, Op1);
3752 default: return Register();
3753 }
3754}
3755
3756// Top-level FastEmit function.
3757
3758Register fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, Register Op1) override {
3759 switch (Opcode) {
3760 case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op1);
3761 case ISD::ADDC: return fastEmit_ISD_ADDC_rr(VT, RetVT, Op0, Op1);
3762 case ISD::ADDE: return fastEmit_ISD_ADDE_rr(VT, RetVT, Op0, Op1);
3763 case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op1);
3764 case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op1);
3765 case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op1);
3766 case ISD::FMAXNUM: return fastEmit_ISD_FMAXNUM_rr(VT, RetVT, Op0, Op1);
3767 case ISD::FMAXNUM_IEEE: return fastEmit_ISD_FMAXNUM_IEEE_rr(VT, RetVT, Op0, Op1);
3768 case ISD::FMINNUM: return fastEmit_ISD_FMINNUM_rr(VT, RetVT, Op0, Op1);
3769 case ISD::FMINNUM_IEEE: return fastEmit_ISD_FMINNUM_IEEE_rr(VT, RetVT, Op0, Op1);
3770 case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op1);
3771 case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op1);
3772 case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op1);
3773 case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op1);
3774 case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op1);
3775 case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op1);
3776 case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op1);
3777 case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op1);
3778 case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op1);
3779 case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op1);
3780 case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op1);
3781 case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op1);
3782 case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op1);
3783 case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op1);
3784 case ISD::STRICT_FADD: return fastEmit_ISD_STRICT_FADD_rr(VT, RetVT, Op0, Op1);
3785 case ISD::STRICT_FDIV: return fastEmit_ISD_STRICT_FDIV_rr(VT, RetVT, Op0, Op1);
3786 case ISD::STRICT_FMUL: return fastEmit_ISD_STRICT_FMUL_rr(VT, RetVT, Op0, Op1);
3787 case ISD::STRICT_FSUB: return fastEmit_ISD_STRICT_FSUB_rr(VT, RetVT, Op0, Op1);
3788 case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op1);
3789 case ISD::SUBC: return fastEmit_ISD_SUBC_rr(VT, RetVT, Op0, Op1);
3790 case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op1);
3791 case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op1);
3792 case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op1);
3793 case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op1);
3794 case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op1);
3795 case MipsISD::BuildPairF64: return fastEmit_MipsISD_BuildPairF64_rr(VT, RetVT, Op0, Op1);
3796 case MipsISD::DivRem: return fastEmit_MipsISD_DivRem_rr(VT, RetVT, Op0, Op1);
3797 case MipsISD::DivRem16: return fastEmit_MipsISD_DivRem16_rr(VT, RetVT, Op0, Op1);
3798 case MipsISD::DivRemU: return fastEmit_MipsISD_DivRemU_rr(VT, RetVT, Op0, Op1);
3799 case MipsISD::DivRemU16: return fastEmit_MipsISD_DivRemU16_rr(VT, RetVT, Op0, Op1);
3800 case MipsISD::EH_RETURN: return fastEmit_MipsISD_EH_RETURN_rr(VT, RetVT, Op0, Op1);
3801 case MipsISD::ILVEV: return fastEmit_MipsISD_ILVEV_rr(VT, RetVT, Op0, Op1);
3802 case MipsISD::ILVL: return fastEmit_MipsISD_ILVL_rr(VT, RetVT, Op0, Op1);
3803 case MipsISD::ILVOD: return fastEmit_MipsISD_ILVOD_rr(VT, RetVT, Op0, Op1);
3804 case MipsISD::ILVR: return fastEmit_MipsISD_ILVR_rr(VT, RetVT, Op0, Op1);
3805 case MipsISD::MTLOHI: return fastEmit_MipsISD_MTLOHI_rr(VT, RetVT, Op0, Op1);
3806 case MipsISD::Mult: return fastEmit_MipsISD_Mult_rr(VT, RetVT, Op0, Op1);
3807 case MipsISD::Multu: return fastEmit_MipsISD_Multu_rr(VT, RetVT, Op0, Op1);
3808 case MipsISD::PCKEV: return fastEmit_MipsISD_PCKEV_rr(VT, RetVT, Op0, Op1);
3809 case MipsISD::PCKOD: return fastEmit_MipsISD_PCKOD_rr(VT, RetVT, Op0, Op1);
3810 case MipsISD::VNOR: return fastEmit_MipsISD_VNOR_rr(VT, RetVT, Op0, Op1);
3811 default: return Register();
3812 }
3813}
3814
3815// FastEmit functions for MipsISD::ExtractElementF64.
3816
3817Register fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3818 if (RetVT.SimpleTy != MVT::i32)
3819 return Register();
3820 if ((Subtarget->isFP64bit()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMips16Mode())) {
3821 return fastEmitInst_ri(MachineInstOpcode: Mips::ExtractElementF64_64, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3822 }
3823 if ((!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode())) {
3824 return fastEmitInst_ri(MachineInstOpcode: Mips::ExtractElementF64, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3825 }
3826 return Register();
3827}
3828
3829Register fastEmit_MipsISD_ExtractElementF64_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3830 switch (VT.SimpleTy) {
3831 case MVT::f64: return fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(RetVT, Op0, imm1);
3832 default: return Register();
3833 }
3834}
3835
3836// FastEmit functions for MipsISD::SHLL_DSP.
3837
3838Register fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3839 if (RetVT.SimpleTy != MVT::v4i8)
3840 return Register();
3841 if ((Subtarget->hasDSP())) {
3842 return fastEmitInst_ri(MachineInstOpcode: Mips::SHLL_QB, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3843 }
3844 return Register();
3845}
3846
3847Register fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3848 if (RetVT.SimpleTy != MVT::v2i16)
3849 return Register();
3850 if ((Subtarget->hasDSP())) {
3851 return fastEmitInst_ri(MachineInstOpcode: Mips::SHLL_PH, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3852 }
3853 return Register();
3854}
3855
3856Register fastEmit_MipsISD_SHLL_DSP_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3857 switch (VT.SimpleTy) {
3858 case MVT::v4i8: return fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(RetVT, Op0, imm1);
3859 case MVT::v2i16: return fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(RetVT, Op0, imm1);
3860 default: return Register();
3861 }
3862}
3863
3864// FastEmit functions for MipsISD::SHRA_DSP.
3865
3866Register fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3867 if (RetVT.SimpleTy != MVT::v4i8)
3868 return Register();
3869 if ((Subtarget->hasDSPR2())) {
3870 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRA_QB, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3871 }
3872 return Register();
3873}
3874
3875Register fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3876 if (RetVT.SimpleTy != MVT::v2i16)
3877 return Register();
3878 if ((Subtarget->hasDSP())) {
3879 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRA_PH, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3880 }
3881 return Register();
3882}
3883
3884Register fastEmit_MipsISD_SHRA_DSP_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3885 switch (VT.SimpleTy) {
3886 case MVT::v4i8: return fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(RetVT, Op0, imm1);
3887 case MVT::v2i16: return fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(RetVT, Op0, imm1);
3888 default: return Register();
3889 }
3890}
3891
3892// FastEmit functions for MipsISD::SHRL_DSP.
3893
3894Register fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3895 if (RetVT.SimpleTy != MVT::v4i8)
3896 return Register();
3897 if ((Subtarget->hasDSP())) {
3898 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRL_QB, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3899 }
3900 return Register();
3901}
3902
3903Register fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3904 if (RetVT.SimpleTy != MVT::v2i16)
3905 return Register();
3906 if ((Subtarget->hasDSPR2())) {
3907 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRL_PH, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3908 }
3909 return Register();
3910}
3911
3912Register fastEmit_MipsISD_SHRL_DSP_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3913 switch (VT.SimpleTy) {
3914 case MVT::v4i8: return fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(RetVT, Op0, imm1);
3915 case MVT::v2i16: return fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(RetVT, Op0, imm1);
3916 default: return Register();
3917 }
3918}
3919
3920// Top-level FastEmit function.
3921
3922Register fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) override {
3923 if (VT == MVT::i32 && Predicate_immZExt5(Imm: imm1))
3924 if (Register Reg = fastEmit_ri_Predicate_immZExt5(VT, RetVT, Opcode, Op0, imm1))
3925 return Reg;
3926
3927 if (VT == MVT::i32 && Predicate_immZExt6(Imm: imm1))
3928 if (Register Reg = fastEmit_ri_Predicate_immZExt6(VT, RetVT, Opcode, Op0, imm1))
3929 return Reg;
3930
3931 if (VT == MVT::iPTR && Predicate_immZExt2Ptr(Imm: imm1))
3932 if (Register Reg = fastEmit_ri_Predicate_immZExt2Ptr(VT, RetVT, Opcode, Op0, imm1))
3933 return Reg;
3934
3935 if (VT == MVT::iPTR && Predicate_immZExt1Ptr(Imm: imm1))
3936 if (Register Reg = fastEmit_ri_Predicate_immZExt1Ptr(VT, RetVT, Opcode, Op0, imm1))
3937 return Reg;
3938
3939 if (VT == MVT::i32 && Predicate_immZExt4(Imm: imm1))
3940 if (Register Reg = fastEmit_ri_Predicate_immZExt4(VT, RetVT, Opcode, Op0, imm1))
3941 return Reg;
3942
3943 if (VT == MVT::i32 && Predicate_immSExtAddiur2(Imm: imm1))
3944 if (Register Reg = fastEmit_ri_Predicate_immSExtAddiur2(VT, RetVT, Opcode, Op0, imm1))
3945 return Reg;
3946
3947 if (VT == MVT::i32 && Predicate_immSExtAddius5(Imm: imm1))
3948 if (Register Reg = fastEmit_ri_Predicate_immSExtAddius5(VT, RetVT, Opcode, Op0, imm1))
3949 return Reg;
3950
3951 if (VT == MVT::i32 && Predicate_immZExtAndi16(Imm: imm1))
3952 if (Register Reg = fastEmit_ri_Predicate_immZExtAndi16(VT, RetVT, Opcode, Op0, imm1))
3953 return Reg;
3954
3955 if (VT == MVT::i32 && Predicate_immZExt2Shift(Imm: imm1))
3956 if (Register Reg = fastEmit_ri_Predicate_immZExt2Shift(VT, RetVT, Opcode, Op0, imm1))
3957 return Reg;
3958
3959 switch (Opcode) {
3960 case MipsISD::ExtractElementF64: return fastEmit_MipsISD_ExtractElementF64_ri(VT, RetVT, Op0, imm1);
3961 case MipsISD::SHLL_DSP: return fastEmit_MipsISD_SHLL_DSP_ri(VT, RetVT, Op0, imm1);
3962 case MipsISD::SHRA_DSP: return fastEmit_MipsISD_SHRA_DSP_ri(VT, RetVT, Op0, imm1);
3963 case MipsISD::SHRL_DSP: return fastEmit_MipsISD_SHRL_DSP_ri(VT, RetVT, Op0, imm1);
3964 default: return Register();
3965 }
3966}
3967
3968// FastEmit functions for ISD::ROTR.
3969
3970Register fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, Register Op0, uint64_t imm1) {
3971 if (RetVT.SimpleTy != MVT::i32)
3972 return Register();
3973 if ((Subtarget->inMicroMipsMode())) {
3974 return fastEmitInst_ri(MachineInstOpcode: Mips::ROTR_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3975 }
3976 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3977 return fastEmitInst_ri(MachineInstOpcode: Mips::ROTR, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3978 }
3979 return Register();
3980}
3981
3982Register fastEmit_ISD_ROTR_ri_Predicate_immZExt5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3983 switch (VT.SimpleTy) {
3984 case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
3985 default: return Register();
3986 }
3987}
3988
3989// FastEmit functions for ISD::SHL.
3990
3991Register fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, Register Op0, uint64_t imm1) {
3992 if (RetVT.SimpleTy != MVT::i32)
3993 return Register();
3994 if ((Subtarget->inMicroMipsMode())) {
3995 return fastEmitInst_ri(MachineInstOpcode: Mips::SLL_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3996 }
3997 if ((Subtarget->inMips16Mode())) {
3998 return fastEmitInst_ri(MachineInstOpcode: Mips::SllX16, RC: &Mips::CPU16RegsRegClass, Op0, Imm: imm1);
3999 }
4000 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
4001 return fastEmitInst_ri(MachineInstOpcode: Mips::SLL, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
4002 }
4003 return Register();
4004}
4005
4006Register fastEmit_ISD_SHL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4007 switch (VT.SimpleTy) {
4008 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
4009 default: return Register();
4010 }
4011}
4012
4013// FastEmit functions for ISD::SRA.
4014
4015Register fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, Register Op0, uint64_t imm1) {
4016 if (RetVT.SimpleTy != MVT::i32)
4017 return Register();
4018 if ((Subtarget->inMicroMipsMode())) {
4019 return fastEmitInst_ri(MachineInstOpcode: Mips::SRA_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
4020 }
4021 if ((Subtarget->inMips16Mode())) {
4022 return fastEmitInst_ri(MachineInstOpcode: Mips::SraX16, RC: &Mips::CPU16RegsRegClass, Op0, Imm: imm1);
4023 }
4024 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
4025 return fastEmitInst_ri(MachineInstOpcode: Mips::SRA, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
4026 }
4027 return Register();
4028}
4029
4030Register fastEmit_ISD_SRA_ri_Predicate_immZExt5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4031 switch (VT.SimpleTy) {
4032 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
4033 default: return Register();
4034 }
4035}
4036
4037// FastEmit functions for ISD::SRL.
4038
4039Register fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, Register Op0, uint64_t imm1) {
4040 if (RetVT.SimpleTy != MVT::i32)
4041 return Register();
4042 if ((Subtarget->inMicroMipsMode())) {
4043 return fastEmitInst_ri(MachineInstOpcode: Mips::SRL_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
4044 }
4045 if ((Subtarget->inMips16Mode())) {
4046 return fastEmitInst_ri(MachineInstOpcode: Mips::SrlX16, RC: &Mips::CPU16RegsRegClass, Op0, Imm: imm1);
4047 }
4048 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
4049 return fastEmitInst_ri(MachineInstOpcode: Mips::SRL, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
4050 }
4051 return Register();
4052}
4053
4054Register fastEmit_ISD_SRL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4055 switch (VT.SimpleTy) {
4056 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
4057 default: return Register();
4058 }
4059}
4060
4061// Top-level FastEmit function.
4062
4063Register fastEmit_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4064 switch (Opcode) {
4065 case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
4066 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
4067 case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
4068 case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
4069 default: return Register();
4070 }
4071}
4072
4073// FastEmit functions for ISD::ROTR.
4074
4075Register fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, Register Op0, uint64_t imm1) {
4076 if (RetVT.SimpleTy != MVT::i64)
4077 return Register();
4078 if ((Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
4079 return fastEmitInst_ri(MachineInstOpcode: Mips::DROTR, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
4080 }
4081 return Register();
4082}
4083
4084Register fastEmit_ISD_ROTR_ri_Predicate_immZExt6(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4085 switch (VT.SimpleTy) {
4086 case MVT::i64: return fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
4087 default: return Register();
4088 }
4089}
4090
4091// FastEmit functions for ISD::SHL.
4092
4093Register fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, Register Op0, uint64_t imm1) {
4094 if (RetVT.SimpleTy != MVT::i64)
4095 return Register();
4096 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
4097 return fastEmitInst_ri(MachineInstOpcode: Mips::DSLL, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
4098 }
4099 return Register();
4100}
4101
4102Register fastEmit_ISD_SHL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4103 switch (VT.SimpleTy) {
4104 case MVT::i64: return fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
4105 default: return Register();
4106 }
4107}
4108
4109// FastEmit functions for ISD::SRA.
4110
4111Register fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, Register Op0, uint64_t imm1) {
4112 if (RetVT.SimpleTy != MVT::i64)
4113 return Register();
4114 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
4115 return fastEmitInst_ri(MachineInstOpcode: Mips::DSRA, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
4116 }
4117 return Register();
4118}
4119
4120Register fastEmit_ISD_SRA_ri_Predicate_immZExt6(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4121 switch (VT.SimpleTy) {
4122 case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
4123 default: return Register();
4124 }
4125}
4126
4127// FastEmit functions for ISD::SRL.
4128
4129Register fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, Register Op0, uint64_t imm1) {
4130 if (RetVT.SimpleTy != MVT::i64)
4131 return Register();
4132 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
4133 return fastEmitInst_ri(MachineInstOpcode: Mips::DSRL, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
4134 }
4135 return Register();
4136}
4137
4138Register fastEmit_ISD_SRL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4139 switch (VT.SimpleTy) {
4140 case MVT::i64: return fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
4141 default: return Register();
4142 }
4143}
4144
4145// Top-level FastEmit function.
4146
4147Register fastEmit_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4148 switch (Opcode) {
4149 case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
4150 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
4151 case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
4152 case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
4153 default: return Register();
4154 }
4155}
4156
4157// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
4158
4159Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(MVT RetVT, Register Op0, uint64_t imm1) {
4160 if (RetVT.SimpleTy != MVT::f32)
4161 return Register();
4162 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
4163 return fastEmitInst_ri(MachineInstOpcode: Mips::COPY_FW_PSEUDO, RC: &Mips::FGR32RegClass, Op0, Imm: imm1);
4164 }
4165 return Register();
4166}
4167
4168Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4169 switch (VT.SimpleTy) {
4170 case MVT::v4f32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(RetVT, Op0, imm1);
4171 default: return Register();
4172 }
4173}
4174
4175// Top-level FastEmit function.
4176
4177Register fastEmit_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4178 switch (Opcode) {
4179 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(VT, RetVT, Op0, imm1);
4180 default: return Register();
4181 }
4182}
4183
4184// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
4185
4186Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(MVT RetVT, Register Op0, uint64_t imm1) {
4187 if (RetVT.SimpleTy != MVT::f64)
4188 return Register();
4189 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
4190 return fastEmitInst_ri(MachineInstOpcode: Mips::COPY_FD_PSEUDO, RC: &Mips::FGR64RegClass, Op0, Imm: imm1);
4191 }
4192 return Register();
4193}
4194
4195Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4196 switch (VT.SimpleTy) {
4197 case MVT::v2f64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(RetVT, Op0, imm1);
4198 default: return Register();
4199 }
4200}
4201
4202// Top-level FastEmit function.
4203
4204Register fastEmit_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4205 switch (Opcode) {
4206 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(VT, RetVT, Op0, imm1);
4207 default: return Register();
4208 }
4209}
4210
4211// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
4212
4213Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(MVT RetVT, Register Op0, uint64_t imm1) {
4214 if (RetVT.SimpleTy != MVT::i32)
4215 return Register();
4216 if ((Subtarget->hasMSA())) {
4217 return fastEmitInst_ri(MachineInstOpcode: Mips::COPY_S_W, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
4218 }
4219 return Register();
4220}
4221
4222Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4223 switch (VT.SimpleTy) {
4224 case MVT::v4i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(RetVT, Op0, imm1);
4225 default: return Register();
4226 }
4227}
4228
4229// Top-level FastEmit function.
4230
4231Register fastEmit_ri_Predicate_immZExt4(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4232 switch (Opcode) {
4233 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(VT, RetVT, Op0, imm1);
4234 default: return Register();
4235 }
4236}
4237
4238// FastEmit functions for ISD::ADD.
4239
4240Register fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(MVT RetVT, Register Op0, uint64_t imm1) {
4241 if (RetVT.SimpleTy != MVT::i32)
4242 return Register();
4243 if ((Subtarget->inMicroMipsMode())) {
4244 return fastEmitInst_ri(MachineInstOpcode: Mips::ADDIUR2_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4245 }
4246 return Register();
4247}
4248
4249Register fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4250 switch (VT.SimpleTy) {
4251 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(RetVT, Op0, imm1);
4252 default: return Register();
4253 }
4254}
4255
4256// Top-level FastEmit function.
4257
4258Register fastEmit_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4259 switch (Opcode) {
4260 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(VT, RetVT, Op0, imm1);
4261 default: return Register();
4262 }
4263}
4264
4265// FastEmit functions for ISD::ADD.
4266
4267Register fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(MVT RetVT, Register Op0, uint64_t imm1) {
4268 if (RetVT.SimpleTy != MVT::i32)
4269 return Register();
4270 if ((Subtarget->inMicroMipsMode())) {
4271 return fastEmitInst_ri(MachineInstOpcode: Mips::ADDIUS5_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
4272 }
4273 return Register();
4274}
4275
4276Register fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4277 switch (VT.SimpleTy) {
4278 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(RetVT, Op0, imm1);
4279 default: return Register();
4280 }
4281}
4282
4283// Top-level FastEmit function.
4284
4285Register fastEmit_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4286 switch (Opcode) {
4287 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(VT, RetVT, Op0, imm1);
4288 default: return Register();
4289 }
4290}
4291
4292// FastEmit functions for ISD::AND.
4293
4294Register fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(MVT RetVT, Register Op0, uint64_t imm1) {
4295 if (RetVT.SimpleTy != MVT::i32)
4296 return Register();
4297 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
4298 return fastEmitInst_ri(MachineInstOpcode: Mips::ANDI16_MMR6, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4299 }
4300 if ((Subtarget->inMicroMipsMode())) {
4301 return fastEmitInst_ri(MachineInstOpcode: Mips::ANDI16_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4302 }
4303 return Register();
4304}
4305
4306Register fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4307 switch (VT.SimpleTy) {
4308 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(RetVT, Op0, imm1);
4309 default: return Register();
4310 }
4311}
4312
4313// Top-level FastEmit function.
4314
4315Register fastEmit_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4316 switch (Opcode) {
4317 case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(VT, RetVT, Op0, imm1);
4318 default: return Register();
4319 }
4320}
4321
4322// FastEmit functions for ISD::SHL.
4323
4324Register fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, Register Op0, uint64_t imm1) {
4325 if (RetVT.SimpleTy != MVT::i32)
4326 return Register();
4327 if ((Subtarget->inMicroMipsMode())) {
4328 return fastEmitInst_ri(MachineInstOpcode: Mips::SLL16_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4329 }
4330 return Register();
4331}
4332
4333Register fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4334 switch (VT.SimpleTy) {
4335 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, imm1);
4336 default: return Register();
4337 }
4338}
4339
4340// FastEmit functions for ISD::SRL.
4341
4342Register fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, Register Op0, uint64_t imm1) {
4343 if (RetVT.SimpleTy != MVT::i32)
4344 return Register();
4345 if ((Subtarget->inMicroMipsMode())) {
4346 return fastEmitInst_ri(MachineInstOpcode: Mips::SRL16_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4347 }
4348 return Register();
4349}
4350
4351Register fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4352 switch (VT.SimpleTy) {
4353 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, imm1);
4354 default: return Register();
4355 }
4356}
4357
4358// Top-level FastEmit function.
4359
4360Register fastEmit_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4361 switch (Opcode) {
4362 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, imm1);
4363 case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, imm1);
4364 default: return Register();
4365 }
4366}
4367
4368// FastEmit functions for ISD::Constant.
4369
4370Register fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) {
4371 if (RetVT.SimpleTy != MVT::i32)
4372 return Register();
4373 if ((Subtarget->inMips16Mode())) {
4374 return fastEmitInst_i(MachineInstOpcode: Mips::LwConstant32, RC: &Mips::CPU16RegsRegClass, Imm: imm0);
4375 }
4376 return Register();
4377}
4378
4379Register fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) {
4380 switch (VT.SimpleTy) {
4381 case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0);
4382 default: return Register();
4383 }
4384}
4385
4386// Top-level FastEmit function.
4387
4388Register fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override {
4389 switch (Opcode) {
4390 case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0);
4391 default: return Register();
4392 }
4393}
4394
4395