1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* "Fast" Instruction Selector for the Mips target *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10// FastEmit Immediate Predicate functions.
11static bool Predicate_immZExt5(int64_t Imm) {
12return Imm == (Imm & 0x1f);
13}
14static bool Predicate_immZExt6(int64_t Imm) {
15return Imm == (Imm & 0x3f);
16}
17static bool Predicate_immSExt6(int64_t Imm) {
18return isInt<6>(x: Imm);
19}
20static bool Predicate_immZExt4Ptr(int64_t Imm) {
21return isUInt<4>(x: Imm);
22}
23static bool Predicate_immZExt3Ptr(int64_t Imm) {
24return isUInt<3>(x: Imm);
25}
26static bool Predicate_immZExt2Ptr(int64_t Imm) {
27return isUInt<2>(x: Imm);
28}
29static bool Predicate_immZExt1Ptr(int64_t Imm) {
30return isUInt<1>(x: Imm);
31}
32static bool Predicate_immZExt4(int64_t Imm) {
33return isUInt<4>(x: Imm);
34}
35static bool Predicate_immSExtAddiur2(int64_t Imm) {
36return Imm == 1 || Imm == -1 ||
37 ((Imm % 4 == 0) &&
38 Imm < 28 && Imm > 0);
39}
40static bool Predicate_immSExtAddius5(int64_t Imm) {
41return Imm >= -8 && Imm <= 7;
42}
43static bool Predicate_immZExtAndi16(int64_t Imm) {
44return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
45 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
46 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
47}
48static bool Predicate_immZExt2Shift(int64_t Imm) {
49return Imm >= 1 && Imm <= 8;
50}
51
52
53// FastEmit functions for ISD::BITCAST.
54
55Register fastEmit_ISD_BITCAST_MVT_i32_r(MVT RetVT, Register Op0) {
56 if (RetVT.SimpleTy != MVT::f32)
57 return Register();
58 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
59 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_MMR6, RC: &Mips::FGR32RegClass, Op0);
60 }
61 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
62 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_MM, RC: &Mips::FGR32RegClass, Op0);
63 }
64 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
65 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1, RC: &Mips::FGR32RegClass, Op0);
66 }
67 return Register();
68}
69
70Register fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, Register Op0) {
71 if (RetVT.SimpleTy != MVT::f64)
72 return Register();
73 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
74 return fastEmitInst_r(MachineInstOpcode: Mips::DMTC1, RC: &Mips::FGR64RegClass, Op0);
75 }
76 return Register();
77}
78
79Register fastEmit_ISD_BITCAST_MVT_f32_r(MVT RetVT, Register Op0) {
80 if (RetVT.SimpleTy != MVT::i32)
81 return Register();
82 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
83 return fastEmitInst_r(MachineInstOpcode: Mips::MFC1_MMR6, RC: &Mips::GPR32RegClass, Op0);
84 }
85 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
86 return fastEmitInst_r(MachineInstOpcode: Mips::MFC1_MM, RC: &Mips::GPR32RegClass, Op0);
87 }
88 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
89 return fastEmitInst_r(MachineInstOpcode: Mips::MFC1, RC: &Mips::GPR32RegClass, Op0);
90 }
91 return Register();
92}
93
94Register fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, Register Op0) {
95 if (RetVT.SimpleTy != MVT::i64)
96 return Register();
97 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
98 return fastEmitInst_r(MachineInstOpcode: Mips::DMFC1, RC: &Mips::GPR64RegClass, Op0);
99 }
100 return Register();
101}
102
103Register fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, Register Op0) {
104 switch (VT.SimpleTy) {
105 case MVT::i32: return fastEmit_ISD_BITCAST_MVT_i32_r(RetVT, Op0);
106 case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0);
107 case MVT::f32: return fastEmit_ISD_BITCAST_MVT_f32_r(RetVT, Op0);
108 case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0);
109 default: return Register();
110 }
111}
112
113// FastEmit functions for ISD::CTLZ.
114
115Register fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, Register Op0) {
116 if (RetVT.SimpleTy != MVT::i32)
117 return Register();
118 if ((Subtarget->inMicroMipsMode())) {
119 return fastEmitInst_r(MachineInstOpcode: Mips::CLZ_MM, RC: &Mips::GPR32RegClass, Op0);
120 }
121 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding())) {
122 return fastEmitInst_r(MachineInstOpcode: Mips::CLZ_R6, RC: &Mips::GPR32RegClass, Op0);
123 }
124 if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
125 return fastEmitInst_r(MachineInstOpcode: Mips::CLZ, RC: &Mips::GPR32RegClass, Op0);
126 }
127 return Register();
128}
129
130Register fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, Register Op0) {
131 if (RetVT.SimpleTy != MVT::i64)
132 return Register();
133 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
134 return fastEmitInst_r(MachineInstOpcode: Mips::DCLZ_R6, RC: &Mips::GPR64RegClass, Op0);
135 }
136 if ((Subtarget->hasMips64()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips64r6())) {
137 return fastEmitInst_r(MachineInstOpcode: Mips::DCLZ, RC: &Mips::GPR64RegClass, Op0);
138 }
139 return Register();
140}
141
142Register fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, Register Op0) {
143 if (RetVT.SimpleTy != MVT::v16i8)
144 return Register();
145 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
146 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_B, RC: &Mips::MSA128BRegClass, Op0);
147 }
148 return Register();
149}
150
151Register fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, Register Op0) {
152 if (RetVT.SimpleTy != MVT::v8i16)
153 return Register();
154 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
155 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_H, RC: &Mips::MSA128HRegClass, Op0);
156 }
157 return Register();
158}
159
160Register fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, Register Op0) {
161 if (RetVT.SimpleTy != MVT::v4i32)
162 return Register();
163 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
164 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_W, RC: &Mips::MSA128WRegClass, Op0);
165 }
166 return Register();
167}
168
169Register fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, Register Op0) {
170 if (RetVT.SimpleTy != MVT::v2i64)
171 return Register();
172 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
173 return fastEmitInst_r(MachineInstOpcode: Mips::NLZC_D, RC: &Mips::MSA128DRegClass, Op0);
174 }
175 return Register();
176}
177
178Register fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, Register Op0) {
179 switch (VT.SimpleTy) {
180 case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0);
181 case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0);
182 case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0);
183 case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0);
184 case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0);
185 case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0);
186 default: return Register();
187 }
188}
189
190// FastEmit functions for ISD::CTPOP.
191
192Register fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, Register Op0) {
193 if (RetVT.SimpleTy != MVT::i32)
194 return Register();
195 if ((Subtarget->hasCnMips())) {
196 return fastEmitInst_r(MachineInstOpcode: Mips::POP, RC: &Mips::GPR32RegClass, Op0);
197 }
198 return Register();
199}
200
201Register fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, Register Op0) {
202 if (RetVT.SimpleTy != MVT::i64)
203 return Register();
204 if ((Subtarget->hasCnMips())) {
205 return fastEmitInst_r(MachineInstOpcode: Mips::DPOP, RC: &Mips::GPR64RegClass, Op0);
206 }
207 return Register();
208}
209
210Register fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, Register Op0) {
211 if (RetVT.SimpleTy != MVT::v16i8)
212 return Register();
213 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
214 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_B, RC: &Mips::MSA128BRegClass, Op0);
215 }
216 return Register();
217}
218
219Register fastEmit_ISD_CTPOP_MVT_v8i16_r(MVT RetVT, Register Op0) {
220 if (RetVT.SimpleTy != MVT::v8i16)
221 return Register();
222 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
223 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_H, RC: &Mips::MSA128HRegClass, Op0);
224 }
225 return Register();
226}
227
228Register fastEmit_ISD_CTPOP_MVT_v4i32_r(MVT RetVT, Register Op0) {
229 if (RetVT.SimpleTy != MVT::v4i32)
230 return Register();
231 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
232 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_W, RC: &Mips::MSA128WRegClass, Op0);
233 }
234 return Register();
235}
236
237Register fastEmit_ISD_CTPOP_MVT_v2i64_r(MVT RetVT, Register Op0) {
238 if (RetVT.SimpleTy != MVT::v2i64)
239 return Register();
240 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
241 return fastEmitInst_r(MachineInstOpcode: Mips::PCNT_D, RC: &Mips::MSA128DRegClass, Op0);
242 }
243 return Register();
244}
245
246Register fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, Register Op0) {
247 switch (VT.SimpleTy) {
248 case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0);
249 case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0);
250 case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0);
251 case MVT::v8i16: return fastEmit_ISD_CTPOP_MVT_v8i16_r(RetVT, Op0);
252 case MVT::v4i32: return fastEmit_ISD_CTPOP_MVT_v4i32_r(RetVT, Op0);
253 case MVT::v2i64: return fastEmit_ISD_CTPOP_MVT_v2i64_r(RetVT, Op0);
254 default: return Register();
255 }
256}
257
258// FastEmit functions for ISD::FABS.
259
260Register fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, Register Op0) {
261 if (RetVT.SimpleTy != MVT::f32)
262 return Register();
263 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
264 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_S_MM, RC: &Mips::FGR32RegClass, Op0);
265 }
266 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
267 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_S, RC: &Mips::FGR32RegClass, Op0);
268 }
269 return Register();
270}
271
272Register fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, Register Op0) {
273 if (RetVT.SimpleTy != MVT::f64)
274 return Register();
275 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
276 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D64_MM, RC: &Mips::FGR64RegClass, Op0);
277 }
278 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
279 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D32_MM, RC: &Mips::AFGR64RegClass, Op0);
280 }
281 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
282 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D64, RC: &Mips::FGR64RegClass, Op0);
283 }
284 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
285 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D32, RC: &Mips::AFGR64RegClass, Op0);
286 }
287 return Register();
288}
289
290Register fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, Register Op0) {
291 if (RetVT.SimpleTy != MVT::v4f32)
292 return Register();
293 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
294 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_W, RC: &Mips::MSA128WRegClass, Op0);
295 }
296 return Register();
297}
298
299Register fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, Register Op0) {
300 if (RetVT.SimpleTy != MVT::v2f64)
301 return Register();
302 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
303 return fastEmitInst_r(MachineInstOpcode: Mips::FABS_D, RC: &Mips::MSA128DRegClass, Op0);
304 }
305 return Register();
306}
307
308Register fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, Register Op0) {
309 switch (VT.SimpleTy) {
310 case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0);
311 case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0);
312 case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0);
313 case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0);
314 default: return Register();
315 }
316}
317
318// FastEmit functions for ISD::FEXP2.
319
320Register fastEmit_ISD_FEXP2_MVT_v4f32_r(MVT RetVT, Register Op0) {
321 if (RetVT.SimpleTy != MVT::v4f32)
322 return Register();
323 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
324 return fastEmitInst_r(MachineInstOpcode: Mips::FEXP2_W_1_PSEUDO, RC: &Mips::MSA128WRegClass, Op0);
325 }
326 return Register();
327}
328
329Register fastEmit_ISD_FEXP2_MVT_v2f64_r(MVT RetVT, Register Op0) {
330 if (RetVT.SimpleTy != MVT::v2f64)
331 return Register();
332 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
333 return fastEmitInst_r(MachineInstOpcode: Mips::FEXP2_D_1_PSEUDO, RC: &Mips::MSA128DRegClass, Op0);
334 }
335 return Register();
336}
337
338Register fastEmit_ISD_FEXP2_r(MVT VT, MVT RetVT, Register Op0) {
339 switch (VT.SimpleTy) {
340 case MVT::v4f32: return fastEmit_ISD_FEXP2_MVT_v4f32_r(RetVT, Op0);
341 case MVT::v2f64: return fastEmit_ISD_FEXP2_MVT_v2f64_r(RetVT, Op0);
342 default: return Register();
343 }
344}
345
346// FastEmit functions for ISD::FLOG2.
347
348Register fastEmit_ISD_FLOG2_MVT_v4f32_r(MVT RetVT, Register Op0) {
349 if (RetVT.SimpleTy != MVT::v4f32)
350 return Register();
351 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
352 return fastEmitInst_r(MachineInstOpcode: Mips::FLOG2_W, RC: &Mips::MSA128WRegClass, Op0);
353 }
354 return Register();
355}
356
357Register fastEmit_ISD_FLOG2_MVT_v2f64_r(MVT RetVT, Register Op0) {
358 if (RetVT.SimpleTy != MVT::v2f64)
359 return Register();
360 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
361 return fastEmitInst_r(MachineInstOpcode: Mips::FLOG2_D, RC: &Mips::MSA128DRegClass, Op0);
362 }
363 return Register();
364}
365
366Register fastEmit_ISD_FLOG2_r(MVT VT, MVT RetVT, Register Op0) {
367 switch (VT.SimpleTy) {
368 case MVT::v4f32: return fastEmit_ISD_FLOG2_MVT_v4f32_r(RetVT, Op0);
369 case MVT::v2f64: return fastEmit_ISD_FLOG2_MVT_v2f64_r(RetVT, Op0);
370 default: return Register();
371 }
372}
373
374// FastEmit functions for ISD::FNEG.
375
376Register fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, Register Op0) {
377 if (RetVT.SimpleTy != MVT::f32)
378 return Register();
379 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
380 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_S_MMR6, RC: &Mips::FGR32RegClass, Op0);
381 }
382 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
383 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_S_MM, RC: &Mips::FGR32RegClass, Op0);
384 }
385 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat())) {
386 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_S, RC: &Mips::FGR32RegClass, Op0);
387 }
388 return Register();
389}
390
391Register fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, Register Op0) {
392 if (RetVT.SimpleTy != MVT::f64)
393 return Register();
394 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
395 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D64_MM, RC: &Mips::FGR64RegClass, Op0);
396 }
397 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
398 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D32_MM, RC: &Mips::AFGR64RegClass, Op0);
399 }
400 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
401 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D64, RC: &Mips::FGR64RegClass, Op0);
402 }
403 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
404 return fastEmitInst_r(MachineInstOpcode: Mips::FNEG_D32, RC: &Mips::AFGR64RegClass, Op0);
405 }
406 return Register();
407}
408
409Register fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, Register Op0) {
410 switch (VT.SimpleTy) {
411 case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0);
412 case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0);
413 default: return Register();
414 }
415}
416
417// FastEmit functions for ISD::FP_EXTEND.
418
419Register fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, Register Op0) {
420 if (RetVT.SimpleTy != MVT::f64)
421 return Register();
422 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) {
423 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D32_S_MM, RC: &Mips::AFGR64RegClass, Op0);
424 }
425 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
426 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D64_S_MM, RC: &Mips::FGR64RegClass, Op0);
427 }
428 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->inMicroMipsMode())) {
429 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D64_S, RC: &Mips::FGR64RegClass, Op0);
430 }
431 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
432 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D32_S, RC: &Mips::AFGR64RegClass, Op0);
433 }
434 return Register();
435}
436
437Register fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
438 switch (VT.SimpleTy) {
439 case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0);
440 default: return Register();
441 }
442}
443
444// FastEmit functions for ISD::FP_ROUND.
445
446Register fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, Register Op0) {
447 if (RetVT.SimpleTy != MVT::f32)
448 return Register();
449 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) {
450 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D32_MM, RC: &Mips::FGR32RegClass, Op0);
451 }
452 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
453 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D64_MM, RC: &Mips::FGR32RegClass, Op0);
454 }
455 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->inMicroMipsMode())) {
456 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D64, RC: &Mips::FGR32RegClass, Op0);
457 }
458 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
459 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D32, RC: &Mips::FGR32RegClass, Op0);
460 }
461 return Register();
462}
463
464Register fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, Register Op0) {
465 switch (VT.SimpleTy) {
466 case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0);
467 default: return Register();
468 }
469}
470
471// FastEmit functions for ISD::FP_TO_SINT.
472
473Register fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
474 if (RetVT.SimpleTy != MVT::v4i32)
475 return Register();
476 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
477 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_S_W, RC: &Mips::MSA128WRegClass, Op0);
478 }
479 return Register();
480}
481
482Register fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
483 if (RetVT.SimpleTy != MVT::v2i64)
484 return Register();
485 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
486 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_S_D, RC: &Mips::MSA128DRegClass, Op0);
487 }
488 return Register();
489}
490
491Register fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, Register Op0) {
492 switch (VT.SimpleTy) {
493 case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0);
494 case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0);
495 default: return Register();
496 }
497}
498
499// FastEmit functions for ISD::FP_TO_UINT.
500
501Register fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
502 if (RetVT.SimpleTy != MVT::v4i32)
503 return Register();
504 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
505 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_U_W, RC: &Mips::MSA128WRegClass, Op0);
506 }
507 return Register();
508}
509
510Register fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
511 if (RetVT.SimpleTy != MVT::v2i64)
512 return Register();
513 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
514 return fastEmitInst_r(MachineInstOpcode: Mips::FTRUNC_U_D, RC: &Mips::MSA128DRegClass, Op0);
515 }
516 return Register();
517}
518
519Register fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, Register Op0) {
520 switch (VT.SimpleTy) {
521 case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0);
522 case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0);
523 default: return Register();
524 }
525}
526
527// FastEmit functions for ISD::FRINT.
528
529Register fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, Register Op0) {
530 if (RetVT.SimpleTy != MVT::v4f32)
531 return Register();
532 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
533 return fastEmitInst_r(MachineInstOpcode: Mips::FRINT_W, RC: &Mips::MSA128WRegClass, Op0);
534 }
535 return Register();
536}
537
538Register fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, Register Op0) {
539 if (RetVT.SimpleTy != MVT::v2f64)
540 return Register();
541 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
542 return fastEmitInst_r(MachineInstOpcode: Mips::FRINT_D, RC: &Mips::MSA128DRegClass, Op0);
543 }
544 return Register();
545}
546
547Register fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, Register Op0) {
548 switch (VT.SimpleTy) {
549 case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0);
550 case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0);
551 default: return Register();
552 }
553}
554
555// FastEmit functions for ISD::FSQRT.
556
557Register fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, Register Op0) {
558 if (RetVT.SimpleTy != MVT::f32)
559 return Register();
560 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
561 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_S_MM, RC: &Mips::FGR32RegClass, Op0);
562 }
563 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
564 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_S, RC: &Mips::FGR32RegClass, Op0);
565 }
566 return Register();
567}
568
569Register fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, Register Op0) {
570 if (RetVT.SimpleTy != MVT::f64)
571 return Register();
572 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
573 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D64_MM, RC: &Mips::FGR64RegClass, Op0);
574 }
575 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
576 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D32_MM, RC: &Mips::AFGR64RegClass, Op0);
577 }
578 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
579 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D64, RC: &Mips::FGR64RegClass, Op0);
580 }
581 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
582 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D32, RC: &Mips::AFGR64RegClass, Op0);
583 }
584 return Register();
585}
586
587Register fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, Register Op0) {
588 if (RetVT.SimpleTy != MVT::v4f32)
589 return Register();
590 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
591 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_W, RC: &Mips::MSA128WRegClass, Op0);
592 }
593 return Register();
594}
595
596Register fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, Register Op0) {
597 if (RetVT.SimpleTy != MVT::v2f64)
598 return Register();
599 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
600 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D, RC: &Mips::MSA128DRegClass, Op0);
601 }
602 return Register();
603}
604
605Register fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, Register Op0) {
606 switch (VT.SimpleTy) {
607 case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0);
608 case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0);
609 case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0);
610 case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0);
611 default: return Register();
612 }
613}
614
615// FastEmit functions for ISD::SIGN_EXTEND.
616
617Register fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, Register Op0) {
618 if (RetVT.SimpleTy != MVT::i64)
619 return Register();
620 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit())) {
621 return fastEmitInst_r(MachineInstOpcode: Mips::SLL64_32, RC: &Mips::GPR64RegClass, Op0);
622 }
623 return Register();
624}
625
626Register fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
627 switch (VT.SimpleTy) {
628 case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0);
629 default: return Register();
630 }
631}
632
633// FastEmit functions for ISD::SINT_TO_FP.
634
635Register fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
636 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_S_W, RC: &Mips::FGR32RegClass, Op0);
637}
638
639Register fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
640 if ((Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
641 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D64_W, RC: &Mips::FGR64RegClass, Op0);
642 }
643 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) {
644 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D32_W, RC: &Mips::AFGR64RegClass, Op0);
645 }
646 return Register();
647}
648
649Register fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
650switch (RetVT.SimpleTy) {
651 case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
652 case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
653 default: return Register();
654}
655}
656
657Register fastEmit_ISD_SINT_TO_FP_MVT_i64_r(MVT RetVT, Register Op0) {
658 if (RetVT.SimpleTy != MVT::f64)
659 return Register();
660 if ((Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
661 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D64_L, RC: &Mips::FGR64RegClass, Op0);
662 }
663 return Register();
664}
665
666Register fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
667 if (RetVT.SimpleTy != MVT::v4f32)
668 return Register();
669 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
670 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_S_W, RC: &Mips::MSA128WRegClass, Op0);
671 }
672 return Register();
673}
674
675Register fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, Register Op0) {
676 if (RetVT.SimpleTy != MVT::v2f64)
677 return Register();
678 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
679 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_S_D, RC: &Mips::MSA128DRegClass, Op0);
680 }
681 return Register();
682}
683
684Register fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
685 switch (VT.SimpleTy) {
686 case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0);
687 case MVT::i64: return fastEmit_ISD_SINT_TO_FP_MVT_i64_r(RetVT, Op0);
688 case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
689 case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
690 default: return Register();
691 }
692}
693
694// FastEmit functions for ISD::STRICT_FP_EXTEND.
695
696Register fastEmit_ISD_STRICT_FP_EXTEND_MVT_f32_r(MVT RetVT, Register Op0) {
697 if (RetVT.SimpleTy != MVT::f64)
698 return Register();
699 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->inMicroMipsMode())) {
700 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D64_S, RC: &Mips::FGR64RegClass, Op0);
701 }
702 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
703 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_D32_S, RC: &Mips::AFGR64RegClass, Op0);
704 }
705 return Register();
706}
707
708Register fastEmit_ISD_STRICT_FP_EXTEND_r(MVT VT, MVT RetVT, Register Op0) {
709 switch (VT.SimpleTy) {
710 case MVT::f32: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_f32_r(RetVT, Op0);
711 default: return Register();
712 }
713}
714
715// FastEmit functions for ISD::STRICT_FP_ROUND.
716
717Register fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(MVT RetVT, Register Op0) {
718 if (RetVT.SimpleTy != MVT::f32)
719 return Register();
720 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->inMicroMipsMode())) {
721 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D64, RC: &Mips::FGR32RegClass, Op0);
722 }
723 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
724 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_S_D32, RC: &Mips::FGR32RegClass, Op0);
725 }
726 return Register();
727}
728
729Register fastEmit_ISD_STRICT_FP_ROUND_r(MVT VT, MVT RetVT, Register Op0) {
730 switch (VT.SimpleTy) {
731 case MVT::f64: return fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(RetVT, Op0);
732 default: return Register();
733 }
734}
735
736// FastEmit functions for ISD::STRICT_FSQRT.
737
738Register fastEmit_ISD_STRICT_FSQRT_MVT_f32_r(MVT RetVT, Register Op0) {
739 if (RetVT.SimpleTy != MVT::f32)
740 return Register();
741 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
742 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_S, RC: &Mips::FGR32RegClass, Op0);
743 }
744 return Register();
745}
746
747Register fastEmit_ISD_STRICT_FSQRT_MVT_f64_r(MVT RetVT, Register Op0) {
748 if (RetVT.SimpleTy != MVT::f64)
749 return Register();
750 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
751 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D64, RC: &Mips::FGR64RegClass, Op0);
752 }
753 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
754 return fastEmitInst_r(MachineInstOpcode: Mips::FSQRT_D32, RC: &Mips::AFGR64RegClass, Op0);
755 }
756 return Register();
757}
758
759Register fastEmit_ISD_STRICT_FSQRT_r(MVT VT, MVT RetVT, Register Op0) {
760 switch (VT.SimpleTy) {
761 case MVT::f32: return fastEmit_ISD_STRICT_FSQRT_MVT_f32_r(RetVT, Op0);
762 case MVT::f64: return fastEmit_ISD_STRICT_FSQRT_MVT_f64_r(RetVT, Op0);
763 default: return Register();
764 }
765}
766
767// FastEmit functions for ISD::STRICT_SINT_TO_FP.
768
769Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(Register Op0) {
770 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_S_W, RC: &Mips::FGR32RegClass, Op0);
771}
772
773Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(Register Op0) {
774 if ((Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
775 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D64_W, RC: &Mips::FGR64RegClass, Op0);
776 }
777 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) {
778 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D32_W, RC: &Mips::AFGR64RegClass, Op0);
779 }
780 return Register();
781}
782
783Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(MVT RetVT, Register Op0) {
784switch (RetVT.SimpleTy) {
785 case MVT::f32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0);
786 case MVT::f64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0);
787 default: return Register();
788}
789}
790
791Register fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_r(MVT RetVT, Register Op0) {
792 if (RetVT.SimpleTy != MVT::f64)
793 return Register();
794 if ((Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
795 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoCVT_D64_L, RC: &Mips::FGR64RegClass, Op0);
796 }
797 return Register();
798}
799
800Register fastEmit_ISD_STRICT_SINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
801 switch (VT.SimpleTy) {
802 case MVT::i32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(RetVT, Op0);
803 case MVT::i64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i64_r(RetVT, Op0);
804 default: return Register();
805 }
806}
807
808// FastEmit functions for ISD::UINT_TO_FP.
809
810Register fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, Register Op0) {
811 if (RetVT.SimpleTy != MVT::v4f32)
812 return Register();
813 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
814 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_U_W, RC: &Mips::MSA128WRegClass, Op0);
815 }
816 return Register();
817}
818
819Register fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, Register Op0) {
820 if (RetVT.SimpleTy != MVT::v2f64)
821 return Register();
822 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
823 return fastEmitInst_r(MachineInstOpcode: Mips::FFINT_U_D, RC: &Mips::MSA128DRegClass, Op0);
824 }
825 return Register();
826}
827
828Register fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, Register Op0) {
829 switch (VT.SimpleTy) {
830 case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0);
831 case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0);
832 default: return Register();
833 }
834}
835
836// FastEmit functions for MipsISD::MFHI.
837
838Register fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(Register Op0) {
839 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
840 return fastEmitInst_r(MachineInstOpcode: Mips::MFHI_DSP_MM, RC: &Mips::GPR32RegClass, Op0);
841 }
842 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
843 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFHI_MM, RC: &Mips::GPR32RegClass, Op0);
844 }
845 if ((Subtarget->hasDSP())) {
846 return fastEmitInst_r(MachineInstOpcode: Mips::MFHI_DSP, RC: &Mips::GPR32RegClass, Op0);
847 }
848 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
849 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFHI, RC: &Mips::GPR32RegClass, Op0);
850 }
851 return Register();
852}
853
854Register fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(Register Op0) {
855 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
856 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFHI64, RC: &Mips::GPR64RegClass, Op0);
857 }
858 return Register();
859}
860
861Register fastEmit_MipsISD_MFHI_MVT_Untyped_r(MVT RetVT, Register Op0) {
862switch (RetVT.SimpleTy) {
863 case MVT::i32: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i32_r(Op0);
864 case MVT::i64: return fastEmit_MipsISD_MFHI_MVT_Untyped_MVT_i64_r(Op0);
865 default: return Register();
866}
867}
868
869Register fastEmit_MipsISD_MFHI_r(MVT VT, MVT RetVT, Register Op0) {
870 switch (VT.SimpleTy) {
871 case MVT::Untyped: return fastEmit_MipsISD_MFHI_MVT_Untyped_r(RetVT, Op0);
872 default: return Register();
873 }
874}
875
876// FastEmit functions for MipsISD::MFLO.
877
878Register fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(Register Op0) {
879 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
880 return fastEmitInst_r(MachineInstOpcode: Mips::MFLO_DSP_MM, RC: &Mips::GPR32RegClass, Op0);
881 }
882 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
883 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFLO_MM, RC: &Mips::GPR32RegClass, Op0);
884 }
885 if ((Subtarget->hasDSP())) {
886 return fastEmitInst_r(MachineInstOpcode: Mips::MFLO_DSP, RC: &Mips::GPR32RegClass, Op0);
887 }
888 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
889 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFLO, RC: &Mips::GPR32RegClass, Op0);
890 }
891 return Register();
892}
893
894Register fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(Register Op0) {
895 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
896 return fastEmitInst_r(MachineInstOpcode: Mips::PseudoMFLO64, RC: &Mips::GPR64RegClass, Op0);
897 }
898 return Register();
899}
900
901Register fastEmit_MipsISD_MFLO_MVT_Untyped_r(MVT RetVT, Register Op0) {
902switch (RetVT.SimpleTy) {
903 case MVT::i32: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i32_r(Op0);
904 case MVT::i64: return fastEmit_MipsISD_MFLO_MVT_Untyped_MVT_i64_r(Op0);
905 default: return Register();
906}
907}
908
909Register fastEmit_MipsISD_MFLO_r(MVT VT, MVT RetVT, Register Op0) {
910 switch (VT.SimpleTy) {
911 case MVT::Untyped: return fastEmit_MipsISD_MFLO_MVT_Untyped_r(RetVT, Op0);
912 default: return Register();
913 }
914}
915
916// FastEmit functions for MipsISD::MTC1_D64.
917
918Register fastEmit_MipsISD_MTC1_D64_MVT_i32_r(MVT RetVT, Register Op0) {
919 if (RetVT.SimpleTy != MVT::f64)
920 return Register();
921 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
922 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_D64_MM, RC: &Mips::FGR64RegClass, Op0);
923 }
924 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
925 return fastEmitInst_r(MachineInstOpcode: Mips::MTC1_D64, RC: &Mips::FGR64RegClass, Op0);
926 }
927 return Register();
928}
929
930Register fastEmit_MipsISD_MTC1_D64_r(MVT VT, MVT RetVT, Register Op0) {
931 switch (VT.SimpleTy) {
932 case MVT::i32: return fastEmit_MipsISD_MTC1_D64_MVT_i32_r(RetVT, Op0);
933 default: return Register();
934 }
935}
936
937// FastEmit functions for MipsISD::TruncIntFP.
938
939Register fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(Register Op0) {
940 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
941 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_S_MMR6, RC: &Mips::FGR32RegClass, Op0);
942 }
943 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
944 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_S_MM, RC: &Mips::FGR32RegClass, Op0);
945 }
946 if ((Subtarget->hasStandardEncoding())) {
947 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_S, RC: &Mips::FGR32RegClass, Op0);
948 }
949 if ((Subtarget->isR5900())) {
950 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_W_S, RC: &Mips::FGR32RegClass, Op0);
951 }
952 return Register();
953}
954
955Register fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(Register Op0) {
956 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
957 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_L_S, RC: &Mips::FGR64RegClass, Op0);
958 }
959 return Register();
960}
961
962Register fastEmit_MipsISD_TruncIntFP_MVT_f32_r(MVT RetVT, Register Op0) {
963switch (RetVT.SimpleTy) {
964 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f32_r(Op0);
965 case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f32_MVT_f64_r(Op0);
966 default: return Register();
967}
968}
969
970Register fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(Register Op0) {
971 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
972 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_D_MMR6, RC: &Mips::FGR32RegClass, Op0);
973 }
974 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->hasMips32r6())) {
975 return fastEmitInst_r(MachineInstOpcode: Mips::CVT_W_D64_MM, RC: &Mips::FGR32RegClass, Op0);
976 }
977 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->hasMips32r6())) {
978 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_MM, RC: &Mips::FGR32RegClass, Op0);
979 }
980 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
981 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_D64, RC: &Mips::FGR32RegClass, Op0);
982 }
983 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
984 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_W_D32, RC: &Mips::FGR32RegClass, Op0);
985 }
986 return Register();
987}
988
989Register fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(Register Op0) {
990 if ((Subtarget->hasMips2()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat())) {
991 return fastEmitInst_r(MachineInstOpcode: Mips::TRUNC_L_D64, RC: &Mips::FGR64RegClass, Op0);
992 }
993 return Register();
994}
995
996Register fastEmit_MipsISD_TruncIntFP_MVT_f64_r(MVT RetVT, Register Op0) {
997switch (RetVT.SimpleTy) {
998 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f32_r(Op0);
999 case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_MVT_f64_r(Op0);
1000 default: return Register();
1001}
1002}
1003
1004Register fastEmit_MipsISD_TruncIntFP_r(MVT VT, MVT RetVT, Register Op0) {
1005 switch (VT.SimpleTy) {
1006 case MVT::f32: return fastEmit_MipsISD_TruncIntFP_MVT_f32_r(RetVT, Op0);
1007 case MVT::f64: return fastEmit_MipsISD_TruncIntFP_MVT_f64_r(RetVT, Op0);
1008 default: return Register();
1009 }
1010}
1011
1012// FastEmit functions for MipsISD::VALL_NONZERO.
1013
1014Register fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(MVT RetVT, Register Op0) {
1015 if (RetVT.SimpleTy != MVT::i32)
1016 return Register();
1017 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_B_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1018}
1019
1020Register fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(MVT RetVT, Register Op0) {
1021 if (RetVT.SimpleTy != MVT::i32)
1022 return Register();
1023 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_H_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1024}
1025
1026Register fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(MVT RetVT, Register Op0) {
1027 if (RetVT.SimpleTy != MVT::i32)
1028 return Register();
1029 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_W_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1030}
1031
1032Register fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(MVT RetVT, Register Op0) {
1033 if (RetVT.SimpleTy != MVT::i32)
1034 return Register();
1035 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_D_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1036}
1037
1038Register fastEmit_MipsISD_VALL_NONZERO_r(MVT VT, MVT RetVT, Register Op0) {
1039 switch (VT.SimpleTy) {
1040 case MVT::v16i8: return fastEmit_MipsISD_VALL_NONZERO_MVT_v16i8_r(RetVT, Op0);
1041 case MVT::v8i16: return fastEmit_MipsISD_VALL_NONZERO_MVT_v8i16_r(RetVT, Op0);
1042 case MVT::v4i32: return fastEmit_MipsISD_VALL_NONZERO_MVT_v4i32_r(RetVT, Op0);
1043 case MVT::v2i64: return fastEmit_MipsISD_VALL_NONZERO_MVT_v2i64_r(RetVT, Op0);
1044 default: return Register();
1045 }
1046}
1047
1048// FastEmit functions for MipsISD::VALL_ZERO.
1049
1050Register fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(MVT RetVT, Register Op0) {
1051 if (RetVT.SimpleTy != MVT::i32)
1052 return Register();
1053 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_B_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1054}
1055
1056Register fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(MVT RetVT, Register Op0) {
1057 if (RetVT.SimpleTy != MVT::i32)
1058 return Register();
1059 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_H_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1060}
1061
1062Register fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(MVT RetVT, Register Op0) {
1063 if (RetVT.SimpleTy != MVT::i32)
1064 return Register();
1065 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_W_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1066}
1067
1068Register fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(MVT RetVT, Register Op0) {
1069 if (RetVT.SimpleTy != MVT::i32)
1070 return Register();
1071 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_D_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1072}
1073
1074Register fastEmit_MipsISD_VALL_ZERO_r(MVT VT, MVT RetVT, Register Op0) {
1075 switch (VT.SimpleTy) {
1076 case MVT::v16i8: return fastEmit_MipsISD_VALL_ZERO_MVT_v16i8_r(RetVT, Op0);
1077 case MVT::v8i16: return fastEmit_MipsISD_VALL_ZERO_MVT_v8i16_r(RetVT, Op0);
1078 case MVT::v4i32: return fastEmit_MipsISD_VALL_ZERO_MVT_v4i32_r(RetVT, Op0);
1079 case MVT::v2i64: return fastEmit_MipsISD_VALL_ZERO_MVT_v2i64_r(RetVT, Op0);
1080 default: return Register();
1081 }
1082}
1083
1084// FastEmit functions for MipsISD::VANY_NONZERO.
1085
1086Register fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(MVT RetVT, Register Op0) {
1087 if (RetVT.SimpleTy != MVT::i32)
1088 return Register();
1089 return fastEmitInst_r(MachineInstOpcode: Mips::SNZ_V_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1090}
1091
1092Register fastEmit_MipsISD_VANY_NONZERO_r(MVT VT, MVT RetVT, Register Op0) {
1093 switch (VT.SimpleTy) {
1094 case MVT::v16i8: return fastEmit_MipsISD_VANY_NONZERO_MVT_v16i8_r(RetVT, Op0);
1095 default: return Register();
1096 }
1097}
1098
1099// FastEmit functions for MipsISD::VANY_ZERO.
1100
1101Register fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(MVT RetVT, Register Op0) {
1102 if (RetVT.SimpleTy != MVT::i32)
1103 return Register();
1104 return fastEmitInst_r(MachineInstOpcode: Mips::SZ_V_PSEUDO, RC: &Mips::GPR32RegClass, Op0);
1105}
1106
1107Register fastEmit_MipsISD_VANY_ZERO_r(MVT VT, MVT RetVT, Register Op0) {
1108 switch (VT.SimpleTy) {
1109 case MVT::v16i8: return fastEmit_MipsISD_VANY_ZERO_MVT_v16i8_r(RetVT, Op0);
1110 default: return Register();
1111 }
1112}
1113
1114// Top-level FastEmit function.
1115
1116Register fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, Register Op0) override {
1117 switch (Opcode) {
1118 case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0);
1119 case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0);
1120 case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0);
1121 case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0);
1122 case ISD::FEXP2: return fastEmit_ISD_FEXP2_r(VT, RetVT, Op0);
1123 case ISD::FLOG2: return fastEmit_ISD_FLOG2_r(VT, RetVT, Op0);
1124 case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0);
1125 case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0);
1126 case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0);
1127 case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0);
1128 case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0);
1129 case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0);
1130 case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0);
1131 case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0);
1132 case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0);
1133 case ISD::STRICT_FP_EXTEND: return fastEmit_ISD_STRICT_FP_EXTEND_r(VT, RetVT, Op0);
1134 case ISD::STRICT_FP_ROUND: return fastEmit_ISD_STRICT_FP_ROUND_r(VT, RetVT, Op0);
1135 case ISD::STRICT_FSQRT: return fastEmit_ISD_STRICT_FSQRT_r(VT, RetVT, Op0);
1136 case ISD::STRICT_SINT_TO_FP: return fastEmit_ISD_STRICT_SINT_TO_FP_r(VT, RetVT, Op0);
1137 case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0);
1138 case MipsISD::MFHI: return fastEmit_MipsISD_MFHI_r(VT, RetVT, Op0);
1139 case MipsISD::MFLO: return fastEmit_MipsISD_MFLO_r(VT, RetVT, Op0);
1140 case MipsISD::MTC1_D64: return fastEmit_MipsISD_MTC1_D64_r(VT, RetVT, Op0);
1141 case MipsISD::TruncIntFP: return fastEmit_MipsISD_TruncIntFP_r(VT, RetVT, Op0);
1142 case MipsISD::VALL_NONZERO: return fastEmit_MipsISD_VALL_NONZERO_r(VT, RetVT, Op0);
1143 case MipsISD::VALL_ZERO: return fastEmit_MipsISD_VALL_ZERO_r(VT, RetVT, Op0);
1144 case MipsISD::VANY_NONZERO: return fastEmit_MipsISD_VANY_NONZERO_r(VT, RetVT, Op0);
1145 case MipsISD::VANY_ZERO: return fastEmit_MipsISD_VANY_ZERO_r(VT, RetVT, Op0);
1146 default: return Register();
1147 }
1148}
1149
1150// FastEmit functions for ISD::ADD.
1151
1152Register fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1153 if (RetVT.SimpleTy != MVT::i32)
1154 return Register();
1155 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1156 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDU16_MMR6, RC: &Mips::GPRMM16RegClass, Op0, Op1);
1157 }
1158 if ((Subtarget->inMips16Mode())) {
1159 return fastEmitInst_rr(MachineInstOpcode: Mips::AdduRxRyRz16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
1160 }
1161 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1162 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDu_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
1163 }
1164 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1165 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDu, RC: &Mips::GPR32RegClass, Op0, Op1);
1166 }
1167 return Register();
1168}
1169
1170Register fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1171 if (RetVT.SimpleTy != MVT::i64)
1172 return Register();
1173 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1174 return fastEmitInst_rr(MachineInstOpcode: Mips::DADDu, RC: &Mips::GPR64RegClass, Op0, Op1);
1175 }
1176 return Register();
1177}
1178
1179Register fastEmit_ISD_ADD_MVT_v4i8_rr(MVT RetVT, Register Op0, Register Op1) {
1180 if (RetVT.SimpleTy != MVT::v4i8)
1181 return Register();
1182 if ((Subtarget->hasDSP())) {
1183 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDU_QB, RC: &Mips::DSPRRegClass, Op0, Op1);
1184 }
1185 return Register();
1186}
1187
1188Register fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1189 if (RetVT.SimpleTy != MVT::v16i8)
1190 return Register();
1191 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1192 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
1193 }
1194 return Register();
1195}
1196
1197Register fastEmit_ISD_ADD_MVT_v2i16_rr(MVT RetVT, Register Op0, Register Op1) {
1198 if (RetVT.SimpleTy != MVT::v2i16)
1199 return Register();
1200 if ((Subtarget->hasDSP())) {
1201 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDQ_PH, RC: &Mips::DSPRRegClass, Op0, Op1);
1202 }
1203 return Register();
1204}
1205
1206Register fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1207 if (RetVT.SimpleTy != MVT::v8i16)
1208 return Register();
1209 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1210 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
1211 }
1212 return Register();
1213}
1214
1215Register fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
1216 if (RetVT.SimpleTy != MVT::v4i32)
1217 return Register();
1218 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1219 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1220 }
1221 return Register();
1222}
1223
1224Register fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
1225 if (RetVT.SimpleTy != MVT::v2i64)
1226 return Register();
1227 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1228 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1229 }
1230 return Register();
1231}
1232
1233Register fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1234 switch (VT.SimpleTy) {
1235 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op1);
1236 case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op1);
1237 case MVT::v4i8: return fastEmit_ISD_ADD_MVT_v4i8_rr(RetVT, Op0, Op1);
1238 case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op1);
1239 case MVT::v2i16: return fastEmit_ISD_ADD_MVT_v2i16_rr(RetVT, Op0, Op1);
1240 case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op1);
1241 case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op1);
1242 case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op1);
1243 default: return Register();
1244 }
1245}
1246
1247// FastEmit functions for ISD::ADDC.
1248
1249Register fastEmit_ISD_ADDC_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1250 if (RetVT.SimpleTy != MVT::i32)
1251 return Register();
1252 if ((Subtarget->hasDSP())) {
1253 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDSC, RC: &Mips::GPR32RegClass, Op0, Op1);
1254 }
1255 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP())) {
1256 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDu, RC: &Mips::GPR32RegClass, Op0, Op1);
1257 }
1258 return Register();
1259}
1260
1261Register fastEmit_ISD_ADDC_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1262 if (RetVT.SimpleTy != MVT::i64)
1263 return Register();
1264 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->hasDSP()) && (!Subtarget->inMicroMipsMode())) {
1265 return fastEmitInst_rr(MachineInstOpcode: Mips::DADDu, RC: &Mips::GPR64RegClass, Op0, Op1);
1266 }
1267 return Register();
1268}
1269
1270Register fastEmit_ISD_ADDC_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1271 switch (VT.SimpleTy) {
1272 case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_rr(RetVT, Op0, Op1);
1273 case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_rr(RetVT, Op0, Op1);
1274 default: return Register();
1275 }
1276}
1277
1278// FastEmit functions for ISD::ADDE.
1279
1280Register fastEmit_ISD_ADDE_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1281 if (RetVT.SimpleTy != MVT::i32)
1282 return Register();
1283 if ((Subtarget->hasDSP())) {
1284 return fastEmitInst_rr(MachineInstOpcode: Mips::ADDWC, RC: &Mips::GPR32RegClass, Op0, Op1);
1285 }
1286 return Register();
1287}
1288
1289Register fastEmit_ISD_ADDE_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1290 switch (VT.SimpleTy) {
1291 case MVT::i32: return fastEmit_ISD_ADDE_MVT_i32_rr(RetVT, Op0, Op1);
1292 default: return Register();
1293 }
1294}
1295
1296// FastEmit functions for ISD::AND.
1297
1298Register fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1299 if (RetVT.SimpleTy != MVT::i32)
1300 return Register();
1301 if ((Subtarget->inMips16Mode())) {
1302 return fastEmitInst_rr(MachineInstOpcode: Mips::AndRxRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
1303 }
1304 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1305 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
1306 }
1307 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1308 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
1309 }
1310 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1311 return fastEmitInst_rr(MachineInstOpcode: Mips::AND, RC: &Mips::GPR32RegClass, Op0, Op1);
1312 }
1313 return Register();
1314}
1315
1316Register fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1317 if (RetVT.SimpleTy != MVT::i64)
1318 return Register();
1319 if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
1320 return fastEmitInst_rr(MachineInstOpcode: Mips::AND64, RC: &Mips::GPR64RegClass, Op0, Op1);
1321 }
1322 return Register();
1323}
1324
1325Register fastEmit_ISD_AND_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1326 if (RetVT.SimpleTy != MVT::v16i8)
1327 return Register();
1328 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1329 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
1330 }
1331 return Register();
1332}
1333
1334Register fastEmit_ISD_AND_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1335 if (RetVT.SimpleTy != MVT::v8i16)
1336 return Register();
1337 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1338 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
1339 }
1340 return Register();
1341}
1342
1343Register fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
1344 if (RetVT.SimpleTy != MVT::v4i32)
1345 return Register();
1346 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1347 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
1348 }
1349 return Register();
1350}
1351
1352Register fastEmit_ISD_AND_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
1353 if (RetVT.SimpleTy != MVT::v2i64)
1354 return Register();
1355 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1356 return fastEmitInst_rr(MachineInstOpcode: Mips::AND_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
1357 }
1358 return Register();
1359}
1360
1361Register fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1362 switch (VT.SimpleTy) {
1363 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op1);
1364 case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op1);
1365 case MVT::v16i8: return fastEmit_ISD_AND_MVT_v16i8_rr(RetVT, Op0, Op1);
1366 case MVT::v8i16: return fastEmit_ISD_AND_MVT_v8i16_rr(RetVT, Op0, Op1);
1367 case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op1);
1368 case MVT::v2i64: return fastEmit_ISD_AND_MVT_v2i64_rr(RetVT, Op0, Op1);
1369 default: return Register();
1370 }
1371}
1372
1373// FastEmit functions for ISD::FADD.
1374
1375Register fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1376 if (RetVT.SimpleTy != MVT::f32)
1377 return Register();
1378 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1379 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1380 }
1381 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1382 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1383 }
1384 return Register();
1385}
1386
1387Register fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1388 if (RetVT.SimpleTy != MVT::f64)
1389 return Register();
1390 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
1391 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1392 }
1393 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1394 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1395 }
1396 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1397 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1398 }
1399 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1400 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1401 }
1402 return Register();
1403}
1404
1405Register fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1406 if (RetVT.SimpleTy != MVT::v4f32)
1407 return Register();
1408 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1409 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1410 }
1411 return Register();
1412}
1413
1414Register fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1415 if (RetVT.SimpleTy != MVT::v2f64)
1416 return Register();
1417 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1418 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1419 }
1420 return Register();
1421}
1422
1423Register fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1424 switch (VT.SimpleTy) {
1425 case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op1);
1426 case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op1);
1427 case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op1);
1428 case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op1);
1429 default: return Register();
1430 }
1431}
1432
1433// FastEmit functions for ISD::FDIV.
1434
1435Register fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1436 if (RetVT.SimpleTy != MVT::f32)
1437 return Register();
1438 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1439 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1440 }
1441 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1442 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1443 }
1444 return Register();
1445}
1446
1447Register fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1448 if (RetVT.SimpleTy != MVT::f64)
1449 return Register();
1450 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
1451 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1452 }
1453 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1454 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1455 }
1456 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1457 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1458 }
1459 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1460 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1461 }
1462 return Register();
1463}
1464
1465Register fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1466 if (RetVT.SimpleTy != MVT::v4f32)
1467 return Register();
1468 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1469 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1470 }
1471 return Register();
1472}
1473
1474Register fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1475 if (RetVT.SimpleTy != MVT::v2f64)
1476 return Register();
1477 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1478 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1479 }
1480 return Register();
1481}
1482
1483Register fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1484 switch (VT.SimpleTy) {
1485 case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op1);
1486 case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op1);
1487 case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op1);
1488 case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op1);
1489 default: return Register();
1490 }
1491}
1492
1493// FastEmit functions for ISD::FMAXNUM.
1494
1495Register fastEmit_ISD_FMAXNUM_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1496 if (RetVT.SimpleTy != MVT::f32)
1497 return Register();
1498 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1499 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1500 }
1501 return Register();
1502}
1503
1504Register fastEmit_ISD_FMAXNUM_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1505 if (RetVT.SimpleTy != MVT::f64)
1506 return Register();
1507 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1508 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_D, RC: &Mips::FGR64RegClass, Op0, Op1);
1509 }
1510 return Register();
1511}
1512
1513Register fastEmit_ISD_FMAXNUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1514 switch (VT.SimpleTy) {
1515 case MVT::f32: return fastEmit_ISD_FMAXNUM_MVT_f32_rr(RetVT, Op0, Op1);
1516 case MVT::f64: return fastEmit_ISD_FMAXNUM_MVT_f64_rr(RetVT, Op0, Op1);
1517 default: return Register();
1518 }
1519}
1520
1521// FastEmit functions for ISD::FMAXNUM_IEEE.
1522
1523Register fastEmit_ISD_FMAXNUM_IEEE_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1524 if (RetVT.SimpleTy != MVT::f32)
1525 return Register();
1526 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1527 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1528 }
1529 return Register();
1530}
1531
1532Register fastEmit_ISD_FMAXNUM_IEEE_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1533 if (RetVT.SimpleTy != MVT::f64)
1534 return Register();
1535 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1536 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_D, RC: &Mips::FGR64RegClass, Op0, Op1);
1537 }
1538 return Register();
1539}
1540
1541Register fastEmit_ISD_FMAXNUM_IEEE_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1542 switch (VT.SimpleTy) {
1543 case MVT::f32: return fastEmit_ISD_FMAXNUM_IEEE_MVT_f32_rr(RetVT, Op0, Op1);
1544 case MVT::f64: return fastEmit_ISD_FMAXNUM_IEEE_MVT_f64_rr(RetVT, Op0, Op1);
1545 default: return Register();
1546 }
1547}
1548
1549// FastEmit functions for ISD::FMINNUM.
1550
1551Register fastEmit_ISD_FMINNUM_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1552 if (RetVT.SimpleTy != MVT::f32)
1553 return Register();
1554 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1555 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1556 }
1557 return Register();
1558}
1559
1560Register fastEmit_ISD_FMINNUM_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1561 if (RetVT.SimpleTy != MVT::f64)
1562 return Register();
1563 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1564 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_D, RC: &Mips::FGR64RegClass, Op0, Op1);
1565 }
1566 return Register();
1567}
1568
1569Register fastEmit_ISD_FMINNUM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1570 switch (VT.SimpleTy) {
1571 case MVT::f32: return fastEmit_ISD_FMINNUM_MVT_f32_rr(RetVT, Op0, Op1);
1572 case MVT::f64: return fastEmit_ISD_FMINNUM_MVT_f64_rr(RetVT, Op0, Op1);
1573 default: return Register();
1574 }
1575}
1576
1577// FastEmit functions for ISD::FMINNUM_IEEE.
1578
1579Register fastEmit_ISD_FMINNUM_IEEE_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1580 if (RetVT.SimpleTy != MVT::f32)
1581 return Register();
1582 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1583 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1584 }
1585 return Register();
1586}
1587
1588Register fastEmit_ISD_FMINNUM_IEEE_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1589 if (RetVT.SimpleTy != MVT::f64)
1590 return Register();
1591 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1592 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_D, RC: &Mips::FGR64RegClass, Op0, Op1);
1593 }
1594 return Register();
1595}
1596
1597Register fastEmit_ISD_FMINNUM_IEEE_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1598 switch (VT.SimpleTy) {
1599 case MVT::f32: return fastEmit_ISD_FMINNUM_IEEE_MVT_f32_rr(RetVT, Op0, Op1);
1600 case MVT::f64: return fastEmit_ISD_FMINNUM_IEEE_MVT_f64_rr(RetVT, Op0, Op1);
1601 default: return Register();
1602 }
1603}
1604
1605// FastEmit functions for ISD::FMUL.
1606
1607Register fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1608 if (RetVT.SimpleTy != MVT::f32)
1609 return Register();
1610 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1611 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1612 }
1613 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1614 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1615 }
1616 return Register();
1617}
1618
1619Register fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1620 if (RetVT.SimpleTy != MVT::f64)
1621 return Register();
1622 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
1623 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1624 }
1625 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1626 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1627 }
1628 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1629 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1630 }
1631 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1632 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1633 }
1634 return Register();
1635}
1636
1637Register fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1638 if (RetVT.SimpleTy != MVT::v4f32)
1639 return Register();
1640 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1641 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1642 }
1643 return Register();
1644}
1645
1646Register fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1647 if (RetVT.SimpleTy != MVT::v2f64)
1648 return Register();
1649 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1650 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1651 }
1652 return Register();
1653}
1654
1655Register fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1656 switch (VT.SimpleTy) {
1657 case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op1);
1658 case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op1);
1659 case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op1);
1660 case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op1);
1661 default: return Register();
1662 }
1663}
1664
1665// FastEmit functions for ISD::FSUB.
1666
1667Register fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
1668 if (RetVT.SimpleTy != MVT::f32)
1669 return Register();
1670 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->useSoftFloat())) {
1671 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_S_MM, RC: &Mips::FGR32RegClass, Op0, Op1);
1672 }
1673 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1674 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_S, RC: &Mips::FGR32RegClass, Op0, Op1);
1675 }
1676 return Register();
1677}
1678
1679Register fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
1680 if (RetVT.SimpleTy != MVT::f64)
1681 return Register();
1682 if ((Subtarget->inMicroMipsMode()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat())) {
1683 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D64_MM, RC: &Mips::FGR64RegClass, Op0, Op1);
1684 }
1685 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit())) {
1686 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D32_MM, RC: &Mips::AFGR64RegClass, Op0, Op1);
1687 }
1688 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
1689 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
1690 }
1691 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
1692 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
1693 }
1694 return Register();
1695}
1696
1697Register fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, Register Op0, Register Op1) {
1698 if (RetVT.SimpleTy != MVT::v4f32)
1699 return Register();
1700 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1701 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1702 }
1703 return Register();
1704}
1705
1706Register fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, Register Op0, Register Op1) {
1707 if (RetVT.SimpleTy != MVT::v2f64)
1708 return Register();
1709 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1710 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1711 }
1712 return Register();
1713}
1714
1715Register fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1716 switch (VT.SimpleTy) {
1717 case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op1);
1718 case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op1);
1719 case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op1);
1720 case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op1);
1721 default: return Register();
1722 }
1723}
1724
1725// FastEmit functions for ISD::MUL.
1726
1727Register fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1728 if (RetVT.SimpleTy != MVT::i32)
1729 return Register();
1730 if ((Subtarget->inMips16Mode())) {
1731 return fastEmitInst_rr(MachineInstOpcode: Mips::MultRxRyRz16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
1732 }
1733 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1734 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
1735 }
1736 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1737 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
1738 }
1739 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1740 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_R6, RC: &Mips::GPR32RegClass, Op0, Op1);
1741 }
1742 if ((Subtarget->hasMips32()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
1743 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL, RC: &Mips::GPR32RegClass, Op0, Op1);
1744 }
1745 return Register();
1746}
1747
1748Register fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1749 if (RetVT.SimpleTy != MVT::i64)
1750 return Register();
1751 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1752 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUL_R6, RC: &Mips::GPR64RegClass, Op0, Op1);
1753 }
1754 if ((Subtarget->hasCnMips())) {
1755 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUL, RC: &Mips::GPR64RegClass, Op0, Op1);
1756 }
1757 return Register();
1758}
1759
1760Register fastEmit_ISD_MUL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1761 if (RetVT.SimpleTy != MVT::v16i8)
1762 return Register();
1763 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1764 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
1765 }
1766 return Register();
1767}
1768
1769Register fastEmit_ISD_MUL_MVT_v2i16_rr(MVT RetVT, Register Op0, Register Op1) {
1770 if (RetVT.SimpleTy != MVT::v2i16)
1771 return Register();
1772 if ((Subtarget->hasDSPR2())) {
1773 return fastEmitInst_rr(MachineInstOpcode: Mips::MUL_PH, RC: &Mips::DSPRRegClass, Op0, Op1);
1774 }
1775 return Register();
1776}
1777
1778Register fastEmit_ISD_MUL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1779 if (RetVT.SimpleTy != MVT::v8i16)
1780 return Register();
1781 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1782 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
1783 }
1784 return Register();
1785}
1786
1787Register fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
1788 if (RetVT.SimpleTy != MVT::v4i32)
1789 return Register();
1790 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1791 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
1792 }
1793 return Register();
1794}
1795
1796Register fastEmit_ISD_MUL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
1797 if (RetVT.SimpleTy != MVT::v2i64)
1798 return Register();
1799 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1800 return fastEmitInst_rr(MachineInstOpcode: Mips::MULV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
1801 }
1802 return Register();
1803}
1804
1805Register fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1806 switch (VT.SimpleTy) {
1807 case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op1);
1808 case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op1);
1809 case MVT::v16i8: return fastEmit_ISD_MUL_MVT_v16i8_rr(RetVT, Op0, Op1);
1810 case MVT::v2i16: return fastEmit_ISD_MUL_MVT_v2i16_rr(RetVT, Op0, Op1);
1811 case MVT::v8i16: return fastEmit_ISD_MUL_MVT_v8i16_rr(RetVT, Op0, Op1);
1812 case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op1);
1813 case MVT::v2i64: return fastEmit_ISD_MUL_MVT_v2i64_rr(RetVT, Op0, Op1);
1814 default: return Register();
1815 }
1816}
1817
1818// FastEmit functions for ISD::MULHS.
1819
1820Register fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1821 if (RetVT.SimpleTy != MVT::i32)
1822 return Register();
1823 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1824 return fastEmitInst_rr(MachineInstOpcode: Mips::MUH_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
1825 }
1826 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1827 return fastEmitInst_rr(MachineInstOpcode: Mips::MUH, RC: &Mips::GPR32RegClass, Op0, Op1);
1828 }
1829 return Register();
1830}
1831
1832Register fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1833 if (RetVT.SimpleTy != MVT::i64)
1834 return Register();
1835 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1836 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUH, RC: &Mips::GPR64RegClass, Op0, Op1);
1837 }
1838 return Register();
1839}
1840
1841Register fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1842 switch (VT.SimpleTy) {
1843 case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op1);
1844 case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op1);
1845 default: return Register();
1846 }
1847}
1848
1849// FastEmit functions for ISD::MULHU.
1850
1851Register fastEmit_ISD_MULHU_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1852 if (RetVT.SimpleTy != MVT::i32)
1853 return Register();
1854 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1855 return fastEmitInst_rr(MachineInstOpcode: Mips::MUHU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
1856 }
1857 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1858 return fastEmitInst_rr(MachineInstOpcode: Mips::MUHU, RC: &Mips::GPR32RegClass, Op0, Op1);
1859 }
1860 return Register();
1861}
1862
1863Register fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1864 if (RetVT.SimpleTy != MVT::i64)
1865 return Register();
1866 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1867 return fastEmitInst_rr(MachineInstOpcode: Mips::DMUHU, RC: &Mips::GPR64RegClass, Op0, Op1);
1868 }
1869 return Register();
1870}
1871
1872Register fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1873 switch (VT.SimpleTy) {
1874 case MVT::i32: return fastEmit_ISD_MULHU_MVT_i32_rr(RetVT, Op0, Op1);
1875 case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op1);
1876 default: return Register();
1877 }
1878}
1879
1880// FastEmit functions for ISD::OR.
1881
1882Register fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1883 if (RetVT.SimpleTy != MVT::i32)
1884 return Register();
1885 if ((Subtarget->inMips16Mode())) {
1886 return fastEmitInst_rr(MachineInstOpcode: Mips::OrRxRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
1887 }
1888 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1889 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
1890 }
1891 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
1892 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
1893 }
1894 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1895 return fastEmitInst_rr(MachineInstOpcode: Mips::OR, RC: &Mips::GPR32RegClass, Op0, Op1);
1896 }
1897 return Register();
1898}
1899
1900Register fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1901 if (RetVT.SimpleTy != MVT::i64)
1902 return Register();
1903 if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
1904 return fastEmitInst_rr(MachineInstOpcode: Mips::OR64, RC: &Mips::GPR64RegClass, Op0, Op1);
1905 }
1906 return Register();
1907}
1908
1909Register fastEmit_ISD_OR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
1910 if (RetVT.SimpleTy != MVT::v16i8)
1911 return Register();
1912 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1913 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
1914 }
1915 return Register();
1916}
1917
1918Register fastEmit_ISD_OR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
1919 if (RetVT.SimpleTy != MVT::v8i16)
1920 return Register();
1921 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1922 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
1923 }
1924 return Register();
1925}
1926
1927Register fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
1928 if (RetVT.SimpleTy != MVT::v4i32)
1929 return Register();
1930 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1931 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
1932 }
1933 return Register();
1934}
1935
1936Register fastEmit_ISD_OR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
1937 if (RetVT.SimpleTy != MVT::v2i64)
1938 return Register();
1939 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
1940 return fastEmitInst_rr(MachineInstOpcode: Mips::OR_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
1941 }
1942 return Register();
1943}
1944
1945Register fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1946 switch (VT.SimpleTy) {
1947 case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op1);
1948 case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op1);
1949 case MVT::v16i8: return fastEmit_ISD_OR_MVT_v16i8_rr(RetVT, Op0, Op1);
1950 case MVT::v8i16: return fastEmit_ISD_OR_MVT_v8i16_rr(RetVT, Op0, Op1);
1951 case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op1);
1952 case MVT::v2i64: return fastEmit_ISD_OR_MVT_v2i64_rr(RetVT, Op0, Op1);
1953 default: return Register();
1954 }
1955}
1956
1957// FastEmit functions for ISD::ROTR.
1958
1959Register fastEmit_ISD_ROTR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1960 if (RetVT.SimpleTy != MVT::i32)
1961 return Register();
1962 if ((Subtarget->inMicroMipsMode())) {
1963 return fastEmitInst_rr(MachineInstOpcode: Mips::ROTRV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
1964 }
1965 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1966 return fastEmitInst_rr(MachineInstOpcode: Mips::ROTRV, RC: &Mips::GPR32RegClass, Op0, Op1);
1967 }
1968 return Register();
1969}
1970
1971Register fastEmit_ISD_ROTR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
1972 switch (VT.SimpleTy) {
1973 case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_rr(RetVT, Op0, Op1);
1974 default: return Register();
1975 }
1976}
1977
1978// FastEmit functions for ISD::SDIV.
1979
1980Register fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
1981 if (RetVT.SimpleTy != MVT::i32)
1982 return Register();
1983 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
1984 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
1985 }
1986 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1987 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV, RC: &Mips::GPR32RegClass, Op0, Op1);
1988 }
1989 return Register();
1990}
1991
1992Register fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
1993 if (RetVT.SimpleTy != MVT::i64)
1994 return Register();
1995 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
1996 return fastEmitInst_rr(MachineInstOpcode: Mips::DDIV, RC: &Mips::GPR64RegClass, Op0, Op1);
1997 }
1998 return Register();
1999}
2000
2001Register fastEmit_ISD_SDIV_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2002 if (RetVT.SimpleTy != MVT::v16i8)
2003 return Register();
2004 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2005 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2006 }
2007 return Register();
2008}
2009
2010Register fastEmit_ISD_SDIV_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2011 if (RetVT.SimpleTy != MVT::v8i16)
2012 return Register();
2013 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2014 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2015 }
2016 return Register();
2017}
2018
2019Register fastEmit_ISD_SDIV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2020 if (RetVT.SimpleTy != MVT::v4i32)
2021 return Register();
2022 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2023 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2024 }
2025 return Register();
2026}
2027
2028Register fastEmit_ISD_SDIV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2029 if (RetVT.SimpleTy != MVT::v2i64)
2030 return Register();
2031 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2032 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2033 }
2034 return Register();
2035}
2036
2037Register fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2038 switch (VT.SimpleTy) {
2039 case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op1);
2040 case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op1);
2041 case MVT::v16i8: return fastEmit_ISD_SDIV_MVT_v16i8_rr(RetVT, Op0, Op1);
2042 case MVT::v8i16: return fastEmit_ISD_SDIV_MVT_v8i16_rr(RetVT, Op0, Op1);
2043 case MVT::v4i32: return fastEmit_ISD_SDIV_MVT_v4i32_rr(RetVT, Op0, Op1);
2044 case MVT::v2i64: return fastEmit_ISD_SDIV_MVT_v2i64_rr(RetVT, Op0, Op1);
2045 default: return Register();
2046 }
2047}
2048
2049// FastEmit functions for ISD::SHL.
2050
2051Register fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2052 if (RetVT.SimpleTy != MVT::i32)
2053 return Register();
2054 if ((Subtarget->inMicroMipsMode())) {
2055 return fastEmitInst_rr(MachineInstOpcode: Mips::SLLV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2056 }
2057 if ((Subtarget->inMips16Mode())) {
2058 return fastEmitInst_rr(MachineInstOpcode: Mips::SllvRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2059 }
2060 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2061 return fastEmitInst_rr(MachineInstOpcode: Mips::SLLV, RC: &Mips::GPR32RegClass, Op0, Op1);
2062 }
2063 return Register();
2064}
2065
2066Register fastEmit_ISD_SHL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2067 if (RetVT.SimpleTy != MVT::v16i8)
2068 return Register();
2069 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2070 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2071 }
2072 return Register();
2073}
2074
2075Register fastEmit_ISD_SHL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2076 if (RetVT.SimpleTy != MVT::v8i16)
2077 return Register();
2078 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2079 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2080 }
2081 return Register();
2082}
2083
2084Register fastEmit_ISD_SHL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2085 if (RetVT.SimpleTy != MVT::v4i32)
2086 return Register();
2087 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2088 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2089 }
2090 return Register();
2091}
2092
2093Register fastEmit_ISD_SHL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2094 if (RetVT.SimpleTy != MVT::v2i64)
2095 return Register();
2096 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2097 return fastEmitInst_rr(MachineInstOpcode: Mips::SLL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2098 }
2099 return Register();
2100}
2101
2102Register fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2103 switch (VT.SimpleTy) {
2104 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op1);
2105 case MVT::v16i8: return fastEmit_ISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op1);
2106 case MVT::v8i16: return fastEmit_ISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op1);
2107 case MVT::v4i32: return fastEmit_ISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op1);
2108 case MVT::v2i64: return fastEmit_ISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op1);
2109 default: return Register();
2110 }
2111}
2112
2113// FastEmit functions for ISD::SMAX.
2114
2115Register fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2116 if (RetVT.SimpleTy != MVT::v16i8)
2117 return Register();
2118 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2119 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2120 }
2121 return Register();
2122}
2123
2124Register fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2125 if (RetVT.SimpleTy != MVT::v8i16)
2126 return Register();
2127 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2128 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2129 }
2130 return Register();
2131}
2132
2133Register fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2134 if (RetVT.SimpleTy != MVT::v4i32)
2135 return Register();
2136 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2137 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2138 }
2139 return Register();
2140}
2141
2142Register fastEmit_ISD_SMAX_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2143 if (RetVT.SimpleTy != MVT::v2i64)
2144 return Register();
2145 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2146 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2147 }
2148 return Register();
2149}
2150
2151Register fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2152 switch (VT.SimpleTy) {
2153 case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
2154 case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
2155 case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
2156 case MVT::v2i64: return fastEmit_ISD_SMAX_MVT_v2i64_rr(RetVT, Op0, Op1);
2157 default: return Register();
2158 }
2159}
2160
2161// FastEmit functions for ISD::SMIN.
2162
2163Register fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2164 if (RetVT.SimpleTy != MVT::v16i8)
2165 return Register();
2166 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2167 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2168 }
2169 return Register();
2170}
2171
2172Register fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2173 if (RetVT.SimpleTy != MVT::v8i16)
2174 return Register();
2175 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2176 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2177 }
2178 return Register();
2179}
2180
2181Register fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2182 if (RetVT.SimpleTy != MVT::v4i32)
2183 return Register();
2184 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2185 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2186 }
2187 return Register();
2188}
2189
2190Register fastEmit_ISD_SMIN_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2191 if (RetVT.SimpleTy != MVT::v2i64)
2192 return Register();
2193 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2194 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2195 }
2196 return Register();
2197}
2198
2199Register fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2200 switch (VT.SimpleTy) {
2201 case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
2202 case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
2203 case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
2204 case MVT::v2i64: return fastEmit_ISD_SMIN_MVT_v2i64_rr(RetVT, Op0, Op1);
2205 default: return Register();
2206 }
2207}
2208
2209// FastEmit functions for ISD::SRA.
2210
2211Register fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2212 if (RetVT.SimpleTy != MVT::i32)
2213 return Register();
2214 if ((Subtarget->inMicroMipsMode())) {
2215 return fastEmitInst_rr(MachineInstOpcode: Mips::SRAV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2216 }
2217 if ((Subtarget->inMips16Mode())) {
2218 return fastEmitInst_rr(MachineInstOpcode: Mips::SravRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2219 }
2220 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2221 return fastEmitInst_rr(MachineInstOpcode: Mips::SRAV, RC: &Mips::GPR32RegClass, Op0, Op1);
2222 }
2223 return Register();
2224}
2225
2226Register fastEmit_ISD_SRA_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2227 if (RetVT.SimpleTy != MVT::v16i8)
2228 return Register();
2229 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2230 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2231 }
2232 return Register();
2233}
2234
2235Register fastEmit_ISD_SRA_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2236 if (RetVT.SimpleTy != MVT::v8i16)
2237 return Register();
2238 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2239 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2240 }
2241 return Register();
2242}
2243
2244Register fastEmit_ISD_SRA_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2245 if (RetVT.SimpleTy != MVT::v4i32)
2246 return Register();
2247 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2248 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2249 }
2250 return Register();
2251}
2252
2253Register fastEmit_ISD_SRA_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2254 if (RetVT.SimpleTy != MVT::v2i64)
2255 return Register();
2256 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2257 return fastEmitInst_rr(MachineInstOpcode: Mips::SRA_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2258 }
2259 return Register();
2260}
2261
2262Register fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2263 switch (VT.SimpleTy) {
2264 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op1);
2265 case MVT::v16i8: return fastEmit_ISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op1);
2266 case MVT::v8i16: return fastEmit_ISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op1);
2267 case MVT::v4i32: return fastEmit_ISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op1);
2268 case MVT::v2i64: return fastEmit_ISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op1);
2269 default: return Register();
2270 }
2271}
2272
2273// FastEmit functions for ISD::SREM.
2274
2275Register fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2276 if (RetVT.SimpleTy != MVT::i32)
2277 return Register();
2278 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2279 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2280 }
2281 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2282 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD, RC: &Mips::GPR32RegClass, Op0, Op1);
2283 }
2284 return Register();
2285}
2286
2287Register fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2288 if (RetVT.SimpleTy != MVT::i64)
2289 return Register();
2290 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2291 return fastEmitInst_rr(MachineInstOpcode: Mips::DMOD, RC: &Mips::GPR64RegClass, Op0, Op1);
2292 }
2293 return Register();
2294}
2295
2296Register fastEmit_ISD_SREM_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2297 if (RetVT.SimpleTy != MVT::v16i8)
2298 return Register();
2299 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2300 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2301 }
2302 return Register();
2303}
2304
2305Register fastEmit_ISD_SREM_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2306 if (RetVT.SimpleTy != MVT::v8i16)
2307 return Register();
2308 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2309 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2310 }
2311 return Register();
2312}
2313
2314Register fastEmit_ISD_SREM_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2315 if (RetVT.SimpleTy != MVT::v4i32)
2316 return Register();
2317 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2318 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2319 }
2320 return Register();
2321}
2322
2323Register fastEmit_ISD_SREM_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2324 if (RetVT.SimpleTy != MVT::v2i64)
2325 return Register();
2326 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2327 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_S_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2328 }
2329 return Register();
2330}
2331
2332Register fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2333 switch (VT.SimpleTy) {
2334 case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op1);
2335 case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op1);
2336 case MVT::v16i8: return fastEmit_ISD_SREM_MVT_v16i8_rr(RetVT, Op0, Op1);
2337 case MVT::v8i16: return fastEmit_ISD_SREM_MVT_v8i16_rr(RetVT, Op0, Op1);
2338 case MVT::v4i32: return fastEmit_ISD_SREM_MVT_v4i32_rr(RetVT, Op0, Op1);
2339 case MVT::v2i64: return fastEmit_ISD_SREM_MVT_v2i64_rr(RetVT, Op0, Op1);
2340 default: return Register();
2341 }
2342}
2343
2344// FastEmit functions for ISD::SRL.
2345
2346Register fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2347 if (RetVT.SimpleTy != MVT::i32)
2348 return Register();
2349 if ((Subtarget->inMicroMipsMode())) {
2350 return fastEmitInst_rr(MachineInstOpcode: Mips::SRLV_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2351 }
2352 if ((Subtarget->inMips16Mode())) {
2353 return fastEmitInst_rr(MachineInstOpcode: Mips::SrlvRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2354 }
2355 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2356 return fastEmitInst_rr(MachineInstOpcode: Mips::SRLV, RC: &Mips::GPR32RegClass, Op0, Op1);
2357 }
2358 return Register();
2359}
2360
2361Register fastEmit_ISD_SRL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2362 if (RetVT.SimpleTy != MVT::v16i8)
2363 return Register();
2364 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2365 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2366 }
2367 return Register();
2368}
2369
2370Register fastEmit_ISD_SRL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2371 if (RetVT.SimpleTy != MVT::v8i16)
2372 return Register();
2373 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2374 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2375 }
2376 return Register();
2377}
2378
2379Register fastEmit_ISD_SRL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2380 if (RetVT.SimpleTy != MVT::v4i32)
2381 return Register();
2382 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2383 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2384 }
2385 return Register();
2386}
2387
2388Register fastEmit_ISD_SRL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2389 if (RetVT.SimpleTy != MVT::v2i64)
2390 return Register();
2391 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2392 return fastEmitInst_rr(MachineInstOpcode: Mips::SRL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2393 }
2394 return Register();
2395}
2396
2397Register fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2398 switch (VT.SimpleTy) {
2399 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op1);
2400 case MVT::v16i8: return fastEmit_ISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op1);
2401 case MVT::v8i16: return fastEmit_ISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op1);
2402 case MVT::v4i32: return fastEmit_ISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op1);
2403 case MVT::v2i64: return fastEmit_ISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op1);
2404 default: return Register();
2405 }
2406}
2407
2408// FastEmit functions for ISD::STRICT_FADD.
2409
2410Register fastEmit_ISD_STRICT_FADD_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
2411 if (RetVT.SimpleTy != MVT::f32)
2412 return Register();
2413 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2414 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_S, RC: &Mips::FGR32RegClass, Op0, Op1);
2415 }
2416 return Register();
2417}
2418
2419Register fastEmit_ISD_STRICT_FADD_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
2420 if (RetVT.SimpleTy != MVT::f64)
2421 return Register();
2422 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2423 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
2424 }
2425 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
2426 return fastEmitInst_rr(MachineInstOpcode: Mips::FADD_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
2427 }
2428 return Register();
2429}
2430
2431Register fastEmit_ISD_STRICT_FADD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2432 switch (VT.SimpleTy) {
2433 case MVT::f32: return fastEmit_ISD_STRICT_FADD_MVT_f32_rr(RetVT, Op0, Op1);
2434 case MVT::f64: return fastEmit_ISD_STRICT_FADD_MVT_f64_rr(RetVT, Op0, Op1);
2435 default: return Register();
2436 }
2437}
2438
2439// FastEmit functions for ISD::STRICT_FDIV.
2440
2441Register fastEmit_ISD_STRICT_FDIV_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
2442 if (RetVT.SimpleTy != MVT::f32)
2443 return Register();
2444 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2445 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_S, RC: &Mips::FGR32RegClass, Op0, Op1);
2446 }
2447 return Register();
2448}
2449
2450Register fastEmit_ISD_STRICT_FDIV_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
2451 if (RetVT.SimpleTy != MVT::f64)
2452 return Register();
2453 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2454 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
2455 }
2456 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
2457 return fastEmitInst_rr(MachineInstOpcode: Mips::FDIV_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
2458 }
2459 return Register();
2460}
2461
2462Register fastEmit_ISD_STRICT_FDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2463 switch (VT.SimpleTy) {
2464 case MVT::f32: return fastEmit_ISD_STRICT_FDIV_MVT_f32_rr(RetVT, Op0, Op1);
2465 case MVT::f64: return fastEmit_ISD_STRICT_FDIV_MVT_f64_rr(RetVT, Op0, Op1);
2466 default: return Register();
2467 }
2468}
2469
2470// FastEmit functions for ISD::STRICT_FMUL.
2471
2472Register fastEmit_ISD_STRICT_FMUL_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
2473 if (RetVT.SimpleTy != MVT::f32)
2474 return Register();
2475 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2476 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_S, RC: &Mips::FGR32RegClass, Op0, Op1);
2477 }
2478 return Register();
2479}
2480
2481Register fastEmit_ISD_STRICT_FMUL_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
2482 if (RetVT.SimpleTy != MVT::f64)
2483 return Register();
2484 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2485 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
2486 }
2487 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
2488 return fastEmitInst_rr(MachineInstOpcode: Mips::FMUL_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
2489 }
2490 return Register();
2491}
2492
2493Register fastEmit_ISD_STRICT_FMUL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2494 switch (VT.SimpleTy) {
2495 case MVT::f32: return fastEmit_ISD_STRICT_FMUL_MVT_f32_rr(RetVT, Op0, Op1);
2496 case MVT::f64: return fastEmit_ISD_STRICT_FMUL_MVT_f64_rr(RetVT, Op0, Op1);
2497 default: return Register();
2498 }
2499}
2500
2501// FastEmit functions for ISD::STRICT_FSUB.
2502
2503Register fastEmit_ISD_STRICT_FSUB_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
2504 if (RetVT.SimpleTy != MVT::f32)
2505 return Register();
2506 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2507 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_S, RC: &Mips::FGR32RegClass, Op0, Op1);
2508 }
2509 return Register();
2510}
2511
2512Register fastEmit_ISD_STRICT_FSUB_MVT_f64_rr(MVT RetVT, Register Op0, Register Op1) {
2513 if (RetVT.SimpleTy != MVT::f64)
2514 return Register();
2515 if ((Subtarget->hasStandardEncoding()) && (Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMicroMipsMode())) {
2516 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D64, RC: &Mips::FGR64RegClass, Op0, Op1);
2517 }
2518 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMicroMipsMode())) {
2519 return fastEmitInst_rr(MachineInstOpcode: Mips::FSUB_D32, RC: &Mips::AFGR64RegClass, Op0, Op1);
2520 }
2521 return Register();
2522}
2523
2524Register fastEmit_ISD_STRICT_FSUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2525 switch (VT.SimpleTy) {
2526 case MVT::f32: return fastEmit_ISD_STRICT_FSUB_MVT_f32_rr(RetVT, Op0, Op1);
2527 case MVT::f64: return fastEmit_ISD_STRICT_FSUB_MVT_f64_rr(RetVT, Op0, Op1);
2528 default: return Register();
2529 }
2530}
2531
2532// FastEmit functions for ISD::SUB.
2533
2534Register fastEmit_ISD_SUB_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2535 if (RetVT.SimpleTy != MVT::i32)
2536 return Register();
2537 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2538 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBU16_MMR6, RC: &Mips::GPRMM16RegClass, Op0, Op1);
2539 }
2540 if ((Subtarget->inMips16Mode())) {
2541 return fastEmitInst_rr(MachineInstOpcode: Mips::SubuRxRyRz16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2542 }
2543 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
2544 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2545 }
2546 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2547 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu, RC: &Mips::GPR32RegClass, Op0, Op1);
2548 }
2549 return Register();
2550}
2551
2552Register fastEmit_ISD_SUB_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2553 if (RetVT.SimpleTy != MVT::i64)
2554 return Register();
2555 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2556 return fastEmitInst_rr(MachineInstOpcode: Mips::DSUBu, RC: &Mips::GPR64RegClass, Op0, Op1);
2557 }
2558 return Register();
2559}
2560
2561Register fastEmit_ISD_SUB_MVT_v4i8_rr(MVT RetVT, Register Op0, Register Op1) {
2562 if (RetVT.SimpleTy != MVT::v4i8)
2563 return Register();
2564 if ((Subtarget->hasDSP())) {
2565 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBU_QB, RC: &Mips::DSPRRegClass, Op0, Op1);
2566 }
2567 return Register();
2568}
2569
2570Register fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2571 if (RetVT.SimpleTy != MVT::v16i8)
2572 return Register();
2573 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2574 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2575 }
2576 return Register();
2577}
2578
2579Register fastEmit_ISD_SUB_MVT_v2i16_rr(MVT RetVT, Register Op0, Register Op1) {
2580 if (RetVT.SimpleTy != MVT::v2i16)
2581 return Register();
2582 if ((Subtarget->hasDSP())) {
2583 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBQ_PH, RC: &Mips::DSPRRegClass, Op0, Op1);
2584 }
2585 return Register();
2586}
2587
2588Register fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2589 if (RetVT.SimpleTy != MVT::v8i16)
2590 return Register();
2591 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2592 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2593 }
2594 return Register();
2595}
2596
2597Register fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2598 if (RetVT.SimpleTy != MVT::v4i32)
2599 return Register();
2600 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2601 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2602 }
2603 return Register();
2604}
2605
2606Register fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2607 if (RetVT.SimpleTy != MVT::v2i64)
2608 return Register();
2609 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2610 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2611 }
2612 return Register();
2613}
2614
2615Register fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2616 switch (VT.SimpleTy) {
2617 case MVT::i32: return fastEmit_ISD_SUB_MVT_i32_rr(RetVT, Op0, Op1);
2618 case MVT::i64: return fastEmit_ISD_SUB_MVT_i64_rr(RetVT, Op0, Op1);
2619 case MVT::v4i8: return fastEmit_ISD_SUB_MVT_v4i8_rr(RetVT, Op0, Op1);
2620 case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op1);
2621 case MVT::v2i16: return fastEmit_ISD_SUB_MVT_v2i16_rr(RetVT, Op0, Op1);
2622 case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op1);
2623 case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op1);
2624 case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op1);
2625 default: return Register();
2626 }
2627}
2628
2629// FastEmit functions for ISD::SUBC.
2630
2631Register fastEmit_ISD_SUBC_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2632 if (RetVT.SimpleTy != MVT::i32)
2633 return Register();
2634 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2635 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2636 }
2637 if ((Subtarget->inMicroMipsMode())) {
2638 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2639 }
2640 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2641 return fastEmitInst_rr(MachineInstOpcode: Mips::SUBu, RC: &Mips::GPR32RegClass, Op0, Op1);
2642 }
2643 return Register();
2644}
2645
2646Register fastEmit_ISD_SUBC_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2647 if (RetVT.SimpleTy != MVT::i64)
2648 return Register();
2649 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (Subtarget->isGP64bit()) && (!Subtarget->inMicroMipsMode())) {
2650 return fastEmitInst_rr(MachineInstOpcode: Mips::DSUBu, RC: &Mips::GPR64RegClass, Op0, Op1);
2651 }
2652 return Register();
2653}
2654
2655Register fastEmit_ISD_SUBC_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2656 switch (VT.SimpleTy) {
2657 case MVT::i32: return fastEmit_ISD_SUBC_MVT_i32_rr(RetVT, Op0, Op1);
2658 case MVT::i64: return fastEmit_ISD_SUBC_MVT_i64_rr(RetVT, Op0, Op1);
2659 default: return Register();
2660 }
2661}
2662
2663// FastEmit functions for ISD::UDIV.
2664
2665Register fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2666 if (RetVT.SimpleTy != MVT::i32)
2667 return Register();
2668 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2669 return fastEmitInst_rr(MachineInstOpcode: Mips::DIVU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2670 }
2671 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2672 return fastEmitInst_rr(MachineInstOpcode: Mips::DIVU, RC: &Mips::GPR32RegClass, Op0, Op1);
2673 }
2674 return Register();
2675}
2676
2677Register fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2678 if (RetVT.SimpleTy != MVT::i64)
2679 return Register();
2680 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2681 return fastEmitInst_rr(MachineInstOpcode: Mips::DDIVU, RC: &Mips::GPR64RegClass, Op0, Op1);
2682 }
2683 return Register();
2684}
2685
2686Register fastEmit_ISD_UDIV_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2687 if (RetVT.SimpleTy != MVT::v16i8)
2688 return Register();
2689 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2690 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2691 }
2692 return Register();
2693}
2694
2695Register fastEmit_ISD_UDIV_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2696 if (RetVT.SimpleTy != MVT::v8i16)
2697 return Register();
2698 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2699 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2700 }
2701 return Register();
2702}
2703
2704Register fastEmit_ISD_UDIV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2705 if (RetVT.SimpleTy != MVT::v4i32)
2706 return Register();
2707 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2708 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2709 }
2710 return Register();
2711}
2712
2713Register fastEmit_ISD_UDIV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2714 if (RetVT.SimpleTy != MVT::v2i64)
2715 return Register();
2716 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2717 return fastEmitInst_rr(MachineInstOpcode: Mips::DIV_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2718 }
2719 return Register();
2720}
2721
2722Register fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2723 switch (VT.SimpleTy) {
2724 case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op1);
2725 case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op1);
2726 case MVT::v16i8: return fastEmit_ISD_UDIV_MVT_v16i8_rr(RetVT, Op0, Op1);
2727 case MVT::v8i16: return fastEmit_ISD_UDIV_MVT_v8i16_rr(RetVT, Op0, Op1);
2728 case MVT::v4i32: return fastEmit_ISD_UDIV_MVT_v4i32_rr(RetVT, Op0, Op1);
2729 case MVT::v2i64: return fastEmit_ISD_UDIV_MVT_v2i64_rr(RetVT, Op0, Op1);
2730 default: return Register();
2731 }
2732}
2733
2734// FastEmit functions for ISD::UMAX.
2735
2736Register fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2737 if (RetVT.SimpleTy != MVT::v16i8)
2738 return Register();
2739 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2740 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2741 }
2742 return Register();
2743}
2744
2745Register fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2746 if (RetVT.SimpleTy != MVT::v8i16)
2747 return Register();
2748 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2749 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2750 }
2751 return Register();
2752}
2753
2754Register fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2755 if (RetVT.SimpleTy != MVT::v4i32)
2756 return Register();
2757 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2758 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2759 }
2760 return Register();
2761}
2762
2763Register fastEmit_ISD_UMAX_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2764 if (RetVT.SimpleTy != MVT::v2i64)
2765 return Register();
2766 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2767 return fastEmitInst_rr(MachineInstOpcode: Mips::MAX_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2768 }
2769 return Register();
2770}
2771
2772Register fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2773 switch (VT.SimpleTy) {
2774 case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op1);
2775 case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op1);
2776 case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op1);
2777 case MVT::v2i64: return fastEmit_ISD_UMAX_MVT_v2i64_rr(RetVT, Op0, Op1);
2778 default: return Register();
2779 }
2780}
2781
2782// FastEmit functions for ISD::UMIN.
2783
2784Register fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2785 if (RetVT.SimpleTy != MVT::v16i8)
2786 return Register();
2787 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2788 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2789 }
2790 return Register();
2791}
2792
2793Register fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2794 if (RetVT.SimpleTy != MVT::v8i16)
2795 return Register();
2796 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2797 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2798 }
2799 return Register();
2800}
2801
2802Register fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2803 if (RetVT.SimpleTy != MVT::v4i32)
2804 return Register();
2805 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2806 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2807 }
2808 return Register();
2809}
2810
2811Register fastEmit_ISD_UMIN_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2812 if (RetVT.SimpleTy != MVT::v2i64)
2813 return Register();
2814 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2815 return fastEmitInst_rr(MachineInstOpcode: Mips::MIN_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2816 }
2817 return Register();
2818}
2819
2820Register fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2821 switch (VT.SimpleTy) {
2822 case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op1);
2823 case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op1);
2824 case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op1);
2825 case MVT::v2i64: return fastEmit_ISD_UMIN_MVT_v2i64_rr(RetVT, Op0, Op1);
2826 default: return Register();
2827 }
2828}
2829
2830// FastEmit functions for ISD::UREM.
2831
2832Register fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2833 if (RetVT.SimpleTy != MVT::i32)
2834 return Register();
2835 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2836 return fastEmitInst_rr(MachineInstOpcode: Mips::MODU_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2837 }
2838 if ((Subtarget->hasMips32r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2839 return fastEmitInst_rr(MachineInstOpcode: Mips::MODU, RC: &Mips::GPR32RegClass, Op0, Op1);
2840 }
2841 return Register();
2842}
2843
2844Register fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2845 if (RetVT.SimpleTy != MVT::i64)
2846 return Register();
2847 if ((Subtarget->hasMips64r6()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2848 return fastEmitInst_rr(MachineInstOpcode: Mips::DMODU, RC: &Mips::GPR64RegClass, Op0, Op1);
2849 }
2850 return Register();
2851}
2852
2853Register fastEmit_ISD_UREM_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2854 if (RetVT.SimpleTy != MVT::v16i8)
2855 return Register();
2856 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2857 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
2858 }
2859 return Register();
2860}
2861
2862Register fastEmit_ISD_UREM_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2863 if (RetVT.SimpleTy != MVT::v8i16)
2864 return Register();
2865 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2866 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
2867 }
2868 return Register();
2869}
2870
2871Register fastEmit_ISD_UREM_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2872 if (RetVT.SimpleTy != MVT::v4i32)
2873 return Register();
2874 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2875 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
2876 }
2877 return Register();
2878}
2879
2880Register fastEmit_ISD_UREM_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2881 if (RetVT.SimpleTy != MVT::v2i64)
2882 return Register();
2883 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2884 return fastEmitInst_rr(MachineInstOpcode: Mips::MOD_U_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
2885 }
2886 return Register();
2887}
2888
2889Register fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2890 switch (VT.SimpleTy) {
2891 case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op1);
2892 case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op1);
2893 case MVT::v16i8: return fastEmit_ISD_UREM_MVT_v16i8_rr(RetVT, Op0, Op1);
2894 case MVT::v8i16: return fastEmit_ISD_UREM_MVT_v8i16_rr(RetVT, Op0, Op1);
2895 case MVT::v4i32: return fastEmit_ISD_UREM_MVT_v4i32_rr(RetVT, Op0, Op1);
2896 case MVT::v2i64: return fastEmit_ISD_UREM_MVT_v2i64_rr(RetVT, Op0, Op1);
2897 default: return Register();
2898 }
2899}
2900
2901// FastEmit functions for ISD::XOR.
2902
2903Register fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2904 if (RetVT.SimpleTy != MVT::i32)
2905 return Register();
2906 if ((Subtarget->inMips16Mode())) {
2907 return fastEmitInst_rr(MachineInstOpcode: Mips::XorRxRxRy16, RC: &Mips::CPU16RegsRegClass, Op0, Op1);
2908 }
2909 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
2910 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_MMR6, RC: &Mips::GPR32RegClass, Op0, Op1);
2911 }
2912 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6())) {
2913 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_MM, RC: &Mips::GPR32RegClass, Op0, Op1);
2914 }
2915 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
2916 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR, RC: &Mips::GPR32RegClass, Op0, Op1);
2917 }
2918 return Register();
2919}
2920
2921Register fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
2922 if (RetVT.SimpleTy != MVT::i64)
2923 return Register();
2924 if ((Subtarget->isGP64bit()) && (!Subtarget->inMips16Mode())) {
2925 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR64, RC: &Mips::GPR64RegClass, Op0, Op1);
2926 }
2927 return Register();
2928}
2929
2930Register fastEmit_ISD_XOR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
2931 if (RetVT.SimpleTy != MVT::v16i8)
2932 return Register();
2933 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2934 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
2935 }
2936 return Register();
2937}
2938
2939Register fastEmit_ISD_XOR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
2940 if (RetVT.SimpleTy != MVT::v8i16)
2941 return Register();
2942 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2943 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
2944 }
2945 return Register();
2946}
2947
2948Register fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
2949 if (RetVT.SimpleTy != MVT::v4i32)
2950 return Register();
2951 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2952 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
2953 }
2954 return Register();
2955}
2956
2957Register fastEmit_ISD_XOR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
2958 if (RetVT.SimpleTy != MVT::v2i64)
2959 return Register();
2960 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
2961 return fastEmitInst_rr(MachineInstOpcode: Mips::XOR_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
2962 }
2963 return Register();
2964}
2965
2966Register fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2967 switch (VT.SimpleTy) {
2968 case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op1);
2969 case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op1);
2970 case MVT::v16i8: return fastEmit_ISD_XOR_MVT_v16i8_rr(RetVT, Op0, Op1);
2971 case MVT::v8i16: return fastEmit_ISD_XOR_MVT_v8i16_rr(RetVT, Op0, Op1);
2972 case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op1);
2973 case MVT::v2i64: return fastEmit_ISD_XOR_MVT_v2i64_rr(RetVT, Op0, Op1);
2974 default: return Register();
2975 }
2976}
2977
2978// FastEmit functions for MipsISD::BuildPairF64.
2979
2980Register fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
2981 if (RetVT.SimpleTy != MVT::f64)
2982 return Register();
2983 if ((Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMips16Mode())) {
2984 return fastEmitInst_rr(MachineInstOpcode: Mips::BuildPairF64_64, RC: &Mips::FGR64RegClass, Op0, Op1);
2985 }
2986 if ((!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode())) {
2987 return fastEmitInst_rr(MachineInstOpcode: Mips::BuildPairF64, RC: &Mips::AFGR64RegClass, Op0, Op1);
2988 }
2989 return Register();
2990}
2991
2992Register fastEmit_MipsISD_BuildPairF64_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
2993 switch (VT.SimpleTy) {
2994 case MVT::i32: return fastEmit_MipsISD_BuildPairF64_MVT_i32_rr(RetVT, Op0, Op1);
2995 default: return Register();
2996 }
2997}
2998
2999// FastEmit functions for MipsISD::BuildPairF64_FPR.
3000
3001Register fastEmit_MipsISD_BuildPairF64_FPR_MVT_f32_rr(MVT RetVT, Register Op0, Register Op1) {
3002 if (RetVT.SimpleTy != MVT::f64)
3003 return Register();
3004 if ((!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode())) {
3005 return fastEmitInst_rr(MachineInstOpcode: Mips::BuildPairF64_FPR, RC: &Mips::AFGR64RegClass, Op0, Op1);
3006 }
3007 return Register();
3008}
3009
3010Register fastEmit_MipsISD_BuildPairF64_FPR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3011 switch (VT.SimpleTy) {
3012 case MVT::f32: return fastEmit_MipsISD_BuildPairF64_FPR_MVT_f32_rr(RetVT, Op0, Op1);
3013 default: return Register();
3014 }
3015}
3016
3017// FastEmit functions for MipsISD::DivRem.
3018
3019Register fastEmit_MipsISD_DivRem_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3020 if (RetVT.SimpleTy != MVT::Untyped)
3021 return Register();
3022 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3023 return fastEmitInst_rr(MachineInstOpcode: Mips::SDIV_MM_Pseudo, RC: &Mips::ACC64RegClass, Op0, Op1);
3024 }
3025 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3026 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoSDIV, RC: &Mips::ACC64RegClass, Op0, Op1);
3027 }
3028 return Register();
3029}
3030
3031Register fastEmit_MipsISD_DivRem_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3032 if (RetVT.SimpleTy != MVT::Untyped)
3033 return Register();
3034 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (!Subtarget->isR5900())) {
3035 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDSDIV, RC: &Mips::ACC128RegClass, Op0, Op1);
3036 }
3037 return Register();
3038}
3039
3040Register fastEmit_MipsISD_DivRem_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3041 switch (VT.SimpleTy) {
3042 case MVT::i32: return fastEmit_MipsISD_DivRem_MVT_i32_rr(RetVT, Op0, Op1);
3043 case MVT::i64: return fastEmit_MipsISD_DivRem_MVT_i64_rr(RetVT, Op0, Op1);
3044 default: return Register();
3045 }
3046}
3047
3048// FastEmit functions for MipsISD::DivRemU.
3049
3050Register fastEmit_MipsISD_DivRemU_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3051 if (RetVT.SimpleTy != MVT::Untyped)
3052 return Register();
3053 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3054 return fastEmitInst_rr(MachineInstOpcode: Mips::UDIV_MM_Pseudo, RC: &Mips::ACC64RegClass, Op0, Op1);
3055 }
3056 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3057 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoUDIV, RC: &Mips::ACC64RegClass, Op0, Op1);
3058 }
3059 return Register();
3060}
3061
3062Register fastEmit_MipsISD_DivRemU_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3063 if (RetVT.SimpleTy != MVT::Untyped)
3064 return Register();
3065 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (!Subtarget->isR5900())) {
3066 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDUDIV, RC: &Mips::ACC128RegClass, Op0, Op1);
3067 }
3068 return Register();
3069}
3070
3071Register fastEmit_MipsISD_DivRemU_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3072 switch (VT.SimpleTy) {
3073 case MVT::i32: return fastEmit_MipsISD_DivRemU_MVT_i32_rr(RetVT, Op0, Op1);
3074 case MVT::i64: return fastEmit_MipsISD_DivRemU_MVT_i64_rr(RetVT, Op0, Op1);
3075 default: return Register();
3076 }
3077}
3078
3079// FastEmit functions for MipsISD::ILVEV.
3080
3081Register fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3082 if (RetVT.SimpleTy != MVT::v16i8)
3083 return Register();
3084 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3085 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3086 }
3087 return Register();
3088}
3089
3090Register fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3091 if (RetVT.SimpleTy != MVT::v8i16)
3092 return Register();
3093 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3094 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3095 }
3096 return Register();
3097}
3098
3099Register fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3100 if (RetVT.SimpleTy != MVT::v4i32)
3101 return Register();
3102 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3103 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3104 }
3105 return Register();
3106}
3107
3108Register fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3109 if (RetVT.SimpleTy != MVT::v2i64)
3110 return Register();
3111 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3112 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVEV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3113 }
3114 return Register();
3115}
3116
3117Register fastEmit_MipsISD_ILVEV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3118 switch (VT.SimpleTy) {
3119 case MVT::v16i8: return fastEmit_MipsISD_ILVEV_MVT_v16i8_rr(RetVT, Op0, Op1);
3120 case MVT::v8i16: return fastEmit_MipsISD_ILVEV_MVT_v8i16_rr(RetVT, Op0, Op1);
3121 case MVT::v4i32: return fastEmit_MipsISD_ILVEV_MVT_v4i32_rr(RetVT, Op0, Op1);
3122 case MVT::v2i64: return fastEmit_MipsISD_ILVEV_MVT_v2i64_rr(RetVT, Op0, Op1);
3123 default: return Register();
3124 }
3125}
3126
3127// FastEmit functions for MipsISD::ILVL.
3128
3129Register fastEmit_MipsISD_ILVL_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3130 if (RetVT.SimpleTy != MVT::v16i8)
3131 return Register();
3132 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3133 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3134 }
3135 return Register();
3136}
3137
3138Register fastEmit_MipsISD_ILVL_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3139 if (RetVT.SimpleTy != MVT::v8i16)
3140 return Register();
3141 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3142 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3143 }
3144 return Register();
3145}
3146
3147Register fastEmit_MipsISD_ILVL_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3148 if (RetVT.SimpleTy != MVT::v4i32)
3149 return Register();
3150 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3151 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3152 }
3153 return Register();
3154}
3155
3156Register fastEmit_MipsISD_ILVL_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3157 if (RetVT.SimpleTy != MVT::v2i64)
3158 return Register();
3159 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3160 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVL_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3161 }
3162 return Register();
3163}
3164
3165Register fastEmit_MipsISD_ILVL_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3166 switch (VT.SimpleTy) {
3167 case MVT::v16i8: return fastEmit_MipsISD_ILVL_MVT_v16i8_rr(RetVT, Op0, Op1);
3168 case MVT::v8i16: return fastEmit_MipsISD_ILVL_MVT_v8i16_rr(RetVT, Op0, Op1);
3169 case MVT::v4i32: return fastEmit_MipsISD_ILVL_MVT_v4i32_rr(RetVT, Op0, Op1);
3170 case MVT::v2i64: return fastEmit_MipsISD_ILVL_MVT_v2i64_rr(RetVT, Op0, Op1);
3171 default: return Register();
3172 }
3173}
3174
3175// FastEmit functions for MipsISD::ILVOD.
3176
3177Register fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3178 if (RetVT.SimpleTy != MVT::v16i8)
3179 return Register();
3180 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3181 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3182 }
3183 return Register();
3184}
3185
3186Register fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3187 if (RetVT.SimpleTy != MVT::v8i16)
3188 return Register();
3189 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3190 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3191 }
3192 return Register();
3193}
3194
3195Register fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3196 if (RetVT.SimpleTy != MVT::v4i32)
3197 return Register();
3198 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3199 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3200 }
3201 return Register();
3202}
3203
3204Register fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3205 if (RetVT.SimpleTy != MVT::v2i64)
3206 return Register();
3207 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3208 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVOD_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3209 }
3210 return Register();
3211}
3212
3213Register fastEmit_MipsISD_ILVOD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3214 switch (VT.SimpleTy) {
3215 case MVT::v16i8: return fastEmit_MipsISD_ILVOD_MVT_v16i8_rr(RetVT, Op0, Op1);
3216 case MVT::v8i16: return fastEmit_MipsISD_ILVOD_MVT_v8i16_rr(RetVT, Op0, Op1);
3217 case MVT::v4i32: return fastEmit_MipsISD_ILVOD_MVT_v4i32_rr(RetVT, Op0, Op1);
3218 case MVT::v2i64: return fastEmit_MipsISD_ILVOD_MVT_v2i64_rr(RetVT, Op0, Op1);
3219 default: return Register();
3220 }
3221}
3222
3223// FastEmit functions for MipsISD::ILVR.
3224
3225Register fastEmit_MipsISD_ILVR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3226 if (RetVT.SimpleTy != MVT::v16i8)
3227 return Register();
3228 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3229 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3230 }
3231 return Register();
3232}
3233
3234Register fastEmit_MipsISD_ILVR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3235 if (RetVT.SimpleTy != MVT::v8i16)
3236 return Register();
3237 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3238 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3239 }
3240 return Register();
3241}
3242
3243Register fastEmit_MipsISD_ILVR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3244 if (RetVT.SimpleTy != MVT::v4i32)
3245 return Register();
3246 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3247 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3248 }
3249 return Register();
3250}
3251
3252Register fastEmit_MipsISD_ILVR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3253 if (RetVT.SimpleTy != MVT::v2i64)
3254 return Register();
3255 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3256 return fastEmitInst_rr(MachineInstOpcode: Mips::ILVR_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3257 }
3258 return Register();
3259}
3260
3261Register fastEmit_MipsISD_ILVR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3262 switch (VT.SimpleTy) {
3263 case MVT::v16i8: return fastEmit_MipsISD_ILVR_MVT_v16i8_rr(RetVT, Op0, Op1);
3264 case MVT::v8i16: return fastEmit_MipsISD_ILVR_MVT_v8i16_rr(RetVT, Op0, Op1);
3265 case MVT::v4i32: return fastEmit_MipsISD_ILVR_MVT_v4i32_rr(RetVT, Op0, Op1);
3266 case MVT::v2i64: return fastEmit_MipsISD_ILVR_MVT_v2i64_rr(RetVT, Op0, Op1);
3267 default: return Register();
3268 }
3269}
3270
3271// FastEmit functions for MipsISD::MTLOHI.
3272
3273Register fastEmit_MipsISD_MTLOHI_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3274 if (RetVT.SimpleTy != MVT::Untyped)
3275 return Register();
3276 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
3277 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI_MM, RC: &Mips::ACC64RegClass, Op0, Op1);
3278 }
3279 if ((Subtarget->hasDSP()) && (!Subtarget->inMips16Mode())) {
3280 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI_DSP, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3281 }
3282 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3283 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI, RC: &Mips::ACC64RegClass, Op0, Op1);
3284 }
3285 return Register();
3286}
3287
3288Register fastEmit_MipsISD_MTLOHI_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3289 if (RetVT.SimpleTy != MVT::Untyped)
3290 return Register();
3291 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3292 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMTLOHI64, RC: &Mips::ACC128RegClass, Op0, Op1);
3293 }
3294 return Register();
3295}
3296
3297Register fastEmit_MipsISD_MTLOHI_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3298 switch (VT.SimpleTy) {
3299 case MVT::i32: return fastEmit_MipsISD_MTLOHI_MVT_i32_rr(RetVT, Op0, Op1);
3300 case MVT::i64: return fastEmit_MipsISD_MTLOHI_MVT_i64_rr(RetVT, Op0, Op1);
3301 default: return Register();
3302 }
3303}
3304
3305// FastEmit functions for MipsISD::Mult.
3306
3307Register fastEmit_MipsISD_Mult_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3308 if (RetVT.SimpleTy != MVT::Untyped)
3309 return Register();
3310 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
3311 return fastEmitInst_rr(MachineInstOpcode: Mips::MULT_DSP_MM, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3312 }
3313 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
3314 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULT_MM, RC: &Mips::ACC64RegClass, Op0, Op1);
3315 }
3316 if ((Subtarget->hasDSP())) {
3317 return fastEmitInst_rr(MachineInstOpcode: Mips::MULT_DSP, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3318 }
3319 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3320 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULT, RC: &Mips::ACC64RegClass, Op0, Op1);
3321 }
3322 return Register();
3323}
3324
3325Register fastEmit_MipsISD_Mult_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3326 if (RetVT.SimpleTy != MVT::Untyped)
3327 return Register();
3328 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (!Subtarget->isR5900())) {
3329 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDMULT, RC: &Mips::ACC128RegClass, Op0, Op1);
3330 }
3331 return Register();
3332}
3333
3334Register fastEmit_MipsISD_Mult_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3335 switch (VT.SimpleTy) {
3336 case MVT::i32: return fastEmit_MipsISD_Mult_MVT_i32_rr(RetVT, Op0, Op1);
3337 case MVT::i64: return fastEmit_MipsISD_Mult_MVT_i64_rr(RetVT, Op0, Op1);
3338 default: return Register();
3339 }
3340}
3341
3342// FastEmit functions for MipsISD::Multu.
3343
3344Register fastEmit_MipsISD_Multu_MVT_i32_rr(MVT RetVT, Register Op0, Register Op1) {
3345 if (RetVT.SimpleTy != MVT::Untyped)
3346 return Register();
3347 if ((Subtarget->hasDSP()) && (Subtarget->inMicroMipsMode())) {
3348 return fastEmitInst_rr(MachineInstOpcode: Mips::MULTU_DSP_MM, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3349 }
3350 if ((Subtarget->inMicroMipsMode()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6())) {
3351 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULTu_MM, RC: &Mips::ACC64RegClass, Op0, Op1);
3352 }
3353 if ((Subtarget->hasDSP())) {
3354 return fastEmitInst_rr(MachineInstOpcode: Mips::MULTU_DSP, RC: &Mips::ACC64DSPRegClass, Op0, Op1);
3355 }
3356 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->hasDSP()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6())) {
3357 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoMULTu, RC: &Mips::ACC64RegClass, Op0, Op1);
3358 }
3359 return Register();
3360}
3361
3362Register fastEmit_MipsISD_Multu_MVT_i64_rr(MVT RetVT, Register Op0, Register Op1) {
3363 if (RetVT.SimpleTy != MVT::Untyped)
3364 return Register();
3365 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->hasMips32r6()) && (!Subtarget->hasMips64r6()) && (!Subtarget->isR5900())) {
3366 return fastEmitInst_rr(MachineInstOpcode: Mips::PseudoDMULTu, RC: &Mips::ACC128RegClass, Op0, Op1);
3367 }
3368 return Register();
3369}
3370
3371Register fastEmit_MipsISD_Multu_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3372 switch (VT.SimpleTy) {
3373 case MVT::i32: return fastEmit_MipsISD_Multu_MVT_i32_rr(RetVT, Op0, Op1);
3374 case MVT::i64: return fastEmit_MipsISD_Multu_MVT_i64_rr(RetVT, Op0, Op1);
3375 default: return Register();
3376 }
3377}
3378
3379// FastEmit functions for MipsISD::PCKEV.
3380
3381Register fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3382 if (RetVT.SimpleTy != MVT::v16i8)
3383 return Register();
3384 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3385 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3386 }
3387 return Register();
3388}
3389
3390Register fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3391 if (RetVT.SimpleTy != MVT::v8i16)
3392 return Register();
3393 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3394 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3395 }
3396 return Register();
3397}
3398
3399Register fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3400 if (RetVT.SimpleTy != MVT::v4i32)
3401 return Register();
3402 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3403 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3404 }
3405 return Register();
3406}
3407
3408Register fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3409 if (RetVT.SimpleTy != MVT::v2i64)
3410 return Register();
3411 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3412 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKEV_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3413 }
3414 return Register();
3415}
3416
3417Register fastEmit_MipsISD_PCKEV_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3418 switch (VT.SimpleTy) {
3419 case MVT::v16i8: return fastEmit_MipsISD_PCKEV_MVT_v16i8_rr(RetVT, Op0, Op1);
3420 case MVT::v8i16: return fastEmit_MipsISD_PCKEV_MVT_v8i16_rr(RetVT, Op0, Op1);
3421 case MVT::v4i32: return fastEmit_MipsISD_PCKEV_MVT_v4i32_rr(RetVT, Op0, Op1);
3422 case MVT::v2i64: return fastEmit_MipsISD_PCKEV_MVT_v2i64_rr(RetVT, Op0, Op1);
3423 default: return Register();
3424 }
3425}
3426
3427// FastEmit functions for MipsISD::PCKOD.
3428
3429Register fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3430 if (RetVT.SimpleTy != MVT::v16i8)
3431 return Register();
3432 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3433 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_B, RC: &Mips::MSA128BRegClass, Op0, Op1);
3434 }
3435 return Register();
3436}
3437
3438Register fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3439 if (RetVT.SimpleTy != MVT::v8i16)
3440 return Register();
3441 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3442 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_H, RC: &Mips::MSA128HRegClass, Op0, Op1);
3443 }
3444 return Register();
3445}
3446
3447Register fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3448 if (RetVT.SimpleTy != MVT::v4i32)
3449 return Register();
3450 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3451 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_W, RC: &Mips::MSA128WRegClass, Op0, Op1);
3452 }
3453 return Register();
3454}
3455
3456Register fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3457 if (RetVT.SimpleTy != MVT::v2i64)
3458 return Register();
3459 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3460 return fastEmitInst_rr(MachineInstOpcode: Mips::PCKOD_D, RC: &Mips::MSA128DRegClass, Op0, Op1);
3461 }
3462 return Register();
3463}
3464
3465Register fastEmit_MipsISD_PCKOD_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3466 switch (VT.SimpleTy) {
3467 case MVT::v16i8: return fastEmit_MipsISD_PCKOD_MVT_v16i8_rr(RetVT, Op0, Op1);
3468 case MVT::v8i16: return fastEmit_MipsISD_PCKOD_MVT_v8i16_rr(RetVT, Op0, Op1);
3469 case MVT::v4i32: return fastEmit_MipsISD_PCKOD_MVT_v4i32_rr(RetVT, Op0, Op1);
3470 case MVT::v2i64: return fastEmit_MipsISD_PCKOD_MVT_v2i64_rr(RetVT, Op0, Op1);
3471 default: return Register();
3472 }
3473}
3474
3475// FastEmit functions for MipsISD::VNOR.
3476
3477Register fastEmit_MipsISD_VNOR_MVT_v16i8_rr(MVT RetVT, Register Op0, Register Op1) {
3478 if (RetVT.SimpleTy != MVT::v16i8)
3479 return Register();
3480 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3481 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V, RC: &Mips::MSA128BRegClass, Op0, Op1);
3482 }
3483 return Register();
3484}
3485
3486Register fastEmit_MipsISD_VNOR_MVT_v8i16_rr(MVT RetVT, Register Op0, Register Op1) {
3487 if (RetVT.SimpleTy != MVT::v8i16)
3488 return Register();
3489 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3490 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V_H_PSEUDO, RC: &Mips::MSA128HRegClass, Op0, Op1);
3491 }
3492 return Register();
3493}
3494
3495Register fastEmit_MipsISD_VNOR_MVT_v4i32_rr(MVT RetVT, Register Op0, Register Op1) {
3496 if (RetVT.SimpleTy != MVT::v4i32)
3497 return Register();
3498 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3499 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V_W_PSEUDO, RC: &Mips::MSA128WRegClass, Op0, Op1);
3500 }
3501 return Register();
3502}
3503
3504Register fastEmit_MipsISD_VNOR_MVT_v2i64_rr(MVT RetVT, Register Op0, Register Op1) {
3505 if (RetVT.SimpleTy != MVT::v2i64)
3506 return Register();
3507 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3508 return fastEmitInst_rr(MachineInstOpcode: Mips::NOR_V_D_PSEUDO, RC: &Mips::MSA128DRegClass, Op0, Op1);
3509 }
3510 return Register();
3511}
3512
3513Register fastEmit_MipsISD_VNOR_rr(MVT VT, MVT RetVT, Register Op0, Register Op1) {
3514 switch (VT.SimpleTy) {
3515 case MVT::v16i8: return fastEmit_MipsISD_VNOR_MVT_v16i8_rr(RetVT, Op0, Op1);
3516 case MVT::v8i16: return fastEmit_MipsISD_VNOR_MVT_v8i16_rr(RetVT, Op0, Op1);
3517 case MVT::v4i32: return fastEmit_MipsISD_VNOR_MVT_v4i32_rr(RetVT, Op0, Op1);
3518 case MVT::v2i64: return fastEmit_MipsISD_VNOR_MVT_v2i64_rr(RetVT, Op0, Op1);
3519 default: return Register();
3520 }
3521}
3522
3523// Top-level FastEmit function.
3524
3525Register fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, Register Op1) override {
3526 switch (Opcode) {
3527 case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op1);
3528 case ISD::ADDC: return fastEmit_ISD_ADDC_rr(VT, RetVT, Op0, Op1);
3529 case ISD::ADDE: return fastEmit_ISD_ADDE_rr(VT, RetVT, Op0, Op1);
3530 case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op1);
3531 case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op1);
3532 case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op1);
3533 case ISD::FMAXNUM: return fastEmit_ISD_FMAXNUM_rr(VT, RetVT, Op0, Op1);
3534 case ISD::FMAXNUM_IEEE: return fastEmit_ISD_FMAXNUM_IEEE_rr(VT, RetVT, Op0, Op1);
3535 case ISD::FMINNUM: return fastEmit_ISD_FMINNUM_rr(VT, RetVT, Op0, Op1);
3536 case ISD::FMINNUM_IEEE: return fastEmit_ISD_FMINNUM_IEEE_rr(VT, RetVT, Op0, Op1);
3537 case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op1);
3538 case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op1);
3539 case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op1);
3540 case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op1);
3541 case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op1);
3542 case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op1);
3543 case ISD::ROTR: return fastEmit_ISD_ROTR_rr(VT, RetVT, Op0, Op1);
3544 case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op1);
3545 case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op1);
3546 case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op1);
3547 case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op1);
3548 case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op1);
3549 case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op1);
3550 case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op1);
3551 case ISD::STRICT_FADD: return fastEmit_ISD_STRICT_FADD_rr(VT, RetVT, Op0, Op1);
3552 case ISD::STRICT_FDIV: return fastEmit_ISD_STRICT_FDIV_rr(VT, RetVT, Op0, Op1);
3553 case ISD::STRICT_FMUL: return fastEmit_ISD_STRICT_FMUL_rr(VT, RetVT, Op0, Op1);
3554 case ISD::STRICT_FSUB: return fastEmit_ISD_STRICT_FSUB_rr(VT, RetVT, Op0, Op1);
3555 case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op1);
3556 case ISD::SUBC: return fastEmit_ISD_SUBC_rr(VT, RetVT, Op0, Op1);
3557 case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op1);
3558 case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op1);
3559 case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op1);
3560 case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op1);
3561 case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op1);
3562 case MipsISD::BuildPairF64: return fastEmit_MipsISD_BuildPairF64_rr(VT, RetVT, Op0, Op1);
3563 case MipsISD::BuildPairF64_FPR: return fastEmit_MipsISD_BuildPairF64_FPR_rr(VT, RetVT, Op0, Op1);
3564 case MipsISD::DivRem: return fastEmit_MipsISD_DivRem_rr(VT, RetVT, Op0, Op1);
3565 case MipsISD::DivRemU: return fastEmit_MipsISD_DivRemU_rr(VT, RetVT, Op0, Op1);
3566 case MipsISD::ILVEV: return fastEmit_MipsISD_ILVEV_rr(VT, RetVT, Op0, Op1);
3567 case MipsISD::ILVL: return fastEmit_MipsISD_ILVL_rr(VT, RetVT, Op0, Op1);
3568 case MipsISD::ILVOD: return fastEmit_MipsISD_ILVOD_rr(VT, RetVT, Op0, Op1);
3569 case MipsISD::ILVR: return fastEmit_MipsISD_ILVR_rr(VT, RetVT, Op0, Op1);
3570 case MipsISD::MTLOHI: return fastEmit_MipsISD_MTLOHI_rr(VT, RetVT, Op0, Op1);
3571 case MipsISD::Mult: return fastEmit_MipsISD_Mult_rr(VT, RetVT, Op0, Op1);
3572 case MipsISD::Multu: return fastEmit_MipsISD_Multu_rr(VT, RetVT, Op0, Op1);
3573 case MipsISD::PCKEV: return fastEmit_MipsISD_PCKEV_rr(VT, RetVT, Op0, Op1);
3574 case MipsISD::PCKOD: return fastEmit_MipsISD_PCKOD_rr(VT, RetVT, Op0, Op1);
3575 case MipsISD::VNOR: return fastEmit_MipsISD_VNOR_rr(VT, RetVT, Op0, Op1);
3576 default: return Register();
3577 }
3578}
3579
3580// FastEmit functions for MipsISD::ExtractElementF64.
3581
3582Register fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3583 if (RetVT.SimpleTy != MVT::i32)
3584 return Register();
3585 if ((Subtarget->isFP64bit()) && (!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->inMips16Mode())) {
3586 return fastEmitInst_ri(MachineInstOpcode: Mips::ExtractElementF64_64, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3587 }
3588 if ((!Subtarget->isSingleFloat()) && (!Subtarget->useSoftFloat()) && (!Subtarget->isFP64bit()) && (!Subtarget->inMips16Mode())) {
3589 return fastEmitInst_ri(MachineInstOpcode: Mips::ExtractElementF64, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3590 }
3591 return Register();
3592}
3593
3594Register fastEmit_MipsISD_ExtractElementF64_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3595 switch (VT.SimpleTy) {
3596 case MVT::f64: return fastEmit_MipsISD_ExtractElementF64_MVT_f64_ri(RetVT, Op0, imm1);
3597 default: return Register();
3598 }
3599}
3600
3601// FastEmit functions for MipsISD::SHLL_DSP.
3602
3603Register fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3604 if (RetVT.SimpleTy != MVT::v4i8)
3605 return Register();
3606 if ((Subtarget->hasDSP())) {
3607 return fastEmitInst_ri(MachineInstOpcode: Mips::SHLL_QB, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3608 }
3609 return Register();
3610}
3611
3612Register fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3613 if (RetVT.SimpleTy != MVT::v2i16)
3614 return Register();
3615 if ((Subtarget->hasDSP())) {
3616 return fastEmitInst_ri(MachineInstOpcode: Mips::SHLL_PH, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3617 }
3618 return Register();
3619}
3620
3621Register fastEmit_MipsISD_SHLL_DSP_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3622 switch (VT.SimpleTy) {
3623 case MVT::v4i8: return fastEmit_MipsISD_SHLL_DSP_MVT_v4i8_ri(RetVT, Op0, imm1);
3624 case MVT::v2i16: return fastEmit_MipsISD_SHLL_DSP_MVT_v2i16_ri(RetVT, Op0, imm1);
3625 default: return Register();
3626 }
3627}
3628
3629// FastEmit functions for MipsISD::SHRA_DSP.
3630
3631Register fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3632 if (RetVT.SimpleTy != MVT::v4i8)
3633 return Register();
3634 if ((Subtarget->hasDSPR2())) {
3635 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRA_QB, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3636 }
3637 return Register();
3638}
3639
3640Register fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3641 if (RetVT.SimpleTy != MVT::v2i16)
3642 return Register();
3643 if ((Subtarget->hasDSP())) {
3644 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRA_PH, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3645 }
3646 return Register();
3647}
3648
3649Register fastEmit_MipsISD_SHRA_DSP_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3650 switch (VT.SimpleTy) {
3651 case MVT::v4i8: return fastEmit_MipsISD_SHRA_DSP_MVT_v4i8_ri(RetVT, Op0, imm1);
3652 case MVT::v2i16: return fastEmit_MipsISD_SHRA_DSP_MVT_v2i16_ri(RetVT, Op0, imm1);
3653 default: return Register();
3654 }
3655}
3656
3657// FastEmit functions for MipsISD::SHRL_DSP.
3658
3659Register fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3660 if (RetVT.SimpleTy != MVT::v4i8)
3661 return Register();
3662 if ((Subtarget->hasDSP())) {
3663 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRL_QB, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3664 }
3665 return Register();
3666}
3667
3668Register fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(MVT RetVT, Register Op0, uint64_t imm1) {
3669 if (RetVT.SimpleTy != MVT::v2i16)
3670 return Register();
3671 if ((Subtarget->hasDSPR2())) {
3672 return fastEmitInst_ri(MachineInstOpcode: Mips::SHRL_PH, RC: &Mips::DSPRRegClass, Op0, Imm: imm1);
3673 }
3674 return Register();
3675}
3676
3677Register fastEmit_MipsISD_SHRL_DSP_ri(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3678 switch (VT.SimpleTy) {
3679 case MVT::v4i8: return fastEmit_MipsISD_SHRL_DSP_MVT_v4i8_ri(RetVT, Op0, imm1);
3680 case MVT::v2i16: return fastEmit_MipsISD_SHRL_DSP_MVT_v2i16_ri(RetVT, Op0, imm1);
3681 default: return Register();
3682 }
3683}
3684
3685// Top-level FastEmit function.
3686
3687Register fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) override {
3688 if (VT == MVT::i32 && Predicate_immZExt5(Imm: imm1))
3689 if (Register Reg = fastEmit_ri_Predicate_immZExt5(VT, RetVT, Opcode, Op0, imm1))
3690 return Reg;
3691
3692 if (VT == MVT::i32 && Predicate_immZExt6(Imm: imm1))
3693 if (Register Reg = fastEmit_ri_Predicate_immZExt6(VT, RetVT, Opcode, Op0, imm1))
3694 return Reg;
3695
3696 if (VT == MVT::iPTR && Predicate_immZExt2Ptr(Imm: imm1))
3697 if (Register Reg = fastEmit_ri_Predicate_immZExt2Ptr(VT, RetVT, Opcode, Op0, imm1))
3698 return Reg;
3699
3700 if (VT == MVT::iPTR && Predicate_immZExt1Ptr(Imm: imm1))
3701 if (Register Reg = fastEmit_ri_Predicate_immZExt1Ptr(VT, RetVT, Opcode, Op0, imm1))
3702 return Reg;
3703
3704 if (VT == MVT::i32 && Predicate_immZExt4(Imm: imm1))
3705 if (Register Reg = fastEmit_ri_Predicate_immZExt4(VT, RetVT, Opcode, Op0, imm1))
3706 return Reg;
3707
3708 if (VT == MVT::i32 && Predicate_immSExtAddiur2(Imm: imm1))
3709 if (Register Reg = fastEmit_ri_Predicate_immSExtAddiur2(VT, RetVT, Opcode, Op0, imm1))
3710 return Reg;
3711
3712 if (VT == MVT::i32 && Predicate_immSExtAddius5(Imm: imm1))
3713 if (Register Reg = fastEmit_ri_Predicate_immSExtAddius5(VT, RetVT, Opcode, Op0, imm1))
3714 return Reg;
3715
3716 if (VT == MVT::i32 && Predicate_immZExtAndi16(Imm: imm1))
3717 if (Register Reg = fastEmit_ri_Predicate_immZExtAndi16(VT, RetVT, Opcode, Op0, imm1))
3718 return Reg;
3719
3720 if (VT == MVT::i32 && Predicate_immZExt2Shift(Imm: imm1))
3721 if (Register Reg = fastEmit_ri_Predicate_immZExt2Shift(VT, RetVT, Opcode, Op0, imm1))
3722 return Reg;
3723
3724 switch (Opcode) {
3725 case MipsISD::ExtractElementF64: return fastEmit_MipsISD_ExtractElementF64_ri(VT, RetVT, Op0, imm1);
3726 case MipsISD::SHLL_DSP: return fastEmit_MipsISD_SHLL_DSP_ri(VT, RetVT, Op0, imm1);
3727 case MipsISD::SHRA_DSP: return fastEmit_MipsISD_SHRA_DSP_ri(VT, RetVT, Op0, imm1);
3728 case MipsISD::SHRL_DSP: return fastEmit_MipsISD_SHRL_DSP_ri(VT, RetVT, Op0, imm1);
3729 default: return Register();
3730 }
3731}
3732
3733// FastEmit functions for ISD::ROTR.
3734
3735Register fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, Register Op0, uint64_t imm1) {
3736 if (RetVT.SimpleTy != MVT::i32)
3737 return Register();
3738 if ((Subtarget->inMicroMipsMode())) {
3739 return fastEmitInst_ri(MachineInstOpcode: Mips::ROTR_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3740 }
3741 if ((Subtarget->hasMips32r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3742 return fastEmitInst_ri(MachineInstOpcode: Mips::ROTR, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3743 }
3744 return Register();
3745}
3746
3747Register fastEmit_ISD_ROTR_ri_Predicate_immZExt5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3748 switch (VT.SimpleTy) {
3749 case MVT::i32: return fastEmit_ISD_ROTR_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
3750 default: return Register();
3751 }
3752}
3753
3754// FastEmit functions for ISD::SHL.
3755
3756Register fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, Register Op0, uint64_t imm1) {
3757 if (RetVT.SimpleTy != MVT::i32)
3758 return Register();
3759 if ((Subtarget->inMicroMipsMode())) {
3760 return fastEmitInst_ri(MachineInstOpcode: Mips::SLL_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3761 }
3762 if ((Subtarget->inMips16Mode())) {
3763 return fastEmitInst_ri(MachineInstOpcode: Mips::SllX16, RC: &Mips::CPU16RegsRegClass, Op0, Imm: imm1);
3764 }
3765 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3766 return fastEmitInst_ri(MachineInstOpcode: Mips::SLL, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3767 }
3768 return Register();
3769}
3770
3771Register fastEmit_ISD_SHL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3772 switch (VT.SimpleTy) {
3773 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
3774 default: return Register();
3775 }
3776}
3777
3778// FastEmit functions for ISD::SRA.
3779
3780Register fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, Register Op0, uint64_t imm1) {
3781 if (RetVT.SimpleTy != MVT::i32)
3782 return Register();
3783 if ((Subtarget->inMicroMipsMode())) {
3784 return fastEmitInst_ri(MachineInstOpcode: Mips::SRA_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3785 }
3786 if ((Subtarget->inMips16Mode())) {
3787 return fastEmitInst_ri(MachineInstOpcode: Mips::SraX16, RC: &Mips::CPU16RegsRegClass, Op0, Imm: imm1);
3788 }
3789 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3790 return fastEmitInst_ri(MachineInstOpcode: Mips::SRA, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3791 }
3792 return Register();
3793}
3794
3795Register fastEmit_ISD_SRA_ri_Predicate_immZExt5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3796 switch (VT.SimpleTy) {
3797 case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
3798 default: return Register();
3799 }
3800}
3801
3802// FastEmit functions for ISD::SRL.
3803
3804Register fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(MVT RetVT, Register Op0, uint64_t imm1) {
3805 if (RetVT.SimpleTy != MVT::i32)
3806 return Register();
3807 if ((Subtarget->inMicroMipsMode())) {
3808 return fastEmitInst_ri(MachineInstOpcode: Mips::SRL_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3809 }
3810 if ((Subtarget->inMips16Mode())) {
3811 return fastEmitInst_ri(MachineInstOpcode: Mips::SrlX16, RC: &Mips::CPU16RegsRegClass, Op0, Imm: imm1);
3812 }
3813 if ((Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3814 return fastEmitInst_ri(MachineInstOpcode: Mips::SRL, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3815 }
3816 return Register();
3817}
3818
3819Register fastEmit_ISD_SRL_ri_Predicate_immZExt5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3820 switch (VT.SimpleTy) {
3821 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt5(RetVT, Op0, imm1);
3822 default: return Register();
3823 }
3824}
3825
3826// Top-level FastEmit function.
3827
3828Register fastEmit_ri_Predicate_immZExt5(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
3829 switch (Opcode) {
3830 case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
3831 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
3832 case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
3833 case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt5(VT, RetVT, Op0, imm1);
3834 default: return Register();
3835 }
3836}
3837
3838// FastEmit functions for ISD::ROTR.
3839
3840Register fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, Register Op0, uint64_t imm1) {
3841 if (RetVT.SimpleTy != MVT::i64)
3842 return Register();
3843 if ((Subtarget->hasMips64r2()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3844 return fastEmitInst_ri(MachineInstOpcode: Mips::DROTR, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
3845 }
3846 return Register();
3847}
3848
3849Register fastEmit_ISD_ROTR_ri_Predicate_immZExt6(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3850 switch (VT.SimpleTy) {
3851 case MVT::i64: return fastEmit_ISD_ROTR_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
3852 default: return Register();
3853 }
3854}
3855
3856// FastEmit functions for ISD::SHL.
3857
3858Register fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, Register Op0, uint64_t imm1) {
3859 if (RetVT.SimpleTy != MVT::i64)
3860 return Register();
3861 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3862 return fastEmitInst_ri(MachineInstOpcode: Mips::DSLL, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
3863 }
3864 return Register();
3865}
3866
3867Register fastEmit_ISD_SHL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3868 switch (VT.SimpleTy) {
3869 case MVT::i64: return fastEmit_ISD_SHL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
3870 default: return Register();
3871 }
3872}
3873
3874// FastEmit functions for ISD::SRA.
3875
3876Register fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, Register Op0, uint64_t imm1) {
3877 if (RetVT.SimpleTy != MVT::i64)
3878 return Register();
3879 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3880 return fastEmitInst_ri(MachineInstOpcode: Mips::DSRA, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
3881 }
3882 return Register();
3883}
3884
3885Register fastEmit_ISD_SRA_ri_Predicate_immZExt6(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3886 switch (VT.SimpleTy) {
3887 case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
3888 default: return Register();
3889 }
3890}
3891
3892// FastEmit functions for ISD::SRL.
3893
3894Register fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(MVT RetVT, Register Op0, uint64_t imm1) {
3895 if (RetVT.SimpleTy != MVT::i64)
3896 return Register();
3897 if ((Subtarget->hasMips3()) && (Subtarget->hasStandardEncoding()) && (!Subtarget->inMicroMipsMode())) {
3898 return fastEmitInst_ri(MachineInstOpcode: Mips::DSRL, RC: &Mips::GPR64RegClass, Op0, Imm: imm1);
3899 }
3900 return Register();
3901}
3902
3903Register fastEmit_ISD_SRL_ri_Predicate_immZExt6(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3904 switch (VT.SimpleTy) {
3905 case MVT::i64: return fastEmit_ISD_SRL_MVT_i64_ri_Predicate_immZExt6(RetVT, Op0, imm1);
3906 default: return Register();
3907 }
3908}
3909
3910// Top-level FastEmit function.
3911
3912Register fastEmit_ri_Predicate_immZExt6(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
3913 switch (Opcode) {
3914 case ISD::ROTR: return fastEmit_ISD_ROTR_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
3915 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
3916 case ISD::SRA: return fastEmit_ISD_SRA_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
3917 case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt6(VT, RetVT, Op0, imm1);
3918 default: return Register();
3919 }
3920}
3921
3922// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
3923
3924Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(MVT RetVT, Register Op0, uint64_t imm1) {
3925 if (RetVT.SimpleTy != MVT::f32)
3926 return Register();
3927 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3928 return fastEmitInst_ri(MachineInstOpcode: Mips::COPY_FW_PSEUDO, RC: &Mips::FGR32RegClass, Op0, Imm: imm1);
3929 }
3930 return Register();
3931}
3932
3933Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3934 switch (VT.SimpleTy) {
3935 case MVT::v4f32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4f32_ri_Predicate_immZExt2Ptr(RetVT, Op0, imm1);
3936 default: return Register();
3937 }
3938}
3939
3940// Top-level FastEmit function.
3941
3942Register fastEmit_ri_Predicate_immZExt2Ptr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
3943 switch (Opcode) {
3944 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt2Ptr(VT, RetVT, Op0, imm1);
3945 default: return Register();
3946 }
3947}
3948
3949// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
3950
3951Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(MVT RetVT, Register Op0, uint64_t imm1) {
3952 if (RetVT.SimpleTy != MVT::f64)
3953 return Register();
3954 if ((Subtarget->hasMSA()) && (Subtarget->hasStandardEncoding())) {
3955 return fastEmitInst_ri(MachineInstOpcode: Mips::COPY_FD_PSEUDO, RC: &Mips::FGR64RegClass, Op0, Imm: imm1);
3956 }
3957 return Register();
3958}
3959
3960Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3961 switch (VT.SimpleTy) {
3962 case MVT::v2f64: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v2f64_ri_Predicate_immZExt1Ptr(RetVT, Op0, imm1);
3963 default: return Register();
3964 }
3965}
3966
3967// Top-level FastEmit function.
3968
3969Register fastEmit_ri_Predicate_immZExt1Ptr(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
3970 switch (Opcode) {
3971 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt1Ptr(VT, RetVT, Op0, imm1);
3972 default: return Register();
3973 }
3974}
3975
3976// FastEmit functions for ISD::EXTRACT_VECTOR_ELT.
3977
3978Register fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(MVT RetVT, Register Op0, uint64_t imm1) {
3979 if (RetVT.SimpleTy != MVT::i32)
3980 return Register();
3981 if ((Subtarget->hasMSA())) {
3982 return fastEmitInst_ri(MachineInstOpcode: Mips::COPY_S_W, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
3983 }
3984 return Register();
3985}
3986
3987Register fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
3988 switch (VT.SimpleTy) {
3989 case MVT::v4i32: return fastEmit_ISD_EXTRACT_VECTOR_ELT_MVT_v4i32_ri_Predicate_immZExt4(RetVT, Op0, imm1);
3990 default: return Register();
3991 }
3992}
3993
3994// Top-level FastEmit function.
3995
3996Register fastEmit_ri_Predicate_immZExt4(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
3997 switch (Opcode) {
3998 case ISD::EXTRACT_VECTOR_ELT: return fastEmit_ISD_EXTRACT_VECTOR_ELT_ri_Predicate_immZExt4(VT, RetVT, Op0, imm1);
3999 default: return Register();
4000 }
4001}
4002
4003// FastEmit functions for ISD::ADD.
4004
4005Register fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(MVT RetVT, Register Op0, uint64_t imm1) {
4006 if (RetVT.SimpleTy != MVT::i32)
4007 return Register();
4008 if ((Subtarget->inMicroMipsMode())) {
4009 return fastEmitInst_ri(MachineInstOpcode: Mips::ADDIUR2_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4010 }
4011 return Register();
4012}
4013
4014Register fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4015 switch (VT.SimpleTy) {
4016 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddiur2(RetVT, Op0, imm1);
4017 default: return Register();
4018 }
4019}
4020
4021// Top-level FastEmit function.
4022
4023Register fastEmit_ri_Predicate_immSExtAddiur2(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4024 switch (Opcode) {
4025 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddiur2(VT, RetVT, Op0, imm1);
4026 default: return Register();
4027 }
4028}
4029
4030// FastEmit functions for ISD::ADD.
4031
4032Register fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(MVT RetVT, Register Op0, uint64_t imm1) {
4033 if (RetVT.SimpleTy != MVT::i32)
4034 return Register();
4035 if ((Subtarget->inMicroMipsMode())) {
4036 return fastEmitInst_ri(MachineInstOpcode: Mips::ADDIUS5_MM, RC: &Mips::GPR32RegClass, Op0, Imm: imm1);
4037 }
4038 return Register();
4039}
4040
4041Register fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4042 switch (VT.SimpleTy) {
4043 case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_immSExtAddius5(RetVT, Op0, imm1);
4044 default: return Register();
4045 }
4046}
4047
4048// Top-level FastEmit function.
4049
4050Register fastEmit_ri_Predicate_immSExtAddius5(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4051 switch (Opcode) {
4052 case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_immSExtAddius5(VT, RetVT, Op0, imm1);
4053 default: return Register();
4054 }
4055}
4056
4057// FastEmit functions for ISD::AND.
4058
4059Register fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(MVT RetVT, Register Op0, uint64_t imm1) {
4060 if (RetVT.SimpleTy != MVT::i32)
4061 return Register();
4062 if ((Subtarget->hasMips32r6()) && (Subtarget->inMicroMipsMode())) {
4063 return fastEmitInst_ri(MachineInstOpcode: Mips::ANDI16_MMR6, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4064 }
4065 if ((Subtarget->inMicroMipsMode())) {
4066 return fastEmitInst_ri(MachineInstOpcode: Mips::ANDI16_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4067 }
4068 return Register();
4069}
4070
4071Register fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4072 switch (VT.SimpleTy) {
4073 case MVT::i32: return fastEmit_ISD_AND_MVT_i32_ri_Predicate_immZExtAndi16(RetVT, Op0, imm1);
4074 default: return Register();
4075 }
4076}
4077
4078// Top-level FastEmit function.
4079
4080Register fastEmit_ri_Predicate_immZExtAndi16(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4081 switch (Opcode) {
4082 case ISD::AND: return fastEmit_ISD_AND_ri_Predicate_immZExtAndi16(VT, RetVT, Op0, imm1);
4083 default: return Register();
4084 }
4085}
4086
4087// FastEmit functions for ISD::SHL.
4088
4089Register fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, Register Op0, uint64_t imm1) {
4090 if (RetVT.SimpleTy != MVT::i32)
4091 return Register();
4092 if ((Subtarget->inMicroMipsMode())) {
4093 return fastEmitInst_ri(MachineInstOpcode: Mips::SLL16_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4094 }
4095 return Register();
4096}
4097
4098Register fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4099 switch (VT.SimpleTy) {
4100 case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, imm1);
4101 default: return Register();
4102 }
4103}
4104
4105// FastEmit functions for ISD::SRL.
4106
4107Register fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(MVT RetVT, Register Op0, uint64_t imm1) {
4108 if (RetVT.SimpleTy != MVT::i32)
4109 return Register();
4110 if ((Subtarget->inMicroMipsMode())) {
4111 return fastEmitInst_ri(MachineInstOpcode: Mips::SRL16_MM, RC: &Mips::GPRMM16RegClass, Op0, Imm: imm1);
4112 }
4113 return Register();
4114}
4115
4116Register fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, Register Op0, uint64_t imm1) {
4117 switch (VT.SimpleTy) {
4118 case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_ri_Predicate_immZExt2Shift(RetVT, Op0, imm1);
4119 default: return Register();
4120 }
4121}
4122
4123// Top-level FastEmit function.
4124
4125Register fastEmit_ri_Predicate_immZExt2Shift(MVT VT, MVT RetVT, unsigned Opcode, Register Op0, uint64_t imm1) {
4126 switch (Opcode) {
4127 case ISD::SHL: return fastEmit_ISD_SHL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, imm1);
4128 case ISD::SRL: return fastEmit_ISD_SRL_ri_Predicate_immZExt2Shift(VT, RetVT, Op0, imm1);
4129 default: return Register();
4130 }
4131}
4132
4133// FastEmit functions for ISD::Constant.
4134
4135Register fastEmit_ISD_Constant_MVT_i32_i(MVT RetVT, uint64_t imm0) {
4136 if (RetVT.SimpleTy != MVT::i32)
4137 return Register();
4138 if ((Subtarget->inMips16Mode())) {
4139 return fastEmitInst_i(MachineInstOpcode: Mips::LwConstant32, RC: &Mips::CPU16RegsRegClass, Imm: imm0);
4140 }
4141 return Register();
4142}
4143
4144Register fastEmit_ISD_Constant_i(MVT VT, MVT RetVT, uint64_t imm0) {
4145 switch (VT.SimpleTy) {
4146 case MVT::i32: return fastEmit_ISD_Constant_MVT_i32_i(RetVT, imm0);
4147 default: return Register();
4148 }
4149}
4150
4151// Top-level FastEmit function.
4152
4153Register fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t imm0) override {
4154 switch (Opcode) {
4155 case ISD::Constant: return fastEmit_ISD_Constant_i(VT, RetVT, imm0);
4156 default: return Register();
4157 }
4158}
4159
4160