1//===- MipsFastISel.cpp - Mips FastISel implementation --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file defines the MIPS-specific support for the FastISel class.
11/// Some of the target-specific code is generated by tablegen in the file
12/// MipsGenFastISel.inc, which is #included here.
13///
14//===----------------------------------------------------------------------===//
15
16#include "MCTargetDesc/MipsABIInfo.h"
17#include "MCTargetDesc/MipsBaseInfo.h"
18#include "MipsCCState.h"
19#include "MipsISelLowering.h"
20#include "MipsInstrInfo.h"
21#include "MipsMachineFunction.h"
22#include "MipsSubtarget.h"
23#include "llvm/ADT/APInt.h"
24#include "llvm/ADT/DenseMap.h"
25#include "llvm/ADT/SmallVector.h"
26#include "llvm/Analysis/TargetLibraryInfo.h"
27#include "llvm/CodeGen/CallingConvLower.h"
28#include "llvm/CodeGen/FastISel.h"
29#include "llvm/CodeGen/FunctionLoweringInfo.h"
30#include "llvm/CodeGen/ISDOpcodes.h"
31#include "llvm/CodeGen/MachineBasicBlock.h"
32#include "llvm/CodeGen/MachineFrameInfo.h"
33#include "llvm/CodeGen/MachineInstrBuilder.h"
34#include "llvm/CodeGen/MachineMemOperand.h"
35#include "llvm/CodeGen/MachineRegisterInfo.h"
36#include "llvm/CodeGen/TargetInstrInfo.h"
37#include "llvm/CodeGen/TargetLowering.h"
38#include "llvm/CodeGen/ValueTypes.h"
39#include "llvm/CodeGenTypes/MachineValueType.h"
40#include "llvm/IR/Attributes.h"
41#include "llvm/IR/CallingConv.h"
42#include "llvm/IR/Constant.h"
43#include "llvm/IR/Constants.h"
44#include "llvm/IR/DataLayout.h"
45#include "llvm/IR/Function.h"
46#include "llvm/IR/GetElementPtrTypeIterator.h"
47#include "llvm/IR/GlobalValue.h"
48#include "llvm/IR/GlobalVariable.h"
49#include "llvm/IR/InstrTypes.h"
50#include "llvm/IR/Instruction.h"
51#include "llvm/IR/Instructions.h"
52#include "llvm/IR/IntrinsicInst.h"
53#include "llvm/IR/Operator.h"
54#include "llvm/IR/Type.h"
55#include "llvm/IR/User.h"
56#include "llvm/IR/Value.h"
57#include "llvm/MC/MCContext.h"
58#include "llvm/MC/MCInstrDesc.h"
59#include "llvm/MC/MCSymbol.h"
60#include "llvm/Support/Casting.h"
61#include "llvm/Support/Compiler.h"
62#include "llvm/Support/Debug.h"
63#include "llvm/Support/ErrorHandling.h"
64#include "llvm/Support/MathExtras.h"
65#include "llvm/Support/raw_ostream.h"
66#include <algorithm>
67#include <array>
68#include <cassert>
69#include <cstdint>
70
71#define DEBUG_TYPE "mips-fastisel"
72
73using namespace llvm;
74
75extern cl::opt<bool> EmitJalrReloc;
76extern cl::opt<bool> NoZeroDivCheck;
77
78namespace {
79
80class MipsFastISel final : public FastISel {
81
82 // All possible address modes.
83 class Address {
84 public:
85 enum BaseKind { RegBase, FrameIndexBase };
86
87 private:
88 BaseKind Kind = RegBase;
89 union {
90 unsigned Reg;
91 int FI;
92 } Base;
93
94 int64_t Offset = 0;
95
96 const GlobalValue *GV = nullptr;
97
98 public:
99 // Innocuous defaults for our address.
100 Address() { Base.Reg = 0; }
101
102 void setKind(BaseKind K) { Kind = K; }
103 BaseKind getKind() const { return Kind; }
104 bool isRegBase() const { return Kind == RegBase; }
105 bool isFIBase() const { return Kind == FrameIndexBase; }
106
107 void setReg(unsigned Reg) {
108 assert(isRegBase() && "Invalid base register access!");
109 Base.Reg = Reg;
110 }
111
112 unsigned getReg() const {
113 assert(isRegBase() && "Invalid base register access!");
114 return Base.Reg;
115 }
116
117 void setFI(unsigned FI) {
118 assert(isFIBase() && "Invalid base frame index access!");
119 Base.FI = FI;
120 }
121
122 unsigned getFI() const {
123 assert(isFIBase() && "Invalid base frame index access!");
124 return Base.FI;
125 }
126
127 void setOffset(int64_t Offset_) { Offset = Offset_; }
128 int64_t getOffset() const { return Offset; }
129 void setGlobalValue(const GlobalValue *G) { GV = G; }
130 const GlobalValue *getGlobalValue() { return GV; }
131 };
132
133 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
134 /// make the right decision when generating code for different targets.
135 const TargetMachine &TM;
136 const MipsSubtarget *Subtarget;
137 const TargetInstrInfo &TII;
138 const TargetLowering &TLI;
139 MipsFunctionInfo *MFI;
140
141 // Convenience variables to avoid some queries.
142 LLVMContext *Context;
143
144 bool fastLowerArguments() override;
145 bool fastLowerCall(CallLoweringInfo &CLI) override;
146 bool fastLowerIntrinsicCall(const IntrinsicInst *II) override;
147
148 bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle
149 // floating point but not reject doing fast-isel in other
150 // situations
151
152private:
153 // Selection routines.
154 bool selectLogicalOp(const Instruction *I);
155 bool selectLoad(const Instruction *I);
156 bool selectStore(const Instruction *I);
157 bool selectBranch(const Instruction *I);
158 bool selectSelect(const Instruction *I);
159 bool selectCmp(const Instruction *I);
160 bool selectFPExt(const Instruction *I);
161 bool selectFPTrunc(const Instruction *I);
162 bool selectFPToInt(const Instruction *I, bool IsSigned);
163 bool selectRet(const Instruction *I);
164 bool selectTrunc(const Instruction *I);
165 bool selectIntExt(const Instruction *I);
166 bool selectShift(const Instruction *I);
167 bool selectDivRem(const Instruction *I, unsigned ISDOpcode);
168
169 // Utility helper routines.
170 bool isTypeLegal(Type *Ty, MVT &VT);
171 bool isTypeSupported(Type *Ty, MVT &VT);
172 bool isLoadTypeLegal(Type *Ty, MVT &VT);
173 bool computeAddress(const Value *Obj, Address &Addr);
174 bool computeCallAddress(const Value *V, Address &Addr);
175 void simplifyAddress(Address &Addr);
176
177 // Emit helper routines.
178 bool emitCmp(unsigned DestReg, const CmpInst *CI);
179 bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr);
180 bool emitStore(MVT VT, unsigned SrcReg, Address &Addr);
181 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
182 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
183
184 bool IsZExt);
185 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
186
187 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
188 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
189 unsigned DestReg);
190 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
191 unsigned DestReg);
192
193 unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
194
195 unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
196 const Value *RHS);
197
198 unsigned materializeFP(const ConstantFP *CFP, MVT VT);
199 unsigned materializeGV(const GlobalValue *GV, MVT VT);
200 unsigned materializeInt(const Constant *C, MVT VT);
201 unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
202 unsigned materializeExternalCallSym(MCSymbol *Syn);
203
204 MachineInstrBuilder emitInst(unsigned Opc) {
205 return BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc));
206 }
207
208 MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) {
209 return BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc),
210 DestReg: DstReg);
211 }
212
213 MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
214 unsigned MemReg, int64_t MemOffset) {
215 return emitInst(Opc).addReg(RegNo: SrcReg).addReg(RegNo: MemReg).addImm(Val: MemOffset);
216 }
217
218 MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg,
219 unsigned MemReg, int64_t MemOffset) {
220 return emitInst(Opc, DstReg).addReg(RegNo: MemReg).addImm(Val: MemOffset);
221 }
222
223 unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
224 const TargetRegisterClass *RC,
225 unsigned Op0, unsigned Op1);
226
227 // for some reason, this default is not generated by tablegen
228 // so we explicitly generate it here.
229 unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
230 unsigned Op0, uint64_t imm1, uint64_t imm2,
231 unsigned Op3) {
232 return 0;
233 }
234
235 // Call handling routines.
236private:
237 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
238 bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
239 unsigned &NumBytes);
240 bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
241
242 const MipsABIInfo &getABI() const { return Subtarget->getABI(); }
243
244public:
245 // Backend specific FastISel code.
246 explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
247 const TargetLibraryInfo *libInfo,
248 const LibcallLoweringInfo *libcallLowering)
249 : FastISel(funcInfo, libInfo, libcallLowering),
250 TM(funcInfo.MF->getTarget()),
251 Subtarget(&funcInfo.MF->getSubtarget<MipsSubtarget>()),
252 TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
253 MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
254 Context = &funcInfo.Fn->getContext();
255 UnsupportedFPMode = Subtarget->isFP64bit() || Subtarget->useSoftFloat();
256 }
257
258 Register fastMaterializeAlloca(const AllocaInst *AI) override;
259 Register fastMaterializeConstant(const Constant *C) override;
260 bool fastSelectInstruction(const Instruction *I) override;
261
262#include "MipsGenFastISel.inc"
263};
264
265} // end anonymous namespace
266
267[[maybe_unused]] static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT,
268 CCValAssign::LocInfo LocInfo,
269 ISD::ArgFlagsTy ArgFlags, Type *OrigTy,
270 CCState &State);
271
272static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT,
273 CCValAssign::LocInfo LocInfo,
274 ISD::ArgFlagsTy ArgFlags, Type *OrigTy,
275 CCState &State) {
276 llvm_unreachable("should not be called");
277}
278
279static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT,
280 CCValAssign::LocInfo LocInfo,
281 ISD::ArgFlagsTy ArgFlags, Type *OrigTy,
282 CCState &State) {
283 llvm_unreachable("should not be called");
284}
285
286#define GET_CALLING_CONV_IMPL
287#include "MipsGenCallingConv.inc"
288
289CCAssignFn *MipsFastISel::CCAssignFnForCall(CallingConv::ID CC) const {
290 return CC_MipsO32;
291}
292
293unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
294 const Value *LHS, const Value *RHS) {
295 // Canonicalize immediates to the RHS first.
296 if (isa<ConstantInt>(Val: LHS) && !isa<ConstantInt>(Val: RHS))
297 std::swap(a&: LHS, b&: RHS);
298
299 unsigned Opc;
300 switch (ISDOpc) {
301 case ISD::AND:
302 Opc = Mips::AND;
303 break;
304 case ISD::OR:
305 Opc = Mips::OR;
306 break;
307 case ISD::XOR:
308 Opc = Mips::XOR;
309 break;
310 default:
311 llvm_unreachable("unexpected opcode");
312 }
313
314 Register LHSReg = getRegForValue(V: LHS);
315 if (!LHSReg)
316 return 0;
317
318 unsigned RHSReg;
319 if (const auto *C = dyn_cast<ConstantInt>(Val: RHS))
320 RHSReg = materializeInt(C, VT: MVT::i32);
321 else
322 RHSReg = getRegForValue(V: RHS);
323 if (!RHSReg)
324 return 0;
325
326 Register ResultReg = createResultReg(RC: &Mips::GPR32RegClass);
327 if (!ResultReg)
328 return 0;
329
330 emitInst(Opc, DstReg: ResultReg).addReg(RegNo: LHSReg).addReg(RegNo: RHSReg);
331 return ResultReg;
332}
333
334Register MipsFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
335 assert(TLI.getValueType(DL, AI->getType(), true) == MVT::i32 &&
336 "Alloca should always return a pointer.");
337
338 auto SI = FuncInfo.StaticAllocaMap.find(Val: AI);
339
340 if (SI != FuncInfo.StaticAllocaMap.end()) {
341 Register ResultReg = createResultReg(RC: &Mips::GPR32RegClass);
342 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Mips::LEA_ADDiu),
343 DestReg: ResultReg)
344 .addFrameIndex(Idx: SI->second)
345 .addImm(Val: 0);
346 return ResultReg;
347 }
348
349 return Register();
350}
351
352unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
353 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
354 return 0;
355 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
356 const ConstantInt *CI = cast<ConstantInt>(Val: C);
357 return materialize32BitInt(Imm: CI->getZExtValue(), RC);
358}
359
360unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
361 const TargetRegisterClass *RC) {
362 Register ResultReg = createResultReg(RC);
363
364 if (isInt<16>(x: Imm)) {
365 unsigned Opc = Mips::ADDiu;
366 emitInst(Opc, DstReg: ResultReg).addReg(RegNo: Mips::ZERO).addImm(Val: Imm);
367 return ResultReg;
368 } else if (isUInt<16>(x: Imm)) {
369 emitInst(Opc: Mips::ORi, DstReg: ResultReg).addReg(RegNo: Mips::ZERO).addImm(Val: Imm);
370 return ResultReg;
371 }
372 unsigned Lo = Imm & 0xFFFF;
373 unsigned Hi = (Imm >> 16) & 0xFFFF;
374 if (Lo) {
375 // Both Lo and Hi have nonzero bits.
376 Register TmpReg = createResultReg(RC);
377 emitInst(Opc: Mips::LUi, DstReg: TmpReg).addImm(Val: Hi);
378 emitInst(Opc: Mips::ORi, DstReg: ResultReg).addReg(RegNo: TmpReg).addImm(Val: Lo);
379 } else {
380 emitInst(Opc: Mips::LUi, DstReg: ResultReg).addImm(Val: Hi);
381 }
382 return ResultReg;
383}
384
385unsigned MipsFastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
386 if (UnsupportedFPMode)
387 return 0;
388 int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
389 if (VT == MVT::f32) {
390 const TargetRegisterClass *RC = &Mips::FGR32RegClass;
391 Register DestReg = createResultReg(RC);
392 unsigned TempReg = materialize32BitInt(Imm, RC: &Mips::GPR32RegClass);
393 emitInst(Opc: Mips::MTC1, DstReg: DestReg).addReg(RegNo: TempReg);
394 return DestReg;
395 } else if (VT == MVT::f64) {
396 const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
397 Register DestReg = createResultReg(RC);
398 unsigned TempReg1 = materialize32BitInt(Imm: Imm >> 32, RC: &Mips::GPR32RegClass);
399 unsigned TempReg2 =
400 materialize32BitInt(Imm: Imm & 0xFFFFFFFF, RC: &Mips::GPR32RegClass);
401 emitInst(Opc: Mips::BuildPairF64, DstReg: DestReg).addReg(RegNo: TempReg2).addReg(RegNo: TempReg1);
402 return DestReg;
403 }
404 return 0;
405}
406
407unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) {
408 // For now 32-bit only.
409 if (VT != MVT::i32)
410 return 0;
411 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
412 Register DestReg = createResultReg(RC);
413 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(Val: GV);
414 bool IsThreadLocal = GVar && GVar->isThreadLocal();
415 // TLS not supported at this time.
416 if (IsThreadLocal)
417 return 0;
418 emitInst(Opc: Mips::LW, DstReg: DestReg)
419 .addReg(RegNo: MFI->getGlobalBaseReg(MF&: *MF))
420 .addGlobalAddress(GV, Offset: 0, TargetFlags: MipsII::MO_GOT);
421 if (GV->hasLocalLinkage()) {
422 Register TempReg = createResultReg(RC);
423 emitInst(Opc: Mips::ADDiu, DstReg: TempReg)
424 .addReg(RegNo: DestReg)
425 .addGlobalAddress(GV, Offset: 0, TargetFlags: MipsII::MO_ABS_LO);
426 DestReg = TempReg;
427 }
428 return DestReg;
429}
430
431unsigned MipsFastISel::materializeExternalCallSym(MCSymbol *Sym) {
432 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
433 Register DestReg = createResultReg(RC);
434 emitInst(Opc: Mips::LW, DstReg: DestReg)
435 .addReg(RegNo: MFI->getGlobalBaseReg(MF&: *MF))
436 .addSym(Sym, TargetFlags: MipsII::MO_GOT);
437 return DestReg;
438}
439
440// Materialize a constant into a register, and return the register
441// number (or zero if we failed to handle it).
442Register MipsFastISel::fastMaterializeConstant(const Constant *C) {
443 EVT CEVT = TLI.getValueType(DL, Ty: C->getType(), AllowUnknown: true);
444
445 // Only handle simple types.
446 if (!CEVT.isSimple())
447 return Register();
448 MVT VT = CEVT.getSimpleVT();
449
450 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Val: C))
451 return (UnsupportedFPMode) ? 0 : materializeFP(CFP, VT);
452 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(Val: C))
453 return materializeGV(GV, VT);
454 else if (isa<ConstantInt>(Val: C))
455 return materializeInt(C, VT);
456
457 return Register();
458}
459
460bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {
461 const User *U = nullptr;
462 unsigned Opcode = Instruction::UserOp1;
463 if (const Instruction *I = dyn_cast<Instruction>(Val: Obj)) {
464 // Don't walk into other basic blocks unless the object is an alloca from
465 // another block, otherwise it may not have a virtual register assigned.
466 if (FuncInfo.StaticAllocaMap.count(Val: static_cast<const AllocaInst *>(Obj)) ||
467 FuncInfo.getMBB(BB: I->getParent()) == FuncInfo.MBB) {
468 Opcode = I->getOpcode();
469 U = I;
470 }
471 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Val: Obj)) {
472 Opcode = C->getOpcode();
473 U = C;
474 }
475 switch (Opcode) {
476 default:
477 break;
478 case Instruction::BitCast:
479 // Look through bitcasts.
480 return computeAddress(Obj: U->getOperand(i: 0), Addr);
481 case Instruction::GetElementPtr: {
482 Address SavedAddr = Addr;
483 int64_t TmpOffset = Addr.getOffset();
484 // Iterate through the GEP folding the constants into offsets where
485 // we can.
486 gep_type_iterator GTI = gep_type_begin(GEP: U);
487 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
488 ++i, ++GTI) {
489 const Value *Op = *i;
490 if (StructType *STy = GTI.getStructTypeOrNull()) {
491 const StructLayout *SL = DL.getStructLayout(Ty: STy);
492 unsigned Idx = cast<ConstantInt>(Val: Op)->getZExtValue();
493 TmpOffset += SL->getElementOffset(Idx);
494 } else {
495 uint64_t S = GTI.getSequentialElementStride(DL);
496 while (true) {
497 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Val: Op)) {
498 // Constant-offset addressing.
499 TmpOffset += CI->getSExtValue() * S;
500 break;
501 }
502 if (canFoldAddIntoGEP(GEP: U, Add: Op)) {
503 // A compatible add with a constant operand. Fold the constant.
504 ConstantInt *CI =
505 cast<ConstantInt>(Val: cast<AddOperator>(Val: Op)->getOperand(i_nocapture: 1));
506 TmpOffset += CI->getSExtValue() * S;
507 // Iterate on the other operand.
508 Op = cast<AddOperator>(Val: Op)->getOperand(i_nocapture: 0);
509 continue;
510 }
511 // Unsupported
512 goto unsupported_gep;
513 }
514 }
515 }
516 // Try to grab the base operand now.
517 Addr.setOffset(TmpOffset);
518 if (computeAddress(Obj: U->getOperand(i: 0), Addr))
519 return true;
520 // We failed, restore everything and try the other options.
521 Addr = SavedAddr;
522 unsupported_gep:
523 break;
524 }
525 case Instruction::Alloca: {
526 const AllocaInst *AI = cast<AllocaInst>(Val: Obj);
527 auto SI = FuncInfo.StaticAllocaMap.find(Val: AI);
528 if (SI != FuncInfo.StaticAllocaMap.end()) {
529 Addr.setKind(Address::FrameIndexBase);
530 Addr.setFI(SI->second);
531 return true;
532 }
533 break;
534 }
535 }
536 Addr.setReg(getRegForValue(V: Obj));
537 return Addr.getReg() != 0;
538}
539
540bool MipsFastISel::computeCallAddress(const Value *V, Address &Addr) {
541 const User *U = nullptr;
542 unsigned Opcode = Instruction::UserOp1;
543
544 if (const auto *I = dyn_cast<Instruction>(Val: V)) {
545 // Check if the value is defined in the same basic block. This information
546 // is crucial to know whether or not folding an operand is valid.
547 if (I->getParent() == FuncInfo.MBB->getBasicBlock()) {
548 Opcode = I->getOpcode();
549 U = I;
550 }
551 } else if (const auto *C = dyn_cast<ConstantExpr>(Val: V)) {
552 Opcode = C->getOpcode();
553 U = C;
554 }
555
556 switch (Opcode) {
557 default:
558 break;
559 case Instruction::BitCast:
560 // Look past bitcasts if its operand is in the same BB.
561 return computeCallAddress(V: U->getOperand(i: 0), Addr);
562 break;
563 case Instruction::IntToPtr:
564 // Look past no-op inttoptrs if its operand is in the same BB.
565 if (TLI.getValueType(DL, Ty: U->getOperand(i: 0)->getType()) ==
566 TLI.getPointerTy(DL))
567 return computeCallAddress(V: U->getOperand(i: 0), Addr);
568 break;
569 case Instruction::PtrToInt:
570 // Look past no-op ptrtoints if its operand is in the same BB.
571 if (TLI.getValueType(DL, Ty: U->getType()) == TLI.getPointerTy(DL))
572 return computeCallAddress(V: U->getOperand(i: 0), Addr);
573 break;
574 }
575
576 if (const GlobalValue *GV = dyn_cast<GlobalValue>(Val: V)) {
577 Addr.setGlobalValue(GV);
578 return true;
579 }
580
581 // If all else fails, try to materialize the value in a register.
582 if (!Addr.getGlobalValue()) {
583 Addr.setReg(getRegForValue(V));
584 return Addr.getReg() != 0;
585 }
586
587 return false;
588}
589
590bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
591 EVT evt = TLI.getValueType(DL, Ty, AllowUnknown: true);
592 // Only handle simple types.
593 if (evt == MVT::Other || !evt.isSimple())
594 return false;
595 VT = evt.getSimpleVT();
596
597 // Handle all legal types, i.e. a register that will directly hold this
598 // value.
599 return TLI.isTypeLegal(VT);
600}
601
602bool MipsFastISel::isTypeSupported(Type *Ty, MVT &VT) {
603 if (Ty->isVectorTy())
604 return false;
605
606 if (isTypeLegal(Ty, VT))
607 return true;
608
609 // If this is a type than can be sign or zero-extended to a basic operation
610 // go ahead and accept it now.
611 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
612 return true;
613
614 return false;
615}
616
617bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
618 if (isTypeLegal(Ty, VT))
619 return true;
620 // We will extend this in a later patch:
621 // If this is a type than can be sign or zero-extended to a basic operation
622 // go ahead and accept it now.
623 if (VT == MVT::i8 || VT == MVT::i16)
624 return true;
625 return false;
626}
627
628// Because of how EmitCmp is called with fast-isel, you can
629// end up with redundant "andi" instructions after the sequences emitted below.
630// We should try and solve this issue in the future.
631//
632bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
633 const Value *Left = CI->getOperand(i_nocapture: 0), *Right = CI->getOperand(i_nocapture: 1);
634 bool IsUnsigned = CI->isUnsigned();
635 unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned);
636 if (LeftReg == 0)
637 return false;
638 unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned);
639 if (RightReg == 0)
640 return false;
641 CmpInst::Predicate P = CI->getPredicate();
642
643 switch (P) {
644 default:
645 return false;
646 case CmpInst::ICMP_EQ: {
647 Register TempReg = createResultReg(RC: &Mips::GPR32RegClass);
648 emitInst(Opc: Mips::XOR, DstReg: TempReg).addReg(RegNo: LeftReg).addReg(RegNo: RightReg);
649 emitInst(Opc: Mips::SLTiu, DstReg: ResultReg).addReg(RegNo: TempReg).addImm(Val: 1);
650 break;
651 }
652 case CmpInst::ICMP_NE: {
653 Register TempReg = createResultReg(RC: &Mips::GPR32RegClass);
654 emitInst(Opc: Mips::XOR, DstReg: TempReg).addReg(RegNo: LeftReg).addReg(RegNo: RightReg);
655 emitInst(Opc: Mips::SLTu, DstReg: ResultReg).addReg(RegNo: Mips::ZERO).addReg(RegNo: TempReg);
656 break;
657 }
658 case CmpInst::ICMP_UGT:
659 emitInst(Opc: Mips::SLTu, DstReg: ResultReg).addReg(RegNo: RightReg).addReg(RegNo: LeftReg);
660 break;
661 case CmpInst::ICMP_ULT:
662 emitInst(Opc: Mips::SLTu, DstReg: ResultReg).addReg(RegNo: LeftReg).addReg(RegNo: RightReg);
663 break;
664 case CmpInst::ICMP_UGE: {
665 Register TempReg = createResultReg(RC: &Mips::GPR32RegClass);
666 emitInst(Opc: Mips::SLTu, DstReg: TempReg).addReg(RegNo: LeftReg).addReg(RegNo: RightReg);
667 emitInst(Opc: Mips::XORi, DstReg: ResultReg).addReg(RegNo: TempReg).addImm(Val: 1);
668 break;
669 }
670 case CmpInst::ICMP_ULE: {
671 Register TempReg = createResultReg(RC: &Mips::GPR32RegClass);
672 emitInst(Opc: Mips::SLTu, DstReg: TempReg).addReg(RegNo: RightReg).addReg(RegNo: LeftReg);
673 emitInst(Opc: Mips::XORi, DstReg: ResultReg).addReg(RegNo: TempReg).addImm(Val: 1);
674 break;
675 }
676 case CmpInst::ICMP_SGT:
677 emitInst(Opc: Mips::SLT, DstReg: ResultReg).addReg(RegNo: RightReg).addReg(RegNo: LeftReg);
678 break;
679 case CmpInst::ICMP_SLT:
680 emitInst(Opc: Mips::SLT, DstReg: ResultReg).addReg(RegNo: LeftReg).addReg(RegNo: RightReg);
681 break;
682 case CmpInst::ICMP_SGE: {
683 Register TempReg = createResultReg(RC: &Mips::GPR32RegClass);
684 emitInst(Opc: Mips::SLT, DstReg: TempReg).addReg(RegNo: LeftReg).addReg(RegNo: RightReg);
685 emitInst(Opc: Mips::XORi, DstReg: ResultReg).addReg(RegNo: TempReg).addImm(Val: 1);
686 break;
687 }
688 case CmpInst::ICMP_SLE: {
689 Register TempReg = createResultReg(RC: &Mips::GPR32RegClass);
690 emitInst(Opc: Mips::SLT, DstReg: TempReg).addReg(RegNo: RightReg).addReg(RegNo: LeftReg);
691 emitInst(Opc: Mips::XORi, DstReg: ResultReg).addReg(RegNo: TempReg).addImm(Val: 1);
692 break;
693 }
694 case CmpInst::FCMP_OEQ:
695 case CmpInst::FCMP_UNE:
696 case CmpInst::FCMP_OLT:
697 case CmpInst::FCMP_OLE:
698 case CmpInst::FCMP_OGT:
699 case CmpInst::FCMP_OGE: {
700 if (UnsupportedFPMode)
701 return false;
702 bool IsFloat = Left->getType()->isFloatTy();
703 bool IsDouble = Left->getType()->isDoubleTy();
704 if (!IsFloat && !IsDouble)
705 return false;
706 unsigned Opc, CondMovOpc;
707 switch (P) {
708 case CmpInst::FCMP_OEQ:
709 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
710 CondMovOpc = Mips::MOVT_I;
711 break;
712 case CmpInst::FCMP_UNE:
713 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
714 CondMovOpc = Mips::MOVF_I;
715 break;
716 case CmpInst::FCMP_OLT:
717 Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32;
718 CondMovOpc = Mips::MOVT_I;
719 break;
720 case CmpInst::FCMP_OLE:
721 Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32;
722 CondMovOpc = Mips::MOVT_I;
723 break;
724 case CmpInst::FCMP_OGT:
725 Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32;
726 CondMovOpc = Mips::MOVF_I;
727 break;
728 case CmpInst::FCMP_OGE:
729 Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32;
730 CondMovOpc = Mips::MOVF_I;
731 break;
732 default:
733 llvm_unreachable("Only switching of a subset of CCs.");
734 }
735 Register RegWithZero = createResultReg(RC: &Mips::GPR32RegClass);
736 Register RegWithOne = createResultReg(RC: &Mips::GPR32RegClass);
737 emitInst(Opc: Mips::ADDiu, DstReg: RegWithZero).addReg(RegNo: Mips::ZERO).addImm(Val: 0);
738 emitInst(Opc: Mips::ADDiu, DstReg: RegWithOne).addReg(RegNo: Mips::ZERO).addImm(Val: 1);
739 emitInst(Opc).addReg(RegNo: Mips::FCC0, Flags: RegState::Define).addReg(RegNo: LeftReg)
740 .addReg(RegNo: RightReg);
741 emitInst(Opc: CondMovOpc, DstReg: ResultReg)
742 .addReg(RegNo: RegWithOne)
743 .addReg(RegNo: Mips::FCC0)
744 .addReg(RegNo: RegWithZero);
745 break;
746 }
747 }
748 return true;
749}
750
751bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr) {
752 //
753 // more cases will be handled here in following patches.
754 //
755 unsigned Opc;
756 switch (VT.SimpleTy) {
757 case MVT::i32:
758 ResultReg = createResultReg(RC: &Mips::GPR32RegClass);
759 Opc = Mips::LW;
760 break;
761 case MVT::i16:
762 ResultReg = createResultReg(RC: &Mips::GPR32RegClass);
763 Opc = Mips::LHu;
764 break;
765 case MVT::i8:
766 ResultReg = createResultReg(RC: &Mips::GPR32RegClass);
767 Opc = Mips::LBu;
768 break;
769 case MVT::f32:
770 if (UnsupportedFPMode)
771 return false;
772 ResultReg = createResultReg(RC: &Mips::FGR32RegClass);
773 Opc = Mips::LWC1;
774 break;
775 case MVT::f64:
776 if (UnsupportedFPMode)
777 return false;
778 ResultReg = createResultReg(RC: &Mips::AFGR64RegClass);
779 Opc = Mips::LDC1;
780 break;
781 default:
782 return false;
783 }
784 if (Addr.isRegBase()) {
785 simplifyAddress(Addr);
786 emitInstLoad(Opc, DstReg: ResultReg, MemReg: Addr.getReg(), MemOffset: Addr.getOffset());
787 return true;
788 }
789 if (Addr.isFIBase()) {
790 unsigned FI = Addr.getFI();
791 int64_t Offset = Addr.getOffset();
792 MachineFrameInfo &MFI = MF->getFrameInfo();
793 MachineMemOperand *MMO = MF->getMachineMemOperand(
794 PtrInfo: MachinePointerInfo::getFixedStack(MF&: *MF, FI), F: MachineMemOperand::MOLoad,
795 Size: MFI.getObjectSize(ObjectIdx: FI), BaseAlignment: Align(4));
796 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc), DestReg: ResultReg)
797 .addFrameIndex(Idx: FI)
798 .addImm(Val: Offset)
799 .addMemOperand(MMO);
800 return true;
801 }
802 return false;
803}
804
805bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr) {
806 //
807 // more cases will be handled here in following patches.
808 //
809 unsigned Opc;
810 switch (VT.SimpleTy) {
811 case MVT::i8:
812 Opc = Mips::SB;
813 break;
814 case MVT::i16:
815 Opc = Mips::SH;
816 break;
817 case MVT::i32:
818 Opc = Mips::SW;
819 break;
820 case MVT::f32:
821 if (UnsupportedFPMode)
822 return false;
823 Opc = Mips::SWC1;
824 break;
825 case MVT::f64:
826 if (UnsupportedFPMode)
827 return false;
828 Opc = Mips::SDC1;
829 break;
830 default:
831 return false;
832 }
833 if (Addr.isRegBase()) {
834 simplifyAddress(Addr);
835 emitInstStore(Opc, SrcReg, MemReg: Addr.getReg(), MemOffset: Addr.getOffset());
836 return true;
837 }
838 if (Addr.isFIBase()) {
839 unsigned FI = Addr.getFI();
840 int64_t Offset = Addr.getOffset();
841 MachineFrameInfo &MFI = MF->getFrameInfo();
842 MachineMemOperand *MMO = MF->getMachineMemOperand(
843 PtrInfo: MachinePointerInfo::getFixedStack(MF&: *MF, FI), F: MachineMemOperand::MOStore,
844 Size: MFI.getObjectSize(ObjectIdx: FI), BaseAlignment: Align(4));
845 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc))
846 .addReg(RegNo: SrcReg)
847 .addFrameIndex(Idx: FI)
848 .addImm(Val: Offset)
849 .addMemOperand(MMO);
850 return true;
851 }
852 return false;
853}
854
855bool MipsFastISel::selectLogicalOp(const Instruction *I) {
856 MVT VT;
857 if (!isTypeSupported(Ty: I->getType(), VT))
858 return false;
859
860 unsigned ResultReg;
861 switch (I->getOpcode()) {
862 default:
863 llvm_unreachable("Unexpected instruction.");
864 case Instruction::And:
865 ResultReg = emitLogicalOp(ISDOpc: ISD::AND, RetVT: VT, LHS: I->getOperand(i: 0), RHS: I->getOperand(i: 1));
866 break;
867 case Instruction::Or:
868 ResultReg = emitLogicalOp(ISDOpc: ISD::OR, RetVT: VT, LHS: I->getOperand(i: 0), RHS: I->getOperand(i: 1));
869 break;
870 case Instruction::Xor:
871 ResultReg = emitLogicalOp(ISDOpc: ISD::XOR, RetVT: VT, LHS: I->getOperand(i: 0), RHS: I->getOperand(i: 1));
872 break;
873 }
874
875 if (!ResultReg)
876 return false;
877
878 updateValueMap(I, Reg: ResultReg);
879 return true;
880}
881
882bool MipsFastISel::selectLoad(const Instruction *I) {
883 const LoadInst *LI = cast<LoadInst>(Val: I);
884
885 // Atomic loads need special handling.
886 if (LI->isAtomic())
887 return false;
888
889 // Verify we have a legal type before going any further.
890 MVT VT;
891 if (!isLoadTypeLegal(Ty: LI->getType(), VT))
892 return false;
893
894 // Underaligned loads need special handling.
895 if (LI->getAlign() < VT.getFixedSizeInBits() / 8 &&
896 !Subtarget->systemSupportsUnalignedAccess())
897 return false;
898
899 // See if we can handle this address.
900 Address Addr;
901 if (!computeAddress(Obj: LI->getOperand(i_nocapture: 0), Addr))
902 return false;
903
904 unsigned ResultReg;
905 if (!emitLoad(VT, ResultReg, Addr))
906 return false;
907 updateValueMap(I: LI, Reg: ResultReg);
908 return true;
909}
910
911bool MipsFastISel::selectStore(const Instruction *I) {
912 const StoreInst *SI = cast<StoreInst>(Val: I);
913
914 Value *Op0 = SI->getOperand(i_nocapture: 0);
915 unsigned SrcReg = 0;
916
917 // Atomic stores need special handling.
918 if (SI->isAtomic())
919 return false;
920
921 // Verify we have a legal type before going any further.
922 MVT VT;
923 if (!isLoadTypeLegal(Ty: SI->getOperand(i_nocapture: 0)->getType(), VT))
924 return false;
925
926 // Underaligned stores need special handling.
927 if (SI->getAlign() < VT.getFixedSizeInBits() / 8 &&
928 !Subtarget->systemSupportsUnalignedAccess())
929 return false;
930
931 // Get the value to be stored into a register.
932 SrcReg = getRegForValue(V: Op0);
933 if (SrcReg == 0)
934 return false;
935
936 // See if we can handle this address.
937 Address Addr;
938 if (!computeAddress(Obj: SI->getOperand(i_nocapture: 1), Addr))
939 return false;
940
941 if (!emitStore(VT, SrcReg, Addr))
942 return false;
943 return true;
944}
945
946// This can cause a redundant sltiu to be generated.
947// FIXME: try and eliminate this in a future patch.
948bool MipsFastISel::selectBranch(const Instruction *I) {
949 const CondBrInst *BI = cast<CondBrInst>(Val: I);
950 MachineBasicBlock *BrBB = FuncInfo.MBB;
951 //
952 // TBB is the basic block for the case where the comparison is true.
953 // FBB is the basic block for the case where the comparison is false.
954 // if (cond) goto TBB
955 // goto FBB
956 // TBB:
957 //
958 MachineBasicBlock *TBB = FuncInfo.getMBB(BB: BI->getSuccessor(i: 0));
959 MachineBasicBlock *FBB = FuncInfo.getMBB(BB: BI->getSuccessor(i: 1));
960
961 // Fold the common case of a conditional branch with a comparison
962 // in the same block.
963 unsigned ZExtCondReg = 0;
964 if (const CmpInst *CI = dyn_cast<CmpInst>(Val: BI->getCondition())) {
965 if (CI->hasOneUse() && CI->getParent() == I->getParent()) {
966 ZExtCondReg = createResultReg(RC: &Mips::GPR32RegClass);
967 if (!emitCmp(ResultReg: ZExtCondReg, CI))
968 return false;
969 }
970 }
971
972 // For the general case, we need to mask with 1.
973 if (ZExtCondReg == 0) {
974 Register CondReg = getRegForValue(V: BI->getCondition());
975 if (CondReg == 0)
976 return false;
977
978 ZExtCondReg = emitIntExt(SrcVT: MVT::i1, SrcReg: CondReg, DestVT: MVT::i32, isZExt: true);
979 if (ZExtCondReg == 0)
980 return false;
981 }
982
983 BuildMI(BB&: *BrBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Mips::BGTZ))
984 .addReg(RegNo: ZExtCondReg)
985 .addMBB(MBB: TBB)
986 .setOperandDead(2); // implicit-def $at
987 finishCondBranch(BranchBB: BI->getParent(), TrueMBB: TBB, FalseMBB: FBB);
988 return true;
989}
990
991bool MipsFastISel::selectCmp(const Instruction *I) {
992 const CmpInst *CI = cast<CmpInst>(Val: I);
993 Register ResultReg = createResultReg(RC: &Mips::GPR32RegClass);
994 if (!emitCmp(ResultReg, CI))
995 return false;
996 updateValueMap(I, Reg: ResultReg);
997 return true;
998}
999
1000// Attempt to fast-select a floating-point extend instruction.
1001bool MipsFastISel::selectFPExt(const Instruction *I) {
1002 if (UnsupportedFPMode)
1003 return false;
1004 Value *Src = I->getOperand(i: 0);
1005 EVT SrcVT = TLI.getValueType(DL, Ty: Src->getType(), AllowUnknown: true);
1006 EVT DestVT = TLI.getValueType(DL, Ty: I->getType(), AllowUnknown: true);
1007
1008 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
1009 return false;
1010
1011 Register SrcReg =
1012 getRegForValue(V: Src); // this must be a 32bit floating point register class
1013 // maybe we should handle this differently
1014 if (!SrcReg)
1015 return false;
1016
1017 Register DestReg = createResultReg(RC: &Mips::AFGR64RegClass);
1018 emitInst(Opc: Mips::CVT_D32_S, DstReg: DestReg).addReg(RegNo: SrcReg);
1019 updateValueMap(I, Reg: DestReg);
1020 return true;
1021}
1022
1023bool MipsFastISel::selectSelect(const Instruction *I) {
1024 assert(isa<SelectInst>(I) && "Expected a select instruction.");
1025
1026 LLVM_DEBUG(dbgs() << "selectSelect\n");
1027
1028 MVT VT;
1029 if (!isTypeSupported(Ty: I->getType(), VT) || UnsupportedFPMode) {
1030 LLVM_DEBUG(
1031 dbgs() << ".. .. gave up (!isTypeSupported || UnsupportedFPMode)\n");
1032 return false;
1033 }
1034
1035 unsigned CondMovOpc;
1036 const TargetRegisterClass *RC;
1037
1038 if (VT.isInteger() && !VT.isVector() && VT.getSizeInBits() <= 32) {
1039 CondMovOpc = Mips::MOVN_I_I;
1040 RC = &Mips::GPR32RegClass;
1041 } else if (VT == MVT::f32) {
1042 CondMovOpc = Mips::MOVN_I_S;
1043 RC = &Mips::FGR32RegClass;
1044 } else if (VT == MVT::f64) {
1045 CondMovOpc = Mips::MOVN_I_D32;
1046 RC = &Mips::AFGR64RegClass;
1047 } else
1048 return false;
1049
1050 const SelectInst *SI = cast<SelectInst>(Val: I);
1051 const Value *Cond = SI->getCondition();
1052 Register Src1Reg = getRegForValue(V: SI->getTrueValue());
1053 Register Src2Reg = getRegForValue(V: SI->getFalseValue());
1054 Register CondReg = getRegForValue(V: Cond);
1055
1056 if (!Src1Reg || !Src2Reg || !CondReg)
1057 return false;
1058
1059 Register ZExtCondReg = createResultReg(RC: &Mips::GPR32RegClass);
1060 if (!ZExtCondReg)
1061 return false;
1062
1063 if (!emitIntExt(SrcVT: MVT::i1, SrcReg: CondReg, DestVT: MVT::i32, DestReg: ZExtCondReg, IsZExt: true))
1064 return false;
1065
1066 Register ResultReg = createResultReg(RC);
1067 Register TempReg = createResultReg(RC);
1068
1069 if (!ResultReg || !TempReg)
1070 return false;
1071
1072 emitInst(Opc: TargetOpcode::COPY, DstReg: TempReg).addReg(RegNo: Src2Reg);
1073 emitInst(Opc: CondMovOpc, DstReg: ResultReg)
1074 .addReg(RegNo: Src1Reg).addReg(RegNo: ZExtCondReg).addReg(RegNo: TempReg);
1075 updateValueMap(I, Reg: ResultReg);
1076 return true;
1077}
1078
1079// Attempt to fast-select a floating-point truncate instruction.
1080bool MipsFastISel::selectFPTrunc(const Instruction *I) {
1081 if (UnsupportedFPMode)
1082 return false;
1083 Value *Src = I->getOperand(i: 0);
1084 EVT SrcVT = TLI.getValueType(DL, Ty: Src->getType(), AllowUnknown: true);
1085 EVT DestVT = TLI.getValueType(DL, Ty: I->getType(), AllowUnknown: true);
1086
1087 if (SrcVT != MVT::f64 || DestVT != MVT::f32)
1088 return false;
1089
1090 Register SrcReg = getRegForValue(V: Src);
1091 if (!SrcReg)
1092 return false;
1093
1094 Register DestReg = createResultReg(RC: &Mips::FGR32RegClass);
1095 if (!DestReg)
1096 return false;
1097
1098 emitInst(Opc: Mips::CVT_S_D32, DstReg: DestReg).addReg(RegNo: SrcReg);
1099 updateValueMap(I, Reg: DestReg);
1100 return true;
1101}
1102
1103// Attempt to fast-select a floating-point-to-integer conversion.
1104bool MipsFastISel::selectFPToInt(const Instruction *I, bool IsSigned) {
1105 if (UnsupportedFPMode)
1106 return false;
1107 MVT DstVT, SrcVT;
1108 if (!IsSigned)
1109 return false; // We don't handle this case yet. There is no native
1110 // instruction for this but it can be synthesized.
1111 Type *DstTy = I->getType();
1112 if (!isTypeLegal(Ty: DstTy, VT&: DstVT))
1113 return false;
1114
1115 if (DstVT != MVT::i32)
1116 return false;
1117
1118 Value *Src = I->getOperand(i: 0);
1119 Type *SrcTy = Src->getType();
1120 if (!isTypeLegal(Ty: SrcTy, VT&: SrcVT))
1121 return false;
1122
1123 if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1124 return false;
1125
1126 Register SrcReg = getRegForValue(V: Src);
1127 if (SrcReg == 0)
1128 return false;
1129
1130 // Determine the opcode for the conversion, which takes place
1131 // entirely within FPRs.
1132 Register DestReg = createResultReg(RC: &Mips::GPR32RegClass);
1133 Register TempReg = createResultReg(RC: &Mips::FGR32RegClass);
1134 unsigned Opc = (SrcVT == MVT::f32) ? Mips::TRUNC_W_S : Mips::TRUNC_W_D32;
1135
1136 // Generate the convert.
1137 emitInst(Opc, DstReg: TempReg).addReg(RegNo: SrcReg);
1138 emitInst(Opc: Mips::MFC1, DstReg: DestReg).addReg(RegNo: TempReg);
1139
1140 updateValueMap(I, Reg: DestReg);
1141 return true;
1142}
1143
1144bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
1145 SmallVectorImpl<MVT> &OutVTs,
1146 unsigned &NumBytes) {
1147 CallingConv::ID CC = CLI.CallConv;
1148 SmallVector<CCValAssign, 16> ArgLocs;
1149 SmallVector<Type *, 16> ArgTys;
1150 for (const ArgListEntry &Arg : CLI.Args)
1151 ArgTys.push_back(Elt: Arg.Val->getType());
1152 CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
1153 CCInfo.AnalyzeCallOperands(ArgVTs&: OutVTs, Flags&: CLI.OutFlags, OrigTys&: ArgTys,
1154 Fn: CCAssignFnForCall(CC));
1155 // Get a count of how many bytes are to be pushed on the stack.
1156 NumBytes = CCInfo.getStackSize();
1157 // This is the minimum argument area used for A0-A3.
1158 if (NumBytes < 16)
1159 NumBytes = 16;
1160
1161 emitInst(Opc: Mips::ADJCALLSTACKDOWN).addImm(Val: 16).addImm(Val: 0);
1162 // Process the args.
1163 MVT firstMVT;
1164 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1165 CCValAssign &VA = ArgLocs[i];
1166 const Value *ArgVal = CLI.OutVals[VA.getValNo()];
1167 MVT ArgVT = OutVTs[VA.getValNo()];
1168
1169 if (i == 0) {
1170 firstMVT = ArgVT;
1171 if (ArgVT == MVT::f32) {
1172 VA.convertToReg(Reg: Mips::F12);
1173 } else if (ArgVT == MVT::f64) {
1174 if (Subtarget->isFP64bit())
1175 VA.convertToReg(Reg: Mips::D6_64);
1176 else
1177 VA.convertToReg(Reg: Mips::D6);
1178 }
1179 } else if (i == 1) {
1180 if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) {
1181 if (ArgVT == MVT::f32) {
1182 VA.convertToReg(Reg: Mips::F14);
1183 } else if (ArgVT == MVT::f64) {
1184 if (Subtarget->isFP64bit())
1185 VA.convertToReg(Reg: Mips::D7_64);
1186 else
1187 VA.convertToReg(Reg: Mips::D7);
1188 }
1189 }
1190 }
1191 if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32) || (ArgVT == MVT::i16) ||
1192 (ArgVT == MVT::i8)) &&
1193 VA.isMemLoc()) {
1194 switch (VA.getLocMemOffset()) {
1195 case 0:
1196 VA.convertToReg(Reg: getABI().getArgReg(I: 0, Is64Bit: false));
1197 break;
1198 case 4:
1199 VA.convertToReg(Reg: getABI().getArgReg(I: 1, Is64Bit: false));
1200 break;
1201 case 8:
1202 VA.convertToReg(Reg: getABI().getArgReg(I: 2, Is64Bit: false));
1203 break;
1204 case 12:
1205 VA.convertToReg(Reg: getABI().getArgReg(I: 3, Is64Bit: false));
1206 break;
1207 default:
1208 break;
1209 }
1210 }
1211 Register ArgReg = getRegForValue(V: ArgVal);
1212 if (!ArgReg)
1213 return false;
1214
1215 // Handle arg promotion: SExt, ZExt, AExt.
1216 switch (VA.getLocInfo()) {
1217 case CCValAssign::Full:
1218 break;
1219 case CCValAssign::AExt:
1220 case CCValAssign::SExt: {
1221 MVT DestVT = VA.getLocVT();
1222 MVT SrcVT = ArgVT;
1223 ArgReg = emitIntExt(SrcVT, SrcReg: ArgReg, DestVT, /*isZExt=*/false);
1224 if (!ArgReg)
1225 return false;
1226 break;
1227 }
1228 case CCValAssign::ZExt: {
1229 MVT DestVT = VA.getLocVT();
1230 MVT SrcVT = ArgVT;
1231 ArgReg = emitIntExt(SrcVT, SrcReg: ArgReg, DestVT, /*isZExt=*/true);
1232 if (!ArgReg)
1233 return false;
1234 break;
1235 }
1236 default:
1237 llvm_unreachable("Unknown arg promotion!");
1238 }
1239
1240 // Now copy/store arg to correct locations.
1241 if (VA.isRegLoc() && !VA.needsCustom()) {
1242 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1243 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: VA.getLocReg()).addReg(RegNo: ArgReg);
1244 CLI.OutRegs.push_back(Elt: VA.getLocReg());
1245 } else if (VA.needsCustom()) {
1246 llvm_unreachable("Mips does not use custom args.");
1247 return false;
1248 } else {
1249 //
1250 // FIXME: This path will currently return false. It was copied
1251 // from the AArch64 port and should be essentially fine for Mips too.
1252 // The work to finish up this path will be done in a follow-on patch.
1253 //
1254 assert(VA.isMemLoc() && "Assuming store on stack.");
1255 // Don't emit stores for undef values.
1256 if (isa<UndefValue>(Val: ArgVal))
1257 continue;
1258
1259 // Need to store on the stack.
1260 // FIXME: This alignment is incorrect but this path is disabled
1261 // for now (will return false). We need to determine the right alignment
1262 // based on the normal alignment for the underlying machine type.
1263 //
1264 unsigned ArgSize = alignTo(Size: ArgVT.getSizeInBits(), Align: 4);
1265
1266 unsigned BEAlign = 0;
1267 if (ArgSize < 8 && !Subtarget->isLittle())
1268 BEAlign = 8 - ArgSize;
1269
1270 Address Addr;
1271 Addr.setKind(Address::RegBase);
1272 Addr.setReg(Mips::SP);
1273 Addr.setOffset(VA.getLocMemOffset() + BEAlign);
1274
1275 Align Alignment = DL.getABITypeAlign(Ty: ArgVal->getType());
1276 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
1277 PtrInfo: MachinePointerInfo::getStack(MF&: *FuncInfo.MF, Offset: Addr.getOffset()),
1278 F: MachineMemOperand::MOStore, Size: ArgVT.getStoreSize(), BaseAlignment: Alignment);
1279 (void)(MMO);
1280 // if (!emitStore(ArgVT, ArgReg, Addr, MMO))
1281 return false; // can't store on the stack yet.
1282 }
1283 }
1284
1285 return true;
1286}
1287
1288bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
1289 unsigned NumBytes) {
1290 CallingConv::ID CC = CLI.CallConv;
1291 emitInst(Opc: Mips::ADJCALLSTACKUP).addImm(Val: 16).addImm(Val: 0);
1292 if (RetVT != MVT::isVoid) {
1293 SmallVector<CCValAssign, 16> RVLocs;
1294 MipsCCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1295
1296 CCInfo.AnalyzeCallResult(Ins: CLI.Ins, Fn: RetCC_Mips);
1297
1298 // Only handle a single return value.
1299 if (RVLocs.size() != 1)
1300 return false;
1301 // Copy all of the result registers out of their specified physreg.
1302 MVT CopyVT = RVLocs[0].getValVT();
1303 // Special handling for extended integers.
1304 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1305 CopyVT = MVT::i32;
1306
1307 Register ResultReg = createResultReg(RC: TLI.getRegClassFor(VT: CopyVT));
1308 if (!ResultReg)
1309 return false;
1310 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1311 MCID: TII.get(Opcode: TargetOpcode::COPY),
1312 DestReg: ResultReg).addReg(RegNo: RVLocs[0].getLocReg());
1313 CLI.InRegs.push_back(Elt: RVLocs[0].getLocReg());
1314
1315 CLI.ResultReg = ResultReg;
1316 CLI.NumResultRegs = 1;
1317 }
1318 return true;
1319}
1320
1321bool MipsFastISel::fastLowerArguments() {
1322 LLVM_DEBUG(dbgs() << "fastLowerArguments\n");
1323
1324 if (!FuncInfo.CanLowerReturn) {
1325 LLVM_DEBUG(dbgs() << ".. gave up (!CanLowerReturn)\n");
1326 return false;
1327 }
1328
1329 const Function *F = FuncInfo.Fn;
1330 if (F->isVarArg()) {
1331 LLVM_DEBUG(dbgs() << ".. gave up (varargs)\n");
1332 return false;
1333 }
1334
1335 CallingConv::ID CC = F->getCallingConv();
1336 if (CC != CallingConv::C) {
1337 LLVM_DEBUG(dbgs() << ".. gave up (calling convention is not C)\n");
1338 return false;
1339 }
1340
1341 ArrayRef<MCPhysReg> GPR32ArgRegs = getABI().getArgRegs(Is64Bit: false);
1342 std::array<MCPhysReg, 2> FGR32ArgRegs = {._M_elems: {Mips::F12, Mips::F14}};
1343 std::array<MCPhysReg, 2> AFGR64ArgRegs = {._M_elems: {Mips::D6, Mips::D7}};
1344 auto NextGPR32 = GPR32ArgRegs.begin();
1345 auto NextFGR32 = FGR32ArgRegs.begin();
1346 auto NextAFGR64 = AFGR64ArgRegs.begin();
1347
1348 struct AllocatedReg {
1349 const TargetRegisterClass *RC;
1350 unsigned Reg;
1351 AllocatedReg(const TargetRegisterClass *RC, unsigned Reg)
1352 : RC(RC), Reg(Reg) {}
1353 };
1354
1355 // Only handle simple cases. i.e. All arguments are directly mapped to
1356 // registers of the appropriate type.
1357 SmallVector<AllocatedReg, 4> Allocation;
1358 for (const auto &FormalArg : F->args()) {
1359 if (FormalArg.hasAttribute(Kind: Attribute::InReg) ||
1360 FormalArg.hasAttribute(Kind: Attribute::StructRet) ||
1361 FormalArg.hasAttribute(Kind: Attribute::ByVal)) {
1362 LLVM_DEBUG(dbgs() << ".. gave up (inreg, structret, byval)\n");
1363 return false;
1364 }
1365
1366 Type *ArgTy = FormalArg.getType();
1367 if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy()) {
1368 LLVM_DEBUG(dbgs() << ".. gave up (struct, array, or vector)\n");
1369 return false;
1370 }
1371
1372 EVT ArgVT = TLI.getValueType(DL, Ty: ArgTy);
1373 LLVM_DEBUG(dbgs() << ".. " << FormalArg.getArgNo() << ": "
1374 << ArgVT << "\n");
1375 if (!ArgVT.isSimple()) {
1376 LLVM_DEBUG(dbgs() << ".. .. gave up (not a simple type)\n");
1377 return false;
1378 }
1379
1380 switch (ArgVT.getSimpleVT().SimpleTy) {
1381 case MVT::i1:
1382 case MVT::i8:
1383 case MVT::i16:
1384 if (!FormalArg.hasAttribute(Kind: Attribute::SExt) &&
1385 !FormalArg.hasAttribute(Kind: Attribute::ZExt)) {
1386 // It must be any extend, this shouldn't happen for clang-generated IR
1387 // so just fall back on SelectionDAG.
1388 LLVM_DEBUG(dbgs() << ".. .. gave up (i8/i16 arg is not extended)\n");
1389 return false;
1390 }
1391
1392 if (NextGPR32 == GPR32ArgRegs.end()) {
1393 LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n");
1394 return false;
1395 }
1396
1397 LLVM_DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n");
1398 Allocation.emplace_back(Args: &Mips::GPR32RegClass, Args: *NextGPR32++);
1399
1400 // Allocating any GPR32 prohibits further use of floating point arguments.
1401 NextFGR32 = FGR32ArgRegs.end();
1402 NextAFGR64 = AFGR64ArgRegs.end();
1403 break;
1404
1405 case MVT::i32:
1406 if (FormalArg.hasAttribute(Kind: Attribute::ZExt)) {
1407 // The O32 ABI does not permit a zero-extended i32.
1408 LLVM_DEBUG(dbgs() << ".. .. gave up (i32 arg is zero extended)\n");
1409 return false;
1410 }
1411
1412 if (NextGPR32 == GPR32ArgRegs.end()) {
1413 LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n");
1414 return false;
1415 }
1416
1417 LLVM_DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n");
1418 Allocation.emplace_back(Args: &Mips::GPR32RegClass, Args: *NextGPR32++);
1419
1420 // Allocating any GPR32 prohibits further use of floating point arguments.
1421 NextFGR32 = FGR32ArgRegs.end();
1422 NextAFGR64 = AFGR64ArgRegs.end();
1423 break;
1424
1425 case MVT::f32:
1426 if (UnsupportedFPMode) {
1427 LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n");
1428 return false;
1429 }
1430 if (NextFGR32 == FGR32ArgRegs.end()) {
1431 LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of FGR32 arguments)\n");
1432 return false;
1433 }
1434 LLVM_DEBUG(dbgs() << ".. .. FGR32(" << *NextFGR32 << ")\n");
1435 Allocation.emplace_back(Args: &Mips::FGR32RegClass, Args&: *NextFGR32++);
1436 // Allocating an FGR32 also allocates the super-register AFGR64, and
1437 // ABI rules require us to skip the corresponding GPR32.
1438 if (NextGPR32 != GPR32ArgRegs.end())
1439 NextGPR32++;
1440 if (NextAFGR64 != AFGR64ArgRegs.end())
1441 NextAFGR64++;
1442 break;
1443
1444 case MVT::f64:
1445 if (UnsupportedFPMode) {
1446 LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n");
1447 return false;
1448 }
1449 if (NextAFGR64 == AFGR64ArgRegs.end()) {
1450 LLVM_DEBUG(dbgs() << ".. .. gave up (ran out of AFGR64 arguments)\n");
1451 return false;
1452 }
1453 LLVM_DEBUG(dbgs() << ".. .. AFGR64(" << *NextAFGR64 << ")\n");
1454 Allocation.emplace_back(Args: &Mips::AFGR64RegClass, Args&: *NextAFGR64++);
1455 // Allocating an FGR32 also allocates the super-register AFGR64, and
1456 // ABI rules require us to skip the corresponding GPR32 pair.
1457 if (NextGPR32 != GPR32ArgRegs.end())
1458 NextGPR32++;
1459 if (NextGPR32 != GPR32ArgRegs.end())
1460 NextGPR32++;
1461 if (NextFGR32 != FGR32ArgRegs.end())
1462 NextFGR32++;
1463 break;
1464
1465 default:
1466 LLVM_DEBUG(dbgs() << ".. .. gave up (unknown type)\n");
1467 return false;
1468 }
1469 }
1470
1471 for (const auto &FormalArg : F->args()) {
1472 unsigned ArgNo = FormalArg.getArgNo();
1473 unsigned SrcReg = Allocation[ArgNo].Reg;
1474 Register DstReg = FuncInfo.MF->addLiveIn(PReg: SrcReg, RC: Allocation[ArgNo].RC);
1475 // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
1476 // Without this, EmitLiveInCopies may eliminate the livein if its only
1477 // use is a bitcast (which isn't turned into an instruction).
1478 Register ResultReg = createResultReg(RC: Allocation[ArgNo].RC);
1479 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: TargetOpcode::COPY),
1480 DestReg: ResultReg)
1481 .addReg(RegNo: DstReg);
1482 updateValueMap(I: &FormalArg, Reg: ResultReg);
1483 }
1484
1485 // Calculate the size of the incoming arguments area.
1486 // We currently reject all the cases where this would be non-zero.
1487 unsigned IncomingArgSizeInBytes = 0;
1488
1489 // Account for the reserved argument area on ABI's that have one (O32).
1490 // It seems strange to do this on the caller side but it's necessary in
1491 // SelectionDAG's implementation.
1492 IncomingArgSizeInBytes = std::max(a: getABI().GetCalleeAllocdArgSizeInBytes(CC),
1493 b: IncomingArgSizeInBytes);
1494
1495 MF->getInfo<MipsFunctionInfo>()->setFormalArgInfo(Size: IncomingArgSizeInBytes,
1496 HasByval: false);
1497
1498 return true;
1499}
1500
1501bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1502 CallingConv::ID CC = CLI.CallConv;
1503 bool IsTailCall = CLI.IsTailCall;
1504 bool IsVarArg = CLI.IsVarArg;
1505 const Value *Callee = CLI.Callee;
1506 MCSymbol *Symbol = CLI.Symbol;
1507
1508 // Do not handle FastCC.
1509 if (CC == CallingConv::Fast)
1510 return false;
1511
1512 // Allow SelectionDAG isel to handle tail calls.
1513 if (IsTailCall)
1514 return false;
1515
1516 // Let SDISel handle vararg functions.
1517 if (IsVarArg)
1518 return false;
1519
1520 // FIXME: Only handle *simple* calls for now.
1521 MVT RetVT;
1522 if (CLI.RetTy->isVoidTy())
1523 RetVT = MVT::isVoid;
1524 else if (!isTypeSupported(Ty: CLI.RetTy, VT&: RetVT))
1525 return false;
1526
1527 for (auto Flag : CLI.OutFlags)
1528 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
1529 return false;
1530
1531 // Set up the argument vectors.
1532 SmallVector<MVT, 16> OutVTs;
1533 OutVTs.reserve(N: CLI.OutVals.size());
1534
1535 for (auto *Val : CLI.OutVals) {
1536 MVT VT;
1537 if (!isTypeLegal(Ty: Val->getType(), VT) &&
1538 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
1539 return false;
1540
1541 // We don't handle vector parameters yet.
1542 if (VT.isVector() || VT.getSizeInBits() > 64)
1543 return false;
1544
1545 OutVTs.push_back(Elt: VT);
1546 }
1547
1548 Address Addr;
1549 if (!computeCallAddress(V: Callee, Addr))
1550 return false;
1551
1552 // Handle the arguments now that we've gotten them.
1553 unsigned NumBytes;
1554 if (!processCallArgs(CLI, OutVTs, NumBytes))
1555 return false;
1556
1557 if (!Addr.getGlobalValue())
1558 return false;
1559
1560 // Issue the call.
1561 unsigned DestAddress;
1562 if (Symbol)
1563 DestAddress = materializeExternalCallSym(Sym: Symbol);
1564 else
1565 DestAddress = materializeGV(GV: Addr.getGlobalValue(), VT: MVT::i32);
1566 emitInst(Opc: TargetOpcode::COPY, DstReg: getABI().getTempReg(I: 9, Is64Bit: false))
1567 .addReg(RegNo: DestAddress);
1568 MachineInstrBuilder MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1569 MCID: TII.get(Opcode: Mips::JALR), DestReg: Mips::RA)
1570 .addReg(RegNo: getABI().getTempReg(I: 9, Is64Bit: false));
1571
1572 // Add implicit physical register uses to the call.
1573 for (auto Reg : CLI.OutRegs)
1574 MIB.addReg(RegNo: Reg, Flags: RegState::Implicit);
1575
1576 // Add a register mask with the call-preserved registers.
1577 // Proper defs for return values will be added by setPhysRegsDeadExcept().
1578 MIB.addRegMask(Mask: TRI.getCallPreservedMask(MF: *FuncInfo.MF, CC));
1579
1580 CLI.Call = MIB;
1581
1582 if (EmitJalrReloc && !Subtarget->inMips16Mode()) {
1583 // Attach callee address to the instruction, let asm printer emit
1584 // .reloc R_MIPS_JALR.
1585 if (Symbol)
1586 MIB.addSym(Sym: Symbol, TargetFlags: MipsII::MO_JALR);
1587 else
1588 MIB.addSym(Sym: FuncInfo.MF->getContext().getOrCreateSymbol(
1589 Name: Addr.getGlobalValue()->getName()), TargetFlags: MipsII::MO_JALR);
1590 }
1591
1592 // Finish off the call including any return values.
1593 return finishCall(CLI, RetVT, NumBytes);
1594}
1595
1596bool MipsFastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
1597 switch (II->getIntrinsicID()) {
1598 default:
1599 return false;
1600 case Intrinsic::bswap: {
1601 Type *RetTy = II->getCalledFunction()->getReturnType();
1602
1603 MVT VT;
1604 if (!isTypeSupported(Ty: RetTy, VT))
1605 return false;
1606
1607 Register SrcReg = getRegForValue(V: II->getOperand(i_nocapture: 0));
1608 if (SrcReg == 0)
1609 return false;
1610 Register DestReg = createResultReg(RC: &Mips::GPR32RegClass);
1611 if (DestReg == 0)
1612 return false;
1613 if (VT == MVT::i16) {
1614 if (Subtarget->hasMips32r2()) {
1615 emitInst(Opc: Mips::WSBH, DstReg: DestReg).addReg(RegNo: SrcReg);
1616 updateValueMap(I: II, Reg: DestReg);
1617 return true;
1618 } else {
1619 unsigned TempReg[3];
1620 for (unsigned &R : TempReg) {
1621 R = createResultReg(RC: &Mips::GPR32RegClass);
1622 if (R == 0)
1623 return false;
1624 }
1625 emitInst(Opc: Mips::SLL, DstReg: TempReg[0]).addReg(RegNo: SrcReg).addImm(Val: 8);
1626 emitInst(Opc: Mips::SRL, DstReg: TempReg[1]).addReg(RegNo: SrcReg).addImm(Val: 8);
1627 emitInst(Opc: Mips::ANDi, DstReg: TempReg[2]).addReg(RegNo: TempReg[1]).addImm(Val: 0xFF);
1628 emitInst(Opc: Mips::OR, DstReg: DestReg).addReg(RegNo: TempReg[0]).addReg(RegNo: TempReg[2]);
1629 updateValueMap(I: II, Reg: DestReg);
1630 return true;
1631 }
1632 } else if (VT == MVT::i32) {
1633 if (Subtarget->hasMips32r2()) {
1634 Register TempReg = createResultReg(RC: &Mips::GPR32RegClass);
1635 emitInst(Opc: Mips::WSBH, DstReg: TempReg).addReg(RegNo: SrcReg);
1636 emitInst(Opc: Mips::ROTR, DstReg: DestReg).addReg(RegNo: TempReg).addImm(Val: 16);
1637 updateValueMap(I: II, Reg: DestReg);
1638 return true;
1639 } else {
1640 unsigned TempReg[8];
1641 for (unsigned &R : TempReg) {
1642 R = createResultReg(RC: &Mips::GPR32RegClass);
1643 if (R == 0)
1644 return false;
1645 }
1646
1647 emitInst(Opc: Mips::SRL, DstReg: TempReg[0]).addReg(RegNo: SrcReg).addImm(Val: 8);
1648 emitInst(Opc: Mips::SRL, DstReg: TempReg[1]).addReg(RegNo: SrcReg).addImm(Val: 24);
1649 emitInst(Opc: Mips::ANDi, DstReg: TempReg[2]).addReg(RegNo: TempReg[0]).addImm(Val: 0xFF00);
1650 emitInst(Opc: Mips::OR, DstReg: TempReg[3]).addReg(RegNo: TempReg[1]).addReg(RegNo: TempReg[2]);
1651
1652 emitInst(Opc: Mips::ANDi, DstReg: TempReg[4]).addReg(RegNo: SrcReg).addImm(Val: 0xFF00);
1653 emitInst(Opc: Mips::SLL, DstReg: TempReg[5]).addReg(RegNo: TempReg[4]).addImm(Val: 8);
1654
1655 emitInst(Opc: Mips::SLL, DstReg: TempReg[6]).addReg(RegNo: SrcReg).addImm(Val: 24);
1656 emitInst(Opc: Mips::OR, DstReg: TempReg[7]).addReg(RegNo: TempReg[3]).addReg(RegNo: TempReg[5]);
1657 emitInst(Opc: Mips::OR, DstReg: DestReg).addReg(RegNo: TempReg[6]).addReg(RegNo: TempReg[7]);
1658 updateValueMap(I: II, Reg: DestReg);
1659 return true;
1660 }
1661 }
1662 return false;
1663 }
1664 case Intrinsic::memcpy:
1665 case Intrinsic::memmove: {
1666 const auto *MTI = cast<MemTransferInst>(Val: II);
1667 // Don't handle volatile.
1668 if (MTI->isVolatile())
1669 return false;
1670 if (!MTI->getLength()->getType()->isIntegerTy(BitWidth: 32))
1671 return false;
1672 const char *IntrMemName = isa<MemCpyInst>(Val: II) ? "memcpy" : "memmove";
1673 return lowerCallTo(CI: II, SymName: IntrMemName, NumArgs: II->arg_size() - 1);
1674 }
1675 case Intrinsic::memset: {
1676 const MemSetInst *MSI = cast<MemSetInst>(Val: II);
1677 // Don't handle volatile.
1678 if (MSI->isVolatile())
1679 return false;
1680 if (!MSI->getLength()->getType()->isIntegerTy(BitWidth: 32))
1681 return false;
1682 return lowerCallTo(CI: II, SymName: "memset", NumArgs: II->arg_size() - 1);
1683 }
1684 }
1685 return false;
1686}
1687
1688bool MipsFastISel::selectRet(const Instruction *I) {
1689 const Function &F = *I->getParent()->getParent();
1690 const ReturnInst *Ret = cast<ReturnInst>(Val: I);
1691
1692 LLVM_DEBUG(dbgs() << "selectRet\n");
1693
1694 if (!FuncInfo.CanLowerReturn)
1695 return false;
1696
1697 // Build a list of return value registers.
1698 SmallVector<unsigned, 4> RetRegs;
1699
1700 if (Ret->getNumOperands() > 0) {
1701 CallingConv::ID CC = F.getCallingConv();
1702
1703 // Do not handle FastCC.
1704 if (CC == CallingConv::Fast)
1705 return false;
1706
1707 SmallVector<ISD::OutputArg, 4> Outs;
1708 GetReturnInfo(CC, ReturnType: F.getReturnType(), attr: F.getAttributes(), Outs, TLI, DL);
1709
1710 // Analyze operands of the call, assigning locations to each operand.
1711 SmallVector<CCValAssign, 16> ValLocs;
1712 MipsCCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs,
1713 I->getContext());
1714 CCAssignFn *RetCC = RetCC_Mips;
1715 CCInfo.AnalyzeReturn(Outs, Fn: RetCC);
1716
1717 // Only handle a single return value for now.
1718 if (ValLocs.size() != 1)
1719 return false;
1720
1721 CCValAssign &VA = ValLocs[0];
1722 const Value *RV = Ret->getOperand(i_nocapture: 0);
1723
1724 // Don't bother handling odd stuff for now.
1725 if ((VA.getLocInfo() != CCValAssign::Full) &&
1726 (VA.getLocInfo() != CCValAssign::BCvt))
1727 return false;
1728
1729 // Only handle register returns for now.
1730 if (!VA.isRegLoc())
1731 return false;
1732
1733 Register Reg = getRegForValue(V: RV);
1734 if (Reg == 0)
1735 return false;
1736
1737 unsigned SrcReg = Reg + VA.getValNo();
1738 Register DestReg = VA.getLocReg();
1739 // Avoid a cross-class copy. This is very unlikely.
1740 if (!MRI.getRegClass(Reg: SrcReg)->contains(Reg: DestReg))
1741 return false;
1742
1743 EVT RVEVT = TLI.getValueType(DL, Ty: RV->getType());
1744 if (!RVEVT.isSimple())
1745 return false;
1746
1747 if (RVEVT.isVector())
1748 return false;
1749
1750 MVT RVVT = RVEVT.getSimpleVT();
1751 if (RVVT == MVT::f128)
1752 return false;
1753
1754 // Do not handle FGR64 returns for now.
1755 if (RVVT == MVT::f64 && UnsupportedFPMode) {
1756 LLVM_DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode\n");
1757 return false;
1758 }
1759
1760 MVT DestVT = VA.getValVT();
1761 // Special handling for extended integers.
1762 if (RVVT != DestVT) {
1763 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
1764 return false;
1765
1766 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
1767 bool IsZExt = Outs[0].Flags.isZExt();
1768 SrcReg = emitIntExt(SrcVT: RVVT, SrcReg, DestVT, isZExt: IsZExt);
1769 if (SrcReg == 0)
1770 return false;
1771 }
1772 }
1773
1774 // Make the copy.
1775 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1776 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg).addReg(RegNo: SrcReg);
1777
1778 // Add register to return instruction.
1779 RetRegs.push_back(Elt: VA.getLocReg());
1780 }
1781 MachineInstrBuilder MIB = emitInst(Opc: Mips::RetRA);
1782 for (unsigned Reg : RetRegs)
1783 MIB.addReg(RegNo: Reg, Flags: RegState::Implicit);
1784 return true;
1785}
1786
1787bool MipsFastISel::selectTrunc(const Instruction *I) {
1788 // The high bits for a type smaller than the register size are assumed to be
1789 // undefined.
1790 Value *Op = I->getOperand(i: 0);
1791
1792 EVT SrcVT, DestVT;
1793 SrcVT = TLI.getValueType(DL, Ty: Op->getType(), AllowUnknown: true);
1794 DestVT = TLI.getValueType(DL, Ty: I->getType(), AllowUnknown: true);
1795
1796 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1797 return false;
1798 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1799 return false;
1800
1801 Register SrcReg = getRegForValue(V: Op);
1802 if (!SrcReg)
1803 return false;
1804
1805 // Because the high bits are undefined, a truncate doesn't generate
1806 // any code.
1807 updateValueMap(I, Reg: SrcReg);
1808 return true;
1809}
1810
1811bool MipsFastISel::selectIntExt(const Instruction *I) {
1812 Type *DestTy = I->getType();
1813 Value *Src = I->getOperand(i: 0);
1814 Type *SrcTy = Src->getType();
1815
1816 bool isZExt = isa<ZExtInst>(Val: I);
1817 Register SrcReg = getRegForValue(V: Src);
1818 if (!SrcReg)
1819 return false;
1820
1821 EVT SrcEVT, DestEVT;
1822 SrcEVT = TLI.getValueType(DL, Ty: SrcTy, AllowUnknown: true);
1823 DestEVT = TLI.getValueType(DL, Ty: DestTy, AllowUnknown: true);
1824 if (!SrcEVT.isSimple())
1825 return false;
1826 if (!DestEVT.isSimple())
1827 return false;
1828
1829 MVT SrcVT = SrcEVT.getSimpleVT();
1830 MVT DestVT = DestEVT.getSimpleVT();
1831 Register ResultReg = createResultReg(RC: &Mips::GPR32RegClass);
1832
1833 if (!emitIntExt(SrcVT, SrcReg, DestVT, DestReg: ResultReg, IsZExt: isZExt))
1834 return false;
1835 updateValueMap(I, Reg: ResultReg);
1836 return true;
1837}
1838
1839bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1840 unsigned DestReg) {
1841 unsigned ShiftAmt;
1842 switch (SrcVT.SimpleTy) {
1843 default:
1844 return false;
1845 case MVT::i8:
1846 ShiftAmt = 24;
1847 break;
1848 case MVT::i16:
1849 ShiftAmt = 16;
1850 break;
1851 }
1852 Register TempReg = createResultReg(RC: &Mips::GPR32RegClass);
1853 emitInst(Opc: Mips::SLL, DstReg: TempReg).addReg(RegNo: SrcReg).addImm(Val: ShiftAmt);
1854 emitInst(Opc: Mips::SRA, DstReg: DestReg).addReg(RegNo: TempReg).addImm(Val: ShiftAmt);
1855 return true;
1856}
1857
1858bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1859 unsigned DestReg) {
1860 switch (SrcVT.SimpleTy) {
1861 default:
1862 return false;
1863 case MVT::i8:
1864 emitInst(Opc: Mips::SEB, DstReg: DestReg).addReg(RegNo: SrcReg);
1865 break;
1866 case MVT::i16:
1867 emitInst(Opc: Mips::SEH, DstReg: DestReg).addReg(RegNo: SrcReg);
1868 break;
1869 }
1870 return true;
1871}
1872
1873bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1874 unsigned DestReg) {
1875 if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
1876 return false;
1877 if (Subtarget->hasMips32r2())
1878 return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
1879 return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
1880}
1881
1882bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1883 unsigned DestReg) {
1884 int64_t Imm;
1885
1886 switch (SrcVT.SimpleTy) {
1887 default:
1888 return false;
1889 case MVT::i1:
1890 Imm = 1;
1891 break;
1892 case MVT::i8:
1893 Imm = 0xff;
1894 break;
1895 case MVT::i16:
1896 Imm = 0xffff;
1897 break;
1898 }
1899
1900 emitInst(Opc: Mips::ANDi, DstReg: DestReg).addReg(RegNo: SrcReg).addImm(Val: Imm);
1901 return true;
1902}
1903
1904bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1905 unsigned DestReg, bool IsZExt) {
1906 // FastISel does not have plumbing to deal with extensions where the SrcVT or
1907 // DestVT are odd things, so test to make sure that they are both types we can
1908 // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
1909 // bail out to SelectionDAG.
1910 if (((DestVT != MVT::i8) && (DestVT != MVT::i16) && (DestVT != MVT::i32)) ||
1911 ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && (SrcVT != MVT::i16)))
1912 return false;
1913 if (IsZExt)
1914 return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
1915 return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
1916}
1917
1918unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1919 bool isZExt) {
1920 unsigned DestReg = createResultReg(RC: &Mips::GPR32RegClass);
1921 bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, IsZExt: isZExt);
1922 return Success ? DestReg : 0;
1923}
1924
1925bool MipsFastISel::selectDivRem(const Instruction *I, unsigned ISDOpcode) {
1926 EVT DestEVT = TLI.getValueType(DL, Ty: I->getType(), AllowUnknown: true);
1927 if (!DestEVT.isSimple())
1928 return false;
1929
1930 MVT DestVT = DestEVT.getSimpleVT();
1931 if (DestVT != MVT::i32)
1932 return false;
1933
1934 unsigned DivOpc;
1935 switch (ISDOpcode) {
1936 default:
1937 return false;
1938 case ISD::SDIV:
1939 case ISD::SREM:
1940 DivOpc = Mips::SDIV;
1941 break;
1942 case ISD::UDIV:
1943 case ISD::UREM:
1944 DivOpc = Mips::UDIV;
1945 break;
1946 }
1947
1948 Register Src0Reg = getRegForValue(V: I->getOperand(i: 0));
1949 Register Src1Reg = getRegForValue(V: I->getOperand(i: 1));
1950 if (!Src0Reg || !Src1Reg)
1951 return false;
1952
1953 emitInst(Opc: DivOpc).addReg(RegNo: Src0Reg).addReg(RegNo: Src1Reg);
1954 if (!NoZeroDivCheck && (!isa<ConstantInt>(Val: I->getOperand(i: 1)) ||
1955 dyn_cast<ConstantInt>(Val: I->getOperand(i: 1))->isZero())) {
1956 emitInst(Opc: Mips::TEQ).addReg(RegNo: Src1Reg).addReg(RegNo: Mips::ZERO).addImm(Val: 7);
1957 }
1958
1959 Register ResultReg = createResultReg(RC: &Mips::GPR32RegClass);
1960 if (!ResultReg)
1961 return false;
1962
1963 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM)
1964 ? Mips::MFHI
1965 : Mips::MFLO;
1966 emitInst(Opc: MFOpc, DstReg: ResultReg);
1967
1968 updateValueMap(I, Reg: ResultReg);
1969 return true;
1970}
1971
1972bool MipsFastISel::selectShift(const Instruction *I) {
1973 MVT RetVT;
1974
1975 if (!isTypeSupported(Ty: I->getType(), VT&: RetVT))
1976 return false;
1977
1978 Register ResultReg = createResultReg(RC: &Mips::GPR32RegClass);
1979 if (!ResultReg)
1980 return false;
1981
1982 unsigned Opcode = I->getOpcode();
1983 const Value *Op0 = I->getOperand(i: 0);
1984 Register Op0Reg = getRegForValue(V: Op0);
1985 if (!Op0Reg)
1986 return false;
1987
1988 // If AShr or LShr, then we need to make sure the operand0 is sign extended.
1989 if (Opcode == Instruction::AShr || Opcode == Instruction::LShr) {
1990 Register TempReg = createResultReg(RC: &Mips::GPR32RegClass);
1991 if (!TempReg)
1992 return false;
1993
1994 MVT Op0MVT = TLI.getValueType(DL, Ty: Op0->getType(), AllowUnknown: true).getSimpleVT();
1995 bool IsZExt = Opcode == Instruction::LShr;
1996 if (!emitIntExt(SrcVT: Op0MVT, SrcReg: Op0Reg, DestVT: MVT::i32, DestReg: TempReg, IsZExt))
1997 return false;
1998
1999 Op0Reg = TempReg;
2000 }
2001
2002 if (const auto *C = dyn_cast<ConstantInt>(Val: I->getOperand(i: 1))) {
2003 uint64_t ShiftVal = C->getZExtValue();
2004
2005 switch (Opcode) {
2006 default:
2007 llvm_unreachable("Unexpected instruction.");
2008 case Instruction::Shl:
2009 Opcode = Mips::SLL;
2010 break;
2011 case Instruction::AShr:
2012 Opcode = Mips::SRA;
2013 break;
2014 case Instruction::LShr:
2015 Opcode = Mips::SRL;
2016 break;
2017 }
2018
2019 emitInst(Opc: Opcode, DstReg: ResultReg).addReg(RegNo: Op0Reg).addImm(Val: ShiftVal);
2020 updateValueMap(I, Reg: ResultReg);
2021 return true;
2022 }
2023
2024 Register Op1Reg = getRegForValue(V: I->getOperand(i: 1));
2025 if (!Op1Reg)
2026 return false;
2027
2028 switch (Opcode) {
2029 default:
2030 llvm_unreachable("Unexpected instruction.");
2031 case Instruction::Shl:
2032 Opcode = Mips::SLLV;
2033 break;
2034 case Instruction::AShr:
2035 Opcode = Mips::SRAV;
2036 break;
2037 case Instruction::LShr:
2038 Opcode = Mips::SRLV;
2039 break;
2040 }
2041
2042 emitInst(Opc: Opcode, DstReg: ResultReg).addReg(RegNo: Op0Reg).addReg(RegNo: Op1Reg);
2043 updateValueMap(I, Reg: ResultReg);
2044 return true;
2045}
2046
2047bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
2048 switch (I->getOpcode()) {
2049 default:
2050 break;
2051 case Instruction::Load:
2052 return selectLoad(I);
2053 case Instruction::Store:
2054 return selectStore(I);
2055 case Instruction::SDiv:
2056 if (!selectBinaryOp(I, ISDOpcode: ISD::SDIV))
2057 return selectDivRem(I, ISDOpcode: ISD::SDIV);
2058 return true;
2059 case Instruction::UDiv:
2060 if (!selectBinaryOp(I, ISDOpcode: ISD::UDIV))
2061 return selectDivRem(I, ISDOpcode: ISD::UDIV);
2062 return true;
2063 case Instruction::SRem:
2064 if (!selectBinaryOp(I, ISDOpcode: ISD::SREM))
2065 return selectDivRem(I, ISDOpcode: ISD::SREM);
2066 return true;
2067 case Instruction::URem:
2068 if (!selectBinaryOp(I, ISDOpcode: ISD::UREM))
2069 return selectDivRem(I, ISDOpcode: ISD::UREM);
2070 return true;
2071 case Instruction::Shl:
2072 case Instruction::LShr:
2073 case Instruction::AShr:
2074 return selectShift(I);
2075 case Instruction::And:
2076 case Instruction::Or:
2077 case Instruction::Xor:
2078 return selectLogicalOp(I);
2079 case Instruction::CondBr:
2080 return selectBranch(I);
2081 case Instruction::Ret:
2082 return selectRet(I);
2083 case Instruction::Trunc:
2084 return selectTrunc(I);
2085 case Instruction::ZExt:
2086 case Instruction::SExt:
2087 return selectIntExt(I);
2088 case Instruction::FPTrunc:
2089 return selectFPTrunc(I);
2090 case Instruction::FPExt:
2091 return selectFPExt(I);
2092 case Instruction::FPToSI:
2093 return selectFPToInt(I, /*isSigned*/ IsSigned: true);
2094 case Instruction::FPToUI:
2095 return selectFPToInt(I, /*isSigned*/ IsSigned: false);
2096 case Instruction::ICmp:
2097 case Instruction::FCmp:
2098 return selectCmp(I);
2099 case Instruction::Select:
2100 return selectSelect(I);
2101 }
2102 return false;
2103}
2104
2105unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
2106 bool IsUnsigned) {
2107 Register VReg = getRegForValue(V);
2108 if (VReg == 0)
2109 return 0;
2110 MVT VMVT = TLI.getValueType(DL, Ty: V->getType(), AllowUnknown: true).getSimpleVT();
2111
2112 if (VMVT == MVT::i1)
2113 return 0;
2114
2115 if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
2116 Register TempReg = createResultReg(RC: &Mips::GPR32RegClass);
2117 if (!emitIntExt(SrcVT: VMVT, SrcReg: VReg, DestVT: MVT::i32, DestReg: TempReg, IsZExt: IsUnsigned))
2118 return 0;
2119 VReg = TempReg;
2120 }
2121 return VReg;
2122}
2123
2124void MipsFastISel::simplifyAddress(Address &Addr) {
2125 if (!isInt<16>(x: Addr.getOffset())) {
2126 unsigned TempReg =
2127 materialize32BitInt(Imm: Addr.getOffset(), RC: &Mips::GPR32RegClass);
2128 Register DestReg = createResultReg(RC: &Mips::GPR32RegClass);
2129 emitInst(Opc: Mips::ADDu, DstReg: DestReg).addReg(RegNo: TempReg).addReg(RegNo: Addr.getReg());
2130 Addr.setReg(DestReg);
2131 Addr.setOffset(0);
2132 }
2133}
2134
2135unsigned MipsFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
2136 const TargetRegisterClass *RC,
2137 unsigned Op0, unsigned Op1) {
2138 // We treat the MUL instruction in a special way because it clobbers
2139 // the HI0 & LO0 registers. The TableGen definition of this instruction can
2140 // mark these registers only as implicitly defined. As a result, the
2141 // register allocator runs out of registers when this instruction is
2142 // followed by another instruction that defines the same registers too.
2143 // We can fix this by explicitly marking those registers as dead.
2144 if (MachineInstOpcode == Mips::MUL) {
2145 Register ResultReg = createResultReg(RC);
2146 const MCInstrDesc &II = TII.get(Opcode: MachineInstOpcode);
2147 Op0 = constrainOperandRegClass(II, Op: Op0, OpNum: II.getNumDefs());
2148 Op1 = constrainOperandRegClass(II, Op: Op1, OpNum: II.getNumDefs() + 1);
2149 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: II, DestReg: ResultReg)
2150 .addReg(RegNo: Op0)
2151 .addReg(RegNo: Op1)
2152 .setOperandDead(3) // implicit-def $hi0
2153 .setOperandDead(4); // implicit-def $lo0
2154 return ResultReg;
2155 }
2156
2157 return FastISel::fastEmitInst_rr(MachineInstOpcode, RC, Op0, Op1);
2158}
2159
2160namespace llvm {
2161
2162FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
2163 const TargetLibraryInfo *libInfo,
2164 const LibcallLoweringInfo *libcallLowering) {
2165 return new MipsFastISel(funcInfo, libInfo, libcallLowering);
2166}
2167
2168} // end namespace llvm
2169