1//===-- AMDGPUAtomicOptimizer.cpp -----------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// This pass optimizes atomic operations by using a single lane of a wavefront
11/// to perform the atomic operation, thus reducing contention on that memory
12/// location.
13/// Atomic optimizer uses following strategies to compute scan and reduced
14/// values
15/// 1. DPP -
16/// This is the most efficient implementation for scan. DPP uses Whole Wave
17/// Mode (WWM)
18/// 2. Iterative -
19// An alternative implementation iterates over all active lanes
20/// of Wavefront using llvm.cttz and performs scan using readlane & writelane
21/// intrinsics
22//===----------------------------------------------------------------------===//
23
24#include "AMDGPU.h"
25#include "GCNSubtarget.h"
26#include "llvm/Analysis/DomTreeUpdater.h"
27#include "llvm/Analysis/UniformityAnalysis.h"
28#include "llvm/CodeGen/TargetPassConfig.h"
29#include "llvm/IR/IRBuilder.h"
30#include "llvm/IR/InstVisitor.h"
31#include "llvm/IR/IntrinsicsAMDGPU.h"
32#include "llvm/InitializePasses.h"
33#include "llvm/Target/TargetMachine.h"
34#include "llvm/Transforms/Utils/BasicBlockUtils.h"
35
36#define DEBUG_TYPE "amdgpu-atomic-optimizer"
37
38using namespace llvm;
39using namespace llvm::AMDGPU;
40
41namespace {
42
43struct ReplacementInfo {
44 Instruction *I;
45 AtomicRMWInst::BinOp Op;
46 unsigned ValIdx;
47 bool ValDivergent;
48 bool IsLDS;
49};
50
51class AMDGPUAtomicOptimizer : public FunctionPass {
52public:
53 static char ID;
54 ScanOptions ScanImpl;
55 AMDGPUAtomicOptimizer(ScanOptions ScanImpl)
56 : FunctionPass(ID), ScanImpl(ScanImpl) {}
57
58 bool runOnFunction(Function &F) override;
59
60 void getAnalysisUsage(AnalysisUsage &AU) const override {
61 AU.addPreserved<DominatorTreeWrapperPass>();
62 AU.addRequired<UniformityInfoWrapperPass>();
63 AU.addRequired<TargetPassConfig>();
64 }
65};
66
67class AMDGPUAtomicOptimizerImpl
68 : public InstVisitor<AMDGPUAtomicOptimizerImpl> {
69private:
70 Function &F;
71 SmallVector<ReplacementInfo, 8> ToReplace;
72 const UniformityInfo &UA;
73 const DataLayout &DL;
74 DomTreeUpdater &DTU;
75 const GCNSubtarget &ST;
76 bool IsPixelShader;
77 ScanOptions ScanImpl;
78
79 Value *buildReduction(IRBuilder<> &B, AtomicRMWInst::BinOp Op, Value *V,
80 Value *const Identity) const;
81 Value *buildScan(IRBuilder<> &B, AtomicRMWInst::BinOp Op, Value *V,
82 Value *const Identity) const;
83 Value *buildShiftRight(IRBuilder<> &B, Value *V, Value *const Identity) const;
84
85 std::pair<Value *, Value *>
86 buildScanIteratively(IRBuilder<> &B, AtomicRMWInst::BinOp Op,
87 Value *const Identity, Value *V, Instruction &I,
88 BasicBlock *ComputeLoop, BasicBlock *ComputeEnd) const;
89
90 void optimizeAtomic(Instruction &I, AtomicRMWInst::BinOp Op, unsigned ValIdx,
91 bool ValDivergent, bool IsLDS) const;
92
93public:
94 AMDGPUAtomicOptimizerImpl() = delete;
95
96 AMDGPUAtomicOptimizerImpl(Function &F, const UniformityInfo &UA,
97 DomTreeUpdater &DTU, const GCNSubtarget &ST,
98 ScanOptions ScanImpl)
99 : F(F), UA(UA), DL(F.getDataLayout()), DTU(DTU), ST(ST),
100 IsPixelShader(F.getCallingConv() == CallingConv::AMDGPU_PS),
101 ScanImpl(ScanImpl) {}
102
103 bool run();
104
105 void visitAtomicRMWInst(AtomicRMWInst &I);
106 void visitIntrinsicInst(IntrinsicInst &I);
107};
108
109} // namespace
110
111char AMDGPUAtomicOptimizer::ID = 0;
112
113char &llvm::AMDGPUAtomicOptimizerID = AMDGPUAtomicOptimizer::ID;
114
115bool AMDGPUAtomicOptimizer::runOnFunction(Function &F) {
116 if (skipFunction(F)) {
117 return false;
118 }
119
120 const UniformityInfo &UA =
121 getAnalysis<UniformityInfoWrapperPass>().getUniformityInfo();
122
123 DominatorTreeWrapperPass *DTW =
124 getAnalysisIfAvailable<DominatorTreeWrapperPass>();
125 DomTreeUpdater DTU(DTW ? &DTW->getDomTree() : nullptr,
126 DomTreeUpdater::UpdateStrategy::Lazy);
127
128 const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
129 const TargetMachine &TM = TPC.getTM<TargetMachine>();
130 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F);
131
132 return AMDGPUAtomicOptimizerImpl(F, UA, DTU, ST, ScanImpl).run();
133}
134
135PreservedAnalyses AMDGPUAtomicOptimizerPass::run(Function &F,
136 FunctionAnalysisManager &AM) {
137 const auto &UA = AM.getResult<UniformityInfoAnalysis>(IR&: F);
138
139 DomTreeUpdater DTU(&AM.getResult<DominatorTreeAnalysis>(IR&: F),
140 DomTreeUpdater::UpdateStrategy::Lazy);
141 const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F);
142
143 bool IsChanged = AMDGPUAtomicOptimizerImpl(F, UA, DTU, ST, ScanImpl).run();
144
145 if (!IsChanged) {
146 return PreservedAnalyses::all();
147 }
148
149 PreservedAnalyses PA;
150 PA.preserve<DominatorTreeAnalysis>();
151 return PA;
152}
153
154bool AMDGPUAtomicOptimizerImpl::run() {
155 // Scan option None disables the Pass
156 if (ScanImpl == ScanOptions::None)
157 return false;
158 if (ST.isSingleLaneExecution(Kernel: F))
159 return false;
160
161 visit(F);
162 if (ToReplace.empty())
163 return false;
164
165 for (auto &[I, Op, ValIdx, ValDivergent, IsLDS] : ToReplace)
166 optimizeAtomic(I&: *I, Op, ValIdx, ValDivergent, IsLDS);
167 ToReplace.clear();
168 return true;
169}
170
171static bool isLegalCrossLaneType(Type *Ty) {
172 switch (Ty->getTypeID()) {
173 case Type::FloatTyID:
174 case Type::DoubleTyID:
175 return true;
176 case Type::IntegerTyID: {
177 unsigned Size = Ty->getIntegerBitWidth();
178 return (Size == 32 || Size == 64);
179 }
180 default:
181 return false;
182 }
183}
184
185void AMDGPUAtomicOptimizerImpl::visitAtomicRMWInst(AtomicRMWInst &I) {
186 if (I.getType()->isVectorTy() || I.isVolatile())
187 return;
188
189 // Early exit for unhandled address space atomic instructions.
190 switch (I.getPointerAddressSpace()) {
191 default:
192 return;
193 case AMDGPUAS::GLOBAL_ADDRESS:
194 case AMDGPUAS::LOCAL_ADDRESS:
195 break;
196 }
197
198 AtomicRMWInst::BinOp Op = I.getOperation();
199
200 switch (Op) {
201 default:
202 return;
203 case AtomicRMWInst::Add:
204 case AtomicRMWInst::Sub:
205 case AtomicRMWInst::And:
206 case AtomicRMWInst::Or:
207 case AtomicRMWInst::Xor:
208 case AtomicRMWInst::Max:
209 case AtomicRMWInst::Min:
210 case AtomicRMWInst::UMax:
211 case AtomicRMWInst::UMin:
212 case AtomicRMWInst::FAdd:
213 case AtomicRMWInst::FSub:
214 case AtomicRMWInst::FMax:
215 case AtomicRMWInst::FMin:
216 break;
217 }
218
219 // Only 32 and 64 bit floating point atomic ops are supported.
220 if (AtomicRMWInst::isFPOperation(Op) &&
221 !(I.getType()->isFloatTy() || I.getType()->isDoubleTy())) {
222 return;
223 }
224
225 const unsigned PtrIdx = 0;
226 const unsigned ValIdx = 1;
227
228 // If the pointer operand is divergent, then each lane is doing an atomic
229 // operation on a different address, and we cannot optimize that.
230 if (UA.isDivergentAtUse(U: I.getOperandUse(i: PtrIdx))) {
231 return;
232 }
233
234 bool ValDivergent = UA.isDivergentAtUse(U: I.getOperandUse(i: ValIdx));
235
236 // If the value operand is divergent, each lane is contributing a different
237 // value to the atomic calculation. We can only optimize divergent values if
238 // we have DPP available on our subtarget (for DPP strategy), and the atomic
239 // operation is 32 or 64 bits.
240 if (ValDivergent) {
241 if (ScanImpl == ScanOptions::DPP && !ST.hasDPP())
242 return;
243
244 if (!isLegalCrossLaneType(Ty: I.getType()))
245 return;
246 }
247
248 const bool IsLDS = I.getPointerAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
249
250 // If we get here, we can optimize the atomic using a single wavefront-wide
251 // atomic operation to do the calculation for the entire wavefront, so
252 // remember the instruction so we can come back to it.
253 ToReplace.push_back(Elt: {.I: &I, .Op: Op, .ValIdx: ValIdx, .ValDivergent: ValDivergent, .IsLDS: IsLDS});
254}
255
256void AMDGPUAtomicOptimizerImpl::visitIntrinsicInst(IntrinsicInst &I) {
257 if (I.getType()->isVectorTy())
258 return;
259
260 AtomicRMWInst::BinOp Op;
261
262 switch (I.getIntrinsicID()) {
263 default:
264 return;
265 case Intrinsic::amdgcn_struct_buffer_atomic_add:
266 case Intrinsic::amdgcn_struct_ptr_buffer_atomic_add:
267 case Intrinsic::amdgcn_raw_buffer_atomic_add:
268 case Intrinsic::amdgcn_raw_ptr_buffer_atomic_add:
269 Op = AtomicRMWInst::Add;
270 break;
271 case Intrinsic::amdgcn_struct_buffer_atomic_sub:
272 case Intrinsic::amdgcn_struct_ptr_buffer_atomic_sub:
273 case Intrinsic::amdgcn_raw_buffer_atomic_sub:
274 case Intrinsic::amdgcn_raw_ptr_buffer_atomic_sub:
275 Op = AtomicRMWInst::Sub;
276 break;
277 case Intrinsic::amdgcn_struct_buffer_atomic_and:
278 case Intrinsic::amdgcn_struct_ptr_buffer_atomic_and:
279 case Intrinsic::amdgcn_raw_buffer_atomic_and:
280 case Intrinsic::amdgcn_raw_ptr_buffer_atomic_and:
281 Op = AtomicRMWInst::And;
282 break;
283 case Intrinsic::amdgcn_struct_buffer_atomic_or:
284 case Intrinsic::amdgcn_struct_ptr_buffer_atomic_or:
285 case Intrinsic::amdgcn_raw_buffer_atomic_or:
286 case Intrinsic::amdgcn_raw_ptr_buffer_atomic_or:
287 Op = AtomicRMWInst::Or;
288 break;
289 case Intrinsic::amdgcn_struct_buffer_atomic_xor:
290 case Intrinsic::amdgcn_struct_ptr_buffer_atomic_xor:
291 case Intrinsic::amdgcn_raw_buffer_atomic_xor:
292 case Intrinsic::amdgcn_raw_ptr_buffer_atomic_xor:
293 Op = AtomicRMWInst::Xor;
294 break;
295 case Intrinsic::amdgcn_struct_buffer_atomic_smin:
296 case Intrinsic::amdgcn_struct_ptr_buffer_atomic_smin:
297 case Intrinsic::amdgcn_raw_buffer_atomic_smin:
298 case Intrinsic::amdgcn_raw_ptr_buffer_atomic_smin:
299 Op = AtomicRMWInst::Min;
300 break;
301 case Intrinsic::amdgcn_struct_buffer_atomic_umin:
302 case Intrinsic::amdgcn_struct_ptr_buffer_atomic_umin:
303 case Intrinsic::amdgcn_raw_buffer_atomic_umin:
304 case Intrinsic::amdgcn_raw_ptr_buffer_atomic_umin:
305 Op = AtomicRMWInst::UMin;
306 break;
307 case Intrinsic::amdgcn_struct_buffer_atomic_smax:
308 case Intrinsic::amdgcn_struct_ptr_buffer_atomic_smax:
309 case Intrinsic::amdgcn_raw_buffer_atomic_smax:
310 case Intrinsic::amdgcn_raw_ptr_buffer_atomic_smax:
311 Op = AtomicRMWInst::Max;
312 break;
313 case Intrinsic::amdgcn_struct_buffer_atomic_umax:
314 case Intrinsic::amdgcn_struct_ptr_buffer_atomic_umax:
315 case Intrinsic::amdgcn_raw_buffer_atomic_umax:
316 case Intrinsic::amdgcn_raw_ptr_buffer_atomic_umax:
317 Op = AtomicRMWInst::UMax;
318 break;
319 }
320
321 auto *Aux = cast<ConstantInt>(Val: I.getArgOperand(i: I.arg_size() - 1));
322 if (Aux->getZExtValue() & AMDGPU::CPol::VOLATILE)
323 return;
324
325 const unsigned ValIdx = 0;
326
327 const bool ValDivergent = UA.isDivergentAtUse(U: I.getOperandUse(i: ValIdx));
328
329 // If the value operand is divergent, each lane is contributing a different
330 // value to the atomic calculation. We can only optimize divergent values if
331 // we have DPP available on our subtarget (for DPP strategy), and the atomic
332 // operation is 32 or 64 bits.
333 if (ValDivergent) {
334 if (ScanImpl == ScanOptions::DPP && !ST.hasDPP())
335 return;
336
337 if (!isLegalCrossLaneType(Ty: I.getType()))
338 return;
339 }
340
341 // If any of the other arguments to the intrinsic are divergent, we can't
342 // optimize the operation.
343 for (unsigned Idx = 1; Idx < I.getNumOperands(); Idx++) {
344 if (UA.isDivergentAtUse(U: I.getOperandUse(i: Idx)))
345 return;
346 }
347
348 // If we get here, we can optimize the atomic using a single wavefront-wide
349 // atomic operation to do the calculation for the entire wavefront, so
350 // remember the instruction so we can come back to it.
351 // Buffer atomics are never LDS.
352 ToReplace.push_back(Elt: {.I: &I, .Op: Op, .ValIdx: ValIdx, .ValDivergent: ValDivergent, /*IsLDS=*/false});
353}
354
355// Use the builder to create the non-atomic counterpart of the specified
356// atomicrmw binary op.
357static Value *buildNonAtomicBinOp(IRBuilder<> &B, AtomicRMWInst::BinOp Op,
358 Value *LHS, Value *RHS) {
359 CmpInst::Predicate Pred;
360
361 switch (Op) {
362 default:
363 llvm_unreachable("Unhandled atomic op");
364 case AtomicRMWInst::Add:
365 return B.CreateBinOp(Opc: Instruction::Add, LHS, RHS);
366 case AtomicRMWInst::FAdd:
367 return B.CreateFAdd(L: LHS, R: RHS);
368 case AtomicRMWInst::Sub:
369 return B.CreateBinOp(Opc: Instruction::Sub, LHS, RHS);
370 case AtomicRMWInst::FSub:
371 return B.CreateFSub(L: LHS, R: RHS);
372 case AtomicRMWInst::And:
373 return B.CreateBinOp(Opc: Instruction::And, LHS, RHS);
374 case AtomicRMWInst::Or:
375 return B.CreateBinOp(Opc: Instruction::Or, LHS, RHS);
376 case AtomicRMWInst::Xor:
377 return B.CreateBinOp(Opc: Instruction::Xor, LHS, RHS);
378
379 case AtomicRMWInst::Max:
380 Pred = CmpInst::ICMP_SGT;
381 break;
382 case AtomicRMWInst::Min:
383 Pred = CmpInst::ICMP_SLT;
384 break;
385 case AtomicRMWInst::UMax:
386 Pred = CmpInst::ICMP_UGT;
387 break;
388 case AtomicRMWInst::UMin:
389 Pred = CmpInst::ICMP_ULT;
390 break;
391 case AtomicRMWInst::FMax:
392 return B.CreateMaxNum(LHS, RHS);
393 case AtomicRMWInst::FMin:
394 return B.CreateMinNum(LHS, RHS);
395 }
396 Value *Cond = B.CreateICmp(P: Pred, LHS, RHS);
397 return B.CreateSelect(C: Cond, True: LHS, False: RHS);
398}
399
400// Use the builder to create a reduction of V across the wavefront, with all
401// lanes active, returning the same result in all lanes.
402Value *AMDGPUAtomicOptimizerImpl::buildReduction(IRBuilder<> &B,
403 AtomicRMWInst::BinOp Op,
404 Value *V,
405 Value *const Identity) const {
406 Type *AtomicTy = V->getType();
407 Module *M = B.GetInsertBlock()->getModule();
408
409 // Reduce within each row of 16 lanes.
410 for (unsigned Idx = 0; Idx < 4; Idx++) {
411 V = buildNonAtomicBinOp(
412 B, Op, LHS: V,
413 RHS: B.CreateIntrinsic(ID: Intrinsic::amdgcn_update_dpp, OverloadTypes: AtomicTy,
414 Args: {Identity, V, B.getInt32(C: DPP::ROW_XMASK0 | 1 << Idx),
415 B.getInt32(C: 0xf), B.getInt32(C: 0xf), B.getFalse()}));
416 }
417
418 // Reduce within each pair of rows (i.e. 32 lanes).
419 assert(ST.hasPermlane16Insts());
420 Value *Permlanex16Call =
421 B.CreateIntrinsic(RetTy: AtomicTy, ID: Intrinsic::amdgcn_permlanex16,
422 Args: {PoisonValue::get(T: AtomicTy), V, B.getInt32(C: 0),
423 B.getInt32(C: 0), B.getFalse(), B.getFalse()});
424 V = buildNonAtomicBinOp(B, Op, LHS: V, RHS: Permlanex16Call);
425 if (ST.isWave32()) {
426 return V;
427 }
428
429 if (ST.hasPermLane64()) {
430 // Reduce across the upper and lower 32 lanes.
431 Value *Permlane64Call =
432 B.CreateIntrinsic(RetTy: AtomicTy, ID: Intrinsic::amdgcn_permlane64, Args: V);
433 return buildNonAtomicBinOp(B, Op, LHS: V, RHS: Permlane64Call);
434 }
435
436 // Pick an arbitrary lane from 0..31 and an arbitrary lane from 32..63 and
437 // combine them with a scalar operation.
438 Function *ReadLane = Intrinsic::getOrInsertDeclaration(
439 M, id: Intrinsic::amdgcn_readlane, OverloadTys: AtomicTy);
440 Value *Lane0 = B.CreateCall(Callee: ReadLane, Args: {V, B.getInt32(C: 0)});
441 Value *Lane32 = B.CreateCall(Callee: ReadLane, Args: {V, B.getInt32(C: 32)});
442 return buildNonAtomicBinOp(B, Op, LHS: Lane0, RHS: Lane32);
443}
444
445// Use the builder to create an inclusive scan of V across the wavefront, with
446// all lanes active.
447Value *AMDGPUAtomicOptimizerImpl::buildScan(IRBuilder<> &B,
448 AtomicRMWInst::BinOp Op, Value *V,
449 Value *Identity) const {
450 Type *AtomicTy = V->getType();
451 Module *M = B.GetInsertBlock()->getModule();
452 Function *UpdateDPP = Intrinsic::getOrInsertDeclaration(
453 M, id: Intrinsic::amdgcn_update_dpp, OverloadTys: AtomicTy);
454
455 for (unsigned Idx = 0; Idx < 4; Idx++) {
456 V = buildNonAtomicBinOp(
457 B, Op, LHS: V,
458 RHS: B.CreateCall(Callee: UpdateDPP,
459 Args: {Identity, V, B.getInt32(C: DPP::ROW_SHR0 | 1 << Idx),
460 B.getInt32(C: 0xf), B.getInt32(C: 0xf), B.getFalse()}));
461 }
462 if (ST.hasDPPBroadcasts()) {
463 // GFX9 has DPP row broadcast operations.
464 V = buildNonAtomicBinOp(
465 B, Op, LHS: V,
466 RHS: B.CreateCall(Callee: UpdateDPP,
467 Args: {Identity, V, B.getInt32(C: DPP::BCAST15), B.getInt32(C: 0xa),
468 B.getInt32(C: 0xf), B.getFalse()}));
469 V = buildNonAtomicBinOp(
470 B, Op, LHS: V,
471 RHS: B.CreateCall(Callee: UpdateDPP,
472 Args: {Identity, V, B.getInt32(C: DPP::BCAST31), B.getInt32(C: 0xc),
473 B.getInt32(C: 0xf), B.getFalse()}));
474 } else {
475 // On GFX10 all DPP operations are confined to a single row. To get cross-
476 // row operations we have to use permlane or readlane.
477
478 // Combine lane 15 into lanes 16..31 (and, for wave 64, lane 47 into lanes
479 // 48..63).
480 assert(ST.hasPermlane16Insts());
481 Value *PermX =
482 B.CreateIntrinsic(RetTy: AtomicTy, ID: Intrinsic::amdgcn_permlanex16,
483 Args: {PoisonValue::get(T: AtomicTy), V, B.getInt32(C: -1),
484 B.getInt32(C: -1), B.getFalse(), B.getFalse()});
485
486 Value *UpdateDPPCall = B.CreateCall(
487 Callee: UpdateDPP, Args: {Identity, PermX, B.getInt32(C: DPP::QUAD_PERM_ID),
488 B.getInt32(C: 0xa), B.getInt32(C: 0xf), B.getFalse()});
489 V = buildNonAtomicBinOp(B, Op, LHS: V, RHS: UpdateDPPCall);
490
491 if (!ST.isWave32()) {
492 // Combine lane 31 into lanes 32..63.
493 Value *const Lane31 = B.CreateIntrinsic(
494 RetTy: AtomicTy, ID: Intrinsic::amdgcn_readlane, Args: {V, B.getInt32(C: 31)});
495
496 Value *UpdateDPPCall = B.CreateCall(
497 Callee: UpdateDPP, Args: {Identity, Lane31, B.getInt32(C: DPP::QUAD_PERM_ID),
498 B.getInt32(C: 0xc), B.getInt32(C: 0xf), B.getFalse()});
499
500 V = buildNonAtomicBinOp(B, Op, LHS: V, RHS: UpdateDPPCall);
501 }
502 }
503 return V;
504}
505
506// Use the builder to create a shift right of V across the wavefront, with all
507// lanes active, to turn an inclusive scan into an exclusive scan.
508Value *AMDGPUAtomicOptimizerImpl::buildShiftRight(IRBuilder<> &B, Value *V,
509 Value *Identity) const {
510 Type *AtomicTy = V->getType();
511 Module *M = B.GetInsertBlock()->getModule();
512 Function *UpdateDPP = Intrinsic::getOrInsertDeclaration(
513 M, id: Intrinsic::amdgcn_update_dpp, OverloadTys: AtomicTy);
514 if (ST.hasDPPWavefrontShifts()) {
515 // GFX9 has DPP wavefront shift operations.
516 V = B.CreateCall(Callee: UpdateDPP,
517 Args: {Identity, V, B.getInt32(C: DPP::WAVE_SHR1), B.getInt32(C: 0xf),
518 B.getInt32(C: 0xf), B.getFalse()});
519 } else {
520 Function *ReadLane = Intrinsic::getOrInsertDeclaration(
521 M, id: Intrinsic::amdgcn_readlane, OverloadTys: AtomicTy);
522 Function *WriteLane = Intrinsic::getOrInsertDeclaration(
523 M, id: Intrinsic::amdgcn_writelane, OverloadTys: AtomicTy);
524
525 // On GFX10 all DPP operations are confined to a single row. To get cross-
526 // row operations we have to use permlane or readlane.
527 Value *Old = V;
528 V = B.CreateCall(Callee: UpdateDPP,
529 Args: {Identity, V, B.getInt32(C: DPP::ROW_SHR0 + 1),
530 B.getInt32(C: 0xf), B.getInt32(C: 0xf), B.getFalse()});
531
532 // Copy the old lane 15 to the new lane 16.
533 V = B.CreateCall(Callee: WriteLane, Args: {B.CreateCall(Callee: ReadLane, Args: {Old, B.getInt32(C: 15)}),
534 B.getInt32(C: 16), V});
535
536 if (!ST.isWave32()) {
537 // Copy the old lane 31 to the new lane 32.
538 V = B.CreateCall(
539 Callee: WriteLane,
540 Args: {B.CreateCall(Callee: ReadLane, Args: {Old, B.getInt32(C: 31)}), B.getInt32(C: 32), V});
541
542 // Copy the old lane 47 to the new lane 48.
543 V = B.CreateCall(
544 Callee: WriteLane,
545 Args: {B.CreateCall(Callee: ReadLane, Args: {Old, B.getInt32(C: 47)}), B.getInt32(C: 48), V});
546 }
547 }
548
549 return V;
550}
551
552// Use the builder to create an exclusive scan and compute the final reduced
553// value using an iterative approach. This provides an alternative
554// implementation to DPP which uses WMM for scan computations. This API iterate
555// over active lanes to read, compute and update the value using
556// readlane and writelane intrinsics.
557std::pair<Value *, Value *> AMDGPUAtomicOptimizerImpl::buildScanIteratively(
558 IRBuilder<> &B, AtomicRMWInst::BinOp Op, Value *const Identity, Value *V,
559 Instruction &I, BasicBlock *ComputeLoop, BasicBlock *ComputeEnd) const {
560 auto *Ty = I.getType();
561 auto *WaveTy = B.getIntNTy(N: ST.getWavefrontSize());
562 auto *EntryBB = I.getParent();
563 auto NeedResult = !I.use_empty();
564
565 auto *Ballot =
566 B.CreateIntrinsic(ID: Intrinsic::amdgcn_ballot, OverloadTypes: WaveTy, Args: B.getTrue());
567
568 // Start inserting instructions for ComputeLoop block
569 B.SetInsertPoint(ComputeLoop);
570 // Phi nodes for Accumulator, Scan results destination, and Active Lanes
571 auto *Accumulator = B.CreatePHI(Ty, NumReservedValues: 2, Name: "Accumulator");
572 Accumulator->addIncoming(V: Identity, BB: EntryBB);
573 PHINode *OldValuePhi = nullptr;
574 if (NeedResult) {
575 OldValuePhi = B.CreatePHI(Ty, NumReservedValues: 2, Name: "OldValuePhi");
576 OldValuePhi->addIncoming(V: PoisonValue::get(T: Ty), BB: EntryBB);
577 }
578 auto *ActiveBits = B.CreatePHI(Ty: WaveTy, NumReservedValues: 2, Name: "ActiveBits");
579 ActiveBits->addIncoming(V: Ballot, BB: EntryBB);
580
581 // Use llvm.cttz intrinsic to find the lowest remaining active lane.
582 auto *FF1 =
583 B.CreateIntrinsic(ID: Intrinsic::cttz, OverloadTypes: WaveTy, Args: {ActiveBits, B.getTrue()});
584
585 auto *LaneIdxInt = B.CreateTrunc(V: FF1, DestTy: B.getInt32Ty());
586
587 // Get the value required for atomic operation
588 Value *LaneValue = B.CreateIntrinsic(RetTy: V->getType(), ID: Intrinsic::amdgcn_readlane,
589 Args: {V, LaneIdxInt});
590
591 // Perform writelane if intermediate scan results are required later in the
592 // kernel computations
593 Value *OldValue = nullptr;
594 if (NeedResult) {
595 OldValue = B.CreateIntrinsic(RetTy: V->getType(), ID: Intrinsic::amdgcn_writelane,
596 Args: {Accumulator, LaneIdxInt, OldValuePhi});
597 OldValuePhi->addIncoming(V: OldValue, BB: ComputeLoop);
598 }
599
600 // Accumulate the results
601 auto *NewAccumulator = buildNonAtomicBinOp(B, Op, LHS: Accumulator, RHS: LaneValue);
602 Accumulator->addIncoming(V: NewAccumulator, BB: ComputeLoop);
603
604 // Set bit to zero of current active lane so that for next iteration llvm.cttz
605 // return the next active lane
606 auto *Mask = B.CreateShl(LHS: ConstantInt::get(Ty: WaveTy, V: 1), RHS: FF1);
607
608 auto *InverseMask = B.CreateXor(LHS: Mask, RHS: ConstantInt::getAllOnesValue(Ty: WaveTy));
609 auto *NewActiveBits = B.CreateAnd(LHS: ActiveBits, RHS: InverseMask);
610 ActiveBits->addIncoming(V: NewActiveBits, BB: ComputeLoop);
611
612 // Branch out of the loop when all lanes are processed.
613 auto *IsEnd = B.CreateICmpEQ(LHS: NewActiveBits, RHS: ConstantInt::get(Ty: WaveTy, V: 0));
614 B.CreateCondBr(Cond: IsEnd, True: ComputeEnd, False: ComputeLoop);
615
616 B.SetInsertPoint(ComputeEnd);
617
618 return {OldValue, NewAccumulator};
619}
620
621static Constant *getIdentityValueForAtomicOp(Type *const Ty,
622 AtomicRMWInst::BinOp Op) {
623 LLVMContext &C = Ty->getContext();
624 const unsigned BitWidth = Ty->getPrimitiveSizeInBits();
625 switch (Op) {
626 default:
627 llvm_unreachable("Unhandled atomic op");
628 case AtomicRMWInst::Add:
629 case AtomicRMWInst::Sub:
630 case AtomicRMWInst::Or:
631 case AtomicRMWInst::Xor:
632 case AtomicRMWInst::UMax:
633 return ConstantInt::get(Context&: C, V: APInt::getMinValue(numBits: BitWidth));
634 case AtomicRMWInst::And:
635 case AtomicRMWInst::UMin:
636 return ConstantInt::get(Context&: C, V: APInt::getMaxValue(numBits: BitWidth));
637 case AtomicRMWInst::Max:
638 return ConstantInt::get(Context&: C, V: APInt::getSignedMinValue(numBits: BitWidth));
639 case AtomicRMWInst::Min:
640 return ConstantInt::get(Context&: C, V: APInt::getSignedMaxValue(numBits: BitWidth));
641 case AtomicRMWInst::FAdd:
642 return ConstantFP::get(Context&: C, V: APFloat::getZero(Sem: Ty->getFltSemantics(), Negative: true));
643 case AtomicRMWInst::FSub:
644 return ConstantFP::get(Context&: C, V: APFloat::getZero(Sem: Ty->getFltSemantics(), Negative: false));
645 case AtomicRMWInst::FMin:
646 case AtomicRMWInst::FMax:
647 // FIXME: atomicrmw fmax/fmin behave like llvm.maxnum/minnum so NaN is the
648 // closest thing they have to an identity, but it still does not preserve
649 // the difference between quiet and signaling NaNs or NaNs with different
650 // payloads.
651 return ConstantFP::get(Context&: C, V: APFloat::getNaN(Sem: Ty->getFltSemantics()));
652 }
653}
654
655static Value *buildMul(IRBuilder<> &B, Value *LHS, Value *RHS) {
656 const ConstantInt *CI = dyn_cast<ConstantInt>(Val: LHS);
657 return (CI && CI->isOne()) ? RHS : B.CreateMul(LHS, RHS);
658}
659
660void AMDGPUAtomicOptimizerImpl::optimizeAtomic(Instruction &I,
661 AtomicRMWInst::BinOp Op,
662 unsigned ValIdx,
663 bool ValDivergent,
664 bool IsLDS) const {
665 // Don't generate a DPP scan if !amdgpu.expected.active.lane hint indicates
666 // insufficient lanes to offset fixed overhead.
667
668 // FIXME: The threshold was tuned empirically on gfx11 and gfx12. The DPP scan
669 // overhead differs across subtargets, so the break-even point may differ too;
670 // this may need to become subtarget-dependent.
671 if (IsLDS && ValDivergent && ScanImpl == ScanOptions::DPP) {
672 if (MDNode *MD = I.getMetadata(Kind: "amdgpu.expected.active.lanes")) {
673 auto *CI = mdconst::extract<ConstantInt>(MD: MD->getOperand(I: 0));
674 constexpr unsigned ActiveLanesThreshold = 5;
675 if (CI->getValue().ule(RHS: ActiveLanesThreshold))
676 return;
677 }
678 }
679
680 // Start building just before the instruction.
681 IRBuilder<> B(&I);
682
683 if (AtomicRMWInst::isFPOperation(Op)) {
684 B.setIsFPConstrained(I.getFunction()->hasFnAttribute(Kind: Attribute::StrictFP));
685 }
686
687 // If we are in a pixel shader, because of how we have to mask out helper
688 // lane invocations, we need to record the entry and exit BB's.
689 BasicBlock *PixelEntryBB = nullptr;
690 BasicBlock *PixelExitBB = nullptr;
691
692 // If we're optimizing an atomic within a pixel shader, we need to wrap the
693 // entire atomic operation in a helper-lane check. We do not want any helper
694 // lanes that are around only for the purposes of derivatives to take part
695 // in any cross-lane communication, and we use a branch on whether the lane is
696 // live to do this.
697 if (IsPixelShader) {
698 // Record I's original position as the entry block.
699 PixelEntryBB = I.getParent();
700
701 Value *const Cond = B.CreateIntrinsic(ID: Intrinsic::amdgcn_ps_live, Args: {});
702 Instruction *const NonHelperTerminator =
703 SplitBlockAndInsertIfThen(Cond, SplitBefore: &I, Unreachable: false, BranchWeights: nullptr, DTU: &DTU, LI: nullptr);
704
705 // Record I's new position as the exit block.
706 PixelExitBB = I.getParent();
707
708 I.moveBefore(InsertPos: NonHelperTerminator->getIterator());
709 B.SetInsertPoint(&I);
710 }
711
712 Type *const Ty = I.getType();
713 Type *Int32Ty = B.getInt32Ty();
714 bool isAtomicFloatingPointTy = Ty->isFloatingPointTy();
715 [[maybe_unused]] const unsigned TyBitWidth = DL.getTypeSizeInBits(Ty);
716
717 // This is the value in the atomic operation we need to combine in order to
718 // reduce the number of atomic operations.
719 Value *V = I.getOperand(i: ValIdx);
720
721 // We need to know how many lanes are active within the wavefront, and we do
722 // this by doing a ballot of active lanes.
723 Type *const WaveTy = B.getIntNTy(N: ST.getWavefrontSize());
724 CallInst *const Ballot = B.CreateIntrinsicWithoutFolding(
725 ID: Intrinsic::amdgcn_ballot, OverloadTypes: WaveTy, Args: B.getTrue());
726
727 // We need to know how many lanes are active within the wavefront that are
728 // below us. If we counted each lane linearly starting from 0, a lane is
729 // below us only if its associated index was less than ours. We do this by
730 // using the mbcnt intrinsic.
731 Value *Mbcnt;
732 if (ST.isWave32()) {
733 Mbcnt =
734 B.CreateIntrinsic(ID: Intrinsic::amdgcn_mbcnt_lo, Args: {Ballot, B.getInt32(C: 0)});
735 } else {
736 Value *const ExtractLo = B.CreateTrunc(V: Ballot, DestTy: Int32Ty);
737 Value *const ExtractHi = B.CreateTrunc(V: B.CreateLShr(LHS: Ballot, RHS: 32), DestTy: Int32Ty);
738 Mbcnt = B.CreateIntrinsic(ID: Intrinsic::amdgcn_mbcnt_lo,
739 Args: {ExtractLo, B.getInt32(C: 0)});
740 Mbcnt = B.CreateIntrinsic(ID: Intrinsic::amdgcn_mbcnt_hi, Args: {ExtractHi, Mbcnt});
741 }
742
743 Function *F = I.getFunction();
744 LLVMContext &C = F->getContext();
745
746 // For atomic sub, perform scan with add operation and allow one lane to
747 // subtract the reduced value later.
748 AtomicRMWInst::BinOp ScanOp = Op;
749 if (Op == AtomicRMWInst::Sub) {
750 ScanOp = AtomicRMWInst::Add;
751 } else if (Op == AtomicRMWInst::FSub) {
752 ScanOp = AtomicRMWInst::FAdd;
753 }
754 Value *Identity = getIdentityValueForAtomicOp(Ty, Op: ScanOp);
755
756 Value *ExclScan = nullptr;
757 Value *NewV = nullptr;
758
759 const bool NeedResult = !I.use_empty();
760
761 BasicBlock *ComputeLoop = nullptr;
762 BasicBlock *ComputeEnd = nullptr;
763 // If we have a divergent value in each lane, we need to combine the value
764 // using DPP.
765 if (ValDivergent) {
766 if (ScanImpl == ScanOptions::DPP) {
767 // First we need to set all inactive invocations to the identity value, so
768 // that they can correctly contribute to the final result.
769 NewV =
770 B.CreateIntrinsic(ID: Intrinsic::amdgcn_set_inactive, OverloadTypes: Ty, Args: {V, Identity});
771 if (!NeedResult && ST.hasPermlane16Insts()) {
772 // On GFX10 the permlanex16 instruction helps us build a reduction
773 // without too many readlanes and writelanes, which are generally bad
774 // for performance.
775 NewV = buildReduction(B, Op: ScanOp, V: NewV, Identity);
776 } else {
777 NewV = buildScan(B, Op: ScanOp, V: NewV, Identity);
778 if (NeedResult)
779 ExclScan = buildShiftRight(B, V: NewV, Identity);
780 // Read the value from the last lane, which has accumulated the values
781 // of each active lane in the wavefront. This will be our new value
782 // which we will provide to the atomic operation.
783 Value *const LastLaneIdx = B.getInt32(C: ST.getWavefrontSize() - 1);
784 NewV = B.CreateIntrinsic(RetTy: Ty, ID: Intrinsic::amdgcn_readlane,
785 Args: {NewV, LastLaneIdx});
786 }
787 // Finally mark the readlanes in the WWM section.
788 NewV = B.CreateIntrinsic(ID: Intrinsic::amdgcn_strict_wwm, OverloadTypes: Ty, Args: NewV);
789 } else if (ScanImpl == ScanOptions::Iterative) {
790 // Alternative implementation for scan
791 ComputeLoop = BasicBlock::Create(Context&: C, Name: "ComputeLoop", Parent: F);
792 ComputeEnd = BasicBlock::Create(Context&: C, Name: "ComputeEnd", Parent: F);
793 std::tie(args&: ExclScan, args&: NewV) = buildScanIteratively(B, Op: ScanOp, Identity, V, I,
794 ComputeLoop, ComputeEnd);
795 } else {
796 llvm_unreachable("Atomic Optimzer is disabled for None strategy");
797 }
798 } else {
799 switch (Op) {
800 default:
801 llvm_unreachable("Unhandled atomic op");
802
803 case AtomicRMWInst::Add:
804 case AtomicRMWInst::Sub: {
805 // The new value we will be contributing to the atomic operation is the
806 // old value times the number of active lanes.
807 Value *const Ctpop = B.CreateIntCast(
808 V: B.CreateUnaryIntrinsic(ID: Intrinsic::ctpop, Op: Ballot), DestTy: Ty, isSigned: false);
809 NewV = buildMul(B, LHS: V, RHS: Ctpop);
810 break;
811 }
812 case AtomicRMWInst::FAdd:
813 case AtomicRMWInst::FSub: {
814 Value *const Ctpop = B.CreateIntCast(
815 V: B.CreateUnaryIntrinsic(ID: Intrinsic::ctpop, Op: Ballot), DestTy: Int32Ty, isSigned: false);
816 Value *const CtpopFP = B.CreateUIToFP(V: Ctpop, DestTy: Ty);
817 NewV = B.CreateFMul(L: V, R: CtpopFP);
818 break;
819 }
820 case AtomicRMWInst::And:
821 case AtomicRMWInst::Or:
822 case AtomicRMWInst::Max:
823 case AtomicRMWInst::Min:
824 case AtomicRMWInst::UMax:
825 case AtomicRMWInst::UMin:
826 case AtomicRMWInst::FMin:
827 case AtomicRMWInst::FMax:
828 // These operations with a uniform value are idempotent: doing the atomic
829 // operation multiple times has the same effect as doing it once.
830 NewV = V;
831 break;
832
833 case AtomicRMWInst::Xor:
834 // The new value we will be contributing to the atomic operation is the
835 // old value times the parity of the number of active lanes.
836 Value *const Ctpop = B.CreateIntCast(
837 V: B.CreateUnaryIntrinsic(ID: Intrinsic::ctpop, Op: Ballot), DestTy: Ty, isSigned: false);
838 NewV = buildMul(B, LHS: V, RHS: B.CreateAnd(LHS: Ctpop, RHS: 1));
839 break;
840 }
841 }
842
843 // We only want a single lane to enter our new control flow, and we do this
844 // by checking if there are any active lanes below us. Only one lane will
845 // have 0 active lanes below us, so that will be the only one to progress.
846 Value *const Cond = B.CreateICmpEQ(LHS: Mbcnt, RHS: B.getInt32(C: 0));
847
848 // Store I's original basic block before we split the block.
849 BasicBlock *const OriginalBB = I.getParent();
850
851 // We need to introduce some new control flow to force a single lane to be
852 // active. We do this by splitting I's basic block at I, and introducing the
853 // new block such that:
854 // entry --> single_lane -\
855 // \------------------> exit
856 Instruction *const SingleLaneTerminator =
857 SplitBlockAndInsertIfThen(Cond, SplitBefore: &I, Unreachable: false, BranchWeights: nullptr, DTU: &DTU, LI: nullptr);
858
859 // At this point, we have split the I's block to allow one lane in wavefront
860 // to update the precomputed reduced value. Also, completed the codegen for
861 // new control flow i.e. iterative loop which perform reduction and scan using
862 // ComputeLoop and ComputeEnd.
863 // For the new control flow, we need to move branch instruction i.e.
864 // terminator created during SplitBlockAndInsertIfThen from I's block to
865 // ComputeEnd block. We also need to set up predecessor to next block when
866 // single lane done updating the final reduced value.
867 BasicBlock *Predecessor = nullptr;
868 if (ValDivergent && ScanImpl == ScanOptions::Iterative) {
869 // Move terminator from I's block to ComputeEnd block.
870 //
871 // OriginalBB is known to have a branch as terminator because
872 // SplitBlockAndInsertIfThen will have inserted one.
873 CondBrInst *Terminator = cast<CondBrInst>(Val: OriginalBB->getTerminator());
874 B.SetInsertPoint(ComputeEnd);
875 Terminator->removeFromParent();
876 B.Insert(I: Terminator);
877
878 // Branch to ComputeLoop Block unconditionally from the I's block for
879 // iterative approach.
880 B.SetInsertPoint(OriginalBB);
881 B.CreateBr(Dest: ComputeLoop);
882
883 // Update the dominator tree for new control flow.
884 SmallVector<DominatorTree::UpdateType, 6> DomTreeUpdates(
885 {{DominatorTree::Insert, OriginalBB, ComputeLoop},
886 {DominatorTree::Insert, ComputeLoop, ComputeEnd}});
887
888 // We're moving the terminator from EntryBB to ComputeEnd, make sure we move
889 // the DT edges as well.
890 for (auto *Succ : Terminator->successors()) {
891 DomTreeUpdates.push_back(Elt: {DominatorTree::Insert, ComputeEnd, Succ});
892 DomTreeUpdates.push_back(Elt: {DominatorTree::Delete, OriginalBB, Succ});
893 }
894
895 DTU.applyUpdates(Updates: DomTreeUpdates);
896
897 Predecessor = ComputeEnd;
898 } else {
899 Predecessor = OriginalBB;
900 }
901 // Move the IR builder into single_lane next.
902 B.SetInsertPoint(SingleLaneTerminator);
903
904 // Clone the original atomic operation into single lane, replacing the
905 // original value with our newly created one.
906 Instruction *const NewI = I.clone();
907 B.Insert(I: NewI);
908 NewI->setOperand(i: ValIdx, Val: NewV);
909
910 // Move the IR builder into exit next, and start inserting just before the
911 // original instruction.
912 B.SetInsertPoint(&I);
913
914 if (NeedResult) {
915 // Create a PHI node to get our new atomic result into the exit block.
916 PHINode *const PHI = B.CreatePHI(Ty, NumReservedValues: 2);
917 PHI->addIncoming(V: PoisonValue::get(T: Ty), BB: Predecessor);
918 PHI->addIncoming(V: NewI, BB: SingleLaneTerminator->getParent());
919
920 // We need to broadcast the value who was the lowest active lane (the first
921 // lane) to all other lanes in the wavefront.
922
923 Value *ReadlaneVal = PHI;
924 if (TyBitWidth < 32)
925 ReadlaneVal = B.CreateZExt(V: PHI, DestTy: B.getInt32Ty());
926
927 Value *BroadcastI = B.CreateIntrinsic(
928 RetTy: ReadlaneVal->getType(), ID: Intrinsic::amdgcn_readfirstlane, Args: ReadlaneVal);
929 if (TyBitWidth < 32)
930 BroadcastI = B.CreateTrunc(V: BroadcastI, DestTy: Ty);
931
932 // Now that we have the result of our single atomic operation, we need to
933 // get our individual lane's slice into the result. We use the lane offset
934 // we previously calculated combined with the atomic result value we got
935 // from the first lane, to get our lane's index into the atomic result.
936 Value *LaneOffset = nullptr;
937 if (ValDivergent) {
938 if (ScanImpl == ScanOptions::DPP) {
939 LaneOffset =
940 B.CreateIntrinsic(ID: Intrinsic::amdgcn_strict_wwm, OverloadTypes: Ty, Args: ExclScan);
941 } else if (ScanImpl == ScanOptions::Iterative) {
942 LaneOffset = ExclScan;
943 } else {
944 llvm_unreachable("Atomic Optimzer is disabled for None strategy");
945 }
946 } else {
947 Mbcnt = isAtomicFloatingPointTy ? B.CreateUIToFP(V: Mbcnt, DestTy: Ty)
948 : B.CreateIntCast(V: Mbcnt, DestTy: Ty, isSigned: false);
949 switch (Op) {
950 default:
951 llvm_unreachable("Unhandled atomic op");
952 case AtomicRMWInst::Add:
953 case AtomicRMWInst::Sub:
954 LaneOffset = buildMul(B, LHS: V, RHS: Mbcnt);
955 break;
956 case AtomicRMWInst::And:
957 case AtomicRMWInst::Or:
958 case AtomicRMWInst::Max:
959 case AtomicRMWInst::Min:
960 case AtomicRMWInst::UMax:
961 case AtomicRMWInst::UMin:
962 case AtomicRMWInst::FMin:
963 case AtomicRMWInst::FMax:
964 LaneOffset = B.CreateSelect(C: Cond, True: Identity, False: V);
965 break;
966 case AtomicRMWInst::Xor:
967 LaneOffset = buildMul(B, LHS: V, RHS: B.CreateAnd(LHS: Mbcnt, RHS: 1));
968 break;
969 case AtomicRMWInst::FAdd:
970 case AtomicRMWInst::FSub: {
971 LaneOffset = B.CreateFMul(L: V, R: Mbcnt);
972 break;
973 }
974 }
975 }
976 Value *Result = buildNonAtomicBinOp(B, Op, LHS: BroadcastI, RHS: LaneOffset);
977 if (isAtomicFloatingPointTy) {
978 // For fadd/fsub the first active lane of LaneOffset should be the
979 // identity (-0.0 for fadd or +0.0 for fsub) but the value we calculated
980 // is V * +0.0 which might have the wrong sign or might be nan (if V is
981 // inf or nan).
982 //
983 // For all floating point ops if the in-memory value was a nan then the
984 // binop we just built might have quieted it or changed its payload.
985 //
986 // Correct all these problems by using BroadcastI as the result in the
987 // first active lane.
988 Result = B.CreateSelect(C: Cond, True: BroadcastI, False: Result);
989 }
990
991 if (IsPixelShader) {
992 // Need a final PHI to reconverge to above the helper lane branch mask.
993 B.SetInsertPoint(TheBB: PixelExitBB, IP: PixelExitBB->getFirstNonPHIIt());
994
995 PHINode *const PHI = B.CreatePHI(Ty, NumReservedValues: 2);
996 PHI->addIncoming(V: PoisonValue::get(T: Ty), BB: PixelEntryBB);
997 PHI->addIncoming(V: Result, BB: I.getParent());
998 I.replaceAllUsesWith(V: PHI);
999 } else {
1000 // Replace the original atomic instruction with the new one.
1001 I.replaceAllUsesWith(V: Result);
1002 }
1003 }
1004
1005 // And delete the original.
1006 I.eraseFromParent();
1007}
1008
1009INITIALIZE_PASS_BEGIN(AMDGPUAtomicOptimizer, DEBUG_TYPE,
1010 "AMDGPU atomic optimizations", false, false)
1011INITIALIZE_PASS_DEPENDENCY(UniformityInfoWrapperPass)
1012INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
1013INITIALIZE_PASS_END(AMDGPUAtomicOptimizer, DEBUG_TYPE,
1014 "AMDGPU atomic optimizations", false, false)
1015
1016FunctionPass *llvm::createAMDGPUAtomicOptimizerPass(ScanOptions ScanStrategy) {
1017 return new AMDGPUAtomicOptimizer(ScanStrategy);
1018}
1019