1//=== lib/CodeGen/GlobalISel/AMDGPUPreLegalizerCombiner.cpp ---------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This pass does combining of machine instructions at the generic MI level,
10// before the legalizer.
11//
12//===----------------------------------------------------------------------===//
13
14#include "AMDGPU.h"
15#include "AMDGPUCombinerHelper.h"
16#include "AMDGPULegalizerInfo.h"
17#include "GCNSubtarget.h"
18#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
19#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
20#include "llvm/CodeGen/GlobalISel/Combiner.h"
21#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
22#include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
23#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
24#include "llvm/CodeGen/GlobalISel/GISelValueTracking.h"
25#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
26#include "llvm/CodeGen/MachineDominators.h"
27#include "llvm/CodeGen/TargetPassConfig.h"
28#include "llvm/Target/TargetMachine.h"
29
30#define GET_GICOMBINER_DEPS
31#include "AMDGPUGenPreLegalizeGICombiner.inc"
32#undef GET_GICOMBINER_DEPS
33
34#define DEBUG_TYPE "amdgpu-prelegalizer-combiner"
35
36using namespace llvm;
37using namespace MIPatternMatch;
38namespace {
39
40#define GET_GICOMBINER_TYPES
41#include "AMDGPUGenPreLegalizeGICombiner.inc"
42#undef GET_GICOMBINER_TYPES
43
44class AMDGPUPreLegalizerCombinerImpl : public Combiner {
45protected:
46 const AMDGPUPreLegalizerCombinerImplRuleConfig &RuleConfig;
47 const GCNSubtarget &STI;
48 const AMDGPUCombinerHelper Helper;
49
50public:
51 AMDGPUPreLegalizerCombinerImpl(
52 MachineFunction &MF, CombinerInfo &CInfo, GISelValueTracking &VT,
53 GISelCSEInfo *CSEInfo,
54 const AMDGPUPreLegalizerCombinerImplRuleConfig &RuleConfig,
55 const GCNSubtarget &STI, MachineDominatorTree *MDT,
56 const LegalizerInfo *LI);
57
58 static const char *getName() { return "AMDGPUPreLegalizerCombinerImpl"; }
59
60 bool tryCombineAllImpl(MachineInstr &MI) const;
61 bool tryCombineAll(MachineInstr &I) const override;
62
63 struct ClampI64ToI16MatchInfo {
64 int64_t Cmp1 = 0;
65 int64_t Cmp2 = 0;
66 Register Origin;
67 };
68
69 bool matchClampI64ToI16(MachineInstr &MI, const MachineRegisterInfo &MRI,
70 const MachineFunction &MF,
71 ClampI64ToI16MatchInfo &MatchInfo) const;
72
73 void applyClampI64ToI16(MachineInstr &MI,
74 const ClampI64ToI16MatchInfo &MatchInfo) const;
75
76private:
77#define GET_GICOMBINER_CLASS_MEMBERS
78#define AMDGPUSubtarget GCNSubtarget
79#include "AMDGPUGenPreLegalizeGICombiner.inc"
80#undef GET_GICOMBINER_CLASS_MEMBERS
81#undef AMDGPUSubtarget
82};
83
84#define GET_GICOMBINER_IMPL
85#define AMDGPUSubtarget GCNSubtarget
86#include "AMDGPUGenPreLegalizeGICombiner.inc"
87#undef AMDGPUSubtarget
88#undef GET_GICOMBINER_IMPL
89
90AMDGPUPreLegalizerCombinerImpl::AMDGPUPreLegalizerCombinerImpl(
91 MachineFunction &MF, CombinerInfo &CInfo, GISelValueTracking &VT,
92 GISelCSEInfo *CSEInfo,
93 const AMDGPUPreLegalizerCombinerImplRuleConfig &RuleConfig,
94 const GCNSubtarget &STI, MachineDominatorTree *MDT, const LegalizerInfo *LI)
95 : Combiner(MF, CInfo, &VT, CSEInfo), RuleConfig(RuleConfig), STI(STI),
96 Helper(Observer, B, /*IsPreLegalize*/ true, &VT, MDT, LI, STI),
97#define GET_GICOMBINER_CONSTRUCTOR_INITS
98#include "AMDGPUGenPreLegalizeGICombiner.inc"
99#undef GET_GICOMBINER_CONSTRUCTOR_INITS
100{
101}
102
103bool AMDGPUPreLegalizerCombinerImpl::tryCombineAll(MachineInstr &MI) const {
104 if (tryCombineAllImpl(I&: MI))
105 return true;
106 return false;
107}
108
109bool AMDGPUPreLegalizerCombinerImpl::matchClampI64ToI16(
110 MachineInstr &MI, const MachineRegisterInfo &MRI, const MachineFunction &MF,
111 ClampI64ToI16MatchInfo &MatchInfo) const {
112 assert(MI.getOpcode() == TargetOpcode::G_TRUNC && "Invalid instruction!");
113
114 // Try to find a pattern where an i64 value should get clamped to short.
115 const LLT SrcType = MRI.getType(Reg: MI.getOperand(i: 1).getReg());
116 if (SrcType != LLT::scalar(SizeInBits: 64))
117 return false;
118
119 const LLT DstType = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
120 if (DstType != LLT::scalar(SizeInBits: 16))
121 return false;
122
123 Register Base;
124
125 // Lo must not exceed Hi: with inverted bounds smin(smax(X, Lo), Hi) is
126 // constant, but the med3 built below would still clamp X to [Hi, Lo].
127 auto IsApplicableForCombine = [&MatchInfo](bool OuterIsMin) -> bool {
128 const int64_t Lo = OuterIsMin ? MatchInfo.Cmp2 : MatchInfo.Cmp1;
129 const int64_t Hi = OuterIsMin ? MatchInfo.Cmp1 : MatchInfo.Cmp2;
130
131 // Range-check first so Hi - Lo below can't overflow.
132 const int64_t Min = std::numeric_limits<int16_t>::min();
133 const int64_t Max = std::numeric_limits<int16_t>::max();
134 if (Lo < Min || Lo > Max || Hi < Min || Hi > Max)
135 return false;
136
137 // Reject inverted bounds, and bounds so close there is no need to clamp.
138 return Hi - Lo > 1;
139 };
140
141 // Try to match a combination of min / max MIR opcodes.
142 if (mi_match(R: MI.getOperand(i: 1).getReg(), MRI,
143 P: m_GSMin(L: m_Reg(R&: Base), R: m_ICst(Cst&: MatchInfo.Cmp1)))) {
144 if (mi_match(R: Base, MRI,
145 P: m_GSMax(L: m_Reg(R&: MatchInfo.Origin), R: m_ICst(Cst&: MatchInfo.Cmp2)))) {
146 return IsApplicableForCombine(/*OuterIsMin=*/true);
147 }
148 }
149
150 if (mi_match(R: MI.getOperand(i: 1).getReg(), MRI,
151 P: m_GSMax(L: m_Reg(R&: Base), R: m_ICst(Cst&: MatchInfo.Cmp1)))) {
152 if (mi_match(R: Base, MRI,
153 P: m_GSMin(L: m_Reg(R&: MatchInfo.Origin), R: m_ICst(Cst&: MatchInfo.Cmp2)))) {
154 return IsApplicableForCombine(/*OuterIsMin=*/false);
155 }
156 }
157
158 return false;
159}
160
161// We want to find a combination of instructions that
162// gets generated when an i64 gets clamped to i16.
163// The corresponding pattern is:
164// G_MAX / G_MAX for i16 <= G_TRUNC i64.
165// This can be efficiently written as following:
166// v_cvt_pk_i16_i32 v0, v0, v1
167// v_med3_i32 v0, Clamp_Min, v0, Clamp_Max
168void AMDGPUPreLegalizerCombinerImpl::applyClampI64ToI16(
169 MachineInstr &MI, const ClampI64ToI16MatchInfo &MatchInfo) const {
170
171 Register Src = MatchInfo.Origin;
172 assert(MI.getMF()->getRegInfo().getType(Src) == LLT::scalar(64));
173 const LLT I32 = LLT::integer(SizeInBits: 32);
174
175 auto Unmerge = B.buildUnmerge(Res: I32, Op: Src);
176
177 assert(MI.getOpcode() != AMDGPU::G_AMDGPU_CVT_PK_I16_I32);
178
179 const LLT V2S16 = LLT::fixed_vector(NumElements: 2, ScalarSizeInBits: 16);
180 auto CvtPk =
181 B.buildInstr(Opc: AMDGPU::G_AMDGPU_CVT_PK_I16_I32, DstOps: {V2S16},
182 SrcOps: {Unmerge.getReg(Idx: 0), Unmerge.getReg(Idx: 1)}, Flags: MI.getFlags());
183
184 auto MinBoundary = std::min(a: MatchInfo.Cmp1, b: MatchInfo.Cmp2);
185 auto MaxBoundary = std::max(a: MatchInfo.Cmp1, b: MatchInfo.Cmp2);
186 auto MinBoundaryDst = B.buildConstant(Res: I32, Val: MinBoundary);
187 auto MaxBoundaryDst = B.buildConstant(Res: I32, Val: MaxBoundary);
188
189 auto Bitcast = B.buildBitcast(Dst: {I32}, Src: CvtPk);
190
191 auto Med3 = B.buildInstr(
192 Opc: AMDGPU::G_AMDGPU_SMED3, DstOps: {I32},
193 SrcOps: {MinBoundaryDst.getReg(Idx: 0), Bitcast.getReg(Idx: 0), MaxBoundaryDst.getReg(Idx: 0)},
194 Flags: MI.getFlags());
195
196 B.buildTrunc(Res: MI.getOperand(i: 0).getReg(), Op: Med3);
197
198 MI.eraseFromParent();
199}
200
201// Pass boilerplate
202// ================
203
204class AMDGPUPreLegalizerCombiner : public MachineFunctionPass {
205public:
206 static char ID;
207
208 AMDGPUPreLegalizerCombiner(bool IsOptNone = false);
209
210 StringRef getPassName() const override {
211 return "AMDGPUPreLegalizerCombiner";
212 }
213
214 bool runOnMachineFunction(MachineFunction &MF) override;
215
216 void getAnalysisUsage(AnalysisUsage &AU) const override;
217
218private:
219 bool IsOptNone;
220 AMDGPUPreLegalizerCombinerImplRuleConfig RuleConfig;
221};
222} // end anonymous namespace
223
224void AMDGPUPreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
225 AU.addRequired<TargetPassConfig>();
226 AU.setPreservesCFG();
227 getSelectionDAGFallbackAnalysisUsage(AU);
228 AU.addRequired<GISelValueTrackingAnalysisLegacy>();
229 AU.addPreserved<GISelValueTrackingAnalysisLegacy>();
230 if (!IsOptNone) {
231 AU.addRequired<MachineDominatorTreeWrapperPass>();
232 }
233
234 AU.addRequired<GISelCSEAnalysisWrapperPass>();
235 AU.addPreserved<GISelCSEAnalysisWrapperPass>();
236 MachineFunctionPass::getAnalysisUsage(AU);
237}
238
239AMDGPUPreLegalizerCombiner::AMDGPUPreLegalizerCombiner(bool IsOptNone)
240 : MachineFunctionPass(ID), IsOptNone(IsOptNone) {
241 if (!RuleConfig.parseCommandLineOption())
242 report_fatal_error(reason: "Invalid rule identifier");
243}
244
245bool AMDGPUPreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
246 if (MF.getProperties().hasFailedISel())
247 return false;
248 auto *TPC = &getAnalysis<TargetPassConfig>();
249 const Function &F = MF.getFunction();
250 bool EnableOpt =
251 MF.getTarget().getOptLevel() != CodeGenOptLevel::None && !skipFunction(F);
252 GISelValueTracking *VT =
253 &getAnalysis<GISelValueTrackingAnalysisLegacy>().get(MF);
254
255 // Enable CSE.
256 GISelCSEAnalysisWrapper &Wrapper =
257 getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
258 auto *CSEInfo = &Wrapper.get(CSEOpt: TPC->getCSEConfig());
259
260 const GCNSubtarget &STI = MF.getSubtarget<GCNSubtarget>();
261 MachineDominatorTree *MDT =
262 IsOptNone ? nullptr
263 : &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
264 CombinerInfo CInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
265 nullptr, EnableOpt, F.hasOptSize(), F.hasMinSize());
266 // Disable fixed-point iteration to reduce compile-time
267 CInfo.MaxIterations = 1;
268 CInfo.ObserverLvl = CombinerInfo::ObserverLevel::SinglePass;
269 // This is the first Combiner, so the input IR might contain dead
270 // instructions.
271 CInfo.EnableFullDCE = true;
272 AMDGPUPreLegalizerCombinerImpl Impl(MF, CInfo, *VT, CSEInfo, RuleConfig, STI,
273 MDT, STI.getLegalizerInfo());
274 return Impl.combineMachineInstrs();
275}
276
277char AMDGPUPreLegalizerCombiner::ID = 0;
278INITIALIZE_PASS_BEGIN(AMDGPUPreLegalizerCombiner, DEBUG_TYPE,
279 "Combine AMDGPU machine instrs before legalization",
280 false, false)
281INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
282INITIALIZE_PASS_DEPENDENCY(GISelValueTrackingAnalysisLegacy)
283INITIALIZE_PASS_END(AMDGPUPreLegalizerCombiner, DEBUG_TYPE,
284 "Combine AMDGPU machine instrs before legalization", false,
285 false)
286
287FunctionPass *llvm::createAMDGPUPreLegalizeCombiner(bool IsOptNone) {
288 return new AMDGPUPreLegalizerCombiner(IsOptNone);
289}
290