1//===-- GCNPreRALongBranchReg.cpp ----------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8// \file
9// \brief Pass to estimate pre RA branch size and reserve a pair of SGPRs if
10// there is a long branch. Branch size at this point is difficult to track since
11// we have no idea what spills will be inserted later on. We just assume 8 bytes
12// per instruction to compute approximations without computing the actual
13// instruction size to see if we're in the neighborhood of the maximum branch
14// distrance threshold tuning of what is considered "long" is handled through
15// amdgpu-long-branch-factor cl argument which sets LongBranchFactor.
16//===----------------------------------------------------------------------===//
17#include "GCNPreRALongBranchReg.h"
18#include "AMDGPU.h"
19#include "GCNSubtarget.h"
20#include "SIMachineFunctionInfo.h"
21#include "llvm/CodeGen/MachineFunctionPass.h"
22
23using namespace llvm;
24
25#define DEBUG_TYPE "amdgpu-pre-ra-long-branch-reg"
26
27namespace {
28
29static cl::opt<double> LongBranchFactor(
30 "amdgpu-long-branch-factor", cl::init(Val: 1.0), cl::Hidden,
31 cl::desc("Factor to apply to what qualifies as a long branch "
32 "to reserve a pair of scalar registers. If this value "
33 "is 0 the long branch registers are never reserved. As this "
34 "value grows the greater chance the branch distance will fall "
35 "within the threshold and the registers will be marked to be "
36 "reserved. We lean towards always reserving a register for "
37 "long jumps"));
38
39class GCNPreRALongBranchReg {
40
41 struct BasicBlockInfo {
42 // Offset - Distance from the beginning of the function to the beginning
43 // of this basic block.
44 uint64_t Offset = 0;
45 // Size - Size of the basic block in bytes
46 uint64_t Size = 0;
47 };
48 void generateBlockInfo(MachineFunction &MF,
49 SmallVectorImpl<BasicBlockInfo> &BlockInfo);
50
51public:
52 GCNPreRALongBranchReg() = default;
53 bool run(MachineFunction &MF);
54};
55
56class GCNPreRALongBranchRegLegacy : public MachineFunctionPass {
57public:
58 static char ID;
59 GCNPreRALongBranchRegLegacy() : MachineFunctionPass(ID) {}
60
61 bool runOnMachineFunction(MachineFunction &MF) override {
62 return GCNPreRALongBranchReg().run(MF);
63 }
64
65 StringRef getPassName() const override {
66 return "AMDGPU Pre-RA Long Branch Reg";
67 }
68
69 void getAnalysisUsage(AnalysisUsage &AU) const override {
70 AU.setPreservesAll();
71 MachineFunctionPass::getAnalysisUsage(AU);
72 }
73};
74} // End anonymous namespace.
75
76char GCNPreRALongBranchRegLegacy::ID = 0;
77
78INITIALIZE_PASS(GCNPreRALongBranchRegLegacy, DEBUG_TYPE,
79 "AMDGPU Pre-RA Long Branch Reg", false, false)
80
81char &llvm::GCNPreRALongBranchRegID = GCNPreRALongBranchRegLegacy::ID;
82void GCNPreRALongBranchReg::generateBlockInfo(
83 MachineFunction &MF, SmallVectorImpl<BasicBlockInfo> &BlockInfo) {
84
85 BlockInfo.resize(N: MF.getNumBlockIDs());
86
87 // Approximate the size of all basic blocks by just
88 // assuming 8 bytes per instruction
89 for (const MachineBasicBlock &MBB : MF) {
90 uint64_t NumInstr = 0;
91 // Loop through the basic block and add up all non-debug
92 // non-meta instructions
93 for (const MachineInstr &MI : MBB) {
94 // isMetaInstruction is a superset of isDebugIstr
95 if (MI.isMetaInstruction())
96 continue;
97 NumInstr += 1;
98 }
99 // Approximate size as just 8 bytes per instruction
100 BlockInfo[MBB.getNumber()].Size = 8 * NumInstr;
101 }
102 uint64_t PrevNum = (&MF)->begin()->getNumber();
103 for (auto &MBB :
104 make_range(x: std::next(x: MachineFunction::iterator((&MF)->begin())),
105 y: (&MF)->end())) {
106 uint64_t Num = MBB.getNumber();
107 // Compute the offset immediately following this block.
108 BlockInfo[Num].Offset = BlockInfo[PrevNum].Offset + BlockInfo[PrevNum].Size;
109 PrevNum = Num;
110 }
111}
112
113bool GCNPreRALongBranchReg::run(MachineFunction &MF) {
114 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
115 const SIInstrInfo *TII = STM.getInstrInfo();
116 const SIRegisterInfo *TRI = STM.getRegisterInfo();
117 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
118 MachineRegisterInfo &MRI = MF.getRegInfo();
119
120 // For now, reserve highest available SGPR pair. After RA,
121 // shift down to a lower unused pair of SGPRs
122 // If all registers are used, then findUnusedRegister will return
123 // AMDGPU::NoRegister.
124 constexpr bool ReserveHighestRegister = true;
125 Register LongBranchReservedReg = TRI->findUnusedRegister(
126 MRI, RC: &AMDGPU::SGPR_64RegClass, MF, ReserveHighestVGPR: ReserveHighestRegister);
127 if (!LongBranchReservedReg)
128 return false;
129
130 // Approximate code size and offsets of each basic block
131 SmallVector<BasicBlockInfo, 16> BlockInfo;
132 generateBlockInfo(MF, BlockInfo);
133
134 for (const MachineBasicBlock &MBB : MF) {
135 MachineBasicBlock::const_iterator Last = MBB.getLastNonDebugInstr();
136 if (Last == MBB.end() || !Last->isUnconditionalBranch())
137 continue;
138 MachineBasicBlock *DestBB = TII->getBranchDestBlock(MI: *Last);
139 uint64_t BlockDistance = static_cast<uint64_t>(
140 LongBranchFactor * BlockInfo[DestBB->getNumber()].Offset);
141 // If the distance falls outside the threshold assume it is a long branch
142 // and we need to reserve the registers
143 if (!TII->isBranchOffsetInRange(BranchOpc: Last->getOpcode(), BrOffset: BlockDistance)) {
144 MFI->setLongBranchReservedReg(LongBranchReservedReg);
145 return true;
146 }
147 }
148 return false;
149}
150
151PreservedAnalyses
152GCNPreRALongBranchRegPass::run(MachineFunction &MF,
153 MachineFunctionAnalysisManager &MFAM) {
154 GCNPreRALongBranchReg().run(MF);
155 return PreservedAnalyses::all();
156}
157