1//===-- SIModeRegister.cpp - Mode Register --------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This pass inserts changes to the Mode register settings as required.
10/// Note that currently it only deals with the Double Precision Floating Point
11/// rounding mode setting, but is intended to be generic enough to be easily
12/// expanded.
13///
14//===----------------------------------------------------------------------===//
15//
16#include "AMDGPU.h"
17#include "GCNSubtarget.h"
18#include "llvm/ADT/Statistic.h"
19#include "llvm/CodeGen/MachineFunctionPass.h"
20#include <optional>
21#include <queue>
22
23#define DEBUG_TYPE "si-mode-register"
24
25STATISTIC(NumSetregInserted, "Number of setreg of mode register inserted.");
26
27using namespace llvm;
28
29struct Status {
30 // Mask is a bitmask where a '1' indicates the corresponding Mode bit has a
31 // known value
32 unsigned Mask = 0;
33 unsigned Mode = 0;
34
35 Status() = default;
36
37 Status(unsigned NewMask, unsigned NewMode) : Mask(NewMask), Mode(NewMode) {
38 Mode &= Mask;
39 };
40
41 // merge two status values such that only values that don't conflict are
42 // preserved
43 Status merge(const Status &S) const {
44 return Status((Mask | S.Mask), ((Mode & ~S.Mask) | (S.Mode & S.Mask)));
45 }
46
47 // merge an unknown value by using the unknown value's mask to remove bits
48 // from the result
49 Status mergeUnknown(unsigned newMask) {
50 return Status(Mask & ~newMask, Mode & ~newMask);
51 }
52
53 // intersect two Status values to produce a mode and mask that is a subset
54 // of both values
55 Status intersect(const Status &S) const {
56 unsigned NewMask = (Mask & S.Mask) & (Mode ^ ~S.Mode);
57 unsigned NewMode = (Mode & NewMask);
58 return Status(NewMask, NewMode);
59 }
60
61 // produce the delta required to change the Mode to the required Mode
62 Status delta(const Status &S) const {
63 return Status((S.Mask & (Mode ^ S.Mode)) | (~Mask & S.Mask), S.Mode);
64 }
65
66 bool operator==(const Status &S) const {
67 return (Mask == S.Mask) && (Mode == S.Mode);
68 }
69
70 bool operator!=(const Status &S) const { return !(*this == S); }
71
72 bool isCompatible(Status &S) {
73 return ((Mask & S.Mask) == S.Mask) && ((Mode & S.Mask) == S.Mode);
74 }
75
76 bool isCombinable(Status &S) { return !(Mask & S.Mask) || isCompatible(S); }
77};
78
79class BlockData {
80public:
81 // The Status that represents the mode register settings required by the
82 // FirstInsertionPoint (if any) in this block. Calculated in Phase 1.
83 Status Require;
84
85 // The Status that represents the net changes to the Mode register made by
86 // this block, Calculated in Phase 1.
87 Status Change;
88
89 // The Status that represents the mode register settings on exit from this
90 // block. Calculated in Phase 2.
91 Status Exit;
92
93 // The Status that represents the intersection of exit Mode register settings
94 // from all predecessor blocks. Calculated in Phase 2, and used by Phase 3.
95 Status Pred;
96
97 // In Phase 1 we record the first instruction that has a mode requirement,
98 // which is used in Phase 3 if we need to insert a mode change.
99 MachineInstr *FirstInsertionPoint = nullptr;
100
101 // Call and return sites, each paired with the block local mode changes that
102 // precede it. Phase 3 merges the pair with Pred to get the mode at the site.
103 SmallVector<std::pair<MachineInstr *, Status>, 2> BoundarySites;
104
105 // A flag to indicate whether an Exit value has been set (we can't tell by
106 // examining the Exit value itself as all values may be valid results).
107 bool ExitSet = false;
108
109 BlockData() = default;
110};
111
112namespace {
113
114class SIModeRegister {
115public:
116 std::vector<std::unique_ptr<BlockData>> BlockInfo;
117 std::queue<MachineBasicBlock *> Phase2List;
118
119 // The default mode register setting currently only caters for the floating
120 // point double precision rounding mode.
121 // We currently assume the default rounding mode is Round to Nearest
122 // NOTE: this should come from a per function rounding mode setting once such
123 // a setting exists.
124 unsigned DefaultMode = FP_ROUND_ROUND_TO_NEAREST;
125 Status DefaultStatus =
126 Status(FP_ROUND_MODE_DP(0x3), FP_ROUND_MODE_DP(DefaultMode));
127
128 bool Changed = false;
129
130 // Set during Phase 1. A restore at a boundary would undo an explicit request,
131 // so the mixed case is not handled.
132 bool AnyNonDefaultMode = false;
133 bool AnyWritesRoundMode = false;
134
135 bool run(MachineFunction &MF);
136
137 void processBlockPhase1(MachineBasicBlock &MBB, const SIInstrInfo *TII);
138
139 void processBlockPhase2(MachineBasicBlock &MBB, const SIInstrInfo *TII);
140
141 void processBlockPhase3(MachineBasicBlock &MBB, const SIInstrInfo *TII);
142
143 Status getInstructionMode(MachineInstr &MI, const SIInstrInfo *TII);
144
145 void insertSetreg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
146 const SIInstrInfo *TII, Status InstrMode);
147};
148
149class SIModeRegisterLegacy : public MachineFunctionPass {
150public:
151 static char ID;
152
153 SIModeRegisterLegacy() : MachineFunctionPass(ID) {}
154
155 bool runOnMachineFunction(MachineFunction &MF) override;
156
157 void getAnalysisUsage(AnalysisUsage &AU) const override {
158 AU.setPreservesCFG();
159 MachineFunctionPass::getAnalysisUsage(AU);
160 }
161};
162} // End anonymous namespace.
163
164INITIALIZE_PASS(SIModeRegisterLegacy, DEBUG_TYPE,
165 "Insert required mode register values", false, false)
166
167char SIModeRegisterLegacy::ID = 0;
168
169char &llvm::SIModeRegisterID = SIModeRegisterLegacy::ID;
170
171FunctionPass *llvm::createSIModeRegisterPass() {
172 return new SIModeRegisterLegacy();
173}
174
175static bool isFPTruncRoundPseudo(const MachineInstr &MI) {
176 switch (MI.getOpcode()) {
177 case AMDGPU::FPTRUNC_ROUND_F16_F32_PSEUDO:
178 case AMDGPU::FPTRUNC_ROUND_F16_F32_PSEUDO_fake16_e32:
179 case AMDGPU::FPTRUNC_ROUND_F16_F32_PSEUDO_t16_e64:
180 case AMDGPU::FPTRUNC_ROUND_F32_F64_PSEUDO:
181 case AMDGPU::FPTRUNC_ROUND_F16_F32_SALU_PSEUDO:
182 return true;
183 default:
184 return false;
185 }
186}
187
188// The opcodes for which getInstructionMode below returns a non-default Status.
189static bool mayNeedNonDefaultMode(const MachineInstr &MI) {
190 switch (MI.getOpcode()) {
191 case AMDGPU::V_INTERP_P1LL_F16:
192 case AMDGPU::V_INTERP_P1LV_F16:
193 case AMDGPU::V_INTERP_P2_F16:
194 return true;
195 default:
196 return isFPTruncRoundPseudo(MI);
197 }
198}
199
200// Returns the {offset, mask} of the mode field an explicit setreg writes.
201static std::optional<std::pair<unsigned, unsigned>>
202getModeSetregField(const MachineInstr &MI, const SIInstrInfo *TII) {
203 switch (MI.getOpcode()) {
204 case AMDGPU::S_SETREG_B32:
205 case AMDGPU::S_SETREG_B32_mode:
206 case AMDGPU::S_SETREG_IMM32_B32:
207 case AMDGPU::S_SETREG_IMM32_B32_mode:
208 break;
209 default:
210 return std::nullopt;
211 }
212 using namespace AMDGPU::Hwreg;
213 unsigned Dst = TII->getNamedOperand(MI, OperandName: AMDGPU::OpName::simm16)->getImm();
214 auto [Id, Offset, Width] = HwregEncoding::decode(Encoded: Dst);
215 if (Id != ID_MODE)
216 return std::nullopt;
217 return std::make_pair(x&: Offset, y: maskTrailingOnes<unsigned>(N: Width) << Offset);
218}
219
220// The wave-ending opcodes are isReturn too, but have no caller to restore for.
221static bool isReturnToCaller(const MachineInstr &MI) {
222 switch (MI.getOpcode()) {
223 case AMDGPU::S_ENDPGM:
224 case AMDGPU::S_ENDPGM_SAVED:
225 case AMDGPU::S_ENDPGM_ORDERED_PS_DONE:
226 return false;
227 default:
228 return MI.isReturn();
229 }
230}
231
232// Determine the Mode register setting required for this instruction.
233// Instructions which don't use the Mode register return a null Status.
234// Note this currently only deals with instructions that use the floating point
235// double precision setting.
236Status SIModeRegister::getInstructionMode(MachineInstr &MI,
237 const SIInstrInfo *TII) {
238 unsigned Opcode = MI.getOpcode();
239 if (TII->usesFPDPRounding(MI) || isFPTruncRoundPseudo(MI)) {
240 switch (Opcode) {
241 case AMDGPU::V_INTERP_P1LL_F16:
242 case AMDGPU::V_INTERP_P1LV_F16:
243 case AMDGPU::V_INTERP_P2_F16:
244 // f16 interpolation instructions need double precision round to zero
245 return Status(FP_ROUND_MODE_DP(3),
246 FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_ZERO));
247 case AMDGPU::FPTRUNC_ROUND_F16_F32_PSEUDO: {
248 unsigned Mode = MI.getOperand(i: 2).getImm();
249 MI.removeOperand(OpNo: 2);
250 MI.setDesc(TII->get(Opcode: AMDGPU::V_CVT_F16_F32_e32));
251 return Status(FP_ROUND_MODE_DP(3), FP_ROUND_MODE_DP(Mode));
252 }
253 case AMDGPU::FPTRUNC_ROUND_F16_F32_PSEUDO_fake16_e32: {
254 unsigned Mode = MI.getOperand(i: 2).getImm();
255 MI.removeOperand(OpNo: 2);
256 MI.setDesc(TII->get(Opcode: AMDGPU::V_CVT_F16_F32_fake16_e32));
257 return Status(FP_ROUND_MODE_DP(3), FP_ROUND_MODE_DP(Mode));
258 }
259 case AMDGPU::FPTRUNC_ROUND_F16_F32_PSEUDO_t16_e64: {
260 unsigned Mode = MI.getOperand(i: 6).getImm();
261 MI.removeOperand(OpNo: 6);
262 MI.setDesc(TII->get(Opcode: AMDGPU::V_CVT_F16_F32_t16_e64));
263 return Status(FP_ROUND_MODE_DP(3), FP_ROUND_MODE_DP(Mode));
264 }
265 case AMDGPU::FPTRUNC_ROUND_F32_F64_PSEUDO: {
266 unsigned Mode = MI.getOperand(i: 2).getImm();
267 MI.removeOperand(OpNo: 2);
268 MI.setDesc(TII->get(Opcode: AMDGPU::V_CVT_F32_F64_e32));
269 return Status(FP_ROUND_MODE_DP(3), FP_ROUND_MODE_DP(Mode));
270 }
271 case AMDGPU::FPTRUNC_ROUND_F16_F32_SALU_PSEUDO: {
272 unsigned Mode = MI.getOperand(i: 2).getImm();
273 MI.removeOperand(OpNo: 2);
274 MI.setDesc(TII->get(Opcode: AMDGPU::S_CVT_F16_F32));
275 return Status(FP_ROUND_MODE_DP(3), FP_ROUND_MODE_DP(Mode));
276 }
277 default:
278 return DefaultStatus;
279 }
280 }
281 return Status();
282}
283
284// Insert a setreg instruction to update the Mode register.
285// It is possible (though unlikely) for an instruction to require a change to
286// the value of disjoint parts of the Mode register when we don't know the
287// value of the intervening bits. In that case we need to use more than one
288// setreg instruction.
289void SIModeRegister::insertSetreg(MachineBasicBlock &MBB,
290 MachineBasicBlock::iterator I,
291 const SIInstrInfo *TII, Status InstrMode) {
292 while (InstrMode.Mask) {
293 unsigned Offset = llvm::countr_zero<unsigned>(Val: InstrMode.Mask);
294 unsigned Width = llvm::countr_one<unsigned>(Value: InstrMode.Mask >> Offset);
295 unsigned Value = (InstrMode.Mode >> Offset) & ((1 << Width) - 1);
296 using namespace AMDGPU::Hwreg;
297 BuildMI(BB&: MBB, I, MIMD: nullptr, MCID: TII->get(Opcode: AMDGPU::S_SETREG_IMM32_B32))
298 .addImm(Val: Value)
299 .addImm(Val: HwregEncoding::encode(Values: ID_MODE, Values: Offset, Values: Width));
300 ++NumSetregInserted;
301 Changed = true;
302 InstrMode.Mask &= ~(((1 << Width) - 1) << Offset);
303 }
304}
305
306// In Phase 1 we iterate through the instructions of the block and for each
307// instruction we get its mode usage. If the instruction uses the Mode register
308// we:
309// - update the Change status, which tracks the changes to the Mode register
310// made by this block
311// - if this instruction's requirements are compatible with the current setting
312// of the Mode register we merge the modes
313// - if it isn't compatible and an InsertionPoint isn't set, then we set the
314// InsertionPoint to the current instruction, and we remember the current
315// mode
316// - if it isn't compatible and InsertionPoint is set we insert a seteg before
317// that instruction (unless this instruction forms part of the block's
318// entry requirements in which case the insertion is deferred until Phase 3
319// when predecessor exit values are known), and move the insertion point to
320// this instruction
321// - if this is a setreg instruction we treat it as an incompatible instruction.
322// This is sub-optimal but avoids some nasty corner cases, and is expected to
323// occur very rarely.
324// - on exit we have set the Require, Change, and initial Exit modes.
325void SIModeRegister::processBlockPhase1(MachineBasicBlock &MBB,
326 const SIInstrInfo *TII) {
327 auto NewInfo = std::make_unique<BlockData>();
328 MachineInstr *InsertionPoint = nullptr;
329 // RequirePending is used to indicate whether we are collecting the initial
330 // requirements for the block, and need to defer the first InsertionPoint to
331 // Phase 3. It is set to false once we have set FirstInsertionPoint, or when
332 // we discover an explicit setreg that means this block doesn't have any
333 // initial requirements.
334 bool RequirePending = true;
335 Status IPChange;
336 for (MachineInstr &MI : MBB) {
337 // getInstructionMode rewrites the pseudos, so classify MI before the call.
338 AnyNonDefaultMode |= mayNeedNonDefaultMode(MI);
339 AnyWritesRoundMode |= MI.getOpcode() == AMDGPU::S_ROUND_MODE;
340 Status InstrMode = getInstructionMode(MI, TII);
341 if (auto Field = getModeSetregField(MI, TII)) {
342 // We preserve any explicit mode register setreg instruction we encounter,
343 // as we assume it has been inserted by a higher authority (this is
344 // likely to be a very rare occurrence).
345 auto [Offset, Mask] = *Field;
346 AnyWritesRoundMode |= (Mask & FP_ROUND_MODE_DP(0x3)) != 0;
347
348 // If an InsertionPoint is set we will insert a setreg there.
349 if (InsertionPoint) {
350 insertSetreg(MBB, I: InsertionPoint, TII, InstrMode: IPChange.delta(S: NewInfo->Change));
351 InsertionPoint = nullptr;
352 }
353 // If this is an immediate then we know the value being set, but if it is
354 // not an immediate then we treat the modified bits of the mode register
355 // as unknown.
356 if (MI.getOpcode() == AMDGPU::S_SETREG_IMM32_B32 ||
357 MI.getOpcode() == AMDGPU::S_SETREG_IMM32_B32_mode) {
358 unsigned Val = TII->getNamedOperand(MI, OperandName: AMDGPU::OpName::imm)->getImm();
359 unsigned Mode = (Val << Offset) & Mask;
360 Status Setreg = Status(Mask, Mode);
361 // If we haven't already set the initial requirements for the block we
362 // don't need to as the requirements start from this explicit setreg.
363 RequirePending = false;
364 NewInfo->Change = NewInfo->Change.merge(S: Setreg);
365 } else {
366 NewInfo->Change = NewInfo->Change.mergeUnknown(newMask: Mask);
367 }
368 } else if (MI.isCall() || isReturnToCaller(MI)) {
369 // Whether a restore is needed is a whole function property, so only
370 // record the site here. Change is unaffected: Phase 3 pairs any restore
371 // it inserts with a re-set after the call.
372 NewInfo->BoundarySites.emplace_back(Args: &MI, Args&: NewInfo->Change);
373 } else if (!NewInfo->Change.isCompatible(S&: InstrMode)) {
374 // This instruction uses the Mode register and its requirements aren't
375 // compatible with the current mode.
376 if (InsertionPoint) {
377 // If the required mode change cannot be included in the current
378 // InsertionPoint changes, we need a setreg and start a new
379 // InsertionPoint.
380 if (!IPChange.delta(S: NewInfo->Change).isCombinable(S&: InstrMode)) {
381 if (RequirePending) {
382 // This is the first insertionPoint in the block so we will defer
383 // the insertion of the setreg to Phase 3 where we know whether or
384 // not it is actually needed.
385 NewInfo->FirstInsertionPoint = InsertionPoint;
386 NewInfo->Require = NewInfo->Change;
387 RequirePending = false;
388 } else {
389 insertSetreg(MBB, I: InsertionPoint, TII,
390 InstrMode: IPChange.delta(S: NewInfo->Change));
391 IPChange = NewInfo->Change;
392 }
393 // Set the new InsertionPoint
394 InsertionPoint = &MI;
395 }
396 NewInfo->Change = NewInfo->Change.merge(S: InstrMode);
397 } else {
398 // No InsertionPoint is currently set - this is either the first in
399 // the block or we have previously seen an explicit setreg.
400 InsertionPoint = &MI;
401 IPChange = NewInfo->Change;
402 NewInfo->Change = NewInfo->Change.merge(S: InstrMode);
403 }
404 }
405 }
406 if (RequirePending) {
407 // If we haven't yet set the initial requirements for the block we set them
408 // now.
409 NewInfo->FirstInsertionPoint = InsertionPoint;
410 NewInfo->Require = NewInfo->Change;
411 } else if (InsertionPoint) {
412 // We need to insert a setreg at the InsertionPoint
413 insertSetreg(MBB, I: InsertionPoint, TII, InstrMode: IPChange.delta(S: NewInfo->Change));
414 }
415 NewInfo->Exit = NewInfo->Change;
416 BlockInfo[MBB.getNumber()] = std::move(NewInfo);
417}
418
419// In Phase 2 we revisit each block and calculate the common Mode register
420// value provided by all predecessor blocks. If the Exit value for the block
421// is changed, then we add the successor blocks to the worklist so that the
422// exit value is propagated.
423void SIModeRegister::processBlockPhase2(MachineBasicBlock &MBB,
424 const SIInstrInfo *TII) {
425 bool RevisitRequired = false;
426 bool ExitSet = false;
427 unsigned ThisBlock = MBB.getNumber();
428 if (MBB.pred_empty()) {
429 // There are no predecessors, so use the default starting status.
430 BlockInfo[ThisBlock]->Pred = DefaultStatus;
431 ExitSet = true;
432 } else {
433 // Build a status that is common to all the predecessors by intersecting
434 // all the predecessor exit status values.
435 // Mask bits (which represent the Mode bits with a known value) can only be
436 // added by explicit SETREG instructions or the initial default value -
437 // the intersection process may remove Mask bits.
438 // If we find a predecessor that has not yet had an exit value determined
439 // (this can happen for example if a block is its own predecessor) we defer
440 // use of that value as the Mask will be all zero, and we will revisit this
441 // block again later (unless the only predecessor without an exit value is
442 // this block).
443 MachineBasicBlock::pred_iterator P = MBB.pred_begin(), E = MBB.pred_end();
444 MachineBasicBlock &PB = *(*P);
445 unsigned PredBlock = PB.getNumber();
446 if ((ThisBlock == PredBlock) && (std::next(x: P) == E)) {
447 BlockInfo[ThisBlock]->Pred = DefaultStatus;
448 ExitSet = true;
449 } else if (BlockInfo[PredBlock]->ExitSet) {
450 BlockInfo[ThisBlock]->Pred = BlockInfo[PredBlock]->Exit;
451 ExitSet = true;
452 } else if (PredBlock != ThisBlock)
453 RevisitRequired = true;
454
455 for (P = std::next(x: P); P != E; P = std::next(x: P)) {
456 MachineBasicBlock *Pred = *P;
457 unsigned PredBlock = Pred->getNumber();
458 if (BlockInfo[PredBlock]->ExitSet) {
459 if (BlockInfo[ThisBlock]->ExitSet) {
460 BlockInfo[ThisBlock]->Pred =
461 BlockInfo[ThisBlock]->Pred.intersect(S: BlockInfo[PredBlock]->Exit);
462 } else {
463 BlockInfo[ThisBlock]->Pred = BlockInfo[PredBlock]->Exit;
464 }
465 ExitSet = true;
466 } else if (PredBlock != ThisBlock)
467 RevisitRequired = true;
468 }
469 }
470 Status TmpStatus =
471 BlockInfo[ThisBlock]->Pred.merge(S: BlockInfo[ThisBlock]->Change);
472 if (BlockInfo[ThisBlock]->Exit != TmpStatus) {
473 BlockInfo[ThisBlock]->Exit = TmpStatus;
474 // Add the successors to the work list so we can propagate the changed exit
475 // status.
476 for (MachineBasicBlock *Succ : MBB.successors())
477 Phase2List.push(x: Succ);
478 }
479 BlockInfo[ThisBlock]->ExitSet = ExitSet;
480 if (RevisitRequired)
481 Phase2List.push(x: &MBB);
482}
483
484// In Phase 3 we revisit each block and if it has an insertion point defined we
485// check whether the predecessor mode meets the block's entry requirements. If
486// not we insert an appropriate setreg instruction to modify the Mode register.
487void SIModeRegister::processBlockPhase3(MachineBasicBlock &MBB,
488 const SIInstrInfo *TII) {
489 unsigned ThisBlock = MBB.getNumber();
490 if (!BlockInfo[ThisBlock]->Pred.isCompatible(S&: BlockInfo[ThisBlock]->Require)) {
491 Status Delta =
492 BlockInfo[ThisBlock]->Pred.delta(S: BlockInfo[ThisBlock]->Require);
493 if (BlockInfo[ThisBlock]->FirstInsertionPoint)
494 insertSetreg(MBB, I: BlockInfo[ThisBlock]->FirstInsertionPoint, TII, InstrMode: Delta);
495 else
496 insertSetreg(MBB, I: &MBB.instr_front(), TII, InstrMode: Delta);
497 }
498
499 // Restore the default at the sites recorded in Phase 1.
500 if (!AnyNonDefaultMode || AnyWritesRoundMode)
501 return;
502 for (auto &[MI, ChangeAtSite] : BlockInfo[ThisBlock]->BoundarySites) {
503 Status AtSite = BlockInfo[ThisBlock]->Pred.merge(S: ChangeAtSite);
504 if (AtSite.isCompatible(S&: DefaultStatus))
505 continue;
506 insertSetreg(MBB, I: MI, TII, InstrMode: AtSite.delta(S: DefaultStatus));
507 // Phase 1 modelled the site as mode preserving, so put the mode back.
508 if (!MI->isTerminator()) {
509 insertSetreg(MBB, I: std::next(x: MI->getIterator()), TII,
510 InstrMode: DefaultStatus.delta(S: AtSite));
511 }
512 }
513}
514
515bool SIModeRegisterLegacy::runOnMachineFunction(MachineFunction &MF) {
516 return SIModeRegister().run(MF);
517}
518
519PreservedAnalyses SIModeRegisterPass::run(MachineFunction &MF,
520 MachineFunctionAnalysisManager &AM) {
521 if (!SIModeRegister().run(MF))
522 return PreservedAnalyses::all();
523 auto PA = getMachineFunctionPassPreservedAnalyses();
524 PA.preserveSet<CFGAnalyses>();
525 return PA;
526}
527
528bool SIModeRegister::run(MachineFunction &MF) {
529 // Constrained FP intrinsics are used to support non-default rounding modes.
530 // strictfp attribute is required to mark functions with strict FP semantics
531 // having constrained FP intrinsics. This pass fixes up operations that uses
532 // a non-default rounding mode for non-strictfp functions. But it should not
533 // assume or modify any default rounding modes in case of strictfp functions.
534 const Function &F = MF.getFunction();
535 if (F.hasFnAttribute(Kind: llvm::Attribute::StrictFP))
536 return Changed;
537 BlockInfo.resize(new_size: MF.getNumBlockIDs());
538 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
539 const SIInstrInfo *TII = ST.getInstrInfo();
540
541 // Processing is performed in a number of phases
542
543 // Phase 1 - determine the initial mode required by each block, and add setreg
544 // instructions for intra block requirements.
545 for (MachineBasicBlock &BB : MF)
546 processBlockPhase1(MBB&: BB, TII);
547
548 // Phase 2 - determine the exit mode from each block. We add all blocks to the
549 // list here, but will also add any that need to be revisited during Phase 2
550 // processing.
551 for (MachineBasicBlock &BB : MF)
552 Phase2List.push(x: &BB);
553 while (!Phase2List.empty()) {
554 processBlockPhase2(MBB&: *Phase2List.front(), TII);
555 Phase2List.pop();
556 }
557
558 // Phase 3 - add an initial setreg to each block where the required entry mode
559 // is not satisfied by the exit mode of all its predecessors.
560 for (MachineBasicBlock &BB : MF)
561 processBlockPhase3(MBB&: BB, TII);
562
563 BlockInfo.clear();
564
565 return Changed;
566}
567