1//===-- SIProgramInfo.cpp ----------------------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10///
11/// The SIProgramInfo tracks resource usage and hardware flags for kernels and
12/// entry functions.
13//
14//===----------------------------------------------------------------------===//
15//
16
17#include "SIProgramInfo.h"
18#include "GCNSubtarget.h"
19#include "SIDefines.h"
20#include "Utils/AMDGPUBaseInfo.h"
21#include "llvm/MC/MCExpr.h"
22
23using namespace llvm;
24
25void SIProgramInfo::reset(const MachineFunction &MF) {
26 MCContext &Ctx = MF.getContext();
27
28 const MCExpr *ZeroExpr = MCConstantExpr::create(Value: 0, Ctx);
29
30 CodeSizeInBytes.reset();
31
32 VGPRBlocks = ZeroExpr;
33 SGPRBlocks = ZeroExpr;
34 Priority = 0;
35 FloatMode = 0;
36 Priv = 0;
37 DX10Clamp = 0;
38 DebugMode = 0;
39 IEEEMode = 0;
40 WgpMode = 0;
41 MemOrdered = 0;
42 FwdProgress = 0;
43 RrWgMode = 0;
44 ScratchSize = ZeroExpr;
45
46 LDSBlocks = 0;
47 ScratchBlocks = ZeroExpr;
48
49 ScratchEnable = ZeroExpr;
50 UserSGPR = 0;
51 TrapHandlerEnable = 0;
52 TGIdXEnable = 0;
53 TGIdYEnable = 0;
54 TGIdZEnable = 0;
55 TGSizeEnable = 0;
56 TIdIGCompCount = 0;
57 EXCPEnMSB = 0;
58 LdsSize = 0;
59 EXCPEnable = 0;
60
61 ComputePGMRSrc3 = ZeroExpr;
62
63 NumVGPR = ZeroExpr;
64 NumArchVGPR = ZeroExpr;
65 NumAccVGPR = ZeroExpr;
66 AccumOffset = ZeroExpr;
67 TgSplit = 0;
68 NumSGPR = ZeroExpr;
69 SGPRSpill = 0;
70 VGPRSpill = 0;
71 LDSSize = 0;
72 FlatUsed = ZeroExpr;
73
74 NumSGPRsForWavesPerEU = ZeroExpr;
75 NumVGPRsForWavesPerEU = ZeroExpr;
76 NamedBarCnt = ZeroExpr;
77 Occupancy = ZeroExpr;
78 DynamicCallStack = ZeroExpr;
79 VCCUsed = ZeroExpr;
80}
81
82static uint64_t getComputePGMRSrc1Reg(const SIProgramInfo &ProgInfo,
83 const GCNSubtarget &ST) {
84 uint64_t Reg = S_00B848_PRIORITY(ProgInfo.Priority) |
85 S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
86 S_00B848_PRIV(ProgInfo.Priv) |
87 S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
88 S_00B848_WGP_MODE(ProgInfo.WgpMode) |
89 S_00B848_MEM_ORDERED(ProgInfo.MemOrdered) |
90 S_00B848_FWD_PROGRESS(ProgInfo.FwdProgress);
91
92 if (ST.hasFeature(Feature: AMDGPU::FeatureDX10ClampAndIEEEMode)) {
93 Reg |= S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp);
94 Reg |= S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
95 }
96
97 if (ST.hasRrWGMode())
98 Reg |= S_00B848_RR_WG_MODE(ProgInfo.RrWgMode);
99
100 return Reg;
101}
102
103static uint64_t getPGMRSrc1Reg(const SIProgramInfo &ProgInfo,
104 CallingConv::ID CC, const GCNSubtarget &ST) {
105 uint64_t Reg = S_00B848_PRIORITY(ProgInfo.Priority) |
106 S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
107 S_00B848_PRIV(ProgInfo.Priv) |
108 S_00B848_DEBUG_MODE(ProgInfo.DebugMode);
109
110 if (ST.hasFeature(Feature: AMDGPU::FeatureDX10ClampAndIEEEMode)) {
111 Reg |= S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp);
112 Reg |= S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
113 }
114
115 if (ST.hasRrWGMode())
116 Reg |= S_00B848_RR_WG_MODE(ProgInfo.RrWgMode);
117
118 switch (CC) {
119 case CallingConv::AMDGPU_PS:
120 Reg |= S_00B028_MEM_ORDERED(ProgInfo.MemOrdered);
121 break;
122 case CallingConv::AMDGPU_VS:
123 Reg |= S_00B128_MEM_ORDERED(ProgInfo.MemOrdered);
124 break;
125 case CallingConv::AMDGPU_GS:
126 Reg |= S_00B228_WGP_MODE(ProgInfo.WgpMode) |
127 S_00B228_MEM_ORDERED(ProgInfo.MemOrdered);
128 break;
129 case CallingConv::AMDGPU_HS:
130 Reg |= S_00B428_WGP_MODE(ProgInfo.WgpMode) |
131 S_00B428_MEM_ORDERED(ProgInfo.MemOrdered);
132 break;
133 default:
134 break;
135 }
136 return Reg;
137}
138
139static uint64_t getComputePGMRSrc2Reg(const SIProgramInfo &ProgInfo) {
140 uint64_t Reg = S_00B84C_USER_SGPR(ProgInfo.UserSGPR) |
141 S_00B84C_TRAP_HANDLER(ProgInfo.TrapHandlerEnable) |
142 S_00B84C_TGID_X_EN(ProgInfo.TGIdXEnable) |
143 S_00B84C_TGID_Y_EN(ProgInfo.TGIdYEnable) |
144 S_00B84C_TGID_Z_EN(ProgInfo.TGIdZEnable) |
145 S_00B84C_TG_SIZE_EN(ProgInfo.TGSizeEnable) |
146 S_00B84C_TIDIG_COMP_CNT(ProgInfo.TIdIGCompCount) |
147 S_00B84C_EXCP_EN_MSB(ProgInfo.EXCPEnMSB) |
148 S_00B84C_LDS_SIZE(ProgInfo.LdsSize) |
149 S_00B84C_EXCP_EN(ProgInfo.EXCPEnable);
150
151 return Reg;
152}
153
154static const MCExpr *MaskShift(const MCExpr *Val, uint32_t Mask, uint32_t Shift,
155 MCContext &Ctx) {
156 if (Mask) {
157 const MCExpr *MaskExpr = MCConstantExpr::create(Value: Mask, Ctx);
158 Val = MCBinaryExpr::createAnd(LHS: Val, RHS: MaskExpr, Ctx);
159 }
160 if (Shift) {
161 const MCExpr *ShiftExpr = MCConstantExpr::create(Value: Shift, Ctx);
162 Val = MCBinaryExpr::createShl(LHS: Val, RHS: ShiftExpr, Ctx);
163 }
164 return Val;
165}
166
167const MCExpr *SIProgramInfo::getComputePGMRSrc1(const GCNSubtarget &ST,
168 MCContext &Ctx) const {
169 uint64_t Reg = getComputePGMRSrc1Reg(ProgInfo: *this, ST);
170 const MCExpr *RegExpr = MCConstantExpr::create(Value: Reg, Ctx);
171 const MCExpr *Res = MCBinaryExpr::createOr(
172 LHS: MaskShift(Val: VGPRBlocks, /*Mask=*/0x3F, /*Shift=*/0, Ctx),
173 RHS: MaskShift(Val: SGPRBlocks, /*Mask=*/0xF, /*Shift=*/6, Ctx), Ctx);
174 return MCBinaryExpr::createOr(LHS: RegExpr, RHS: Res, Ctx);
175}
176
177const MCExpr *SIProgramInfo::getPGMRSrc1(CallingConv::ID CC,
178 const GCNSubtarget &ST,
179 MCContext &Ctx) const {
180 if (AMDGPU::isCompute(CC)) {
181 return getComputePGMRSrc1(ST, Ctx);
182 }
183
184 uint64_t Reg = getPGMRSrc1Reg(ProgInfo: *this, CC, ST);
185 const MCExpr *RegExpr = MCConstantExpr::create(Value: Reg, Ctx);
186 const MCExpr *Res = MCBinaryExpr::createOr(
187 LHS: MaskShift(Val: VGPRBlocks, /*Mask=*/0x3F, /*Shift=*/0, Ctx),
188 RHS: MaskShift(Val: SGPRBlocks, /*Mask=*/0xF, /*Shift=*/6, Ctx), Ctx);
189 return MCBinaryExpr::createOr(LHS: RegExpr, RHS: Res, Ctx);
190}
191
192const MCExpr *SIProgramInfo::getComputePGMRSrc2(MCContext &Ctx) const {
193 uint64_t Reg = getComputePGMRSrc2Reg(ProgInfo: *this);
194 const MCExpr *RegExpr = MCConstantExpr::create(Value: Reg, Ctx);
195 return MCBinaryExpr::createOr(LHS: ScratchEnable, RHS: RegExpr, Ctx);
196}
197
198const MCExpr *SIProgramInfo::getPGMRSrc2(CallingConv::ID CC,
199 MCContext &Ctx) const {
200 if (AMDGPU::isCompute(CC))
201 return getComputePGMRSrc2(Ctx);
202
203 return MCConstantExpr::create(Value: 0, Ctx);
204}
205
206uint64_t SIProgramInfo::getFunctionCodeSize(const MachineFunction &MF,
207 bool IsLowerBound) {
208 if (!IsLowerBound && CodeSizeInBytes.has_value())
209 return *CodeSizeInBytes;
210
211 const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
212 const SIInstrInfo *TII = STM.getInstrInfo();
213
214 uint64_t CodeSize = 0;
215
216 for (const MachineBasicBlock &MBB : MF) {
217 // The amount of padding to align code can be both underestimated and
218 // overestimated. In case of inline asm used getInstSizeInBytes() will
219 // return a maximum size of a single instruction, where the real size may
220 // differ. At this point CodeSize may be already off.
221 if (!IsLowerBound)
222 CodeSize = alignTo(Size: CodeSize, A: MBB.getAlignment());
223
224 for (const MachineInstr &MI : MBB) {
225 // TODO: CodeSize should account for multiple functions.
226
227 if (MI.isMetaInstruction())
228 continue;
229
230 // We cannot properly estimate inline asm size. It can be as small as zero
231 // if that is just a comment.
232 if (IsLowerBound && MI.isInlineAsm())
233 continue;
234
235 CodeSize += TII->getInstSizeInBytes(MI);
236 }
237 }
238
239 CodeSizeInBytes = CodeSize;
240 return CodeSize;
241}
242