1//===- ARMConstantIslandPass.cpp - ARM constant islands -------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a pass that splits the constant pool up into 'islands'
10// which are scattered through-out the function. This is required due to the
11// limited pc-relative displacements that ARM has.
12//
13//===----------------------------------------------------------------------===//
14
15#include "ARM.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMBasicBlockInfo.h"
18#include "ARMMachineFunctionInfo.h"
19#include "ARMSubtarget.h"
20#include "MCTargetDesc/ARMBaseInfo.h"
21#include "MVETailPredUtils.h"
22#include "Thumb2InstrInfo.h"
23#include "Utils/ARMBaseInfo.h"
24#include "llvm/ADT/DenseMap.h"
25#include "llvm/ADT/STLExtras.h"
26#include "llvm/ADT/SmallVector.h"
27#include "llvm/ADT/Statistic.h"
28#include "llvm/ADT/StringRef.h"
29#include "llvm/CodeGen/LivePhysRegs.h"
30#include "llvm/CodeGen/MachineBasicBlock.h"
31#include "llvm/CodeGen/MachineConstantPool.h"
32#include "llvm/CodeGen/MachineDominators.h"
33#include "llvm/CodeGen/MachineFunction.h"
34#include "llvm/CodeGen/MachineFunctionPass.h"
35#include "llvm/CodeGen/MachineInstr.h"
36#include "llvm/CodeGen/MachineJumpTableInfo.h"
37#include "llvm/CodeGen/MachineOperand.h"
38#include "llvm/CodeGen/MachineRegisterInfo.h"
39#include "llvm/Config/llvm-config.h"
40#include "llvm/IR/DataLayout.h"
41#include "llvm/IR/DebugLoc.h"
42#include "llvm/MC/MCInstrDesc.h"
43#include "llvm/Pass.h"
44#include "llvm/Support/CommandLine.h"
45#include "llvm/Support/Compiler.h"
46#include "llvm/Support/Debug.h"
47#include "llvm/Support/ErrorHandling.h"
48#include "llvm/Support/Format.h"
49#include "llvm/Support/raw_ostream.h"
50#include <algorithm>
51#include <cassert>
52#include <cstdint>
53#include <iterator>
54#include <vector>
55
56using namespace llvm;
57
58#define DEBUG_TYPE "arm-cp-islands"
59
60#define ARM_CP_ISLANDS_OPT_NAME \
61 "ARM constant island placement and branch shortening pass"
62STATISTIC(NumCPEs, "Number of constpool entries");
63STATISTIC(NumSplit, "Number of uncond branches inserted");
64STATISTIC(NumCBrFixed, "Number of cond branches fixed");
65STATISTIC(NumUBrFixed, "Number of uncond branches fixed");
66STATISTIC(NumTBs, "Number of table branches generated");
67STATISTIC(NumT2CPShrunk, "Number of Thumb2 constantpool instructions shrunk");
68STATISTIC(NumT2BrShrunk, "Number of Thumb2 immediate branches shrunk");
69STATISTIC(NumCBZ, "Number of CBZ / CBNZ formed");
70STATISTIC(NumJTMoved, "Number of jump table destination blocks moved");
71STATISTIC(NumJTInserted, "Number of jump table intermediate blocks inserted");
72STATISTIC(NumLEInserted, "Number of LE backwards branches inserted");
73
74static cl::opt<bool>
75AdjustJumpTableBlocks("arm-adjust-jump-tables", cl::Hidden, cl::init(Val: true),
76 cl::desc("Adjust basic block layout to better use TB[BH]"));
77
78static cl::opt<unsigned>
79CPMaxIteration("arm-constant-island-max-iteration", cl::Hidden, cl::init(Val: 30),
80 cl::desc("The max number of iteration for converge"));
81
82static cl::opt<bool> SynthesizeThumb1TBB(
83 "arm-synthesize-thumb-1-tbb", cl::Hidden, cl::init(Val: true),
84 cl::desc("Use compressed jump tables in Thumb-1 by synthesizing an "
85 "equivalent to the TBB/TBH instructions"));
86
87namespace {
88
89 /// ARMConstantIslands - Due to limited PC-relative displacements, ARM
90 /// requires constant pool entries to be scattered among the instructions
91 /// inside a function. To do this, it completely ignores the normal LLVM
92 /// constant pool; instead, it places constants wherever it feels like with
93 /// special instructions.
94 ///
95 /// The terminology used in this pass includes:
96 /// Islands - Clumps of constants placed in the function.
97 /// Water - Potential places where an island could be formed.
98 /// CPE - A constant pool entry that has been placed somewhere, which
99 /// tracks a list of users.
100 class ARMConstantIslands : public MachineFunctionPass {
101 std::unique_ptr<ARMBasicBlockUtils> BBUtils = nullptr;
102
103 /// WaterList - A sorted list of basic blocks where islands could be placed
104 /// (i.e. blocks that don't fall through to the following block, due
105 /// to a return, unreachable, or unconditional branch).
106 std::vector<MachineBasicBlock*> WaterList;
107
108 /// NewWaterList - The subset of WaterList that was created since the
109 /// previous iteration by inserting unconditional branches.
110 SmallPtrSet<MachineBasicBlock *, 4> NewWaterList;
111
112 using water_iterator = std::vector<MachineBasicBlock *>::iterator;
113
114 /// CPUser - One user of a constant pool, keeping the machine instruction
115 /// pointer, the constant pool being referenced, and the max displacement
116 /// allowed from the instruction to the CP. The HighWaterMark records the
117 /// highest basic block where a new CPEntry can be placed. To ensure this
118 /// pass terminates, the CP entries are initially placed at the end of the
119 /// function and then move monotonically to lower addresses. The
120 /// exception to this rule is when the current CP entry for a particular
121 /// CPUser is out of range, but there is another CP entry for the same
122 /// constant value in range. We want to use the existing in-range CP
123 /// entry, but if it later moves out of range, the search for new water
124 /// should resume where it left off. The HighWaterMark is used to record
125 /// that point.
126 struct CPUser {
127 MachineInstr *MI;
128 MachineInstr *CPEMI;
129 MachineBasicBlock *HighWaterMark;
130 unsigned MaxDisp;
131 bool NegOk;
132 bool IsSoImm;
133 bool KnownAlignment = false;
134
135 CPUser(MachineInstr *mi, MachineInstr *cpemi, unsigned maxdisp,
136 bool neg, bool soimm)
137 : MI(mi), CPEMI(cpemi), MaxDisp(maxdisp), NegOk(neg), IsSoImm(soimm) {
138 HighWaterMark = CPEMI->getParent();
139 }
140
141 /// getMaxDisp - Returns the maximum displacement supported by MI.
142 /// Correct for unknown alignment.
143 /// Conservatively subtract 2 bytes to handle weird alignment effects.
144 unsigned getMaxDisp() const {
145 return (KnownAlignment ? MaxDisp : MaxDisp - 2) - 2;
146 }
147 };
148
149 /// CPUsers - Keep track of all of the machine instructions that use various
150 /// constant pools and their max displacement.
151 std::vector<CPUser> CPUsers;
152
153 /// CPEntry - One per constant pool entry, keeping the machine instruction
154 /// pointer, the constpool index, and the number of CPUser's which
155 /// reference this entry.
156 struct CPEntry {
157 MachineInstr *CPEMI;
158 unsigned CPI;
159 unsigned RefCount;
160
161 CPEntry(MachineInstr *cpemi, unsigned cpi, unsigned rc = 0)
162 : CPEMI(cpemi), CPI(cpi), RefCount(rc) {}
163 };
164
165 /// CPEntries - Keep track of all of the constant pool entry machine
166 /// instructions. For each original constpool index (i.e. those that existed
167 /// upon entry to this pass), it keeps a vector of entries. Original
168 /// elements are cloned as we go along; the clones are put in the vector of
169 /// the original element, but have distinct CPIs.
170 ///
171 /// The first half of CPEntries contains generic constants, the second half
172 /// contains jump tables. Use getCombinedIndex on a generic CPEMI to look up
173 /// which vector it will be in here.
174 std::vector<std::vector<CPEntry>> CPEntries;
175
176 /// Maps a JT index to the offset in CPEntries containing copies of that
177 /// table. The equivalent map for a CONSTPOOL_ENTRY is the identity.
178 DenseMap<int, int> JumpTableEntryIndices;
179
180 /// Maps a JT index to the LEA that actually uses the index to calculate its
181 /// base address.
182 DenseMap<int, int> JumpTableUserIndices;
183
184 /// ImmBranch - One per immediate branch, keeping the machine instruction
185 /// pointer, conditional or unconditional, the max displacement,
186 /// and (if isCond is true) the corresponding unconditional branch
187 /// opcode.
188 struct ImmBranch {
189 MachineInstr *MI;
190 unsigned MaxDisp : 31;
191 LLVM_PREFERRED_TYPE(bool)
192 unsigned isCond : 1;
193 unsigned UncondBr;
194
195 ImmBranch(MachineInstr *mi, unsigned maxdisp, bool cond, unsigned ubr)
196 : MI(mi), MaxDisp(maxdisp), isCond(cond), UncondBr(ubr) {}
197 };
198
199 /// ImmBranches - Keep track of all the immediate branch instructions.
200 std::vector<ImmBranch> ImmBranches;
201
202 /// PushPopMIs - Keep track of all the Thumb push / pop instructions.
203 SmallVector<MachineInstr*, 4> PushPopMIs;
204
205 /// T2JumpTables - Keep track of all the Thumb2 jumptable instructions.
206 SmallVector<MachineInstr*, 4> T2JumpTables;
207
208 MachineFunction *MF;
209 MachineConstantPool *MCP;
210 const ARMBaseInstrInfo *TII;
211 const ARMSubtarget *STI;
212 ARMFunctionInfo *AFI;
213 MachineDominatorTree *DT = nullptr;
214 bool isThumb;
215 bool isThumb1;
216 bool isThumb2;
217 bool isPositionIndependentOrROPI;
218
219 public:
220 static char ID;
221
222 ARMConstantIslands() : MachineFunctionPass(ID) {}
223
224 bool runOnMachineFunction(MachineFunction &MF) override;
225
226 void getAnalysisUsage(AnalysisUsage &AU) const override {
227 AU.addRequired<MachineDominatorTreeWrapperPass>();
228 MachineFunctionPass::getAnalysisUsage(AU);
229 }
230
231 MachineFunctionProperties getRequiredProperties() const override {
232 return MachineFunctionProperties().setNoVRegs();
233 }
234
235 StringRef getPassName() const override {
236 return ARM_CP_ISLANDS_OPT_NAME;
237 }
238
239 private:
240 void doInitialConstPlacement(std::vector<MachineInstr *> &CPEMIs);
241 void doInitialJumpTablePlacement(std::vector<MachineInstr *> &CPEMIs);
242 bool BBHasFallthrough(MachineBasicBlock *MBB);
243 CPEntry *findConstPoolEntry(unsigned CPI, const MachineInstr *CPEMI);
244 Align getCPEAlign(const MachineInstr *CPEMI);
245 void scanFunctionJumpTables();
246 void initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs);
247 MachineBasicBlock *splitBlockBeforeInstr(MachineInstr *MI);
248 void updateForInsertedWaterBlock(MachineBasicBlock *NewBB);
249 bool decrementCPEReferenceCount(unsigned CPI, MachineInstr* CPEMI);
250 unsigned getCombinedIndex(const MachineInstr *CPEMI);
251 int findInRangeCPEntry(CPUser& U, unsigned UserOffset);
252 bool findAvailableWater(CPUser&U, unsigned UserOffset,
253 water_iterator &WaterIter, bool CloserWater);
254 void createNewWater(unsigned CPUserIndex, unsigned UserOffset,
255 MachineBasicBlock *&NewMBB);
256 bool handleConstantPoolUser(unsigned CPUserIndex, bool CloserWater);
257 void removeDeadCPEMI(MachineInstr *CPEMI);
258 bool removeUnusedCPEntries();
259 bool isCPEntryInRange(MachineInstr *MI, unsigned UserOffset,
260 MachineInstr *CPEMI, unsigned Disp, bool NegOk,
261 bool DoDump = false);
262 bool isWaterInRange(unsigned UserOffset, MachineBasicBlock *Water,
263 CPUser &U, unsigned &Growth);
264 bool fixupImmediateBr(ImmBranch &Br);
265 bool fixupConditionalBr(ImmBranch &Br);
266 bool fixupUnconditionalBr(ImmBranch &Br);
267 bool optimizeThumb2Instructions();
268 bool optimizeThumb2Branches();
269 bool reorderThumb2JumpTables();
270 bool preserveBaseRegister(MachineInstr *JumpMI, MachineInstr *LEAMI,
271 unsigned &DeadSize, bool &CanDeleteLEA,
272 bool &BaseRegKill);
273 bool optimizeThumb2JumpTables();
274 MachineBasicBlock *adjustJTTargetBlockForward(unsigned JTI,
275 MachineBasicBlock *BB,
276 MachineBasicBlock *JTBB);
277
278 unsigned getUserOffset(CPUser&) const;
279 void dumpBBs();
280 void verify();
281
282 bool isOffsetInRange(unsigned UserOffset, unsigned TrialOffset,
283 unsigned Disp, bool NegativeOK, bool IsSoImm = false);
284 bool isOffsetInRange(unsigned UserOffset, unsigned TrialOffset,
285 const CPUser &U) {
286 return isOffsetInRange(UserOffset, TrialOffset,
287 Disp: U.getMaxDisp(), NegativeOK: U.NegOk, IsSoImm: U.IsSoImm);
288 }
289 };
290
291} // end anonymous namespace
292
293char ARMConstantIslands::ID = 0;
294
295/// verify - check BBOffsets, BBSizes, alignment of islands
296void ARMConstantIslands::verify() {
297#ifndef NDEBUG
298 BBInfoVector &BBInfo = BBUtils->getBBInfo();
299 assert(is_sorted(*MF, [&BBInfo](const MachineBasicBlock &LHS,
300 const MachineBasicBlock &RHS) {
301 return BBInfo[LHS.getNumber()].postOffset() <
302 BBInfo[RHS.getNumber()].postOffset();
303 }));
304 LLVM_DEBUG(dbgs() << "Verifying " << CPUsers.size() << " CP users.\n");
305 for (CPUser &U : CPUsers) {
306 unsigned UserOffset = getUserOffset(U);
307 // Verify offset using the real max displacement without the safety
308 // adjustment.
309 if (isCPEntryInRange(U.MI, UserOffset, U.CPEMI, U.getMaxDisp()+2, U.NegOk,
310 /* DoDump = */ true)) {
311 LLVM_DEBUG(dbgs() << "OK\n");
312 continue;
313 }
314 LLVM_DEBUG(dbgs() << "Out of range.\n");
315 dumpBBs();
316 LLVM_DEBUG(MF->dump());
317 llvm_unreachable("Constant pool entry out of range!");
318 }
319#endif
320}
321
322#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
323/// print block size and offset information - debugging
324LLVM_DUMP_METHOD void ARMConstantIslands::dumpBBs() {
325 LLVM_DEBUG({
326 BBInfoVector &BBInfo = BBUtils->getBBInfo();
327 for (unsigned J = 0, E = BBInfo.size(); J !=E; ++J) {
328 const BasicBlockInfo &BBI = BBInfo[J];
329 dbgs() << format("%08x %bb.%u\t", BBI.Offset, J)
330 << " kb=" << unsigned(BBI.KnownBits)
331 << " ua=" << unsigned(BBI.Unalign) << " pa=" << Log2(BBI.PostAlign)
332 << format(" size=%#x\n", BBInfo[J].Size);
333 }
334 });
335}
336#endif
337
338// Align blocks where the previous block does not fall through. This may add
339// extra NOP's but they will not be executed. It uses the PrefLoopAlignment as a
340// measure of how much to align, and only runs at CodeGenOptLevel::Aggressive.
341static bool AlignBlocks(MachineFunction *MF, const ARMSubtarget *STI) {
342 if (MF->getTarget().getOptLevel() != CodeGenOptLevel::Aggressive ||
343 MF->getFunction().hasOptSize())
344 return false;
345
346 auto *TLI = STI->getTargetLowering();
347 const Align Alignment = TLI->getPrefLoopAlignment();
348 if (Alignment < 4)
349 return false;
350
351 bool Changed = false;
352 bool PrevCanFallthrough = true;
353 for (auto &MBB : *MF) {
354 if (!PrevCanFallthrough) {
355 Changed = true;
356 MBB.setAlignment(Alignment);
357 }
358
359 PrevCanFallthrough = MBB.canFallThrough();
360
361 // For LOB's, the ARMLowOverheadLoops pass may remove the unconditional
362 // branch later in the pipeline.
363 if (STI->hasLOB()) {
364 for (const auto &MI : reverse(C: MBB.terminators())) {
365 if (MI.getOpcode() == ARM::t2B &&
366 MI.getOperand(i: 0).getMBB() == MBB.getNextNode())
367 continue;
368 if (isLoopStart(MI) || MI.getOpcode() == ARM::t2LoopEnd ||
369 MI.getOpcode() == ARM::t2LoopEndDec) {
370 PrevCanFallthrough = true;
371 break;
372 }
373 // Any other terminator - nothing to do
374 break;
375 }
376 }
377 }
378
379 return Changed;
380}
381
382bool ARMConstantIslands::runOnMachineFunction(MachineFunction &mf) {
383 MF = &mf;
384 MCP = mf.getConstantPool();
385 BBUtils = std::make_unique<ARMBasicBlockUtils>(args&: mf);
386
387 LLVM_DEBUG(dbgs() << "***** ARMConstantIslands: "
388 << MCP->getConstants().size() << " CP entries, aligned to "
389 << MCP->getConstantPoolAlign().value() << " bytes *****\n");
390
391 STI = &MF->getSubtarget<ARMSubtarget>();
392 TII = STI->getInstrInfo();
393 isPositionIndependentOrROPI =
394 STI->getTargetLowering()->isPositionIndependent() || STI->isROPI();
395 AFI = MF->getInfo<ARMFunctionInfo>();
396 DT = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
397
398 isThumb = AFI->isThumbFunction();
399 isThumb1 = AFI->isThumb1OnlyFunction();
400 isThumb2 = AFI->isThumb2Function();
401
402 bool GenerateTBB = isThumb2 || (isThumb1 && SynthesizeThumb1TBB);
403 // TBB generation code in this constant island pass has not been adapted to
404 // deal with speculation barriers.
405 if (STI->hardenSlsRetBr())
406 GenerateTBB = false;
407
408 // Renumber all of the machine basic blocks in the function, guaranteeing that
409 // the numbers agree with the position of the block in the function.
410 MF->RenumberBlocks();
411
412 // Try to reorder and otherwise adjust the block layout to make good use
413 // of the TB[BH] instructions.
414 bool MadeChange = false;
415 if (GenerateTBB && AdjustJumpTableBlocks) {
416 scanFunctionJumpTables();
417 MadeChange |= reorderThumb2JumpTables();
418 // Data is out of date, so clear it. It'll be re-computed later.
419 T2JumpTables.clear();
420 // Blocks may have shifted around. Keep the numbering up to date.
421 MF->RenumberBlocks();
422 }
423
424 // Align any non-fallthrough blocks
425 MadeChange |= AlignBlocks(MF, STI);
426
427 // Perform the initial placement of the constant pool entries. To start with,
428 // we put them all at the end of the function.
429 std::vector<MachineInstr*> CPEMIs;
430 if (!MCP->isEmpty())
431 doInitialConstPlacement(CPEMIs);
432
433 if (MF->getJumpTableInfo())
434 doInitialJumpTablePlacement(CPEMIs);
435
436 /// The next UID to take is the first unused one.
437 AFI->initPICLabelUId(UId: CPEMIs.size());
438
439 // Do the initial scan of the function, building up information about the
440 // sizes of each block, the location of all the water, and finding all of the
441 // constant pool users.
442 initializeFunctionInfo(CPEMIs);
443 CPEMIs.clear();
444 LLVM_DEBUG(dumpBBs());
445
446 // Functions with jump tables need an alignment of 4 because they use the ADR
447 // instruction, which aligns the PC to 4 bytes before adding an offset.
448 if (!T2JumpTables.empty())
449 MF->ensureAlignment(A: Align(4));
450
451 /// Remove dead constant pool entries.
452 MadeChange |= removeUnusedCPEntries();
453
454 // Iteratively place constant pool entries and fix up branches until there
455 // is no change.
456 unsigned NoCPIters = 0, NoBRIters = 0;
457 while (true) {
458 LLVM_DEBUG(dbgs() << "Beginning CP iteration #" << NoCPIters << '\n');
459 bool CPChange = false;
460 for (unsigned i = 0, e = CPUsers.size(); i != e; ++i)
461 // For most inputs, it converges in no more than 5 iterations.
462 // If it doesn't end in 10, the input may have huge BB or many CPEs.
463 // In this case, we will try different heuristics.
464 CPChange |= handleConstantPoolUser(CPUserIndex: i, CloserWater: NoCPIters >= CPMaxIteration / 2);
465 if (CPChange && ++NoCPIters > CPMaxIteration)
466 report_fatal_error(reason: "Constant Island pass failed to converge!");
467 LLVM_DEBUG(dumpBBs());
468
469 // Clear NewWaterList now. If we split a block for branches, it should
470 // appear as "new water" for the next iteration of constant pool placement.
471 NewWaterList.clear();
472
473 LLVM_DEBUG(dbgs() << "Beginning BR iteration #" << NoBRIters << '\n');
474 bool BRChange = false;
475 for (unsigned i = 0, e = ImmBranches.size(); i != e; ++i) {
476 // Note: fixupImmediateBr can append to ImmBranches.
477 BRChange |= fixupImmediateBr(Br&: ImmBranches[i]);
478 }
479 if (BRChange && ++NoBRIters > 30)
480 report_fatal_error(reason: "Branch Fix Up pass failed to converge!");
481 LLVM_DEBUG(dumpBBs());
482
483 if (!CPChange && !BRChange)
484 break;
485 MadeChange = true;
486 }
487
488 // Shrink 32-bit Thumb2 load and store instructions.
489 if (isThumb2 && !STI->prefers32BitThumb())
490 MadeChange |= optimizeThumb2Instructions();
491
492 // Shrink 32-bit branch instructions.
493 if (isThumb && STI->hasV8MBaselineOps())
494 MadeChange |= optimizeThumb2Branches();
495
496 // Optimize jump tables using TBB / TBH.
497 if (GenerateTBB && !STI->genExecuteOnly())
498 MadeChange |= optimizeThumb2JumpTables();
499
500 // After a while, this might be made debug-only, but it is not expensive.
501 verify();
502
503 // Save the mapping between original and cloned constpool entries.
504 for (unsigned i = 0, e = CPEntries.size(); i != e; ++i) {
505 for (unsigned j = 0, je = CPEntries[i].size(); j != je; ++j) {
506 const CPEntry & CPE = CPEntries[i][j];
507 if (CPE.CPEMI && CPE.CPEMI->getOperand(i: 1).isCPI())
508 AFI->recordCPEClone(CPIdx: i, CPCloneIdx: CPE.CPI);
509 }
510 }
511
512 LLVM_DEBUG(dbgs() << '\n'; dumpBBs());
513
514 BBUtils->clear();
515 WaterList.clear();
516 CPUsers.clear();
517 CPEntries.clear();
518 JumpTableEntryIndices.clear();
519 JumpTableUserIndices.clear();
520 ImmBranches.clear();
521 PushPopMIs.clear();
522 T2JumpTables.clear();
523
524 return MadeChange;
525}
526
527/// Perform the initial placement of the regular constant pool entries.
528/// To start with, we put them all at the end of the function.
529void
530ARMConstantIslands::doInitialConstPlacement(std::vector<MachineInstr*> &CPEMIs) {
531 // Create the basic block to hold the CPE's.
532 MachineBasicBlock *BB = MF->CreateMachineBasicBlock();
533 MF->push_back(MBB: BB);
534
535 // MachineConstantPool measures alignment in bytes.
536 const Align MaxAlign = MCP->getConstantPoolAlign();
537 const unsigned MaxLogAlign = Log2(A: MaxAlign);
538
539 // Mark the basic block as required by the const-pool.
540 BB->setAlignment(MaxAlign);
541
542 // The function needs to be as aligned as the basic blocks. The linker may
543 // move functions around based on their alignment.
544 // Special case: halfword literals still need word alignment on the function.
545 Align FuncAlign = MaxAlign;
546 if (MaxAlign == 2)
547 FuncAlign = Align(4);
548 MF->ensureAlignment(A: FuncAlign);
549
550 // Order the entries in BB by descending alignment. That ensures correct
551 // alignment of all entries as long as BB is sufficiently aligned. Keep
552 // track of the insertion point for each alignment. We are going to bucket
553 // sort the entries as they are created.
554 SmallVector<MachineBasicBlock::iterator, 8> InsPoint(MaxLogAlign + 1,
555 BB->end());
556
557 // Add all of the constants from the constant pool to the end block, use an
558 // identity mapping of CPI's to CPE's.
559 const std::vector<MachineConstantPoolEntry> &CPs = MCP->getConstants();
560
561 const DataLayout &TD = MF->getDataLayout();
562 for (unsigned i = 0, e = CPs.size(); i != e; ++i) {
563 unsigned Size = CPs[i].getSizeInBytes(DL: TD);
564 Align Alignment = CPs[i].getAlign();
565 // Verify that all constant pool entries are a multiple of their alignment.
566 // If not, we would have to pad them out so that instructions stay aligned.
567 assert(isAligned(Alignment, Size) && "CP Entry not multiple of 4 bytes!");
568
569 // Insert CONSTPOOL_ENTRY before entries with a smaller alignment.
570 unsigned LogAlign = Log2(A: Alignment);
571 MachineBasicBlock::iterator InsAt = InsPoint[LogAlign];
572 MachineInstr *CPEMI =
573 BuildMI(BB&: *BB, I: InsAt, MIMD: DebugLoc(), MCID: TII->get(Opcode: ARM::CONSTPOOL_ENTRY))
574 .addImm(Val: i).addConstantPoolIndex(Idx: i).addImm(Val: Size);
575 CPEMIs.push_back(x: CPEMI);
576
577 // Ensure that future entries with higher alignment get inserted before
578 // CPEMI. This is bucket sort with iterators.
579 for (unsigned a = LogAlign + 1; a <= MaxLogAlign; ++a)
580 if (InsPoint[a] == InsAt)
581 InsPoint[a] = CPEMI;
582
583 // Add a new CPEntry, but no corresponding CPUser yet.
584 CPEntries.emplace_back(args: 1, args: CPEntry(CPEMI, i));
585 ++NumCPEs;
586 LLVM_DEBUG(dbgs() << "Moved CPI#" << i << " to end of function, size = "
587 << Size << ", align = " << Alignment.value() << '\n');
588 }
589 LLVM_DEBUG(BB->dump());
590}
591
592/// Do initial placement of the jump tables. Because Thumb2's TBB and TBH
593/// instructions can be made more efficient if the jump table immediately
594/// follows the instruction, it's best to place them immediately next to their
595/// jumps to begin with. In almost all cases they'll never be moved from that
596/// position.
597void ARMConstantIslands::doInitialJumpTablePlacement(
598 std::vector<MachineInstr *> &CPEMIs) {
599 unsigned i = CPEntries.size();
600 auto MJTI = MF->getJumpTableInfo();
601 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
602
603 // Only inline jump tables are placed in the function.
604 if (MJTI->getEntryKind() != MachineJumpTableInfo::EK_Inline)
605 return;
606
607 MachineBasicBlock *LastCorrectlyNumberedBB = nullptr;
608 for (MachineBasicBlock &MBB : *MF) {
609 auto MI = MBB.getLastNonDebugInstr();
610 // Look past potential SpeculationBarriers at end of BB.
611 while (MI != MBB.end() &&
612 (isSpeculationBarrierEndBBOpcode(Opc: MI->getOpcode()) ||
613 MI->isDebugInstr()))
614 --MI;
615
616 if (MI == MBB.end())
617 continue;
618
619 unsigned JTOpcode;
620 switch (MI->getOpcode()) {
621 default:
622 continue;
623 case ARM::BR_JTadd:
624 case ARM::BR_JTr:
625 case ARM::tBR_JTr:
626 case ARM::BR_JTm_i12:
627 case ARM::BR_JTm_rs:
628 // These instructions are emitted only in ARM or Thumb1 modes which do not
629 // support PACBTI. Hence we don't add BTI instructions in the destination
630 // blocks.
631 assert(!MF->getInfo<ARMFunctionInfo>()->branchTargetEnforcement() &&
632 "Branch protection must not be enabled for Arm or Thumb1 modes");
633 JTOpcode = ARM::JUMPTABLE_ADDRS;
634 break;
635 case ARM::t2BR_JT:
636 JTOpcode = ARM::JUMPTABLE_INSTS;
637 break;
638 case ARM::tTBB_JT:
639 case ARM::t2TBB_JT:
640 JTOpcode = ARM::JUMPTABLE_TBB;
641 break;
642 case ARM::tTBH_JT:
643 case ARM::t2TBH_JT:
644 JTOpcode = ARM::JUMPTABLE_TBH;
645 break;
646 }
647
648 unsigned NumOps = MI->getDesc().getNumOperands();
649 MachineOperand JTOp =
650 MI->getOperand(i: NumOps - (MI->isPredicable() ? 2 : 1));
651 unsigned JTI = JTOp.getIndex();
652 unsigned Size = JT[JTI].MBBs.size() * sizeof(uint32_t);
653 MachineBasicBlock *JumpTableBB = MF->CreateMachineBasicBlock();
654 MF->insert(MBBI: std::next(x: MachineFunction::iterator(MBB)), MBB: JumpTableBB);
655 MachineInstr *CPEMI = BuildMI(BB&: *JumpTableBB, I: JumpTableBB->begin(),
656 MIMD: DebugLoc(), MCID: TII->get(Opcode: JTOpcode))
657 .addImm(Val: i++)
658 .addJumpTableIndex(Idx: JTI)
659 .addImm(Val: Size);
660 CPEMIs.push_back(x: CPEMI);
661 CPEntries.emplace_back(args: 1, args: CPEntry(CPEMI, JTI));
662 JumpTableEntryIndices.insert(KV: std::make_pair(x&: JTI, y: CPEntries.size() - 1));
663 if (!LastCorrectlyNumberedBB)
664 LastCorrectlyNumberedBB = &MBB;
665 }
666
667 // If we did anything then we need to renumber the subsequent blocks.
668 if (LastCorrectlyNumberedBB)
669 MF->RenumberBlocks(MBBFrom: LastCorrectlyNumberedBB);
670}
671
672/// BBHasFallthrough - Return true if the specified basic block can fallthrough
673/// into the block immediately after it.
674bool ARMConstantIslands::BBHasFallthrough(MachineBasicBlock *MBB) {
675 // Get the next machine basic block in the function.
676 MachineFunction::iterator MBBI = MBB->getIterator();
677 // Can't fall off end of function.
678 if (std::next(x: MBBI) == MBB->getParent()->end())
679 return false;
680
681 MachineBasicBlock *NextBB = &*std::next(x: MBBI);
682 if (!MBB->isSuccessor(MBB: NextBB))
683 return false;
684
685 // Try to analyze the end of the block. A potential fallthrough may already
686 // have an unconditional branch for whatever reason.
687 MachineBasicBlock *TBB, *FBB;
688 SmallVector<MachineOperand, 4> Cond;
689 bool TooDifficult = TII->analyzeBranch(MBB&: *MBB, TBB, FBB, Cond);
690 return TooDifficult || FBB == nullptr;
691}
692
693/// findConstPoolEntry - Given the constpool index and CONSTPOOL_ENTRY MI,
694/// look up the corresponding CPEntry.
695ARMConstantIslands::CPEntry *
696ARMConstantIslands::findConstPoolEntry(unsigned CPI,
697 const MachineInstr *CPEMI) {
698 std::vector<CPEntry> &CPEs = CPEntries[CPI];
699 // Number of entries per constpool index should be small, just do a
700 // linear search.
701 for (CPEntry &CPE : CPEs)
702 if (CPE.CPEMI == CPEMI)
703 return &CPE;
704 return nullptr;
705}
706
707/// getCPEAlign - Returns the required alignment of the constant pool entry
708/// represented by CPEMI.
709Align ARMConstantIslands::getCPEAlign(const MachineInstr *CPEMI) {
710 switch (CPEMI->getOpcode()) {
711 case ARM::CONSTPOOL_ENTRY:
712 break;
713 case ARM::JUMPTABLE_TBB:
714 return isThumb1 ? Align(4) : Align(1);
715 case ARM::JUMPTABLE_TBH:
716 return isThumb1 ? Align(4) : Align(2);
717 case ARM::JUMPTABLE_INSTS:
718 return Align(2);
719 case ARM::JUMPTABLE_ADDRS:
720 return Align(4);
721 default:
722 llvm_unreachable("unknown constpool entry kind");
723 }
724
725 unsigned CPI = getCombinedIndex(CPEMI);
726 assert(CPI < MCP->getConstants().size() && "Invalid constant pool index.");
727 return MCP->getConstants()[CPI].getAlign();
728}
729
730/// scanFunctionJumpTables - Do a scan of the function, building up
731/// information about the sizes of each block and the locations of all
732/// the jump tables.
733void ARMConstantIslands::scanFunctionJumpTables() {
734 for (MachineBasicBlock &MBB : *MF) {
735 for (MachineInstr &I : MBB)
736 if (I.isBranch() &&
737 (I.getOpcode() == ARM::t2BR_JT || I.getOpcode() == ARM::tBR_JTr))
738 T2JumpTables.push_back(Elt: &I);
739 }
740}
741
742/// initializeFunctionInfo - Do the initial scan of the function, building up
743/// information about the sizes of each block, the location of all the water,
744/// and finding all of the constant pool users.
745void ARMConstantIslands::
746initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs) {
747
748 BBUtils->computeAllBlockSizes();
749 BBInfoVector &BBInfo = BBUtils->getBBInfo();
750 // The known bits of the entry block offset are determined by the function
751 // alignment.
752 BBInfo.front().KnownBits = Log2(A: MF->getAlignment());
753
754 // Compute block offsets and known bits.
755 BBUtils->adjustBBOffsetsAfter(MBB: &MF->front());
756
757 // We only care about jump table instructions when jump tables are inline.
758 MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
759 bool InlineJumpTables =
760 MJTI && MJTI->getEntryKind() == MachineJumpTableInfo::EK_Inline;
761
762 // Now go back through the instructions and build up our data structures.
763 for (MachineBasicBlock &MBB : *MF) {
764 // If this block doesn't fall through into the next MBB, then this is
765 // 'water' that a constant pool island could be placed.
766 if (!BBHasFallthrough(MBB: &MBB))
767 WaterList.push_back(x: &MBB);
768
769 for (MachineInstr &I : MBB) {
770 if (I.isDebugInstr())
771 continue;
772
773 unsigned Opc = I.getOpcode();
774 if (I.isBranch()) {
775 bool isCond = false;
776 unsigned Bits = 0;
777 unsigned Scale = 1;
778 int UOpc = Opc;
779 switch (Opc) {
780 default:
781 continue; // Ignore other JT branches
782 case ARM::t2BR_JT:
783 case ARM::tBR_JTr:
784 if (InlineJumpTables)
785 T2JumpTables.push_back(Elt: &I);
786 continue; // Does not get an entry in ImmBranches
787 case ARM::Bcc:
788 isCond = true;
789 UOpc = ARM::B;
790 [[fallthrough]];
791 case ARM::B:
792 Bits = 24;
793 Scale = 4;
794 break;
795 case ARM::tBcc:
796 isCond = true;
797 UOpc = ARM::tB;
798 Bits = 8;
799 Scale = 2;
800 break;
801 case ARM::tB:
802 Bits = 11;
803 Scale = 2;
804 break;
805 case ARM::t2Bcc:
806 isCond = true;
807 UOpc = ARM::t2B;
808 Bits = 20;
809 Scale = 2;
810 break;
811 case ARM::t2B:
812 Bits = 24;
813 Scale = 2;
814 break;
815 }
816
817 // Record this immediate branch.
818 unsigned MaxOffs = ((1 << (Bits-1))-1) * Scale;
819 ImmBranches.push_back(x: ImmBranch(&I, MaxOffs, isCond, UOpc));
820 }
821
822 if (Opc == ARM::tPUSH || Opc == ARM::tPOP_RET)
823 PushPopMIs.push_back(Elt: &I);
824
825 if (Opc == ARM::CONSTPOOL_ENTRY || Opc == ARM::JUMPTABLE_ADDRS ||
826 Opc == ARM::JUMPTABLE_INSTS || Opc == ARM::JUMPTABLE_TBB ||
827 Opc == ARM::JUMPTABLE_TBH)
828 continue;
829
830 // Scan the instructions for constant pool operands.
831 for (unsigned op = 0, e = I.getNumOperands(); op != e; ++op)
832 if (I.getOperand(i: op).isCPI() ||
833 (I.getOperand(i: op).isJTI() && InlineJumpTables)) {
834 // We found one. The addressing mode tells us the max displacement
835 // from the PC that this instruction permits.
836
837 // Basic size info comes from the TSFlags field.
838 unsigned Bits = 0;
839 unsigned Scale = 1;
840 bool NegOk = false;
841 bool IsSoImm = false;
842
843 switch (Opc) {
844 default:
845 llvm_unreachable("Unknown addressing mode for CP reference!");
846
847 // Taking the address of a CP entry.
848 case ARM::LEApcrel:
849 case ARM::LEApcrelJT: {
850 // This takes a SoImm, which is 8 bit immediate rotated. We'll
851 // pretend the maximum offset is 255 * 4. Since each instruction
852 // 4 byte wide, this is always correct. We'll check for other
853 // displacements that fits in a SoImm as well.
854 Bits = 8;
855 NegOk = true;
856 IsSoImm = true;
857 unsigned CPI = I.getOperand(i: op).getIndex();
858 assert(CPI < CPEMIs.size());
859 MachineInstr *CPEMI = CPEMIs[CPI];
860 const Align CPEAlign = getCPEAlign(CPEMI);
861 const unsigned LogCPEAlign = Log2(A: CPEAlign);
862 if (LogCPEAlign >= 2)
863 Scale = 4;
864 else
865 // For constants with less than 4-byte alignment,
866 // we'll pretend the maximum offset is 255 * 1.
867 Scale = 1;
868 }
869 break;
870 case ARM::t2LEApcrel:
871 case ARM::t2LEApcrelJT:
872 Bits = 12;
873 NegOk = true;
874 break;
875 case ARM::tLEApcrel:
876 case ARM::tLEApcrelJT:
877 Bits = 8;
878 Scale = 4;
879 break;
880
881 case ARM::LDRBi12:
882 case ARM::LDRi12:
883 case ARM::LDRcp:
884 case ARM::t2LDRpci:
885 case ARM::t2LDRHpci:
886 case ARM::t2LDRSHpci:
887 case ARM::t2LDRBpci:
888 case ARM::t2LDRSBpci:
889 Bits = 12; // +-offset_12
890 NegOk = true;
891 break;
892
893 case ARM::tLDRpci:
894 Bits = 8;
895 Scale = 4; // +(offset_8*4)
896 break;
897
898 case ARM::VLDRD:
899 case ARM::VLDRS:
900 Bits = 8;
901 Scale = 4; // +-(offset_8*4)
902 NegOk = true;
903 break;
904 case ARM::VLDRH:
905 Bits = 8;
906 Scale = 2; // +-(offset_8*2)
907 NegOk = true;
908 break;
909 }
910
911 // Remember that this is a user of a CP entry.
912 unsigned CPI = I.getOperand(i: op).getIndex();
913 if (I.getOperand(i: op).isJTI()) {
914 JumpTableUserIndices.insert(KV: std::make_pair(x&: CPI, y: CPUsers.size()));
915 CPI = JumpTableEntryIndices[CPI];
916 }
917
918 MachineInstr *CPEMI = CPEMIs[CPI];
919 unsigned MaxOffs = ((1 << Bits)-1) * Scale;
920 CPUsers.push_back(x: CPUser(&I, CPEMI, MaxOffs, NegOk, IsSoImm));
921
922 // Increment corresponding CPEntry reference count.
923 CPEntry *CPE = findConstPoolEntry(CPI, CPEMI);
924 assert(CPE && "Cannot find a corresponding CPEntry!");
925 CPE->RefCount++;
926
927 // Instructions can only use one CP entry, don't bother scanning the
928 // rest of the operands.
929 break;
930 }
931 }
932 }
933}
934
935/// CompareMBBNumbers - Little predicate function to sort the WaterList by MBB
936/// ID.
937static bool CompareMBBNumbers(const MachineBasicBlock *LHS,
938 const MachineBasicBlock *RHS) {
939 return LHS->getNumber() < RHS->getNumber();
940}
941
942/// updateForInsertedWaterBlock - When a block is newly inserted into the
943/// machine function, it upsets all of the block numbers. Renumber the blocks
944/// and update the arrays that parallel this numbering.
945void ARMConstantIslands::updateForInsertedWaterBlock(MachineBasicBlock *NewBB) {
946 // Renumber the MBB's to keep them consecutive.
947 NewBB->getParent()->RenumberBlocks(MBBFrom: NewBB);
948
949 // Insert an entry into BBInfo to align it properly with the (newly
950 // renumbered) block numbers.
951 BBUtils->insert(BBNum: NewBB->getNumber(), BBI: BasicBlockInfo());
952
953 // Next, update WaterList. Specifically, we need to add NewMBB as having
954 // available water after it.
955 water_iterator IP = llvm::lower_bound(Range&: WaterList, Value&: NewBB, C: CompareMBBNumbers);
956 WaterList.insert(position: IP, x: NewBB);
957}
958
959/// Split the basic block containing MI into two blocks, which are joined by
960/// an unconditional branch. Update data structures and renumber blocks to
961/// account for this change and returns the newly created block.
962MachineBasicBlock *ARMConstantIslands::splitBlockBeforeInstr(MachineInstr *MI) {
963 MachineBasicBlock *OrigBB = MI->getParent();
964
965 // Collect liveness information at MI.
966 LivePhysRegs LRs(*MF->getSubtarget().getRegisterInfo());
967 LRs.addLiveOuts(MBB: *OrigBB);
968 auto LivenessEnd = ++MachineBasicBlock::iterator(MI).getReverse();
969 for (MachineInstr &LiveMI : make_range(x: OrigBB->rbegin(), y: LivenessEnd))
970 LRs.stepBackward(MI: LiveMI);
971
972 // Create a new MBB for the code after the OrigBB.
973 MachineBasicBlock *NewBB =
974 MF->CreateMachineBasicBlock(BB: OrigBB->getBasicBlock());
975 MachineFunction::iterator MBBI = ++OrigBB->getIterator();
976 MF->insert(MBBI, MBB: NewBB);
977
978 // Splice the instructions starting with MI over to NewBB.
979 NewBB->splice(Where: NewBB->end(), Other: OrigBB, From: MI, To: OrigBB->end());
980
981 // Add an unconditional branch from OrigBB to NewBB.
982 // Note the new unconditional branch is not being recorded.
983 // There doesn't seem to be meaningful DebugInfo available; this doesn't
984 // correspond to anything in the source.
985 unsigned Opc = isThumb ? (isThumb2 ? ARM::t2B : ARM::tB) : ARM::B;
986 if (!isThumb)
987 BuildMI(BB: OrigBB, MIMD: DebugLoc(), MCID: TII->get(Opcode: Opc)).addMBB(MBB: NewBB);
988 else
989 BuildMI(BB: OrigBB, MIMD: DebugLoc(), MCID: TII->get(Opcode: Opc))
990 .addMBB(MBB: NewBB)
991 .add(MOs: predOps(Pred: ARMCC::AL));
992 ++NumSplit;
993
994 // Update the CFG. All succs of OrigBB are now succs of NewBB.
995 NewBB->transferSuccessors(FromMBB: OrigBB);
996
997 // OrigBB branches to NewBB.
998 OrigBB->addSuccessor(Succ: NewBB);
999
1000 // Update live-in information in the new block.
1001 MachineRegisterInfo &MRI = MF->getRegInfo();
1002 for (MCPhysReg L : LRs)
1003 if (!MRI.isReserved(PhysReg: L))
1004 NewBB->addLiveIn(PhysReg: L);
1005
1006 // Update internal data structures to account for the newly inserted MBB.
1007 // This is almost the same as updateForInsertedWaterBlock, except that
1008 // the Water goes after OrigBB, not NewBB.
1009 MF->RenumberBlocks(MBBFrom: NewBB);
1010
1011 // Insert an entry into BBInfo to align it properly with the (newly
1012 // renumbered) block numbers.
1013 BBUtils->insert(BBNum: NewBB->getNumber(), BBI: BasicBlockInfo());
1014
1015 // Next, update WaterList. Specifically, we need to add OrigMBB as having
1016 // available water after it (but not if it's already there, which happens
1017 // when splitting before a conditional branch that is followed by an
1018 // unconditional branch - in that case we want to insert NewBB).
1019 water_iterator IP = llvm::lower_bound(Range&: WaterList, Value&: OrigBB, C: CompareMBBNumbers);
1020 MachineBasicBlock* WaterBB = *IP;
1021 if (WaterBB == OrigBB)
1022 WaterList.insert(position: std::next(x: IP), x: NewBB);
1023 else
1024 WaterList.insert(position: IP, x: OrigBB);
1025 NewWaterList.insert(Ptr: OrigBB);
1026
1027 // Figure out how large the OrigBB is. As the first half of the original
1028 // block, it cannot contain a tablejump. The size includes
1029 // the new jump we added. (It should be possible to do this without
1030 // recounting everything, but it's very confusing, and this is rarely
1031 // executed.)
1032 BBUtils->computeBlockSize(MBB: OrigBB);
1033
1034 // Figure out how large the NewMBB is. As the second half of the original
1035 // block, it may contain a tablejump.
1036 BBUtils->computeBlockSize(MBB: NewBB);
1037
1038 // All BBOffsets following these blocks must be modified.
1039 BBUtils->adjustBBOffsetsAfter(MBB: OrigBB);
1040
1041 return NewBB;
1042}
1043
1044/// getUserOffset - Compute the offset of U.MI as seen by the hardware
1045/// displacement computation. Update U.KnownAlignment to match its current
1046/// basic block location.
1047unsigned ARMConstantIslands::getUserOffset(CPUser &U) const {
1048 unsigned UserOffset = BBUtils->getOffsetOf(MI: U.MI);
1049
1050 SmallVectorImpl<BasicBlockInfo> &BBInfo = BBUtils->getBBInfo();
1051 const BasicBlockInfo &BBI = BBInfo[U.MI->getParent()->getNumber()];
1052 unsigned KnownBits = BBI.internalKnownBits();
1053
1054 // The value read from PC is offset from the actual instruction address.
1055 UserOffset += (isThumb ? 4 : 8);
1056
1057 // Because of inline assembly, we may not know the alignment (mod 4) of U.MI.
1058 // Make sure U.getMaxDisp() returns a constrained range.
1059 U.KnownAlignment = (KnownBits >= 2);
1060
1061 // On Thumb, offsets==2 mod 4 are rounded down by the hardware for
1062 // purposes of the displacement computation; compensate for that here.
1063 // For unknown alignments, getMaxDisp() constrains the range instead.
1064 if (isThumb && U.KnownAlignment)
1065 UserOffset &= ~3u;
1066
1067 return UserOffset;
1068}
1069
1070/// isOffsetInRange - Checks whether UserOffset (the location of a constant pool
1071/// reference) is within MaxDisp of TrialOffset (a proposed location of a
1072/// constant pool entry).
1073/// UserOffset is computed by getUserOffset above to include PC adjustments. If
1074/// the mod 4 alignment of UserOffset is not known, the uncertainty must be
1075/// subtracted from MaxDisp instead. CPUser::getMaxDisp() does that.
1076bool ARMConstantIslands::isOffsetInRange(unsigned UserOffset,
1077 unsigned TrialOffset, unsigned MaxDisp,
1078 bool NegativeOK, bool IsSoImm) {
1079 if (UserOffset <= TrialOffset) {
1080 // User before the Trial.
1081 if (TrialOffset - UserOffset <= MaxDisp)
1082 return true;
1083 // FIXME: Make use full range of soimm values.
1084 } else if (NegativeOK) {
1085 if (UserOffset - TrialOffset <= MaxDisp)
1086 return true;
1087 // FIXME: Make use full range of soimm values.
1088 }
1089 return false;
1090}
1091
1092/// isWaterInRange - Returns true if a CPE placed after the specified
1093/// Water (a basic block) will be in range for the specific MI.
1094///
1095/// Compute how much the function will grow by inserting a CPE after Water.
1096bool ARMConstantIslands::isWaterInRange(unsigned UserOffset,
1097 MachineBasicBlock* Water, CPUser &U,
1098 unsigned &Growth) {
1099 BBInfoVector &BBInfo = BBUtils->getBBInfo();
1100 const Align CPEAlign = getCPEAlign(CPEMI: U.CPEMI);
1101 const unsigned CPEOffset = BBInfo[Water->getNumber()].postOffset(Alignment: CPEAlign);
1102 unsigned NextBlockOffset;
1103 Align NextBlockAlignment;
1104 MachineFunction::const_iterator NextBlock = Water->getIterator();
1105 if (++NextBlock == MF->end()) {
1106 NextBlockOffset = BBInfo[Water->getNumber()].postOffset();
1107 } else {
1108 NextBlockOffset = BBInfo[NextBlock->getNumber()].Offset;
1109 NextBlockAlignment = NextBlock->getAlignment();
1110 }
1111 unsigned Size = U.CPEMI->getOperand(i: 2).getImm();
1112 unsigned CPEEnd = CPEOffset + Size;
1113
1114 // The CPE may be able to hide in the alignment padding before the next
1115 // block. It may also cause more padding to be required if it is more aligned
1116 // that the next block.
1117 if (CPEEnd > NextBlockOffset) {
1118 Growth = CPEEnd - NextBlockOffset;
1119 // Compute the padding that would go at the end of the CPE to align the next
1120 // block.
1121 Growth += offsetToAlignment(Value: CPEEnd, Alignment: NextBlockAlignment);
1122
1123 // If the CPE is to be inserted before the instruction, that will raise
1124 // the offset of the instruction. Also account for unknown alignment padding
1125 // in blocks between CPE and the user.
1126 if (CPEOffset < UserOffset)
1127 UserOffset += Growth + UnknownPadding(Alignment: MF->getAlignment(), KnownBits: Log2(A: CPEAlign));
1128 } else
1129 // CPE fits in existing padding.
1130 Growth = 0;
1131
1132 return isOffsetInRange(UserOffset, TrialOffset: CPEOffset, U);
1133}
1134
1135/// isCPEntryInRange - Returns true if the distance between specific MI and
1136/// specific ConstPool entry instruction can fit in MI's displacement field.
1137bool ARMConstantIslands::isCPEntryInRange(MachineInstr *MI, unsigned UserOffset,
1138 MachineInstr *CPEMI, unsigned MaxDisp,
1139 bool NegOk, bool DoDump) {
1140 unsigned CPEOffset = BBUtils->getOffsetOf(MI: CPEMI);
1141
1142 if (DoDump) {
1143 LLVM_DEBUG({
1144 BBInfoVector &BBInfo = BBUtils->getBBInfo();
1145 unsigned Block = MI->getParent()->getNumber();
1146 const BasicBlockInfo &BBI = BBInfo[Block];
1147 dbgs() << "User of CPE#" << CPEMI->getOperand(0).getImm()
1148 << " max delta=" << MaxDisp
1149 << format(" insn address=%#x", UserOffset) << " in "
1150 << printMBBReference(*MI->getParent()) << ": "
1151 << format("%#x-%x\t", BBI.Offset, BBI.postOffset()) << *MI
1152 << format("CPE address=%#x offset=%+d: ", CPEOffset,
1153 int(CPEOffset - UserOffset));
1154 });
1155 }
1156
1157 return isOffsetInRange(UserOffset, TrialOffset: CPEOffset, MaxDisp, NegativeOK: NegOk);
1158}
1159
1160#ifndef NDEBUG
1161/// BBIsJumpedOver - Return true of the specified basic block's only predecessor
1162/// unconditionally branches to its only successor.
1163static bool BBIsJumpedOver(MachineBasicBlock *MBB) {
1164 if (MBB->pred_size() != 1 || MBB->succ_size() != 1)
1165 return false;
1166
1167 MachineBasicBlock *Succ = *MBB->succ_begin();
1168 MachineBasicBlock *Pred = *MBB->pred_begin();
1169 MachineInstr *PredMI = &Pred->back();
1170 if (PredMI->getOpcode() == ARM::B || PredMI->getOpcode() == ARM::tB
1171 || PredMI->getOpcode() == ARM::t2B)
1172 return PredMI->getOperand(0).getMBB() == Succ;
1173 return false;
1174}
1175#endif // NDEBUG
1176
1177/// decrementCPEReferenceCount - find the constant pool entry with index CPI
1178/// and instruction CPEMI, and decrement its refcount. If the refcount
1179/// becomes 0 remove the entry and instruction. Returns true if we removed
1180/// the entry, false if we didn't.
1181bool ARMConstantIslands::decrementCPEReferenceCount(unsigned CPI,
1182 MachineInstr *CPEMI) {
1183 // Find the old entry. Eliminate it if it is no longer used.
1184 CPEntry *CPE = findConstPoolEntry(CPI, CPEMI);
1185 assert(CPE && "Unexpected!");
1186 if (--CPE->RefCount == 0) {
1187 removeDeadCPEMI(CPEMI);
1188 CPE->CPEMI = nullptr;
1189 --NumCPEs;
1190 return true;
1191 }
1192 return false;
1193}
1194
1195unsigned ARMConstantIslands::getCombinedIndex(const MachineInstr *CPEMI) {
1196 if (CPEMI->getOperand(i: 1).isCPI())
1197 return CPEMI->getOperand(i: 1).getIndex();
1198
1199 return JumpTableEntryIndices[CPEMI->getOperand(i: 1).getIndex()];
1200}
1201
1202/// LookForCPEntryInRange - see if the currently referenced CPE is in range;
1203/// if not, see if an in-range clone of the CPE is in range, and if so,
1204/// change the data structures so the user references the clone. Returns:
1205/// 0 = no existing entry found
1206/// 1 = entry found, and there were no code insertions or deletions
1207/// 2 = entry found, and there were code insertions or deletions
1208int ARMConstantIslands::findInRangeCPEntry(CPUser& U, unsigned UserOffset) {
1209 MachineInstr *UserMI = U.MI;
1210 MachineInstr *CPEMI = U.CPEMI;
1211
1212 // Check to see if the CPE is already in-range.
1213 if (isCPEntryInRange(MI: UserMI, UserOffset, CPEMI, MaxDisp: U.getMaxDisp(), NegOk: U.NegOk,
1214 DoDump: true)) {
1215 LLVM_DEBUG(dbgs() << "In range\n");
1216 return 1;
1217 }
1218
1219 // No. Look for previously created clones of the CPE that are in range.
1220 unsigned CPI = getCombinedIndex(CPEMI);
1221 std::vector<CPEntry> &CPEs = CPEntries[CPI];
1222 for (CPEntry &CPE : CPEs) {
1223 // We already tried this one
1224 if (CPE.CPEMI == CPEMI)
1225 continue;
1226 // Removing CPEs can leave empty entries, skip
1227 if (CPE.CPEMI == nullptr)
1228 continue;
1229 if (isCPEntryInRange(MI: UserMI, UserOffset, CPEMI: CPE.CPEMI, MaxDisp: U.getMaxDisp(),
1230 NegOk: U.NegOk)) {
1231 LLVM_DEBUG(dbgs() << "Replacing CPE#" << CPI << " with CPE#" << CPE.CPI
1232 << "\n");
1233 // Point the CPUser node to the replacement
1234 U.CPEMI = CPE.CPEMI;
1235 // Change the CPI in the instruction operand to refer to the clone.
1236 for (MachineOperand &MO : UserMI->operands())
1237 if (MO.isCPI()) {
1238 MO.setIndex(CPE.CPI);
1239 break;
1240 }
1241 // Adjust the refcount of the clone...
1242 CPE.RefCount++;
1243 // ...and the original. If we didn't remove the old entry, none of the
1244 // addresses changed, so we don't need another pass.
1245 return decrementCPEReferenceCount(CPI, CPEMI) ? 2 : 1;
1246 }
1247 }
1248 return 0;
1249}
1250
1251/// getUnconditionalBrDisp - Returns the maximum displacement that can fit in
1252/// the specific unconditional branch instruction.
1253static inline unsigned getUnconditionalBrDisp(int Opc) {
1254 switch (Opc) {
1255 case ARM::tB:
1256 return ((1<<10)-1)*2;
1257 case ARM::t2B:
1258 return ((1<<23)-1)*2;
1259 default:
1260 break;
1261 }
1262
1263 return ((1<<23)-1)*4;
1264}
1265
1266/// findAvailableWater - Look for an existing entry in the WaterList in which
1267/// we can place the CPE referenced from U so it's within range of U's MI.
1268/// Returns true if found, false if not. If it returns true, WaterIter
1269/// is set to the WaterList entry. For Thumb, prefer water that will not
1270/// introduce padding to water that will. To ensure that this pass
1271/// terminates, the CPE location for a particular CPUser is only allowed to
1272/// move to a lower address, so search backward from the end of the list and
1273/// prefer the first water that is in range.
1274bool ARMConstantIslands::findAvailableWater(CPUser &U, unsigned UserOffset,
1275 water_iterator &WaterIter,
1276 bool CloserWater) {
1277 if (WaterList.empty())
1278 return false;
1279
1280 unsigned BestGrowth = ~0u;
1281 // The nearest water without splitting the UserBB is right after it.
1282 // If the distance is still large (we have a big BB), then we need to split it
1283 // if we don't converge after certain iterations. This helps the following
1284 // situation to converge:
1285 // BB0:
1286 // Big BB
1287 // BB1:
1288 // Constant Pool
1289 // When a CP access is out of range, BB0 may be used as water. However,
1290 // inserting islands between BB0 and BB1 makes other accesses out of range.
1291 MachineBasicBlock *UserBB = U.MI->getParent();
1292 BBInfoVector &BBInfo = BBUtils->getBBInfo();
1293 const Align CPEAlign = getCPEAlign(CPEMI: U.CPEMI);
1294 unsigned MinNoSplitDisp = BBInfo[UserBB->getNumber()].postOffset(Alignment: CPEAlign);
1295 if (CloserWater && MinNoSplitDisp > U.getMaxDisp() / 2)
1296 return false;
1297 for (water_iterator IP = std::prev(x: WaterList.end()), B = WaterList.begin();;
1298 --IP) {
1299 MachineBasicBlock* WaterBB = *IP;
1300 // Check if water is in range and is either at a lower address than the
1301 // current "high water mark" or a new water block that was created since
1302 // the previous iteration by inserting an unconditional branch. In the
1303 // latter case, we want to allow resetting the high water mark back to
1304 // this new water since we haven't seen it before. Inserting branches
1305 // should be relatively uncommon and when it does happen, we want to be
1306 // sure to take advantage of it for all the CPEs near that block, so that
1307 // we don't insert more branches than necessary.
1308 // When CloserWater is true, we try to find the lowest address after (or
1309 // equal to) user MI's BB no matter of padding growth.
1310 unsigned Growth;
1311 if (isWaterInRange(UserOffset, Water: WaterBB, U, Growth) &&
1312 (WaterBB->getNumber() < U.HighWaterMark->getNumber() ||
1313 NewWaterList.count(Ptr: WaterBB) || WaterBB == U.MI->getParent()) &&
1314 Growth < BestGrowth) {
1315 // This is the least amount of required padding seen so far.
1316 BestGrowth = Growth;
1317 WaterIter = IP;
1318 LLVM_DEBUG(dbgs() << "Found water after " << printMBBReference(*WaterBB)
1319 << " Growth=" << Growth << '\n');
1320
1321 if (CloserWater && WaterBB == U.MI->getParent())
1322 return true;
1323 // Keep looking unless it is perfect and we're not looking for the lowest
1324 // possible address.
1325 if (!CloserWater && BestGrowth == 0)
1326 return true;
1327 }
1328 if (IP == B)
1329 break;
1330 }
1331 return BestGrowth != ~0u;
1332}
1333
1334/// createNewWater - No existing WaterList entry will work for
1335/// CPUsers[CPUserIndex], so create a place to put the CPE. The end of the
1336/// block is used if in range, and the conditional branch munged so control
1337/// flow is correct. Otherwise the block is split to create a hole with an
1338/// unconditional branch around it. In either case NewMBB is set to a
1339/// block following which the new island can be inserted (the WaterList
1340/// is not adjusted).
1341void ARMConstantIslands::createNewWater(unsigned CPUserIndex,
1342 unsigned UserOffset,
1343 MachineBasicBlock *&NewMBB) {
1344 CPUser &U = CPUsers[CPUserIndex];
1345 MachineInstr *UserMI = U.MI;
1346 MachineInstr *CPEMI = U.CPEMI;
1347 const Align CPEAlign = getCPEAlign(CPEMI);
1348 MachineBasicBlock *UserMBB = UserMI->getParent();
1349 BBInfoVector &BBInfo = BBUtils->getBBInfo();
1350 const BasicBlockInfo &UserBBI = BBInfo[UserMBB->getNumber()];
1351
1352 // If the block does not end in an unconditional branch already, and if the
1353 // end of the block is within range, make new water there. (The addition
1354 // below is for the unconditional branch we will be adding: 4 bytes on ARM +
1355 // Thumb2, 2 on Thumb1.
1356 if (BBHasFallthrough(MBB: UserMBB)) {
1357 // Size of branch to insert.
1358 unsigned Delta = isThumb1 ? 2 : 4;
1359 // Compute the offset where the CPE will begin.
1360 unsigned CPEOffset = UserBBI.postOffset(Alignment: CPEAlign) + Delta;
1361
1362 if (isOffsetInRange(UserOffset, TrialOffset: CPEOffset, U)) {
1363 LLVM_DEBUG(dbgs() << "Split at end of " << printMBBReference(*UserMBB)
1364 << format(", expected CPE offset %#x\n", CPEOffset));
1365 NewMBB = &*++UserMBB->getIterator();
1366 // Add an unconditional branch from UserMBB to fallthrough block. Record
1367 // it for branch lengthening; this new branch will not get out of range,
1368 // but if the preceding conditional branch is out of range, the targets
1369 // will be exchanged, and the altered branch may be out of range, so the
1370 // machinery has to know about it.
1371 int UncondBr = isThumb ? ((isThumb2) ? ARM::t2B : ARM::tB) : ARM::B;
1372 if (!isThumb)
1373 BuildMI(BB: UserMBB, MIMD: DebugLoc(), MCID: TII->get(Opcode: UncondBr)).addMBB(MBB: NewMBB);
1374 else
1375 BuildMI(BB: UserMBB, MIMD: DebugLoc(), MCID: TII->get(Opcode: UncondBr))
1376 .addMBB(MBB: NewMBB)
1377 .add(MOs: predOps(Pred: ARMCC::AL));
1378 unsigned MaxDisp = getUnconditionalBrDisp(Opc: UncondBr);
1379 ImmBranches.push_back(x: ImmBranch(&UserMBB->back(),
1380 MaxDisp, false, UncondBr));
1381 BBUtils->computeBlockSize(MBB: UserMBB);
1382 BBUtils->adjustBBOffsetsAfter(MBB: UserMBB);
1383 return;
1384 }
1385 }
1386
1387 // What a big block. Find a place within the block to split it. This is a
1388 // little tricky on Thumb1 since instructions are 2 bytes and constant pool
1389 // entries are 4 bytes: if instruction I references island CPE, and
1390 // instruction I+1 references CPE', it will not work well to put CPE as far
1391 // forward as possible, since then CPE' cannot immediately follow it (that
1392 // location is 2 bytes farther away from I+1 than CPE was from I) and we'd
1393 // need to create a new island. So, we make a first guess, then walk through
1394 // the instructions between the one currently being looked at and the
1395 // possible insertion point, and make sure any other instructions that
1396 // reference CPEs will be able to use the same island area; if not, we back
1397 // up the insertion point.
1398
1399 // Try to split the block so it's fully aligned. Compute the latest split
1400 // point where we can add a 4-byte branch instruction, and then align to
1401 // Align which is the largest possible alignment in the function.
1402 const Align Align = MF->getAlignment();
1403 assert(Align >= CPEAlign && "Over-aligned constant pool entry");
1404 unsigned KnownBits = UserBBI.internalKnownBits();
1405 unsigned UPad = UnknownPadding(Alignment: Align, KnownBits);
1406 unsigned BaseInsertOffset = UserOffset + U.getMaxDisp() - UPad;
1407 LLVM_DEBUG(dbgs() << format("Split in middle of big block before %#x",
1408 BaseInsertOffset));
1409
1410 // The 4 in the following is for the unconditional branch we'll be inserting
1411 // (allows for long branch on Thumb1). Alignment of the island is handled
1412 // inside isOffsetInRange.
1413 BaseInsertOffset -= 4;
1414
1415 LLVM_DEBUG(dbgs() << format(", adjusted to %#x", BaseInsertOffset)
1416 << " la=" << Log2(Align) << " kb=" << KnownBits
1417 << " up=" << UPad << '\n');
1418
1419 // This could point off the end of the block if we've already got constant
1420 // pool entries following this block; only the last one is in the water list.
1421 // Back past any possible branches (allow for a conditional and a maximally
1422 // long unconditional).
1423 if (BaseInsertOffset + 8 >= UserBBI.postOffset()) {
1424 // Ensure BaseInsertOffset is larger than the offset of the instruction
1425 // following UserMI so that the loop which searches for the split point
1426 // iterates at least once.
1427 BaseInsertOffset =
1428 std::max(a: UserBBI.postOffset() - UPad - 8,
1429 b: UserOffset + TII->getInstSizeInBytes(MI: *UserMI) + 1);
1430 // If the CP is referenced(ie, UserOffset) is in first four instructions
1431 // after IT, this recalculated BaseInsertOffset could be in the middle of
1432 // an IT block. If it is, change the BaseInsertOffset to just after the
1433 // IT block. This still make the CP Entry is in range because of the
1434 // following reasons.
1435 // 1. The initial BaseseInsertOffset calculated is (UserOffset +
1436 // U.getMaxDisp() - UPad).
1437 // 2. An IT block is only at most 4 instructions plus the "it" itself (18
1438 // bytes).
1439 // 3. All the relevant instructions support much larger Maximum
1440 // displacement.
1441 MachineBasicBlock::iterator I = UserMI;
1442 ++I;
1443 Register PredReg;
1444 for (unsigned Offset = UserOffset + TII->getInstSizeInBytes(MI: *UserMI);
1445 I->getOpcode() != ARM::t2IT &&
1446 getITInstrPredicate(MI: *I, PredReg) != ARMCC::AL;
1447 Offset += TII->getInstSizeInBytes(MI: *I), I = std::next(x: I)) {
1448 BaseInsertOffset =
1449 std::max(a: BaseInsertOffset, b: Offset + TII->getInstSizeInBytes(MI: *I) + 1);
1450 assert(I != UserMBB->end() && "Fell off end of block");
1451 }
1452 LLVM_DEBUG(dbgs() << format("Move inside block: %#x\n", BaseInsertOffset));
1453 }
1454 unsigned EndInsertOffset = BaseInsertOffset + 4 + UPad +
1455 CPEMI->getOperand(i: 2).getImm();
1456 MachineBasicBlock::iterator MI = UserMI;
1457 ++MI;
1458 unsigned CPUIndex = CPUserIndex+1;
1459 unsigned NumCPUsers = CPUsers.size();
1460 MachineInstr *LastIT = nullptr;
1461 for (unsigned Offset = UserOffset + TII->getInstSizeInBytes(MI: *UserMI);
1462 Offset < BaseInsertOffset;
1463 Offset += TII->getInstSizeInBytes(MI: *MI), MI = std::next(x: MI)) {
1464 assert(MI != UserMBB->end() && "Fell off end of block");
1465 if (CPUIndex < NumCPUsers && CPUsers[CPUIndex].MI == &*MI) {
1466 CPUser &U = CPUsers[CPUIndex];
1467 if (!isOffsetInRange(UserOffset: Offset, TrialOffset: EndInsertOffset, U)) {
1468 // Shift intertion point by one unit of alignment so it is within reach.
1469 BaseInsertOffset -= Align.value();
1470 EndInsertOffset -= Align.value();
1471 }
1472 // This is overly conservative, as we don't account for CPEMIs being
1473 // reused within the block, but it doesn't matter much. Also assume CPEs
1474 // are added in order with alignment padding. We may eventually be able
1475 // to pack the aligned CPEs better.
1476 EndInsertOffset += U.CPEMI->getOperand(i: 2).getImm();
1477 CPUIndex++;
1478 }
1479
1480 // Remember the last IT instruction.
1481 if (MI->getOpcode() == ARM::t2IT)
1482 LastIT = &*MI;
1483 }
1484
1485 --MI;
1486
1487 // Avoid splitting an IT block.
1488 if (LastIT) {
1489 Register PredReg;
1490 ARMCC::CondCodes CC = getITInstrPredicate(MI: *MI, PredReg);
1491 if (CC != ARMCC::AL)
1492 MI = LastIT;
1493 }
1494
1495 // Avoid splitting a MOVW+MOVT pair with a relocation on Windows.
1496 // On Windows, this instruction pair is covered by one single
1497 // IMAGE_REL_ARM_MOV32T relocation which covers both instructions. If a
1498 // constant island is injected inbetween them, the relocation will clobber
1499 // the instruction and fail to update the MOVT instruction.
1500 // (These instructions are bundled up until right before the ConstantIslands
1501 // pass.)
1502 if (STI->isTargetWindows() && isThumb && MI->getOpcode() == ARM::t2MOVTi16 &&
1503 (MI->getOperand(i: 2).getTargetFlags() & ARMII::MO_OPTION_MASK) ==
1504 ARMII::MO_HI16) {
1505 --MI;
1506 assert(MI->getOpcode() == ARM::t2MOVi16 &&
1507 (MI->getOperand(1).getTargetFlags() & ARMII::MO_OPTION_MASK) ==
1508 ARMII::MO_LO16);
1509 }
1510
1511 // We really must not split an IT block.
1512#ifndef NDEBUG
1513 Register PredReg;
1514 assert(!isThumb || getITInstrPredicate(*MI, PredReg) == ARMCC::AL);
1515#endif
1516 NewMBB = splitBlockBeforeInstr(MI: &*MI);
1517}
1518
1519/// handleConstantPoolUser - Analyze the specified user, checking to see if it
1520/// is out-of-range. If so, pick up the constant pool value and move it some
1521/// place in-range. Return true if we changed any addresses (thus must run
1522/// another pass of branch lengthening), false otherwise.
1523bool ARMConstantIslands::handleConstantPoolUser(unsigned CPUserIndex,
1524 bool CloserWater) {
1525 CPUser &U = CPUsers[CPUserIndex];
1526 MachineInstr *UserMI = U.MI;
1527 MachineInstr *CPEMI = U.CPEMI;
1528 unsigned CPI = getCombinedIndex(CPEMI);
1529 unsigned Size = CPEMI->getOperand(i: 2).getImm();
1530 // Compute this only once, it's expensive.
1531 unsigned UserOffset = getUserOffset(U);
1532
1533 // See if the current entry is within range, or there is a clone of it
1534 // in range.
1535 int result = findInRangeCPEntry(U, UserOffset);
1536 if (result==1) return false;
1537 else if (result==2) return true;
1538
1539 // No existing clone of this CPE is within range.
1540 // We will be generating a new clone. Get a UID for it.
1541 unsigned ID = AFI->createPICLabelUId();
1542
1543 // Look for water where we can place this CPE.
1544 MachineBasicBlock *NewIsland = MF->CreateMachineBasicBlock();
1545 MachineBasicBlock *NewMBB;
1546 water_iterator IP;
1547 if (findAvailableWater(U, UserOffset, WaterIter&: IP, CloserWater)) {
1548 LLVM_DEBUG(dbgs() << "Found water in range\n");
1549 MachineBasicBlock *WaterBB = *IP;
1550
1551 // If the original WaterList entry was "new water" on this iteration,
1552 // propagate that to the new island. This is just keeping NewWaterList
1553 // updated to match the WaterList, which will be updated below.
1554 if (NewWaterList.erase(Ptr: WaterBB))
1555 NewWaterList.insert(Ptr: NewIsland);
1556
1557 // The new CPE goes before the following block (NewMBB).
1558 NewMBB = &*++WaterBB->getIterator();
1559 } else {
1560 // No water found.
1561 LLVM_DEBUG(dbgs() << "No water found\n");
1562 createNewWater(CPUserIndex, UserOffset, NewMBB);
1563
1564 // splitBlockBeforeInstr adds to WaterList, which is important when it is
1565 // called while handling branches so that the water will be seen on the
1566 // next iteration for constant pools, but in this context, we don't want
1567 // it. Check for this so it will be removed from the WaterList.
1568 // Also remove any entry from NewWaterList.
1569 MachineBasicBlock *WaterBB = &*--NewMBB->getIterator();
1570 IP = find(Range&: WaterList, Val: WaterBB);
1571 if (IP != WaterList.end())
1572 NewWaterList.erase(Ptr: WaterBB);
1573
1574 // We are adding new water. Update NewWaterList.
1575 NewWaterList.insert(Ptr: NewIsland);
1576 }
1577 // Always align the new block because CP entries can be smaller than 4
1578 // bytes. Be careful not to decrease the existing alignment, e.g. NewMBB may
1579 // be an already aligned constant pool block.
1580 const Align Alignment = isThumb ? Align(2) : Align(4);
1581 if (NewMBB->getAlignment() < Alignment)
1582 NewMBB->setAlignment(Alignment);
1583
1584 // Remove the original WaterList entry; we want subsequent insertions in
1585 // this vicinity to go after the one we're about to insert. This
1586 // considerably reduces the number of times we have to move the same CPE
1587 // more than once and is also important to ensure the algorithm terminates.
1588 if (IP != WaterList.end())
1589 WaterList.erase(position: IP);
1590
1591 // Okay, we know we can put an island before NewMBB now, do it!
1592 MF->insert(MBBI: NewMBB->getIterator(), MBB: NewIsland);
1593
1594 // Update internal data structures to account for the newly inserted MBB.
1595 updateForInsertedWaterBlock(NewBB: NewIsland);
1596
1597 // Now that we have an island to add the CPE to, clone the original CPE and
1598 // add it to the island.
1599 U.HighWaterMark = NewIsland;
1600 U.CPEMI = BuildMI(BB: NewIsland, MIMD: DebugLoc(), MCID: CPEMI->getDesc())
1601 .addImm(Val: ID)
1602 .add(MO: CPEMI->getOperand(i: 1))
1603 .addImm(Val: Size);
1604 CPEntries[CPI].push_back(x: CPEntry(U.CPEMI, ID, 1));
1605 ++NumCPEs;
1606
1607 // Decrement the old entry, and remove it if refcount becomes 0.
1608 decrementCPEReferenceCount(CPI, CPEMI);
1609
1610 // Mark the basic block as aligned as required by the const-pool entry.
1611 NewIsland->setAlignment(getCPEAlign(CPEMI: U.CPEMI));
1612
1613 // Increase the size of the island block to account for the new entry.
1614 BBUtils->adjustBBSize(MBB: NewIsland, Size);
1615 BBUtils->adjustBBOffsetsAfter(MBB: &*--NewIsland->getIterator());
1616
1617 // Finally, change the CPI in the instruction operand to be ID.
1618 for (MachineOperand &MO : UserMI->operands())
1619 if (MO.isCPI()) {
1620 MO.setIndex(ID);
1621 break;
1622 }
1623
1624 LLVM_DEBUG(
1625 dbgs() << " Moved CPE to #" << ID << " CPI=" << CPI
1626 << format(" offset=%#x\n",
1627 BBUtils->getBBInfo()[NewIsland->getNumber()].Offset));
1628
1629 return true;
1630}
1631
1632/// removeDeadCPEMI - Remove a dead constant pool entry instruction. Update
1633/// sizes and offsets of impacted basic blocks.
1634void ARMConstantIslands::removeDeadCPEMI(MachineInstr *CPEMI) {
1635 MachineBasicBlock *CPEBB = CPEMI->getParent();
1636 unsigned Size = CPEMI->getOperand(i: 2).getImm();
1637 CPEMI->eraseFromParent();
1638 BBInfoVector &BBInfo = BBUtils->getBBInfo();
1639 BBUtils->adjustBBSize(MBB: CPEBB, Size: -Size);
1640 // All succeeding offsets have the current size value added in, fix this.
1641 if (CPEBB->empty()) {
1642 BBInfo[CPEBB->getNumber()].Size = 0;
1643
1644 // This block no longer needs to be aligned.
1645 CPEBB->setAlignment(Align(1));
1646 } else {
1647 // Entries are sorted by descending alignment, so realign from the front.
1648 CPEBB->setAlignment(getCPEAlign(CPEMI: &*CPEBB->begin()));
1649 }
1650
1651 BBUtils->adjustBBOffsetsAfter(MBB: CPEBB);
1652 // An island has only one predecessor BB and one successor BB. Check if
1653 // this BB's predecessor jumps directly to this BB's successor. This
1654 // shouldn't happen currently.
1655 assert(!BBIsJumpedOver(CPEBB) && "How did this happen?");
1656 // FIXME: remove the empty blocks after all the work is done?
1657}
1658
1659/// removeUnusedCPEntries - Remove constant pool entries whose refcounts
1660/// are zero.
1661bool ARMConstantIslands::removeUnusedCPEntries() {
1662 unsigned MadeChange = false;
1663 for (std::vector<CPEntry> &CPEs : CPEntries) {
1664 for (CPEntry &CPE : CPEs) {
1665 if (CPE.RefCount == 0 && CPE.CPEMI) {
1666 removeDeadCPEMI(CPEMI: CPE.CPEMI);
1667 CPE.CPEMI = nullptr;
1668 MadeChange = true;
1669 }
1670 }
1671 }
1672 return MadeChange;
1673}
1674
1675
1676/// fixupImmediateBr - Fix up an immediate branch whose destination is too far
1677/// away to fit in its displacement field.
1678bool ARMConstantIslands::fixupImmediateBr(ImmBranch &Br) {
1679 MachineInstr *MI = Br.MI;
1680 MachineBasicBlock *DestBB = MI->getOperand(i: 0).getMBB();
1681
1682 // Check to see if the DestBB is already in-range.
1683 if (BBUtils->isBBInRange(MI, DestBB, MaxDisp: Br.MaxDisp))
1684 return false;
1685
1686 if (!Br.isCond)
1687 return fixupUnconditionalBr(Br);
1688 return fixupConditionalBr(Br);
1689}
1690
1691/// fixupUnconditionalBr - Fix up an unconditional branch whose destination is
1692/// too far away to fit in its displacement field. If the LR register has been
1693/// spilled in the epilogue, then we can use BL to implement a far jump.
1694/// Otherwise, add an intermediate branch instruction to a branch.
1695bool
1696ARMConstantIslands::fixupUnconditionalBr(ImmBranch &Br) {
1697 MachineInstr *MI = Br.MI;
1698 MachineBasicBlock *MBB = MI->getParent();
1699 if (!isThumb1)
1700 llvm_unreachable("fixupUnconditionalBr is Thumb1 only!");
1701
1702 if (!AFI->isLRSpilled())
1703 report_fatal_error(reason: "underestimated function size");
1704
1705 // Use BL to implement far jump.
1706 Br.MaxDisp = (1 << 21) * 2;
1707 MI->setDesc(TII->get(Opcode: ARM::tBfar));
1708 BBInfoVector &BBInfo = BBUtils->getBBInfo();
1709 BBInfo[MBB->getNumber()].Size += 2;
1710 BBUtils->adjustBBOffsetsAfter(MBB);
1711 ++NumUBrFixed;
1712
1713 LLVM_DEBUG(dbgs() << " Changed B to long jump " << *MI);
1714
1715 return true;
1716}
1717
1718/// fixupConditionalBr - Fix up a conditional branch whose destination is too
1719/// far away to fit in its displacement field. It is converted to an inverse
1720/// conditional branch + an unconditional branch to the destination.
1721bool
1722ARMConstantIslands::fixupConditionalBr(ImmBranch &Br) {
1723 MachineInstr *MI = Br.MI;
1724 MachineBasicBlock *DestBB = MI->getOperand(i: 0).getMBB();
1725
1726 // Add an unconditional branch to the destination and invert the branch
1727 // condition to jump over it:
1728 // blt L1
1729 // =>
1730 // bge L2
1731 // b L1
1732 // L2:
1733 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(i: 1).getImm();
1734 CC = ARMCC::getOppositeCondition(CC);
1735 Register CCReg = MI->getOperand(i: 2).getReg();
1736
1737 // If the branch is at the end of its MBB and that has a fall-through block,
1738 // direct the updated conditional branch to the fall-through block. Otherwise,
1739 // split the MBB before the next instruction.
1740 MachineBasicBlock *MBB = MI->getParent();
1741 MachineInstr *BMI = &MBB->back();
1742 bool NeedSplit = (BMI != MI) || !BBHasFallthrough(MBB);
1743
1744 ++NumCBrFixed;
1745 if (BMI != MI) {
1746 if (std::next(x: MachineBasicBlock::iterator(MI)) == std::prev(x: MBB->end()) &&
1747 BMI->getOpcode() == Br.UncondBr) {
1748 // Last MI in the BB is an unconditional branch. Can we simply invert the
1749 // condition and swap destinations:
1750 // beq L1
1751 // b L2
1752 // =>
1753 // bne L2
1754 // b L1
1755 MachineBasicBlock *NewDest = BMI->getOperand(i: 0).getMBB();
1756 if (BBUtils->isBBInRange(MI, DestBB: NewDest, MaxDisp: Br.MaxDisp)) {
1757 LLVM_DEBUG(
1758 dbgs() << " Invert Bcc condition and swap its destination with "
1759 << *BMI);
1760 BMI->getOperand(i: 0).setMBB(DestBB);
1761 MI->getOperand(i: 0).setMBB(NewDest);
1762 MI->getOperand(i: 1).setImm(CC);
1763 return true;
1764 }
1765 }
1766 }
1767
1768 if (NeedSplit) {
1769 splitBlockBeforeInstr(MI);
1770 // No need for the branch to the next block. We're adding an unconditional
1771 // branch to the destination.
1772 int delta = TII->getInstSizeInBytes(MI: MBB->back());
1773 BBUtils->adjustBBSize(MBB, Size: -delta);
1774 MBB->back().eraseFromParent();
1775
1776 // The conditional successor will be swapped between the BBs after this, so
1777 // update CFG.
1778 MBB->addSuccessor(Succ: DestBB);
1779 std::next(x: MBB->getIterator())->removeSuccessor(Succ: DestBB);
1780
1781 // BBInfo[SplitBB].Offset is wrong temporarily, fixed below
1782 }
1783 MachineBasicBlock *NextBB = &*++MBB->getIterator();
1784
1785 LLVM_DEBUG(dbgs() << " Insert B to " << printMBBReference(*DestBB)
1786 << " also invert condition and change dest. to "
1787 << printMBBReference(*NextBB) << "\n");
1788
1789 // Insert a new conditional branch and a new unconditional branch.
1790 // Also update the ImmBranch as well as adding a new entry for the new branch.
1791 BuildMI(BB: MBB, MIMD: DebugLoc(), MCID: TII->get(Opcode: MI->getOpcode()))
1792 .addMBB(MBB: NextBB).addImm(Val: CC).addReg(RegNo: CCReg);
1793 Br.MI = &MBB->back();
1794 BBUtils->adjustBBSize(MBB, Size: TII->getInstSizeInBytes(MI: MBB->back()));
1795 if (isThumb)
1796 BuildMI(BB: MBB, MIMD: DebugLoc(), MCID: TII->get(Opcode: Br.UncondBr))
1797 .addMBB(MBB: DestBB)
1798 .add(MOs: predOps(Pred: ARMCC::AL));
1799 else
1800 BuildMI(BB: MBB, MIMD: DebugLoc(), MCID: TII->get(Opcode: Br.UncondBr)).addMBB(MBB: DestBB);
1801 BBUtils->adjustBBSize(MBB, Size: TII->getInstSizeInBytes(MI: MBB->back()));
1802 unsigned MaxDisp = getUnconditionalBrDisp(Opc: Br.UncondBr);
1803 ImmBranches.push_back(x: ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr));
1804
1805 // Remove the old conditional branch. It may or may not still be in MBB.
1806 BBUtils->adjustBBSize(MBB: MI->getParent(), Size: -TII->getInstSizeInBytes(MI: *MI));
1807 MI->eraseFromParent();
1808 BBUtils->adjustBBOffsetsAfter(MBB);
1809 return true;
1810}
1811
1812bool ARMConstantIslands::optimizeThumb2Instructions() {
1813 bool MadeChange = false;
1814
1815 // Shrink ADR and LDR from constantpool.
1816 for (CPUser &U : CPUsers) {
1817 unsigned Opcode = U.MI->getOpcode();
1818 unsigned NewOpc = 0;
1819 unsigned Scale = 1;
1820 unsigned Bits = 0;
1821 switch (Opcode) {
1822 default: break;
1823 case ARM::t2LEApcrel:
1824 if (isARMLowRegister(Reg: U.MI->getOperand(i: 0).getReg())) {
1825 NewOpc = ARM::tLEApcrel;
1826 Bits = 8;
1827 Scale = 4;
1828 }
1829 break;
1830 case ARM::t2LDRpci:
1831 if (isARMLowRegister(Reg: U.MI->getOperand(i: 0).getReg())) {
1832 NewOpc = ARM::tLDRpci;
1833 Bits = 8;
1834 Scale = 4;
1835 }
1836 break;
1837 }
1838
1839 if (!NewOpc)
1840 continue;
1841
1842 unsigned UserOffset = getUserOffset(U);
1843 unsigned MaxOffs = ((1 << Bits) - 1) * Scale;
1844
1845 // Be conservative with inline asm.
1846 if (!U.KnownAlignment)
1847 MaxOffs -= 2;
1848
1849 // FIXME: Check if offset is multiple of scale if scale is not 4.
1850 if (isCPEntryInRange(MI: U.MI, UserOffset, CPEMI: U.CPEMI, MaxDisp: MaxOffs, NegOk: false, DoDump: true)) {
1851 LLVM_DEBUG(dbgs() << "Shrink: " << *U.MI);
1852 U.MI->setDesc(TII->get(Opcode: NewOpc));
1853 MachineBasicBlock *MBB = U.MI->getParent();
1854 BBUtils->adjustBBSize(MBB, Size: -2);
1855 BBUtils->adjustBBOffsetsAfter(MBB);
1856 ++NumT2CPShrunk;
1857 MadeChange = true;
1858 }
1859 }
1860
1861 return MadeChange;
1862}
1863
1864
1865bool ARMConstantIslands::optimizeThumb2Branches() {
1866
1867 auto TryShrinkBranch = [this](ImmBranch &Br) {
1868 unsigned Opcode = Br.MI->getOpcode();
1869 unsigned NewOpc = 0;
1870 unsigned Scale = 1;
1871 unsigned Bits = 0;
1872 switch (Opcode) {
1873 default: break;
1874 case ARM::t2B:
1875 NewOpc = ARM::tB;
1876 Bits = 11;
1877 Scale = 2;
1878 break;
1879 case ARM::t2Bcc:
1880 NewOpc = ARM::tBcc;
1881 Bits = 8;
1882 Scale = 2;
1883 break;
1884 }
1885 if (NewOpc) {
1886 unsigned MaxOffs = ((1 << (Bits-1))-1) * Scale;
1887 MachineBasicBlock *DestBB = Br.MI->getOperand(i: 0).getMBB();
1888 if (BBUtils->isBBInRange(MI: Br.MI, DestBB, MaxDisp: MaxOffs)) {
1889 LLVM_DEBUG(dbgs() << "Shrink branch: " << *Br.MI);
1890 Br.MI->setDesc(TII->get(Opcode: NewOpc));
1891 MachineBasicBlock *MBB = Br.MI->getParent();
1892 BBUtils->adjustBBSize(MBB, Size: -2);
1893 BBUtils->adjustBBOffsetsAfter(MBB);
1894 ++NumT2BrShrunk;
1895 return true;
1896 }
1897 }
1898 return false;
1899 };
1900
1901 struct ImmCompare {
1902 MachineInstr* MI = nullptr;
1903 unsigned NewOpc = 0;
1904 };
1905
1906 auto FindCmpForCBZ = [this](ImmBranch &Br, ImmCompare &ImmCmp,
1907 MachineBasicBlock *DestBB) {
1908 ImmCmp.MI = nullptr;
1909 ImmCmp.NewOpc = 0;
1910
1911 // If the conditional branch doesn't kill CPSR, then CPSR can be liveout
1912 // so this transformation is not safe.
1913 if (!Br.MI->killsRegister(Reg: ARM::CPSR, /*TRI=*/nullptr))
1914 return false;
1915
1916 Register PredReg;
1917 unsigned NewOpc = 0;
1918 ARMCC::CondCodes Pred = getInstrPredicate(MI: *Br.MI, PredReg);
1919 if (Pred == ARMCC::EQ)
1920 NewOpc = ARM::tCBZ;
1921 else if (Pred == ARMCC::NE)
1922 NewOpc = ARM::tCBNZ;
1923 else
1924 return false;
1925
1926 // Check if the distance is within 126. Subtract starting offset by 2
1927 // because the cmp will be eliminated.
1928 unsigned BrOffset = BBUtils->getOffsetOf(MI: Br.MI) + 4 - 2;
1929 BBInfoVector &BBInfo = BBUtils->getBBInfo();
1930 unsigned DestOffset = BBInfo[DestBB->getNumber()].Offset;
1931 if (BrOffset >= DestOffset || (DestOffset - BrOffset) > 126)
1932 return false;
1933
1934 // Search backwards to find a tCMPi8
1935 auto *TRI = STI->getRegisterInfo();
1936 MachineInstr *CmpMI = findCMPToFoldIntoCBZ(Br: Br.MI, TRI);
1937 if (!CmpMI || CmpMI->getOpcode() != ARM::tCMPi8)
1938 return false;
1939
1940 ImmCmp.MI = CmpMI;
1941 ImmCmp.NewOpc = NewOpc;
1942 return true;
1943 };
1944
1945 auto TryConvertToLE = [this](ImmBranch &Br, ImmCompare &Cmp) {
1946 if (Br.MI->getOpcode() != ARM::t2Bcc || !STI->hasLOB() ||
1947 STI->hasMinSize())
1948 return false;
1949
1950 MachineBasicBlock *MBB = Br.MI->getParent();
1951 MachineBasicBlock *DestBB = Br.MI->getOperand(i: 0).getMBB();
1952 if (BBUtils->getOffsetOf(MBB) < BBUtils->getOffsetOf(MBB: DestBB) ||
1953 !BBUtils->isBBInRange(MI: Br.MI, DestBB, MaxDisp: 4094))
1954 return false;
1955
1956 if (!DT->dominates(A: DestBB, B: MBB))
1957 return false;
1958
1959 // We queried for the CBN?Z opcode based upon the 'ExitBB', the opposite
1960 // target of Br. So now we need to reverse the condition.
1961 Cmp.NewOpc = Cmp.NewOpc == ARM::tCBZ ? ARM::tCBNZ : ARM::tCBZ;
1962
1963 MachineInstrBuilder MIB = BuildMI(BB&: *MBB, I: Br.MI, MIMD: Br.MI->getDebugLoc(),
1964 MCID: TII->get(Opcode: ARM::t2LE));
1965 // Swapped a t2Bcc for a t2LE, so no need to update the size of the block.
1966 MIB.add(MO: Br.MI->getOperand(i: 0));
1967 Br.MI->eraseFromParent();
1968 Br.MI = MIB;
1969 ++NumLEInserted;
1970 return true;
1971 };
1972
1973 bool MadeChange = false;
1974
1975 // The order in which branches appear in ImmBranches is approximately their
1976 // order within the function body. By visiting later branches first, we reduce
1977 // the distance between earlier forward branches and their targets, making it
1978 // more likely that the cbn?z optimization, which can only apply to forward
1979 // branches, will succeed.
1980 for (ImmBranch &Br : reverse(C&: ImmBranches)) {
1981 MachineBasicBlock *DestBB = Br.MI->getOperand(i: 0).getMBB();
1982 MachineBasicBlock *MBB = Br.MI->getParent();
1983 MachineBasicBlock *ExitBB = &MBB->back() == Br.MI ?
1984 MBB->getFallThrough() :
1985 MBB->back().getOperand(i: 0).getMBB();
1986
1987 ImmCompare Cmp;
1988 if (FindCmpForCBZ(Br, Cmp, ExitBB) && TryConvertToLE(Br, Cmp)) {
1989 DestBB = ExitBB;
1990 MadeChange = true;
1991 } else {
1992 FindCmpForCBZ(Br, Cmp, DestBB);
1993 MadeChange |= TryShrinkBranch(Br);
1994 }
1995
1996 unsigned Opcode = Br.MI->getOpcode();
1997 if ((Opcode != ARM::tBcc && Opcode != ARM::t2LE) || !Cmp.NewOpc)
1998 continue;
1999
2000 Register Reg = Cmp.MI->getOperand(i: 0).getReg();
2001
2002 // Check for Kill flags on Reg. If they are present remove them and set kill
2003 // on the new CBZ.
2004 auto *TRI = STI->getRegisterInfo();
2005 MachineBasicBlock::iterator KillMI = Br.MI;
2006 bool RegKilled = false;
2007 do {
2008 --KillMI;
2009 if (KillMI->killsRegister(Reg, TRI)) {
2010 KillMI->clearRegisterKills(Reg, RegInfo: TRI);
2011 RegKilled = true;
2012 break;
2013 }
2014 } while (KillMI != Cmp.MI);
2015
2016 // Create the new CBZ/CBNZ
2017 LLVM_DEBUG(dbgs() << "Fold: " << *Cmp.MI << " and: " << *Br.MI);
2018 MachineInstr *NewBR =
2019 BuildMI(BB&: *MBB, I: Br.MI, MIMD: Br.MI->getDebugLoc(), MCID: TII->get(Opcode: Cmp.NewOpc))
2020 .addReg(RegNo: Reg, Flags: getKillRegState(B: RegKilled) |
2021 getRegState(RegOp: Cmp.MI->getOperand(i: 0)))
2022 .addMBB(MBB: DestBB, TargetFlags: Br.MI->getOperand(i: 0).getTargetFlags());
2023
2024 Cmp.MI->eraseFromParent();
2025
2026 if (Br.MI->getOpcode() == ARM::tBcc) {
2027 Br.MI->eraseFromParent();
2028 Br.MI = NewBR;
2029 BBUtils->adjustBBSize(MBB, Size: -2);
2030 } else if (MBB->back().getOpcode() != ARM::t2LE) {
2031 // An LE has been generated, but it's not the terminator - that is an
2032 // unconditional branch. However, the logic has now been reversed with the
2033 // CBN?Z being the conditional branch and the LE being the unconditional
2034 // branch. So this means we can remove the redundant unconditional branch
2035 // at the end of the block.
2036 MachineInstr *LastMI = &MBB->back();
2037 BBUtils->adjustBBSize(MBB, Size: -LastMI->getDesc().getSize());
2038 LastMI->eraseFromParent();
2039 }
2040 BBUtils->adjustBBOffsetsAfter(MBB);
2041 ++NumCBZ;
2042 MadeChange = true;
2043 }
2044
2045 return MadeChange;
2046}
2047
2048static bool isSimpleIndexCalc(MachineInstr &I, unsigned EntryReg,
2049 unsigned BaseReg) {
2050 if (I.getOpcode() != ARM::t2ADDrs)
2051 return false;
2052
2053 if (I.getOperand(i: 0).getReg() != EntryReg)
2054 return false;
2055
2056 if (I.getOperand(i: 1).getReg() != BaseReg)
2057 return false;
2058
2059 // FIXME: what about CC and IdxReg?
2060 return true;
2061}
2062
2063/// While trying to form a TBB/TBH instruction, we may (if the table
2064/// doesn't immediately follow the BR_JT) need access to the start of the
2065/// jump-table. We know one instruction that produces such a register; this
2066/// function works out whether that definition can be preserved to the BR_JT,
2067/// possibly by removing an intervening addition (which is usually needed to
2068/// calculate the actual entry to jump to).
2069bool ARMConstantIslands::preserveBaseRegister(MachineInstr *JumpMI,
2070 MachineInstr *LEAMI,
2071 unsigned &DeadSize,
2072 bool &CanDeleteLEA,
2073 bool &BaseRegKill) {
2074 if (JumpMI->getParent() != LEAMI->getParent())
2075 return false;
2076
2077 // Now we hope that we have at least these instructions in the basic block:
2078 // BaseReg = t2LEA ...
2079 // [...]
2080 // EntryReg = t2ADDrs BaseReg, ...
2081 // [...]
2082 // t2BR_JT EntryReg
2083 //
2084 // We have to be very conservative about what we recognise here though. The
2085 // main perturbing factors to watch out for are:
2086 // + Spills at any point in the chain: not direct problems but we would
2087 // expect a blocking Def of the spilled register so in practice what we
2088 // can do is limited.
2089 // + EntryReg == BaseReg: this is the one situation we should allow a Def
2090 // of BaseReg, but only if the t2ADDrs can be removed.
2091 // + Some instruction other than t2ADDrs computing the entry. Not seen in
2092 // the wild, but we should be careful.
2093 Register EntryReg = JumpMI->getOperand(i: 0).getReg();
2094 Register BaseReg = LEAMI->getOperand(i: 0).getReg();
2095
2096 CanDeleteLEA = true;
2097 BaseRegKill = false;
2098 MachineInstr *RemovableAdd = nullptr;
2099 MachineBasicBlock::iterator I(LEAMI);
2100 for (++I; &*I != JumpMI; ++I) {
2101 if (isSimpleIndexCalc(I&: *I, EntryReg, BaseReg)) {
2102 RemovableAdd = &*I;
2103 break;
2104 }
2105
2106 for (const MachineOperand &MO : I->operands()) {
2107 if (!MO.isReg() || !MO.getReg())
2108 continue;
2109 if (MO.isDef() && MO.getReg() == BaseReg)
2110 return false;
2111 if (MO.isUse() && MO.getReg() == BaseReg) {
2112 BaseRegKill = BaseRegKill || MO.isKill();
2113 CanDeleteLEA = false;
2114 }
2115 }
2116 }
2117
2118 if (!RemovableAdd)
2119 return true;
2120
2121 // Check the add really is removable, and that nothing else in the block
2122 // clobbers BaseReg.
2123 for (++I; &*I != JumpMI; ++I) {
2124 for (const MachineOperand &MO : I->operands()) {
2125 if (!MO.isReg() || !MO.getReg())
2126 continue;
2127 if (MO.isDef() && MO.getReg() == BaseReg)
2128 return false;
2129 if (MO.isUse() && MO.getReg() == EntryReg)
2130 RemovableAdd = nullptr;
2131 }
2132 }
2133
2134 if (RemovableAdd) {
2135 RemovableAdd->eraseFromParent();
2136 DeadSize += isThumb2 ? 4 : 2;
2137 } else if (BaseReg == EntryReg) {
2138 // The add wasn't removable, but clobbered the base for the TBB. So we can't
2139 // preserve it.
2140 return false;
2141 }
2142
2143 // We reached the end of the block without seeing another definition of
2144 // BaseReg (except, possibly the t2ADDrs, which was removed). BaseReg can be
2145 // used in the TBB/TBH if necessary.
2146 return true;
2147}
2148
2149/// Returns whether CPEMI is the first instruction in the block
2150/// immediately following JTMI (assumed to be a TBB or TBH terminator). If so,
2151/// we can switch the first register to PC and usually remove the address
2152/// calculation that preceded it.
2153static bool jumpTableFollowsTB(MachineInstr *JTMI, MachineInstr *CPEMI) {
2154 MachineFunction::iterator MBB = JTMI->getParent()->getIterator();
2155 MachineFunction *MF = MBB->getParent();
2156 ++MBB;
2157
2158 return MBB != MF->end() && !MBB->empty() && &*MBB->begin() == CPEMI;
2159}
2160
2161static void RemoveDeadAddBetweenLEAAndJT(MachineInstr *LEAMI,
2162 MachineInstr *JumpMI,
2163 unsigned &DeadSize) {
2164 // Remove a dead add between the LEA and JT, which used to compute EntryReg,
2165 // but the JT now uses PC. Finds the last ADD (if any) that def's EntryReg
2166 // and is not clobbered / used.
2167 MachineInstr *RemovableAdd = nullptr;
2168 Register EntryReg = JumpMI->getOperand(i: 0).getReg();
2169
2170 // Find the last ADD to set EntryReg
2171 MachineBasicBlock::iterator I(LEAMI);
2172 for (++I; &*I != JumpMI; ++I) {
2173 if (I->getOpcode() == ARM::t2ADDrs && I->getOperand(i: 0).getReg() == EntryReg)
2174 RemovableAdd = &*I;
2175 }
2176
2177 if (!RemovableAdd)
2178 return;
2179
2180 // Ensure EntryReg is not clobbered or used.
2181 MachineBasicBlock::iterator J(RemovableAdd);
2182 for (++J; &*J != JumpMI; ++J) {
2183 for (const MachineOperand &MO : J->operands()) {
2184 if (!MO.isReg() || !MO.getReg())
2185 continue;
2186 if (MO.isDef() && MO.getReg() == EntryReg)
2187 return;
2188 if (MO.isUse() && MO.getReg() == EntryReg)
2189 return;
2190 }
2191 }
2192
2193 LLVM_DEBUG(dbgs() << "Removing Dead Add: " << *RemovableAdd);
2194 RemovableAdd->eraseFromParent();
2195 DeadSize += 4;
2196}
2197
2198/// optimizeThumb2JumpTables - Use tbb / tbh instructions to generate smaller
2199/// jumptables when it's possible.
2200bool ARMConstantIslands::optimizeThumb2JumpTables() {
2201 bool MadeChange = false;
2202
2203 // FIXME: After the tables are shrunk, can we get rid some of the
2204 // constantpool tables?
2205 MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
2206 if (!MJTI) return false;
2207
2208 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
2209 for (MachineInstr *MI : T2JumpTables) {
2210 const MCInstrDesc &MCID = MI->getDesc();
2211 unsigned NumOps = MCID.getNumOperands();
2212 unsigned JTOpIdx = NumOps - (MI->isPredicable() ? 2 : 1);
2213 MachineOperand JTOP = MI->getOperand(i: JTOpIdx);
2214 unsigned JTI = JTOP.getIndex();
2215 assert(JTI < JT.size());
2216
2217 bool ByteOk = true;
2218 bool HalfWordOk = true;
2219 unsigned JTOffset = BBUtils->getOffsetOf(MI) + 4;
2220 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
2221 BBInfoVector &BBInfo = BBUtils->getBBInfo();
2222 for (MachineBasicBlock *MBB : JTBBs) {
2223 unsigned DstOffset = BBInfo[MBB->getNumber()].Offset;
2224 // Negative offset is not ok. FIXME: We should change BB layout to make
2225 // sure all the branches are forward.
2226 if (ByteOk && (DstOffset - JTOffset) > ((1<<8)-1)*2)
2227 ByteOk = false;
2228 unsigned TBHLimit = ((1<<16)-1)*2;
2229 if (HalfWordOk && (DstOffset - JTOffset) > TBHLimit)
2230 HalfWordOk = false;
2231 if (!ByteOk && !HalfWordOk)
2232 break;
2233 }
2234
2235 if (!ByteOk && !HalfWordOk)
2236 continue;
2237
2238 CPUser &User = CPUsers[JumpTableUserIndices[JTI]];
2239 MachineBasicBlock *MBB = MI->getParent();
2240 if (!MI->getOperand(i: 0).isKill()) // FIXME: needed now?
2241 continue;
2242
2243 unsigned DeadSize = 0;
2244 bool CanDeleteLEA = false;
2245 bool BaseRegKill = false;
2246
2247 unsigned IdxReg = ~0U;
2248 bool IdxRegKill = true;
2249 if (isThumb2) {
2250 IdxReg = MI->getOperand(i: 1).getReg();
2251 IdxRegKill = MI->getOperand(i: 1).isKill();
2252
2253 bool PreservedBaseReg =
2254 preserveBaseRegister(JumpMI: MI, LEAMI: User.MI, DeadSize, CanDeleteLEA, BaseRegKill);
2255 if (!jumpTableFollowsTB(JTMI: MI, CPEMI: User.CPEMI) && !PreservedBaseReg)
2256 continue;
2257 } else {
2258 // We're in thumb-1 mode, so we must have something like:
2259 // %idx = tLSLri %idx, 2
2260 // %base = tLEApcrelJT
2261 // %t = tLDRr %base, %idx
2262 Register BaseReg = User.MI->getOperand(i: 0).getReg();
2263
2264 MachineBasicBlock *UserMBB = User.MI->getParent();
2265 MachineBasicBlock::iterator Shift = User.MI->getIterator();
2266 if (Shift == UserMBB->begin())
2267 continue;
2268
2269 Shift = prev_nodbg(It: Shift, Begin: UserMBB->begin());
2270 if (Shift->getOpcode() != ARM::tLSLri ||
2271 Shift->getOperand(i: 3).getImm() != 2 ||
2272 !Shift->getOperand(i: 2).isKill())
2273 continue;
2274 IdxReg = Shift->getOperand(i: 2).getReg();
2275 Register ShiftedIdxReg = Shift->getOperand(i: 0).getReg();
2276
2277 // It's important that IdxReg is live until the actual TBB/TBH. Most of
2278 // the range is checked later, but the LEA might still clobber it and not
2279 // actually get removed.
2280 if (BaseReg == IdxReg && !jumpTableFollowsTB(JTMI: MI, CPEMI: User.CPEMI))
2281 continue;
2282
2283 MachineInstr *Load = User.MI->getNextNode();
2284 if (Load->getOpcode() != ARM::tLDRr)
2285 continue;
2286 if (Load->getOperand(i: 1).getReg() != BaseReg ||
2287 Load->getOperand(i: 2).getReg() != ShiftedIdxReg ||
2288 !Load->getOperand(i: 2).isKill())
2289 continue;
2290
2291 // If we're in PIC mode, there should be another ADD following.
2292 auto *TRI = STI->getRegisterInfo();
2293
2294 // %base cannot be redefined after the load as it will appear before
2295 // TBB/TBH like:
2296 // %base =
2297 // %base =
2298 // tBB %base, %idx
2299 if (registerDefinedBetween(Reg: BaseReg, From: Load->getNextNode(), To: MBB->end(), TRI))
2300 continue;
2301
2302 if (isPositionIndependentOrROPI) {
2303 MachineInstr *Add = Load->getNextNode();
2304 if (Add->getOpcode() != ARM::tADDrr ||
2305 Add->getOperand(i: 2).getReg() != BaseReg ||
2306 Add->getOperand(i: 3).getReg() != Load->getOperand(i: 0).getReg() ||
2307 !Add->getOperand(i: 3).isKill())
2308 continue;
2309 if (Add->getOperand(i: 0).getReg() != MI->getOperand(i: 0).getReg())
2310 continue;
2311 if (registerDefinedBetween(Reg: IdxReg, From: Add->getNextNode(), To: MI, TRI))
2312 // IdxReg gets redefined in the middle of the sequence.
2313 continue;
2314 Add->eraseFromParent();
2315 DeadSize += 2;
2316 } else {
2317 if (Load->getOperand(i: 0).getReg() != MI->getOperand(i: 0).getReg())
2318 continue;
2319 if (registerDefinedBetween(Reg: IdxReg, From: Load->getNextNode(), To: MI, TRI))
2320 // IdxReg gets redefined in the middle of the sequence.
2321 continue;
2322 }
2323
2324 // Now safe to delete the load and lsl. The LEA will be removed later.
2325 CanDeleteLEA = true;
2326 Shift->eraseFromParent();
2327 Load->eraseFromParent();
2328 DeadSize += 4;
2329 }
2330
2331 LLVM_DEBUG(dbgs() << "Shrink JT: " << *MI);
2332 MachineInstr *CPEMI = User.CPEMI;
2333 unsigned Opc = ByteOk ? ARM::t2TBB_JT : ARM::t2TBH_JT;
2334 if (!isThumb2)
2335 Opc = ByteOk ? ARM::tTBB_JT : ARM::tTBH_JT;
2336
2337 MachineBasicBlock::iterator MI_JT = MI;
2338 MachineInstr *NewJTMI =
2339 BuildMI(BB&: *MBB, I: MI_JT, MIMD: MI->getDebugLoc(), MCID: TII->get(Opcode: Opc))
2340 .addReg(RegNo: User.MI->getOperand(i: 0).getReg(),
2341 Flags: getKillRegState(B: BaseRegKill))
2342 .addReg(RegNo: IdxReg, Flags: getKillRegState(B: IdxRegKill))
2343 .addJumpTableIndex(Idx: JTI, TargetFlags: JTOP.getTargetFlags())
2344 .addImm(Val: CPEMI->getOperand(i: 0).getImm());
2345 LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << ": " << *NewJTMI);
2346
2347 unsigned JTOpc = ByteOk ? ARM::JUMPTABLE_TBB : ARM::JUMPTABLE_TBH;
2348 CPEMI->setDesc(TII->get(Opcode: JTOpc));
2349
2350 if (jumpTableFollowsTB(JTMI: MI, CPEMI: User.CPEMI)) {
2351 NewJTMI->getOperand(i: 0).setReg(ARM::PC);
2352 NewJTMI->getOperand(i: 0).setIsKill(false);
2353
2354 if (CanDeleteLEA) {
2355 if (isThumb2)
2356 RemoveDeadAddBetweenLEAAndJT(LEAMI: User.MI, JumpMI: MI, DeadSize);
2357
2358 User.MI->eraseFromParent();
2359 DeadSize += isThumb2 ? 4 : 2;
2360
2361 // The LEA was eliminated, the TBB instruction becomes the only new user
2362 // of the jump table.
2363 User.MI = NewJTMI;
2364 User.MaxDisp = 4;
2365 User.NegOk = false;
2366 User.IsSoImm = false;
2367 User.KnownAlignment = false;
2368 } else {
2369 // The LEA couldn't be eliminated, so we must add another CPUser to
2370 // record the TBB or TBH use.
2371 int CPEntryIdx = JumpTableEntryIndices[JTI];
2372 auto &CPEs = CPEntries[CPEntryIdx];
2373 auto Entry =
2374 find_if(Range&: CPEs, P: [&](CPEntry &E) { return E.CPEMI == User.CPEMI; });
2375 ++Entry->RefCount;
2376 CPUsers.emplace_back(args: CPUser(NewJTMI, User.CPEMI, 4, false, false));
2377 }
2378 }
2379
2380 unsigned NewSize = TII->getInstSizeInBytes(MI: *NewJTMI);
2381 unsigned OrigSize = TII->getInstSizeInBytes(MI: *MI);
2382 MI->eraseFromParent();
2383
2384 int Delta = OrigSize - NewSize + DeadSize;
2385 BBInfo[MBB->getNumber()].Size -= Delta;
2386 BBUtils->adjustBBOffsetsAfter(MBB);
2387
2388 ++NumTBs;
2389 MadeChange = true;
2390 }
2391
2392 return MadeChange;
2393}
2394
2395/// reorderThumb2JumpTables - Adjust the function's block layout to ensure that
2396/// jump tables always branch forwards, since that's what tbb and tbh need.
2397bool ARMConstantIslands::reorderThumb2JumpTables() {
2398 bool MadeChange = false;
2399
2400 MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
2401 if (!MJTI) return false;
2402
2403 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
2404 for (MachineInstr *MI : T2JumpTables) {
2405 const MCInstrDesc &MCID = MI->getDesc();
2406 unsigned NumOps = MCID.getNumOperands();
2407 unsigned JTOpIdx = NumOps - (MI->isPredicable() ? 2 : 1);
2408 MachineOperand JTOP = MI->getOperand(i: JTOpIdx);
2409 unsigned JTI = JTOP.getIndex();
2410 assert(JTI < JT.size());
2411
2412 // We prefer if target blocks for the jump table come after the jump
2413 // instruction so we can use TB[BH]. Loop through the target blocks
2414 // and try to adjust them such that that's true.
2415 int JTNumber = MI->getParent()->getNumber();
2416 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
2417 for (MachineBasicBlock *MBB : JTBBs) {
2418 int DTNumber = MBB->getNumber();
2419
2420 if (DTNumber < JTNumber) {
2421 // The destination precedes the switch. Try to move the block forward
2422 // so we have a positive offset.
2423 MachineBasicBlock *NewBB =
2424 adjustJTTargetBlockForward(JTI, BB: MBB, JTBB: MI->getParent());
2425 if (NewBB)
2426 MJTI->ReplaceMBBInJumpTable(Idx: JTI, Old: MBB, New: NewBB);
2427 MadeChange = true;
2428 }
2429 }
2430 }
2431
2432 return MadeChange;
2433}
2434
2435MachineBasicBlock *ARMConstantIslands::adjustJTTargetBlockForward(
2436 unsigned JTI, MachineBasicBlock *BB, MachineBasicBlock *JTBB) {
2437 // If the destination block is terminated by an unconditional branch,
2438 // try to move it; otherwise, create a new block following the jump
2439 // table that branches back to the actual target. This is a very simple
2440 // heuristic. FIXME: We can definitely improve it.
2441 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
2442 SmallVector<MachineOperand, 4> Cond;
2443 SmallVector<MachineOperand, 4> CondPrior;
2444 MachineFunction::iterator BBi = BB->getIterator();
2445 MachineFunction::iterator OldPrior = std::prev(x: BBi);
2446 MachineFunction::iterator OldNext = std::next(x: BBi);
2447
2448 // If the block terminator isn't analyzable, don't try to move the block
2449 bool B = TII->analyzeBranch(MBB&: *BB, TBB, FBB, Cond);
2450
2451 // If the block ends in an unconditional branch, move it. The prior block
2452 // has to have an analyzable terminator for us to move this one. Be paranoid
2453 // and make sure we're not trying to move the entry block of the function.
2454 if (!B && Cond.empty() && BB != &MF->front() &&
2455 !TII->analyzeBranch(MBB&: *OldPrior, TBB, FBB, Cond&: CondPrior)) {
2456 BB->moveAfter(NewBefore: JTBB);
2457 OldPrior->updateTerminator(PreviousLayoutSuccessor: BB);
2458 BB->updateTerminator(PreviousLayoutSuccessor: OldNext != MF->end() ? &*OldNext : nullptr);
2459 // Update numbering to account for the block being moved.
2460 MF->RenumberBlocks();
2461 ++NumJTMoved;
2462 return nullptr;
2463 }
2464
2465 // Create a new MBB for the code after the jump BB.
2466 MachineBasicBlock *NewBB =
2467 MF->CreateMachineBasicBlock(BB: JTBB->getBasicBlock());
2468 MachineFunction::iterator MBBI = ++JTBB->getIterator();
2469 MF->insert(MBBI, MBB: NewBB);
2470
2471 // Copy live-in information to new block.
2472 for (const MachineBasicBlock::RegisterMaskPair &RegMaskPair : BB->liveins())
2473 NewBB->addLiveIn(RegMaskPair);
2474
2475 // Add an unconditional branch from NewBB to BB.
2476 // There doesn't seem to be meaningful DebugInfo available; this doesn't
2477 // correspond directly to anything in the source.
2478 if (isThumb2)
2479 BuildMI(BB: NewBB, MIMD: DebugLoc(), MCID: TII->get(Opcode: ARM::t2B))
2480 .addMBB(MBB: BB)
2481 .add(MOs: predOps(Pred: ARMCC::AL));
2482 else
2483 BuildMI(BB: NewBB, MIMD: DebugLoc(), MCID: TII->get(Opcode: ARM::tB))
2484 .addMBB(MBB: BB)
2485 .add(MOs: predOps(Pred: ARMCC::AL));
2486
2487 // Update internal data structures to account for the newly inserted MBB.
2488 MF->RenumberBlocks(MBBFrom: NewBB);
2489
2490 // Update the CFG.
2491 NewBB->addSuccessor(Succ: BB);
2492 JTBB->replaceSuccessor(Old: BB, New: NewBB);
2493
2494 ++NumJTInserted;
2495 return NewBB;
2496}
2497
2498/// createARMConstantIslandPass - returns an instance of the constpool
2499/// island pass.
2500FunctionPass *llvm::createARMConstantIslandPass() {
2501 return new ARMConstantIslands();
2502}
2503
2504INITIALIZE_PASS(ARMConstantIslands, "arm-cp-islands", ARM_CP_ISLANDS_OPT_NAME,
2505 false, false)
2506