1//===-- ARMSubtarget.cpp - ARM Subtarget Information ----------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the ARM specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#include "ARM.h"
14
15#include "ARMCallLowering.h"
16#include "ARMFrameLowering.h"
17#include "ARMInstrInfo.h"
18#include "ARMLegalizerInfo.h"
19#include "ARMRegisterBankInfo.h"
20#include "ARMSubtarget.h"
21#include "ARMTargetMachine.h"
22#include "MCTargetDesc/ARMMCTargetDesc.h"
23#include "Thumb1FrameLowering.h"
24#include "Thumb1InstrInfo.h"
25#include "Thumb2InstrInfo.h"
26#include "llvm/ADT/BitVector.h"
27#include "llvm/ADT/StringRef.h"
28#include "llvm/ADT/Twine.h"
29#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
30#include "llvm/CodeGen/MachineFrameInfo.h"
31#include "llvm/CodeGen/MachineFunction.h"
32#include "llvm/IR/Function.h"
33#include "llvm/IR/GlobalValue.h"
34#include "llvm/MC/MCAsmInfo.h"
35#include "llvm/MC/MCTargetOptions.h"
36#include "llvm/Support/CodeGen.h"
37#include "llvm/Support/CommandLine.h"
38#include "llvm/Target/TargetOptions.h"
39#include "llvm/TargetParser/ARMTargetParser.h"
40#include "llvm/TargetParser/Triple.h"
41
42using namespace llvm;
43
44#define DEBUG_TYPE "arm-subtarget"
45
46#define GET_SUBTARGETINFO_TARGET_DESC
47#define GET_SUBTARGETINFO_CTOR
48#include "ARMGenSubtargetInfo.inc"
49
50static cl::opt<bool>
51UseFusedMulOps("arm-use-mulops",
52 cl::init(Val: true), cl::Hidden);
53
54enum ITMode {
55 DefaultIT,
56 RestrictedIT
57};
58
59static cl::opt<ITMode>
60 IT(cl::desc("IT block support"), cl::Hidden, cl::init(Val: DefaultIT),
61 cl::values(clEnumValN(DefaultIT, "arm-default-it",
62 "Generate any type of IT block"),
63 clEnumValN(RestrictedIT, "arm-restrict-it",
64 "Disallow complex IT blocks")));
65
66/// ForceFastISel - Use the fast-isel, even for subtargets where it is not
67/// currently supported (for testing only).
68static cl::opt<bool>
69ForceFastISel("arm-force-fast-isel",
70 cl::init(Val: false), cl::Hidden);
71
72/// initializeSubtargetDependencies - Initializes using a CPU and feature string
73/// so that we can use initializer lists for subtarget initialization.
74ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU,
75 StringRef FS) {
76 initSubtargetFeatures(CPU, FS);
77 return *this;
78}
79
80ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
81 StringRef FS) {
82 ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS);
83 if (STI.isThumb1Only())
84 return (ARMFrameLowering *)new Thumb1FrameLowering(STI);
85
86 return new ARMFrameLowering(STI);
87}
88
89ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
90 const std::string &FS,
91 const ARMBaseTargetMachine &TM, bool IsLittle,
92 FloatABI::ABIType FloatABI, ARM::ARMABI ABI,
93 bool MinSize, DenormalMode DM)
94 : ARMGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
95 UseMulOps(UseFusedMulOps), CPUString(CPU), OptMinSize(MinSize),
96 IsLittle(IsLittle), DM(DM), TargetTriple(TT), Options(TM.Options), TM(TM),
97 FloatABIType(FloatABI), ABI(ABI),
98 FrameLowering(initializeFrameLowering(CPU, FS)),
99 // At this point initializeSubtargetDependencies has been called so
100 // we can query directly.
101 InstrInfo(isThumb1Only() ? (ARMBaseInstrInfo *)new Thumb1InstrInfo(*this)
102 : !isThumb() ? (ARMBaseInstrInfo *)new ARMInstrInfo(*this)
103 : (ARMBaseInstrInfo *)new Thumb2InstrInfo(*this)),
104 TLInfo(TM, *this) {
105
106 CallLoweringInfo.reset(p: new ARMCallLowering(*getTargetLowering()));
107 Legalizer.reset(p: new ARMLegalizerInfo(*this));
108
109 auto *RBI = new ARMRegisterBankInfo(*getRegisterInfo());
110
111 // FIXME: At this point, we can't rely on Subtarget having RBI.
112 // It's awkward to mix passing RBI and the Subtarget; should we pass
113 // TII/TRI as well?
114 InstSelector.reset(p: createARMInstructionSelector(TM, STI: *this, RBI: *RBI));
115
116 RegBankInfo.reset(p: RBI);
117}
118
119const CallLowering *ARMSubtarget::getCallLowering() const {
120 return CallLoweringInfo.get();
121}
122
123InstructionSelector *ARMSubtarget::getInstructionSelector() const {
124 return InstSelector.get();
125}
126
127const LegalizerInfo *ARMSubtarget::getLegalizerInfo() const {
128 return Legalizer.get();
129}
130
131const RegisterBankInfo *ARMSubtarget::getRegBankInfo() const {
132 return RegBankInfo.get();
133}
134
135void ARMSubtarget::initLibcallLoweringInfo(LibcallLoweringInfo &Info) const {
136 const Triple &TT = getTargetTriple();
137 if (TT.isOSBinFormatMachO()) {
138 // Uses VFP for Thumb libfuncs if available.
139 if (isThumb() && hasVFP2Base() && hasARMOps() && !useSoftFloat()) {
140 // clang-format off
141 static const struct {
142 const RTLIB::Libcall Op;
143 const RTLIB::LibcallImpl Impl;
144 } LibraryCalls[] = {
145 // Single-precision floating-point arithmetic.
146 { .Op: RTLIB::ADD_F32, .Impl: RTLIB::impl___addsf3vfp },
147 { .Op: RTLIB::SUB_F32, .Impl: RTLIB::impl___subsf3vfp },
148 { .Op: RTLIB::MUL_F32, .Impl: RTLIB::impl___mulsf3vfp },
149 { .Op: RTLIB::DIV_F32, .Impl: RTLIB::impl___divsf3vfp },
150
151 // Double-precision floating-point arithmetic.
152 { .Op: RTLIB::ADD_F64, .Impl: RTLIB::impl___adddf3vfp },
153 { .Op: RTLIB::SUB_F64, .Impl: RTLIB::impl___subdf3vfp },
154 { .Op: RTLIB::MUL_F64, .Impl: RTLIB::impl___muldf3vfp },
155 { .Op: RTLIB::DIV_F64, .Impl: RTLIB::impl___divdf3vfp },
156
157 // Single-precision comparisons.
158 { .Op: RTLIB::OEQ_F32, .Impl: RTLIB::impl___eqsf2vfp },
159 { .Op: RTLIB::UNE_F32, .Impl: RTLIB::impl___nesf2vfp },
160 { .Op: RTLIB::OLT_F32, .Impl: RTLIB::impl___ltsf2vfp },
161 { .Op: RTLIB::OLE_F32, .Impl: RTLIB::impl___lesf2vfp },
162 { .Op: RTLIB::OGE_F32, .Impl: RTLIB::impl___gesf2vfp },
163 { .Op: RTLIB::OGT_F32, .Impl: RTLIB::impl___gtsf2vfp },
164 { .Op: RTLIB::UO_F32, .Impl: RTLIB::impl___unordsf2vfp },
165
166 // Double-precision comparisons.
167 { .Op: RTLIB::OEQ_F64, .Impl: RTLIB::impl___eqdf2vfp },
168 { .Op: RTLIB::UNE_F64, .Impl: RTLIB::impl___nedf2vfp },
169 { .Op: RTLIB::OLT_F64, .Impl: RTLIB::impl___ltdf2vfp },
170 { .Op: RTLIB::OLE_F64, .Impl: RTLIB::impl___ledf2vfp },
171 { .Op: RTLIB::OGE_F64, .Impl: RTLIB::impl___gedf2vfp },
172 { .Op: RTLIB::OGT_F64, .Impl: RTLIB::impl___gtdf2vfp },
173 { .Op: RTLIB::UO_F64, .Impl: RTLIB::impl___unorddf2vfp },
174
175 // Floating-point to integer conversions.
176 // i64 conversions are done via library routines even when generating VFP
177 // instructions, so use the same ones.
178 { .Op: RTLIB::FPTOSINT_F64_I32, .Impl: RTLIB::impl___fixdfsivfp },
179 { .Op: RTLIB::FPTOUINT_F64_I32, .Impl: RTLIB::impl___fixunsdfsivfp },
180 { .Op: RTLIB::FPTOSINT_F32_I32, .Impl: RTLIB::impl___fixsfsivfp },
181 { .Op: RTLIB::FPTOUINT_F32_I32, .Impl: RTLIB::impl___fixunssfsivfp },
182
183 // Conversions between floating types.
184 { .Op: RTLIB::FPROUND_F64_F32, .Impl: RTLIB::impl___truncdfsf2vfp },
185 { .Op: RTLIB::FPEXT_F32_F64, .Impl: RTLIB::impl___extendsfdf2vfp },
186
187 // Integer to floating-point conversions.
188 // i64 conversions are done via library routines even when generating VFP
189 // instructions, so use the same ones.
190 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
191 // e.g., __floatunsidf vs. __floatunssidfvfp.
192 { .Op: RTLIB::SINTTOFP_I32_F64, .Impl: RTLIB::impl___floatsidfvfp },
193 { .Op: RTLIB::UINTTOFP_I32_F64, .Impl: RTLIB::impl___floatunssidfvfp },
194 { .Op: RTLIB::SINTTOFP_I32_F32, .Impl: RTLIB::impl___floatsisfvfp },
195 { .Op: RTLIB::UINTTOFP_I32_F32, .Impl: RTLIB::impl___floatunssisfvfp },
196 };
197 // clang-format on
198
199 for (const auto &LC : LibraryCalls)
200 Info.setLibcallImpl(Call: LC.Op, Impl: LC.Impl);
201 }
202 }
203
204 static const struct {
205 const RTLIB::Libcall Op;
206 const RTLIB::LibcallImpl Impl;
207 } AEABISelected[] = {
208 // Double-precision arithmetic.
209 {.Op: RTLIB::ADD_F64, .Impl: RTLIB::impl___aeabi_dadd},
210 {.Op: RTLIB::DIV_F64, .Impl: RTLIB::impl___aeabi_ddiv},
211 {.Op: RTLIB::MUL_F64, .Impl: RTLIB::impl___aeabi_dmul},
212 {.Op: RTLIB::SUB_F64, .Impl: RTLIB::impl___aeabi_dsub},
213 // Double-precision comparisons.
214 {.Op: RTLIB::OEQ_F64, .Impl: RTLIB::impl___aeabi_dcmpeq},
215 {.Op: RTLIB::OLT_F64, .Impl: RTLIB::impl___aeabi_dcmplt},
216 {.Op: RTLIB::OLE_F64, .Impl: RTLIB::impl___aeabi_dcmple},
217 {.Op: RTLIB::OGE_F64, .Impl: RTLIB::impl___aeabi_dcmpge},
218 {.Op: RTLIB::OGT_F64, .Impl: RTLIB::impl___aeabi_dcmpgt},
219 {.Op: RTLIB::UO_F64, .Impl: RTLIB::impl___aeabi_dcmpun},
220 // Single-precision arithmetic.
221 {.Op: RTLIB::ADD_F32, .Impl: RTLIB::impl___aeabi_fadd},
222 {.Op: RTLIB::DIV_F32, .Impl: RTLIB::impl___aeabi_fdiv},
223 {.Op: RTLIB::MUL_F32, .Impl: RTLIB::impl___aeabi_fmul},
224 {.Op: RTLIB::SUB_F32, .Impl: RTLIB::impl___aeabi_fsub},
225 // Single-precision comparisons.
226 {.Op: RTLIB::OEQ_F32, .Impl: RTLIB::impl___aeabi_fcmpeq},
227 {.Op: RTLIB::OLT_F32, .Impl: RTLIB::impl___aeabi_fcmplt},
228 {.Op: RTLIB::OLE_F32, .Impl: RTLIB::impl___aeabi_fcmple},
229 {.Op: RTLIB::OGE_F32, .Impl: RTLIB::impl___aeabi_fcmpge},
230 {.Op: RTLIB::OGT_F32, .Impl: RTLIB::impl___aeabi_fcmpgt},
231 {.Op: RTLIB::UO_F32, .Impl: RTLIB::impl___aeabi_fcmpun},
232 // Floating-point to integer conversions.
233 {.Op: RTLIB::FPTOSINT_F64_I32, .Impl: RTLIB::impl___aeabi_d2iz},
234 {.Op: RTLIB::FPTOUINT_F64_I32, .Impl: RTLIB::impl___aeabi_d2uiz},
235 {.Op: RTLIB::FPTOSINT_F64_I64, .Impl: RTLIB::impl___aeabi_d2lz},
236 {.Op: RTLIB::FPTOUINT_F64_I64, .Impl: RTLIB::impl___aeabi_d2ulz},
237 {.Op: RTLIB::FPTOSINT_F32_I32, .Impl: RTLIB::impl___aeabi_f2iz},
238 {.Op: RTLIB::FPTOUINT_F32_I32, .Impl: RTLIB::impl___aeabi_f2uiz},
239 {.Op: RTLIB::FPTOSINT_F32_I64, .Impl: RTLIB::impl___aeabi_f2lz},
240 {.Op: RTLIB::FPTOUINT_F32_I64, .Impl: RTLIB::impl___aeabi_f2ulz},
241 // Integer to floating-point conversions.
242 {.Op: RTLIB::SINTTOFP_I32_F64, .Impl: RTLIB::impl___aeabi_i2d},
243 {.Op: RTLIB::UINTTOFP_I32_F64, .Impl: RTLIB::impl___aeabi_ui2d},
244 {.Op: RTLIB::SINTTOFP_I64_F64, .Impl: RTLIB::impl___aeabi_l2d},
245 {.Op: RTLIB::UINTTOFP_I64_F64, .Impl: RTLIB::impl___aeabi_ul2d},
246 {.Op: RTLIB::SINTTOFP_I32_F32, .Impl: RTLIB::impl___aeabi_i2f},
247 {.Op: RTLIB::UINTTOFP_I32_F32, .Impl: RTLIB::impl___aeabi_ui2f},
248 {.Op: RTLIB::SINTTOFP_I64_F32, .Impl: RTLIB::impl___aeabi_l2f},
249 {.Op: RTLIB::UINTTOFP_I64_F32, .Impl: RTLIB::impl___aeabi_ul2f},
250 // Long long helpers.
251 {.Op: RTLIB::MUL_I64, .Impl: RTLIB::impl___aeabi_lmul},
252 {.Op: RTLIB::SHL_I64, .Impl: RTLIB::impl___aeabi_llsl},
253 {.Op: RTLIB::SRL_I64, .Impl: RTLIB::impl___aeabi_llsr},
254 {.Op: RTLIB::SRA_I64, .Impl: RTLIB::impl___aeabi_lasr},
255 // Integer division.
256 {.Op: RTLIB::SDIV_I32, .Impl: RTLIB::impl___aeabi_idiv},
257 {.Op: RTLIB::UDIV_I32, .Impl: RTLIB::impl___aeabi_uidiv},
258 };
259
260 const RTLIB::RuntimeLibcallsInfo &RTLCI = Info.getRuntimeLibcallsInfo();
261 for (const auto &LC : AEABISelected) {
262 if (RTLCI.isAvailable(Impl: LC.Impl))
263 Info.setLibcallImpl(Call: LC.Op, Impl: LC.Impl);
264 }
265
266 // AEABI provides an ordered-equal compare (__aeabi_{f,d}cmpeq) but no
267 // not-equal compare. Clear the not-equal libcalls so UNE will lower as !OEQ
268 // using the AEABI compare, rather than emitting the generic not-equal helper
269 // which would otherwise be preferred.
270 if (RTLCI.isAvailable(Impl: RTLIB::impl___aeabi_fcmpeq)) {
271 Info.setLibcallImpl(Call: RTLIB::UNE_F32, Impl: RTLIB::Unsupported);
272 Info.setLibcallImpl(Call: RTLIB::FCMP3_PRED_UNE_F32, Impl: RTLIB::Unsupported);
273 }
274
275 if (RTLCI.isAvailable(Impl: RTLIB::impl___aeabi_dcmpeq)) {
276 Info.setLibcallImpl(Call: RTLIB::UNE_F64, Impl: RTLIB::Unsupported);
277 Info.setLibcallImpl(Call: RTLIB::FCMP3_PRED_UNE_F64, Impl: RTLIB::Unsupported);
278 }
279}
280
281bool ARMSubtarget::isXRaySupported() const {
282 // We don't currently support Thumb, but Windows requires Thumb.
283 return hasV6Ops() && hasARMOps() && !isTargetWindows();
284}
285
286void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
287 if (CPUString.empty()) {
288 CPUString = "generic";
289
290 if (isTargetDarwin()) {
291 StringRef ArchName = TargetTriple.getArchName();
292 ARM::ArchKind AK = ARM::parseArch(Arch: ArchName);
293 if (AK == ARM::ArchKind::ARMV7S)
294 // Default to the Swift CPU when targeting armv7s/thumbv7s.
295 CPUString = "swift";
296 else if (AK == ARM::ArchKind::ARMV7K)
297 // Default to the Cortex-a7 CPU when targeting armv7k/thumbv7k.
298 // ARMv7k does not use SjLj exception handling.
299 CPUString = "cortex-a7";
300 }
301 }
302
303 // Insert the architecture feature derived from the target triple into the
304 // feature string. This is important for setting features that are implied
305 // based on the architecture version.
306 std::string ArchFS = ARM_MC::ParseARMTriple(TT: TargetTriple, CPU: CPUString);
307 if (!FS.empty()) {
308 if (!ArchFS.empty())
309 ArchFS = (Twine(ArchFS) + "," + FS).str();
310 else
311 ArchFS = std::string(FS);
312 }
313 ParseSubtargetFeatures(CPU: CPUString, /*TuneCPU*/ CPUString, FS: ArchFS);
314
315 // FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
316 // Assert this for now to make the change obvious.
317 assert(hasV6T2Ops() || !hasThumb2());
318
319 if (genExecuteOnly()) {
320 // Execute only support for >= v8-M Baseline requires movt support
321 if (hasV8MBaselineOps())
322 NoMovt = false;
323 if (!hasV6MOps())
324 report_fatal_error(reason: "Cannot generate execute-only code for this target");
325 }
326
327 // Keep a pointer to static instruction cost data for the specified CPU.
328 SchedModel = getSchedModelForCPU(CPU: CPUString);
329
330 // Initialize scheduling itinerary for the specified CPU.
331 InstrItins = getInstrItineraryForCPU(CPU: CPUString);
332
333 // FIXME: this is invalid for WindowsCE
334 if (isTargetWindows())
335 NoARM = true;
336
337 if (isAAPCS_ABI())
338 stackAlignment = Align(8);
339 if (isAAPCS16_ABI())
340 stackAlignment = Align(16);
341
342 // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
343 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
344 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
345 // support in the assembler and linker to be used. This would need to be
346 // fixed to fully support tail calls in Thumb1.
347 //
348 // For ARMv8-M, we /do/ implement tail calls. Doing this is tricky for v8-M
349 // baseline, since the LDM/POP instruction on Thumb doesn't take LR. This
350 // means if we need to reload LR, it takes extra instructions, which outweighs
351 // the value of the tail call; but here we don't know yet whether LR is going
352 // to be used. We take the optimistic approach of generating the tail call and
353 // perhaps taking a hit if we need to restore the LR.
354
355 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
356 // but we need to make sure there are enough registers; the only valid
357 // registers are the 4 used for parameters. We don't currently do this
358 // case.
359
360 SupportsTailCall = !isThumb1Only() || hasV8MBaselineOps();
361
362 switch (IT) {
363 case DefaultIT:
364 RestrictIT = false;
365 break;
366 case RestrictedIT:
367 RestrictIT = true;
368 break;
369 }
370
371 // NEON f32 ops are non-IEEE 754 compliant. Darwin is ok with it by default.
372 const FeatureBitset &Bits = getFeatureBits();
373 if ((Bits[ARM::ProcA5] || Bits[ARM::ProcA8]) && // Where this matters
374 (isTargetDarwin() || DM == DenormalMode::getPreserveSign()))
375 HasNEONForFP = true;
376
377 const ARM::ArchKind Arch = ARM::parseArch(Arch: TargetTriple.getArchName());
378 if (isRWPI() ||
379 (isTargetIOS() &&
380 (Arch == ARM::ArchKind::ARMV6K || Arch == ARM::ArchKind::ARMV6) &&
381 TargetTriple.isOSVersionLT(Major: 3, Minor: 0)))
382 ReserveR9 = true;
383
384 // If MVEVectorCostFactor is still 0 (has not been set to anything else), default it to 2
385 if (MVEVectorCostFactor == 0)
386 MVEVectorCostFactor = 2;
387
388 // FIXME: Teach TableGen to deal with these instead of doing it manually here.
389 switch (ARMProcFamily) {
390 case Others:
391 case CortexA5:
392 break;
393 case CortexA7:
394 LdStMultipleTiming = DoubleIssue;
395 break;
396 case CortexA8:
397 LdStMultipleTiming = DoubleIssue;
398 break;
399 case CortexA9:
400 LdStMultipleTiming = DoubleIssueCheckUnalignedAccess;
401 PreISelOperandLatencyAdjustment = 1;
402 break;
403 case CortexA12:
404 break;
405 case CortexA15:
406 MaxInterleaveFactor = 2;
407 PreISelOperandLatencyAdjustment = 1;
408 PartialUpdateClearance = 12;
409 break;
410 case CortexA17:
411 case CortexA32:
412 case CortexA35:
413 case CortexA53:
414 case CortexA55:
415 case CortexA57:
416 case CortexA72:
417 case CortexA73:
418 case CortexA75:
419 case CortexA76:
420 case CortexA77:
421 case CortexA78:
422 case CortexA78AE:
423 case CortexA78C:
424 case CortexA510:
425 case CortexA710:
426 case CortexR4:
427 case CortexR5:
428 case CortexR7:
429 case CortexM3:
430 case CortexM55:
431 case CortexM7:
432 case CortexM85:
433 case CortexR52:
434 case CortexR52plus:
435 case CortexX1:
436 case CortexX1C:
437 break;
438 case Exynos:
439 LdStMultipleTiming = SingleIssuePlusExtras;
440 MaxInterleaveFactor = 4;
441 if (!isThumb())
442 PreferBranchLogAlignment = 3;
443 break;
444 case Kryo:
445 break;
446 case Krait:
447 PreISelOperandLatencyAdjustment = 1;
448 break;
449 case NeoverseV1:
450 break;
451 case Swift:
452 MaxInterleaveFactor = 2;
453 LdStMultipleTiming = SingleIssuePlusExtras;
454 PreISelOperandLatencyAdjustment = 1;
455 PartialUpdateClearance = 12;
456 break;
457 }
458}
459
460bool ARMSubtarget::isROPI() const {
461 // FIXME: This should ideally come from a function attribute, to work
462 // correctly with LTO.
463 return TM.getRelocationModel() == Reloc::ROPI ||
464 TM.getRelocationModel() == Reloc::ROPI_RWPI;
465}
466
467bool ARMSubtarget::isRWPI() const {
468 // FIXME: This should ideally come from a function attribute, to work
469 // correctly with LTO.
470 return TM.getRelocationModel() == Reloc::RWPI ||
471 TM.getRelocationModel() == Reloc::ROPI_RWPI;
472}
473
474bool ARMSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const {
475 return TM.isGVIndirectSymbol(GV);
476}
477
478bool ARMSubtarget::isGVInGOT(const GlobalValue *GV) const {
479 return isTargetELF() && TM.isPositionIndependent() && !GV->isDSOLocal();
480}
481
482bool ARMSubtarget::enableMachineScheduler() const {
483 // The MachineScheduler can increase register usage, so we use more high
484 // registers and end up with more T2 instructions that cannot be converted to
485 // T1 instructions. At least until we do better at converting to thumb1
486 // instructions, on cortex-m at Oz where we are size-paranoid, don't use the
487 // Machine scheduler, relying on the DAG register pressure scheduler instead.
488 if (isMClass() && hasMinSize())
489 return false;
490 // Enable the MachineScheduler before register allocation for subtargets
491 // with the use-misched feature.
492 return useMachineScheduler();
493}
494
495bool ARMSubtarget::enableSubRegLiveness() const {
496 // Enable SubRegLiveness for MVE to better optimize s subregs for mqpr regs
497 // and q subregs for qqqqpr regs.
498 return hasMVEIntegerOps();
499}
500
501bool ARMSubtarget::enableMachinePipeliner() const {
502 // Enable the MachinePipeliner before register allocation for subtargets
503 // with the use-mipipeliner feature.
504 return getSchedModel().hasInstrSchedModel() && useMachinePipeliner();
505}
506
507bool ARMSubtarget::useDFAforSMS() const { return false; }
508
509// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
510bool ARMSubtarget::enablePostRAScheduler() const {
511 if (enableMachineScheduler())
512 return false;
513 if (disablePostRAScheduler())
514 return false;
515 // Thumb1 cores will generally not benefit from post-ra scheduling
516 return !isThumb1Only();
517}
518
519bool ARMSubtarget::enablePostRAMachineScheduler() const {
520 if (!enableMachineScheduler())
521 return false;
522 if (disablePostRAScheduler())
523 return false;
524 return !isThumb1Only();
525}
526
527bool ARMSubtarget::useStride4VFPs() const {
528 // For general targets, the prologue can grow when VFPs are allocated with
529 // stride 4 (more vpush instructions). But WatchOS uses a compact unwind
530 // format which it's more important to get right.
531 return isTargetWatchABI() ||
532 (useWideStrideVFP() && !OptMinSize);
533}
534
535bool ARMSubtarget::useMovt() const {
536 // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
537 // immediates as it is inherently position independent, and may be out of
538 // range otherwise.
539 return !NoMovt && hasV8MBaselineOps() &&
540 (isTargetWindows() || !OptMinSize || genExecuteOnly());
541}
542
543bool ARMSubtarget::useFastISel() const {
544 // Enable fast-isel for any target, for testing only.
545 if (ForceFastISel)
546 return true;
547
548 // Limit fast-isel to the targets that are or have been tested.
549 if (!hasV6Ops())
550 return false;
551
552 // Thumb2 support on iOS; ARM support on iOS and Linux.
553 return TM.Options.EnableFastISel && ((isTargetMachO() && !isThumb1Only()) ||
554 (isTargetLinux() && !isThumb()));
555}
556
557unsigned ARMSubtarget::getGPRAllocationOrder(const MachineFunction &MF) const {
558 // The GPR register class has multiple possible allocation orders, with
559 // tradeoffs preferred by different sub-architectures and optimisation goals.
560 // The allocation orders are:
561 // 0: (the default tablegen order, not used)
562 // 1: r14, r0-r13
563 // 2: r0-r7
564 // 3: r0-r7, r12, lr, r8-r11
565 // Note that the register allocator will change this order so that
566 // callee-saved registers are used later, as they require extra work in the
567 // prologue/epilogue (though we sometimes override that).
568
569 // For thumb1-only targets, only the low registers are allocatable.
570 if (isThumb1Only())
571 return 2;
572
573 // Allocate low registers first, so we can select more 16-bit instructions.
574 // We also (in getCSRAllocationOrderMask) override the default behaviour
575 // with regards to callee-saved registers, because pushing extra registers is
576 // much cheaper (in terms of code size) than using high registers. After
577 // that, we allocate r12 (doesn't need to be saved), lr (saving it means we
578 // can return with the pop, don't need an extra "bx lr") and then the rest of
579 // the high registers.
580 if (isThumb2() && MF.getFunction().hasMinSize())
581 return 3;
582
583 // Otherwise, allocate in the default order, using LR first because saving it
584 // allows a shorter epilogue sequence.
585 return 1;
586}
587
588void ARMSubtarget::getCSRAllocationOrderMask(const MachineFunction &MF,
589 BitVector &Mask) const {
590 // To minimize code size in Thumb2, we prefer the usage of low regs (lower
591 // cost per use) so we can use narrow encoding. By default, caller-saved
592 // registers (e.g. lr, r12) are always allocated first, regardless of
593 // their cost per use. When optForMinSize, we prefer the low regs even if
594 // they are CSR because usually push/pop can be folded into existing ones.
595 if (!isThumb2() || !MF.getFunction().hasMinSize())
596 return;
597
598 Mask.resize(N: getRegisterInfo()->getNumRegs());
599 for (MCPhysReg Reg : ARM::GPRRegClass)
600 Mask.set(Reg);
601}
602
603ARMSubtarget::PushPopSplitVariation
604ARMSubtarget::getPushPopSplitVariation(const MachineFunction &MF) const {
605 const Function &F = MF.getFunction();
606 const MachineFrameInfo &MFI = MF.getFrameInfo();
607
608 // Thumb1 always splits the pushes at R7, because the Thumb1 push instruction
609 // cannot use high registers except for lr.
610 if (isThumb1Only())
611 return SplitR7;
612
613 // If R7 is the frame pointer, we must split at R7 to ensure that the
614 // previous frame pointer (R7) and return address (LR) are adjacent on the
615 // stack, to form a valid frame record.
616 if (getFramePointerReg() == ARM::R7 &&
617 MF.getTarget().Options.FramePointerIsReserved(MF))
618 return SplitR7;
619
620 // Returns SplitR11WindowsSEH when the stack pointer needs to be
621 // restored from the frame pointer r11 + an offset and Windows CFI is enabled.
622 // This stack unwinding cannot be expressed with SEH unwind opcodes when done
623 // with a single push, making it necessary to split the push into r4-r10, and
624 // another containing r11+lr.
625 if (MF.getTarget().getMCAsmInfo().usesWindowsCFI() &&
626 F.needsUnwindTableEntry() &&
627 (MFI.hasVarSizedObjects() || getRegisterInfo()->hasStackRealignment(MF)))
628 return SplitR11WindowsSEH;
629
630 // Returns SplitR11AAPCSSignRA when the frame pointer is R11, requiring R11
631 // and LR to be adjacent on the stack, and branch signing is enabled,
632 // requiring R12 to be on the stack.
633 if (MF.getInfo<ARMFunctionInfo>()->shouldSignReturnAddress() &&
634 getFramePointerReg() == ARM::R11 &&
635 MF.getTarget().Options.FramePointerIsReserved(MF))
636 return SplitR11AAPCSSignRA;
637 return NoSplit;
638}
639