1//===-- HexagonISelDAGToDAG.h -----------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8// Hexagon specific code to select Hexagon machine instructions for
9// SelectionDAG operations.
10//===----------------------------------------------------------------------===//
11
12#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H
13#define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H
14
15#include "HexagonSubtarget.h"
16#include "HexagonTargetMachine.h"
17#include "llvm/CodeGen/SelectionDAG.h"
18#include "llvm/CodeGen/SelectionDAGISel.h"
19#include "llvm/Support/CodeGen.h"
20
21#include <vector>
22
23namespace llvm {
24class MachineFunction;
25class HexagonInstrInfo;
26class HexagonRegisterInfo;
27
28class HexagonDAGToDAGISel : public SelectionDAGISel {
29 const HexagonSubtarget *HST;
30 const HexagonInstrInfo *HII;
31 const HexagonRegisterInfo *HRI;
32
33public:
34 HexagonDAGToDAGISel() = delete;
35
36 explicit HexagonDAGToDAGISel(HexagonTargetMachine &tm,
37 CodeGenOptLevel OptLevel)
38 : SelectionDAGISel(tm, OptLevel), HST(nullptr), HII(nullptr),
39 HRI(nullptr) {}
40
41 bool runOnMachineFunction(MachineFunction &MF) override {
42 // Reset the subtarget each time through.
43 HST = &MF.getSubtarget<HexagonSubtarget>();
44 HII = HST->getInstrInfo();
45 HRI = HST->getRegisterInfo();
46 SelectionDAGISel::runOnMachineFunction(mf&: MF);
47 return true;
48 }
49
50 bool ComplexPatternFuncMutatesDAG() const override {
51 return true;
52 }
53 void PreprocessISelDAG() override;
54 void emitFunctionEntryCode() override;
55
56 void Select(SDNode *N) override;
57
58 // Complex Pattern Selectors.
59 inline bool SelectAddrGA(SDValue &N, SDValue &R);
60 inline bool SelectAddrGP(SDValue &N, SDValue &R);
61 inline bool SelectAnyImm(SDValue &N, SDValue &R);
62 inline bool SelectAnyInt(SDValue &N, SDValue &R);
63 bool SelectAnyImmediate(SDValue &N, SDValue &R, Align Alignment);
64 bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP, Align Alignment);
65 bool SelectAddrFI(SDValue &N, SDValue &R);
66 bool DetectUseSxtw(SDValue &N, SDValue &R);
67
68 inline bool SelectAnyImm0(SDValue &N, SDValue &R);
69 inline bool SelectAnyImm1(SDValue &N, SDValue &R);
70 inline bool SelectAnyImm2(SDValue &N, SDValue &R);
71 inline bool SelectAnyImm3(SDValue &N, SDValue &R);
72
73 // Generate a machine instruction node corresponding to the circ/brev
74 // load intrinsic.
75 MachineSDNode *LoadInstrForLoadIntrinsic(SDNode *IntN);
76 // Given the circ/brev load intrinsic and the already generated machine
77 // instruction, generate the appropriate store (that is a part of the
78 // intrinsic's functionality).
79 SDNode *StoreInstrForLoadIntrinsic(MachineSDNode *LoadN, SDNode *IntN);
80
81 void SelectFrameIndex(SDNode *N);
82 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
83 /// inline asm expressions.
84 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
85 InlineAsm::ConstraintCode ConstraintID,
86 std::vector<SDValue> &OutOps) override;
87 bool tryLoadOfLoadIntrinsic(LoadSDNode *N);
88 bool SelectBrevLdIntrinsic(SDNode *IntN);
89 bool SelectNewCircIntrinsic(SDNode *IntN);
90 void SelectLoad(SDNode *N);
91 void SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl);
92 void SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl);
93 void SelectStore(SDNode *N);
94 void SelectSHL(SDNode *N);
95 void SelectIntrinsicWChain(SDNode *N);
96 void SelectIntrinsicWOChain(SDNode *N);
97 void SelectExtractSubvector(SDNode *N);
98 void SelectConstant(SDNode *N);
99 void SelectConstantFP(SDNode *N);
100 void SelectV65Gather(SDNode *N);
101 void SelectV65GatherPred(SDNode *N);
102 void SelectHVXDualOutput(SDNode *N);
103 void SelectAddSubCarry(SDNode *N);
104 void SelectVAlign(SDNode *N);
105 void SelectVAlignAddr(SDNode *N);
106 void SelectTypecast(SDNode *N);
107 void SelectP2D(SDNode *N);
108 void SelectD2P(SDNode *N);
109 void SelectQ2V(SDNode *N);
110 void SelectV2Q(SDNode *N);
111 void SelectFDiv(SDNode *N);
112 void FDiv(SDNode *N);
113 void FastFDiv(SDNode *N);
114
115 bool isIEEEHVXIntrinsic(unsigned);
116 void translateIEEEIntrinsicToQFloat(SDNode *N, unsigned &Opcode);
117
118// Include the declarations autogenerated from the selection patterns.
119#define GET_DAGISEL_DECL
120#include "HexagonGenDAGISel.inc"
121
122private:
123 // This is really only to get access to ReplaceNode (which is a protected
124 // member). Any other members used by HvxSelector can be moved around to
125 // make them accessible).
126 friend struct HvxSelector;
127
128 SDValue selectUndef(const SDLoc &dl, MVT ResTy) {
129 SDNode *U = CurDAG->getMachineNode(Opcode: TargetOpcode::IMPLICIT_DEF, dl, VT: ResTy);
130 return SDValue(U, 0);
131 }
132
133 bool keepsLowBits(const SDValue &Val, unsigned NumBits, SDValue &Src);
134 bool isAlignedMemNode(const MemSDNode *N) const;
135 bool isSmallStackStore(const StoreSDNode *N) const;
136 bool isPositiveHalfWord(const SDNode *N) const;
137 bool hasOneUse(const SDNode *N) const;
138
139 // DAG preprocessing functions.
140 void PreprocessHvxISelDAG();
141 void ppSimplifyOrSelect0(std::vector<SDNode*> &&Nodes);
142 void ppAddrReorderAddShl(std::vector<SDNode*> &&Nodes);
143 void ppAddrRewriteAndSrl(std::vector<SDNode*> &&Nodes);
144 void ppHoistZextI1(std::vector<SDNode*> &&Nodes);
145 void ppHvxShuffleOfShuffle(std::vector<SDNode*> &&Nodes);
146
147 void SelectHvxExtractSubvector(SDNode *N);
148 void SelectHvxShuffle(SDNode *N);
149 void SelectHvxRor(SDNode *N);
150 void SelectHvxVAlign(SDNode *N);
151
152 SmallDenseMap<SDNode *,int> RootWeights;
153 SmallDenseMap<SDNode *,int> RootHeights;
154 SmallDenseMap<const Value *,int> GAUsesInFunction;
155 int getWeight(SDNode *N);
156 int getHeight(SDNode *N);
157 SDValue getMultiplierForSHL(SDNode *N);
158 SDValue factorOutPowerOf2(SDValue V, unsigned Power);
159 unsigned getUsesInFunction(const Value *V);
160 SDValue balanceSubTree(SDNode *N, bool Factorize = false);
161 void rebalanceAddressTrees();
162}; // end HexagonDAGToDAGISel
163
164class HexagonDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
165public:
166 static char ID;
167 explicit HexagonDAGToDAGISelLegacy(HexagonTargetMachine &tm,
168 CodeGenOptLevel OptLevel);
169};
170}
171
172#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H
173