1//===-- MipsSERegisterInfo.cpp - MIPS32/64 Register Information -== -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the MIPS32/64 implementation of the TargetRegisterInfo
10// class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MipsSERegisterInfo.h"
15#include "Mips.h"
16#include "MipsMachineFunction.h"
17#include "MipsSEInstrInfo.h"
18#include "MipsSubtarget.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/TargetFrameLowering.h"
24#include "llvm/CodeGen/TargetInstrInfo.h"
25#include "llvm/IR/Function.h"
26#include "llvm/IR/Type.h"
27#include "llvm/Support/Debug.h"
28#include "llvm/Support/raw_ostream.h"
29#include "llvm/Target/TargetMachine.h"
30#include "llvm/Target/TargetOptions.h"
31
32using namespace llvm;
33
34#define DEBUG_TYPE "mips-reg-info"
35
36MipsSERegisterInfo::MipsSERegisterInfo(const MipsSubtarget &STI)
37 : MipsRegisterInfo(STI) {}
38
39bool MipsSERegisterInfo::
40requiresRegisterScavenging(const MachineFunction &MF) const {
41 return true;
42}
43
44bool MipsSERegisterInfo::
45requiresFrameIndexScavenging(const MachineFunction &MF) const {
46 return true;
47}
48
49const TargetRegisterClass *
50MipsSERegisterInfo::intRegClass(unsigned Size) const {
51 if (Size == 4)
52 return &Mips::GPR32RegClass;
53
54 assert(Size == 8);
55 return &Mips::GPR64RegClass;
56}
57
58/// Get the size of the offset supported by the given load/store/inline asm.
59/// The result includes the effects of any scale factors applied to the
60/// instruction immediate.
61static inline unsigned
62getLoadStoreOffsetSizeInBits(const MipsSubtarget &Subtarget,
63 const unsigned Opcode, const MachineOperand &MO) {
64 switch (Opcode) {
65 case Mips::LD_B:
66 case Mips::ST_B:
67 return 10;
68 case Mips::LD_H:
69 case Mips::ST_H:
70 return 10 + 1 /* scale factor */;
71 case Mips::LD_W:
72 case Mips::ST_W:
73 return 10 + 2 /* scale factor */;
74 case Mips::LD_D:
75 case Mips::ST_D:
76 return 10 + 3 /* scale factor */;
77 case Mips::LL:
78 case Mips::LL64:
79 case Mips::LLD:
80 case Mips::LLE:
81 case Mips::SC:
82 case Mips::SC64:
83 case Mips::SCD:
84 case Mips::SCE:
85 return 16;
86 case Mips::LLE_MM:
87 case Mips::LL_MM:
88 case Mips::SCE_MM:
89 case Mips::SC_MM:
90 return 12;
91 case Mips::LL64_R6:
92 case Mips::LL_R6:
93 case Mips::LLD_R6:
94 case Mips::SC64_R6:
95 case Mips::SCD_R6:
96 case Mips::SC_R6:
97 case Mips::LL_MMR6:
98 case Mips::SC_MMR6:
99 return 9;
100 case Mips::INLINEASM: {
101 const InlineAsm::Flag F(MO.getImm());
102 switch (F.getMemoryConstraintID()) {
103 case InlineAsm::ConstraintCode::ZC: {
104 if (Subtarget.inMicroMipsMode())
105 return 12;
106
107 if (Subtarget.hasMips32r6())
108 return 9;
109
110 return 16;
111 }
112 default:
113 return 16;
114 }
115 }
116 default:
117 return 16;
118 }
119}
120
121/// Get the scale factor applied to the immediate in the given load/store.
122static inline unsigned getLoadStoreOffsetAlign(const unsigned Opcode) {
123 switch (Opcode) {
124 case Mips::LD_H:
125 case Mips::ST_H:
126 return 2;
127 case Mips::LD_W:
128 case Mips::ST_W:
129 return 4;
130 case Mips::LD_D:
131 case Mips::ST_D:
132 return 8;
133 default:
134 return 1;
135 }
136}
137
138void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
139 unsigned OpNo, int FrameIndex,
140 uint64_t StackSize,
141 int64_t SPOffset) const {
142 MachineInstr &MI = *II;
143 MachineFunction &MF = *MI.getParent()->getParent();
144 MachineFrameInfo &MFI = MF.getFrameInfo();
145 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
146
147 MipsABIInfo ABI = MF.getSubtarget<MipsSubtarget>().getABI();
148 const MipsRegisterInfo *RegInfo =
149 static_cast<const MipsRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
150
151 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
152 int MinCSFI = 0;
153 int MaxCSFI = -1;
154
155 if (CSI.size()) {
156 MinCSFI = CSI[0].getFrameIdx();
157 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
158 }
159
160 bool EhDataRegFI = MipsFI->isEhDataRegFI(FI: FrameIndex);
161 bool IsISRRegFI = MipsFI->isISRRegFI(FI: FrameIndex);
162 // The following stack frame objects are always referenced relative to $sp:
163 // 1. Outgoing arguments.
164 // 2. Pointer to dynamically allocated stack space.
165 // 3. Locations for callee-saved registers.
166 // 4. Locations for eh data registers.
167 // 5. Locations for ISR saved Coprocessor 0 registers 12 & 14.
168 // Everything else is referenced relative to whatever register
169 // getFrameRegister() returns.
170 unsigned FrameReg;
171
172 if ((FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI) || EhDataRegFI ||
173 IsISRRegFI)
174 FrameReg = ABI.GetStackPtr();
175 else if (RegInfo->hasStackRealignment(MF)) {
176 if (MFI.hasVarSizedObjects() && !MFI.isFixedObjectIndex(ObjectIdx: FrameIndex))
177 FrameReg = ABI.GetBasePtr();
178 else if (MFI.isFixedObjectIndex(ObjectIdx: FrameIndex))
179 FrameReg = getFrameRegister(MF);
180 else
181 FrameReg = ABI.GetStackPtr();
182 } else
183 FrameReg = getFrameRegister(MF);
184
185 // Calculate final offset.
186 // - There is no need to change the offset if the frame object is one of the
187 // following: an outgoing argument, pointer to a dynamically allocated
188 // stack space or a $gp restore location,
189 // - If the frame object is any of the following, its offset must be adjusted
190 // by adding the size of the stack:
191 // incoming argument, callee-saved register location or local variable.
192 bool IsKill = false;
193 int64_t Offset;
194
195 Offset = SPOffset + (int64_t)StackSize;
196 Offset += MI.getOperand(i: OpNo + 1).getImm();
197
198 LLVM_DEBUG(errs() << "Offset : " << Offset << "\n"
199 << "<--------->\n");
200
201 if (!MI.isDebugValue()) {
202 // Make sure Offset fits within the field available.
203 // For MSA instructions, this is a 10-bit signed immediate (scaled by
204 // element size), otherwise it is a 16-bit signed immediate.
205 unsigned OffsetBitSize =
206 getLoadStoreOffsetSizeInBits(Subtarget: MF.getSubtarget<MipsSubtarget>(),
207 Opcode: MI.getOpcode(), MO: MI.getOperand(i: OpNo - 1));
208 const Align OffsetAlign(getLoadStoreOffsetAlign(Opcode: MI.getOpcode()));
209 if (OffsetBitSize < 16 && isInt<16>(x: Offset) &&
210 (!isIntN(N: OffsetBitSize, x: Offset) || !isAligned(Lhs: OffsetAlign, SizeInBytes: Offset))) {
211 // If we have an offset that needs to fit into a signed n-bit immediate
212 // (where n < 16) and doesn't, but does fit into 16-bits then use an ADDiu
213 MachineBasicBlock &MBB = *MI.getParent();
214 DebugLoc DL = II->getDebugLoc();
215 const TargetRegisterClass *PtrRC =
216 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
217 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
218 Register Reg = RegInfo.createVirtualRegister(RegClass: PtrRC);
219 const MipsSEInstrInfo &TII =
220 *static_cast<const MipsSEInstrInfo *>(
221 MBB.getParent()->getSubtarget().getInstrInfo());
222 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: ABI.GetPtrAddiuOp()), DestReg: Reg)
223 .addReg(RegNo: FrameReg)
224 .addImm(Val: Offset);
225
226 FrameReg = Reg;
227 Offset = 0;
228 IsKill = true;
229 } else if (!isInt<16>(x: Offset)) {
230 // Otherwise split the offset into 16-bit pieces and add it in multiple
231 // instructions.
232 MachineBasicBlock &MBB = *MI.getParent();
233 DebugLoc DL = II->getDebugLoc();
234 unsigned NewImm = 0;
235 const MipsSEInstrInfo &TII =
236 *static_cast<const MipsSEInstrInfo *>(
237 MBB.getParent()->getSubtarget().getInstrInfo());
238 unsigned Reg = TII.loadImmediate(Imm: Offset, MBB, II, DL,
239 NewImm: OffsetBitSize == 16 ? &NewImm : nullptr);
240 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: ABI.GetPtrAdduOp()), DestReg: Reg).addReg(RegNo: FrameReg)
241 .addReg(RegNo: Reg, Flags: RegState::Kill);
242
243 FrameReg = Reg;
244 Offset = SignExtend64<16>(x: NewImm);
245 IsKill = true;
246 }
247 }
248
249 MI.getOperand(i: OpNo).ChangeToRegister(Reg: FrameReg, isDef: false, isImp: false, isKill: IsKill);
250 MI.getOperand(i: OpNo + 1).ChangeToImmediate(ImmVal: Offset);
251}
252