1//===-- MipsSERegisterInfo.cpp - MIPS32/64 Register Information -== -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the MIPS32/64 implementation of the TargetRegisterInfo
10// class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MipsSERegisterInfo.h"
15#include "Mips.h"
16#include "MipsMachineFunction.h"
17#include "MipsSEInstrInfo.h"
18#include "MipsSubtarget.h"
19#include "MipsTargetMachine.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/CodeGen/TargetFrameLowering.h"
25#include "llvm/CodeGen/TargetInstrInfo.h"
26#include "llvm/IR/Function.h"
27#include "llvm/IR/Type.h"
28#include "llvm/Support/Debug.h"
29#include "llvm/Support/raw_ostream.h"
30#include "llvm/Target/TargetMachine.h"
31#include "llvm/Target/TargetOptions.h"
32
33using namespace llvm;
34
35#define DEBUG_TYPE "mips-reg-info"
36
37MipsSERegisterInfo::MipsSERegisterInfo(const MipsSubtarget &STI)
38 : MipsRegisterInfo(STI) {}
39
40bool MipsSERegisterInfo::
41requiresRegisterScavenging(const MachineFunction &MF) const {
42 return true;
43}
44
45bool MipsSERegisterInfo::
46requiresFrameIndexScavenging(const MachineFunction &MF) const {
47 return true;
48}
49
50const TargetRegisterClass *
51MipsSERegisterInfo::intRegClass(unsigned Size) const {
52 if (Size == 4)
53 return &Mips::GPR32RegClass;
54
55 assert(Size == 8);
56 return &Mips::GPR64RegClass;
57}
58
59/// Get the size of the offset supported by the given load/store/inline asm.
60/// The result includes the effects of any scale factors applied to the
61/// instruction immediate.
62static inline unsigned
63getLoadStoreOffsetSizeInBits(const MipsSubtarget &Subtarget,
64 const unsigned Opcode, const MachineOperand &MO) {
65 switch (Opcode) {
66 case Mips::LD_B:
67 case Mips::ST_B:
68 return 10;
69 case Mips::LD_H:
70 case Mips::ST_H:
71 return 10 + 1 /* scale factor */;
72 case Mips::LD_W:
73 case Mips::ST_W:
74 return 10 + 2 /* scale factor */;
75 case Mips::LD_D:
76 case Mips::ST_D:
77 return 10 + 3 /* scale factor */;
78 case Mips::LL:
79 case Mips::LL64:
80 case Mips::LLD:
81 case Mips::LLE:
82 case Mips::SC:
83 case Mips::SC64:
84 case Mips::SCD:
85 case Mips::SCE:
86 return 16;
87 case Mips::LLE_MM:
88 case Mips::LL_MM:
89 case Mips::SCE_MM:
90 case Mips::SC_MM:
91 return 12;
92 case Mips::LL64_R6:
93 case Mips::LL_R6:
94 case Mips::LLD_R6:
95 case Mips::SC64_R6:
96 case Mips::SCD_R6:
97 case Mips::SC_R6:
98 case Mips::LL_MMR6:
99 case Mips::SC_MMR6:
100 return 9;
101 case Mips::INLINEASM: {
102 const InlineAsm::Flag F(MO.getImm());
103 switch (F.getMemoryConstraintID()) {
104 case InlineAsm::ConstraintCode::ZC: {
105 if (Subtarget.inMicroMipsMode())
106 return 12;
107
108 if (Subtarget.hasMips32r6())
109 return 9;
110
111 return 16;
112 }
113 default:
114 return 16;
115 }
116 }
117 default:
118 return 16;
119 }
120}
121
122/// Get the scale factor applied to the immediate in the given load/store.
123static inline unsigned getLoadStoreOffsetAlign(const unsigned Opcode) {
124 switch (Opcode) {
125 case Mips::LD_H:
126 case Mips::ST_H:
127 return 2;
128 case Mips::LD_W:
129 case Mips::ST_W:
130 return 4;
131 case Mips::LD_D:
132 case Mips::ST_D:
133 return 8;
134 default:
135 return 1;
136 }
137}
138
139void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
140 unsigned OpNo, int FrameIndex,
141 uint64_t StackSize,
142 int64_t SPOffset) const {
143 MachineInstr &MI = *II;
144 MachineFunction &MF = *MI.getParent()->getParent();
145 MachineFrameInfo &MFI = MF.getFrameInfo();
146 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
147
148 MipsABIInfo ABI =
149 static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI();
150 const MipsRegisterInfo *RegInfo =
151 static_cast<const MipsRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
152
153 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
154 int MinCSFI = 0;
155 int MaxCSFI = -1;
156
157 if (CSI.size()) {
158 MinCSFI = CSI[0].getFrameIdx();
159 MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
160 }
161
162 bool EhDataRegFI = MipsFI->isEhDataRegFI(FI: FrameIndex);
163 bool IsISRRegFI = MipsFI->isISRRegFI(FI: FrameIndex);
164 // The following stack frame objects are always referenced relative to $sp:
165 // 1. Outgoing arguments.
166 // 2. Pointer to dynamically allocated stack space.
167 // 3. Locations for callee-saved registers.
168 // 4. Locations for eh data registers.
169 // 5. Locations for ISR saved Coprocessor 0 registers 12 & 14.
170 // Everything else is referenced relative to whatever register
171 // getFrameRegister() returns.
172 unsigned FrameReg;
173
174 if ((FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI) || EhDataRegFI ||
175 IsISRRegFI)
176 FrameReg = ABI.GetStackPtr();
177 else if (RegInfo->hasStackRealignment(MF)) {
178 if (MFI.hasVarSizedObjects() && !MFI.isFixedObjectIndex(ObjectIdx: FrameIndex))
179 FrameReg = ABI.GetBasePtr();
180 else if (MFI.isFixedObjectIndex(ObjectIdx: FrameIndex))
181 FrameReg = getFrameRegister(MF);
182 else
183 FrameReg = ABI.GetStackPtr();
184 } else
185 FrameReg = getFrameRegister(MF);
186
187 // Calculate final offset.
188 // - There is no need to change the offset if the frame object is one of the
189 // following: an outgoing argument, pointer to a dynamically allocated
190 // stack space or a $gp restore location,
191 // - If the frame object is any of the following, its offset must be adjusted
192 // by adding the size of the stack:
193 // incoming argument, callee-saved register location or local variable.
194 bool IsKill = false;
195 int64_t Offset;
196
197 Offset = SPOffset + (int64_t)StackSize;
198 Offset += MI.getOperand(i: OpNo + 1).getImm();
199
200 LLVM_DEBUG(errs() << "Offset : " << Offset << "\n"
201 << "<--------->\n");
202
203 if (!MI.isDebugValue()) {
204 // Make sure Offset fits within the field available.
205 // For MSA instructions, this is a 10-bit signed immediate (scaled by
206 // element size), otherwise it is a 16-bit signed immediate.
207 unsigned OffsetBitSize =
208 getLoadStoreOffsetSizeInBits(Subtarget: MF.getSubtarget<MipsSubtarget>(),
209 Opcode: MI.getOpcode(), MO: MI.getOperand(i: OpNo - 1));
210 const Align OffsetAlign(getLoadStoreOffsetAlign(Opcode: MI.getOpcode()));
211 if (OffsetBitSize < 16 && isInt<16>(x: Offset) &&
212 (!isIntN(N: OffsetBitSize, x: Offset) || !isAligned(Lhs: OffsetAlign, SizeInBytes: Offset))) {
213 // If we have an offset that needs to fit into a signed n-bit immediate
214 // (where n < 16) and doesn't, but does fit into 16-bits then use an ADDiu
215 MachineBasicBlock &MBB = *MI.getParent();
216 DebugLoc DL = II->getDebugLoc();
217 const TargetRegisterClass *PtrRC =
218 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
219 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
220 Register Reg = RegInfo.createVirtualRegister(RegClass: PtrRC);
221 const MipsSEInstrInfo &TII =
222 *static_cast<const MipsSEInstrInfo *>(
223 MBB.getParent()->getSubtarget().getInstrInfo());
224 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: ABI.GetPtrAddiuOp()), DestReg: Reg)
225 .addReg(RegNo: FrameReg)
226 .addImm(Val: Offset);
227
228 FrameReg = Reg;
229 Offset = 0;
230 IsKill = true;
231 } else if (!isInt<16>(x: Offset)) {
232 // Otherwise split the offset into 16-bit pieces and add it in multiple
233 // instructions.
234 MachineBasicBlock &MBB = *MI.getParent();
235 DebugLoc DL = II->getDebugLoc();
236 unsigned NewImm = 0;
237 const MipsSEInstrInfo &TII =
238 *static_cast<const MipsSEInstrInfo *>(
239 MBB.getParent()->getSubtarget().getInstrInfo());
240 unsigned Reg = TII.loadImmediate(Imm: Offset, MBB, II, DL,
241 NewImm: OffsetBitSize == 16 ? &NewImm : nullptr);
242 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: ABI.GetPtrAdduOp()), DestReg: Reg).addReg(RegNo: FrameReg)
243 .addReg(RegNo: Reg, Flags: RegState::Kill);
244
245 FrameReg = Reg;
246 Offset = SignExtend64<16>(x: NewImm);
247 IsKill = true;
248 }
249 }
250
251 MI.getOperand(i: OpNo).ChangeToRegister(Reg: FrameReg, isDef: false, isImp: false, isKill: IsKill);
252 MI.getOperand(i: OpNo + 1).ChangeToImmediate(ImmVal: Offset);
253}
254