1//===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the PowerPC implementation of the TargetRegisterInfo
10// class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCRegisterInfo.h"
15#include "PPCFrameLowering.h"
16#include "PPCInstrBuilder.h"
17#include "PPCMachineFunctionInfo.h"
18#include "PPCSubtarget.h"
19#include "PPCTargetMachine.h"
20#include "llvm/ADT/BitVector.h"
21#include "llvm/ADT/Statistic.h"
22#include "llvm/CodeGen/MachineFrameInfo.h"
23#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/MachineInstrBuilder.h"
25#include "llvm/CodeGen/MachineModuleInfo.h"
26#include "llvm/CodeGen/MachineRegisterInfo.h"
27#include "llvm/CodeGen/RegisterScavenging.h"
28#include "llvm/CodeGen/TargetFrameLowering.h"
29#include "llvm/CodeGen/TargetInstrInfo.h"
30#include "llvm/CodeGen/VirtRegMap.h"
31#include "llvm/IR/CallingConv.h"
32#include "llvm/IR/Function.h"
33#include "llvm/IR/Type.h"
34#include "llvm/Support/CommandLine.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/MathExtras.h"
38#include "llvm/Support/raw_ostream.h"
39#include "llvm/Target/TargetMachine.h"
40#include "llvm/Target/TargetOptions.h"
41
42using namespace llvm;
43
44#define DEBUG_TYPE "reginfo"
45
46#define GET_REGINFO_TARGET_DESC
47#include "PPCGenRegisterInfo.inc"
48
49STATISTIC(InflateGPRC, "Number of gprc inputs for getLargestLegalClass");
50STATISTIC(InflateGP8RC, "Number of g8rc inputs for getLargestLegalClass");
51
52static cl::opt<bool>
53EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(Val: true),
54 cl::desc("Enable use of a base pointer for complex stack frames"));
55
56static cl::opt<bool>
57AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(Val: false),
58 cl::desc("Force the use of a base pointer in every function"));
59
60static cl::opt<bool>
61EnableGPRToVecSpills("ppc-enable-gpr-to-vsr-spills", cl::Hidden, cl::init(Val: false),
62 cl::desc("Enable spills from gpr to vsr rather than stack"));
63
64static cl::opt<bool>
65StackPtrConst("ppc-stack-ptr-caller-preserved",
66 cl::desc("Consider R1 caller preserved so stack saves of "
67 "caller preserved registers can be LICM candidates"),
68 cl::init(Val: true), cl::Hidden);
69
70static cl::opt<unsigned>
71MaxCRBitSpillDist("ppc-max-crbit-spill-dist",
72 cl::desc("Maximum search distance for definition of CR bit "
73 "spill on ppc"),
74 cl::Hidden, cl::init(Val: 100));
75
76// Copies/moves of physical accumulators are expensive operations
77// that should be avoided whenever possible. MMA instructions are
78// meant to be used in performance-sensitive computational kernels.
79// This option is provided, at least for the time being, to give the
80// user a tool to detect this expensive operation and either rework
81// their code or report a compiler bug if that turns out to be the
82// cause.
83#ifndef NDEBUG
84static cl::opt<bool>
85ReportAccMoves("ppc-report-acc-moves",
86 cl::desc("Emit information about accumulator register spills "
87 "and copies"),
88 cl::Hidden, cl::init(false));
89#endif
90
91extern cl::opt<bool> DisableAutoPairedVecSt;
92
93static unsigned offsetMinAlignForOpcode(unsigned OpC);
94
95PPCRegisterInfo::PPCRegisterInfo(const PPCTargetMachine &TM)
96 : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR,
97 TM.isPPC64() ? 0 : 1,
98 TM.isPPC64() ? 0 : 1),
99 TM(TM) {
100 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
101 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
102 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
103 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
104 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
105 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
106 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
107 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
108 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32;
109
110 // 64-bit
111 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
112 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
113 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
114 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
115 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
116 ImmToIdxMap[PPC::LQ] = PPC::LQX_PSEUDO;
117 ImmToIdxMap[PPC::STQ] = PPC::STQX_PSEUDO;
118
119 // VSX
120 ImmToIdxMap[PPC::DFLOADf32] = PPC::LXSSPX;
121 ImmToIdxMap[PPC::DFLOADf64] = PPC::LXSDX;
122 ImmToIdxMap[PPC::SPILLTOVSR_LD] = PPC::SPILLTOVSR_LDX;
123 ImmToIdxMap[PPC::SPILLTOVSR_ST] = PPC::SPILLTOVSR_STX;
124 ImmToIdxMap[PPC::DFSTOREf32] = PPC::STXSSPX;
125 ImmToIdxMap[PPC::DFSTOREf64] = PPC::STXSDX;
126 ImmToIdxMap[PPC::LXV] = PPC::LXVX;
127 ImmToIdxMap[PPC::LXSD] = PPC::LXSDX;
128 ImmToIdxMap[PPC::LXSSP] = PPC::LXSSPX;
129 ImmToIdxMap[PPC::STXV] = PPC::STXVX;
130 ImmToIdxMap[PPC::STXSD] = PPC::STXSDX;
131 ImmToIdxMap[PPC::STXSSP] = PPC::STXSSPX;
132
133 // SPE
134 ImmToIdxMap[PPC::EVLDD] = PPC::EVLDDX;
135 ImmToIdxMap[PPC::EVSTDD] = PPC::EVSTDDX;
136 ImmToIdxMap[PPC::SPESTW] = PPC::SPESTWX;
137 ImmToIdxMap[PPC::SPELWZ] = PPC::SPELWZX;
138
139 // Power10
140 ImmToIdxMap[PPC::PLBZ] = PPC::LBZX; ImmToIdxMap[PPC::PLBZ8] = PPC::LBZX8;
141 ImmToIdxMap[PPC::PLHZ] = PPC::LHZX; ImmToIdxMap[PPC::PLHZ8] = PPC::LHZX8;
142 ImmToIdxMap[PPC::PLHA] = PPC::LHAX; ImmToIdxMap[PPC::PLHA8] = PPC::LHAX8;
143 ImmToIdxMap[PPC::PLWZ] = PPC::LWZX; ImmToIdxMap[PPC::PLWZ8] = PPC::LWZX8;
144 ImmToIdxMap[PPC::PLWA] = PPC::LWAX; ImmToIdxMap[PPC::PLWA8] = PPC::LWAX;
145 ImmToIdxMap[PPC::PLD] = PPC::LDX; ImmToIdxMap[PPC::PSTD] = PPC::STDX;
146
147 ImmToIdxMap[PPC::PSTB] = PPC::STBX; ImmToIdxMap[PPC::PSTB8] = PPC::STBX8;
148 ImmToIdxMap[PPC::PSTH] = PPC::STHX; ImmToIdxMap[PPC::PSTH8] = PPC::STHX8;
149 ImmToIdxMap[PPC::PSTW] = PPC::STWX; ImmToIdxMap[PPC::PSTW8] = PPC::STWX8;
150
151 ImmToIdxMap[PPC::PLFS] = PPC::LFSX; ImmToIdxMap[PPC::PSTFS] = PPC::STFSX;
152 ImmToIdxMap[PPC::PLFD] = PPC::LFDX; ImmToIdxMap[PPC::PSTFD] = PPC::STFDX;
153 ImmToIdxMap[PPC::PLXSSP] = PPC::LXSSPX; ImmToIdxMap[PPC::PSTXSSP] = PPC::STXSSPX;
154 ImmToIdxMap[PPC::PLXSD] = PPC::LXSDX; ImmToIdxMap[PPC::PSTXSD] = PPC::STXSDX;
155 ImmToIdxMap[PPC::PLXV] = PPC::LXVX; ImmToIdxMap[PPC::PSTXV] = PPC::STXVX;
156
157 ImmToIdxMap[PPC::LXVP] = PPC::LXVPX;
158 ImmToIdxMap[PPC::STXVP] = PPC::STXVPX;
159 ImmToIdxMap[PPC::PLXVP] = PPC::LXVPX;
160 ImmToIdxMap[PPC::PSTXVP] = PPC::STXVPX;
161}
162
163const MCPhysReg*
164PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
165 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
166 if (MF->getFunction().getCallingConv() == CallingConv::AnyReg) {
167 if (!TM.isPPC64() && Subtarget.isAIXABI())
168 report_fatal_error(reason: "AnyReg unimplemented on 32-bit AIX.");
169 if (Subtarget.hasVSX()) {
170 if (Subtarget.pairedVectorMemops())
171 return CSR_64_AllRegs_VSRP_SaveList;
172 if (Subtarget.isAIXABI() && !Subtarget.isAIXExtendedAltivecABI())
173 return CSR_64_AllRegs_AIX_Dflt_VSX_SaveList;
174 return CSR_64_AllRegs_VSX_SaveList;
175 }
176 if (Subtarget.hasAltivec()) {
177 if (Subtarget.isAIXABI() && !Subtarget.isAIXExtendedAltivecABI())
178 return CSR_64_AllRegs_AIX_Dflt_Altivec_SaveList;
179 return CSR_64_AllRegs_Altivec_SaveList;
180 }
181 return CSR_64_AllRegs_SaveList;
182 }
183
184 // On PPC64, we might need to save r2 (but only if it is not reserved).
185 // We do not need to treat R2 as callee-saved when using PC-Relative calls
186 // because any direct uses of R2 will cause it to be reserved. If the function
187 // is a leaf or the only uses of R2 are implicit uses for calls, the calls
188 // will use the @notoc relocation which will cause this function to set the
189 // st_other bit to 1, thereby communicating to its caller that it arbitrarily
190 // clobbers the TOC.
191 bool SaveR2 = MF->getRegInfo().isAllocatable(PhysReg: PPC::X2) &&
192 !Subtarget.isUsingPCRelativeCalls();
193
194 // Cold calling convention CSRs.
195 if (MF->getFunction().getCallingConv() == CallingConv::Cold) {
196 if (Subtarget.isAIXABI())
197 report_fatal_error(reason: "Cold calling unimplemented on AIX.");
198 if (TM.isPPC64()) {
199 if (Subtarget.pairedVectorMemops())
200 return SaveR2 ? CSR_SVR64_ColdCC_R2_VSRP_SaveList
201 : CSR_SVR64_ColdCC_VSRP_SaveList;
202 if (Subtarget.hasAltivec())
203 return SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList
204 : CSR_SVR64_ColdCC_Altivec_SaveList;
205 return SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList
206 : CSR_SVR64_ColdCC_SaveList;
207 }
208 // 32-bit targets.
209 if (Subtarget.pairedVectorMemops())
210 return CSR_SVR32_ColdCC_VSRP_SaveList;
211 else if (Subtarget.hasAltivec())
212 return CSR_SVR32_ColdCC_Altivec_SaveList;
213 else if (Subtarget.hasSPE())
214 return CSR_SVR32_ColdCC_SPE_SaveList;
215 return CSR_SVR32_ColdCC_SaveList;
216 }
217 // Standard calling convention CSRs.
218 if (TM.isPPC64()) {
219 if (Subtarget.pairedVectorMemops()) {
220 if (Subtarget.isAIXABI()) {
221 if (!Subtarget.isAIXExtendedAltivecABI())
222 return SaveR2 ? CSR_PPC64_R2_SaveList : CSR_PPC64_SaveList;
223 return SaveR2 ? CSR_AIX64_R2_VSRP_SaveList : CSR_AIX64_VSRP_SaveList;
224 }
225 return SaveR2 ? CSR_SVR464_R2_VSRP_SaveList : CSR_SVR464_VSRP_SaveList;
226 }
227 if (Subtarget.hasAltivec() &&
228 (!Subtarget.isAIXABI() || Subtarget.isAIXExtendedAltivecABI())) {
229 return SaveR2 ? CSR_PPC64_R2_Altivec_SaveList
230 : CSR_PPC64_Altivec_SaveList;
231 }
232 return SaveR2 ? CSR_PPC64_R2_SaveList : CSR_PPC64_SaveList;
233 }
234 // 32-bit targets.
235 if (Subtarget.isAIXABI()) {
236 if (Subtarget.pairedVectorMemops())
237 return Subtarget.isAIXExtendedAltivecABI() ? CSR_AIX32_VSRP_SaveList
238 : CSR_AIX32_SaveList;
239 if (Subtarget.hasAltivec())
240 return Subtarget.isAIXExtendedAltivecABI() ? CSR_AIX32_Altivec_SaveList
241 : CSR_AIX32_SaveList;
242 return CSR_AIX32_SaveList;
243 }
244 if (Subtarget.pairedVectorMemops())
245 return CSR_SVR432_VSRP_SaveList;
246 if (Subtarget.hasAltivec())
247 return CSR_SVR432_Altivec_SaveList;
248 else if (Subtarget.hasSPE()) {
249 if (TM.isPositionIndependent() && !TM.isPPC64())
250 return CSR_SVR432_SPE_NO_S30_31_SaveList;
251 return CSR_SVR432_SPE_SaveList;
252 }
253 return CSR_SVR432_SaveList;
254}
255
256const uint32_t *
257PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
258 CallingConv::ID CC) const {
259 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
260 if (CC == CallingConv::AnyReg) {
261 if (Subtarget.hasVSX()) {
262 if (Subtarget.pairedVectorMemops())
263 return CSR_64_AllRegs_VSRP_RegMask;
264 if (Subtarget.isAIXABI() && !Subtarget.isAIXExtendedAltivecABI())
265 return CSR_64_AllRegs_AIX_Dflt_VSX_RegMask;
266 return CSR_64_AllRegs_VSX_RegMask;
267 }
268 if (Subtarget.hasAltivec()) {
269 if (Subtarget.isAIXABI() && !Subtarget.isAIXExtendedAltivecABI())
270 return CSR_64_AllRegs_AIX_Dflt_Altivec_RegMask;
271 return CSR_64_AllRegs_Altivec_RegMask;
272 }
273 return CSR_64_AllRegs_RegMask;
274 }
275
276 if (Subtarget.isAIXABI()) {
277 if (Subtarget.pairedVectorMemops()) {
278 if (!Subtarget.isAIXExtendedAltivecABI())
279 return TM.isPPC64() ? CSR_PPC64_RegMask : CSR_AIX32_RegMask;
280 return TM.isPPC64() ? CSR_AIX64_VSRP_RegMask : CSR_AIX32_VSRP_RegMask;
281 }
282 return TM.isPPC64() ? ((Subtarget.hasAltivec() &&
283 Subtarget.isAIXExtendedAltivecABI())
284 ? CSR_PPC64_Altivec_RegMask
285 : CSR_PPC64_RegMask)
286 : ((Subtarget.hasAltivec() &&
287 Subtarget.isAIXExtendedAltivecABI())
288 ? CSR_AIX32_Altivec_RegMask
289 : CSR_AIX32_RegMask);
290 }
291
292 if (CC == CallingConv::Cold) {
293 if (TM.isPPC64())
294 return Subtarget.pairedVectorMemops()
295 ? CSR_SVR64_ColdCC_VSRP_RegMask
296 : (Subtarget.hasAltivec() ? CSR_SVR64_ColdCC_Altivec_RegMask
297 : CSR_SVR64_ColdCC_RegMask);
298 else
299 return Subtarget.pairedVectorMemops()
300 ? CSR_SVR32_ColdCC_VSRP_RegMask
301 : (Subtarget.hasAltivec()
302 ? CSR_SVR32_ColdCC_Altivec_RegMask
303 : (Subtarget.hasSPE() ? CSR_SVR32_ColdCC_SPE_RegMask
304 : CSR_SVR32_ColdCC_RegMask));
305 }
306
307 if (TM.isPPC64())
308 return Subtarget.pairedVectorMemops()
309 ? CSR_SVR464_VSRP_RegMask
310 : (Subtarget.hasAltivec() ? CSR_PPC64_Altivec_RegMask
311 : CSR_PPC64_RegMask);
312 else
313 return Subtarget.pairedVectorMemops()
314 ? CSR_SVR432_VSRP_RegMask
315 : (Subtarget.hasAltivec()
316 ? CSR_SVR432_Altivec_RegMask
317 : (Subtarget.hasSPE()
318 ? (TM.isPositionIndependent()
319 ? CSR_SVR432_SPE_NO_S30_31_RegMask
320 : CSR_SVR432_SPE_RegMask)
321 : CSR_SVR432_RegMask));
322}
323
324const uint32_t*
325PPCRegisterInfo::getNoPreservedMask() const {
326 return CSR_NoRegs_RegMask;
327}
328
329void PPCRegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
330 for (unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8, PPC::RM})
331 Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32));
332}
333
334BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
335 BitVector Reserved(getNumRegs());
336 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
337 const PPCFrameLowering *TFI = getFrameLowering(MF);
338
339 // The ZERO register is not really a register, but the representation of r0
340 // when used in instructions that treat r0 as the constant 0.
341 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::ZERO);
342
343 // The FP register is also not really a register, but is the representation
344 // of the frame pointer register used by ISD::FRAMEADDR.
345 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::FP);
346
347 // The BP register is also not really a register, but is the representation
348 // of the base pointer register used by setjmp.
349 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::BP);
350
351 // The counter registers must be reserved so that counter-based loops can
352 // be correctly formed (and the mtctr instructions are not DCE'd).
353 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::CTR);
354 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::CTR8);
355
356 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::R1);
357 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::LR);
358 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::LR8);
359 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::RM);
360
361 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::VRSAVE);
362
363 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
364 bool UsesTOCBasePtr = FuncInfo->usesTOCBasePtr();
365 // The SVR4 ABI reserves r2 and r13
366 if (Subtarget.isSVR4ABI() || Subtarget.isAIXABI()) {
367 // We only reserve r2 if we need to use the TOC pointer. If we have no
368 // explicit uses of the TOC pointer (meaning we're a leaf function with
369 // no constant-pool loads, etc.) and we have no potential uses inside an
370 // inline asm block, then we can treat r2 has an ordinary callee-saved
371 // register.
372 if (!TM.isPPC64() || UsesTOCBasePtr || MF.hasInlineAsm())
373 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::R2); // System-reserved register.
374
375 if (Subtarget.isSVR4ABI())
376 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::R13); // Small Data Area pointer register.
377 }
378
379 // On PPC64, r13 is the thread pointer. Never allocate this register.
380 if (TM.isPPC64())
381 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::R13);
382
383 if (TFI->needsFP(MF))
384 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::R31);
385
386 bool IsPositionIndependent = TM.isPositionIndependent();
387 if (hasBasePointer(MF)) {
388 if (Subtarget.is32BitELFABI() && IsPositionIndependent)
389 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::R29);
390 else
391 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::R30);
392 }
393
394 if (Subtarget.is32BitELFABI() && IsPositionIndependent)
395 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::R30);
396
397 // Reserve Altivec registers when Altivec is unavailable.
398 if (!Subtarget.hasAltivec())
399 for (MCRegister Reg : PPC::VRRCRegClass)
400 markSuperRegs(RegisterSet&: Reserved, Reg);
401
402 if (Subtarget.isAIXABI() && Subtarget.hasAltivec() &&
403 !Subtarget.isAIXExtendedAltivecABI()) {
404 // In the AIX default Altivec ABI, vector registers VR20-VR31 are reserved
405 // and cannot be used.
406 for (auto Reg : CSR_Altivec_SaveList) {
407 if (Reg == 0)
408 break;
409 markSuperRegs(RegisterSet&: Reserved, Reg);
410 for (MCRegAliasIterator AS(Reg, this, true); AS.isValid(); ++AS) {
411 Reserved.set(*AS);
412 }
413 }
414 }
415
416 assert(checkAllSuperRegsMarked(Reserved));
417 return Reserved;
418}
419
420bool PPCRegisterInfo::isAsmClobberable(const MachineFunction &MF,
421 MCRegister PhysReg) const {
422 // CTR and LR registers are always reserved, but they are asm clobberable.
423 if (PhysReg == PPC::CTR || PhysReg == PPC::CTR8 || PhysReg == PPC::LR ||
424 PhysReg == PPC::LR8)
425 return true;
426
427 return !getReservedRegs(MF).test(Idx: PhysReg);
428}
429
430bool PPCRegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF) const {
431 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
432 const PPCInstrInfo *InstrInfo = Subtarget.getInstrInfo();
433 const MachineFrameInfo &MFI = MF.getFrameInfo();
434 const std::vector<CalleeSavedInfo> &Info = MFI.getCalleeSavedInfo();
435
436 LLVM_DEBUG(dbgs() << "requiresFrameIndexScavenging for " << MF.getName()
437 << ".\n");
438 // If the callee saved info is invalid we have to default to true for safety.
439 if (!MFI.isCalleeSavedInfoValid()) {
440 LLVM_DEBUG(dbgs() << "TRUE - Invalid callee saved info.\n");
441 return true;
442 }
443
444 // We will require the use of X-Forms because the frame is larger than what
445 // can be represented in signed 16 bits that fit in the immediate of a D-Form.
446 // If we need an X-Form then we need a register to store the address offset.
447 unsigned FrameSize = MFI.getStackSize();
448 // Signed 16 bits means that the FrameSize cannot be more than 15 bits.
449 if (FrameSize & ~0x7FFF) {
450 LLVM_DEBUG(dbgs() << "TRUE - Frame size is too large for D-Form.\n");
451 return true;
452 }
453
454 // The callee saved info is valid so it can be traversed.
455 // Checking for registers that need saving that do not have load or store
456 // forms where the address offset is an immediate.
457 for (const CalleeSavedInfo &CSI : Info) {
458 // If the spill is to a register no scavenging is required.
459 if (CSI.isSpilledToReg())
460 continue;
461
462 int FrIdx = CSI.getFrameIdx();
463 Register Reg = CSI.getReg();
464
465 const TargetRegisterClass *RC = getMinimalPhysRegClass(Reg);
466 unsigned Opcode = InstrInfo->getStoreOpcodeForSpill(RC);
467 if (!MFI.isFixedObjectIndex(ObjectIdx: FrIdx)) {
468 // This is not a fixed object. If it requires alignment then we may still
469 // need to use the XForm.
470 if (offsetMinAlignForOpcode(OpC: Opcode) > 1) {
471 LLVM_DEBUG(dbgs() << "Memory Operand: " << InstrInfo->getName(Opcode)
472 << " for register " << printReg(Reg, this) << ".\n");
473 LLVM_DEBUG(dbgs() << "TRUE - Not fixed frame object that requires "
474 << "alignment.\n");
475 return true;
476 }
477 }
478
479 // This is eiher:
480 // 1) A fixed frame index object which we know are aligned so
481 // as long as we have a valid DForm/DSForm/DQForm (non XForm) we don't
482 // need to consider the alignment here.
483 // 2) A not fixed object but in that case we now know that the min required
484 // alignment is no more than 1 based on the previous check.
485 if (InstrInfo->isXFormMemOp(Opcode)) {
486 LLVM_DEBUG(dbgs() << "Memory Operand: " << InstrInfo->getName(Opcode)
487 << " for register " << printReg(Reg, this) << ".\n");
488 LLVM_DEBUG(dbgs() << "TRUE - Memory operand is X-Form.\n");
489 return true;
490 }
491
492 // This is a spill/restore of a quadword.
493 if ((Opcode == PPC::RESTORE_QUADWORD) || (Opcode == PPC::SPILL_QUADWORD)) {
494 LLVM_DEBUG(dbgs() << "Memory Operand: " << InstrInfo->getName(Opcode)
495 << " for register " << printReg(Reg, this) << ".\n");
496 LLVM_DEBUG(dbgs() << "TRUE - Memory operand is a quadword.\n");
497 return true;
498 }
499 }
500 LLVM_DEBUG(dbgs() << "FALSE - Scavenging is not required.\n");
501 return false;
502}
503
504bool PPCRegisterInfo::requiresVirtualBaseRegisters(
505 const MachineFunction &MF) const {
506 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
507 // Do not use virtual base registers when ROP protection is turned on.
508 // Virtual base registers break the layout of the local variable space and may
509 // push the ROP Hash location past the 512 byte range of the ROP store
510 // instruction.
511 return !Subtarget.hasROPProtect();
512}
513
514bool PPCRegisterInfo::isCallerPreservedPhysReg(MCRegister PhysReg,
515 const MachineFunction &MF) const {
516 assert(PhysReg.isPhysical());
517 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
518 const MachineFrameInfo &MFI = MF.getFrameInfo();
519
520 if (!Subtarget.is64BitELFABI() && !Subtarget.isAIXABI())
521 return false;
522 if (PhysReg == Subtarget.getTOCPointerRegister())
523 // X2/R2 is guaranteed to be preserved within a function if it is reserved.
524 // The reason it's reserved is that it's the TOC pointer (and the function
525 // uses the TOC). In functions where it isn't reserved (i.e. leaf functions
526 // with no TOC access), we can't claim that it is preserved.
527 return (getReservedRegs(MF).test(Idx: PhysReg));
528 if (StackPtrConst && PhysReg == Subtarget.getStackPointerRegister() &&
529 !MFI.hasVarSizedObjects() && !MFI.hasOpaqueSPAdjustment())
530 // The value of the stack pointer does not change within a function after
531 // the prologue and before the epilogue if there are no dynamic allocations
532 // and no inline asm which clobbers X1/R1.
533 return true;
534 return false;
535}
536
537bool PPCRegisterInfo::getRegAllocationHints(Register VirtReg,
538 ArrayRef<MCPhysReg> Order,
539 SmallVectorImpl<MCPhysReg> &Hints,
540 const MachineFunction &MF,
541 const VirtRegMap *VRM,
542 const LiveRegMatrix *Matrix) const {
543 const MachineRegisterInfo *MRI = &MF.getRegInfo();
544
545 // Call the base implementation first to set any hints based on the usual
546 // heuristics and decide what the return value should be. We want to return
547 // the same value returned by the base implementation. If the base
548 // implementation decides to return true and force the allocation then we
549 // will leave it as such. On the other hand if the base implementation
550 // decides to return false the following code will not force the allocation
551 // as we are just looking to provide a hint.
552 bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
553 VirtReg, Order, Hints, MF, VRM, Matrix);
554
555 // Don't use the allocation hints for ISAFuture.
556 // The WACC registers used in ISAFuture are unlike the ACC registers on
557 // Power 10 and so this logic to register allocation hints does not apply.
558 if (MF.getSubtarget<PPCSubtarget>().isISAFuture())
559 return BaseImplRetVal;
560
561 // We are interested in instructions that copy values to ACC/UACC.
562 // The copy into UACC will be simply a COPY to a subreg so we
563 // want to allocate the corresponding physical subreg for the source.
564 // The copy into ACC will be a BUILD_UACC so we want to allocate
565 // the same number UACC for the source.
566 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg: VirtReg);
567 for (MachineInstr &Use : MRI->reg_nodbg_instructions(Reg: VirtReg)) {
568 const MachineOperand *ResultOp = nullptr;
569 Register ResultReg;
570 switch (Use.getOpcode()) {
571 case TargetOpcode::COPY: {
572 ResultOp = &Use.getOperand(i: 0);
573 ResultReg = ResultOp->getReg();
574 if (ResultReg.isVirtual() &&
575 MRI->getRegClass(Reg: ResultReg)->contains(Reg: PPC::UACC0) &&
576 VRM->hasPhys(virtReg: ResultReg)) {
577 Register UACCPhys = VRM->getPhys(virtReg: ResultReg);
578 Register HintReg;
579 if (RegClass->contains(Reg: PPC::VSRp0)) {
580 HintReg = getSubReg(Reg: UACCPhys, Idx: ResultOp->getSubReg());
581 // Ensure that the hint is a VSRp register.
582 if (HintReg >= PPC::VSRp0 && HintReg <= PPC::VSRp31)
583 Hints.push_back(Elt: HintReg);
584 } else if (RegClass->contains(Reg: PPC::ACC0)) {
585 HintReg = PPC::ACC0 + (UACCPhys - PPC::UACC0);
586 if (HintReg >= PPC::ACC0 && HintReg <= PPC::ACC7)
587 Hints.push_back(Elt: HintReg);
588 }
589 }
590 break;
591 }
592 case PPC::BUILD_UACC: {
593 ResultOp = &Use.getOperand(i: 0);
594 ResultReg = ResultOp->getReg();
595 if (MRI->getRegClass(Reg: ResultReg)->contains(Reg: PPC::ACC0) &&
596 VRM->hasPhys(virtReg: ResultReg)) {
597 Register ACCPhys = VRM->getPhys(virtReg: ResultReg);
598 assert((ACCPhys >= PPC::ACC0 && ACCPhys <= PPC::ACC7) &&
599 "Expecting an ACC register for BUILD_UACC.");
600 Register HintReg = PPC::UACC0 + (ACCPhys - PPC::ACC0);
601 Hints.push_back(Elt: HintReg);
602 }
603 break;
604 }
605 }
606 }
607 return BaseImplRetVal;
608}
609
610const TargetRegisterClass *
611PPCRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
612 if (RC == &PPC::CARRYRCRegClass)
613 return TM.isPPC64() ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
614 return RC;
615}
616
617unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
618 MachineFunction &MF) const {
619 const PPCFrameLowering *TFI = getFrameLowering(MF);
620 const unsigned DefaultSafety = 1;
621
622 switch (RC->getID()) {
623 default:
624 return 0;
625 case PPC::G8RC_NOX0RegClassID:
626 case PPC::GPRC_NOR0RegClassID:
627 case PPC::SPERCRegClassID:
628 case PPC::G8RCRegClassID:
629 case PPC::GPRCRegClassID: {
630 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
631 return 32 - FP - DefaultSafety;
632 }
633 case PPC::F4RCRegClassID:
634 case PPC::F8RCRegClassID:
635 case PPC::VSLRCRegClassID:
636 return 32 - DefaultSafety;
637 case PPC::VFRCRegClassID:
638 case PPC::VRRCRegClassID: {
639 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
640 // Vector registers VR20-VR31 are reserved and cannot be used in the default
641 // Altivec ABI on AIX.
642 if (!Subtarget.isAIXExtendedAltivecABI() && Subtarget.isAIXABI())
643 return 20 - DefaultSafety;
644 }
645 return 32 - DefaultSafety;
646 case PPC::VSFRCRegClassID:
647 case PPC::VSSRCRegClassID:
648 case PPC::VSRCRegClassID: {
649 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
650 if (!Subtarget.isAIXExtendedAltivecABI() && Subtarget.isAIXABI())
651 // Vector registers VR20-VR31 are reserved and cannot be used in the
652 // default Altivec ABI on AIX.
653 return 52 - DefaultSafety;
654 }
655 return 64 - DefaultSafety;
656 case PPC::CRRCRegClassID:
657 return 8 - DefaultSafety;
658 }
659}
660
661const TargetRegisterClass *
662PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
663 const MachineFunction &MF) const {
664 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
665 const auto *DefaultSuperclass =
666 TargetRegisterInfo::getLargestLegalSuperClass(RC, MF);
667 if (Subtarget.hasVSX()) {
668 // With VSX, we can inflate various sub-register classes to the full VSX
669 // register set.
670
671 // For Power9 we allow the user to enable GPR to vector spills.
672 // FIXME: Currently limited to spilling GP8RC. A follow on patch will add
673 // support to spill GPRC.
674 if (Subtarget.isELFv2ABI() || Subtarget.isAIXABI()) {
675 if (Subtarget.hasP9Vector() && EnableGPRToVecSpills &&
676 RC == &PPC::G8RCRegClass) {
677 InflateGP8RC++;
678 return &PPC::SPILLTOVSRRCRegClass;
679 }
680 if (RC == &PPC::GPRCRegClass && EnableGPRToVecSpills)
681 InflateGPRC++;
682 }
683
684 for (unsigned SuperID : RC->superclasses()) {
685 if (getRegSizeInBits(RC: *getRegClass(i: SuperID)) != getRegSizeInBits(RC: *RC))
686 continue;
687
688 switch (SuperID) {
689 case PPC::VSSRCRegClassID:
690 return Subtarget.hasP8Vector() ? getRegClass(i: SuperID)
691 : DefaultSuperclass;
692 case PPC::VSFRCRegClassID:
693 case PPC::VSRCRegClassID:
694 return getRegClass(i: SuperID);
695 case PPC::VSRpRCRegClassID:
696 return Subtarget.pairedVectorMemops() ? getRegClass(i: SuperID)
697 : DefaultSuperclass;
698 case PPC::ACCRCRegClassID:
699 case PPC::UACCRCRegClassID:
700 return Subtarget.hasMMA() ? getRegClass(i: SuperID) : DefaultSuperclass;
701 }
702 }
703 }
704
705 return DefaultSuperclass;
706}
707
708//===----------------------------------------------------------------------===//
709// Stack Frame Processing methods
710//===----------------------------------------------------------------------===//
711
712/// lowerDynamicAlloc - Generate the code for allocating an object in the
713/// current frame. The sequence of code will be in the general form
714///
715/// addi R0, SP, \#frameSize ; get the address of the previous frame
716/// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
717/// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
718///
719void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
720 // Get the instruction.
721 MachineInstr &MI = *II;
722 // Get the instruction's basic block.
723 MachineBasicBlock &MBB = *MI.getParent();
724 // Get the basic block's function.
725 MachineFunction &MF = *MBB.getParent();
726 // Get the frame info.
727 MachineFrameInfo &MFI = MF.getFrameInfo();
728 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
729 // Get the instruction info.
730 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
731 // Determine whether 64-bit pointers are used.
732 bool LP64 = TM.isPPC64();
733 DebugLoc dl = MI.getDebugLoc();
734
735 // Get the maximum call stack size.
736 unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
737 Align MaxAlign = MFI.getMaxAlign();
738 assert(isAligned(MaxAlign, maxCallFrameSize) &&
739 "Maximum call-frame size not sufficiently aligned");
740 (void)MaxAlign;
741
742 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
743 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
744 Register Reg = MF.getRegInfo().createVirtualRegister(RegClass: LP64 ? G8RC : GPRC);
745 bool KillNegSizeReg = MI.getOperand(i: 1).isKill();
746 Register NegSizeReg = MI.getOperand(i: 1).getReg();
747
748 prepareDynamicAlloca(II, NegSizeReg, KillNegSizeReg, FramePointer&: Reg);
749 // Grow the stack and update the stack pointer link, then determine the
750 // address of new allocated space.
751 if (LP64) {
752 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: PPC::STDUX), DestReg: PPC::X1)
753 .addReg(RegNo: Reg, Flags: RegState::Kill)
754 .addReg(RegNo: PPC::X1)
755 .addReg(RegNo: NegSizeReg, Flags: getKillRegState(B: KillNegSizeReg));
756 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: PPC::ADDI8), DestReg: MI.getOperand(i: 0).getReg())
757 .addReg(RegNo: PPC::X1)
758 .addImm(Val: maxCallFrameSize);
759 } else {
760 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: PPC::STWUX), DestReg: PPC::R1)
761 .addReg(RegNo: Reg, Flags: RegState::Kill)
762 .addReg(RegNo: PPC::R1)
763 .addReg(RegNo: NegSizeReg, Flags: getKillRegState(B: KillNegSizeReg));
764 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: PPC::ADDI), DestReg: MI.getOperand(i: 0).getReg())
765 .addReg(RegNo: PPC::R1)
766 .addImm(Val: maxCallFrameSize);
767 }
768
769 // Discard the DYNALLOC instruction.
770 MBB.erase(I: II);
771}
772
773/// To accomplish dynamic stack allocation, we have to calculate exact size
774/// subtracted from the stack pointer according alignment information and get
775/// previous frame pointer.
776void PPCRegisterInfo::prepareDynamicAlloca(MachineBasicBlock::iterator II,
777 Register &NegSizeReg,
778 bool &KillNegSizeReg,
779 Register &FramePointer) const {
780 // Get the instruction.
781 MachineInstr &MI = *II;
782 // Get the instruction's basic block.
783 MachineBasicBlock &MBB = *MI.getParent();
784 // Get the basic block's function.
785 MachineFunction &MF = *MBB.getParent();
786 // Get the frame info.
787 MachineFrameInfo &MFI = MF.getFrameInfo();
788 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
789 // Get the instruction info.
790 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
791 // Determine whether 64-bit pointers are used.
792 bool LP64 = TM.isPPC64();
793 DebugLoc dl = MI.getDebugLoc();
794 // Get the total frame size.
795 unsigned FrameSize = MFI.getStackSize();
796
797 // Get stack alignments.
798 const PPCFrameLowering *TFI = getFrameLowering(MF);
799 Align TargetAlign = TFI->getStackAlign();
800 Align MaxAlign = MFI.getMaxAlign();
801
802 // Determine the previous frame's address. If FrameSize can't be
803 // represented as 16 bits or we need special alignment, then we load the
804 // previous frame's address from 0(SP). Why not do an addis of the hi?
805 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
806 // Constructing the constant and adding would take 3 instructions.
807 // Fortunately, a frame greater than 32K is rare.
808 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
809 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
810
811 if (MaxAlign < TargetAlign && isInt<16>(x: FrameSize)) {
812 if (LP64)
813 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: PPC::ADDI8), DestReg: FramePointer)
814 .addReg(RegNo: PPC::X31)
815 .addImm(Val: FrameSize);
816 else
817 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: PPC::ADDI), DestReg: FramePointer)
818 .addReg(RegNo: PPC::R31)
819 .addImm(Val: FrameSize);
820 } else if (LP64) {
821 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: PPC::LD), DestReg: FramePointer)
822 .addImm(Val: 0)
823 .addReg(RegNo: PPC::X1);
824 } else {
825 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: PPC::LWZ), DestReg: FramePointer)
826 .addImm(Val: 0)
827 .addReg(RegNo: PPC::R1);
828 }
829 // Determine the actual NegSizeReg according to alignment info.
830 if (LP64) {
831 if (MaxAlign > TargetAlign) {
832 unsigned UnalNegSizeReg = NegSizeReg;
833 NegSizeReg = MF.getRegInfo().createVirtualRegister(RegClass: G8RC);
834
835 // Unfortunately, there is no andi, only andi., and we can't insert that
836 // here because we might clobber cr0 while it is live.
837 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: PPC::LI8), DestReg: NegSizeReg)
838 .addImm(Val: ~(MaxAlign.value() - 1));
839
840 unsigned NegSizeReg1 = NegSizeReg;
841 NegSizeReg = MF.getRegInfo().createVirtualRegister(RegClass: G8RC);
842 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: PPC::AND8), DestReg: NegSizeReg)
843 .addReg(RegNo: UnalNegSizeReg, Flags: getKillRegState(B: KillNegSizeReg))
844 .addReg(RegNo: NegSizeReg1, Flags: RegState::Kill);
845 KillNegSizeReg = true;
846 }
847 } else {
848 if (MaxAlign > TargetAlign) {
849 unsigned UnalNegSizeReg = NegSizeReg;
850 NegSizeReg = MF.getRegInfo().createVirtualRegister(RegClass: GPRC);
851
852 // Unfortunately, there is no andi, only andi., and we can't insert that
853 // here because we might clobber cr0 while it is live.
854 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: PPC::LI), DestReg: NegSizeReg)
855 .addImm(Val: ~(MaxAlign.value() - 1));
856
857 unsigned NegSizeReg1 = NegSizeReg;
858 NegSizeReg = MF.getRegInfo().createVirtualRegister(RegClass: GPRC);
859 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: PPC::AND), DestReg: NegSizeReg)
860 .addReg(RegNo: UnalNegSizeReg, Flags: getKillRegState(B: KillNegSizeReg))
861 .addReg(RegNo: NegSizeReg1, Flags: RegState::Kill);
862 KillNegSizeReg = true;
863 }
864 }
865}
866
867void PPCRegisterInfo::lowerPrepareProbedAlloca(
868 MachineBasicBlock::iterator II) const {
869 MachineInstr &MI = *II;
870 // Get the instruction's basic block.
871 MachineBasicBlock &MBB = *MI.getParent();
872 // Get the basic block's function.
873 MachineFunction &MF = *MBB.getParent();
874 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
875 // Get the instruction info.
876 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
877 // Determine whether 64-bit pointers are used.
878 bool LP64 = TM.isPPC64();
879 DebugLoc dl = MI.getDebugLoc();
880 Register FramePointer = MI.getOperand(i: 0).getReg();
881 const Register ActualNegSizeReg = MI.getOperand(i: 1).getReg();
882 bool KillNegSizeReg = MI.getOperand(i: 2).isKill();
883 Register NegSizeReg = MI.getOperand(i: 2).getReg();
884 const MCInstrDesc &CopyInst = TII.get(Opcode: LP64 ? PPC::OR8 : PPC::OR);
885 // RegAllocator might allocate FramePointer and NegSizeReg in the same phyreg.
886 if (FramePointer == NegSizeReg) {
887 assert(KillNegSizeReg && "FramePointer is a def and NegSizeReg is an use, "
888 "NegSizeReg should be killed");
889 // FramePointer is clobbered earlier than the use of NegSizeReg in
890 // prepareDynamicAlloca, save NegSizeReg in ActualNegSizeReg to avoid
891 // misuse.
892 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: CopyInst, DestReg: ActualNegSizeReg)
893 .addReg(RegNo: NegSizeReg)
894 .addReg(RegNo: NegSizeReg);
895 NegSizeReg = ActualNegSizeReg;
896 KillNegSizeReg = false;
897 }
898 prepareDynamicAlloca(II, NegSizeReg, KillNegSizeReg, FramePointer);
899 // NegSizeReg might be updated in prepareDynamicAlloca if MaxAlign >
900 // TargetAlign.
901 if (NegSizeReg != ActualNegSizeReg)
902 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: CopyInst, DestReg: ActualNegSizeReg)
903 .addReg(RegNo: NegSizeReg)
904 .addReg(RegNo: NegSizeReg);
905 MBB.erase(I: II);
906}
907
908void PPCRegisterInfo::lowerDynamicAreaOffset(
909 MachineBasicBlock::iterator II) const {
910 // Get the instruction.
911 MachineInstr &MI = *II;
912 // Get the instruction's basic block.
913 MachineBasicBlock &MBB = *MI.getParent();
914 // Get the basic block's function.
915 MachineFunction &MF = *MBB.getParent();
916 // Get the frame info.
917 MachineFrameInfo &MFI = MF.getFrameInfo();
918 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
919 // Get the instruction info.
920 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
921
922 unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
923 bool is64Bit = TM.isPPC64();
924 DebugLoc dl = MI.getDebugLoc();
925 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: is64Bit ? PPC::LI8 : PPC::LI),
926 DestReg: MI.getOperand(i: 0).getReg())
927 .addImm(Val: maxCallFrameSize);
928 MBB.erase(I: II);
929}
930
931/// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
932/// reserving a whole register (R0), we scrounge for one here. This generates
933/// code like this:
934///
935/// mfcr rA ; Move the conditional register into GPR rA.
936/// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
937/// stw rA, FI ; Store rA to the frame.
938///
939void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
940 unsigned FrameIndex) const {
941 // Get the instruction.
942 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
943 // Get the instruction's basic block.
944 MachineBasicBlock &MBB = *MI.getParent();
945 MachineFunction &MF = *MBB.getParent();
946 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
947 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
948 DebugLoc dl = MI.getDebugLoc();
949
950 bool LP64 = TM.isPPC64();
951 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
952 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
953
954 Register Reg = MF.getRegInfo().createVirtualRegister(RegClass: LP64 ? G8RC : GPRC);
955 Register SrcReg = MI.getOperand(i: 0).getReg();
956
957 // We need to store the CR in the low 4-bits of the saved value. First, issue
958 // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg.
959 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), DestReg: Reg)
960 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: MI.getOperand(i: 0).isKill()));
961
962 // If the saved register wasn't CR0, shift the bits left so that they are in
963 // CR0's slot.
964 if (SrcReg != PPC::CR0) {
965 Register Reg1 = Reg;
966 Reg = MF.getRegInfo().createVirtualRegister(RegClass: LP64 ? G8RC : GPRC);
967
968 // rlwinm rA, rA, ShiftBits, 0, 31.
969 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::RLWINM8 : PPC::RLWINM), DestReg: Reg)
970 .addReg(RegNo: Reg1, Flags: RegState::Kill)
971 .addImm(Val: getEncodingValue(Reg: SrcReg) * 4)
972 .addImm(Val: 0)
973 .addImm(Val: 31);
974 }
975
976 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::STW8 : PPC::STW))
977 .addReg(RegNo: Reg, Flags: RegState::Kill),
978 FI: FrameIndex);
979
980 // Discard the pseudo instruction.
981 MBB.erase(I: II);
982}
983
984void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
985 unsigned FrameIndex) const {
986 // Get the instruction.
987 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
988 // Get the instruction's basic block.
989 MachineBasicBlock &MBB = *MI.getParent();
990 MachineFunction &MF = *MBB.getParent();
991 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
992 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
993 DebugLoc dl = MI.getDebugLoc();
994
995 bool LP64 = TM.isPPC64();
996 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
997 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
998
999 Register Reg = MF.getRegInfo().createVirtualRegister(RegClass: LP64 ? G8RC : GPRC);
1000 Register DestReg = MI.getOperand(i: 0).getReg();
1001 assert(MI.definesRegister(DestReg, /*TRI=*/nullptr) &&
1002 "RESTORE_CR does not define its destination");
1003
1004 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::LWZ8 : PPC::LWZ),
1005 DestReg: Reg), FI: FrameIndex);
1006
1007 // If the reloaded register isn't CR0, shift the bits right so that they are
1008 // in the right CR's slot.
1009 if (DestReg != PPC::CR0) {
1010 Register Reg1 = Reg;
1011 Reg = MF.getRegInfo().createVirtualRegister(RegClass: LP64 ? G8RC : GPRC);
1012
1013 unsigned ShiftBits = getEncodingValue(Reg: DestReg)*4;
1014 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
1015 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::RLWINM8 : PPC::RLWINM), DestReg: Reg)
1016 .addReg(RegNo: Reg1, Flags: RegState::Kill).addImm(Val: 32-ShiftBits).addImm(Val: 0)
1017 .addImm(Val: 31);
1018 }
1019
1020 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg)
1021 .addReg(RegNo: Reg, Flags: RegState::Kill);
1022
1023 // Discard the pseudo instruction.
1024 MBB.erase(I: II);
1025}
1026
1027void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II,
1028 unsigned FrameIndex) const {
1029 // Get the instruction.
1030 MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset>
1031 // Get the instruction's basic block.
1032 MachineBasicBlock &MBB = *MI.getParent();
1033 MachineFunction &MF = *MBB.getParent();
1034 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1035 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1036 const TargetRegisterInfo* TRI = Subtarget.getRegisterInfo();
1037 DebugLoc dl = MI.getDebugLoc();
1038
1039 bool LP64 = TM.isPPC64();
1040 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1041 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1042
1043 Register Reg = MF.getRegInfo().createVirtualRegister(RegClass: LP64 ? G8RC : GPRC);
1044 Register SrcReg = MI.getOperand(i: 0).getReg();
1045
1046 // Search up the BB to find the definition of the CR bit.
1047 MachineBasicBlock::reverse_iterator Ins = MI;
1048 MachineBasicBlock::reverse_iterator Rend = MBB.rend();
1049 ++Ins;
1050 unsigned CRBitSpillDistance = 0;
1051 bool SeenUse = false;
1052 for (; Ins != Rend; ++Ins) {
1053 // Definition found.
1054 if (Ins->modifiesRegister(Reg: SrcReg, TRI))
1055 break;
1056 // Use found.
1057 if (Ins->readsRegister(Reg: SrcReg, TRI))
1058 SeenUse = true;
1059 // Unable to find CR bit definition within maximum search distance.
1060 if (CRBitSpillDistance == MaxCRBitSpillDist) {
1061 Ins = MI;
1062 break;
1063 }
1064 // Skip debug instructions when counting CR bit spill distance.
1065 if (!Ins->isDebugInstr())
1066 CRBitSpillDistance++;
1067 }
1068
1069 // Unable to find the definition of the CR bit in the MBB.
1070 if (Ins == MBB.rend())
1071 Ins = MI;
1072
1073 bool SpillsKnownBit = false;
1074 // There is no need to extract the CR bit if its value is already known.
1075 switch (Ins->getOpcode()) {
1076 case PPC::CRUNSET:
1077 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::LI8 : PPC::LI), DestReg: Reg)
1078 .addImm(Val: 0);
1079 SpillsKnownBit = true;
1080 break;
1081 case PPC::CRSET:
1082 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::LIS8 : PPC::LIS), DestReg: Reg)
1083 .addImm(Val: -32768);
1084 SpillsKnownBit = true;
1085 break;
1086 default:
1087 // When spilling a CR bit, the super register may not be explicitly defined
1088 // (i.e. it can be defined by a CR-logical that only defines the subreg) so
1089 // we state that the CR field is undef. Also, in order to preserve the kill
1090 // flag on the CR bit, we add it as an implicit use.
1091
1092 // On Power10, we can use SETNBC to spill all CR bits. SETNBC will set all
1093 // bits (specifically, it produces a -1 if the CR bit is set). Ultimately,
1094 // the bit that is of importance to us is bit 32 (bit 0 of a 32-bit
1095 // register), and SETNBC will set this.
1096 if (Subtarget.isISA3_1()) {
1097 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::SETNBC8 : PPC::SETNBC), DestReg: Reg)
1098 .addReg(RegNo: SrcReg, Flags: RegState::Undef)
1099 .addReg(RegNo: SrcReg, Flags: RegState::Implicit |
1100 getKillRegState(B: MI.getOperand(i: 0).isKill()));
1101 break;
1102 }
1103
1104 // On Power9, we can use SETB to extract the LT bit. This only works for
1105 // the LT bit since SETB produces -1/1/0 for LT/GT/<neither>. So the value
1106 // of the bit we care about (32-bit sign bit) will be set to the value of
1107 // the LT bit (regardless of the other bits in the CR field).
1108 if (Subtarget.isISA3_0()) {
1109 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR1LT ||
1110 SrcReg == PPC::CR2LT || SrcReg == PPC::CR3LT ||
1111 SrcReg == PPC::CR4LT || SrcReg == PPC::CR5LT ||
1112 SrcReg == PPC::CR6LT || SrcReg == PPC::CR7LT) {
1113 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::SETB8 : PPC::SETB), DestReg: Reg)
1114 .addReg(RegNo: getCRFromCRBit(SrcReg), Flags: RegState::Undef)
1115 .addReg(RegNo: SrcReg, Flags: RegState::Implicit |
1116 getKillRegState(B: MI.getOperand(i: 0).isKill()));
1117 break;
1118 }
1119 }
1120
1121 // We need to move the CR field that contains the CR bit we are spilling.
1122 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), DestReg: Reg)
1123 .addReg(RegNo: getCRFromCRBit(SrcReg), Flags: RegState::Undef)
1124 .addReg(RegNo: SrcReg,
1125 Flags: RegState::Implicit | getKillRegState(B: MI.getOperand(i: 0).isKill()));
1126
1127 // If the saved register wasn't CR0LT, shift the bits left so that the bit
1128 // to store is the first one. Mask all but that bit.
1129 Register Reg1 = Reg;
1130 Reg = MF.getRegInfo().createVirtualRegister(RegClass: LP64 ? G8RC : GPRC);
1131
1132 // rlwinm rA, rA, ShiftBits, 0, 0.
1133 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::RLWINM8 : PPC::RLWINM), DestReg: Reg)
1134 .addReg(RegNo: Reg1, Flags: RegState::Kill)
1135 .addImm(Val: getEncodingValue(Reg: SrcReg))
1136 .addImm(Val: 0).addImm(Val: 0);
1137 }
1138 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::STW8 : PPC::STW))
1139 .addReg(RegNo: Reg, Flags: RegState::Kill),
1140 FI: FrameIndex);
1141
1142 bool KillsCRBit = MI.killsRegister(Reg: SrcReg, TRI);
1143 // Discard the pseudo instruction.
1144 MBB.erase(I: II);
1145 if (SpillsKnownBit && KillsCRBit && !SeenUse) {
1146 Ins->setDesc(TII.get(Opcode: PPC::UNENCODED_NOP));
1147 Ins->removeOperand(OpNo: 0);
1148 }
1149}
1150
1151void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II,
1152 unsigned FrameIndex) const {
1153 // Get the instruction.
1154 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset>
1155 // Get the instruction's basic block.
1156 MachineBasicBlock &MBB = *MI.getParent();
1157 MachineFunction &MF = *MBB.getParent();
1158 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1159 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1160 DebugLoc dl = MI.getDebugLoc();
1161
1162 bool LP64 = TM.isPPC64();
1163 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1164 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1165
1166 Register Reg = MF.getRegInfo().createVirtualRegister(RegClass: LP64 ? G8RC : GPRC);
1167 Register DestReg = MI.getOperand(i: 0).getReg();
1168 assert(MI.definesRegister(DestReg, /*TRI=*/nullptr) &&
1169 "RESTORE_CRBIT does not define its destination");
1170
1171 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::LWZ8 : PPC::LWZ),
1172 DestReg: Reg), FI: FrameIndex);
1173
1174 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: TargetOpcode::IMPLICIT_DEF), DestReg);
1175
1176 Register RegO = MF.getRegInfo().createVirtualRegister(RegClass: LP64 ? G8RC : GPRC);
1177 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), DestReg: RegO)
1178 .addReg(RegNo: getCRFromCRBit(SrcReg: DestReg));
1179
1180 unsigned ShiftBits = getEncodingValue(Reg: DestReg);
1181 // rlwimi r11, r10, 32-ShiftBits, ..., ...
1182 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), DestReg: RegO)
1183 .addReg(RegNo: RegO, Flags: RegState::Kill)
1184 .addReg(RegNo: Reg, Flags: RegState::Kill)
1185 .addImm(Val: ShiftBits ? 32 - ShiftBits : 0)
1186 .addImm(Val: ShiftBits)
1187 .addImm(Val: ShiftBits);
1188
1189 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::MTOCRF8 : PPC::MTOCRF),
1190 DestReg: getCRFromCRBit(SrcReg: DestReg))
1191 .addReg(RegNo: RegO, Flags: RegState::Kill)
1192 // Make sure we have a use dependency all the way through this
1193 // sequence of instructions. We can't have the other bits in the CR
1194 // modified in between the mfocrf and the mtocrf.
1195 .addReg(RegNo: getCRFromCRBit(SrcReg: DestReg), Flags: RegState::Implicit);
1196
1197 // Discard the pseudo instruction.
1198 MBB.erase(I: II);
1199}
1200
1201void PPCRegisterInfo::emitAccCopyInfo(MachineBasicBlock &MBB,
1202 MCRegister DestReg, MCRegister SrcReg) {
1203#ifdef NDEBUG
1204 return;
1205#else
1206 if (ReportAccMoves) {
1207 std::string Dest = PPC::ACCRCRegClass.contains(DestReg) ? "acc" : "uacc";
1208 std::string Src = PPC::ACCRCRegClass.contains(SrcReg) ? "acc" : "uacc";
1209 dbgs() << "Emitting copy from " << Src << " to " << Dest << ":\n";
1210 MBB.dump();
1211 }
1212#endif
1213}
1214
1215static void emitAccSpillRestoreInfo(MachineBasicBlock &MBB, bool IsPrimed,
1216 bool IsRestore) {
1217#ifdef NDEBUG
1218 return;
1219#else
1220 if (ReportAccMoves) {
1221 dbgs() << "Emitting " << (IsPrimed ? "acc" : "uacc") << " register "
1222 << (IsRestore ? "restore" : "spill") << ":\n";
1223 MBB.dump();
1224 }
1225#endif
1226}
1227
1228void PPCRegisterInfo::spillRegPair(MachineBasicBlock &MBB,
1229 MachineBasicBlock::iterator II, DebugLoc DL,
1230 const TargetInstrInfo &TII,
1231 unsigned FrameIndex, bool IsLittleEndian,
1232 bool IsKilled, Register Reg,
1233 int Offset) const {
1234
1235 // This function does not support virtual registers.
1236 assert(!Reg.isVirtual() &&
1237 "Spilling register pairs does not support virtual registers.");
1238
1239 addFrameReference(
1240 MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::STXV))
1241 .addReg(RegNo: TargetRegisterInfo::getSubReg(Reg, Idx: PPC::sub_vsx0),
1242 Flags: getKillRegState(B: IsKilled)),
1243 FI: FrameIndex, Offset);
1244
1245 addFrameReference(
1246 MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::STXV))
1247 .addReg(RegNo: TargetRegisterInfo::getSubReg(Reg, Idx: PPC::sub_vsx1),
1248 Flags: getKillRegState(B: IsKilled)),
1249 FI: FrameIndex, Offset: IsLittleEndian ? Offset - 16 : Offset + 16);
1250}
1251
1252/// Remove any STXVP[X] instructions and split them out into a pair of
1253/// STXV[X] instructions if --disable-auto-paired-vec-st is specified on
1254/// the command line.
1255void PPCRegisterInfo::lowerOctWordSpilling(MachineBasicBlock::iterator II,
1256 unsigned FrameIndex) const {
1257 assert(DisableAutoPairedVecSt &&
1258 "Expecting to do this only if paired vector stores are disabled.");
1259 MachineInstr &MI = *II; // STXVP <SrcReg>, <offset>
1260 MachineBasicBlock &MBB = *MI.getParent();
1261 MachineFunction &MF = *MBB.getParent();
1262 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1263 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1264 DebugLoc DL = MI.getDebugLoc();
1265 Register SrcReg = MI.getOperand(i: 0).getReg();
1266 bool IsLittleEndian = Subtarget.isLittleEndian();
1267 bool IsKilled = MI.getOperand(i: 0).isKill();
1268
1269 spillRegPair(MBB, II, DL, TII, FrameIndex, IsLittleEndian, IsKilled, Reg: SrcReg,
1270 Offset: IsLittleEndian ? 16 : 0);
1271
1272 // Discard the original instruction.
1273 MBB.erase(I: II);
1274}
1275
1276static void emitWAccSpillRestoreInfo(MachineBasicBlock &MBB, bool IsRestore) {
1277#ifdef NDEBUG
1278 return;
1279#else
1280 if (ReportAccMoves) {
1281 dbgs() << "Emitting wacc register " << (IsRestore ? "restore" : "spill")
1282 << ":\n";
1283 MBB.dump();
1284 }
1285#endif
1286}
1287
1288/// lowerACCSpilling - Generate the code for spilling the accumulator register.
1289/// Similarly to other spills/reloads that use pseudo-ops, we do not actually
1290/// eliminate the FrameIndex here nor compute the stack offset. We simply
1291/// create a real instruction with an FI and rely on eliminateFrameIndex to
1292/// handle the FI elimination.
1293void PPCRegisterInfo::lowerACCSpilling(MachineBasicBlock::iterator II,
1294 unsigned FrameIndex) const {
1295 MachineInstr &MI = *II; // SPILL_ACC <SrcReg>, <offset>
1296 MachineBasicBlock &MBB = *MI.getParent();
1297 MachineFunction &MF = *MBB.getParent();
1298 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1299 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1300 DebugLoc DL = MI.getDebugLoc();
1301 Register SrcReg = MI.getOperand(i: 0).getReg();
1302 bool IsKilled = MI.getOperand(i: 0).isKill();
1303
1304 bool IsPrimed = PPC::ACCRCRegClass.contains(Reg: SrcReg);
1305 bool IsLittleEndian = Subtarget.isLittleEndian();
1306
1307 emitAccSpillRestoreInfo(MBB, IsPrimed, IsRestore: false);
1308
1309 // De-prime the register being spilled, create two stores for the pair
1310 // subregisters accounting for endianness and then re-prime the register if
1311 // it isn't killed. This uses the Offset parameter to addFrameReference() to
1312 // adjust the offset of the store that is within the 64-byte stack slot.
1313 if (IsPrimed)
1314 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::XXMFACC), DestReg: SrcReg).addReg(RegNo: SrcReg);
1315 if (DisableAutoPairedVecSt) {
1316 spillRegPair(MBB, II, DL, TII, FrameIndex, IsLittleEndian, IsKilled,
1317 Reg: TargetRegisterInfo::getSubReg(Reg: SrcReg, Idx: PPC::sub_pair0),
1318 Offset: IsLittleEndian ? 48 : 0);
1319 spillRegPair(MBB, II, DL, TII, FrameIndex, IsLittleEndian, IsKilled,
1320 Reg: TargetRegisterInfo::getSubReg(Reg: SrcReg, Idx: PPC::sub_pair1),
1321 Offset: IsLittleEndian ? 16 : 32);
1322 } else {
1323 addFrameReference(
1324 MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::STXVP))
1325 .addReg(RegNo: TargetRegisterInfo::getSubReg(Reg: SrcReg, Idx: PPC::sub_pair0),
1326 Flags: getKillRegState(B: IsKilled)),
1327 FI: FrameIndex, Offset: IsLittleEndian ? 32 : 0);
1328 addFrameReference(
1329 MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::STXVP))
1330 .addReg(RegNo: TargetRegisterInfo::getSubReg(Reg: SrcReg, Idx: PPC::sub_pair1),
1331 Flags: getKillRegState(B: IsKilled)),
1332 FI: FrameIndex, Offset: IsLittleEndian ? 0 : 32);
1333 }
1334 if (IsPrimed && !IsKilled)
1335 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::XXMTACC), DestReg: SrcReg).addReg(RegNo: SrcReg);
1336
1337 // Discard the pseudo instruction.
1338 MBB.erase(I: II);
1339}
1340
1341/// lowerACCRestore - Generate the code to restore the accumulator register.
1342void PPCRegisterInfo::lowerACCRestore(MachineBasicBlock::iterator II,
1343 unsigned FrameIndex) const {
1344 MachineInstr &MI = *II; // <DestReg> = RESTORE_ACC <offset>
1345 MachineBasicBlock &MBB = *MI.getParent();
1346 MachineFunction &MF = *MBB.getParent();
1347 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1348 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1349 DebugLoc DL = MI.getDebugLoc();
1350
1351 Register DestReg = MI.getOperand(i: 0).getReg();
1352 assert(MI.definesRegister(DestReg, /*TRI=*/nullptr) &&
1353 "RESTORE_ACC does not define its destination");
1354
1355 bool IsPrimed = PPC::ACCRCRegClass.contains(Reg: DestReg);
1356 Register Reg =
1357 PPC::VSRp0 + (DestReg - (IsPrimed ? PPC::ACC0 : PPC::UACC0)) * 2;
1358 bool IsLittleEndian = Subtarget.isLittleEndian();
1359
1360 emitAccSpillRestoreInfo(MBB, IsPrimed, IsRestore: true);
1361
1362 // Create two loads for the pair subregisters accounting for endianness and
1363 // then prime the accumulator register being restored.
1364 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::LXVP), DestReg: Reg),
1365 FI: FrameIndex, Offset: IsLittleEndian ? 32 : 0);
1366 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::LXVP), DestReg: Reg + 1),
1367 FI: FrameIndex, Offset: IsLittleEndian ? 0 : 32);
1368 if (IsPrimed)
1369 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::XXMTACC), DestReg).addReg(RegNo: DestReg);
1370
1371 // Discard the pseudo instruction.
1372 MBB.erase(I: II);
1373}
1374
1375/// lowerWACCSpilling - Generate the code for spilling the wide accumulator
1376/// register.
1377void PPCRegisterInfo::lowerWACCSpilling(MachineBasicBlock::iterator II,
1378 unsigned FrameIndex) const {
1379 MachineInstr &MI = *II; // SPILL_WACC <SrcReg>, <offset>
1380 MachineBasicBlock &MBB = *MI.getParent();
1381 MachineFunction &MF = *MBB.getParent();
1382 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1383 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1384 DebugLoc DL = MI.getDebugLoc();
1385 bool IsLittleEndian = Subtarget.isLittleEndian();
1386
1387 emitWAccSpillRestoreInfo(MBB, IsRestore: false);
1388
1389 const TargetRegisterClass *RC = &PPC::VSRpRCRegClass;
1390 Register VSRpReg0 = MF.getRegInfo().createVirtualRegister(RegClass: RC);
1391 Register VSRpReg1 = MF.getRegInfo().createVirtualRegister(RegClass: RC);
1392 Register SrcReg = MI.getOperand(i: 0).getReg();
1393
1394 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::DMXXEXTFDMR512), DestReg: VSRpReg0)
1395 .addDef(RegNo: VSRpReg1)
1396 .addReg(RegNo: SrcReg);
1397
1398 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::STXVP))
1399 .addReg(RegNo: VSRpReg0, Flags: RegState::Kill),
1400 FI: FrameIndex, Offset: IsLittleEndian ? 32 : 0);
1401 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::STXVP))
1402 .addReg(RegNo: VSRpReg1, Flags: RegState::Kill),
1403 FI: FrameIndex, Offset: IsLittleEndian ? 0 : 32);
1404
1405 // Discard the pseudo instruction.
1406 MBB.erase(I: II);
1407}
1408
1409/// lowerWACCRestore - Generate the code to restore the wide accumulator
1410/// register.
1411void PPCRegisterInfo::lowerWACCRestore(MachineBasicBlock::iterator II,
1412 unsigned FrameIndex) const {
1413 MachineInstr &MI = *II; // <DestReg> = RESTORE_WACC <offset>
1414 MachineBasicBlock &MBB = *MI.getParent();
1415 MachineFunction &MF = *MBB.getParent();
1416 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1417 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1418 DebugLoc DL = MI.getDebugLoc();
1419 bool IsLittleEndian = Subtarget.isLittleEndian();
1420
1421 emitWAccSpillRestoreInfo(MBB, IsRestore: true);
1422
1423 const TargetRegisterClass *RC = &PPC::VSRpRCRegClass;
1424 Register VSRpReg0 = MF.getRegInfo().createVirtualRegister(RegClass: RC);
1425 Register VSRpReg1 = MF.getRegInfo().createVirtualRegister(RegClass: RC);
1426 Register DestReg = MI.getOperand(i: 0).getReg();
1427
1428 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::LXVP), DestReg: VSRpReg0),
1429 FI: FrameIndex, Offset: IsLittleEndian ? 32 : 0);
1430 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::LXVP), DestReg: VSRpReg1),
1431 FI: FrameIndex, Offset: IsLittleEndian ? 0 : 32);
1432
1433 // Kill VSRpReg0, VSRpReg1 (killedRegState::Killed)
1434 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::DMXXINSTDMR512), DestReg)
1435 .addReg(RegNo: VSRpReg0, Flags: RegState::Kill)
1436 .addReg(RegNo: VSRpReg1, Flags: RegState::Kill);
1437
1438 // Discard the pseudo instruction.
1439 MBB.erase(I: II);
1440}
1441
1442/// lowerQuadwordSpilling - Generate code to spill paired general register.
1443void PPCRegisterInfo::lowerQuadwordSpilling(MachineBasicBlock::iterator II,
1444 unsigned FrameIndex) const {
1445 MachineInstr &MI = *II;
1446 MachineBasicBlock &MBB = *MI.getParent();
1447 MachineFunction &MF = *MBB.getParent();
1448 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1449 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1450 DebugLoc DL = MI.getDebugLoc();
1451
1452 Register SrcReg = MI.getOperand(i: 0).getReg();
1453 bool IsKilled = MI.getOperand(i: 0).isKill();
1454
1455 Register Reg = PPC::X0 + (SrcReg - PPC::G8p0) * 2;
1456 bool IsLittleEndian = Subtarget.isLittleEndian();
1457
1458 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::STD))
1459 .addReg(RegNo: Reg, Flags: getKillRegState(B: IsKilled)),
1460 FI: FrameIndex, Offset: IsLittleEndian ? 8 : 0);
1461 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::STD))
1462 .addReg(RegNo: Reg + 1, Flags: getKillRegState(B: IsKilled)),
1463 FI: FrameIndex, Offset: IsLittleEndian ? 0 : 8);
1464
1465 // Discard the pseudo instruction.
1466 MBB.erase(I: II);
1467}
1468
1469/// lowerQuadwordRestore - Generate code to restore paired general register.
1470void PPCRegisterInfo::lowerQuadwordRestore(MachineBasicBlock::iterator II,
1471 unsigned FrameIndex) const {
1472 MachineInstr &MI = *II;
1473 MachineBasicBlock &MBB = *MI.getParent();
1474 MachineFunction &MF = *MBB.getParent();
1475 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1476 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1477 DebugLoc DL = MI.getDebugLoc();
1478
1479 Register DestReg = MI.getOperand(i: 0).getReg();
1480 assert(MI.definesRegister(DestReg, /*TRI=*/nullptr) &&
1481 "RESTORE_QUADWORD does not define its destination");
1482
1483 Register Reg = PPC::X0 + (DestReg - PPC::G8p0) * 2;
1484 bool IsLittleEndian = Subtarget.isLittleEndian();
1485
1486 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::LD), DestReg: Reg), FI: FrameIndex,
1487 Offset: IsLittleEndian ? 8 : 0);
1488 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::LD), DestReg: Reg + 1), FI: FrameIndex,
1489 Offset: IsLittleEndian ? 0 : 8);
1490
1491 // Discard the pseudo instruction.
1492 MBB.erase(I: II);
1493}
1494
1495/// lowerDMRSpilling - Generate the code for spilling the DMR register.
1496void PPCRegisterInfo::lowerDMRSpilling(MachineBasicBlock::iterator II,
1497 unsigned FrameIndex) const {
1498 MachineInstr &MI = *II; // SPILL_DMR <SrcReg>, <offset>
1499 MachineBasicBlock &MBB = *MI.getParent();
1500 MachineFunction &MF = *MBB.getParent();
1501 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1502 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1503 DebugLoc DL = MI.getDebugLoc();
1504 bool IsLittleEndian = Subtarget.isLittleEndian();
1505
1506 // DMR is made up of WACC and WACC_HI, so DMXXEXTFDMR512 to spill
1507 // the corresponding 512 bits.
1508 const TargetRegisterClass *RC = &PPC::VSRpRCRegClass;
1509 auto spillDMR = [&](Register SrcReg, int BEIdx, int LEIdx) {
1510 auto spillWACC = [&](unsigned Opc, unsigned RegIdx, int IdxBE, int IdxLE) {
1511 Register VSRpReg0 = MF.getRegInfo().createVirtualRegister(RegClass: RC);
1512 Register VSRpReg1 = MF.getRegInfo().createVirtualRegister(RegClass: RC);
1513
1514 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: Opc), DestReg: VSRpReg0)
1515 .addDef(RegNo: VSRpReg1)
1516 .addReg(RegNo: TargetRegisterInfo::getSubReg(Reg: SrcReg, Idx: RegIdx));
1517
1518 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::STXVP))
1519 .addReg(RegNo: VSRpReg0, Flags: RegState::Kill),
1520 FI: FrameIndex, Offset: IsLittleEndian ? IdxLE : IdxBE);
1521 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::STXVP))
1522 .addReg(RegNo: VSRpReg1, Flags: RegState::Kill),
1523 FI: FrameIndex, Offset: IsLittleEndian ? IdxLE - 32 : IdxBE + 32);
1524 };
1525 spillWACC(PPC::DMXXEXTFDMR512, PPC::sub_wacc_lo, BEIdx, LEIdx);
1526 spillWACC(PPC::DMXXEXTFDMR512_HI, PPC::sub_wacc_hi, BEIdx + 64, LEIdx - 64);
1527 };
1528
1529 Register SrcReg = MI.getOperand(i: 0).getReg();
1530 if (MI.getOpcode() == PPC::SPILL_DMRP) {
1531 spillDMR(TargetRegisterInfo::getSubReg(Reg: SrcReg, Idx: PPC::sub_dmr1), 0, 96);
1532 spillDMR(TargetRegisterInfo::getSubReg(Reg: SrcReg, Idx: PPC::sub_dmr0), 128, 224);
1533 } else
1534 spillDMR(SrcReg, 0, 96);
1535
1536 // Discard the pseudo instruction.
1537 MBB.erase(I: II);
1538}
1539
1540/// lowerDMRRestore - Generate the code to restore the DMR register.
1541void PPCRegisterInfo::lowerDMRRestore(MachineBasicBlock::iterator II,
1542 unsigned FrameIndex) const {
1543 MachineInstr &MI = *II; // <DestReg> = RESTORE_DMR[P] <offset>
1544 MachineBasicBlock &MBB = *MI.getParent();
1545 MachineFunction &MF = *MBB.getParent();
1546 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1547 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1548 DebugLoc DL = MI.getDebugLoc();
1549 bool IsLittleEndian = Subtarget.isLittleEndian();
1550
1551 const TargetRegisterClass *RC = &PPC::VSRpRCRegClass;
1552 auto restoreDMR = [&](Register DestReg, int BEIdx, int LEIdx) {
1553 auto restoreWACC = [&](unsigned Opc, unsigned RegIdx, int IdxBE,
1554 int IdxLE) {
1555 Register VSRpReg0 = MF.getRegInfo().createVirtualRegister(RegClass: RC);
1556 Register VSRpReg1 = MF.getRegInfo().createVirtualRegister(RegClass: RC);
1557
1558 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::LXVP), DestReg: VSRpReg0),
1559 FI: FrameIndex, Offset: IsLittleEndian ? IdxLE : IdxBE);
1560 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::LXVP), DestReg: VSRpReg1),
1561 FI: FrameIndex, Offset: IsLittleEndian ? IdxLE - 32 : IdxBE + 32);
1562
1563 // Kill virtual registers (killedRegState::Killed).
1564 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: Opc),
1565 DestReg: TargetRegisterInfo::getSubReg(Reg: DestReg, Idx: RegIdx))
1566 .addReg(RegNo: VSRpReg0, Flags: RegState::Kill)
1567 .addReg(RegNo: VSRpReg1, Flags: RegState::Kill);
1568 };
1569 restoreWACC(PPC::DMXXINSTDMR512, PPC::sub_wacc_lo, BEIdx, LEIdx);
1570 restoreWACC(PPC::DMXXINSTDMR512_HI, PPC::sub_wacc_hi, BEIdx + 64,
1571 LEIdx - 64);
1572 };
1573
1574 Register DestReg = MI.getOperand(i: 0).getReg();
1575 if (MI.getOpcode() == PPC::RESTORE_DMRP) {
1576 restoreDMR(TargetRegisterInfo::getSubReg(Reg: DestReg, Idx: PPC::sub_dmr1), 0, 96);
1577 restoreDMR(TargetRegisterInfo::getSubReg(Reg: DestReg, Idx: PPC::sub_dmr0), 128, 224);
1578 } else
1579 restoreDMR(DestReg, 0, 96);
1580
1581 // Discard the pseudo instruction.
1582 MBB.erase(I: II);
1583}
1584
1585bool PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
1586 Register Reg, int &FrameIdx) const {
1587 // For the nonvolatile condition registers (CR2, CR3, CR4) return true to
1588 // prevent allocating an additional frame slot.
1589 // For 64-bit ELF and AIX, the CR save area is in the linkage area at SP+8,
1590 // for 32-bit AIX the CR save area is in the linkage area at SP+4.
1591 // We have created a FrameIndex to that spill slot to keep the CalleSaveInfos
1592 // valid.
1593 // For 32-bit ELF, we have previously created the stack slot if needed, so
1594 // return its FrameIdx.
1595 if (PPC::CR2 <= Reg && Reg <= PPC::CR4) {
1596 FrameIdx = MF.getInfo<PPCFunctionInfo>()->getCRSpillFrameIndex();
1597 return true;
1598 }
1599 return false;
1600}
1601
1602// If the offset must be a multiple of some value, return what that value is.
1603static unsigned offsetMinAlignForOpcode(unsigned OpC) {
1604 switch (OpC) {
1605 default:
1606 return 1;
1607 case PPC::LWA:
1608 case PPC::LWA_32:
1609 case PPC::LD:
1610 case PPC::LDU:
1611 case PPC::STD:
1612 case PPC::STDU:
1613 case PPC::DFLOADf32:
1614 case PPC::DFLOADf64:
1615 case PPC::DFSTOREf32:
1616 case PPC::DFSTOREf64:
1617 case PPC::LXSD:
1618 case PPC::LXSSP:
1619 case PPC::STXSD:
1620 case PPC::STXSSP:
1621 case PPC::STQ:
1622 return 4;
1623 case PPC::EVLDD:
1624 case PPC::EVSTDD:
1625 return 8;
1626 case PPC::LXV:
1627 case PPC::STXV:
1628 case PPC::LQ:
1629 case PPC::LXVP:
1630 case PPC::STXVP:
1631 return 16;
1632 }
1633}
1634
1635// If the offset must be a multiple of some value, return what that value is.
1636static unsigned offsetMinAlign(const MachineInstr &MI) {
1637 unsigned OpC = MI.getOpcode();
1638 return offsetMinAlignForOpcode(OpC);
1639}
1640
1641// Return the OffsetOperandNo given the FIOperandNum (and the instruction).
1642static unsigned getOffsetONFromFION(const MachineInstr &MI,
1643 unsigned FIOperandNum) {
1644 // Take into account whether it's an add or mem instruction
1645 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
1646 if (MI.isInlineAsm())
1647 OffsetOperandNo = FIOperandNum - 1;
1648 else if (MI.getOpcode() == TargetOpcode::STACKMAP ||
1649 MI.getOpcode() == TargetOpcode::PATCHPOINT)
1650 OffsetOperandNo = FIOperandNum + 1;
1651
1652 return OffsetOperandNo;
1653}
1654
1655bool
1656PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1657 int SPAdj, unsigned FIOperandNum,
1658 RegScavenger *RS) const {
1659 assert(SPAdj == 0 && "Unexpected");
1660
1661 // Get the instruction.
1662 MachineInstr &MI = *II;
1663 // Get the instruction's basic block.
1664 MachineBasicBlock &MBB = *MI.getParent();
1665 // Get the basic block's function.
1666 MachineFunction &MF = *MBB.getParent();
1667 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1668 // Get the instruction info.
1669 const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
1670 // Get the frame info.
1671 MachineFrameInfo &MFI = MF.getFrameInfo();
1672 DebugLoc dl = MI.getDebugLoc();
1673
1674 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
1675
1676 // Get the frame index.
1677 int FrameIndex = MI.getOperand(i: FIOperandNum).getIndex();
1678
1679 // Get the frame pointer save index. Users of this index are primarily
1680 // DYNALLOC instructions.
1681 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1682 int FPSI = FI->getFramePointerSaveIndex();
1683 // Get the instruction opcode.
1684 unsigned OpC = MI.getOpcode();
1685
1686 switch (OpC) {
1687 default:
1688 break;
1689 case PPC::DYNAREAOFFSET:
1690 case PPC::DYNAREAOFFSET8:
1691 lowerDynamicAreaOffset(II);
1692 // lowerDynamicAreaOffset erases II
1693 return true;
1694 case PPC::DYNALLOC:
1695 case PPC::DYNALLOC8: {
1696 // Special case for dynamic alloca.
1697 if (FPSI && FrameIndex == FPSI) {
1698 lowerDynamicAlloc(II); // lowerDynamicAlloc erases II
1699 return true;
1700 }
1701 break;
1702 }
1703 case PPC::PREPARE_PROBED_ALLOCA_64:
1704 case PPC::PREPARE_PROBED_ALLOCA_32:
1705 case PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64:
1706 case PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32: {
1707 if (FPSI && FrameIndex == FPSI) {
1708 lowerPrepareProbedAlloca(II); // lowerPrepareProbedAlloca erases II
1709 return true;
1710 }
1711 break;
1712 }
1713 case PPC::SPILL_CR:
1714 // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc.
1715 lowerCRSpilling(II, FrameIndex);
1716 return true;
1717 case PPC::RESTORE_CR:
1718 lowerCRRestore(II, FrameIndex);
1719 return true;
1720 case PPC::SPILL_CRBIT:
1721 lowerCRBitSpilling(II, FrameIndex);
1722 return true;
1723 case PPC::RESTORE_CRBIT:
1724 lowerCRBitRestore(II, FrameIndex);
1725 return true;
1726 case PPC::SPILL_ACC:
1727 case PPC::SPILL_UACC:
1728 lowerACCSpilling(II, FrameIndex);
1729 return true;
1730 case PPC::RESTORE_ACC:
1731 case PPC::RESTORE_UACC:
1732 lowerACCRestore(II, FrameIndex);
1733 return true;
1734 case PPC::STXVP: {
1735 if (DisableAutoPairedVecSt) {
1736 lowerOctWordSpilling(II, FrameIndex);
1737 return true;
1738 }
1739 break;
1740 }
1741 case PPC::SPILL_WACC:
1742 lowerWACCSpilling(II, FrameIndex);
1743 return true;
1744 case PPC::RESTORE_WACC:
1745 lowerWACCRestore(II, FrameIndex);
1746 return true;
1747 case PPC::SPILL_DMRP:
1748 case PPC::SPILL_DMR:
1749 lowerDMRSpilling(II, FrameIndex);
1750 return true;
1751 case PPC::RESTORE_DMRP:
1752 case PPC::RESTORE_DMR:
1753 lowerDMRRestore(II, FrameIndex);
1754 return true;
1755 case PPC::SPILL_QUADWORD:
1756 lowerQuadwordSpilling(II, FrameIndex);
1757 return true;
1758 case PPC::RESTORE_QUADWORD:
1759 lowerQuadwordRestore(II, FrameIndex);
1760 return true;
1761 }
1762
1763 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
1764 MI.getOperand(i: FIOperandNum).ChangeToRegister(
1765 Reg: FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), isDef: false);
1766
1767 // If the instruction is not present in ImmToIdxMap, then it has no immediate
1768 // form (and must be r+r).
1769 bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP &&
1770 OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(Val: OpC);
1771
1772 // Now add the frame object offset to the offset from r1.
1773 int64_t Offset = MFI.getObjectOffset(ObjectIdx: FrameIndex);
1774 Offset += MI.getOperand(i: OffsetOperandNo).getImm();
1775
1776 // If we're not using a Frame Pointer that has been set to the value of the
1777 // SP before having the stack size subtracted from it, then add the stack size
1778 // to Offset to get the correct offset.
1779 // Naked functions have stack size 0, although getStackSize may not reflect
1780 // that because we didn't call all the pieces that compute it for naked
1781 // functions.
1782 if (!MF.getFunction().hasFnAttribute(Kind: Attribute::Naked)) {
1783 if (!(hasBasePointer(MF) && FrameIndex < 0))
1784 Offset += MFI.getStackSize();
1785 }
1786
1787 // If we encounter an LXVP/STXVP with an offset that doesn't fit, we can
1788 // transform it to the prefixed version so we don't have to use the XForm.
1789 if ((OpC == PPC::LXVP || OpC == PPC::STXVP) &&
1790 (!isInt<16>(x: Offset) || (Offset % offsetMinAlign(MI)) != 0) &&
1791 Subtarget.hasPrefixInstrs() && Subtarget.hasP10Vector()) {
1792 unsigned NewOpc = OpC == PPC::LXVP ? PPC::PLXVP : PPC::PSTXVP;
1793 MI.setDesc(TII.get(Opcode: NewOpc));
1794 OpC = NewOpc;
1795 }
1796
1797 // If we can, encode the offset directly into the instruction. If this is a
1798 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
1799 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
1800 // clear can be encoded. This is extremely uncommon, because normally you
1801 // only "std" to a stack slot that is at least 4-byte aligned, but it can
1802 // happen in invalid code.
1803 assert(OpC != PPC::DBG_VALUE &&
1804 "This should be handled in a target-independent way");
1805 // FIXME: This should be factored out to a separate function as prefixed
1806 // instructions add a number of opcodes for which we can use 34-bit imm.
1807 bool OffsetFitsMnemonic = (OpC == PPC::EVSTDD || OpC == PPC::EVLDD) ?
1808 isUInt<8>(x: Offset) :
1809 isInt<16>(x: Offset);
1810 if (TII.isPrefixed(Opcode: MI.getOpcode()))
1811 OffsetFitsMnemonic = isInt<34>(x: Offset);
1812 if (!noImmForm && ((OffsetFitsMnemonic &&
1813 ((Offset % offsetMinAlign(MI)) == 0)) ||
1814 OpC == TargetOpcode::STACKMAP ||
1815 OpC == TargetOpcode::PATCHPOINT)) {
1816 MI.getOperand(i: OffsetOperandNo).ChangeToImmediate(ImmVal: Offset);
1817 return false;
1818 }
1819
1820 // The offset doesn't fit into a single register, scavenge one to build the
1821 // offset in.
1822
1823 bool is64Bit = TM.isPPC64();
1824 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1825 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1826 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
1827 unsigned NewOpcode = 0u;
1828 bool ScavengingFailed = RS && RS->getRegsAvailable(RC).none() &&
1829 RS->getRegsAvailable(RC: &PPC::VSFRCRegClass).any();
1830 Register SRegHi, SReg, VSReg;
1831
1832 // The register scavenger is unable to get a GPR but can get a VSR. We
1833 // need to stash a GPR into a VSR so that we can free one up.
1834 if (ScavengingFailed && Subtarget.hasDirectMove()) {
1835 // Pick a volatile register and if we are spilling/restoring that
1836 // particular one, pick the next one.
1837 SRegHi = SReg = is64Bit ? PPC::X4 : PPC::R4;
1838 if (MI.getOperand(i: 0).getReg() == SReg)
1839 SRegHi = SReg = SReg + 1;
1840 VSReg = MF.getRegInfo().createVirtualRegister(RegClass: &PPC::VSFRCRegClass);
1841 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: is64Bit ? PPC::MTVSRD : PPC::MTVSRWZ), DestReg: VSReg)
1842 .addReg(RegNo: SReg);
1843 } else {
1844 SRegHi = MF.getRegInfo().createVirtualRegister(RegClass: RC);
1845 SReg = MF.getRegInfo().createVirtualRegister(RegClass: RC);
1846 }
1847
1848 // Insert a set of rA with the full offset value before the ld, st, or add
1849 if (isInt<16>(x: Offset))
1850 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: is64Bit ? PPC::LI8 : PPC::LI), DestReg: SReg)
1851 .addImm(Val: Offset);
1852 else if (isInt<32>(x: Offset)) {
1853 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: is64Bit ? PPC::LIS8 : PPC::LIS), DestReg: SRegHi)
1854 .addImm(Val: Offset >> 16);
1855 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: is64Bit ? PPC::ORI8 : PPC::ORI), DestReg: SReg)
1856 .addReg(RegNo: SRegHi, Flags: RegState::Kill)
1857 .addImm(Val: Offset);
1858 } else {
1859 assert(is64Bit && "Huge stack is only supported on PPC64");
1860 TII.materializeImmPostRA(MBB, MBBI: II, DL: dl, Reg: SReg, Imm: Offset);
1861 }
1862
1863 // Convert into indexed form of the instruction:
1864 //
1865 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
1866 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
1867 unsigned OperandBase;
1868
1869 if (noImmForm)
1870 OperandBase = 1;
1871 else if (OpC != TargetOpcode::INLINEASM &&
1872 OpC != TargetOpcode::INLINEASM_BR) {
1873 assert(ImmToIdxMap.count(OpC) &&
1874 "No indexed form of load or store available!");
1875 NewOpcode = ImmToIdxMap.find(Val: OpC)->second;
1876 MI.setDesc(TII.get(Opcode: NewOpcode));
1877 OperandBase = 1;
1878 } else {
1879 OperandBase = OffsetOperandNo;
1880 }
1881
1882 Register StackReg = MI.getOperand(i: FIOperandNum).getReg();
1883 MI.getOperand(i: OperandBase).ChangeToRegister(Reg: StackReg, isDef: false);
1884 MI.getOperand(i: OperandBase + 1).ChangeToRegister(Reg: SReg, isDef: false, isImp: false, isKill: true);
1885
1886 // If we stashed a value from a GPR into a VSR, we need to get it back after
1887 // spilling the register.
1888 if (ScavengingFailed && Subtarget.hasDirectMove())
1889 BuildMI(BB&: MBB, I: ++II, MIMD: dl, MCID: TII.get(Opcode: is64Bit ? PPC::MFVSRD : PPC::MFVSRWZ), DestReg: SReg)
1890 .addReg(RegNo: VSReg);
1891
1892 // Since these are not real X-Form instructions, we must
1893 // add the registers and access 0(NewReg) rather than
1894 // emitting the X-Form pseudo.
1895 if (NewOpcode == PPC::LQX_PSEUDO || NewOpcode == PPC::STQX_PSEUDO) {
1896 assert(is64Bit && "Quadword loads/stores only supported in 64-bit mode");
1897 Register NewReg = MF.getRegInfo().createVirtualRegister(RegClass: &PPC::G8RCRegClass);
1898 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: PPC::ADD8), DestReg: NewReg)
1899 .addReg(RegNo: SReg, Flags: RegState::Kill)
1900 .addReg(RegNo: StackReg);
1901 MI.setDesc(TII.get(Opcode: NewOpcode == PPC::LQX_PSEUDO ? PPC::LQ : PPC::STQ));
1902 MI.getOperand(i: OperandBase + 1).ChangeToRegister(Reg: NewReg, isDef: false);
1903 MI.getOperand(i: OperandBase).ChangeToImmediate(ImmVal: 0);
1904 }
1905 return false;
1906}
1907
1908Register PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
1909 const PPCFrameLowering *TFI = getFrameLowering(MF);
1910
1911 if (!TM.isPPC64())
1912 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
1913 else
1914 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
1915}
1916
1917Register PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const {
1918 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1919 if (!hasBasePointer(MF))
1920 return getFrameRegister(MF);
1921
1922 if (TM.isPPC64())
1923 return PPC::X30;
1924
1925 if (Subtarget.isSVR4ABI() && TM.isPositionIndependent())
1926 return PPC::R29;
1927
1928 return PPC::R30;
1929}
1930
1931bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
1932 if (!EnableBasePointer)
1933 return false;
1934 if (AlwaysBasePointer)
1935 return true;
1936
1937 // If we need to realign the stack, then the stack pointer can no longer
1938 // serve as an offset into the caller's stack space. As a result, we need a
1939 // base pointer.
1940 return hasStackRealignment(MF);
1941}
1942
1943/// Returns true if the instruction's frame index
1944/// reference would be better served by a base register other than FP
1945/// or SP. Used by LocalStackFrameAllocation to determine which frame index
1946/// references it should create new base registers for.
1947bool PPCRegisterInfo::
1948needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
1949 assert(Offset < 0 && "Local offset must be negative");
1950
1951 // It's the load/store FI references that cause issues, as it can be difficult
1952 // to materialize the offset if it won't fit in the literal field. Estimate
1953 // based on the size of the local frame and some conservative assumptions
1954 // about the rest of the stack frame (note, this is pre-regalloc, so
1955 // we don't know everything for certain yet) whether this offset is likely
1956 // to be out of range of the immediate. Return true if so.
1957
1958 // We only generate virtual base registers for loads and stores that have
1959 // an r+i form. Return false for everything else.
1960 unsigned OpC = MI->getOpcode();
1961 if (!ImmToIdxMap.count(Val: OpC))
1962 return false;
1963
1964 // Don't generate a new virtual base register just to add zero to it.
1965 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) &&
1966 MI->getOperand(i: 2).getImm() == 0)
1967 return false;
1968
1969 MachineBasicBlock &MBB = *MI->getParent();
1970 MachineFunction &MF = *MBB.getParent();
1971 const PPCFrameLowering *TFI = getFrameLowering(MF);
1972 unsigned StackEst = TFI->determineFrameLayout(MF, UseEstimate: true);
1973
1974 // If we likely don't need a stack frame, then we probably don't need a
1975 // virtual base register either.
1976 if (!StackEst)
1977 return false;
1978
1979 // Estimate an offset from the stack pointer.
1980 // The incoming offset is relating to the SP at the start of the function,
1981 // but when we access the local it'll be relative to the SP after local
1982 // allocation, so adjust our SP-relative offset by that allocation size.
1983 Offset += StackEst;
1984
1985 // The frame pointer will point to the end of the stack, so estimate the
1986 // offset as the difference between the object offset and the FP location.
1987 return !isFrameOffsetLegal(MI, BaseReg: getBaseRegister(MF), Offset);
1988}
1989
1990/// Insert defining instruction(s) for BaseReg to
1991/// be a pointer to FrameIdx at the beginning of the basic block.
1992Register PPCRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
1993 int FrameIdx,
1994 int64_t Offset) const {
1995 unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI;
1996
1997 MachineBasicBlock::iterator Ins = MBB->begin();
1998 DebugLoc DL; // Defaults to "unknown"
1999 if (Ins != MBB->end())
2000 DL = Ins->getDebugLoc();
2001
2002 const MachineFunction &MF = *MBB->getParent();
2003 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
2004 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
2005 const MCInstrDesc &MCID = TII.get(Opcode: ADDriOpc);
2006 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
2007 Register BaseReg = MRI.createVirtualRegister(RegClass: TII.getRegClass(MCID, OpNum: 0));
2008
2009 BuildMI(BB&: *MBB, I: Ins, MIMD: DL, MCID, DestReg: BaseReg)
2010 .addFrameIndex(Idx: FrameIdx).addImm(Val: Offset);
2011
2012 return BaseReg;
2013}
2014
2015void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg,
2016 int64_t Offset) const {
2017 unsigned FIOperandNum = 0;
2018 while (!MI.getOperand(i: FIOperandNum).isFI()) {
2019 ++FIOperandNum;
2020 assert(FIOperandNum < MI.getNumOperands() &&
2021 "Instr doesn't have FrameIndex operand!");
2022 }
2023
2024 MI.getOperand(i: FIOperandNum).ChangeToRegister(Reg: BaseReg, isDef: false);
2025 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
2026 Offset += MI.getOperand(i: OffsetOperandNo).getImm();
2027 MI.getOperand(i: OffsetOperandNo).ChangeToImmediate(ImmVal: Offset);
2028
2029 MachineBasicBlock &MBB = *MI.getParent();
2030 MachineFunction &MF = *MBB.getParent();
2031 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
2032 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
2033 const MCInstrDesc &MCID = MI.getDesc();
2034 MachineRegisterInfo &MRI = MF.getRegInfo();
2035 MRI.constrainRegClass(Reg: BaseReg, RC: TII.getRegClass(MCID, OpNum: FIOperandNum));
2036}
2037
2038bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
2039 Register BaseReg,
2040 int64_t Offset) const {
2041 unsigned FIOperandNum = 0;
2042 while (!MI->getOperand(i: FIOperandNum).isFI()) {
2043 ++FIOperandNum;
2044 assert(FIOperandNum < MI->getNumOperands() &&
2045 "Instr doesn't have FrameIndex operand!");
2046 }
2047
2048 unsigned OffsetOperandNo = getOffsetONFromFION(MI: *MI, FIOperandNum);
2049 Offset += MI->getOperand(i: OffsetOperandNo).getImm();
2050
2051 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
2052 MI->getOpcode() == TargetOpcode::STACKMAP ||
2053 MI->getOpcode() == TargetOpcode::PATCHPOINT ||
2054 (isInt<16>(x: Offset) && (Offset % offsetMinAlign(MI: *MI)) == 0);
2055}
2056