1//===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the PowerPC implementation of the TargetRegisterInfo
10// class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCRegisterInfo.h"
15#include "PPCFrameLowering.h"
16#include "PPCInstrBuilder.h"
17#include "PPCMachineFunctionInfo.h"
18#include "PPCSubtarget.h"
19#include "PPCTargetMachine.h"
20#include "llvm/ADT/BitVector.h"
21#include "llvm/ADT/Statistic.h"
22#include "llvm/CodeGen/MachineFrameInfo.h"
23#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/MachineInstrBuilder.h"
25#include "llvm/CodeGen/MachineModuleInfo.h"
26#include "llvm/CodeGen/MachineRegisterInfo.h"
27#include "llvm/CodeGen/RegisterScavenging.h"
28#include "llvm/CodeGen/TargetFrameLowering.h"
29#include "llvm/CodeGen/TargetInstrInfo.h"
30#include "llvm/CodeGen/VirtRegMap.h"
31#include "llvm/IR/CallingConv.h"
32#include "llvm/IR/Function.h"
33#include "llvm/IR/Type.h"
34#include "llvm/Support/CommandLine.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/MathExtras.h"
38#include "llvm/Support/raw_ostream.h"
39#include "llvm/Target/TargetMachine.h"
40#include "llvm/Target/TargetOptions.h"
41
42using namespace llvm;
43
44#define DEBUG_TYPE "reginfo"
45
46#define GET_REGINFO_TARGET_DESC
47#include "PPCGenRegisterInfo.inc"
48
49STATISTIC(InflateGPRC, "Number of gprc inputs for getLargestLegalClass");
50STATISTIC(InflateGP8RC, "Number of g8rc inputs for getLargestLegalClass");
51
52static cl::opt<bool>
53EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(Val: true),
54 cl::desc("Enable use of a base pointer for complex stack frames"));
55
56static cl::opt<bool>
57AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(Val: false),
58 cl::desc("Force the use of a base pointer in every function"));
59
60static cl::opt<bool>
61EnableGPRToVecSpills("ppc-enable-gpr-to-vsr-spills", cl::Hidden, cl::init(Val: false),
62 cl::desc("Enable spills from gpr to vsr rather than stack"));
63
64static cl::opt<bool>
65StackPtrConst("ppc-stack-ptr-caller-preserved",
66 cl::desc("Consider R1 caller preserved so stack saves of "
67 "caller preserved registers can be LICM candidates"),
68 cl::init(Val: true), cl::Hidden);
69
70static cl::opt<unsigned>
71MaxCRBitSpillDist("ppc-max-crbit-spill-dist",
72 cl::desc("Maximum search distance for definition of CR bit "
73 "spill on ppc"),
74 cl::Hidden, cl::init(Val: 100));
75
76// Copies/moves of physical accumulators are expensive operations
77// that should be avoided whenever possible. MMA instructions are
78// meant to be used in performance-sensitive computational kernels.
79// This option is provided, at least for the time being, to give the
80// user a tool to detect this expensive operation and either rework
81// their code or report a compiler bug if that turns out to be the
82// cause.
83#ifndef NDEBUG
84static cl::opt<bool>
85ReportAccMoves("ppc-report-acc-moves",
86 cl::desc("Emit information about accumulator register spills "
87 "and copies"),
88 cl::Hidden, cl::init(false));
89#endif
90
91extern cl::opt<bool> DisableAutoPairedVecSt;
92
93static unsigned offsetMinAlignForOpcode(unsigned OpC);
94
95PPCRegisterInfo::PPCRegisterInfo(const PPCTargetMachine &TM)
96 : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR,
97 TM.isPPC64() ? 0 : 1,
98 TM.isPPC64() ? 0 : 1),
99 TM(TM) {
100 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
101 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
102 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
103 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
104 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
105 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
106 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
107 ImmToIdxMap[PPC::ADDI] = PPC::ADD4;
108 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32;
109
110 // 64-bit
111 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8;
112 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8;
113 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8;
114 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX;
115 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8;
116 ImmToIdxMap[PPC::LQ] = PPC::LQX_PSEUDO;
117 ImmToIdxMap[PPC::STQ] = PPC::STQX_PSEUDO;
118
119 // VSX
120 ImmToIdxMap[PPC::DFLOADf32] = PPC::LXSSPX;
121 ImmToIdxMap[PPC::DFLOADf64] = PPC::LXSDX;
122 ImmToIdxMap[PPC::SPILLTOVSR_LD] = PPC::SPILLTOVSR_LDX;
123 ImmToIdxMap[PPC::SPILLTOVSR_ST] = PPC::SPILLTOVSR_STX;
124 ImmToIdxMap[PPC::DFSTOREf32] = PPC::STXSSPX;
125 ImmToIdxMap[PPC::DFSTOREf64] = PPC::STXSDX;
126 ImmToIdxMap[PPC::LXV] = PPC::LXVX;
127 ImmToIdxMap[PPC::LXSD] = PPC::LXSDX;
128 ImmToIdxMap[PPC::LXSSP] = PPC::LXSSPX;
129 ImmToIdxMap[PPC::STXV] = PPC::STXVX;
130 ImmToIdxMap[PPC::STXSD] = PPC::STXSDX;
131 ImmToIdxMap[PPC::STXSSP] = PPC::STXSSPX;
132
133 // SPE
134 ImmToIdxMap[PPC::EVLDD] = PPC::EVLDDX;
135 ImmToIdxMap[PPC::EVSTDD] = PPC::EVSTDDX;
136 ImmToIdxMap[PPC::SPESTW] = PPC::SPESTWX;
137 ImmToIdxMap[PPC::SPELWZ] = PPC::SPELWZX;
138
139 // Power10
140 ImmToIdxMap[PPC::PLBZ] = PPC::LBZX; ImmToIdxMap[PPC::PLBZ8] = PPC::LBZX8;
141 ImmToIdxMap[PPC::PLHZ] = PPC::LHZX; ImmToIdxMap[PPC::PLHZ8] = PPC::LHZX8;
142 ImmToIdxMap[PPC::PLHA] = PPC::LHAX; ImmToIdxMap[PPC::PLHA8] = PPC::LHAX8;
143 ImmToIdxMap[PPC::PLWZ] = PPC::LWZX; ImmToIdxMap[PPC::PLWZ8] = PPC::LWZX8;
144 ImmToIdxMap[PPC::PLWA] = PPC::LWAX; ImmToIdxMap[PPC::PLWA8] = PPC::LWAX;
145 ImmToIdxMap[PPC::PLD] = PPC::LDX; ImmToIdxMap[PPC::PSTD] = PPC::STDX;
146
147 ImmToIdxMap[PPC::PSTB] = PPC::STBX; ImmToIdxMap[PPC::PSTB8] = PPC::STBX8;
148 ImmToIdxMap[PPC::PSTH] = PPC::STHX; ImmToIdxMap[PPC::PSTH8] = PPC::STHX8;
149 ImmToIdxMap[PPC::PSTW] = PPC::STWX; ImmToIdxMap[PPC::PSTW8] = PPC::STWX8;
150
151 ImmToIdxMap[PPC::PLFS] = PPC::LFSX; ImmToIdxMap[PPC::PSTFS] = PPC::STFSX;
152 ImmToIdxMap[PPC::PLFD] = PPC::LFDX; ImmToIdxMap[PPC::PSTFD] = PPC::STFDX;
153 ImmToIdxMap[PPC::PLXSSP] = PPC::LXSSPX; ImmToIdxMap[PPC::PSTXSSP] = PPC::STXSSPX;
154 ImmToIdxMap[PPC::PLXSD] = PPC::LXSDX; ImmToIdxMap[PPC::PSTXSD] = PPC::STXSDX;
155 ImmToIdxMap[PPC::PLXV] = PPC::LXVX; ImmToIdxMap[PPC::PSTXV] = PPC::STXVX;
156
157 ImmToIdxMap[PPC::LXVP] = PPC::LXVPX;
158 ImmToIdxMap[PPC::STXVP] = PPC::STXVPX;
159 ImmToIdxMap[PPC::PLXVP] = PPC::LXVPX;
160 ImmToIdxMap[PPC::PSTXVP] = PPC::STXVPX;
161}
162
163const MCPhysReg*
164PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
165 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
166 if (MF->getFunction().getCallingConv() == CallingConv::AnyReg) {
167 if (!TM.isPPC64() && Subtarget.isAIXABI())
168 report_fatal_error(reason: "AnyReg unimplemented on 32-bit AIX.");
169 if (Subtarget.hasVSX()) {
170 if (Subtarget.pairedVectorMemops())
171 return CSR_64_AllRegs_VSRP_SaveList;
172 if (Subtarget.isAIXABI() && !Subtarget.isAIXExtendedAltivecABI())
173 return CSR_64_AllRegs_AIX_Dflt_VSX_SaveList;
174 return CSR_64_AllRegs_VSX_SaveList;
175 }
176 if (Subtarget.hasAltivec()) {
177 if (Subtarget.isAIXABI() && !Subtarget.isAIXExtendedAltivecABI())
178 return CSR_64_AllRegs_AIX_Dflt_Altivec_SaveList;
179 return CSR_64_AllRegs_Altivec_SaveList;
180 }
181 return CSR_64_AllRegs_SaveList;
182 }
183
184 // On PPC64, we might need to save r2 (but only if it is not reserved).
185 // We do not need to treat R2 as callee-saved when using PC-Relative calls
186 // because any direct uses of R2 will cause it to be reserved. If the function
187 // is a leaf or the only uses of R2 are implicit uses for calls, the calls
188 // will use the @notoc relocation which will cause this function to set the
189 // st_other bit to 1, thereby communicating to its caller that it arbitrarily
190 // clobbers the TOC.
191 bool SaveR2 = MF->getRegInfo().isAllocatable(PhysReg: PPC::X2) &&
192 !Subtarget.isUsingPCRelativeCalls();
193
194 // Cold calling convention CSRs.
195 if (MF->getFunction().getCallingConv() == CallingConv::Cold) {
196 if (Subtarget.isAIXABI())
197 report_fatal_error(reason: "Cold calling unimplemented on AIX.");
198 if (TM.isPPC64()) {
199 if (Subtarget.pairedVectorMemops())
200 return SaveR2 ? CSR_SVR64_ColdCC_R2_VSRP_SaveList
201 : CSR_SVR64_ColdCC_VSRP_SaveList;
202 if (Subtarget.hasAltivec())
203 return SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList
204 : CSR_SVR64_ColdCC_Altivec_SaveList;
205 return SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList
206 : CSR_SVR64_ColdCC_SaveList;
207 }
208 // 32-bit targets.
209 if (Subtarget.pairedVectorMemops())
210 return CSR_SVR32_ColdCC_VSRP_SaveList;
211 else if (Subtarget.hasAltivec())
212 return CSR_SVR32_ColdCC_Altivec_SaveList;
213 else if (Subtarget.hasSPE())
214 return CSR_SVR32_ColdCC_SPE_SaveList;
215 return CSR_SVR32_ColdCC_SaveList;
216 }
217 // Standard calling convention CSRs.
218 if (TM.isPPC64()) {
219 if (Subtarget.pairedVectorMemops()) {
220 if (Subtarget.isAIXABI()) {
221 if (!Subtarget.isAIXExtendedAltivecABI())
222 return SaveR2 ? CSR_PPC64_R2_SaveList : CSR_PPC64_SaveList;
223 return SaveR2 ? CSR_AIX64_R2_VSRP_SaveList : CSR_AIX64_VSRP_SaveList;
224 }
225 return SaveR2 ? CSR_SVR464_R2_VSRP_SaveList : CSR_SVR464_VSRP_SaveList;
226 }
227 if (Subtarget.hasAltivec() &&
228 (!Subtarget.isAIXABI() || Subtarget.isAIXExtendedAltivecABI())) {
229 return SaveR2 ? CSR_PPC64_R2_Altivec_SaveList
230 : CSR_PPC64_Altivec_SaveList;
231 }
232 return SaveR2 ? CSR_PPC64_R2_SaveList : CSR_PPC64_SaveList;
233 }
234 // 32-bit targets.
235 if (Subtarget.isAIXABI()) {
236 if (Subtarget.pairedVectorMemops())
237 return Subtarget.isAIXExtendedAltivecABI() ? CSR_AIX32_VSRP_SaveList
238 : CSR_AIX32_SaveList;
239 if (Subtarget.hasAltivec())
240 return Subtarget.isAIXExtendedAltivecABI() ? CSR_AIX32_Altivec_SaveList
241 : CSR_AIX32_SaveList;
242 return CSR_AIX32_SaveList;
243 }
244 if (Subtarget.pairedVectorMemops())
245 return CSR_SVR432_VSRP_SaveList;
246 if (Subtarget.hasAltivec())
247 return CSR_SVR432_Altivec_SaveList;
248 else if (Subtarget.hasSPE()) {
249 if (TM.isPositionIndependent() && !TM.isPPC64())
250 return CSR_SVR432_SPE_NO_S30_31_SaveList;
251 return CSR_SVR432_SPE_SaveList;
252 }
253 return CSR_SVR432_SaveList;
254}
255
256const uint32_t *
257PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
258 CallingConv::ID CC) const {
259 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
260 if (CC == CallingConv::AnyReg) {
261 if (Subtarget.hasVSX()) {
262 if (Subtarget.pairedVectorMemops())
263 return CSR_64_AllRegs_VSRP_RegMask;
264 if (Subtarget.isAIXABI() && !Subtarget.isAIXExtendedAltivecABI())
265 return CSR_64_AllRegs_AIX_Dflt_VSX_RegMask;
266 return CSR_64_AllRegs_VSX_RegMask;
267 }
268 if (Subtarget.hasAltivec()) {
269 if (Subtarget.isAIXABI() && !Subtarget.isAIXExtendedAltivecABI())
270 return CSR_64_AllRegs_AIX_Dflt_Altivec_RegMask;
271 return CSR_64_AllRegs_Altivec_RegMask;
272 }
273 return CSR_64_AllRegs_RegMask;
274 }
275
276 if (Subtarget.isAIXABI()) {
277 if (Subtarget.pairedVectorMemops()) {
278 if (!Subtarget.isAIXExtendedAltivecABI())
279 return TM.isPPC64() ? CSR_PPC64_RegMask : CSR_AIX32_RegMask;
280 return TM.isPPC64() ? CSR_AIX64_VSRP_RegMask : CSR_AIX32_VSRP_RegMask;
281 }
282 return TM.isPPC64() ? ((Subtarget.hasAltivec() &&
283 Subtarget.isAIXExtendedAltivecABI())
284 ? CSR_PPC64_Altivec_RegMask
285 : CSR_PPC64_RegMask)
286 : ((Subtarget.hasAltivec() &&
287 Subtarget.isAIXExtendedAltivecABI())
288 ? CSR_AIX32_Altivec_RegMask
289 : CSR_AIX32_RegMask);
290 }
291
292 if (CC == CallingConv::Cold) {
293 if (TM.isPPC64())
294 return Subtarget.pairedVectorMemops()
295 ? CSR_SVR64_ColdCC_VSRP_RegMask
296 : (Subtarget.hasAltivec() ? CSR_SVR64_ColdCC_Altivec_RegMask
297 : CSR_SVR64_ColdCC_RegMask);
298 else
299 return Subtarget.pairedVectorMemops()
300 ? CSR_SVR32_ColdCC_VSRP_RegMask
301 : (Subtarget.hasAltivec()
302 ? CSR_SVR32_ColdCC_Altivec_RegMask
303 : (Subtarget.hasSPE() ? CSR_SVR32_ColdCC_SPE_RegMask
304 : CSR_SVR32_ColdCC_RegMask));
305 }
306
307 if (TM.isPPC64())
308 return Subtarget.pairedVectorMemops()
309 ? CSR_SVR464_VSRP_RegMask
310 : (Subtarget.hasAltivec() ? CSR_PPC64_Altivec_RegMask
311 : CSR_PPC64_RegMask);
312 else
313 return Subtarget.pairedVectorMemops()
314 ? CSR_SVR432_VSRP_RegMask
315 : (Subtarget.hasAltivec()
316 ? CSR_SVR432_Altivec_RegMask
317 : (Subtarget.hasSPE()
318 ? (TM.isPositionIndependent()
319 ? CSR_SVR432_SPE_NO_S30_31_RegMask
320 : CSR_SVR432_SPE_RegMask)
321 : CSR_SVR432_RegMask));
322}
323
324const uint32_t*
325PPCRegisterInfo::getNoPreservedMask() const {
326 return CSR_NoRegs_RegMask;
327}
328
329void PPCRegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {
330 for (unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8, PPC::RM})
331 Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32));
332}
333
334BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
335 BitVector Reserved(getNumRegs());
336 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
337 const PPCFrameLowering *TFI = getFrameLowering(MF);
338
339 // The ZERO register is not really a register, but the representation of r0
340 // when used in instructions that treat r0 as the constant 0.
341 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::ZERO);
342
343 // The FP register is also not really a register, but is the representation
344 // of the frame pointer register used by ISD::FRAMEADDR.
345 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::FP);
346
347 // The BP register is also not really a register, but is the representation
348 // of the base pointer register used by setjmp.
349 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::BP);
350
351 // The counter registers must be reserved so that counter-based loops can
352 // be correctly formed (and the mtctr instructions are not DCE'd).
353 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::CTR);
354 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::CTR8);
355
356 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::R1);
357 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::LR);
358 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::LR8);
359 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::RM);
360
361 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::VRSAVE);
362
363 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
364 bool UsesTOCBasePtr = FuncInfo->usesTOCBasePtr();
365 // The SVR4 ABI reserves r2 and r13
366 if (Subtarget.isSVR4ABI() || Subtarget.isAIXABI()) {
367 // We only reserve r2 if we need to use the TOC pointer. If we have no
368 // explicit uses of the TOC pointer (meaning we're a leaf function with
369 // no constant-pool loads, etc.) and we have no potential uses inside an
370 // inline asm block, then we can treat r2 has an ordinary callee-saved
371 // register.
372 if (!TM.isPPC64() || UsesTOCBasePtr || MF.hasInlineAsm())
373 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::R2); // System-reserved register.
374
375 if (Subtarget.isSVR4ABI())
376 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::R13); // Small Data Area pointer register.
377 }
378
379 // On PPC64, r13 is the thread pointer. Never allocate this register.
380 if (TM.isPPC64())
381 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::R13);
382
383 if (TFI->needsFP(MF))
384 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::R31);
385
386 bool IsPositionIndependent = TM.isPositionIndependent();
387 if (hasBasePointer(MF)) {
388 if (Subtarget.is32BitELFABI() && IsPositionIndependent)
389 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::R29);
390 else
391 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::R30);
392 }
393
394 if (Subtarget.is32BitELFABI() && IsPositionIndependent)
395 markSuperRegs(RegisterSet&: Reserved, Reg: PPC::R30);
396
397 // Reserve Altivec registers when Altivec is unavailable.
398 if (!Subtarget.hasAltivec())
399 for (MCRegister Reg : PPC::VRRCRegClass)
400 markSuperRegs(RegisterSet&: Reserved, Reg);
401
402 if (Subtarget.isAIXABI() && Subtarget.hasAltivec() &&
403 !Subtarget.isAIXExtendedAltivecABI()) {
404 // In the AIX default Altivec ABI, vector registers VR20-VR31 are reserved
405 // and cannot be used.
406 for (auto Reg : CSR_Altivec_SaveList) {
407 if (Reg == 0)
408 break;
409 markSuperRegs(RegisterSet&: Reserved, Reg);
410 for (MCRegAliasIterator AS(Reg, this, true); AS.isValid(); ++AS) {
411 Reserved.set(*AS);
412 }
413 }
414 }
415
416 assert(checkAllSuperRegsMarked(Reserved));
417 return Reserved;
418}
419
420bool PPCRegisterInfo::isAsmClobberable(const MachineFunction &MF,
421 MCRegister PhysReg) const {
422 // CTR and LR registers are always reserved, but they are asm clobberable.
423 if (PhysReg == PPC::CTR || PhysReg == PPC::CTR8 || PhysReg == PPC::LR ||
424 PhysReg == PPC::LR8)
425 return true;
426
427 return !getReservedRegs(MF).test(Idx: PhysReg);
428}
429
430bool PPCRegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF) const {
431 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
432 const PPCInstrInfo *InstrInfo = Subtarget.getInstrInfo();
433 const MachineFrameInfo &MFI = MF.getFrameInfo();
434 const std::vector<CalleeSavedInfo> &Info = MFI.getCalleeSavedInfo();
435
436 LLVM_DEBUG(dbgs() << "requiresFrameIndexScavenging for " << MF.getName()
437 << ".\n");
438 // If the callee saved info is invalid we have to default to true for safety.
439 if (!MFI.isCalleeSavedInfoValid()) {
440 LLVM_DEBUG(dbgs() << "TRUE - Invalid callee saved info.\n");
441 return true;
442 }
443
444 // We will require the use of X-Forms because the frame is larger than what
445 // can be represented in signed 16 bits that fit in the immediate of a D-Form.
446 // If we need an X-Form then we need a register to store the address offset.
447 unsigned FrameSize = MFI.getStackSize();
448 // Signed 16 bits means that the FrameSize cannot be more than 15 bits.
449 if (FrameSize & ~0x7FFF) {
450 LLVM_DEBUG(dbgs() << "TRUE - Frame size is too large for D-Form.\n");
451 return true;
452 }
453
454 // The callee saved info is valid so it can be traversed.
455 // Checking for registers that need saving that do not have load or store
456 // forms where the address offset is an immediate.
457 for (const CalleeSavedInfo &CSI : Info) {
458 // If the spill is to a register no scavenging is required.
459 if (CSI.isSpilledToReg())
460 continue;
461
462 int FrIdx = CSI.getFrameIdx();
463 Register Reg = CSI.getReg();
464
465 const TargetRegisterClass *RC = getMinimalPhysRegClass(Reg);
466 unsigned Opcode = InstrInfo->getStoreOpcodeForSpill(RC);
467 if (!MFI.isFixedObjectIndex(ObjectIdx: FrIdx)) {
468 // This is not a fixed object. If it requires alignment then we may still
469 // need to use the XForm.
470 if (offsetMinAlignForOpcode(OpC: Opcode) > 1) {
471 LLVM_DEBUG(dbgs() << "Memory Operand: " << InstrInfo->getName(Opcode)
472 << " for register " << printReg(Reg, this) << ".\n");
473 LLVM_DEBUG(dbgs() << "TRUE - Not fixed frame object that requires "
474 << "alignment.\n");
475 return true;
476 }
477 }
478
479 // This is eiher:
480 // 1) A fixed frame index object which we know are aligned so
481 // as long as we have a valid DForm/DSForm/DQForm (non XForm) we don't
482 // need to consider the alignment here.
483 // 2) A not fixed object but in that case we now know that the min required
484 // alignment is no more than 1 based on the previous check.
485 if (InstrInfo->isXFormMemOp(Opcode)) {
486 LLVM_DEBUG(dbgs() << "Memory Operand: " << InstrInfo->getName(Opcode)
487 << " for register " << printReg(Reg, this) << ".\n");
488 LLVM_DEBUG(dbgs() << "TRUE - Memory operand is X-Form.\n");
489 return true;
490 }
491
492 // This is a spill/restore of a quadword.
493 if ((Opcode == PPC::RESTORE_QUADWORD) || (Opcode == PPC::SPILL_QUADWORD)) {
494 LLVM_DEBUG(dbgs() << "Memory Operand: " << InstrInfo->getName(Opcode)
495 << " for register " << printReg(Reg, this) << ".\n");
496 LLVM_DEBUG(dbgs() << "TRUE - Memory operand is a quadword.\n");
497 return true;
498 }
499 }
500 LLVM_DEBUG(dbgs() << "FALSE - Scavenging is not required.\n");
501 return false;
502}
503
504bool PPCRegisterInfo::requiresVirtualBaseRegisters(
505 const MachineFunction &MF) const {
506 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
507 // Do not use virtual base registers when ROP protection is turned on.
508 // Virtual base registers break the layout of the local variable space and may
509 // push the ROP Hash location past the 512 byte range of the ROP store
510 // instruction.
511 return !Subtarget.hasROPProtect();
512}
513
514bool PPCRegisterInfo::isCallerPreservedPhysReg(MCRegister PhysReg,
515 const MachineFunction &MF) const {
516 assert(PhysReg.isPhysical());
517 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
518 const MachineFrameInfo &MFI = MF.getFrameInfo();
519
520 if (!Subtarget.is64BitELFABI() && !Subtarget.isAIXABI())
521 return false;
522 if (PhysReg == Subtarget.getTOCPointerRegister())
523 // X2/R2 is guaranteed to be preserved within a function if it is reserved.
524 // The reason it's reserved is that it's the TOC pointer (and the function
525 // uses the TOC). In functions where it isn't reserved (i.e. leaf functions
526 // with no TOC access), we can't claim that it is preserved.
527 return (getReservedRegs(MF).test(Idx: PhysReg));
528 if (StackPtrConst && PhysReg == Subtarget.getStackPointerRegister() &&
529 !MFI.hasVarSizedObjects() && !MFI.hasOpaqueSPAdjustment())
530 // The value of the stack pointer does not change within a function after
531 // the prologue and before the epilogue if there are no dynamic allocations
532 // and no inline asm which clobbers X1/R1.
533 return true;
534 return false;
535}
536
537bool PPCRegisterInfo::getRegAllocationHints(
538 Register VirtReg, ArrayRef<MCPhysReg> Order,
539 SmallSetVector<MCPhysReg, 16> &Hints, const MachineFunction &MF,
540 const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
541 const MachineRegisterInfo *MRI = &MF.getRegInfo();
542
543 // Call the base implementation first to set any hints based on the usual
544 // heuristics and decide what the return value should be. We want to return
545 // the same value returned by the base implementation. If the base
546 // implementation decides to return true and force the allocation then we
547 // will leave it as such. On the other hand if the base implementation
548 // decides to return false the following code will not force the allocation
549 // as we are just looking to provide a hint.
550 bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
551 VirtReg, Order, Hints, MF, VRM, Matrix);
552
553 // Don't use the allocation hints for ISAFuture.
554 // The WACC registers used in ISAFuture are unlike the ACC registers on
555 // Power 10 and so this logic to register allocation hints does not apply.
556 if (MF.getSubtarget<PPCSubtarget>().isISAFuture())
557 return BaseImplRetVal;
558
559 // We are interested in instructions that copy values to ACC/UACC.
560 // The copy into UACC will be simply a COPY to a subreg so we
561 // want to allocate the corresponding physical subreg for the source.
562 // The copy into ACC will be a BUILD_UACC so we want to allocate
563 // the same number UACC for the source.
564 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg: VirtReg);
565 for (MachineInstr &Use : MRI->reg_nodbg_instructions(Reg: VirtReg)) {
566 const MachineOperand *ResultOp = nullptr;
567 Register ResultReg;
568 switch (Use.getOpcode()) {
569 case TargetOpcode::COPY: {
570 ResultOp = &Use.getOperand(i: 0);
571 ResultReg = ResultOp->getReg();
572 if (ResultReg.isVirtual() &&
573 MRI->getRegClass(Reg: ResultReg)->contains(Reg: PPC::UACC0) &&
574 VRM->hasPhys(virtReg: ResultReg)) {
575 Register UACCPhys = VRM->getPhys(virtReg: ResultReg);
576 Register HintReg;
577 if (RegClass->contains(Reg: PPC::VSRp0)) {
578 HintReg = getSubReg(Reg: UACCPhys, Idx: ResultOp->getSubReg());
579 // Ensure that the hint is a VSRp register.
580 if (HintReg >= PPC::VSRp0 && HintReg <= PPC::VSRp31)
581 Hints.insert(X: HintReg);
582 } else if (RegClass->contains(Reg: PPC::ACC0)) {
583 HintReg = PPC::ACC0 + (UACCPhys - PPC::UACC0);
584 if (HintReg >= PPC::ACC0 && HintReg <= PPC::ACC7)
585 Hints.insert(X: HintReg);
586 }
587 }
588 break;
589 }
590 case PPC::BUILD_UACC: {
591 ResultOp = &Use.getOperand(i: 0);
592 ResultReg = ResultOp->getReg();
593 if (MRI->getRegClass(Reg: ResultReg)->contains(Reg: PPC::ACC0) &&
594 VRM->hasPhys(virtReg: ResultReg)) {
595 Register ACCPhys = VRM->getPhys(virtReg: ResultReg);
596 assert((ACCPhys >= PPC::ACC0 && ACCPhys <= PPC::ACC7) &&
597 "Expecting an ACC register for BUILD_UACC.");
598 Register HintReg = PPC::UACC0 + (ACCPhys - PPC::ACC0);
599 Hints.insert(X: HintReg);
600 }
601 break;
602 }
603 }
604 }
605 return BaseImplRetVal;
606}
607
608const TargetRegisterClass *
609PPCRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
610 if (RC == &PPC::CARRYRCRegClass)
611 return TM.isPPC64() ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
612 return RC;
613}
614
615unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
616 MachineFunction &MF) const {
617 const PPCFrameLowering *TFI = getFrameLowering(MF);
618 const unsigned DefaultSafety = 1;
619
620 switch (RC->getID()) {
621 default:
622 return 0;
623 case PPC::G8RC_NOX0RegClassID:
624 case PPC::GPRC_NOR0RegClassID:
625 case PPC::SPERCRegClassID:
626 case PPC::G8RCRegClassID:
627 case PPC::GPRCRegClassID: {
628 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
629 return 32 - FP - DefaultSafety;
630 }
631 case PPC::F4RCRegClassID:
632 case PPC::F8RCRegClassID:
633 case PPC::VSLRCRegClassID:
634 return 32 - DefaultSafety;
635 case PPC::VFRCRegClassID:
636 case PPC::VRRCRegClassID: {
637 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
638 // Vector registers VR20-VR31 are reserved and cannot be used in the default
639 // Altivec ABI on AIX.
640 if (!Subtarget.isAIXExtendedAltivecABI() && Subtarget.isAIXABI())
641 return 20 - DefaultSafety;
642 }
643 return 32 - DefaultSafety;
644 case PPC::VSFRCRegClassID:
645 case PPC::VSSRCRegClassID:
646 case PPC::VSRCRegClassID: {
647 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
648 if (!Subtarget.isAIXExtendedAltivecABI() && Subtarget.isAIXABI())
649 // Vector registers VR20-VR31 are reserved and cannot be used in the
650 // default Altivec ABI on AIX.
651 return 52 - DefaultSafety;
652 }
653 return 64 - DefaultSafety;
654 case PPC::CRRCRegClassID:
655 return 8 - DefaultSafety;
656 }
657}
658
659const TargetRegisterClass *
660PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
661 const MachineFunction &MF) const {
662 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
663 const auto *DefaultSuperclass =
664 TargetRegisterInfo::getLargestLegalSuperClass(RC, MF);
665 if (Subtarget.hasVSX()) {
666 // With VSX, we can inflate various sub-register classes to the full VSX
667 // register set.
668
669 // For Power9 we allow the user to enable GPR to vector spills.
670 // FIXME: Currently limited to spilling GP8RC. A follow on patch will add
671 // support to spill GPRC.
672 if (Subtarget.isELFv2ABI() || Subtarget.isAIXABI()) {
673 if (Subtarget.hasP9Vector() && EnableGPRToVecSpills &&
674 RC == &PPC::G8RCRegClass) {
675 InflateGP8RC++;
676 return &PPC::SPILLTOVSRRCRegClass;
677 }
678 if (RC == &PPC::GPRCRegClass && EnableGPRToVecSpills)
679 InflateGPRC++;
680 }
681
682 for (unsigned SuperID : RC->superclasses()) {
683 if (getRegSizeInBits(RC: *getRegClass(i: SuperID)) != getRegSizeInBits(RC: *RC))
684 continue;
685
686 switch (SuperID) {
687 case PPC::VSSRCRegClassID:
688 return Subtarget.hasP8Vector() ? getRegClass(i: SuperID)
689 : DefaultSuperclass;
690 case PPC::VSFRCRegClassID:
691 case PPC::VSRCRegClassID:
692 return getRegClass(i: SuperID);
693 case PPC::VSRpRCRegClassID:
694 return Subtarget.pairedVectorMemops() ? getRegClass(i: SuperID)
695 : DefaultSuperclass;
696 case PPC::ACCRCRegClassID:
697 case PPC::UACCRCRegClassID:
698 return Subtarget.hasMMA() ? getRegClass(i: SuperID) : DefaultSuperclass;
699 }
700 }
701 }
702
703 return DefaultSuperclass;
704}
705
706//===----------------------------------------------------------------------===//
707// Stack Frame Processing methods
708//===----------------------------------------------------------------------===//
709
710/// lowerDynamicAlloc - Generate the code for allocating an object in the
711/// current frame. The sequence of code will be in the general form
712///
713/// addi R0, SP, \#frameSize ; get the address of the previous frame
714/// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size
715/// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation
716///
717void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const {
718 // Get the instruction.
719 MachineInstr &MI = *II;
720 // Get the instruction's basic block.
721 MachineBasicBlock &MBB = *MI.getParent();
722 // Get the basic block's function.
723 MachineFunction &MF = *MBB.getParent();
724 // Get the frame info.
725 MachineFrameInfo &MFI = MF.getFrameInfo();
726 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
727 // Get the instruction info.
728 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
729 // Determine whether 64-bit pointers are used.
730 bool LP64 = TM.isPPC64();
731 DebugLoc dl = MI.getDebugLoc();
732
733 // Get the maximum call stack size.
734 unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
735 Align MaxAlign = MFI.getMaxAlign();
736 assert(isAligned(MaxAlign, maxCallFrameSize) &&
737 "Maximum call-frame size not sufficiently aligned");
738 (void)MaxAlign;
739
740 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
741 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
742 Register Reg = MF.getRegInfo().createVirtualRegister(RegClass: LP64 ? G8RC : GPRC);
743 bool KillNegSizeReg = MI.getOperand(i: 1).isKill();
744 Register NegSizeReg = MI.getOperand(i: 1).getReg();
745
746 prepareDynamicAlloca(II, NegSizeReg, KillNegSizeReg, FramePointer&: Reg);
747 // Grow the stack and update the stack pointer link, then determine the
748 // address of new allocated space.
749 if (LP64) {
750 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: PPC::STDUX), DestReg: PPC::X1)
751 .addReg(RegNo: Reg, Flags: RegState::Kill)
752 .addReg(RegNo: PPC::X1)
753 .addReg(RegNo: NegSizeReg, Flags: getKillRegState(B: KillNegSizeReg));
754 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: PPC::ADDI8), DestReg: MI.getOperand(i: 0).getReg())
755 .addReg(RegNo: PPC::X1)
756 .addImm(Val: maxCallFrameSize);
757 } else {
758 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: PPC::STWUX), DestReg: PPC::R1)
759 .addReg(RegNo: Reg, Flags: RegState::Kill)
760 .addReg(RegNo: PPC::R1)
761 .addReg(RegNo: NegSizeReg, Flags: getKillRegState(B: KillNegSizeReg));
762 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: PPC::ADDI), DestReg: MI.getOperand(i: 0).getReg())
763 .addReg(RegNo: PPC::R1)
764 .addImm(Val: maxCallFrameSize);
765 }
766
767 // Discard the DYNALLOC instruction.
768 MBB.erase(I: II);
769}
770
771/// To accomplish dynamic stack allocation, we have to calculate exact size
772/// subtracted from the stack pointer according alignment information and get
773/// previous frame pointer.
774void PPCRegisterInfo::prepareDynamicAlloca(MachineBasicBlock::iterator II,
775 Register &NegSizeReg,
776 bool &KillNegSizeReg,
777 Register &FramePointer) const {
778 // Get the instruction.
779 MachineInstr &MI = *II;
780 // Get the instruction's basic block.
781 MachineBasicBlock &MBB = *MI.getParent();
782 // Get the basic block's function.
783 MachineFunction &MF = *MBB.getParent();
784 // Get the frame info.
785 MachineFrameInfo &MFI = MF.getFrameInfo();
786 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
787 // Get the instruction info.
788 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
789 // Determine whether 64-bit pointers are used.
790 bool LP64 = TM.isPPC64();
791 DebugLoc dl = MI.getDebugLoc();
792 // Get the total frame size.
793 unsigned FrameSize = MFI.getStackSize();
794
795 // Get stack alignments.
796 const PPCFrameLowering *TFI = getFrameLowering(MF);
797 Align TargetAlign = TFI->getStackAlign();
798 Align MaxAlign = MFI.getMaxAlign();
799
800 // Determine the previous frame's address. If FrameSize can't be
801 // represented as 16 bits or we need special alignment, then we load the
802 // previous frame's address from 0(SP). Why not do an addis of the hi?
803 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero.
804 // Constructing the constant and adding would take 3 instructions.
805 // Fortunately, a frame greater than 32K is rare.
806 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
807 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
808
809 if (MaxAlign < TargetAlign && isInt<16>(x: FrameSize)) {
810 if (LP64)
811 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: PPC::ADDI8), DestReg: FramePointer)
812 .addReg(RegNo: PPC::X31)
813 .addImm(Val: FrameSize);
814 else
815 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: PPC::ADDI), DestReg: FramePointer)
816 .addReg(RegNo: PPC::R31)
817 .addImm(Val: FrameSize);
818 } else if (LP64) {
819 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: PPC::LD), DestReg: FramePointer)
820 .addImm(Val: 0)
821 .addReg(RegNo: PPC::X1);
822 } else {
823 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: PPC::LWZ), DestReg: FramePointer)
824 .addImm(Val: 0)
825 .addReg(RegNo: PPC::R1);
826 }
827 // Determine the actual NegSizeReg according to alignment info.
828 if (LP64) {
829 if (MaxAlign > TargetAlign) {
830 unsigned UnalNegSizeReg = NegSizeReg;
831 NegSizeReg = MF.getRegInfo().createVirtualRegister(RegClass: G8RC);
832
833 // Unfortunately, there is no andi, only andi., and we can't insert that
834 // here because we might clobber cr0 while it is live.
835 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: PPC::LI8), DestReg: NegSizeReg)
836 .addImm(Val: ~(MaxAlign.value() - 1));
837
838 unsigned NegSizeReg1 = NegSizeReg;
839 NegSizeReg = MF.getRegInfo().createVirtualRegister(RegClass: G8RC);
840 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: PPC::AND8), DestReg: NegSizeReg)
841 .addReg(RegNo: UnalNegSizeReg, Flags: getKillRegState(B: KillNegSizeReg))
842 .addReg(RegNo: NegSizeReg1, Flags: RegState::Kill);
843 KillNegSizeReg = true;
844 }
845 } else {
846 if (MaxAlign > TargetAlign) {
847 unsigned UnalNegSizeReg = NegSizeReg;
848 NegSizeReg = MF.getRegInfo().createVirtualRegister(RegClass: GPRC);
849
850 // Unfortunately, there is no andi, only andi., and we can't insert that
851 // here because we might clobber cr0 while it is live.
852 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: PPC::LI), DestReg: NegSizeReg)
853 .addImm(Val: ~(MaxAlign.value() - 1));
854
855 unsigned NegSizeReg1 = NegSizeReg;
856 NegSizeReg = MF.getRegInfo().createVirtualRegister(RegClass: GPRC);
857 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: PPC::AND), DestReg: NegSizeReg)
858 .addReg(RegNo: UnalNegSizeReg, Flags: getKillRegState(B: KillNegSizeReg))
859 .addReg(RegNo: NegSizeReg1, Flags: RegState::Kill);
860 KillNegSizeReg = true;
861 }
862 }
863}
864
865void PPCRegisterInfo::lowerPrepareProbedAlloca(
866 MachineBasicBlock::iterator II) const {
867 MachineInstr &MI = *II;
868 // Get the instruction's basic block.
869 MachineBasicBlock &MBB = *MI.getParent();
870 // Get the basic block's function.
871 MachineFunction &MF = *MBB.getParent();
872 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
873 // Get the instruction info.
874 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
875 // Determine whether 64-bit pointers are used.
876 bool LP64 = TM.isPPC64();
877 DebugLoc dl = MI.getDebugLoc();
878 Register FramePointer = MI.getOperand(i: 0).getReg();
879 const Register ActualNegSizeReg = MI.getOperand(i: 1).getReg();
880 bool KillNegSizeReg = MI.getOperand(i: 2).isKill();
881 Register NegSizeReg = MI.getOperand(i: 2).getReg();
882 const MCInstrDesc &CopyInst = TII.get(Opcode: LP64 ? PPC::OR8 : PPC::OR);
883 // RegAllocator might allocate FramePointer and NegSizeReg in the same phyreg.
884 if (FramePointer == NegSizeReg) {
885 assert(KillNegSizeReg && "FramePointer is a def and NegSizeReg is an use, "
886 "NegSizeReg should be killed");
887 // FramePointer is clobbered earlier than the use of NegSizeReg in
888 // prepareDynamicAlloca, save NegSizeReg in ActualNegSizeReg to avoid
889 // misuse.
890 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: CopyInst, DestReg: ActualNegSizeReg)
891 .addReg(RegNo: NegSizeReg)
892 .addReg(RegNo: NegSizeReg);
893 NegSizeReg = ActualNegSizeReg;
894 KillNegSizeReg = false;
895 }
896 prepareDynamicAlloca(II, NegSizeReg, KillNegSizeReg, FramePointer);
897 // NegSizeReg might be updated in prepareDynamicAlloca if MaxAlign >
898 // TargetAlign.
899 if (NegSizeReg != ActualNegSizeReg)
900 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: CopyInst, DestReg: ActualNegSizeReg)
901 .addReg(RegNo: NegSizeReg)
902 .addReg(RegNo: NegSizeReg);
903 MBB.erase(I: II);
904}
905
906void PPCRegisterInfo::lowerDynamicAreaOffset(
907 MachineBasicBlock::iterator II) const {
908 // Get the instruction.
909 MachineInstr &MI = *II;
910 // Get the instruction's basic block.
911 MachineBasicBlock &MBB = *MI.getParent();
912 // Get the basic block's function.
913 MachineFunction &MF = *MBB.getParent();
914 // Get the frame info.
915 MachineFrameInfo &MFI = MF.getFrameInfo();
916 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
917 // Get the instruction info.
918 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
919
920 unsigned maxCallFrameSize = MFI.getMaxCallFrameSize();
921 bool is64Bit = TM.isPPC64();
922 DebugLoc dl = MI.getDebugLoc();
923 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: is64Bit ? PPC::LI8 : PPC::LI),
924 DestReg: MI.getOperand(i: 0).getReg())
925 .addImm(Val: maxCallFrameSize);
926 MBB.erase(I: II);
927}
928
929/// lowerCRSpilling - Generate the code for spilling a CR register. Instead of
930/// reserving a whole register (R0), we scrounge for one here. This generates
931/// code like this:
932///
933/// mfcr rA ; Move the conditional register into GPR rA.
934/// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot.
935/// stw rA, FI ; Store rA to the frame.
936///
937void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
938 unsigned FrameIndex) const {
939 // Get the instruction.
940 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
941 // Get the instruction's basic block.
942 MachineBasicBlock &MBB = *MI.getParent();
943 MachineFunction &MF = *MBB.getParent();
944 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
945 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
946 DebugLoc dl = MI.getDebugLoc();
947
948 bool LP64 = TM.isPPC64();
949 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
950 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
951
952 Register Reg = MF.getRegInfo().createVirtualRegister(RegClass: LP64 ? G8RC : GPRC);
953 Register SrcReg = MI.getOperand(i: 0).getReg();
954
955 // We need to store the CR in the low 4-bits of the saved value. First, issue
956 // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg.
957 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), DestReg: Reg)
958 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: MI.getOperand(i: 0).isKill()));
959
960 // If the saved register wasn't CR0, shift the bits left so that they are in
961 // CR0's slot.
962 if (SrcReg != PPC::CR0) {
963 Register Reg1 = Reg;
964 Reg = MF.getRegInfo().createVirtualRegister(RegClass: LP64 ? G8RC : GPRC);
965
966 // rlwinm rA, rA, ShiftBits, 0, 31.
967 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::RLWINM8 : PPC::RLWINM), DestReg: Reg)
968 .addReg(RegNo: Reg1, Flags: RegState::Kill)
969 .addImm(Val: getEncodingValue(Reg: SrcReg) * 4)
970 .addImm(Val: 0)
971 .addImm(Val: 31);
972 }
973
974 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::STW8 : PPC::STW))
975 .addReg(RegNo: Reg, Flags: RegState::Kill),
976 FI: FrameIndex);
977
978 // Discard the pseudo instruction.
979 MBB.erase(I: II);
980}
981
982void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
983 unsigned FrameIndex) const {
984 // Get the instruction.
985 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
986 // Get the instruction's basic block.
987 MachineBasicBlock &MBB = *MI.getParent();
988 MachineFunction &MF = *MBB.getParent();
989 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
990 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
991 DebugLoc dl = MI.getDebugLoc();
992
993 bool LP64 = TM.isPPC64();
994 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
995 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
996
997 Register Reg = MF.getRegInfo().createVirtualRegister(RegClass: LP64 ? G8RC : GPRC);
998 Register DestReg = MI.getOperand(i: 0).getReg();
999 assert(MI.definesRegister(DestReg, /*TRI=*/nullptr) &&
1000 "RESTORE_CR does not define its destination");
1001
1002 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::LWZ8 : PPC::LWZ),
1003 DestReg: Reg), FI: FrameIndex);
1004
1005 // If the reloaded register isn't CR0, shift the bits right so that they are
1006 // in the right CR's slot.
1007 if (DestReg != PPC::CR0) {
1008 Register Reg1 = Reg;
1009 Reg = MF.getRegInfo().createVirtualRegister(RegClass: LP64 ? G8RC : GPRC);
1010
1011 unsigned ShiftBits = getEncodingValue(Reg: DestReg)*4;
1012 // rlwinm r11, r11, 32-ShiftBits, 0, 31.
1013 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::RLWINM8 : PPC::RLWINM), DestReg: Reg)
1014 .addReg(RegNo: Reg1, Flags: RegState::Kill).addImm(Val: 32-ShiftBits).addImm(Val: 0)
1015 .addImm(Val: 31);
1016 }
1017
1018 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg)
1019 .addReg(RegNo: Reg, Flags: RegState::Kill);
1020
1021 // Discard the pseudo instruction.
1022 MBB.erase(I: II);
1023}
1024
1025void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II,
1026 unsigned FrameIndex) const {
1027 // Get the instruction.
1028 MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset>
1029 // Get the instruction's basic block.
1030 MachineBasicBlock &MBB = *MI.getParent();
1031 MachineFunction &MF = *MBB.getParent();
1032 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1033 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1034 const TargetRegisterInfo* TRI = Subtarget.getRegisterInfo();
1035 DebugLoc dl = MI.getDebugLoc();
1036
1037 bool LP64 = TM.isPPC64();
1038 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1039 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1040
1041 Register Reg = MF.getRegInfo().createVirtualRegister(RegClass: LP64 ? G8RC : GPRC);
1042 Register SrcReg = MI.getOperand(i: 0).getReg();
1043
1044 // Search up the BB to find the definition of the CR bit.
1045 MachineBasicBlock::reverse_iterator Ins = MI;
1046 MachineBasicBlock::reverse_iterator Rend = MBB.rend();
1047 ++Ins;
1048 unsigned CRBitSpillDistance = 0;
1049 bool SeenUse = false;
1050 for (; Ins != Rend; ++Ins) {
1051 // Definition found.
1052 if (Ins->modifiesRegister(Reg: SrcReg, TRI))
1053 break;
1054 // Use found.
1055 if (Ins->readsRegister(Reg: SrcReg, TRI))
1056 SeenUse = true;
1057 // Unable to find CR bit definition within maximum search distance.
1058 if (CRBitSpillDistance == MaxCRBitSpillDist) {
1059 Ins = MI;
1060 break;
1061 }
1062 // Skip debug instructions when counting CR bit spill distance.
1063 if (!Ins->isDebugInstr())
1064 CRBitSpillDistance++;
1065 }
1066
1067 // Unable to find the definition of the CR bit in the MBB.
1068 if (Ins == MBB.rend())
1069 Ins = MI;
1070
1071 bool SpillsKnownBit = false;
1072 // There is no need to extract the CR bit if its value is already known.
1073 switch (Ins->getOpcode()) {
1074 case PPC::CRUNSET:
1075 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::LI8 : PPC::LI), DestReg: Reg)
1076 .addImm(Val: 0);
1077 SpillsKnownBit = true;
1078 break;
1079 case PPC::CRSET:
1080 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::LIS8 : PPC::LIS), DestReg: Reg)
1081 .addImm(Val: -32768);
1082 SpillsKnownBit = true;
1083 break;
1084 default:
1085 // When spilling a CR bit, the super register may not be explicitly defined
1086 // (i.e. it can be defined by a CR-logical that only defines the subreg) so
1087 // we state that the CR field is undef. Also, in order to preserve the kill
1088 // flag on the CR bit, we add it as an implicit use.
1089
1090 // On Power10, we can use SETNBC to spill all CR bits. SETNBC will set all
1091 // bits (specifically, it produces a -1 if the CR bit is set). Ultimately,
1092 // the bit that is of importance to us is bit 32 (bit 0 of a 32-bit
1093 // register), and SETNBC will set this.
1094 if (Subtarget.isISA3_1()) {
1095 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::SETNBC8 : PPC::SETNBC), DestReg: Reg)
1096 .addReg(RegNo: SrcReg, Flags: RegState::Undef)
1097 .addReg(RegNo: SrcReg, Flags: RegState::Implicit |
1098 getKillRegState(B: MI.getOperand(i: 0).isKill()));
1099 break;
1100 }
1101
1102 // On Power9, we can use SETB to extract the LT bit. This only works for
1103 // the LT bit since SETB produces -1/1/0 for LT/GT/<neither>. So the value
1104 // of the bit we care about (32-bit sign bit) will be set to the value of
1105 // the LT bit (regardless of the other bits in the CR field).
1106 if (Subtarget.isISA3_0()) {
1107 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR1LT ||
1108 SrcReg == PPC::CR2LT || SrcReg == PPC::CR3LT ||
1109 SrcReg == PPC::CR4LT || SrcReg == PPC::CR5LT ||
1110 SrcReg == PPC::CR6LT || SrcReg == PPC::CR7LT) {
1111 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::SETB8 : PPC::SETB), DestReg: Reg)
1112 .addReg(RegNo: getCRFromCRBit(SrcReg), Flags: RegState::Undef)
1113 .addReg(RegNo: SrcReg, Flags: RegState::Implicit |
1114 getKillRegState(B: MI.getOperand(i: 0).isKill()));
1115 break;
1116 }
1117 }
1118
1119 // We need to move the CR field that contains the CR bit we are spilling.
1120 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), DestReg: Reg)
1121 .addReg(RegNo: getCRFromCRBit(SrcReg), Flags: RegState::Undef)
1122 .addReg(RegNo: SrcReg,
1123 Flags: RegState::Implicit | getKillRegState(B: MI.getOperand(i: 0).isKill()));
1124
1125 // If the saved register wasn't CR0LT, shift the bits left so that the bit
1126 // to store is the first one. Mask all but that bit.
1127 Register Reg1 = Reg;
1128 Reg = MF.getRegInfo().createVirtualRegister(RegClass: LP64 ? G8RC : GPRC);
1129
1130 // rlwinm rA, rA, ShiftBits, 0, 0.
1131 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::RLWINM8 : PPC::RLWINM), DestReg: Reg)
1132 .addReg(RegNo: Reg1, Flags: RegState::Kill)
1133 .addImm(Val: getEncodingValue(Reg: SrcReg))
1134 .addImm(Val: 0).addImm(Val: 0);
1135 }
1136 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::STW8 : PPC::STW))
1137 .addReg(RegNo: Reg, Flags: RegState::Kill),
1138 FI: FrameIndex);
1139
1140 bool KillsCRBit = MI.killsRegister(Reg: SrcReg, TRI);
1141 // Discard the pseudo instruction.
1142 MBB.erase(I: II);
1143 if (SpillsKnownBit && KillsCRBit && !SeenUse) {
1144 Ins->setDesc(TII.get(Opcode: PPC::UNENCODED_NOP));
1145 Ins->removeOperand(OpNo: 0);
1146 }
1147}
1148
1149void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II,
1150 unsigned FrameIndex) const {
1151 // Get the instruction.
1152 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset>
1153 // Get the instruction's basic block.
1154 MachineBasicBlock &MBB = *MI.getParent();
1155 MachineFunction &MF = *MBB.getParent();
1156 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1157 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1158 DebugLoc dl = MI.getDebugLoc();
1159
1160 bool LP64 = TM.isPPC64();
1161 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1162 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1163
1164 Register Reg = MF.getRegInfo().createVirtualRegister(RegClass: LP64 ? G8RC : GPRC);
1165 Register DestReg = MI.getOperand(i: 0).getReg();
1166 assert(MI.definesRegister(DestReg, /*TRI=*/nullptr) &&
1167 "RESTORE_CRBIT does not define its destination");
1168
1169 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::LWZ8 : PPC::LWZ),
1170 DestReg: Reg), FI: FrameIndex);
1171
1172 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: TargetOpcode::IMPLICIT_DEF), DestReg);
1173
1174 Register RegO = MF.getRegInfo().createVirtualRegister(RegClass: LP64 ? G8RC : GPRC);
1175 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), DestReg: RegO)
1176 .addReg(RegNo: getCRFromCRBit(SrcReg: DestReg));
1177
1178 unsigned ShiftBits = getEncodingValue(Reg: DestReg);
1179 // rlwimi r11, r10, 32-ShiftBits, ..., ...
1180 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), DestReg: RegO)
1181 .addReg(RegNo: RegO, Flags: RegState::Kill)
1182 .addReg(RegNo: Reg, Flags: RegState::Kill)
1183 .addImm(Val: ShiftBits ? 32 - ShiftBits : 0)
1184 .addImm(Val: ShiftBits)
1185 .addImm(Val: ShiftBits);
1186
1187 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: LP64 ? PPC::MTOCRF8 : PPC::MTOCRF),
1188 DestReg: getCRFromCRBit(SrcReg: DestReg))
1189 .addReg(RegNo: RegO, Flags: RegState::Kill)
1190 // Make sure we have a use dependency all the way through this
1191 // sequence of instructions. We can't have the other bits in the CR
1192 // modified in between the mfocrf and the mtocrf.
1193 .addReg(RegNo: getCRFromCRBit(SrcReg: DestReg), Flags: RegState::Implicit);
1194
1195 // Discard the pseudo instruction.
1196 MBB.erase(I: II);
1197}
1198
1199void PPCRegisterInfo::emitAccCopyInfo(MachineBasicBlock &MBB,
1200 MCRegister DestReg, MCRegister SrcReg) {
1201#ifdef NDEBUG
1202 return;
1203#else
1204 if (ReportAccMoves) {
1205 std::string Dest = PPC::ACCRCRegClass.contains(DestReg) ? "acc" : "uacc";
1206 std::string Src = PPC::ACCRCRegClass.contains(SrcReg) ? "acc" : "uacc";
1207 dbgs() << "Emitting copy from " << Src << " to " << Dest << ":\n";
1208 MBB.dump();
1209 }
1210#endif
1211}
1212
1213static void emitAccSpillRestoreInfo(MachineBasicBlock &MBB, bool IsPrimed,
1214 bool IsRestore) {
1215#ifdef NDEBUG
1216 return;
1217#else
1218 if (ReportAccMoves) {
1219 dbgs() << "Emitting " << (IsPrimed ? "acc" : "uacc") << " register "
1220 << (IsRestore ? "restore" : "spill") << ":\n";
1221 MBB.dump();
1222 }
1223#endif
1224}
1225
1226void PPCRegisterInfo::spillRegPair(MachineBasicBlock &MBB,
1227 MachineBasicBlock::iterator II, DebugLoc DL,
1228 const TargetInstrInfo &TII,
1229 unsigned FrameIndex, bool IsLittleEndian,
1230 bool IsKilled, Register Reg,
1231 int Offset) const {
1232
1233 // This function does not support virtual registers.
1234 assert(!Reg.isVirtual() &&
1235 "Spilling register pairs does not support virtual registers.");
1236
1237 addFrameReference(
1238 MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::STXV))
1239 .addReg(RegNo: TargetRegisterInfo::getSubReg(Reg, Idx: PPC::sub_vsx0),
1240 Flags: getKillRegState(B: IsKilled)),
1241 FI: FrameIndex, Offset);
1242
1243 addFrameReference(
1244 MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::STXV))
1245 .addReg(RegNo: TargetRegisterInfo::getSubReg(Reg, Idx: PPC::sub_vsx1),
1246 Flags: getKillRegState(B: IsKilled)),
1247 FI: FrameIndex, Offset: IsLittleEndian ? Offset - 16 : Offset + 16);
1248}
1249
1250/// Remove any STXVP[X] instructions and split them out into a pair of
1251/// STXV[X] instructions if --disable-auto-paired-vec-st is specified on
1252/// the command line.
1253void PPCRegisterInfo::lowerOctWordSpilling(MachineBasicBlock::iterator II,
1254 unsigned FrameIndex) const {
1255 assert(DisableAutoPairedVecSt &&
1256 "Expecting to do this only if paired vector stores are disabled.");
1257 MachineInstr &MI = *II; // STXVP <SrcReg>, <offset>
1258 MachineBasicBlock &MBB = *MI.getParent();
1259 MachineFunction &MF = *MBB.getParent();
1260 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1261 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1262 DebugLoc DL = MI.getDebugLoc();
1263 Register SrcReg = MI.getOperand(i: 0).getReg();
1264 bool IsLittleEndian = Subtarget.isLittleEndian();
1265 bool IsKilled = MI.getOperand(i: 0).isKill();
1266
1267 spillRegPair(MBB, II, DL, TII, FrameIndex, IsLittleEndian, IsKilled, Reg: SrcReg,
1268 Offset: IsLittleEndian ? 16 : 0);
1269
1270 // Discard the original instruction.
1271 MBB.erase(I: II);
1272}
1273
1274static void emitWAccSpillRestoreInfo(MachineBasicBlock &MBB, bool IsRestore) {
1275#ifdef NDEBUG
1276 return;
1277#else
1278 if (ReportAccMoves) {
1279 dbgs() << "Emitting wacc register " << (IsRestore ? "restore" : "spill")
1280 << ":\n";
1281 MBB.dump();
1282 }
1283#endif
1284}
1285
1286/// lowerACCSpilling - Generate the code for spilling the accumulator register.
1287/// Similarly to other spills/reloads that use pseudo-ops, we do not actually
1288/// eliminate the FrameIndex here nor compute the stack offset. We simply
1289/// create a real instruction with an FI and rely on eliminateFrameIndex to
1290/// handle the FI elimination.
1291void PPCRegisterInfo::lowerACCSpilling(MachineBasicBlock::iterator II,
1292 unsigned FrameIndex) const {
1293 MachineInstr &MI = *II; // SPILL_ACC <SrcReg>, <offset>
1294 MachineBasicBlock &MBB = *MI.getParent();
1295 MachineFunction &MF = *MBB.getParent();
1296 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1297 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1298 DebugLoc DL = MI.getDebugLoc();
1299 Register SrcReg = MI.getOperand(i: 0).getReg();
1300 bool IsKilled = MI.getOperand(i: 0).isKill();
1301
1302 bool IsPrimed = PPC::ACCRCRegClass.contains(Reg: SrcReg);
1303 bool IsLittleEndian = Subtarget.isLittleEndian();
1304
1305 emitAccSpillRestoreInfo(MBB, IsPrimed, IsRestore: false);
1306
1307 // De-prime the register being spilled, create two stores for the pair
1308 // subregisters accounting for endianness and then re-prime the register if
1309 // it isn't killed. This uses the Offset parameter to addFrameReference() to
1310 // adjust the offset of the store that is within the 64-byte stack slot.
1311 if (IsPrimed)
1312 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::XXMFACC), DestReg: SrcReg).addReg(RegNo: SrcReg);
1313 if (DisableAutoPairedVecSt) {
1314 spillRegPair(MBB, II, DL, TII, FrameIndex, IsLittleEndian, IsKilled,
1315 Reg: TargetRegisterInfo::getSubReg(Reg: SrcReg, Idx: PPC::sub_pair0),
1316 Offset: IsLittleEndian ? 48 : 0);
1317 spillRegPair(MBB, II, DL, TII, FrameIndex, IsLittleEndian, IsKilled,
1318 Reg: TargetRegisterInfo::getSubReg(Reg: SrcReg, Idx: PPC::sub_pair1),
1319 Offset: IsLittleEndian ? 16 : 32);
1320 } else {
1321 addFrameReference(
1322 MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::STXVP))
1323 .addReg(RegNo: TargetRegisterInfo::getSubReg(Reg: SrcReg, Idx: PPC::sub_pair0),
1324 Flags: getKillRegState(B: IsKilled)),
1325 FI: FrameIndex, Offset: IsLittleEndian ? 32 : 0);
1326 addFrameReference(
1327 MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::STXVP))
1328 .addReg(RegNo: TargetRegisterInfo::getSubReg(Reg: SrcReg, Idx: PPC::sub_pair1),
1329 Flags: getKillRegState(B: IsKilled)),
1330 FI: FrameIndex, Offset: IsLittleEndian ? 0 : 32);
1331 }
1332 if (IsPrimed && !IsKilled)
1333 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::XXMTACC), DestReg: SrcReg).addReg(RegNo: SrcReg);
1334
1335 // Discard the pseudo instruction.
1336 MBB.erase(I: II);
1337}
1338
1339/// lowerACCRestore - Generate the code to restore the accumulator register.
1340void PPCRegisterInfo::lowerACCRestore(MachineBasicBlock::iterator II,
1341 unsigned FrameIndex) const {
1342 MachineInstr &MI = *II; // <DestReg> = RESTORE_ACC <offset>
1343 MachineBasicBlock &MBB = *MI.getParent();
1344 MachineFunction &MF = *MBB.getParent();
1345 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1346 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1347 DebugLoc DL = MI.getDebugLoc();
1348
1349 Register DestReg = MI.getOperand(i: 0).getReg();
1350 assert(MI.definesRegister(DestReg, /*TRI=*/nullptr) &&
1351 "RESTORE_ACC does not define its destination");
1352
1353 bool IsPrimed = PPC::ACCRCRegClass.contains(Reg: DestReg);
1354 Register Reg =
1355 PPC::VSRp0 + (DestReg - (IsPrimed ? PPC::ACC0 : PPC::UACC0)) * 2;
1356 bool IsLittleEndian = Subtarget.isLittleEndian();
1357
1358 emitAccSpillRestoreInfo(MBB, IsPrimed, IsRestore: true);
1359
1360 // Create two loads for the pair subregisters accounting for endianness and
1361 // then prime the accumulator register being restored.
1362 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::LXVP), DestReg: Reg),
1363 FI: FrameIndex, Offset: IsLittleEndian ? 32 : 0);
1364 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::LXVP), DestReg: Reg + 1),
1365 FI: FrameIndex, Offset: IsLittleEndian ? 0 : 32);
1366 if (IsPrimed)
1367 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::XXMTACC), DestReg).addReg(RegNo: DestReg);
1368
1369 // Discard the pseudo instruction.
1370 MBB.erase(I: II);
1371}
1372
1373/// lowerWACCSpilling - Generate the code for spilling the wide accumulator
1374/// register.
1375void PPCRegisterInfo::lowerWACCSpilling(MachineBasicBlock::iterator II,
1376 unsigned FrameIndex) const {
1377 MachineInstr &MI = *II; // SPILL_WACC <SrcReg>, <offset>
1378 MachineBasicBlock &MBB = *MI.getParent();
1379 MachineFunction &MF = *MBB.getParent();
1380 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1381 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1382 DebugLoc DL = MI.getDebugLoc();
1383 bool IsLittleEndian = Subtarget.isLittleEndian();
1384
1385 emitWAccSpillRestoreInfo(MBB, IsRestore: false);
1386
1387 const TargetRegisterClass *RC = &PPC::VSRpRCRegClass;
1388 Register VSRpReg0 = MF.getRegInfo().createVirtualRegister(RegClass: RC);
1389 Register VSRpReg1 = MF.getRegInfo().createVirtualRegister(RegClass: RC);
1390 Register SrcReg = MI.getOperand(i: 0).getReg();
1391
1392 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::DMXXEXTFDMR512), DestReg: VSRpReg0)
1393 .addDef(RegNo: VSRpReg1)
1394 .addReg(RegNo: SrcReg);
1395
1396 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::STXVP))
1397 .addReg(RegNo: VSRpReg0, Flags: RegState::Kill),
1398 FI: FrameIndex, Offset: IsLittleEndian ? 32 : 0);
1399 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::STXVP))
1400 .addReg(RegNo: VSRpReg1, Flags: RegState::Kill),
1401 FI: FrameIndex, Offset: IsLittleEndian ? 0 : 32);
1402
1403 // Discard the pseudo instruction.
1404 MBB.erase(I: II);
1405}
1406
1407/// lowerWACCRestore - Generate the code to restore the wide accumulator
1408/// register.
1409void PPCRegisterInfo::lowerWACCRestore(MachineBasicBlock::iterator II,
1410 unsigned FrameIndex) const {
1411 MachineInstr &MI = *II; // <DestReg> = RESTORE_WACC <offset>
1412 MachineBasicBlock &MBB = *MI.getParent();
1413 MachineFunction &MF = *MBB.getParent();
1414 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1415 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1416 DebugLoc DL = MI.getDebugLoc();
1417 bool IsLittleEndian = Subtarget.isLittleEndian();
1418
1419 emitWAccSpillRestoreInfo(MBB, IsRestore: true);
1420
1421 const TargetRegisterClass *RC = &PPC::VSRpRCRegClass;
1422 Register VSRpReg0 = MF.getRegInfo().createVirtualRegister(RegClass: RC);
1423 Register VSRpReg1 = MF.getRegInfo().createVirtualRegister(RegClass: RC);
1424 Register DestReg = MI.getOperand(i: 0).getReg();
1425
1426 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::LXVP), DestReg: VSRpReg0),
1427 FI: FrameIndex, Offset: IsLittleEndian ? 32 : 0);
1428 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::LXVP), DestReg: VSRpReg1),
1429 FI: FrameIndex, Offset: IsLittleEndian ? 0 : 32);
1430
1431 // Kill VSRpReg0, VSRpReg1 (killedRegState::Killed)
1432 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::DMXXINSTDMR512), DestReg)
1433 .addReg(RegNo: VSRpReg0, Flags: RegState::Kill)
1434 .addReg(RegNo: VSRpReg1, Flags: RegState::Kill);
1435
1436 // Discard the pseudo instruction.
1437 MBB.erase(I: II);
1438}
1439
1440/// lowerQuadwordSpilling - Generate code to spill paired general register.
1441void PPCRegisterInfo::lowerQuadwordSpilling(MachineBasicBlock::iterator II,
1442 unsigned FrameIndex) const {
1443 MachineInstr &MI = *II;
1444 MachineBasicBlock &MBB = *MI.getParent();
1445 MachineFunction &MF = *MBB.getParent();
1446 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1447 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1448 DebugLoc DL = MI.getDebugLoc();
1449
1450 Register SrcReg = MI.getOperand(i: 0).getReg();
1451 bool IsKilled = MI.getOperand(i: 0).isKill();
1452
1453 Register Reg = PPC::X0 + (SrcReg - PPC::G8p0) * 2;
1454 bool IsLittleEndian = Subtarget.isLittleEndian();
1455
1456 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::STD))
1457 .addReg(RegNo: Reg, Flags: getKillRegState(B: IsKilled)),
1458 FI: FrameIndex, Offset: IsLittleEndian ? 8 : 0);
1459 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::STD))
1460 .addReg(RegNo: Reg + 1, Flags: getKillRegState(B: IsKilled)),
1461 FI: FrameIndex, Offset: IsLittleEndian ? 0 : 8);
1462
1463 // Discard the pseudo instruction.
1464 MBB.erase(I: II);
1465}
1466
1467/// lowerQuadwordRestore - Generate code to restore paired general register.
1468void PPCRegisterInfo::lowerQuadwordRestore(MachineBasicBlock::iterator II,
1469 unsigned FrameIndex) const {
1470 MachineInstr &MI = *II;
1471 MachineBasicBlock &MBB = *MI.getParent();
1472 MachineFunction &MF = *MBB.getParent();
1473 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1474 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1475 DebugLoc DL = MI.getDebugLoc();
1476
1477 Register DestReg = MI.getOperand(i: 0).getReg();
1478 assert(MI.definesRegister(DestReg, /*TRI=*/nullptr) &&
1479 "RESTORE_QUADWORD does not define its destination");
1480
1481 Register Reg = PPC::X0 + (DestReg - PPC::G8p0) * 2;
1482 bool IsLittleEndian = Subtarget.isLittleEndian();
1483
1484 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::LD), DestReg: Reg), FI: FrameIndex,
1485 Offset: IsLittleEndian ? 8 : 0);
1486 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::LD), DestReg: Reg + 1), FI: FrameIndex,
1487 Offset: IsLittleEndian ? 0 : 8);
1488
1489 // Discard the pseudo instruction.
1490 MBB.erase(I: II);
1491}
1492
1493/// lowerDMRSpilling - Generate the code for spilling the DMR register.
1494void PPCRegisterInfo::lowerDMRSpilling(MachineBasicBlock::iterator II,
1495 unsigned FrameIndex) const {
1496 MachineInstr &MI = *II; // SPILL_DMR <SrcReg>, <offset>
1497 MachineBasicBlock &MBB = *MI.getParent();
1498 MachineFunction &MF = *MBB.getParent();
1499 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1500 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1501 DebugLoc DL = MI.getDebugLoc();
1502 bool IsLittleEndian = Subtarget.isLittleEndian();
1503
1504 // DMR is made up of WACC and WACC_HI, so DMXXEXTFDMR512 to spill
1505 // the corresponding 512 bits.
1506 const TargetRegisterClass *RC = &PPC::VSRpRCRegClass;
1507 auto spillDMR = [&](Register SrcReg, int BEIdx, int LEIdx) {
1508 auto spillWACC = [&](unsigned Opc, unsigned RegIdx, int IdxBE, int IdxLE) {
1509 Register VSRpReg0 = MF.getRegInfo().createVirtualRegister(RegClass: RC);
1510 Register VSRpReg1 = MF.getRegInfo().createVirtualRegister(RegClass: RC);
1511
1512 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: Opc), DestReg: VSRpReg0)
1513 .addDef(RegNo: VSRpReg1)
1514 .addReg(RegNo: TargetRegisterInfo::getSubReg(Reg: SrcReg, Idx: RegIdx));
1515
1516 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::STXVP))
1517 .addReg(RegNo: VSRpReg0, Flags: RegState::Kill),
1518 FI: FrameIndex, Offset: IsLittleEndian ? IdxLE : IdxBE);
1519 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::STXVP))
1520 .addReg(RegNo: VSRpReg1, Flags: RegState::Kill),
1521 FI: FrameIndex, Offset: IsLittleEndian ? IdxLE - 32 : IdxBE + 32);
1522 };
1523 spillWACC(PPC::DMXXEXTFDMR512, PPC::sub_wacc_lo, BEIdx, LEIdx);
1524 spillWACC(PPC::DMXXEXTFDMR512_HI, PPC::sub_wacc_hi, BEIdx + 64, LEIdx - 64);
1525 };
1526
1527 Register SrcReg = MI.getOperand(i: 0).getReg();
1528 if (MI.getOpcode() == PPC::SPILL_DMRP) {
1529 spillDMR(TargetRegisterInfo::getSubReg(Reg: SrcReg, Idx: PPC::sub_dmr1), 0, 96);
1530 spillDMR(TargetRegisterInfo::getSubReg(Reg: SrcReg, Idx: PPC::sub_dmr0), 128, 224);
1531 } else
1532 spillDMR(SrcReg, 0, 96);
1533
1534 // Discard the pseudo instruction.
1535 MBB.erase(I: II);
1536}
1537
1538/// lowerDMRRestore - Generate the code to restore the DMR register.
1539void PPCRegisterInfo::lowerDMRRestore(MachineBasicBlock::iterator II,
1540 unsigned FrameIndex) const {
1541 MachineInstr &MI = *II; // <DestReg> = RESTORE_DMR[P] <offset>
1542 MachineBasicBlock &MBB = *MI.getParent();
1543 MachineFunction &MF = *MBB.getParent();
1544 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1545 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1546 DebugLoc DL = MI.getDebugLoc();
1547 bool IsLittleEndian = Subtarget.isLittleEndian();
1548
1549 const TargetRegisterClass *RC = &PPC::VSRpRCRegClass;
1550 auto restoreDMR = [&](Register DestReg, int BEIdx, int LEIdx) {
1551 auto restoreWACC = [&](unsigned Opc, unsigned RegIdx, int IdxBE,
1552 int IdxLE) {
1553 Register VSRpReg0 = MF.getRegInfo().createVirtualRegister(RegClass: RC);
1554 Register VSRpReg1 = MF.getRegInfo().createVirtualRegister(RegClass: RC);
1555
1556 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::LXVP), DestReg: VSRpReg0),
1557 FI: FrameIndex, Offset: IsLittleEndian ? IdxLE : IdxBE);
1558 addFrameReference(MIB: BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: PPC::LXVP), DestReg: VSRpReg1),
1559 FI: FrameIndex, Offset: IsLittleEndian ? IdxLE - 32 : IdxBE + 32);
1560
1561 // Kill virtual registers (killedRegState::Killed).
1562 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: TII.get(Opcode: Opc),
1563 DestReg: TargetRegisterInfo::getSubReg(Reg: DestReg, Idx: RegIdx))
1564 .addReg(RegNo: VSRpReg0, Flags: RegState::Kill)
1565 .addReg(RegNo: VSRpReg1, Flags: RegState::Kill);
1566 };
1567 restoreWACC(PPC::DMXXINSTDMR512, PPC::sub_wacc_lo, BEIdx, LEIdx);
1568 restoreWACC(PPC::DMXXINSTDMR512_HI, PPC::sub_wacc_hi, BEIdx + 64,
1569 LEIdx - 64);
1570 };
1571
1572 Register DestReg = MI.getOperand(i: 0).getReg();
1573 if (MI.getOpcode() == PPC::RESTORE_DMRP) {
1574 restoreDMR(TargetRegisterInfo::getSubReg(Reg: DestReg, Idx: PPC::sub_dmr1), 0, 96);
1575 restoreDMR(TargetRegisterInfo::getSubReg(Reg: DestReg, Idx: PPC::sub_dmr0), 128, 224);
1576 } else
1577 restoreDMR(DestReg, 0, 96);
1578
1579 // Discard the pseudo instruction.
1580 MBB.erase(I: II);
1581}
1582
1583bool PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
1584 Register Reg, int &FrameIdx) const {
1585 // For the nonvolatile condition registers (CR2, CR3, CR4) return true to
1586 // prevent allocating an additional frame slot.
1587 // For 64-bit ELF and AIX, the CR save area is in the linkage area at SP+8,
1588 // for 32-bit AIX the CR save area is in the linkage area at SP+4.
1589 // We have created a FrameIndex to that spill slot to keep the CalleSaveInfos
1590 // valid.
1591 // For 32-bit ELF, we have previously created the stack slot if needed, so
1592 // return its FrameIdx.
1593 if (PPC::CR2 <= Reg && Reg <= PPC::CR4) {
1594 FrameIdx = MF.getInfo<PPCFunctionInfo>()->getCRSpillFrameIndex();
1595 return true;
1596 }
1597 return false;
1598}
1599
1600// If the offset must be a multiple of some value, return what that value is.
1601static unsigned offsetMinAlignForOpcode(unsigned OpC) {
1602 switch (OpC) {
1603 default:
1604 return 1;
1605 case PPC::LWA:
1606 case PPC::LWA_32:
1607 case PPC::LD:
1608 case PPC::LDU:
1609 case PPC::STD:
1610 case PPC::STDU:
1611 case PPC::DFLOADf32:
1612 case PPC::DFLOADf64:
1613 case PPC::DFSTOREf32:
1614 case PPC::DFSTOREf64:
1615 case PPC::LXSD:
1616 case PPC::LXSSP:
1617 case PPC::STXSD:
1618 case PPC::STXSSP:
1619 case PPC::STQ:
1620 return 4;
1621 case PPC::EVLDD:
1622 case PPC::EVSTDD:
1623 return 8;
1624 case PPC::LXV:
1625 case PPC::STXV:
1626 case PPC::LQ:
1627 case PPC::LXVP:
1628 case PPC::STXVP:
1629 return 16;
1630 }
1631}
1632
1633// If the offset must be a multiple of some value, return what that value is.
1634static unsigned offsetMinAlign(const MachineInstr &MI) {
1635 unsigned OpC = MI.getOpcode();
1636 return offsetMinAlignForOpcode(OpC);
1637}
1638
1639// Return the OffsetOperandNo given the FIOperandNum (and the instruction).
1640static unsigned getOffsetONFromFION(const MachineInstr &MI,
1641 unsigned FIOperandNum) {
1642 // Take into account whether it's an add or mem instruction
1643 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
1644 if (MI.isInlineAsm())
1645 OffsetOperandNo = FIOperandNum - 1;
1646 else if (MI.getOpcode() == TargetOpcode::STACKMAP ||
1647 MI.getOpcode() == TargetOpcode::PATCHPOINT)
1648 OffsetOperandNo = FIOperandNum + 1;
1649
1650 return OffsetOperandNo;
1651}
1652
1653bool
1654PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1655 int SPAdj, unsigned FIOperandNum,
1656 RegScavenger *RS) const {
1657 assert(SPAdj == 0 && "Unexpected");
1658
1659 // Get the instruction.
1660 MachineInstr &MI = *II;
1661 // Get the instruction's basic block.
1662 MachineBasicBlock &MBB = *MI.getParent();
1663 // Get the basic block's function.
1664 MachineFunction &MF = *MBB.getParent();
1665 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1666 // Get the instruction info.
1667 const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
1668 // Get the frame info.
1669 MachineFrameInfo &MFI = MF.getFrameInfo();
1670 DebugLoc dl = MI.getDebugLoc();
1671
1672 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
1673
1674 // Get the frame index.
1675 int FrameIndex = MI.getOperand(i: FIOperandNum).getIndex();
1676
1677 // Get the frame pointer save index. Users of this index are primarily
1678 // DYNALLOC instructions.
1679 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1680 int FPSI = FI->getFramePointerSaveIndex();
1681 // Get the instruction opcode.
1682 unsigned OpC = MI.getOpcode();
1683
1684 switch (OpC) {
1685 default:
1686 break;
1687 case PPC::DYNAREAOFFSET:
1688 case PPC::DYNAREAOFFSET8:
1689 lowerDynamicAreaOffset(II);
1690 // lowerDynamicAreaOffset erases II
1691 return true;
1692 case PPC::DYNALLOC:
1693 case PPC::DYNALLOC8: {
1694 // Special case for dynamic alloca.
1695 if (FPSI && FrameIndex == FPSI) {
1696 lowerDynamicAlloc(II); // lowerDynamicAlloc erases II
1697 return true;
1698 }
1699 break;
1700 }
1701 case PPC::PREPARE_PROBED_ALLOCA_64:
1702 case PPC::PREPARE_PROBED_ALLOCA_32:
1703 case PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64:
1704 case PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32: {
1705 if (FPSI && FrameIndex == FPSI) {
1706 lowerPrepareProbedAlloca(II); // lowerPrepareProbedAlloca erases II
1707 return true;
1708 }
1709 break;
1710 }
1711 case PPC::SPILL_CR:
1712 // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc.
1713 lowerCRSpilling(II, FrameIndex);
1714 return true;
1715 case PPC::RESTORE_CR:
1716 lowerCRRestore(II, FrameIndex);
1717 return true;
1718 case PPC::SPILL_CRBIT:
1719 lowerCRBitSpilling(II, FrameIndex);
1720 return true;
1721 case PPC::RESTORE_CRBIT:
1722 lowerCRBitRestore(II, FrameIndex);
1723 return true;
1724 case PPC::SPILL_ACC:
1725 case PPC::SPILL_UACC:
1726 lowerACCSpilling(II, FrameIndex);
1727 return true;
1728 case PPC::RESTORE_ACC:
1729 case PPC::RESTORE_UACC:
1730 lowerACCRestore(II, FrameIndex);
1731 return true;
1732 case PPC::STXVP: {
1733 if (DisableAutoPairedVecSt) {
1734 lowerOctWordSpilling(II, FrameIndex);
1735 return true;
1736 }
1737 break;
1738 }
1739 case PPC::SPILL_WACC:
1740 lowerWACCSpilling(II, FrameIndex);
1741 return true;
1742 case PPC::RESTORE_WACC:
1743 lowerWACCRestore(II, FrameIndex);
1744 return true;
1745 case PPC::SPILL_DMRP:
1746 case PPC::SPILL_DMR:
1747 lowerDMRSpilling(II, FrameIndex);
1748 return true;
1749 case PPC::RESTORE_DMRP:
1750 case PPC::RESTORE_DMR:
1751 lowerDMRRestore(II, FrameIndex);
1752 return true;
1753 case PPC::SPILL_QUADWORD:
1754 lowerQuadwordSpilling(II, FrameIndex);
1755 return true;
1756 case PPC::RESTORE_QUADWORD:
1757 lowerQuadwordRestore(II, FrameIndex);
1758 return true;
1759 }
1760
1761 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
1762 MI.getOperand(i: FIOperandNum).ChangeToRegister(
1763 Reg: FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), isDef: false);
1764
1765 // If the instruction is not present in ImmToIdxMap, then it has no immediate
1766 // form (and must be r+r).
1767 bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP &&
1768 OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(Val: OpC);
1769
1770 // Now add the frame object offset to the offset from r1.
1771 int64_t Offset = MFI.getObjectOffset(ObjectIdx: FrameIndex);
1772 Offset += MI.getOperand(i: OffsetOperandNo).getImm();
1773
1774 // If we're not using a Frame Pointer that has been set to the value of the
1775 // SP before having the stack size subtracted from it, then add the stack size
1776 // to Offset to get the correct offset.
1777 // Naked functions have stack size 0, although getStackSize may not reflect
1778 // that because we didn't call all the pieces that compute it for naked
1779 // functions.
1780 if (!MF.getFunction().hasFnAttribute(Kind: Attribute::Naked)) {
1781 if (!(hasBasePointer(MF) && FrameIndex < 0))
1782 Offset += MFI.getStackSize();
1783 }
1784
1785 // If we encounter an LXVP/STXVP with an offset that doesn't fit, we can
1786 // transform it to the prefixed version so we don't have to use the XForm.
1787 if ((OpC == PPC::LXVP || OpC == PPC::STXVP) &&
1788 (!isInt<16>(x: Offset) || (Offset % offsetMinAlign(MI)) != 0) &&
1789 Subtarget.hasPrefixInstrs() && Subtarget.hasP10Vector()) {
1790 unsigned NewOpc = OpC == PPC::LXVP ? PPC::PLXVP : PPC::PSTXVP;
1791 MI.setDesc(TII.get(Opcode: NewOpc));
1792 OpC = NewOpc;
1793 }
1794
1795 // If we can, encode the offset directly into the instruction. If this is a
1796 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If
1797 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits
1798 // clear can be encoded. This is extremely uncommon, because normally you
1799 // only "std" to a stack slot that is at least 4-byte aligned, but it can
1800 // happen in invalid code.
1801 assert(OpC != PPC::DBG_VALUE &&
1802 "This should be handled in a target-independent way");
1803 // FIXME: This should be factored out to a separate function as prefixed
1804 // instructions add a number of opcodes for which we can use 34-bit imm.
1805 bool OffsetFitsMnemonic = (OpC == PPC::EVSTDD || OpC == PPC::EVLDD) ?
1806 isUInt<8>(x: Offset) :
1807 isInt<16>(x: Offset);
1808 if (TII.isPrefixed(Opcode: MI.getOpcode()))
1809 OffsetFitsMnemonic = isInt<34>(x: Offset);
1810 if (!noImmForm && ((OffsetFitsMnemonic &&
1811 ((Offset % offsetMinAlign(MI)) == 0)) ||
1812 OpC == TargetOpcode::STACKMAP ||
1813 OpC == TargetOpcode::PATCHPOINT)) {
1814 MI.getOperand(i: OffsetOperandNo).ChangeToImmediate(ImmVal: Offset);
1815 return false;
1816 }
1817
1818 // The offset doesn't fit into a single register, scavenge one to build the
1819 // offset in.
1820
1821 bool is64Bit = TM.isPPC64();
1822 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1823 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1824 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
1825 unsigned NewOpcode = 0u;
1826 bool ScavengingFailed = RS && RS->getRegsAvailable(RC).none() &&
1827 RS->getRegsAvailable(RC: &PPC::VSFRCRegClass).any();
1828 Register SRegHi, SReg, VSReg;
1829
1830 // The register scavenger is unable to get a GPR but can get a VSR. We
1831 // need to stash a GPR into a VSR so that we can free one up.
1832 if (ScavengingFailed && Subtarget.hasDirectMove()) {
1833 // Pick a volatile register and if we are spilling/restoring that
1834 // particular one, pick the next one.
1835 SRegHi = SReg = is64Bit ? PPC::X4 : PPC::R4;
1836 if (MI.getOperand(i: 0).getReg() == SReg)
1837 SRegHi = SReg = SReg + 1;
1838 VSReg = MF.getRegInfo().createVirtualRegister(RegClass: &PPC::VSFRCRegClass);
1839 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: is64Bit ? PPC::MTVSRD : PPC::MTVSRWZ), DestReg: VSReg)
1840 .addReg(RegNo: SReg);
1841 } else {
1842 SRegHi = MF.getRegInfo().createVirtualRegister(RegClass: RC);
1843 SReg = MF.getRegInfo().createVirtualRegister(RegClass: RC);
1844 }
1845
1846 // Insert a set of rA with the full offset value before the ld, st, or add
1847 if (isInt<16>(x: Offset))
1848 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: is64Bit ? PPC::LI8 : PPC::LI), DestReg: SReg)
1849 .addImm(Val: Offset);
1850 else if (isInt<32>(x: Offset)) {
1851 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: is64Bit ? PPC::LIS8 : PPC::LIS), DestReg: SRegHi)
1852 .addImm(Val: Offset >> 16);
1853 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: is64Bit ? PPC::ORI8 : PPC::ORI), DestReg: SReg)
1854 .addReg(RegNo: SRegHi, Flags: RegState::Kill)
1855 .addImm(Val: Offset);
1856 } else {
1857 assert(is64Bit && "Huge stack is only supported on PPC64");
1858 TII.materializeImmPostRA(MBB, MBBI: II, DL: dl, Reg: SReg, Imm: Offset);
1859 }
1860
1861 // Convert into indexed form of the instruction:
1862 //
1863 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
1864 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
1865 unsigned OperandBase;
1866
1867 if (noImmForm)
1868 OperandBase = 1;
1869 else if (OpC != TargetOpcode::INLINEASM &&
1870 OpC != TargetOpcode::INLINEASM_BR) {
1871 assert(ImmToIdxMap.count(OpC) &&
1872 "No indexed form of load or store available!");
1873 NewOpcode = ImmToIdxMap.find(Val: OpC)->second;
1874 MI.setDesc(TII.get(Opcode: NewOpcode));
1875 OperandBase = 1;
1876 } else {
1877 OperandBase = OffsetOperandNo;
1878 }
1879
1880 Register StackReg = MI.getOperand(i: FIOperandNum).getReg();
1881 MI.getOperand(i: OperandBase).ChangeToRegister(Reg: StackReg, isDef: false);
1882 MI.getOperand(i: OperandBase + 1).ChangeToRegister(Reg: SReg, isDef: false, isImp: false, isKill: true);
1883
1884 // If we stashed a value from a GPR into a VSR, we need to get it back after
1885 // spilling the register.
1886 if (ScavengingFailed && Subtarget.hasDirectMove())
1887 BuildMI(BB&: MBB, I: ++II, MIMD: dl, MCID: TII.get(Opcode: is64Bit ? PPC::MFVSRD : PPC::MFVSRWZ), DestReg: SReg)
1888 .addReg(RegNo: VSReg);
1889
1890 // Since these are not real X-Form instructions, we must
1891 // add the registers and access 0(NewReg) rather than
1892 // emitting the X-Form pseudo.
1893 if (NewOpcode == PPC::LQX_PSEUDO || NewOpcode == PPC::STQX_PSEUDO) {
1894 assert(is64Bit && "Quadword loads/stores only supported in 64-bit mode");
1895 Register NewReg = MF.getRegInfo().createVirtualRegister(RegClass: &PPC::G8RCRegClass);
1896 BuildMI(BB&: MBB, I: II, MIMD: dl, MCID: TII.get(Opcode: PPC::ADD8), DestReg: NewReg)
1897 .addReg(RegNo: SReg, Flags: RegState::Kill)
1898 .addReg(RegNo: StackReg);
1899 MI.setDesc(TII.get(Opcode: NewOpcode == PPC::LQX_PSEUDO ? PPC::LQ : PPC::STQ));
1900 MI.getOperand(i: OperandBase + 1).ChangeToRegister(Reg: NewReg, isDef: false);
1901 MI.getOperand(i: OperandBase).ChangeToImmediate(ImmVal: 0);
1902 }
1903 return false;
1904}
1905
1906Register PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
1907 const PPCFrameLowering *TFI = getFrameLowering(MF);
1908
1909 if (!TM.isPPC64())
1910 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
1911 else
1912 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
1913}
1914
1915Register PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const {
1916 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
1917 if (!hasBasePointer(MF))
1918 return getFrameRegister(MF);
1919
1920 if (TM.isPPC64())
1921 return PPC::X30;
1922
1923 if (Subtarget.isSVR4ABI() && TM.isPositionIndependent())
1924 return PPC::R29;
1925
1926 return PPC::R30;
1927}
1928
1929bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
1930 if (!EnableBasePointer)
1931 return false;
1932 if (AlwaysBasePointer)
1933 return true;
1934
1935 // If we need to realign the stack, then the stack pointer can no longer
1936 // serve as an offset into the caller's stack space. As a result, we need a
1937 // base pointer.
1938 return hasStackRealignment(MF);
1939}
1940
1941/// Returns true if the instruction's frame index
1942/// reference would be better served by a base register other than FP
1943/// or SP. Used by LocalStackFrameAllocation to determine which frame index
1944/// references it should create new base registers for.
1945bool PPCRegisterInfo::
1946needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
1947 assert(Offset < 0 && "Local offset must be negative");
1948
1949 // It's the load/store FI references that cause issues, as it can be difficult
1950 // to materialize the offset if it won't fit in the literal field. Estimate
1951 // based on the size of the local frame and some conservative assumptions
1952 // about the rest of the stack frame (note, this is pre-regalloc, so
1953 // we don't know everything for certain yet) whether this offset is likely
1954 // to be out of range of the immediate. Return true if so.
1955
1956 // We only generate virtual base registers for loads and stores that have
1957 // an r+i form. Return false for everything else.
1958 unsigned OpC = MI->getOpcode();
1959 if (!ImmToIdxMap.count(Val: OpC))
1960 return false;
1961
1962 // Don't generate a new virtual base register just to add zero to it.
1963 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) &&
1964 MI->getOperand(i: 2).getImm() == 0)
1965 return false;
1966
1967 MachineBasicBlock &MBB = *MI->getParent();
1968 MachineFunction &MF = *MBB.getParent();
1969 const PPCFrameLowering *TFI = getFrameLowering(MF);
1970 unsigned StackEst = TFI->determineFrameLayout(MF, UseEstimate: true);
1971
1972 // If we likely don't need a stack frame, then we probably don't need a
1973 // virtual base register either.
1974 if (!StackEst)
1975 return false;
1976
1977 // Estimate an offset from the stack pointer.
1978 // The incoming offset is relating to the SP at the start of the function,
1979 // but when we access the local it'll be relative to the SP after local
1980 // allocation, so adjust our SP-relative offset by that allocation size.
1981 Offset += StackEst;
1982
1983 // The frame pointer will point to the end of the stack, so estimate the
1984 // offset as the difference between the object offset and the FP location.
1985 return !isFrameOffsetLegal(MI, BaseReg: getBaseRegister(MF), Offset);
1986}
1987
1988/// Insert defining instruction(s) for BaseReg to
1989/// be a pointer to FrameIdx at the beginning of the basic block.
1990Register PPCRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
1991 int FrameIdx,
1992 int64_t Offset) const {
1993 unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI;
1994
1995 MachineBasicBlock::iterator Ins = MBB->begin();
1996 DebugLoc DL; // Defaults to "unknown"
1997 if (Ins != MBB->end())
1998 DL = Ins->getDebugLoc();
1999
2000 const MachineFunction &MF = *MBB->getParent();
2001 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
2002 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
2003 const MCInstrDesc &MCID = TII.get(Opcode: ADDriOpc);
2004 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
2005 Register BaseReg = MRI.createVirtualRegister(RegClass: TII.getRegClass(MCID, OpNum: 0));
2006
2007 BuildMI(BB&: *MBB, I: Ins, MIMD: DL, MCID, DestReg: BaseReg)
2008 .addFrameIndex(Idx: FrameIdx).addImm(Val: Offset);
2009
2010 return BaseReg;
2011}
2012
2013void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg,
2014 int64_t Offset) const {
2015 unsigned FIOperandNum = 0;
2016 while (!MI.getOperand(i: FIOperandNum).isFI()) {
2017 ++FIOperandNum;
2018 assert(FIOperandNum < MI.getNumOperands() &&
2019 "Instr doesn't have FrameIndex operand!");
2020 }
2021
2022 MI.getOperand(i: FIOperandNum).ChangeToRegister(Reg: BaseReg, isDef: false);
2023 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
2024 Offset += MI.getOperand(i: OffsetOperandNo).getImm();
2025 MI.getOperand(i: OffsetOperandNo).ChangeToImmediate(ImmVal: Offset);
2026
2027 MachineBasicBlock &MBB = *MI.getParent();
2028 MachineFunction &MF = *MBB.getParent();
2029 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
2030 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
2031 const MCInstrDesc &MCID = MI.getDesc();
2032 MachineRegisterInfo &MRI = MF.getRegInfo();
2033 MRI.constrainRegClass(Reg: BaseReg, RC: TII.getRegClass(MCID, OpNum: FIOperandNum));
2034}
2035
2036bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
2037 Register BaseReg,
2038 int64_t Offset) const {
2039 unsigned FIOperandNum = 0;
2040 while (!MI->getOperand(i: FIOperandNum).isFI()) {
2041 ++FIOperandNum;
2042 assert(FIOperandNum < MI->getNumOperands() &&
2043 "Instr doesn't have FrameIndex operand!");
2044 }
2045
2046 unsigned OffsetOperandNo = getOffsetONFromFION(MI: *MI, FIOperandNum);
2047 Offset += MI->getOperand(i: OffsetOperandNo).getImm();
2048
2049 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
2050 MI->getOpcode() == TargetOpcode::STACKMAP ||
2051 MI->getOpcode() == TargetOpcode::PATCHPOINT ||
2052 (isInt<16>(x: Offset) && (Offset % offsetMinAlign(MI: *MI)) == 0);
2053}
2054