1//===-- RISCVRegisterBankInfo.cpp -------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file implements the targeting of the RegisterBankInfo class for RISC-V.
10/// \todo This should be generated by TableGen.
11//===----------------------------------------------------------------------===//
12
13#include "RISCVRegisterBankInfo.h"
14#include "MCTargetDesc/RISCVMCTargetDesc.h"
15#include "RISCVSubtarget.h"
16#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
17#include "llvm/CodeGen/MachineRegisterInfo.h"
18#include "llvm/CodeGen/RegisterBank.h"
19#include "llvm/CodeGen/RegisterBankInfo.h"
20#include "llvm/CodeGen/TargetRegisterInfo.h"
21#include "llvm/IR/IntrinsicsRISCV.h"
22
23#define GET_TARGET_REGBANK_IMPL
24#include "RISCVGenRegisterBank.inc"
25
26namespace llvm {
27namespace RISCV {
28
29const RegisterBankInfo::PartialMapping PartMappings[] = {
30 // clang-format off
31 {0, 32, GPRBRegBank},
32 {0, 64, GPRBRegBank},
33 {0, 16, FPRBRegBank},
34 {0, 32, FPRBRegBank},
35 {0, 64, FPRBRegBank},
36 {0, 64, VRBRegBank},
37 {0, 128, VRBRegBank},
38 {0, 256, VRBRegBank},
39 {0, 512, VRBRegBank},
40 // clang-format on
41};
42
43enum PartialMappingIdx {
44 PMI_GPRB32 = 0,
45 PMI_GPRB64 = 1,
46 PMI_FPRB16 = 2,
47 PMI_FPRB32 = 3,
48 PMI_FPRB64 = 4,
49 PMI_VRB64 = 5,
50 PMI_VRB128 = 6,
51 PMI_VRB256 = 7,
52 PMI_VRB512 = 8,
53};
54
55const RegisterBankInfo::ValueMapping ValueMappings[] = {
56 // Invalid value mapping.
57 {nullptr, 0},
58 // Maximum 3 GPR operands; 32 bit.
59 {&PartMappings[PMI_GPRB32], 1},
60 {&PartMappings[PMI_GPRB32], 1},
61 {&PartMappings[PMI_GPRB32], 1},
62 // Maximum 3 GPR operands; 64 bit.
63 {&PartMappings[PMI_GPRB64], 1},
64 {&PartMappings[PMI_GPRB64], 1},
65 {&PartMappings[PMI_GPRB64], 1},
66 // Maximum 3 FPR operands; 16 bit.
67 {&PartMappings[PMI_FPRB16], 1},
68 {&PartMappings[PMI_FPRB16], 1},
69 {&PartMappings[PMI_FPRB16], 1},
70 // Maximum 3 FPR operands; 32 bit.
71 {&PartMappings[PMI_FPRB32], 1},
72 {&PartMappings[PMI_FPRB32], 1},
73 {&PartMappings[PMI_FPRB32], 1},
74 // Maximum 3 FPR operands; 64 bit.
75 {&PartMappings[PMI_FPRB64], 1},
76 {&PartMappings[PMI_FPRB64], 1},
77 {&PartMappings[PMI_FPRB64], 1},
78 // Maximum 3 VR LMUL={1, MF2, MF4, MF8} operands.
79 {&PartMappings[PMI_VRB64], 1},
80 {&PartMappings[PMI_VRB64], 1},
81 {&PartMappings[PMI_VRB64], 1},
82 // Maximum 3 VR LMUL=2 operands.
83 {&PartMappings[PMI_VRB128], 1},
84 {&PartMappings[PMI_VRB128], 1},
85 {&PartMappings[PMI_VRB128], 1},
86 // Maximum 3 VR LMUL=4 operands.
87 {&PartMappings[PMI_VRB256], 1},
88 {&PartMappings[PMI_VRB256], 1},
89 {&PartMappings[PMI_VRB256], 1},
90 // Maximum 3 VR LMUL=8 operands.
91 {&PartMappings[PMI_VRB512], 1},
92 {&PartMappings[PMI_VRB512], 1},
93 {&PartMappings[PMI_VRB512], 1},
94};
95
96enum ValueMappingIdx {
97 InvalidIdx = 0,
98 GPRB32Idx = 1,
99 GPRB64Idx = 4,
100 FPRB16Idx = 7,
101 FPRB32Idx = 10,
102 FPRB64Idx = 13,
103 VRB64Idx = 16,
104 VRB128Idx = 19,
105 VRB256Idx = 22,
106 VRB512Idx = 25,
107};
108} // namespace RISCV
109} // namespace llvm
110
111using namespace llvm;
112
113RISCVRegisterBankInfo::RISCVRegisterBankInfo(unsigned HwMode)
114 : RISCVGenRegisterBankInfo(HwMode) {}
115
116const RegisterBank &
117RISCVRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
118 LLT Ty) const {
119 switch (RC.getID()) {
120 // Vector control and status register class
121 case RISCV::VCSRRegClassID:
122 return getRegBank(ID: RISCV::GPRBRegBankID);
123 default:
124 // For all GPR register classes and others, use the default implementation
125 return RISCVGenRegisterBankInfo::getRegBankFromRegClass(RC, Ty);
126 }
127}
128
129static const RegisterBankInfo::ValueMapping *getFPValueMapping(unsigned Size) {
130 unsigned Idx;
131 switch (Size) {
132 default:
133 llvm_unreachable("Unexpected size");
134 case 16:
135 Idx = RISCV::FPRB16Idx;
136 break;
137 case 32:
138 Idx = RISCV::FPRB32Idx;
139 break;
140 case 64:
141 Idx = RISCV::FPRB64Idx;
142 break;
143 }
144 return &RISCV::ValueMappings[Idx];
145}
146
147// TODO: Make this more like AArch64?
148bool RISCVRegisterBankInfo::hasFPConstraints(
149 const MachineInstr &MI, const MachineRegisterInfo &MRI,
150 const TargetRegisterInfo &TRI) const {
151 if (isPreISelGenericFloatingPointOpcode(Opc: MI.getOpcode()))
152 return true;
153
154 // If we have a copy instruction, we could be feeding floating point
155 // instructions.
156 if (MI.getOpcode() != TargetOpcode::COPY)
157 return false;
158
159 return getRegBank(Reg: MI.getOperand(i: 0).getReg(), MRI, TRI) == &RISCV::FPRBRegBank;
160}
161
162bool RISCVRegisterBankInfo::onlyUsesFP(const MachineInstr &MI,
163 const MachineRegisterInfo &MRI,
164 const TargetRegisterInfo &TRI) const {
165 switch (MI.getOpcode()) {
166 case RISCV::G_FCVT_W_RV64:
167 case RISCV::G_FCVT_WU_RV64:
168 case RISCV::G_FCLASS:
169 case TargetOpcode::G_FPTOSI:
170 case TargetOpcode::G_FPTOUI:
171 case TargetOpcode::G_LROUND:
172 case TargetOpcode::G_LLROUND:
173 case TargetOpcode::G_FCMP:
174 return true;
175 default:
176 break;
177 }
178
179 return hasFPConstraints(MI, MRI, TRI);
180}
181
182bool RISCVRegisterBankInfo::onlyDefinesFP(const MachineInstr &MI,
183 const MachineRegisterInfo &MRI,
184 const TargetRegisterInfo &TRI) const {
185 switch (MI.getOpcode()) {
186 case TargetOpcode::G_SITOFP:
187 case TargetOpcode::G_UITOFP:
188 return true;
189 default:
190 break;
191 }
192
193 return hasFPConstraints(MI, MRI, TRI);
194}
195
196bool RISCVRegisterBankInfo::anyUseOnlyUseFP(
197 Register Def, const MachineRegisterInfo &MRI,
198 const TargetRegisterInfo &TRI) const {
199 return any_of(
200 Range: MRI.use_nodbg_instructions(Reg: Def),
201 P: [&](const MachineInstr &UseMI) { return onlyUsesFP(MI: UseMI, MRI, TRI); });
202}
203
204static const RegisterBankInfo::ValueMapping *getVRBValueMapping(unsigned Size) {
205 unsigned Idx;
206
207 if (Size <= 64)
208 Idx = RISCV::VRB64Idx;
209 else if (Size == 128)
210 Idx = RISCV::VRB128Idx;
211 else if (Size == 256)
212 Idx = RISCV::VRB256Idx;
213 else if (Size == 512)
214 Idx = RISCV::VRB512Idx;
215 else
216 llvm::report_fatal_error(reason: "Invalid Size");
217
218 return &RISCV::ValueMappings[Idx];
219}
220
221const RegisterBankInfo::InstructionMapping &
222RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
223 const unsigned Opc = MI.getOpcode();
224
225 // Try the default logic for non-generic instructions that are either copies
226 // or already have some operands assigned to banks.
227 if (!isPreISelGenericOpcode(Opcode: Opc) || Opc == TargetOpcode::G_PHI) {
228 const InstructionMapping &Mapping = getInstrMappingImpl(MI);
229 if (Mapping.isValid())
230 return Mapping;
231 }
232
233 const MachineFunction &MF = *MI.getParent()->getParent();
234 const MachineRegisterInfo &MRI = MF.getRegInfo();
235 const RISCVSubtarget &Subtarget = MF.getSubtarget<RISCVSubtarget>();
236 const TargetRegisterInfo &TRI = *Subtarget.getRegisterInfo();
237
238 unsigned GPRSize = Subtarget.getXLen();
239
240 unsigned NumOperands = MI.getNumOperands();
241 const ValueMapping *GPRValueMapping =
242 &RISCV::ValueMappings[GPRSize == 64 ? RISCV::GPRB64Idx
243 : RISCV::GPRB32Idx];
244
245 switch (Opc) {
246 case TargetOpcode::G_ADD:
247 case TargetOpcode::G_SUB:
248 case TargetOpcode::G_SHL:
249 case TargetOpcode::G_ASHR:
250 case TargetOpcode::G_LSHR:
251 case TargetOpcode::G_AND:
252 case TargetOpcode::G_OR:
253 case TargetOpcode::G_XOR:
254 case TargetOpcode::G_MUL:
255 case TargetOpcode::G_SDIV:
256 case TargetOpcode::G_SREM:
257 case TargetOpcode::G_SMULH:
258 case TargetOpcode::G_SMAX:
259 case TargetOpcode::G_SMIN:
260 case TargetOpcode::G_UDIV:
261 case TargetOpcode::G_UREM:
262 case TargetOpcode::G_UMULH:
263 case TargetOpcode::G_UMAX:
264 case TargetOpcode::G_UMIN:
265 case TargetOpcode::G_PTR_ADD:
266 case TargetOpcode::G_PTRTOINT:
267 case TargetOpcode::G_INTTOPTR:
268 case TargetOpcode::G_FADD:
269 case TargetOpcode::G_FSUB:
270 case TargetOpcode::G_FMUL:
271 case TargetOpcode::G_FDIV:
272 case TargetOpcode::G_FABS:
273 case TargetOpcode::G_FNEG:
274 case TargetOpcode::G_FSQRT:
275 case TargetOpcode::G_FMAXNUM:
276 case TargetOpcode::G_FMINNUM: {
277 LLT Ty = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
278 TypeSize Size = Ty.getSizeInBits();
279
280 const ValueMapping *Mapping;
281 if (Ty.isVector())
282 Mapping = getVRBValueMapping(Size: Size.getKnownMinValue());
283 else if (isPreISelGenericFloatingPointOpcode(Opc))
284 Mapping = getFPValueMapping(Size: Size.getFixedValue());
285 else
286 Mapping = GPRValueMapping;
287
288#ifndef NDEBUG
289 // Make sure all the operands are using similar size and type.
290 for (unsigned Idx = 1; Idx != NumOperands; ++Idx) {
291 LLT OpTy = MRI.getType(MI.getOperand(Idx).getReg());
292 assert(Ty.isVector() == OpTy.isVector() &&
293 "Operand has incompatible type");
294 // Don't check size for GPR.
295 if (OpTy.isVector() || isPreISelGenericFloatingPointOpcode(Opc))
296 assert(Size == OpTy.getSizeInBits() && "Operand has incompatible size");
297 }
298#endif // End NDEBUG
299
300 return getInstructionMapping(ID: DefaultMappingID, Cost: 1, OperandsMapping: Mapping, NumOperands);
301 }
302 case TargetOpcode::G_SEXTLOAD:
303 case TargetOpcode::G_ZEXTLOAD:
304 return getInstructionMapping(ID: DefaultMappingID, /*Cost=*/1, OperandsMapping: GPRValueMapping,
305 NumOperands);
306 case TargetOpcode::G_IMPLICIT_DEF: {
307 Register Dst = MI.getOperand(i: 0).getReg();
308 LLT DstTy = MRI.getType(Reg: Dst);
309 unsigned DstMinSize = DstTy.getSizeInBits().getKnownMinValue();
310 auto Mapping = GPRValueMapping;
311 // FIXME: May need to do a better job determining when to use FPRB.
312 // For example, the look through COPY case:
313 // %0:_(s32) = G_IMPLICIT_DEF
314 // %1:_(s32) = COPY %0
315 // $f10_d = COPY %1(s32)
316 if (DstTy.isVector())
317 Mapping = getVRBValueMapping(Size: DstMinSize);
318 else if (anyUseOnlyUseFP(Def: Dst, MRI, TRI))
319 Mapping = getFPValueMapping(Size: DstMinSize);
320
321 return getInstructionMapping(ID: DefaultMappingID, /*Cost=*/1, OperandsMapping: Mapping,
322 NumOperands);
323 }
324 }
325
326 SmallVector<const ValueMapping *, 4> OpdsMapping(NumOperands);
327
328 switch (Opc) {
329 case TargetOpcode::G_LOAD: {
330 LLT Ty = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
331 TypeSize Size = Ty.getSizeInBits();
332
333 OpdsMapping[1] = GPRValueMapping;
334
335 if (Ty.isVector()) {
336 OpdsMapping[0] = getVRBValueMapping(Size: Size.getKnownMinValue());
337 break;
338 }
339
340 OpdsMapping[0] = GPRValueMapping;
341
342 // Atomics always use GPR destinations. Don't refine any further.
343 if (cast<GLoad>(Val: MI).isAtomic())
344 break;
345
346 // Use FPR64 for s64 loads on rv32.
347 if (GPRSize == 32 && Size.getFixedValue() == 64) {
348 assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD());
349 OpdsMapping[0] = getFPValueMapping(Size);
350 break;
351 }
352
353 // Check if that load feeds fp instructions.
354 // In that case, we want the default mapping to be on FPR
355 // instead of blind map every scalar to GPR.
356 if (anyUseOnlyUseFP(Def: MI.getOperand(i: 0).getReg(), MRI, TRI)) {
357 // If we have at least one direct use in a FP instruction,
358 // assume this was a floating point load in the IR. If it was
359 // not, we would have had a bitcast before reaching that
360 // instruction.
361 OpdsMapping[0] = getFPValueMapping(Size);
362 break;
363 }
364
365 break;
366 }
367 case TargetOpcode::G_STORE: {
368 LLT Ty = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
369 TypeSize Size = Ty.getSizeInBits();
370
371 OpdsMapping[1] = GPRValueMapping;
372
373 if (Ty.isVector()) {
374 OpdsMapping[0] = getVRBValueMapping(Size: Size.getKnownMinValue());
375 break;
376 }
377
378 OpdsMapping[0] = GPRValueMapping;
379
380 // Atomics always use GPR sources. Don't refine any further.
381 if (cast<GStore>(Val: MI).isAtomic())
382 break;
383
384 // Use FPR64 for s64 stores on rv32.
385 if (GPRSize == 32 && Size.getFixedValue() == 64) {
386 assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD());
387 OpdsMapping[0] = getFPValueMapping(Size: Ty.getSizeInBits());
388 break;
389 }
390
391 MachineInstr *DefMI = MRI.getVRegDef(Reg: MI.getOperand(i: 0).getReg());
392 if (onlyDefinesFP(MI: *DefMI, MRI, TRI))
393 OpdsMapping[0] = getFPValueMapping(Size: Ty.getSizeInBits());
394 break;
395 }
396 case TargetOpcode::G_SELECT: {
397 LLT Ty = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
398
399 if (Ty.isVector()) {
400 auto &Sel = cast<GSelect>(Val: MI);
401 LLT TestTy = MRI.getType(Reg: Sel.getCondReg());
402 assert(TestTy.isVector() && "Unexpected condition argument type");
403 OpdsMapping[0] = OpdsMapping[2] = OpdsMapping[3] =
404 getVRBValueMapping(Size: Ty.getSizeInBits().getKnownMinValue());
405 OpdsMapping[1] =
406 getVRBValueMapping(Size: TestTy.getSizeInBits().getKnownMinValue());
407 break;
408 }
409
410 // Try to minimize the number of copies. If we have more floating point
411 // constrained values than not, then we'll put everything on FPR. Otherwise,
412 // everything has to be on GPR.
413 unsigned NumFP = 0;
414
415 // Use FPR64 for s64 select on rv32.
416 if (GPRSize == 32 && Ty.getSizeInBits() == 64) {
417 NumFP = 3;
418 } else {
419 // Check if the uses of the result always produce floating point values.
420 //
421 // For example:
422 //
423 // %z = G_SELECT %cond %x %y
424 // fpr = G_FOO %z ...
425 if (any_of(Range: MRI.use_nodbg_instructions(Reg: MI.getOperand(i: 0).getReg()),
426 P: [&](const MachineInstr &UseMI) {
427 return onlyUsesFP(MI: UseMI, MRI, TRI);
428 }))
429 ++NumFP;
430
431 // Check if the defs of the source values always produce floating point
432 // values.
433 //
434 // For example:
435 //
436 // %x = G_SOMETHING_ALWAYS_FLOAT %a ...
437 // %z = G_SELECT %cond %x %y
438 //
439 // Also check whether or not the sources have already been decided to be
440 // FPR. Keep track of this.
441 //
442 // This doesn't check the condition, since the condition is always an
443 // integer.
444 for (unsigned Idx = 2; Idx < 4; ++Idx) {
445 Register VReg = MI.getOperand(i: Idx).getReg();
446 MachineInstr *DefMI = MRI.getVRegDef(Reg: VReg);
447 if (getRegBank(Reg: VReg, MRI, TRI) == &RISCV::FPRBRegBank ||
448 onlyDefinesFP(MI: *DefMI, MRI, TRI))
449 ++NumFP;
450 }
451 }
452
453 // Condition operand is always GPR.
454 OpdsMapping[1] = GPRValueMapping;
455
456 const ValueMapping *Mapping = GPRValueMapping;
457 if (NumFP >= 2)
458 Mapping = getFPValueMapping(Size: Ty.getSizeInBits());
459
460 OpdsMapping[0] = OpdsMapping[2] = OpdsMapping[3] = Mapping;
461 break;
462 }
463 case RISCV::G_FCVT_W_RV64:
464 case RISCV::G_FCVT_WU_RV64:
465 case TargetOpcode::G_FPTOSI:
466 case TargetOpcode::G_FPTOUI:
467 case TargetOpcode::G_LROUND:
468 case TargetOpcode::G_LLROUND:
469 case RISCV::G_FCLASS: {
470 LLT Ty = MRI.getType(Reg: MI.getOperand(i: 1).getReg());
471 OpdsMapping[0] = GPRValueMapping;
472 OpdsMapping[1] = getFPValueMapping(Size: Ty.getSizeInBits());
473 break;
474 }
475 case TargetOpcode::G_SITOFP:
476 case TargetOpcode::G_UITOFP: {
477 LLT Ty = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
478 OpdsMapping[0] = getFPValueMapping(Size: Ty.getSizeInBits());
479 OpdsMapping[1] = GPRValueMapping;
480 break;
481 }
482 case TargetOpcode::G_FCMP: {
483 LLT Ty = MRI.getType(Reg: MI.getOperand(i: 2).getReg());
484
485 unsigned Size = Ty.getSizeInBits();
486
487 OpdsMapping[0] = GPRValueMapping;
488 OpdsMapping[2] = OpdsMapping[3] = getFPValueMapping(Size);
489 break;
490 }
491 case TargetOpcode::G_MERGE_VALUES: {
492 // Use FPR64 for s64 merge on rv32.
493 LLT Ty = MRI.getType(Reg: MI.getOperand(i: 0).getReg());
494 if (GPRSize == 32 && Ty.getSizeInBits() == 64) {
495 assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD());
496 OpdsMapping[0] = getFPValueMapping(Size: Ty.getSizeInBits());
497 OpdsMapping[1] = GPRValueMapping;
498 OpdsMapping[2] = GPRValueMapping;
499 }
500 break;
501 }
502 case TargetOpcode::G_UNMERGE_VALUES: {
503 // Use FPR64 for s64 unmerge on rv32.
504 LLT Ty = MRI.getType(Reg: MI.getOperand(i: 2).getReg());
505 if (GPRSize == 32 && Ty.getSizeInBits() == 64) {
506 assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD());
507 OpdsMapping[0] = GPRValueMapping;
508 OpdsMapping[1] = GPRValueMapping;
509 OpdsMapping[2] = getFPValueMapping(Size: Ty.getSizeInBits());
510 }
511 break;
512 }
513 case TargetOpcode::G_SPLAT_VECTOR: {
514 OpdsMapping[0] = getVRBValueMapping(Size: MRI.getType(Reg: MI.getOperand(i: 0).getReg())
515 .getSizeInBits()
516 .getKnownMinValue());
517
518 LLT ScalarTy = MRI.getType(Reg: MI.getOperand(i: 1).getReg());
519 MachineInstr *DefMI = MRI.getVRegDef(Reg: MI.getOperand(i: 1).getReg());
520 if ((GPRSize == 32 && ScalarTy.getSizeInBits() == 64) ||
521 onlyDefinesFP(MI: *DefMI, MRI, TRI)) {
522 assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD());
523 OpdsMapping[1] = getFPValueMapping(Size: ScalarTy.getSizeInBits());
524 } else
525 OpdsMapping[1] = GPRValueMapping;
526 break;
527 }
528 case TargetOpcode::G_INTRINSIC: {
529 Intrinsic::ID IntrinsicID = cast<GIntrinsic>(Val: MI).getIntrinsicID();
530
531 if (const RISCVVIntrinsicsTable::RISCVVIntrinsicInfo *II =
532 RISCVVIntrinsicsTable::getRISCVVIntrinsicInfo(IntrinsicID)) {
533 unsigned ScalarIdx = -1;
534 if (II->hasScalarOperand()) {
535 ScalarIdx = II->ScalarOperand + 2;
536 }
537 for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
538 const MachineOperand &MO = MI.getOperand(i: Idx);
539 if (!MO.isReg())
540 continue;
541 LLT Ty = MRI.getType(Reg: MO.getReg());
542 if (Ty.isVector()) {
543 OpdsMapping[Idx] =
544 getVRBValueMapping(Size: Ty.getSizeInBits().getKnownMinValue());
545 } else if (II->IsFPIntrinsic && ScalarIdx == Idx) {
546 // Chose the right FPR for scalar operand of RVV intrinsics.
547 OpdsMapping[Idx] = getFPValueMapping(Size: Ty.getSizeInBits());
548 } else {
549 OpdsMapping[Idx] = GPRValueMapping;
550 }
551 }
552 }
553
554 if (IntrinsicID == Intrinsic::riscv_vsetvli ||
555 IntrinsicID == Intrinsic::riscv_vsetvlimax) {
556 for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
557 const MachineOperand &MO = MI.getOperand(i: Idx);
558 if (!MO.isReg())
559 continue;
560 OpdsMapping[Idx] = GPRValueMapping;
561 }
562 }
563 break;
564 }
565 default:
566 // By default map all scalars to GPR.
567 for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
568 auto &MO = MI.getOperand(i: Idx);
569 if (!MO.isReg() || !MO.getReg())
570 continue;
571 LLT Ty = MRI.getType(Reg: MO.getReg());
572 if (!Ty.isValid())
573 continue;
574
575 if (Ty.isVector())
576 OpdsMapping[Idx] =
577 getVRBValueMapping(Size: Ty.getSizeInBits().getKnownMinValue());
578 else if (isPreISelGenericFloatingPointOpcode(Opc))
579 OpdsMapping[Idx] = getFPValueMapping(Size: Ty.getSizeInBits());
580 else
581 OpdsMapping[Idx] = GPRValueMapping;
582 }
583 break;
584 }
585
586 return getInstructionMapping(ID: DefaultMappingID, /*Cost=*/1,
587 OperandsMapping: getOperandsMapping(OpdsMapping), NumOperands);
588}
589