1//===-- RISCVAsmPrinter.cpp - RISC-V LLVM assembly writer -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a printer that converts from our internal representation
10// of machine-dependent LLVM code to the RISC-V assembly language.
11//
12//===----------------------------------------------------------------------===//
13
14#include "RISCVAsmPrinter.h"
15#include "MCTargetDesc/RISCVBaseInfo.h"
16#include "MCTargetDesc/RISCVELFStreamer.h"
17#include "MCTargetDesc/RISCVInstPrinter.h"
18#include "MCTargetDesc/RISCVMCAsmInfo.h"
19#include "MCTargetDesc/RISCVMatInt.h"
20#include "MCTargetDesc/RISCVTargetStreamer.h"
21#include "RISCV.h"
22#include "RISCVConstantPoolValue.h"
23#include "RISCVMachineFunctionInfo.h"
24#include "RISCVRegisterInfo.h"
25#include "TargetInfo/RISCVTargetInfo.h"
26#include "llvm/ADT/APInt.h"
27#include "llvm/ADT/Statistic.h"
28#include "llvm/BinaryFormat/ELF.h"
29#include "llvm/CodeGen/AsmPrinter.h"
30#include "llvm/CodeGen/AsmPrinterAnalysis.h"
31#include "llvm/CodeGen/MachineConstantPool.h"
32#include "llvm/CodeGen/MachineFunctionAnalysisManager.h"
33#include "llvm/CodeGen/MachineInstr.h"
34#include "llvm/CodeGen/MachineModuleInfo.h"
35#include "llvm/IR/Module.h"
36#include "llvm/MC/MCAsmInfo.h"
37#include "llvm/MC/MCContext.h"
38#include "llvm/MC/MCInst.h"
39#include "llvm/MC/MCInstBuilder.h"
40#include "llvm/MC/MCObjectFileInfo.h"
41#include "llvm/MC/MCSectionELF.h"
42#include "llvm/MC/MCStreamer.h"
43#include "llvm/MC/MCSymbol.h"
44#include "llvm/MC/TargetRegistry.h"
45#include "llvm/Support/CHERICapabilityFormat.h"
46#include "llvm/Support/Compiler.h"
47#include "llvm/Support/raw_ostream.h"
48#include "llvm/TargetParser/RISCVISAInfo.h"
49#include "llvm/Transforms/Instrumentation/HWAddressSanitizer.h"
50
51using namespace llvm;
52
53#define DEBUG_TYPE "asm-printer"
54
55STATISTIC(RISCVNumInstrsCompressed,
56 "Number of RISC-V Compressed instructions emitted");
57
58namespace {
59class RISCVAsmPrinter : public AsmPrinter {
60public:
61 static char ID;
62
63private:
64 const RISCVSubtarget *STI;
65
66public:
67 explicit RISCVAsmPrinter(TargetMachine &TM,
68 std::unique_ptr<MCStreamer> Streamer)
69 : AsmPrinter(TM, std::move(Streamer), ID) {}
70
71 StringRef getPassName() const override { return "RISC-V Assembly Printer"; }
72
73 RISCVTargetStreamer &getTargetStreamer() const {
74 return static_cast<RISCVTargetStreamer &>(
75 *OutStreamer->getTargetStreamer());
76 }
77
78 void LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
79 const MachineInstr &MI);
80
81 void LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
82 const MachineInstr &MI);
83
84 void LowerSTATEPOINT(MCStreamer &OutStreamer, StackMaps &SM,
85 const MachineInstr &MI);
86
87 bool runOnMachineFunction(MachineFunction &MF) override;
88
89 void emitInstruction(const MachineInstr *MI) override;
90
91 void emitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override;
92
93 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
94 const char *ExtraCode, raw_ostream &OS) override;
95 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
96 const char *ExtraCode, raw_ostream &OS) override;
97
98 // Returns whether Inst is compressed.
99 bool EmitToStreamer(MCStreamer &S, const MCInst &Inst,
100 const MCSubtargetInfo &SubtargetInfo);
101 bool EmitToStreamer(MCStreamer &S, const MCInst &Inst) {
102 return EmitToStreamer(S, Inst, SubtargetInfo: *STI);
103 }
104
105 bool lowerPseudoInstExpansion(const MachineInstr *MI, MCInst &Inst);
106
107 typedef std::tuple<unsigned, uint32_t> HwasanMemaccessTuple;
108 std::map<HwasanMemaccessTuple, MCSymbol *> HwasanMemaccessSymbols;
109 void LowerHWASAN_CHECK_MEMACCESS(const MachineInstr &MI);
110 void LowerKCFI_CHECK(const MachineInstr &MI);
111 void EmitHwasanMemaccessSymbols(Module &M);
112
113 // Wrapper needed for tblgenned pseudo lowering.
114 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const;
115
116 void emitStartOfAsmFile(Module &M) override;
117 void emitEndOfAsmFile(Module &M) override;
118
119 void emitFunctionEntryLabel() override;
120 bool emitTargetFeaturePush(const MCSubtargetInfo &STI) override;
121 void emitTargetFeaturePop(const MCSubtargetInfo &STI, bool DidPush) override;
122
123 void emitNoteGnuProperty(const Module &M);
124
125private:
126 void emitAttributes(const MCSubtargetInfo &SubtargetInfo);
127
128 void emitNTLHint(const MachineInstr *MI);
129
130 void emitLpadAlignedCall(const MachineInstr &MI);
131
132 // XRay Support
133 void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr *MI);
134 void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr *MI);
135 void LowerPATCHABLE_TAIL_CALL(const MachineInstr *MI);
136 void emitSled(const MachineInstr *MI, SledKind Kind);
137
138 void lowerToMCInst(const MachineInstr *MI, MCInst &OutMI);
139
140 MaybeAlign
141 getRequiredGlobalAlignmentGranule(const GlobalVariable &GV) override;
142};
143} // namespace
144
145void RISCVAsmPrinter::LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
146 const MachineInstr &MI) {
147 unsigned NOPBytes = STI->hasStdExtZca() ? 2 : 4;
148 unsigned NumNOPBytes = StackMapOpers(&MI).getNumPatchBytes();
149
150 auto &Ctx = OutStreamer.getContext();
151 MCSymbol *MILabel = Ctx.createTempSymbol();
152 OutStreamer.emitLabel(Symbol: MILabel);
153
154 SM.recordStackMap(L: *MILabel, MI);
155 assert(NumNOPBytes % NOPBytes == 0 &&
156 "Invalid number of NOP bytes requested!");
157
158 // Scan ahead to trim the shadow.
159 const MachineBasicBlock &MBB = *MI.getParent();
160 MachineBasicBlock::const_iterator MII(MI);
161 ++MII;
162 while (NumNOPBytes > 0) {
163 if (MII == MBB.end() || MII->isCall() ||
164 MII->getOpcode() == RISCV::DBG_VALUE ||
165 MII->getOpcode() == TargetOpcode::PATCHPOINT ||
166 MII->getOpcode() == TargetOpcode::STACKMAP)
167 break;
168 ++MII;
169 NumNOPBytes -= NOPBytes;
170 }
171
172 // Emit nops.
173 emitNops(N: NumNOPBytes / NOPBytes);
174}
175
176// Lower a patchpoint of the form:
177// [<def>], <id>, <numBytes>, <target>, <numArgs>
178void RISCVAsmPrinter::LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
179 const MachineInstr &MI) {
180 unsigned NOPBytes = STI->hasStdExtZca() ? 2 : 4;
181
182 auto &Ctx = OutStreamer.getContext();
183 MCSymbol *MILabel = Ctx.createTempSymbol();
184 OutStreamer.emitLabel(Symbol: MILabel);
185 SM.recordPatchPoint(L: *MILabel, MI);
186
187 PatchPointOpers Opers(&MI);
188
189 const MachineOperand &CalleeMO = Opers.getCallTarget();
190 unsigned EncodedBytes = 0;
191
192 if (CalleeMO.isImm()) {
193 uint64_t CallTarget = CalleeMO.getImm();
194 if (CallTarget) {
195 assert((CallTarget & 0xFFFF'FFFF'FFFF) == CallTarget &&
196 "High 16 bits of call target should be zero.");
197 // Materialize the jump address:
198 SmallVector<MCInst, 8> Seq;
199 RISCVMatInt::generateMCInstSeq(Val: CallTarget, STI: *STI, DestReg: RISCV::X1, Insts&: Seq);
200 for (MCInst &Inst : Seq) {
201 bool Compressed = EmitToStreamer(S&: OutStreamer, Inst);
202 EncodedBytes += Compressed ? 2 : 4;
203 }
204 bool Compressed = EmitToStreamer(S&: OutStreamer, Inst: MCInstBuilder(RISCV::JALR)
205 .addReg(Reg: RISCV::X1)
206 .addReg(Reg: RISCV::X1)
207 .addImm(Val: 0));
208 EncodedBytes += Compressed ? 2 : 4;
209 }
210 } else if (CalleeMO.isGlobal()) {
211 MCOperand CallTargetMCOp;
212 lowerOperand(MO: CalleeMO, MCOp&: CallTargetMCOp);
213 EmitToStreamer(S&: OutStreamer,
214 Inst: MCInstBuilder(RISCV::PseudoCALL).addOperand(Op: CallTargetMCOp));
215 EncodedBytes += 8;
216 }
217
218 // Emit padding.
219 unsigned NumBytes = Opers.getNumPatchBytes();
220 assert(NumBytes >= EncodedBytes &&
221 "Patchpoint can't request size less than the length of a call.");
222 assert((NumBytes - EncodedBytes) % NOPBytes == 0 &&
223 "Invalid number of NOP bytes requested!");
224 emitNops(N: (NumBytes - EncodedBytes) / NOPBytes);
225}
226
227void RISCVAsmPrinter::LowerSTATEPOINT(MCStreamer &OutStreamer, StackMaps &SM,
228 const MachineInstr &MI) {
229 unsigned NOPBytes = STI->hasStdExtZca() ? 2 : 4;
230
231 StatepointOpers SOpers(&MI);
232 if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
233 assert(PatchBytes % NOPBytes == 0 &&
234 "Invalid number of NOP bytes requested!");
235 emitNops(N: PatchBytes / NOPBytes);
236 } else {
237 // Lower call target and choose correct opcode
238 const MachineOperand &CallTarget = SOpers.getCallTarget();
239 MCOperand CallTargetMCOp;
240 switch (CallTarget.getType()) {
241 case MachineOperand::MO_GlobalAddress:
242 case MachineOperand::MO_ExternalSymbol:
243 lowerOperand(MO: CallTarget, MCOp&: CallTargetMCOp);
244 EmitToStreamer(
245 S&: OutStreamer,
246 Inst: MCInstBuilder(RISCV::PseudoCALL).addOperand(Op: CallTargetMCOp));
247 break;
248 case MachineOperand::MO_Immediate:
249 CallTargetMCOp = MCOperand::createImm(Val: CallTarget.getImm());
250 EmitToStreamer(S&: OutStreamer, Inst: MCInstBuilder(RISCV::JAL)
251 .addReg(Reg: RISCV::X1)
252 .addOperand(Op: CallTargetMCOp));
253 break;
254 case MachineOperand::MO_Register:
255 CallTargetMCOp = MCOperand::createReg(Reg: CallTarget.getReg());
256 EmitToStreamer(S&: OutStreamer, Inst: MCInstBuilder(RISCV::JALR)
257 .addReg(Reg: RISCV::X1)
258 .addOperand(Op: CallTargetMCOp)
259 .addImm(Val: 0));
260 break;
261 default:
262 llvm_unreachable("Unsupported operand type in statepoint call target");
263 break;
264 }
265 }
266
267 auto &Ctx = OutStreamer.getContext();
268 MCSymbol *MILabel = Ctx.createTempSymbol();
269 OutStreamer.emitLabel(Symbol: MILabel);
270 SM.recordStatepoint(L: *MILabel, MI);
271}
272
273bool RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst,
274 const MCSubtargetInfo &SubtargetInfo) {
275 MCInst CInst;
276 bool Res = RISCVRVC::compress(OutInst&: CInst, MI: Inst, STI: SubtargetInfo);
277 if (Res)
278 ++RISCVNumInstrsCompressed;
279 S.emitInstruction(Inst: Res ? CInst : Inst, STI: SubtargetInfo);
280 return Res;
281}
282
283// Simple pseudo-instructions have their lowering (with expansion to real
284// instructions) auto-generated.
285#include "RISCVGenMCPseudoLowering.inc"
286
287// Emit a call to a returns_twice function with LPAD.
288// When Zca is enabled, emit .p2align 2 before the call to ensure the
289// following LPAD is 4-byte aligned. For assembly output, wrap with
290// .option push/exact/pop to prevent relaxation. For object output,
291// emit the pseudo directly so MCCodeEmitter handles it without R_RISCV_RELAX.
292void RISCVAsmPrinter::emitLpadAlignedCall(const MachineInstr &MI) {
293 const MCSubtargetInfo &MCSTI = getSubtargetInfo();
294 const bool IsIndirect = MI.getOpcode() == RISCV::PseudoCALLIndirectLpadAlign,
295 HasZca = MCSTI.hasFeature(Feature: RISCV::FeatureStdExtZca),
296 HasRelax = MCSTI.hasFeature(Feature: RISCV::FeatureRelax);
297
298 if (HasZca)
299 OutStreamer->emitCodeAlignment(Alignment: Align(4), STI: MCSTI);
300
301 if (OutStreamer->hasRawTextSupport()) {
302 // Assembly path: wrap call with .option push/exact/pop and emit LPAD
303 // separately so the output is human-readable.
304 RISCVTargetStreamer &RTS = getTargetStreamer();
305 if (HasZca && HasRelax) {
306 RTS.emitDirectiveOptionPush();
307 RTS.emitDirectiveOptionExact();
308 }
309
310 MCInst CallInst;
311 if (!IsIndirect) {
312 MCOperand MCOp;
313 lowerOperand(MO: MI.getOperand(i: 0), MCOp);
314 CallInst = MCInstBuilder(RISCV::PseudoCALL).addOperand(Op: MCOp);
315 } else {
316 CallInst = MCInstBuilder(RISCV::JALR)
317 .addReg(Reg: RISCV::X1)
318 .addReg(Reg: MI.getOperand(i: 0).getReg())
319 .addImm(Val: 0);
320 }
321
322 if (HasZca && HasRelax) {
323 MCSubtargetInfo NoRelaxSTI(MCSTI);
324 NoRelaxSTI.ToggleFeature(FB: RISCV::FeatureRelax);
325 EmitToStreamer(S&: *OutStreamer, Inst: CallInst, SubtargetInfo: NoRelaxSTI);
326 RTS.emitDirectiveOptionPop();
327 } else {
328 EmitToStreamer(S&: *OutStreamer, Inst: CallInst, SubtargetInfo: MCSTI);
329 }
330
331 // LPAD is encoded as AUIPC X0, label.
332 MCInst LpadInst = MCInstBuilder(RISCV::AUIPC)
333 .addReg(Reg: RISCV::X0)
334 .addImm(Val: MI.getOperand(i: 1).getImm());
335 EmitToStreamer(S&: *OutStreamer, Inst: LpadInst, SubtargetInfo: MCSTI);
336 } else {
337 // Object path: emit PseudoCALL(Indirect)LpadAlign directly.
338 // MCCodeEmitter::expandFunctionCallLpad expands to AUIPC+JALR+LPAD
339 // without emitting R_RISCV_RELAX on the call fixup.
340 MCInst TmpInst;
341 TmpInst.setOpcode(MI.getOpcode());
342 if (!IsIndirect) {
343 MCOperand MCOp;
344 lowerOperand(MO: MI.getOperand(i: 0), MCOp);
345 TmpInst.addOperand(Op: MCOp);
346 } else {
347 TmpInst.addOperand(Op: MCOperand::createReg(Reg: MI.getOperand(i: 0).getReg()));
348 }
349 TmpInst.addOperand(Op: MCOperand::createImm(Val: MI.getOperand(i: 1).getImm()));
350 EmitToStreamer(S&: *OutStreamer, Inst: TmpInst, SubtargetInfo: MCSTI);
351 }
352}
353
354// If the instruction has a nontemporal MachineMemOperand, emit an NTL hint
355// instruction before it. NTL hints are always safe to emit since they use
356// HINT encodings that are guaranteed not to trap
357// (riscv-non-isa/riscv-elf-psabi-doc#474).
358void RISCVAsmPrinter::emitNTLHint(const MachineInstr *MI) {
359 if (!STI->getInstrInfo()->requiresNTLHint(MI: *MI))
360 return;
361
362 assert(!MI->memoperands_empty());
363
364 MachineMemOperand *MMO = *(MI->memoperands_begin());
365
366 assert(MMO->isNonTemporal());
367
368 unsigned NontemporalMode = 0;
369 if (MMO->getFlags() & MONontemporalBit0)
370 NontemporalMode += 0b1;
371 if (MMO->getFlags() & MONontemporalBit1)
372 NontemporalMode += 0b10;
373
374 MCInst Hint;
375 if (STI->hasStdExtZca())
376 Hint.setOpcode(RISCV::C_ADD);
377 else
378 Hint.setOpcode(RISCV::ADD);
379
380 Hint.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
381 Hint.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
382 Hint.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2 + NontemporalMode));
383
384 EmitToStreamer(S&: *OutStreamer, Inst: Hint);
385}
386
387void RISCVAsmPrinter::emitInstruction(const MachineInstr *MI) {
388 RISCV_MC::verifyInstructionPredicates(Opcode: MI->getOpcode(), Features: STI->getFeatureBits());
389
390 emitNTLHint(MI);
391
392 // Do any auto-generated pseudo lowerings.
393 if (MCInst OutInst; lowerPseudoInstExpansion(MI, Inst&: OutInst)) {
394 EmitToStreamer(S&: *OutStreamer, Inst: OutInst);
395 return;
396 }
397
398 switch (MI->getOpcode()) {
399 case RISCV::PseudoTAILX7: {
400 // Lower to PseudoTAILReg with X7 as the register operand.
401 MCOperand SymOp;
402 lowerOperand(MO: MI->getOperand(i: 0), MCOp&: SymOp);
403 MCInst TmpInst;
404 TmpInst.setOpcode(RISCV::PseudoTAILReg);
405 TmpInst.addOperand(Op: SymOp);
406 TmpInst.addOperand(Op: MCOperand::createReg(Reg: RISCV::X7));
407 EmitToStreamer(S&: *OutStreamer, Inst: TmpInst);
408 return;
409 }
410 case RISCV::HWASAN_CHECK_MEMACCESS_SHORTGRANULES:
411 LowerHWASAN_CHECK_MEMACCESS(MI: *MI);
412 return;
413 case RISCV::KCFI_CHECK:
414 LowerKCFI_CHECK(MI: *MI);
415 return;
416 case TargetOpcode::STACKMAP:
417 return LowerSTACKMAP(OutStreamer&: *OutStreamer, SM, MI: *MI);
418 case TargetOpcode::PATCHPOINT:
419 return LowerPATCHPOINT(OutStreamer&: *OutStreamer, SM, MI: *MI);
420 case TargetOpcode::STATEPOINT:
421 return LowerSTATEPOINT(OutStreamer&: *OutStreamer, SM, MI: *MI);
422 case TargetOpcode::PATCHABLE_FUNCTION_ENTER: {
423 const Function &F = MI->getParent()->getParent()->getFunction();
424 if (F.hasFnAttribute(Kind: "patchable-function-entry")) {
425 unsigned Num =
426 F.getFnAttributeAsParsedInteger(Kind: "patchable-function-entry");
427 emitNops(N: Num);
428 return;
429 }
430 LowerPATCHABLE_FUNCTION_ENTER(MI);
431 return;
432 }
433 case TargetOpcode::PATCHABLE_FUNCTION_EXIT:
434 LowerPATCHABLE_FUNCTION_EXIT(MI);
435 return;
436 case TargetOpcode::PATCHABLE_TAIL_CALL:
437 LowerPATCHABLE_TAIL_CALL(MI);
438 return;
439 case RISCV::PseudoCALLLpadAlign:
440 case RISCV::PseudoCALLIndirectLpadAlign:
441 emitLpadAlignedCall(MI: *MI);
442 return;
443 }
444
445 MCInst OutInst;
446 lowerToMCInst(MI, OutMI&: OutInst);
447 EmitToStreamer(S&: *OutStreamer, Inst: OutInst);
448}
449
450bool RISCVAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
451 const char *ExtraCode, raw_ostream &OS) {
452 // First try the generic code, which knows about modifiers like 'c' and 'n'.
453 if (!AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS))
454 return false;
455
456 const MachineOperand &MO = MI->getOperand(i: OpNo);
457 if (ExtraCode && ExtraCode[0]) {
458 if (ExtraCode[1] != 0)
459 return true; // Unknown modifier.
460
461 switch (ExtraCode[0]) {
462 default:
463 return true; // Unknown modifier.
464 case 'z': // Print zero register if zero, regular printing otherwise.
465 if (MO.isImm() && MO.getImm() == 0) {
466 OS << RISCVInstPrinter::getRegisterName(Reg: RISCV::X0);
467 return false;
468 }
469 break;
470 case 'i': // Literal 'i' if operand is not a register.
471 if (!MO.isReg())
472 OS << 'i';
473 return false;
474 case 'N': // Print the register encoding as an integer (0-31)
475 if (!MO.isReg())
476 return true;
477
478 const RISCVRegisterInfo *TRI = STI->getRegisterInfo();
479 OS << TRI->getEncodingValue(Reg: MO.getReg());
480 return false;
481 }
482 }
483
484 switch (MO.getType()) {
485 case MachineOperand::MO_Immediate:
486 OS << MO.getImm();
487 return false;
488 case MachineOperand::MO_Register:
489 OS << RISCVInstPrinter::getRegisterName(Reg: MO.getReg());
490 return false;
491 case MachineOperand::MO_GlobalAddress:
492 PrintSymbolOperand(MO, OS);
493 return false;
494 case MachineOperand::MO_BlockAddress: {
495 MCSymbol *Sym = GetBlockAddressSymbol(BA: MO.getBlockAddress());
496 Sym->print(OS, MAI);
497 return false;
498 }
499 default:
500 break;
501 }
502
503 return true;
504}
505
506bool RISCVAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
507 unsigned OpNo,
508 const char *ExtraCode,
509 raw_ostream &OS) {
510 if (ExtraCode)
511 return AsmPrinter::PrintAsmMemoryOperand(MI, OpNo, ExtraCode, OS);
512
513 const MachineOperand &AddrReg = MI->getOperand(i: OpNo);
514 assert(MI->getNumOperands() > OpNo + 1 && "Expected additional operand");
515 const MachineOperand &Offset = MI->getOperand(i: OpNo + 1);
516 // All memory operands should have a register and an immediate operand (see
517 // RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand).
518 if (!AddrReg.isReg())
519 return true;
520 if (!Offset.isImm() && !Offset.isGlobal() && !Offset.isBlockAddress() &&
521 !Offset.isMCSymbol())
522 return true;
523
524 MCOperand MCO;
525 if (!lowerOperand(MO: Offset, MCOp&: MCO))
526 return true;
527
528 if (Offset.isImm())
529 OS << MCO.getImm();
530 else if (Offset.isGlobal() || Offset.isBlockAddress() || Offset.isMCSymbol())
531 MAI.printExpr(OS, *MCO.getExpr());
532
533 if (Offset.isMCSymbol())
534 MMI->getContext().registerInlineAsmLabel(Sym: Offset.getMCSymbol());
535 if (Offset.isBlockAddress()) {
536 const BlockAddress *BA = Offset.getBlockAddress();
537 MCSymbol *Sym = GetBlockAddressSymbol(BA);
538 MMI->getContext().registerInlineAsmLabel(Sym);
539 }
540
541 OS << "(" << RISCVInstPrinter::getRegisterName(Reg: AddrReg.getReg()) << ")";
542 return false;
543}
544
545bool RISCVAsmPrinter::emitTargetFeaturePush(const MCSubtargetInfo &STI) {
546 RISCVTargetStreamer &RTS = getTargetStreamer();
547 SmallVector<RISCVOptionArchArg> NeedEmitStdOptionArgs;
548 const MCSubtargetInfo &MCSTI = TM.getMCSubtargetInfo();
549 for (const auto &Feature : MCSTI.getAllProcessorFeatures()) {
550 if (STI.hasFeature(Feature: Feature.Value) == MCSTI.hasFeature(Feature: Feature.Value))
551 continue;
552
553 if (!llvm::RISCVISAInfo::isSupportedExtensionFeature(Ext: Feature.key()))
554 continue;
555
556 auto Delta = STI.hasFeature(Feature: Feature.Value) ? RISCVOptionArchArgType::Plus
557 : RISCVOptionArchArgType::Minus;
558 StringRef ExtName = Feature.key();
559 ExtName.consume_front(Prefix: "experimental-");
560 NeedEmitStdOptionArgs.emplace_back(Args&: Delta, Args: ExtName.str());
561 }
562 if (!NeedEmitStdOptionArgs.empty()) {
563 RTS.emitDirectiveOptionPush();
564 RTS.emitDirectiveOptionArch(Args: NeedEmitStdOptionArgs);
565 return true;
566 }
567
568 return false;
569}
570
571void RISCVAsmPrinter::emitTargetFeaturePop(const MCSubtargetInfo &STI,
572 bool DidPush) {
573 if (DidPush)
574 getTargetStreamer().emitDirectiveOptionPop();
575}
576
577bool RISCVAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
578 STI = &MF.getSubtarget<RISCVSubtarget>();
579
580 bool EmittedOptionArch = emitTargetFeaturePush(STI: *STI);
581
582 SetupMachineFunction(MF);
583 emitFunctionBody();
584
585 // Emit the XRay table
586 emitXRayTable();
587
588 emitTargetFeaturePop(STI: *STI, DidPush: EmittedOptionArch);
589 return false;
590}
591
592void RISCVAsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr *MI) {
593 emitSled(MI, Kind: SledKind::FUNCTION_ENTER);
594}
595
596void RISCVAsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr *MI) {
597 emitSled(MI, Kind: SledKind::FUNCTION_EXIT);
598}
599
600void RISCVAsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr *MI) {
601 emitSled(MI, Kind: SledKind::TAIL_CALL);
602}
603
604void RISCVAsmPrinter::emitSled(const MachineInstr *MI, SledKind Kind) {
605 // We want to emit the jump instruction and the nops constituting the sled.
606 // The format is as follows:
607 // .Lxray_sled_N
608 // ALIGN
609 // J .tmpN
610 // 21 or 33 C.NOP instructions
611 // .tmpN
612
613 // The following variable holds the count of the number of NOPs to be patched
614 // in for XRay instrumentation during compilation.
615 // Note that RV64 and RV32 each has a sled of 68 and 44 bytes, respectively.
616 // Assuming we're using JAL to jump to .tmpN, then we only need
617 // (68 - 4)/2 = 32 NOPs for RV64 and (44 - 4)/2 = 20 for RV32. However, there
618 // is a chance that we'll use C.JAL instead, so an additional NOP is needed.
619 const uint8_t NoopsInSledCount = STI->is64Bit() ? 33 : 21;
620
621 OutStreamer->emitCodeAlignment(Alignment: Align(4), STI: *STI);
622 auto CurSled = OutContext.createTempSymbol(Name: "xray_sled_", AlwaysAddSuffix: true);
623 OutStreamer->emitLabel(Symbol: CurSled);
624 auto Target = OutContext.createTempSymbol();
625
626 const MCExpr *TargetExpr = MCSymbolRefExpr::create(Symbol: Target, Ctx&: OutContext);
627
628 // Emit "J bytes" instruction, which jumps over the nop sled to the actual
629 // start of function.
630 EmitToStreamer(
631 S&: *OutStreamer,
632 Inst: MCInstBuilder(RISCV::JAL).addReg(Reg: RISCV::X0).addExpr(Val: TargetExpr));
633
634 // Emit NOP instructions
635 for (int8_t I = 0; I < NoopsInSledCount; ++I)
636 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(RISCV::ADDI)
637 .addReg(Reg: RISCV::X0)
638 .addReg(Reg: RISCV::X0)
639 .addImm(Val: 0));
640
641 OutStreamer->emitLabel(Symbol: Target);
642 recordSled(Sled: CurSled, MI: *MI, Kind, Version: 2);
643}
644
645void RISCVAsmPrinter::emitStartOfAsmFile(Module &M) {
646 assert(OutStreamer->getTargetStreamer() &&
647 "target streamer is uninitialized");
648 RISCVTargetStreamer &RTS = getTargetStreamer();
649 if (const MDString *ModuleTargetABI =
650 dyn_cast_or_null<MDString>(Val: M.getModuleFlag(Key: "target-abi")))
651 RTS.setTargetABI(RISCVABI::getTargetABI(ABIName: ModuleTargetABI->getString()));
652 else if (!RTS.hasTargetABI())
653 RTS.setTargetABI(
654 cantFail(ValOrErr: RISCVABI::computeTargetABI(STI: TM.getMCSubtargetInfo(), ABIName: "")));
655
656 MCSubtargetInfo SubtargetInfo = TM.getMCSubtargetInfo();
657
658 // Use module flag to update feature bits.
659 if (auto *MD = dyn_cast_or_null<MDNode>(Val: M.getModuleFlag(Key: "riscv-isa"))) {
660 for (auto &ISA : MD->operands()) {
661 if (auto *ISAString = dyn_cast_or_null<MDString>(Val: ISA)) {
662 auto ParseResult = llvm::RISCVISAInfo::parseArchString(
663 Arch: ISAString->getString(), /*EnableExperimentalExtension=*/true,
664 /*ExperimentalExtensionVersionCheck=*/true);
665 if (!errorToBool(Err: ParseResult.takeError())) {
666 auto &ISAInfo = *ParseResult;
667 for (const auto &Feature : SubtargetInfo.getAllProcessorFeatures()) {
668 if (ISAInfo->hasExtension(Ext: Feature.key()) &&
669 !SubtargetInfo.hasFeature(Feature: Feature.Value))
670 SubtargetInfo.ToggleFeature(FS: Feature.key());
671 }
672 }
673 }
674 }
675
676 RTS.setFlagsFromFeatures(SubtargetInfo);
677 }
678
679 if (TM.getTargetTriple().isOSBinFormatELF())
680 emitAttributes(SubtargetInfo);
681}
682
683void RISCVAsmPrinter::emitEndOfAsmFile(Module &M) {
684 RISCVTargetStreamer &RTS = getTargetStreamer();
685
686 if (TM.getTargetTriple().isOSBinFormatELF()) {
687 RTS.finishAttributeSection();
688 emitNoteGnuProperty(M);
689 }
690 EmitHwasanMemaccessSymbols(M);
691}
692
693void RISCVAsmPrinter::emitAttributes(const MCSubtargetInfo &SubtargetInfo) {
694 RISCVTargetStreamer &RTS = getTargetStreamer();
695 // Use MCSubtargetInfo from TargetMachine. Individual functions may have
696 // attributes that differ from other functions in the module and we have no
697 // way to know which function is correct.
698 RTS.emitTargetAttributes(STI: SubtargetInfo, /*EmitStackAlign*/ true);
699}
700
701void RISCVAsmPrinter::emitFunctionEntryLabel() {
702 const auto *RMFI = MF->getInfo<RISCVMachineFunctionInfo>();
703 if (RMFI->isVectorCall()) {
704 RISCVTargetStreamer &RTS = getTargetStreamer();
705 RTS.emitDirectiveVariantCC(Symbol&: *CurrentFnSym);
706 }
707 return AsmPrinter::emitFunctionEntryLabel();
708}
709
710// Force static initialization.
711extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
712LLVMInitializeRISCVAsmPrinter() {
713 RegisterAsmPrinter<RISCVAsmPrinter> X(getTheRISCV32Target());
714 RegisterAsmPrinter<RISCVAsmPrinter> Y(getTheRISCV64Target());
715 RegisterAsmPrinter<RISCVAsmPrinter> A(getTheRISCV32beTarget());
716 RegisterAsmPrinter<RISCVAsmPrinter> B(getTheRISCV64beTarget());
717}
718
719void RISCVAsmPrinter::LowerHWASAN_CHECK_MEMACCESS(const MachineInstr &MI) {
720 Register Reg = MI.getOperand(i: 0).getReg();
721 uint32_t AccessInfo = MI.getOperand(i: 1).getImm();
722 MCSymbol *&Sym =
723 HwasanMemaccessSymbols[HwasanMemaccessTuple(Reg, AccessInfo)];
724 if (!Sym) {
725 // FIXME: Make this work on non-ELF.
726 if (!TM.getTargetTriple().isOSBinFormatELF())
727 report_fatal_error(reason: "llvm.hwasan.check.memaccess only supported on ELF");
728
729 std::string SymName = "__hwasan_check_x" + utostr(X: Reg - RISCV::X0) + "_" +
730 utostr(X: AccessInfo) + "_short";
731 Sym = OutContext.getOrCreateSymbol(Name: SymName);
732 }
733 auto Res = MCSymbolRefExpr::create(Symbol: Sym, Ctx&: OutContext);
734 auto Expr = MCSpecifierExpr::create(Expr: Res, S: RISCV::S_CALL_PLT, Ctx&: OutContext);
735
736 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(RISCV::PseudoCALL).addExpr(Val: Expr));
737}
738
739void RISCVAsmPrinter::LowerKCFI_CHECK(const MachineInstr &MI) {
740 Register AddrReg = MI.getOperand(i: 0).getReg();
741 assert(std::next(MI.getIterator())->isCall() &&
742 "KCFI_CHECK not followed by a call instruction");
743 assert(std::next(MI.getIterator())->getOperand(0).getReg() == AddrReg &&
744 "KCFI_CHECK call target doesn't match call operand");
745
746 // Temporary registers for comparing the hashes. If a register is used
747 // for the call target, or reserved by the user, we can clobber another
748 // temporary register as the check is immediately followed by the
749 // call. The check defaults to X6/X7, but can fall back to X28-X31 if
750 // needed.
751 unsigned ScratchRegs[] = {RISCV::X6, RISCV::X7};
752 unsigned NextReg = RISCV::X28;
753 auto isRegAvailable = [&](unsigned Reg) {
754 return Reg != AddrReg && !STI->isRegisterReservedByUser(i: Reg);
755 };
756 for (auto &Reg : ScratchRegs) {
757 if (isRegAvailable(Reg))
758 continue;
759 while (!isRegAvailable(NextReg))
760 ++NextReg;
761 Reg = NextReg++;
762 if (Reg > RISCV::X31)
763 report_fatal_error(reason: "Unable to find scratch registers for KCFI_CHECK");
764 }
765
766 if (AddrReg == RISCV::X0) {
767 // Checking X0 makes no sense. Instead of emitting a load, zero
768 // ScratchRegs[0].
769 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(RISCV::ADDI)
770 .addReg(Reg: ScratchRegs[0])
771 .addReg(Reg: RISCV::X0)
772 .addImm(Val: 0));
773 } else {
774 // Adjust the offset for patchable-function-prefix. This assumes that
775 // patchable-function-prefix is the same for all functions.
776 int NopSize = STI->hasStdExtZca() ? 2 : 4;
777 int64_t PrefixNops =
778 MI.getMF()->getFunction().getFnAttributeAsParsedInteger(
779 Kind: "patchable-function-prefix");
780
781 // Load the target function type hash.
782 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(RISCV::LW)
783 .addReg(Reg: ScratchRegs[0])
784 .addReg(Reg: AddrReg)
785 .addImm(Val: -(PrefixNops * NopSize + 4)));
786 }
787
788 // Load the expected 32-bit type hash.
789 const int64_t Type = MI.getOperand(i: 1).getImm();
790 const int64_t Hi20 = ((Type + 0x800) >> 12) & 0xFFFFF;
791 const int64_t Lo12 = SignExtend64<12>(x: Type);
792 if (Hi20) {
793 EmitToStreamer(
794 S&: *OutStreamer,
795 Inst: MCInstBuilder(RISCV::LUI).addReg(Reg: ScratchRegs[1]).addImm(Val: Hi20));
796 }
797 if (Lo12 || Hi20 == 0) {
798 EmitToStreamer(S&: *OutStreamer,
799 Inst: MCInstBuilder((STI->hasFeature(Feature: RISCV::Feature64Bit) && Hi20)
800 ? RISCV::ADDIW
801 : RISCV::ADDI)
802 .addReg(Reg: ScratchRegs[1])
803 .addReg(Reg: ScratchRegs[1])
804 .addImm(Val: Lo12));
805 }
806
807 // Compare the hashes and trap if there's a mismatch.
808 MCSymbol *Pass = OutContext.createTempSymbol();
809 EmitToStreamer(S&: *OutStreamer,
810 Inst: MCInstBuilder(RISCV::BEQ)
811 .addReg(Reg: ScratchRegs[0])
812 .addReg(Reg: ScratchRegs[1])
813 .addExpr(Val: MCSymbolRefExpr::create(Symbol: Pass, Ctx&: OutContext)));
814
815 MCSymbol *Trap = OutContext.createTempSymbol();
816 OutStreamer->emitLabel(Symbol: Trap);
817 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(RISCV::EBREAK));
818 emitKCFITrapEntry(MF: *MI.getMF(), Symbol: Trap);
819 OutStreamer->emitLabel(Symbol: Pass);
820}
821
822void RISCVAsmPrinter::EmitHwasanMemaccessSymbols(Module &M) {
823 if (HwasanMemaccessSymbols.empty())
824 return;
825
826 assert(TM.getTargetTriple().isOSBinFormatELF());
827 // Use MCSubtargetInfo from TargetMachine. Individual functions may have
828 // attributes that differ from other functions in the module and we have no
829 // way to know which function is correct.
830 const MCSubtargetInfo &MCSTI = TM.getMCSubtargetInfo();
831
832 MCSymbol *HwasanTagMismatchV2Sym =
833 OutContext.getOrCreateSymbol(Name: "__hwasan_tag_mismatch_v2");
834 // Annotate symbol as one having incompatible calling convention, so
835 // run-time linkers can instead eagerly bind this function.
836 RISCVTargetStreamer &RTS = getTargetStreamer();
837 RTS.emitDirectiveVariantCC(Symbol&: *HwasanTagMismatchV2Sym);
838
839 const MCSymbolRefExpr *HwasanTagMismatchV2Ref =
840 MCSymbolRefExpr::create(Symbol: HwasanTagMismatchV2Sym, Ctx&: OutContext);
841 auto Expr = MCSpecifierExpr::create(Expr: HwasanTagMismatchV2Ref, S: RISCV::S_CALL_PLT,
842 Ctx&: OutContext);
843
844 for (auto &P : HwasanMemaccessSymbols) {
845 unsigned Reg = std::get<0>(t: P.first);
846 uint32_t AccessInfo = std::get<1>(t: P.first);
847 MCSymbol *Sym = P.second;
848
849 unsigned Size =
850 1 << ((AccessInfo >> HWASanAccessInfo::AccessSizeShift) & 0xf);
851 OutStreamer->switchSection(Section: OutContext.getELFSection(
852 Section: ".text.hot", Type: ELF::SHT_PROGBITS,
853 Flags: ELF::SHF_EXECINSTR | ELF::SHF_ALLOC | ELF::SHF_GROUP, EntrySize: 0, Group: Sym->getName(),
854 /*IsComdat=*/true));
855
856 OutStreamer->emitSymbolAttribute(Symbol: Sym, Attribute: MCSA_ELF_TypeFunction);
857 OutStreamer->emitSymbolAttribute(Symbol: Sym, Attribute: MCSA_Weak);
858 OutStreamer->emitSymbolAttribute(Symbol: Sym, Attribute: MCSA_Hidden);
859 OutStreamer->emitLabel(Symbol: Sym);
860
861 // Extract shadow offset from ptr
862 EmitToStreamer(
863 S&: *OutStreamer,
864 Inst: MCInstBuilder(RISCV::SLLI).addReg(Reg: RISCV::X6).addReg(Reg).addImm(Val: 8),
865 SubtargetInfo: MCSTI);
866 EmitToStreamer(S&: *OutStreamer,
867 Inst: MCInstBuilder(RISCV::SRLI)
868 .addReg(Reg: RISCV::X6)
869 .addReg(Reg: RISCV::X6)
870 .addImm(Val: 12),
871 SubtargetInfo: MCSTI);
872 // load shadow tag in X6, X5 contains shadow base
873 EmitToStreamer(S&: *OutStreamer,
874 Inst: MCInstBuilder(RISCV::ADD)
875 .addReg(Reg: RISCV::X6)
876 .addReg(Reg: RISCV::X5)
877 .addReg(Reg: RISCV::X6),
878 SubtargetInfo: MCSTI);
879 EmitToStreamer(
880 S&: *OutStreamer,
881 Inst: MCInstBuilder(RISCV::LBU).addReg(Reg: RISCV::X6).addReg(Reg: RISCV::X6).addImm(Val: 0),
882 SubtargetInfo: MCSTI);
883 // Extract tag from pointer and compare it with loaded tag from shadow
884 EmitToStreamer(
885 S&: *OutStreamer,
886 Inst: MCInstBuilder(RISCV::SRLI).addReg(Reg: RISCV::X7).addReg(Reg).addImm(Val: 56),
887 SubtargetInfo: MCSTI);
888 MCSymbol *HandleMismatchOrPartialSym = OutContext.createTempSymbol();
889 // X7 contains tag from the pointer, while X6 contains tag from memory
890 EmitToStreamer(S&: *OutStreamer,
891 Inst: MCInstBuilder(RISCV::BNE)
892 .addReg(Reg: RISCV::X7)
893 .addReg(Reg: RISCV::X6)
894 .addExpr(Val: MCSymbolRefExpr::create(
895 Symbol: HandleMismatchOrPartialSym, Ctx&: OutContext)),
896 SubtargetInfo: MCSTI);
897 MCSymbol *ReturnSym = OutContext.createTempSymbol();
898 OutStreamer->emitLabel(Symbol: ReturnSym);
899 EmitToStreamer(S&: *OutStreamer,
900 Inst: MCInstBuilder(RISCV::JALR)
901 .addReg(Reg: RISCV::X0)
902 .addReg(Reg: RISCV::X1)
903 .addImm(Val: 0),
904 SubtargetInfo: MCSTI);
905 OutStreamer->emitLabel(Symbol: HandleMismatchOrPartialSym);
906
907 EmitToStreamer(S&: *OutStreamer,
908 Inst: MCInstBuilder(RISCV::ADDI)
909 .addReg(Reg: RISCV::X28)
910 .addReg(Reg: RISCV::X0)
911 .addImm(Val: 16),
912 SubtargetInfo: MCSTI);
913 MCSymbol *HandleMismatchSym = OutContext.createTempSymbol();
914 EmitToStreamer(
915 S&: *OutStreamer,
916 Inst: MCInstBuilder(RISCV::BGEU)
917 .addReg(Reg: RISCV::X6)
918 .addReg(Reg: RISCV::X28)
919 .addExpr(Val: MCSymbolRefExpr::create(Symbol: HandleMismatchSym, Ctx&: OutContext)),
920 SubtargetInfo: MCSTI);
921
922 EmitToStreamer(
923 S&: *OutStreamer,
924 Inst: MCInstBuilder(RISCV::ANDI).addReg(Reg: RISCV::X28).addReg(Reg).addImm(Val: 0xF),
925 SubtargetInfo: MCSTI);
926
927 if (Size != 1)
928 EmitToStreamer(S&: *OutStreamer,
929 Inst: MCInstBuilder(RISCV::ADDI)
930 .addReg(Reg: RISCV::X28)
931 .addReg(Reg: RISCV::X28)
932 .addImm(Val: Size - 1),
933 SubtargetInfo: MCSTI);
934 EmitToStreamer(
935 S&: *OutStreamer,
936 Inst: MCInstBuilder(RISCV::BGE)
937 .addReg(Reg: RISCV::X28)
938 .addReg(Reg: RISCV::X6)
939 .addExpr(Val: MCSymbolRefExpr::create(Symbol: HandleMismatchSym, Ctx&: OutContext)),
940 SubtargetInfo: MCSTI);
941
942 EmitToStreamer(
943 S&: *OutStreamer,
944 Inst: MCInstBuilder(RISCV::ORI).addReg(Reg: RISCV::X6).addReg(Reg).addImm(Val: 0xF),
945 SubtargetInfo: MCSTI);
946 EmitToStreamer(
947 S&: *OutStreamer,
948 Inst: MCInstBuilder(RISCV::LBU).addReg(Reg: RISCV::X6).addReg(Reg: RISCV::X6).addImm(Val: 0),
949 SubtargetInfo: MCSTI);
950 EmitToStreamer(S&: *OutStreamer,
951 Inst: MCInstBuilder(RISCV::BEQ)
952 .addReg(Reg: RISCV::X6)
953 .addReg(Reg: RISCV::X7)
954 .addExpr(Val: MCSymbolRefExpr::create(Symbol: ReturnSym, Ctx&: OutContext)),
955 SubtargetInfo: MCSTI);
956
957 OutStreamer->emitLabel(Symbol: HandleMismatchSym);
958
959 // | Previous stack frames... |
960 // +=================================+ <-- [SP + 256]
961 // | ... |
962 // | |
963 // | Stack frame space for x12 - x31.|
964 // | |
965 // | ... |
966 // +---------------------------------+ <-- [SP + 96]
967 // | Saved x11(arg1), as |
968 // | __hwasan_check_* clobbers it. |
969 // +---------------------------------+ <-- [SP + 88]
970 // | Saved x10(arg0), as |
971 // | __hwasan_check_* clobbers it. |
972 // +---------------------------------+ <-- [SP + 80]
973 // | |
974 // | Stack frame space for x9. |
975 // +---------------------------------+ <-- [SP + 72]
976 // | |
977 // | Saved x8(fp), as |
978 // | __hwasan_check_* clobbers it. |
979 // +---------------------------------+ <-- [SP + 64]
980 // | ... |
981 // | |
982 // | Stack frame space for x2 - x7. |
983 // | |
984 // | ... |
985 // +---------------------------------+ <-- [SP + 16]
986 // | Return address (x1) for caller |
987 // | of __hwasan_check_*. |
988 // +---------------------------------+ <-- [SP + 8]
989 // | Reserved place for x0, possibly |
990 // | junk, since we don't save it. |
991 // +---------------------------------+ <-- [x2 / SP]
992
993 // Adjust sp
994 EmitToStreamer(S&: *OutStreamer,
995 Inst: MCInstBuilder(RISCV::ADDI)
996 .addReg(Reg: RISCV::X2)
997 .addReg(Reg: RISCV::X2)
998 .addImm(Val: -256),
999 SubtargetInfo: MCSTI);
1000
1001 // store x10(arg0) by new sp
1002 EmitToStreamer(S&: *OutStreamer,
1003 Inst: MCInstBuilder(RISCV::SD)
1004 .addReg(Reg: RISCV::X10)
1005 .addReg(Reg: RISCV::X2)
1006 .addImm(Val: 8 * 10),
1007 SubtargetInfo: MCSTI);
1008 // store x11(arg1) by new sp
1009 EmitToStreamer(S&: *OutStreamer,
1010 Inst: MCInstBuilder(RISCV::SD)
1011 .addReg(Reg: RISCV::X11)
1012 .addReg(Reg: RISCV::X2)
1013 .addImm(Val: 8 * 11),
1014 SubtargetInfo: MCSTI);
1015
1016 // store x8(fp) by new sp
1017 EmitToStreamer(
1018 S&: *OutStreamer,
1019 Inst: MCInstBuilder(RISCV::SD).addReg(Reg: RISCV::X8).addReg(Reg: RISCV::X2).addImm(Val: 8 *
1020 8),
1021 SubtargetInfo: MCSTI);
1022 // store x1(ra) by new sp
1023 EmitToStreamer(
1024 S&: *OutStreamer,
1025 Inst: MCInstBuilder(RISCV::SD).addReg(Reg: RISCV::X1).addReg(Reg: RISCV::X2).addImm(Val: 1 *
1026 8),
1027 SubtargetInfo: MCSTI);
1028 if (Reg != RISCV::X10)
1029 EmitToStreamer(
1030 S&: *OutStreamer,
1031 Inst: MCInstBuilder(RISCV::ADDI).addReg(Reg: RISCV::X10).addReg(Reg).addImm(Val: 0),
1032 SubtargetInfo: MCSTI);
1033 EmitToStreamer(S&: *OutStreamer,
1034 Inst: MCInstBuilder(RISCV::ADDI)
1035 .addReg(Reg: RISCV::X11)
1036 .addReg(Reg: RISCV::X0)
1037 .addImm(Val: AccessInfo & HWASanAccessInfo::RuntimeMask),
1038 SubtargetInfo: MCSTI);
1039
1040 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(RISCV::PseudoCALL).addExpr(Val: Expr),
1041 SubtargetInfo: MCSTI);
1042 }
1043}
1044
1045void RISCVAsmPrinter::emitNoteGnuProperty(const Module &M) {
1046 assert(TM.getTargetTriple().isOSBinFormatELF() && "invalid binary format");
1047 uint32_t GnuProps = 0;
1048 if (const Metadata *const Flag = M.getModuleFlag(Key: "cf-protection-return");
1049 Flag && !mdconst::extract<ConstantInt>(MD: Flag)->isZero())
1050 GnuProps |= ELF::GNU_PROPERTY_RISCV_FEATURE_1_CFI_SS;
1051
1052 if (const Metadata *const Flag = M.getModuleFlag(Key: "cf-protection-branch");
1053 Flag && !mdconst::extract<ConstantInt>(MD: Flag)->isZero()) {
1054 using namespace llvm::RISCVISAUtils;
1055 const Metadata *const CFBranchLabelSchemeFlag =
1056 M.getModuleFlag(Key: "cf-branch-label-scheme");
1057 assert(CFBranchLabelSchemeFlag &&
1058 "cf-protection=branch should come with cf-branch-label-scheme=... "
1059 "on RISC-V targets");
1060 const StringRef CFBranchLabelScheme =
1061 cast<MDString>(Val: CFBranchLabelSchemeFlag)->getString();
1062 switch (llvm::RISCVCFI::getZicfilpLabelScheme(CFBranchLabelScheme)) {
1063 case llvm::RISCVCFI::ZicfilpLabelSchemeKind::Invalid:
1064 reportFatalInternalError(reason: "invalid RISC-V Zicfilp label scheme");
1065 case llvm::RISCVCFI::ZicfilpLabelSchemeKind::Unlabeled:
1066 GnuProps |= ELF::GNU_PROPERTY_RISCV_FEATURE_1_CFI_LP_UNLABELED;
1067 break;
1068 case llvm::RISCVCFI::ZicfilpLabelSchemeKind::FuncSig:
1069 // TODO: Emit the func-sig bit after the feature is implemented
1070 reportFatalUsageError(reason: "the complete func-sig label scheme feature is not "
1071 "implemented yet");
1072 break;
1073 }
1074 }
1075
1076 if (!GnuProps)
1077 return;
1078
1079 auto &RTS = static_cast<RISCVTargetELFStreamer &>(getTargetStreamer());
1080 RTS.emitNoteGnuPropertySection(Feature1And: GnuProps);
1081}
1082
1083static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym,
1084 const AsmPrinter &AP) {
1085 MCContext &Ctx = AP.OutContext;
1086 RISCV::Specifier Kind;
1087
1088 switch (MO.getTargetFlags()) {
1089 default:
1090 llvm_unreachable("Unknown target flag on GV operand");
1091 case RISCVII::MO_None:
1092 Kind = RISCV::S_None;
1093 break;
1094 case RISCVII::MO_CALL:
1095 Kind = RISCV::S_CALL_PLT;
1096 break;
1097 case RISCVII::MO_LO:
1098 Kind = RISCV::S_LO;
1099 break;
1100 case RISCVII::MO_HI:
1101 Kind = ELF::R_RISCV_HI20;
1102 break;
1103 case RISCVII::MO_PCREL_LO:
1104 Kind = RISCV::S_PCREL_LO;
1105 break;
1106 case RISCVII::MO_PCREL_HI:
1107 Kind = RISCV::S_PCREL_HI;
1108 break;
1109 case RISCVII::MO_GOT_HI:
1110 Kind = RISCV::S_GOT_HI;
1111 break;
1112 case RISCVII::MO_TPREL_LO:
1113 Kind = RISCV::S_TPREL_LO;
1114 break;
1115 case RISCVII::MO_TPREL_HI:
1116 Kind = ELF::R_RISCV_TPREL_HI20;
1117 break;
1118 case RISCVII::MO_TPREL_ADD:
1119 Kind = ELF::R_RISCV_TPREL_ADD;
1120 break;
1121 case RISCVII::MO_TLS_GOT_HI:
1122 Kind = ELF::R_RISCV_TLS_GOT_HI20;
1123 break;
1124 case RISCVII::MO_TLS_GD_HI:
1125 Kind = ELF::R_RISCV_TLS_GD_HI20;
1126 break;
1127 case RISCVII::MO_TLSDESC_HI:
1128 Kind = ELF::R_RISCV_TLSDESC_HI20;
1129 break;
1130 case RISCVII::MO_TLSDESC_LOAD_LO:
1131 Kind = ELF::R_RISCV_TLSDESC_LOAD_LO12;
1132 break;
1133 case RISCVII::MO_TLSDESC_ADD_LO:
1134 Kind = ELF::R_RISCV_TLSDESC_ADD_LO12;
1135 break;
1136 case RISCVII::MO_TLSDESC_CALL:
1137 Kind = ELF::R_RISCV_TLSDESC_CALL;
1138 break;
1139 case RISCVII::MO_QC_ACCESS:
1140 Kind = RISCV::S_QC_ACCESS;
1141 break;
1142 }
1143
1144 const MCExpr *ME = MCSymbolRefExpr::create(Symbol: Sym, Ctx);
1145
1146 if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
1147 ME = MCBinaryExpr::createAdd(
1148 LHS: ME, RHS: MCConstantExpr::create(Value: MO.getOffset(), Ctx), Ctx);
1149
1150 if (Kind != RISCV::S_None)
1151 ME = MCSpecifierExpr::create(Expr: ME, S: Kind, Ctx);
1152 return MCOperand::createExpr(Val: ME);
1153}
1154
1155bool RISCVAsmPrinter::lowerOperand(const MachineOperand &MO,
1156 MCOperand &MCOp) const {
1157 switch (MO.getType()) {
1158 default:
1159 report_fatal_error(reason: "lowerOperand: unknown operand type");
1160 case MachineOperand::MO_Register:
1161 // Ignore all implicit register operands.
1162 if (MO.isImplicit())
1163 return false;
1164 MCOp = MCOperand::createReg(Reg: MO.getReg());
1165 break;
1166 case MachineOperand::MO_RegisterMask:
1167 // Regmasks are like implicit defs.
1168 return false;
1169 case MachineOperand::MO_Immediate:
1170 MCOp = MCOperand::createImm(Val: MO.getImm());
1171 break;
1172 case MachineOperand::MO_MachineBasicBlock:
1173 MCOp = lowerSymbolOperand(MO, Sym: MO.getMBB()->getSymbol(), AP: *this);
1174 break;
1175 case MachineOperand::MO_GlobalAddress:
1176 MCOp = lowerSymbolOperand(MO, Sym: getSymbolPreferLocal(GV: *MO.getGlobal()), AP: *this);
1177 break;
1178 case MachineOperand::MO_BlockAddress:
1179 MCOp = lowerSymbolOperand(MO, Sym: GetBlockAddressSymbol(BA: MO.getBlockAddress()),
1180 AP: *this);
1181 break;
1182 case MachineOperand::MO_ExternalSymbol:
1183 MCOp = lowerSymbolOperand(MO, Sym: GetExternalSymbolSymbol(Sym: MO.getSymbolName()),
1184 AP: *this);
1185 break;
1186 case MachineOperand::MO_ConstantPoolIndex:
1187 MCOp = lowerSymbolOperand(MO, Sym: GetCPISymbol(CPID: MO.getIndex()), AP: *this);
1188 break;
1189 case MachineOperand::MO_JumpTableIndex:
1190 MCOp = lowerSymbolOperand(MO, Sym: GetJTISymbol(JTID: MO.getIndex()), AP: *this);
1191 break;
1192 case MachineOperand::MO_MCSymbol:
1193 MCOp = lowerSymbolOperand(MO, Sym: MO.getMCSymbol(), AP: *this);
1194 break;
1195 }
1196 return true;
1197}
1198
1199static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI,
1200 MCInst &OutMI,
1201 const RISCVSubtarget *STI) {
1202 const RISCVVPseudosTable::PseudoInfo *RVV =
1203 RISCVVPseudosTable::getPseudoInfo(Pseudo: MI->getOpcode());
1204 if (!RVV)
1205 return false;
1206
1207 OutMI.setOpcode(RVV->BaseInstr);
1208
1209 const TargetInstrInfo *TII = STI->getInstrInfo();
1210 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
1211 assert(TRI && "TargetRegisterInfo expected");
1212
1213 const MCInstrDesc &MCID = MI->getDesc();
1214 uint64_t TSFlags = MCID.TSFlags;
1215 unsigned NumOps = MI->getNumExplicitOperands();
1216
1217 // Skip policy, SEW, VL, VXRM/FRM operands which are the last operands if
1218 // present.
1219 if (RISCVII::hasVecPolicyOp(TSFlags))
1220 --NumOps;
1221 if (RISCVII::hasSEWOp(TSFlags))
1222 --NumOps;
1223 if (RISCVII::hasVLOp(TSFlags))
1224 --NumOps;
1225 if (RISCVII::hasRoundModeOp(TSFlags))
1226 --NumOps;
1227 if (RISCVII::hasTWidenOp(TSFlags))
1228 --NumOps;
1229 if (RISCVII::hasTMOp(TSFlags))
1230 --NumOps;
1231 if (RISCVII::hasTKOp(TSFlags))
1232 --NumOps;
1233
1234 bool hasVLOutput = RISCVInstrInfo::isFaultOnlyFirstLoad(MI: *MI);
1235 for (unsigned OpNo = 0; OpNo != NumOps; ++OpNo) {
1236 const MachineOperand &MO = MI->getOperand(i: OpNo);
1237 // Skip vl output. It should be the second output.
1238 if (hasVLOutput && OpNo == 1)
1239 continue;
1240
1241 // Skip passthru op. It should be the first operand after the defs.
1242 if (OpNo == MI->getNumExplicitDefs() && MO.isReg() && MO.isTied()) {
1243 assert(MCID.getOperandConstraint(OpNo, MCOI::TIED_TO) == 0 &&
1244 "Expected tied to first def.");
1245 const MCInstrDesc &OutMCID = TII->get(Opcode: OutMI.getOpcode());
1246 // Skip if the next operand in OutMI is not supposed to be tied. Unless it
1247 // is a _TIED instruction.
1248 if (OutMCID.getOperandConstraint(OpNum: OutMI.getNumOperands(), Constraint: MCOI::TIED_TO) <
1249 0 &&
1250 !RISCVII::isTiedPseudo(TSFlags))
1251 continue;
1252 }
1253
1254 MCOperand MCOp;
1255 switch (MO.getType()) {
1256 default:
1257 llvm_unreachable("Unknown operand type");
1258 case MachineOperand::MO_Register: {
1259 Register Reg = MO.getReg();
1260
1261 if (RISCV::VRM2RegClass.contains(Reg) ||
1262 RISCV::VRM4RegClass.contains(Reg) ||
1263 RISCV::VRM8RegClass.contains(Reg)) {
1264 Reg = TRI->getSubReg(Reg, Idx: RISCV::sub_vrm1_0);
1265 assert(Reg && "Subregister does not exist");
1266 } else if (RISCV::FPR16RegClass.contains(Reg)) {
1267 Reg =
1268 TRI->getMatchingSuperReg(Reg, SubIdx: RISCV::sub_16, RC: &RISCV::FPR32RegClass);
1269 assert(Reg && "Subregister does not exist");
1270 } else if (RISCV::FPR64RegClass.contains(Reg)) {
1271 Reg = TRI->getSubReg(Reg, Idx: RISCV::sub_32);
1272 assert(Reg && "Superregister does not exist");
1273 } else if (RISCV::VRN2M1RegClass.contains(Reg) ||
1274 RISCV::VRN2M2RegClass.contains(Reg) ||
1275 RISCV::VRN2M4RegClass.contains(Reg) ||
1276 RISCV::VRN3M1RegClass.contains(Reg) ||
1277 RISCV::VRN3M2RegClass.contains(Reg) ||
1278 RISCV::VRN4M1RegClass.contains(Reg) ||
1279 RISCV::VRN4M2RegClass.contains(Reg) ||
1280 RISCV::VRN5M1RegClass.contains(Reg) ||
1281 RISCV::VRN6M1RegClass.contains(Reg) ||
1282 RISCV::VRN7M1RegClass.contains(Reg) ||
1283 RISCV::VRN8M1RegClass.contains(Reg)) {
1284 Reg = TRI->getSubReg(Reg, Idx: RISCV::sub_vrm1_0);
1285 assert(Reg && "Subregister does not exist");
1286 }
1287
1288 MCOp = MCOperand::createReg(Reg);
1289 break;
1290 }
1291 case MachineOperand::MO_Immediate:
1292 MCOp = MCOperand::createImm(Val: MO.getImm());
1293 break;
1294 }
1295 OutMI.addOperand(Op: MCOp);
1296 }
1297
1298 // Unmasked pseudo instructions need to append dummy mask operand to
1299 // V instructions. All V instructions are modeled as the masked version.
1300 const MCInstrDesc &OutMCID = TII->get(Opcode: OutMI.getOpcode());
1301 if (OutMI.getNumOperands() < OutMCID.getNumOperands()) {
1302 assert(OutMCID.operands()[OutMI.getNumOperands()].OperandType ==
1303 RISCVOp::OPERAND_VMASK &&
1304 "Expected only mask operand to be missing");
1305 OutMI.addOperand(Op: MCOperand::createReg(Reg: RISCV::NoRegister));
1306 }
1307
1308 assert(OutMI.getNumOperands() == OutMCID.getNumOperands());
1309 return true;
1310}
1311
1312void RISCVAsmPrinter::lowerToMCInst(const MachineInstr *MI, MCInst &OutMI) {
1313 if (lowerRISCVVMachineInstrToMCInst(MI, OutMI, STI))
1314 return;
1315
1316 OutMI.setOpcode(MI->getOpcode());
1317
1318 for (const MachineOperand &MO : MI->operands()) {
1319 MCOperand MCOp;
1320 if (lowerOperand(MO, MCOp))
1321 OutMI.addOperand(Op: MCOp);
1322 }
1323}
1324
1325void RISCVAsmPrinter::emitMachineConstantPoolValue(
1326 MachineConstantPoolValue *MCPV) {
1327 auto *RCPV = static_cast<RISCVConstantPoolValue *>(MCPV);
1328 MCSymbol *MCSym;
1329
1330 if (RCPV->isGlobalValue()) {
1331 auto *GV = RCPV->getGlobalValue();
1332 MCSym = getSymbol(GV);
1333 } else {
1334 assert(RCPV->isExtSymbol() && "unrecognized constant pool type");
1335 auto Sym = RCPV->getSymbol();
1336 MCSym = GetExternalSymbolSymbol(Sym);
1337 }
1338
1339 const MCExpr *Expr = MCSymbolRefExpr::create(Symbol: MCSym, Ctx&: OutContext);
1340 uint64_t Size = getDataLayout().getTypeAllocSize(Ty: RCPV->getType());
1341 OutStreamer->emitValue(Value: Expr, Size);
1342}
1343
1344MaybeAlign
1345RISCVAsmPrinter::getRequiredGlobalAlignmentGranule(const GlobalVariable &GV) {
1346 const MCSubtargetInfo &MCSTI = TM.getMCSubtargetInfo();
1347 if (!GV.getValueType()->isSized())
1348 return std::nullopt;
1349
1350 // When the alignment granule is determined by a CHERI requirement,
1351 // don't increase alignment if a custom section has been specified,
1352 // as doing so can break existing code that relies on the lack of
1353 // padding (e.g. linker sets).
1354 if (GV.hasSection())
1355 return std::nullopt;
1356
1357 uint64_t Size = GV.getGlobalSize(DL: getDataLayout());
1358 if (MCSTI.hasFeature(Feature: RISCV::FeatureVendorXCheriot))
1359 return CHERIoTCapabilityFormat::getRequiredAlignment(Length: Size);
1360
1361 if (MCSTI.hasFeature(Feature: RISCV::FeatureStdExtY)) {
1362 if (MCSTI.hasFeature(Feature: RISCV::Feature64Bit))
1363 return RV64YCapabilityFormat::getRequiredAlignment(Length: Size);
1364 else
1365 return RV32YCapabilityFormat::getRequiredAlignment(Length: Size);
1366 }
1367
1368 return std::nullopt;
1369}
1370
1371char RISCVAsmPrinter::ID = 0;
1372
1373INITIALIZE_PASS(RISCVAsmPrinter, "riscv-asm-printer", "RISC-V Assembly Printer",
1374 false, false)
1375
1376PreservedAnalyses RISCVAsmPrinterBeginPass::run(Module &M,
1377 ModuleAnalysisManager &MAM) {
1378 RISCVAsmPrinter &AsmPrinter = static_cast<RISCVAsmPrinter &>(
1379 MAM.getResult<AsmPrinterAnalysis>(IR&: M).getPrinter());
1380 setupModuleAsmPrinter(M, MAM, AsmPrinter);
1381 AsmPrinter.doInitialization(M);
1382 return PreservedAnalyses::all();
1383}
1384
1385PreservedAnalyses
1386RISCVAsmPrinterPass::run(MachineFunction &MF,
1387 MachineFunctionAnalysisManager &MFAM) {
1388 RISCVAsmPrinter &AsmPrinter = static_cast<RISCVAsmPrinter &>(
1389 MFAM.getResult<ModuleAnalysisManagerMachineFunctionProxy>(IR&: MF)
1390 .getCachedResult<AsmPrinterAnalysis>(IR&: *MF.getFunction().getParent())
1391 ->getPrinter());
1392 setupMachineFunctionAsmPrinter(MFAM, MF, AsmPrinter);
1393 AsmPrinter.runOnMachineFunction(MF);
1394 return PreservedAnalyses::all();
1395}
1396
1397PreservedAnalyses RISCVAsmPrinterEndPass::run(Module &M,
1398 ModuleAnalysisManager &MAM) {
1399 RISCVAsmPrinter &AsmPrinter = static_cast<RISCVAsmPrinter &>(
1400 MAM.getResult<AsmPrinterAnalysis>(IR&: M).getPrinter());
1401 setupModuleAsmPrinter(M, MAM, AsmPrinter);
1402 AsmPrinter.doFinalization(M);
1403 return PreservedAnalyses::all();
1404}
1405