1//===-- RISCVAsmPrinter.cpp - RISC-V LLVM assembly writer -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a printer that converts from our internal representation
10// of machine-dependent LLVM code to the RISC-V assembly language.
11//
12//===----------------------------------------------------------------------===//
13
14#include "RISCVAsmPrinter.h"
15#include "MCTargetDesc/RISCVBaseInfo.h"
16#include "MCTargetDesc/RISCVELFStreamer.h"
17#include "MCTargetDesc/RISCVInstPrinter.h"
18#include "MCTargetDesc/RISCVMCAsmInfo.h"
19#include "MCTargetDesc/RISCVMatInt.h"
20#include "MCTargetDesc/RISCVTargetStreamer.h"
21#include "RISCV.h"
22#include "RISCVConstantPoolValue.h"
23#include "RISCVMachineFunctionInfo.h"
24#include "RISCVRegisterInfo.h"
25#include "TargetInfo/RISCVTargetInfo.h"
26#include "llvm/ADT/APInt.h"
27#include "llvm/ADT/Statistic.h"
28#include "llvm/BinaryFormat/ELF.h"
29#include "llvm/CodeGen/AsmPrinter.h"
30#include "llvm/CodeGen/AsmPrinterAnalysis.h"
31#include "llvm/CodeGen/MachineConstantPool.h"
32#include "llvm/CodeGen/MachineFunctionAnalysisManager.h"
33#include "llvm/CodeGen/MachineInstr.h"
34#include "llvm/CodeGen/MachineModuleInfo.h"
35#include "llvm/IR/Module.h"
36#include "llvm/MC/MCAsmInfo.h"
37#include "llvm/MC/MCContext.h"
38#include "llvm/MC/MCInst.h"
39#include "llvm/MC/MCInstBuilder.h"
40#include "llvm/MC/MCObjectFileInfo.h"
41#include "llvm/MC/MCSectionELF.h"
42#include "llvm/MC/MCStreamer.h"
43#include "llvm/MC/MCSymbol.h"
44#include "llvm/MC/TargetRegistry.h"
45#include "llvm/Support/CHERICapabilityFormat.h"
46#include "llvm/Support/Compiler.h"
47#include "llvm/Support/raw_ostream.h"
48#include "llvm/TargetParser/RISCVISAInfo.h"
49#include "llvm/Transforms/Instrumentation/HWAddressSanitizer.h"
50
51using namespace llvm;
52
53#define DEBUG_TYPE "asm-printer"
54
55STATISTIC(RISCVNumInstrsCompressed,
56 "Number of RISC-V Compressed instructions emitted");
57
58namespace {
59class RISCVAsmPrinter : public AsmPrinter {
60public:
61 static char ID;
62
63private:
64 const RISCVSubtarget *STI;
65
66public:
67 explicit RISCVAsmPrinter(TargetMachine &TM,
68 std::unique_ptr<MCStreamer> Streamer)
69 : AsmPrinter(TM, std::move(Streamer), ID) {}
70
71 StringRef getPassName() const override { return "RISC-V Assembly Printer"; }
72
73 RISCVTargetStreamer &getTargetStreamer() const {
74 return static_cast<RISCVTargetStreamer &>(
75 *OutStreamer->getTargetStreamer());
76 }
77
78 void LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
79 const MachineInstr &MI);
80
81 void LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
82 const MachineInstr &MI);
83
84 void LowerSTATEPOINT(MCStreamer &OutStreamer, StackMaps &SM,
85 const MachineInstr &MI);
86
87 bool runOnMachineFunction(MachineFunction &MF) override;
88
89 void emitInstruction(const MachineInstr *MI) override;
90
91 void emitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override;
92
93 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
94 const char *ExtraCode, raw_ostream &OS) override;
95 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
96 const char *ExtraCode, raw_ostream &OS) override;
97
98 // Returns whether Inst is compressed.
99 bool EmitToStreamer(MCStreamer &S, const MCInst &Inst,
100 const MCSubtargetInfo &SubtargetInfo);
101 bool EmitToStreamer(MCStreamer &S, const MCInst &Inst) {
102 return EmitToStreamer(S, Inst, SubtargetInfo: *STI);
103 }
104
105 bool lowerPseudoInstExpansion(const MachineInstr *MI, MCInst &Inst);
106
107 typedef std::tuple<unsigned, uint32_t> HwasanMemaccessTuple;
108 std::map<HwasanMemaccessTuple, MCSymbol *> HwasanMemaccessSymbols;
109 void LowerHWASAN_CHECK_MEMACCESS(const MachineInstr &MI);
110 void LowerKCFI_CHECK(const MachineInstr &MI);
111 void EmitHwasanMemaccessSymbols(Module &M);
112
113 // Wrapper needed for tblgenned pseudo lowering.
114 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const;
115
116 void emitStartOfAsmFile(Module &M) override;
117 void emitEndOfAsmFile(Module &M) override;
118
119 void emitFunctionEntryLabel() override;
120 bool emitTargetFeaturePush(const MCSubtargetInfo &STI) override;
121 void emitTargetFeaturePop(const MCSubtargetInfo &STI, bool DidPush) override;
122
123 void emitNoteGnuProperty(const Module &M);
124
125private:
126 void emitAttributes(const MCSubtargetInfo &SubtargetInfo);
127
128 void emitNTLHint(const MachineInstr *MI);
129
130 void emitLpadAlignedCall(const MachineInstr &MI);
131
132 // XRay Support
133 void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr *MI);
134 void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr *MI);
135 void LowerPATCHABLE_TAIL_CALL(const MachineInstr *MI);
136 void emitSled(const MachineInstr *MI, SledKind Kind);
137
138 void lowerToMCInst(const MachineInstr *MI, MCInst &OutMI);
139
140 MaybeAlign
141 getRequiredGlobalAlignmentGranule(const GlobalVariable &GV) override;
142};
143} // namespace
144
145void RISCVAsmPrinter::LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
146 const MachineInstr &MI) {
147 unsigned NOPBytes = STI->hasStdExtZca() ? 2 : 4;
148 unsigned NumNOPBytes = StackMapOpers(&MI).getNumPatchBytes();
149
150 auto &Ctx = OutStreamer.getContext();
151 MCSymbol *MILabel = Ctx.createTempSymbol();
152 OutStreamer.emitLabel(Symbol: MILabel);
153
154 SM.recordStackMap(L: *MILabel, MI);
155 assert(NumNOPBytes % NOPBytes == 0 &&
156 "Invalid number of NOP bytes requested!");
157
158 // Scan ahead to trim the shadow.
159 const MachineBasicBlock &MBB = *MI.getParent();
160 MachineBasicBlock::const_iterator MII(MI);
161 ++MII;
162 while (NumNOPBytes > 0) {
163 if (MII == MBB.end() || MII->isCall() ||
164 MII->getOpcode() == RISCV::DBG_VALUE ||
165 MII->getOpcode() == TargetOpcode::PATCHPOINT ||
166 MII->getOpcode() == TargetOpcode::STACKMAP)
167 break;
168 ++MII;
169 NumNOPBytes -= NOPBytes;
170 }
171
172 // Emit nops.
173 emitNops(N: NumNOPBytes / NOPBytes);
174}
175
176// Lower a patchpoint of the form:
177// [<def>], <id>, <numBytes>, <target>, <numArgs>
178void RISCVAsmPrinter::LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
179 const MachineInstr &MI) {
180 unsigned NOPBytes = STI->hasStdExtZca() ? 2 : 4;
181
182 auto &Ctx = OutStreamer.getContext();
183 MCSymbol *MILabel = Ctx.createTempSymbol();
184 OutStreamer.emitLabel(Symbol: MILabel);
185 SM.recordPatchPoint(L: *MILabel, MI);
186
187 PatchPointOpers Opers(&MI);
188
189 const MachineOperand &CalleeMO = Opers.getCallTarget();
190 unsigned EncodedBytes = 0;
191
192 if (CalleeMO.isImm()) {
193 uint64_t CallTarget = CalleeMO.getImm();
194 if (CallTarget) {
195 assert((CallTarget & 0xFFFF'FFFF'FFFF) == CallTarget &&
196 "High 16 bits of call target should be zero.");
197 // Materialize the jump address:
198 SmallVector<MCInst, 8> Seq;
199 RISCVMatInt::generateMCInstSeq(Val: CallTarget, STI: *STI, DestReg: RISCV::X1, Insts&: Seq);
200 for (MCInst &Inst : Seq) {
201 bool Compressed = EmitToStreamer(S&: OutStreamer, Inst);
202 EncodedBytes += Compressed ? 2 : 4;
203 }
204 bool Compressed = EmitToStreamer(S&: OutStreamer, Inst: MCInstBuilder(RISCV::JALR)
205 .addReg(Reg: RISCV::X1)
206 .addReg(Reg: RISCV::X1)
207 .addImm(Val: 0));
208 EncodedBytes += Compressed ? 2 : 4;
209 }
210 } else if (CalleeMO.isGlobal()) {
211 MCOperand CallTargetMCOp;
212 lowerOperand(MO: CalleeMO, MCOp&: CallTargetMCOp);
213 EmitToStreamer(S&: OutStreamer,
214 Inst: MCInstBuilder(RISCV::PseudoCALL).addOperand(Op: CallTargetMCOp));
215 EncodedBytes += 8;
216 }
217
218 // Emit padding.
219 unsigned NumBytes = Opers.getNumPatchBytes();
220 assert(NumBytes >= EncodedBytes &&
221 "Patchpoint can't request size less than the length of a call.");
222 assert((NumBytes - EncodedBytes) % NOPBytes == 0 &&
223 "Invalid number of NOP bytes requested!");
224 emitNops(N: (NumBytes - EncodedBytes) / NOPBytes);
225}
226
227void RISCVAsmPrinter::LowerSTATEPOINT(MCStreamer &OutStreamer, StackMaps &SM,
228 const MachineInstr &MI) {
229 unsigned NOPBytes = STI->hasStdExtZca() ? 2 : 4;
230
231 StatepointOpers SOpers(&MI);
232 if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
233 assert(PatchBytes % NOPBytes == 0 &&
234 "Invalid number of NOP bytes requested!");
235 emitNops(N: PatchBytes / NOPBytes);
236 } else {
237 // Lower call target and choose correct opcode
238 const MachineOperand &CallTarget = SOpers.getCallTarget();
239 MCOperand CallTargetMCOp;
240 switch (CallTarget.getType()) {
241 case MachineOperand::MO_GlobalAddress:
242 case MachineOperand::MO_ExternalSymbol:
243 lowerOperand(MO: CallTarget, MCOp&: CallTargetMCOp);
244 EmitToStreamer(
245 S&: OutStreamer,
246 Inst: MCInstBuilder(RISCV::PseudoCALL).addOperand(Op: CallTargetMCOp));
247 break;
248 case MachineOperand::MO_Immediate:
249 CallTargetMCOp = MCOperand::createImm(Val: CallTarget.getImm());
250 EmitToStreamer(S&: OutStreamer, Inst: MCInstBuilder(RISCV::JAL)
251 .addReg(Reg: RISCV::X1)
252 .addOperand(Op: CallTargetMCOp));
253 break;
254 case MachineOperand::MO_Register:
255 CallTargetMCOp = MCOperand::createReg(Reg: CallTarget.getReg());
256 EmitToStreamer(S&: OutStreamer, Inst: MCInstBuilder(RISCV::JALR)
257 .addReg(Reg: RISCV::X1)
258 .addOperand(Op: CallTargetMCOp)
259 .addImm(Val: 0));
260 break;
261 default:
262 llvm_unreachable("Unsupported operand type in statepoint call target");
263 break;
264 }
265 }
266
267 auto &Ctx = OutStreamer.getContext();
268 MCSymbol *MILabel = Ctx.createTempSymbol();
269 OutStreamer.emitLabel(Symbol: MILabel);
270 SM.recordStatepoint(L: *MILabel, MI);
271}
272
273bool RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst,
274 const MCSubtargetInfo &SubtargetInfo) {
275 MCInst CInst;
276 bool Res = RISCVRVC::compress(OutInst&: CInst, MI: Inst, STI: SubtargetInfo);
277 if (Res)
278 ++RISCVNumInstrsCompressed;
279 S.emitInstruction(Inst: Res ? CInst : Inst, STI: SubtargetInfo);
280 return Res;
281}
282
283// Simple pseudo-instructions have their lowering (with expansion to real
284// instructions) auto-generated.
285#include "RISCVGenMCPseudoLowering.inc"
286
287// Emit a call to a returns_twice function with LPAD.
288// When Zca is enabled, emit .p2align 2 before the call to ensure the
289// following LPAD is 4-byte aligned. For assembly output, wrap with
290// .option push/exact/pop to prevent relaxation. For object output,
291// emit the pseudo directly so MCCodeEmitter handles it without R_RISCV_RELAX.
292void RISCVAsmPrinter::emitLpadAlignedCall(const MachineInstr &MI) {
293 const MCSubtargetInfo &MCSTI = getSubtargetInfo();
294 const bool IsIndirect = MI.getOpcode() == RISCV::PseudoCALLIndirectLpadAlign,
295 HasZca = MCSTI.hasFeature(Feature: RISCV::FeatureStdExtZca),
296 HasRelax = MCSTI.hasFeature(Feature: RISCV::FeatureRelax);
297
298 if (HasZca)
299 OutStreamer->emitCodeAlignment(Alignment: Align(4), STI: MCSTI);
300
301 if (OutStreamer->hasRawTextSupport()) {
302 // Assembly path: wrap call with .option push/exact/pop and emit LPAD
303 // separately so the output is human-readable.
304 RISCVTargetStreamer &RTS = getTargetStreamer();
305 if (HasZca && HasRelax) {
306 RTS.emitDirectiveOptionPush();
307 RTS.emitDirectiveOptionExact();
308 }
309
310 MCInst CallInst;
311 if (!IsIndirect) {
312 MCOperand MCOp;
313 lowerOperand(MO: MI.getOperand(i: 0), MCOp);
314 CallInst = MCInstBuilder(RISCV::PseudoCALL).addOperand(Op: MCOp);
315 } else {
316 CallInst = MCInstBuilder(RISCV::JALR)
317 .addReg(Reg: RISCV::X1)
318 .addReg(Reg: MI.getOperand(i: 0).getReg())
319 .addImm(Val: 0);
320 }
321
322 if (HasZca && HasRelax) {
323 MCSubtargetInfo NoRelaxSTI(MCSTI);
324 NoRelaxSTI.ToggleFeature(FB: RISCV::FeatureRelax);
325 EmitToStreamer(S&: *OutStreamer, Inst: CallInst, SubtargetInfo: NoRelaxSTI);
326 RTS.emitDirectiveOptionPop();
327 } else {
328 EmitToStreamer(S&: *OutStreamer, Inst: CallInst, SubtargetInfo: MCSTI);
329 }
330
331 // LPAD is encoded as AUIPC X0, label.
332 MCInst LpadInst = MCInstBuilder(RISCV::AUIPC)
333 .addReg(Reg: RISCV::X0)
334 .addImm(Val: MI.getOperand(i: 1).getImm());
335 EmitToStreamer(S&: *OutStreamer, Inst: LpadInst, SubtargetInfo: MCSTI);
336 } else {
337 // Object path: emit PseudoCALL(Indirect)LpadAlign directly.
338 // MCCodeEmitter::expandFunctionCallLpad expands to AUIPC+JALR+LPAD
339 // without emitting R_RISCV_RELAX on the call fixup.
340 MCInst TmpInst;
341 TmpInst.setOpcode(MI.getOpcode());
342 if (!IsIndirect) {
343 MCOperand MCOp;
344 lowerOperand(MO: MI.getOperand(i: 0), MCOp);
345 TmpInst.addOperand(Op: MCOp);
346 } else {
347 TmpInst.addOperand(Op: MCOperand::createReg(Reg: MI.getOperand(i: 0).getReg()));
348 }
349 TmpInst.addOperand(Op: MCOperand::createImm(Val: MI.getOperand(i: 1).getImm()));
350 EmitToStreamer(S&: *OutStreamer, Inst: TmpInst, SubtargetInfo: MCSTI);
351 }
352}
353
354// If the instruction has a nontemporal MachineMemOperand, emit an NTL hint
355// instruction before it. NTL hints are always safe to emit since they use
356// HINT encodings that are guaranteed not to trap
357// (riscv-non-isa/riscv-elf-psabi-doc#474).
358void RISCVAsmPrinter::emitNTLHint(const MachineInstr *MI) {
359 if (!STI->getInstrInfo()->requiresNTLHint(MI: *MI))
360 return;
361
362 assert(!MI->memoperands_empty());
363
364 MachineMemOperand *MMO = *(MI->memoperands_begin());
365
366 assert(MMO->isNonTemporal());
367
368 unsigned NontemporalMode = 0;
369 if (MMO->getFlags() & MONontemporalBit0)
370 NontemporalMode += 0b1;
371 if (MMO->getFlags() & MONontemporalBit1)
372 NontemporalMode += 0b10;
373
374 MCInst Hint;
375 if (STI->hasStdExtZca())
376 Hint.setOpcode(RISCV::C_ADD);
377 else
378 Hint.setOpcode(RISCV::ADD);
379
380 Hint.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
381 Hint.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
382 Hint.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2 + NontemporalMode));
383
384 EmitToStreamer(S&: *OutStreamer, Inst: Hint);
385}
386
387void RISCVAsmPrinter::emitInstruction(const MachineInstr *MI) {
388 RISCV_MC::verifyInstructionPredicates(Opcode: MI->getOpcode(), Features: STI->getFeatureBits());
389
390 emitNTLHint(MI);
391
392 // Do any auto-generated pseudo lowerings.
393 if (MCInst OutInst; lowerPseudoInstExpansion(MI, Inst&: OutInst)) {
394 EmitToStreamer(S&: *OutStreamer, Inst: OutInst);
395 return;
396 }
397
398 switch (MI->getOpcode()) {
399 case RISCV::HWASAN_CHECK_MEMACCESS_SHORTGRANULES:
400 LowerHWASAN_CHECK_MEMACCESS(MI: *MI);
401 return;
402 case RISCV::KCFI_CHECK:
403 LowerKCFI_CHECK(MI: *MI);
404 return;
405 case TargetOpcode::STACKMAP:
406 return LowerSTACKMAP(OutStreamer&: *OutStreamer, SM, MI: *MI);
407 case TargetOpcode::PATCHPOINT:
408 return LowerPATCHPOINT(OutStreamer&: *OutStreamer, SM, MI: *MI);
409 case TargetOpcode::STATEPOINT:
410 return LowerSTATEPOINT(OutStreamer&: *OutStreamer, SM, MI: *MI);
411 case TargetOpcode::PATCHABLE_FUNCTION_ENTER: {
412 const Function &F = MI->getParent()->getParent()->getFunction();
413 if (F.hasFnAttribute(Kind: "patchable-function-entry")) {
414 unsigned Num =
415 F.getFnAttributeAsParsedInteger(Kind: "patchable-function-entry");
416 emitNops(N: Num);
417 return;
418 }
419 LowerPATCHABLE_FUNCTION_ENTER(MI);
420 return;
421 }
422 case TargetOpcode::PATCHABLE_FUNCTION_EXIT:
423 LowerPATCHABLE_FUNCTION_EXIT(MI);
424 return;
425 case TargetOpcode::PATCHABLE_TAIL_CALL:
426 LowerPATCHABLE_TAIL_CALL(MI);
427 return;
428 case RISCV::PseudoCALLLpadAlign:
429 case RISCV::PseudoCALLIndirectLpadAlign:
430 emitLpadAlignedCall(MI: *MI);
431 return;
432 }
433
434 MCInst OutInst;
435 lowerToMCInst(MI, OutMI&: OutInst);
436 EmitToStreamer(S&: *OutStreamer, Inst: OutInst);
437}
438
439bool RISCVAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
440 const char *ExtraCode, raw_ostream &OS) {
441 // First try the generic code, which knows about modifiers like 'c' and 'n'.
442 if (!AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS))
443 return false;
444
445 const MachineOperand &MO = MI->getOperand(i: OpNo);
446 if (ExtraCode && ExtraCode[0]) {
447 if (ExtraCode[1] != 0)
448 return true; // Unknown modifier.
449
450 switch (ExtraCode[0]) {
451 default:
452 return true; // Unknown modifier.
453 case 'z': // Print zero register if zero, regular printing otherwise.
454 if (MO.isImm() && MO.getImm() == 0) {
455 OS << RISCVInstPrinter::getRegisterName(Reg: RISCV::X0);
456 return false;
457 }
458 break;
459 case 'i': // Literal 'i' if operand is not a register.
460 if (!MO.isReg())
461 OS << 'i';
462 return false;
463 case 'N': // Print the register encoding as an integer (0-31)
464 if (!MO.isReg())
465 return true;
466
467 const RISCVRegisterInfo *TRI = STI->getRegisterInfo();
468 OS << TRI->getEncodingValue(Reg: MO.getReg());
469 return false;
470 }
471 }
472
473 switch (MO.getType()) {
474 case MachineOperand::MO_Immediate:
475 OS << MO.getImm();
476 return false;
477 case MachineOperand::MO_Register:
478 OS << RISCVInstPrinter::getRegisterName(Reg: MO.getReg());
479 return false;
480 case MachineOperand::MO_GlobalAddress:
481 PrintSymbolOperand(MO, OS);
482 return false;
483 case MachineOperand::MO_BlockAddress: {
484 MCSymbol *Sym = GetBlockAddressSymbol(BA: MO.getBlockAddress());
485 Sym->print(OS, MAI);
486 return false;
487 }
488 default:
489 break;
490 }
491
492 return true;
493}
494
495bool RISCVAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
496 unsigned OpNo,
497 const char *ExtraCode,
498 raw_ostream &OS) {
499 if (ExtraCode)
500 return AsmPrinter::PrintAsmMemoryOperand(MI, OpNo, ExtraCode, OS);
501
502 const MachineOperand &AddrReg = MI->getOperand(i: OpNo);
503 assert(MI->getNumOperands() > OpNo + 1 && "Expected additional operand");
504 const MachineOperand &Offset = MI->getOperand(i: OpNo + 1);
505 // All memory operands should have a register and an immediate operand (see
506 // RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand).
507 if (!AddrReg.isReg())
508 return true;
509 if (!Offset.isImm() && !Offset.isGlobal() && !Offset.isBlockAddress() &&
510 !Offset.isMCSymbol())
511 return true;
512
513 MCOperand MCO;
514 if (!lowerOperand(MO: Offset, MCOp&: MCO))
515 return true;
516
517 if (Offset.isImm())
518 OS << MCO.getImm();
519 else if (Offset.isGlobal() || Offset.isBlockAddress() || Offset.isMCSymbol())
520 MAI.printExpr(OS, *MCO.getExpr());
521
522 if (Offset.isMCSymbol())
523 MMI->getContext().registerInlineAsmLabel(Sym: Offset.getMCSymbol());
524 if (Offset.isBlockAddress()) {
525 const BlockAddress *BA = Offset.getBlockAddress();
526 MCSymbol *Sym = GetBlockAddressSymbol(BA);
527 MMI->getContext().registerInlineAsmLabel(Sym);
528 }
529
530 OS << "(" << RISCVInstPrinter::getRegisterName(Reg: AddrReg.getReg()) << ")";
531 return false;
532}
533
534bool RISCVAsmPrinter::emitTargetFeaturePush(const MCSubtargetInfo &STI) {
535 RISCVTargetStreamer &RTS = getTargetStreamer();
536 SmallVector<RISCVOptionArchArg> NeedEmitStdOptionArgs;
537 const MCSubtargetInfo &MCSTI = TM.getMCSubtargetInfo();
538 for (const auto &Feature : MCSTI.getAllProcessorFeatures()) {
539 if (STI.hasFeature(Feature: Feature.Value) == MCSTI.hasFeature(Feature: Feature.Value))
540 continue;
541
542 if (!llvm::RISCVISAInfo::isSupportedExtensionFeature(Ext: Feature.key()))
543 continue;
544
545 auto Delta = STI.hasFeature(Feature: Feature.Value) ? RISCVOptionArchArgType::Plus
546 : RISCVOptionArchArgType::Minus;
547 StringRef ExtName = Feature.key();
548 ExtName.consume_front(Prefix: "experimental-");
549 NeedEmitStdOptionArgs.emplace_back(Args&: Delta, Args: ExtName.str());
550 }
551 if (!NeedEmitStdOptionArgs.empty()) {
552 RTS.emitDirectiveOptionPush();
553 RTS.emitDirectiveOptionArch(Args: NeedEmitStdOptionArgs);
554 return true;
555 }
556
557 return false;
558}
559
560void RISCVAsmPrinter::emitTargetFeaturePop(const MCSubtargetInfo &STI,
561 bool DidPush) {
562 if (DidPush)
563 getTargetStreamer().emitDirectiveOptionPop();
564}
565
566bool RISCVAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
567 STI = &MF.getSubtarget<RISCVSubtarget>();
568
569 bool EmittedOptionArch = emitTargetFeaturePush(STI: *STI);
570
571 SetupMachineFunction(MF);
572 emitFunctionBody();
573
574 // Emit the XRay table
575 emitXRayTable();
576
577 emitTargetFeaturePop(STI: *STI, DidPush: EmittedOptionArch);
578 return false;
579}
580
581void RISCVAsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr *MI) {
582 emitSled(MI, Kind: SledKind::FUNCTION_ENTER);
583}
584
585void RISCVAsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr *MI) {
586 emitSled(MI, Kind: SledKind::FUNCTION_EXIT);
587}
588
589void RISCVAsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr *MI) {
590 emitSled(MI, Kind: SledKind::TAIL_CALL);
591}
592
593void RISCVAsmPrinter::emitSled(const MachineInstr *MI, SledKind Kind) {
594 // We want to emit the jump instruction and the nops constituting the sled.
595 // The format is as follows:
596 // .Lxray_sled_N
597 // ALIGN
598 // J .tmpN
599 // 21 or 33 C.NOP instructions
600 // .tmpN
601
602 // The following variable holds the count of the number of NOPs to be patched
603 // in for XRay instrumentation during compilation.
604 // Note that RV64 and RV32 each has a sled of 68 and 44 bytes, respectively.
605 // Assuming we're using JAL to jump to .tmpN, then we only need
606 // (68 - 4)/2 = 32 NOPs for RV64 and (44 - 4)/2 = 20 for RV32. However, there
607 // is a chance that we'll use C.JAL instead, so an additional NOP is needed.
608 const uint8_t NoopsInSledCount = STI->is64Bit() ? 33 : 21;
609
610 OutStreamer->emitCodeAlignment(Alignment: Align(4), STI: *STI);
611 auto CurSled = OutContext.createTempSymbol(Name: "xray_sled_", AlwaysAddSuffix: true);
612 OutStreamer->emitLabel(Symbol: CurSled);
613 auto Target = OutContext.createTempSymbol();
614
615 const MCExpr *TargetExpr = MCSymbolRefExpr::create(Symbol: Target, Ctx&: OutContext);
616
617 // Emit "J bytes" instruction, which jumps over the nop sled to the actual
618 // start of function.
619 EmitToStreamer(
620 S&: *OutStreamer,
621 Inst: MCInstBuilder(RISCV::JAL).addReg(Reg: RISCV::X0).addExpr(Val: TargetExpr));
622
623 // Emit NOP instructions
624 for (int8_t I = 0; I < NoopsInSledCount; ++I)
625 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(RISCV::ADDI)
626 .addReg(Reg: RISCV::X0)
627 .addReg(Reg: RISCV::X0)
628 .addImm(Val: 0));
629
630 OutStreamer->emitLabel(Symbol: Target);
631 recordSled(Sled: CurSled, MI: *MI, Kind, Version: 2);
632}
633
634void RISCVAsmPrinter::emitStartOfAsmFile(Module &M) {
635 assert(OutStreamer->getTargetStreamer() &&
636 "target streamer is uninitialized");
637 RISCVTargetStreamer &RTS = getTargetStreamer();
638 if (const MDString *ModuleTargetABI =
639 dyn_cast_or_null<MDString>(Val: M.getModuleFlag(Key: "target-abi")))
640 RTS.setTargetABI(RISCVABI::getTargetABI(ABIName: ModuleTargetABI->getString()));
641
642 MCSubtargetInfo SubtargetInfo = TM.getMCSubtargetInfo();
643
644 // Use module flag to update feature bits.
645 if (auto *MD = dyn_cast_or_null<MDNode>(Val: M.getModuleFlag(Key: "riscv-isa"))) {
646 for (auto &ISA : MD->operands()) {
647 if (auto *ISAString = dyn_cast_or_null<MDString>(Val: ISA)) {
648 auto ParseResult = llvm::RISCVISAInfo::parseArchString(
649 Arch: ISAString->getString(), /*EnableExperimentalExtension=*/true,
650 /*ExperimentalExtensionVersionCheck=*/true);
651 if (!errorToBool(Err: ParseResult.takeError())) {
652 auto &ISAInfo = *ParseResult;
653 for (const auto &Feature : SubtargetInfo.getAllProcessorFeatures()) {
654 if (ISAInfo->hasExtension(Ext: Feature.key()) &&
655 !SubtargetInfo.hasFeature(Feature: Feature.Value))
656 SubtargetInfo.ToggleFeature(FS: Feature.key());
657 }
658 }
659 }
660 }
661
662 RTS.setFlagsFromFeatures(SubtargetInfo);
663 }
664
665 if (TM.getTargetTriple().isOSBinFormatELF())
666 emitAttributes(SubtargetInfo);
667}
668
669void RISCVAsmPrinter::emitEndOfAsmFile(Module &M) {
670 RISCVTargetStreamer &RTS = getTargetStreamer();
671
672 if (TM.getTargetTriple().isOSBinFormatELF()) {
673 RTS.finishAttributeSection();
674 emitNoteGnuProperty(M);
675 }
676 EmitHwasanMemaccessSymbols(M);
677}
678
679void RISCVAsmPrinter::emitAttributes(const MCSubtargetInfo &SubtargetInfo) {
680 RISCVTargetStreamer &RTS = getTargetStreamer();
681 // Use MCSubtargetInfo from TargetMachine. Individual functions may have
682 // attributes that differ from other functions in the module and we have no
683 // way to know which function is correct.
684 RTS.emitTargetAttributes(STI: SubtargetInfo, /*EmitStackAlign*/ true);
685}
686
687void RISCVAsmPrinter::emitFunctionEntryLabel() {
688 const auto *RMFI = MF->getInfo<RISCVMachineFunctionInfo>();
689 if (RMFI->isVectorCall()) {
690 RISCVTargetStreamer &RTS = getTargetStreamer();
691 RTS.emitDirectiveVariantCC(Symbol&: *CurrentFnSym);
692 }
693 return AsmPrinter::emitFunctionEntryLabel();
694}
695
696// Force static initialization.
697extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
698LLVMInitializeRISCVAsmPrinter() {
699 RegisterAsmPrinter<RISCVAsmPrinter> X(getTheRISCV32Target());
700 RegisterAsmPrinter<RISCVAsmPrinter> Y(getTheRISCV64Target());
701 RegisterAsmPrinter<RISCVAsmPrinter> A(getTheRISCV32beTarget());
702 RegisterAsmPrinter<RISCVAsmPrinter> B(getTheRISCV64beTarget());
703}
704
705void RISCVAsmPrinter::LowerHWASAN_CHECK_MEMACCESS(const MachineInstr &MI) {
706 Register Reg = MI.getOperand(i: 0).getReg();
707 uint32_t AccessInfo = MI.getOperand(i: 1).getImm();
708 MCSymbol *&Sym =
709 HwasanMemaccessSymbols[HwasanMemaccessTuple(Reg, AccessInfo)];
710 if (!Sym) {
711 // FIXME: Make this work on non-ELF.
712 if (!TM.getTargetTriple().isOSBinFormatELF())
713 report_fatal_error(reason: "llvm.hwasan.check.memaccess only supported on ELF");
714
715 std::string SymName = "__hwasan_check_x" + utostr(X: Reg - RISCV::X0) + "_" +
716 utostr(X: AccessInfo) + "_short";
717 Sym = OutContext.getOrCreateSymbol(Name: SymName);
718 }
719 auto Res = MCSymbolRefExpr::create(Symbol: Sym, Ctx&: OutContext);
720 auto Expr = MCSpecifierExpr::create(Expr: Res, S: RISCV::S_CALL_PLT, Ctx&: OutContext);
721
722 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(RISCV::PseudoCALL).addExpr(Val: Expr));
723}
724
725void RISCVAsmPrinter::LowerKCFI_CHECK(const MachineInstr &MI) {
726 Register AddrReg = MI.getOperand(i: 0).getReg();
727 assert(std::next(MI.getIterator())->isCall() &&
728 "KCFI_CHECK not followed by a call instruction");
729 assert(std::next(MI.getIterator())->getOperand(0).getReg() == AddrReg &&
730 "KCFI_CHECK call target doesn't match call operand");
731
732 // Temporary registers for comparing the hashes. If a register is used
733 // for the call target, or reserved by the user, we can clobber another
734 // temporary register as the check is immediately followed by the
735 // call. The check defaults to X6/X7, but can fall back to X28-X31 if
736 // needed.
737 unsigned ScratchRegs[] = {RISCV::X6, RISCV::X7};
738 unsigned NextReg = RISCV::X28;
739 auto isRegAvailable = [&](unsigned Reg) {
740 return Reg != AddrReg && !STI->isRegisterReservedByUser(i: Reg);
741 };
742 for (auto &Reg : ScratchRegs) {
743 if (isRegAvailable(Reg))
744 continue;
745 while (!isRegAvailable(NextReg))
746 ++NextReg;
747 Reg = NextReg++;
748 if (Reg > RISCV::X31)
749 report_fatal_error(reason: "Unable to find scratch registers for KCFI_CHECK");
750 }
751
752 if (AddrReg == RISCV::X0) {
753 // Checking X0 makes no sense. Instead of emitting a load, zero
754 // ScratchRegs[0].
755 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(RISCV::ADDI)
756 .addReg(Reg: ScratchRegs[0])
757 .addReg(Reg: RISCV::X0)
758 .addImm(Val: 0));
759 } else {
760 // Adjust the offset for patchable-function-prefix. This assumes that
761 // patchable-function-prefix is the same for all functions.
762 int NopSize = STI->hasStdExtZca() ? 2 : 4;
763 int64_t PrefixNops =
764 MI.getMF()->getFunction().getFnAttributeAsParsedInteger(
765 Kind: "patchable-function-prefix");
766
767 // Load the target function type hash.
768 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(RISCV::LW)
769 .addReg(Reg: ScratchRegs[0])
770 .addReg(Reg: AddrReg)
771 .addImm(Val: -(PrefixNops * NopSize + 4)));
772 }
773
774 // Load the expected 32-bit type hash.
775 const int64_t Type = MI.getOperand(i: 1).getImm();
776 const int64_t Hi20 = ((Type + 0x800) >> 12) & 0xFFFFF;
777 const int64_t Lo12 = SignExtend64<12>(x: Type);
778 if (Hi20) {
779 EmitToStreamer(
780 S&: *OutStreamer,
781 Inst: MCInstBuilder(RISCV::LUI).addReg(Reg: ScratchRegs[1]).addImm(Val: Hi20));
782 }
783 if (Lo12 || Hi20 == 0) {
784 EmitToStreamer(S&: *OutStreamer,
785 Inst: MCInstBuilder((STI->hasFeature(Feature: RISCV::Feature64Bit) && Hi20)
786 ? RISCV::ADDIW
787 : RISCV::ADDI)
788 .addReg(Reg: ScratchRegs[1])
789 .addReg(Reg: ScratchRegs[1])
790 .addImm(Val: Lo12));
791 }
792
793 // Compare the hashes and trap if there's a mismatch.
794 MCSymbol *Pass = OutContext.createTempSymbol();
795 EmitToStreamer(S&: *OutStreamer,
796 Inst: MCInstBuilder(RISCV::BEQ)
797 .addReg(Reg: ScratchRegs[0])
798 .addReg(Reg: ScratchRegs[1])
799 .addExpr(Val: MCSymbolRefExpr::create(Symbol: Pass, Ctx&: OutContext)));
800
801 MCSymbol *Trap = OutContext.createTempSymbol();
802 OutStreamer->emitLabel(Symbol: Trap);
803 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(RISCV::EBREAK));
804 emitKCFITrapEntry(MF: *MI.getMF(), Symbol: Trap);
805 OutStreamer->emitLabel(Symbol: Pass);
806}
807
808void RISCVAsmPrinter::EmitHwasanMemaccessSymbols(Module &M) {
809 if (HwasanMemaccessSymbols.empty())
810 return;
811
812 assert(TM.getTargetTriple().isOSBinFormatELF());
813 // Use MCSubtargetInfo from TargetMachine. Individual functions may have
814 // attributes that differ from other functions in the module and we have no
815 // way to know which function is correct.
816 const MCSubtargetInfo &MCSTI = TM.getMCSubtargetInfo();
817
818 MCSymbol *HwasanTagMismatchV2Sym =
819 OutContext.getOrCreateSymbol(Name: "__hwasan_tag_mismatch_v2");
820 // Annotate symbol as one having incompatible calling convention, so
821 // run-time linkers can instead eagerly bind this function.
822 RISCVTargetStreamer &RTS = getTargetStreamer();
823 RTS.emitDirectiveVariantCC(Symbol&: *HwasanTagMismatchV2Sym);
824
825 const MCSymbolRefExpr *HwasanTagMismatchV2Ref =
826 MCSymbolRefExpr::create(Symbol: HwasanTagMismatchV2Sym, Ctx&: OutContext);
827 auto Expr = MCSpecifierExpr::create(Expr: HwasanTagMismatchV2Ref, S: RISCV::S_CALL_PLT,
828 Ctx&: OutContext);
829
830 for (auto &P : HwasanMemaccessSymbols) {
831 unsigned Reg = std::get<0>(t: P.first);
832 uint32_t AccessInfo = std::get<1>(t: P.first);
833 MCSymbol *Sym = P.second;
834
835 unsigned Size =
836 1 << ((AccessInfo >> HWASanAccessInfo::AccessSizeShift) & 0xf);
837 OutStreamer->switchSection(Section: OutContext.getELFSection(
838 Section: ".text.hot", Type: ELF::SHT_PROGBITS,
839 Flags: ELF::SHF_EXECINSTR | ELF::SHF_ALLOC | ELF::SHF_GROUP, EntrySize: 0, Group: Sym->getName(),
840 /*IsComdat=*/true));
841
842 OutStreamer->emitSymbolAttribute(Symbol: Sym, Attribute: MCSA_ELF_TypeFunction);
843 OutStreamer->emitSymbolAttribute(Symbol: Sym, Attribute: MCSA_Weak);
844 OutStreamer->emitSymbolAttribute(Symbol: Sym, Attribute: MCSA_Hidden);
845 OutStreamer->emitLabel(Symbol: Sym);
846
847 // Extract shadow offset from ptr
848 EmitToStreamer(
849 S&: *OutStreamer,
850 Inst: MCInstBuilder(RISCV::SLLI).addReg(Reg: RISCV::X6).addReg(Reg).addImm(Val: 8),
851 SubtargetInfo: MCSTI);
852 EmitToStreamer(S&: *OutStreamer,
853 Inst: MCInstBuilder(RISCV::SRLI)
854 .addReg(Reg: RISCV::X6)
855 .addReg(Reg: RISCV::X6)
856 .addImm(Val: 12),
857 SubtargetInfo: MCSTI);
858 // load shadow tag in X6, X5 contains shadow base
859 EmitToStreamer(S&: *OutStreamer,
860 Inst: MCInstBuilder(RISCV::ADD)
861 .addReg(Reg: RISCV::X6)
862 .addReg(Reg: RISCV::X5)
863 .addReg(Reg: RISCV::X6),
864 SubtargetInfo: MCSTI);
865 EmitToStreamer(
866 S&: *OutStreamer,
867 Inst: MCInstBuilder(RISCV::LBU).addReg(Reg: RISCV::X6).addReg(Reg: RISCV::X6).addImm(Val: 0),
868 SubtargetInfo: MCSTI);
869 // Extract tag from pointer and compare it with loaded tag from shadow
870 EmitToStreamer(
871 S&: *OutStreamer,
872 Inst: MCInstBuilder(RISCV::SRLI).addReg(Reg: RISCV::X7).addReg(Reg).addImm(Val: 56),
873 SubtargetInfo: MCSTI);
874 MCSymbol *HandleMismatchOrPartialSym = OutContext.createTempSymbol();
875 // X7 contains tag from the pointer, while X6 contains tag from memory
876 EmitToStreamer(S&: *OutStreamer,
877 Inst: MCInstBuilder(RISCV::BNE)
878 .addReg(Reg: RISCV::X7)
879 .addReg(Reg: RISCV::X6)
880 .addExpr(Val: MCSymbolRefExpr::create(
881 Symbol: HandleMismatchOrPartialSym, Ctx&: OutContext)),
882 SubtargetInfo: MCSTI);
883 MCSymbol *ReturnSym = OutContext.createTempSymbol();
884 OutStreamer->emitLabel(Symbol: ReturnSym);
885 EmitToStreamer(S&: *OutStreamer,
886 Inst: MCInstBuilder(RISCV::JALR)
887 .addReg(Reg: RISCV::X0)
888 .addReg(Reg: RISCV::X1)
889 .addImm(Val: 0),
890 SubtargetInfo: MCSTI);
891 OutStreamer->emitLabel(Symbol: HandleMismatchOrPartialSym);
892
893 EmitToStreamer(S&: *OutStreamer,
894 Inst: MCInstBuilder(RISCV::ADDI)
895 .addReg(Reg: RISCV::X28)
896 .addReg(Reg: RISCV::X0)
897 .addImm(Val: 16),
898 SubtargetInfo: MCSTI);
899 MCSymbol *HandleMismatchSym = OutContext.createTempSymbol();
900 EmitToStreamer(
901 S&: *OutStreamer,
902 Inst: MCInstBuilder(RISCV::BGEU)
903 .addReg(Reg: RISCV::X6)
904 .addReg(Reg: RISCV::X28)
905 .addExpr(Val: MCSymbolRefExpr::create(Symbol: HandleMismatchSym, Ctx&: OutContext)),
906 SubtargetInfo: MCSTI);
907
908 EmitToStreamer(
909 S&: *OutStreamer,
910 Inst: MCInstBuilder(RISCV::ANDI).addReg(Reg: RISCV::X28).addReg(Reg).addImm(Val: 0xF),
911 SubtargetInfo: MCSTI);
912
913 if (Size != 1)
914 EmitToStreamer(S&: *OutStreamer,
915 Inst: MCInstBuilder(RISCV::ADDI)
916 .addReg(Reg: RISCV::X28)
917 .addReg(Reg: RISCV::X28)
918 .addImm(Val: Size - 1),
919 SubtargetInfo: MCSTI);
920 EmitToStreamer(
921 S&: *OutStreamer,
922 Inst: MCInstBuilder(RISCV::BGE)
923 .addReg(Reg: RISCV::X28)
924 .addReg(Reg: RISCV::X6)
925 .addExpr(Val: MCSymbolRefExpr::create(Symbol: HandleMismatchSym, Ctx&: OutContext)),
926 SubtargetInfo: MCSTI);
927
928 EmitToStreamer(
929 S&: *OutStreamer,
930 Inst: MCInstBuilder(RISCV::ORI).addReg(Reg: RISCV::X6).addReg(Reg).addImm(Val: 0xF),
931 SubtargetInfo: MCSTI);
932 EmitToStreamer(
933 S&: *OutStreamer,
934 Inst: MCInstBuilder(RISCV::LBU).addReg(Reg: RISCV::X6).addReg(Reg: RISCV::X6).addImm(Val: 0),
935 SubtargetInfo: MCSTI);
936 EmitToStreamer(S&: *OutStreamer,
937 Inst: MCInstBuilder(RISCV::BEQ)
938 .addReg(Reg: RISCV::X6)
939 .addReg(Reg: RISCV::X7)
940 .addExpr(Val: MCSymbolRefExpr::create(Symbol: ReturnSym, Ctx&: OutContext)),
941 SubtargetInfo: MCSTI);
942
943 OutStreamer->emitLabel(Symbol: HandleMismatchSym);
944
945 // | Previous stack frames... |
946 // +=================================+ <-- [SP + 256]
947 // | ... |
948 // | |
949 // | Stack frame space for x12 - x31.|
950 // | |
951 // | ... |
952 // +---------------------------------+ <-- [SP + 96]
953 // | Saved x11(arg1), as |
954 // | __hwasan_check_* clobbers it. |
955 // +---------------------------------+ <-- [SP + 88]
956 // | Saved x10(arg0), as |
957 // | __hwasan_check_* clobbers it. |
958 // +---------------------------------+ <-- [SP + 80]
959 // | |
960 // | Stack frame space for x9. |
961 // +---------------------------------+ <-- [SP + 72]
962 // | |
963 // | Saved x8(fp), as |
964 // | __hwasan_check_* clobbers it. |
965 // +---------------------------------+ <-- [SP + 64]
966 // | ... |
967 // | |
968 // | Stack frame space for x2 - x7. |
969 // | |
970 // | ... |
971 // +---------------------------------+ <-- [SP + 16]
972 // | Return address (x1) for caller |
973 // | of __hwasan_check_*. |
974 // +---------------------------------+ <-- [SP + 8]
975 // | Reserved place for x0, possibly |
976 // | junk, since we don't save it. |
977 // +---------------------------------+ <-- [x2 / SP]
978
979 // Adjust sp
980 EmitToStreamer(S&: *OutStreamer,
981 Inst: MCInstBuilder(RISCV::ADDI)
982 .addReg(Reg: RISCV::X2)
983 .addReg(Reg: RISCV::X2)
984 .addImm(Val: -256),
985 SubtargetInfo: MCSTI);
986
987 // store x10(arg0) by new sp
988 EmitToStreamer(S&: *OutStreamer,
989 Inst: MCInstBuilder(RISCV::SD)
990 .addReg(Reg: RISCV::X10)
991 .addReg(Reg: RISCV::X2)
992 .addImm(Val: 8 * 10),
993 SubtargetInfo: MCSTI);
994 // store x11(arg1) by new sp
995 EmitToStreamer(S&: *OutStreamer,
996 Inst: MCInstBuilder(RISCV::SD)
997 .addReg(Reg: RISCV::X11)
998 .addReg(Reg: RISCV::X2)
999 .addImm(Val: 8 * 11),
1000 SubtargetInfo: MCSTI);
1001
1002 // store x8(fp) by new sp
1003 EmitToStreamer(
1004 S&: *OutStreamer,
1005 Inst: MCInstBuilder(RISCV::SD).addReg(Reg: RISCV::X8).addReg(Reg: RISCV::X2).addImm(Val: 8 *
1006 8),
1007 SubtargetInfo: MCSTI);
1008 // store x1(ra) by new sp
1009 EmitToStreamer(
1010 S&: *OutStreamer,
1011 Inst: MCInstBuilder(RISCV::SD).addReg(Reg: RISCV::X1).addReg(Reg: RISCV::X2).addImm(Val: 1 *
1012 8),
1013 SubtargetInfo: MCSTI);
1014 if (Reg != RISCV::X10)
1015 EmitToStreamer(
1016 S&: *OutStreamer,
1017 Inst: MCInstBuilder(RISCV::ADDI).addReg(Reg: RISCV::X10).addReg(Reg).addImm(Val: 0),
1018 SubtargetInfo: MCSTI);
1019 EmitToStreamer(S&: *OutStreamer,
1020 Inst: MCInstBuilder(RISCV::ADDI)
1021 .addReg(Reg: RISCV::X11)
1022 .addReg(Reg: RISCV::X0)
1023 .addImm(Val: AccessInfo & HWASanAccessInfo::RuntimeMask),
1024 SubtargetInfo: MCSTI);
1025
1026 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(RISCV::PseudoCALL).addExpr(Val: Expr),
1027 SubtargetInfo: MCSTI);
1028 }
1029}
1030
1031void RISCVAsmPrinter::emitNoteGnuProperty(const Module &M) {
1032 assert(TM.getTargetTriple().isOSBinFormatELF() && "invalid binary format");
1033 uint32_t GnuProps = 0;
1034 if (const Metadata *const Flag = M.getModuleFlag(Key: "cf-protection-return");
1035 Flag && !mdconst::extract<ConstantInt>(MD: Flag)->isZero())
1036 GnuProps |= ELF::GNU_PROPERTY_RISCV_FEATURE_1_CFI_SS;
1037
1038 if (const Metadata *const Flag = M.getModuleFlag(Key: "cf-protection-branch");
1039 Flag && !mdconst::extract<ConstantInt>(MD: Flag)->isZero()) {
1040 using namespace llvm::RISCVISAUtils;
1041 const Metadata *const CFBranchLabelSchemeFlag =
1042 M.getModuleFlag(Key: "cf-branch-label-scheme");
1043 assert(CFBranchLabelSchemeFlag &&
1044 "cf-protection=branch should come with cf-branch-label-scheme=... "
1045 "on RISC-V targets");
1046 const StringRef CFBranchLabelScheme =
1047 cast<MDString>(Val: CFBranchLabelSchemeFlag)->getString();
1048 switch (llvm::RISCVCFI::getZicfilpLabelScheme(CFBranchLabelScheme)) {
1049 case llvm::RISCVCFI::ZicfilpLabelSchemeKind::Invalid:
1050 reportFatalInternalError(reason: "invalid RISC-V Zicfilp label scheme");
1051 case llvm::RISCVCFI::ZicfilpLabelSchemeKind::Unlabeled:
1052 GnuProps |= ELF::GNU_PROPERTY_RISCV_FEATURE_1_CFI_LP_UNLABELED;
1053 break;
1054 case llvm::RISCVCFI::ZicfilpLabelSchemeKind::FuncSig:
1055 // TODO: Emit the func-sig bit after the feature is implemented
1056 reportFatalUsageError(reason: "the complete func-sig label scheme feature is not "
1057 "implemented yet");
1058 break;
1059 }
1060 }
1061
1062 if (!GnuProps)
1063 return;
1064
1065 auto &RTS = static_cast<RISCVTargetELFStreamer &>(getTargetStreamer());
1066 RTS.emitNoteGnuPropertySection(Feature1And: GnuProps);
1067}
1068
1069static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym,
1070 const AsmPrinter &AP) {
1071 MCContext &Ctx = AP.OutContext;
1072 RISCV::Specifier Kind;
1073
1074 switch (MO.getTargetFlags()) {
1075 default:
1076 llvm_unreachable("Unknown target flag on GV operand");
1077 case RISCVII::MO_None:
1078 Kind = RISCV::S_None;
1079 break;
1080 case RISCVII::MO_CALL:
1081 Kind = RISCV::S_CALL_PLT;
1082 break;
1083 case RISCVII::MO_LO:
1084 Kind = RISCV::S_LO;
1085 break;
1086 case RISCVII::MO_HI:
1087 Kind = ELF::R_RISCV_HI20;
1088 break;
1089 case RISCVII::MO_PCREL_LO:
1090 Kind = RISCV::S_PCREL_LO;
1091 break;
1092 case RISCVII::MO_PCREL_HI:
1093 Kind = RISCV::S_PCREL_HI;
1094 break;
1095 case RISCVII::MO_GOT_HI:
1096 Kind = RISCV::S_GOT_HI;
1097 break;
1098 case RISCVII::MO_TPREL_LO:
1099 Kind = RISCV::S_TPREL_LO;
1100 break;
1101 case RISCVII::MO_TPREL_HI:
1102 Kind = ELF::R_RISCV_TPREL_HI20;
1103 break;
1104 case RISCVII::MO_TPREL_ADD:
1105 Kind = ELF::R_RISCV_TPREL_ADD;
1106 break;
1107 case RISCVII::MO_TLS_GOT_HI:
1108 Kind = ELF::R_RISCV_TLS_GOT_HI20;
1109 break;
1110 case RISCVII::MO_TLS_GD_HI:
1111 Kind = ELF::R_RISCV_TLS_GD_HI20;
1112 break;
1113 case RISCVII::MO_TLSDESC_HI:
1114 Kind = ELF::R_RISCV_TLSDESC_HI20;
1115 break;
1116 case RISCVII::MO_TLSDESC_LOAD_LO:
1117 Kind = ELF::R_RISCV_TLSDESC_LOAD_LO12;
1118 break;
1119 case RISCVII::MO_TLSDESC_ADD_LO:
1120 Kind = ELF::R_RISCV_TLSDESC_ADD_LO12;
1121 break;
1122 case RISCVII::MO_TLSDESC_CALL:
1123 Kind = ELF::R_RISCV_TLSDESC_CALL;
1124 break;
1125 case RISCVII::MO_QC_ACCESS:
1126 Kind = RISCV::S_QC_ACCESS;
1127 break;
1128 }
1129
1130 const MCExpr *ME = MCSymbolRefExpr::create(Symbol: Sym, Ctx);
1131
1132 if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
1133 ME = MCBinaryExpr::createAdd(
1134 LHS: ME, RHS: MCConstantExpr::create(Value: MO.getOffset(), Ctx), Ctx);
1135
1136 if (Kind != RISCV::S_None)
1137 ME = MCSpecifierExpr::create(Expr: ME, S: Kind, Ctx);
1138 return MCOperand::createExpr(Val: ME);
1139}
1140
1141bool RISCVAsmPrinter::lowerOperand(const MachineOperand &MO,
1142 MCOperand &MCOp) const {
1143 switch (MO.getType()) {
1144 default:
1145 report_fatal_error(reason: "lowerOperand: unknown operand type");
1146 case MachineOperand::MO_Register:
1147 // Ignore all implicit register operands.
1148 if (MO.isImplicit())
1149 return false;
1150 MCOp = MCOperand::createReg(Reg: MO.getReg());
1151 break;
1152 case MachineOperand::MO_RegisterMask:
1153 // Regmasks are like implicit defs.
1154 return false;
1155 case MachineOperand::MO_Immediate:
1156 MCOp = MCOperand::createImm(Val: MO.getImm());
1157 break;
1158 case MachineOperand::MO_MachineBasicBlock:
1159 MCOp = lowerSymbolOperand(MO, Sym: MO.getMBB()->getSymbol(), AP: *this);
1160 break;
1161 case MachineOperand::MO_GlobalAddress:
1162 MCOp = lowerSymbolOperand(MO, Sym: getSymbolPreferLocal(GV: *MO.getGlobal()), AP: *this);
1163 break;
1164 case MachineOperand::MO_BlockAddress:
1165 MCOp = lowerSymbolOperand(MO, Sym: GetBlockAddressSymbol(BA: MO.getBlockAddress()),
1166 AP: *this);
1167 break;
1168 case MachineOperand::MO_ExternalSymbol:
1169 MCOp = lowerSymbolOperand(MO, Sym: GetExternalSymbolSymbol(Sym: MO.getSymbolName()),
1170 AP: *this);
1171 break;
1172 case MachineOperand::MO_ConstantPoolIndex:
1173 MCOp = lowerSymbolOperand(MO, Sym: GetCPISymbol(CPID: MO.getIndex()), AP: *this);
1174 break;
1175 case MachineOperand::MO_JumpTableIndex:
1176 MCOp = lowerSymbolOperand(MO, Sym: GetJTISymbol(JTID: MO.getIndex()), AP: *this);
1177 break;
1178 case MachineOperand::MO_MCSymbol:
1179 MCOp = lowerSymbolOperand(MO, Sym: MO.getMCSymbol(), AP: *this);
1180 break;
1181 }
1182 return true;
1183}
1184
1185static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI,
1186 MCInst &OutMI,
1187 const RISCVSubtarget *STI) {
1188 const RISCVVPseudosTable::PseudoInfo *RVV =
1189 RISCVVPseudosTable::getPseudoInfo(Pseudo: MI->getOpcode());
1190 if (!RVV)
1191 return false;
1192
1193 OutMI.setOpcode(RVV->BaseInstr);
1194
1195 const TargetInstrInfo *TII = STI->getInstrInfo();
1196 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
1197 assert(TRI && "TargetRegisterInfo expected");
1198
1199 const MCInstrDesc &MCID = MI->getDesc();
1200 uint64_t TSFlags = MCID.TSFlags;
1201 unsigned NumOps = MI->getNumExplicitOperands();
1202
1203 // Skip policy, SEW, VL, VXRM/FRM operands which are the last operands if
1204 // present.
1205 if (RISCVII::hasVecPolicyOp(TSFlags))
1206 --NumOps;
1207 if (RISCVII::hasSEWOp(TSFlags))
1208 --NumOps;
1209 if (RISCVII::hasVLOp(TSFlags))
1210 --NumOps;
1211 if (RISCVII::hasRoundModeOp(TSFlags))
1212 --NumOps;
1213 if (RISCVII::hasTWidenOp(TSFlags))
1214 --NumOps;
1215 if (RISCVII::hasTMOp(TSFlags))
1216 --NumOps;
1217 if (RISCVII::hasTKOp(TSFlags))
1218 --NumOps;
1219
1220 bool hasVLOutput = RISCVInstrInfo::isFaultOnlyFirstLoad(MI: *MI);
1221 for (unsigned OpNo = 0; OpNo != NumOps; ++OpNo) {
1222 const MachineOperand &MO = MI->getOperand(i: OpNo);
1223 // Skip vl output. It should be the second output.
1224 if (hasVLOutput && OpNo == 1)
1225 continue;
1226
1227 // Skip passthru op. It should be the first operand after the defs.
1228 if (OpNo == MI->getNumExplicitDefs() && MO.isReg() && MO.isTied()) {
1229 assert(MCID.getOperandConstraint(OpNo, MCOI::TIED_TO) == 0 &&
1230 "Expected tied to first def.");
1231 const MCInstrDesc &OutMCID = TII->get(Opcode: OutMI.getOpcode());
1232 // Skip if the next operand in OutMI is not supposed to be tied. Unless it
1233 // is a _TIED instruction.
1234 if (OutMCID.getOperandConstraint(OpNum: OutMI.getNumOperands(), Constraint: MCOI::TIED_TO) <
1235 0 &&
1236 !RISCVII::isTiedPseudo(TSFlags))
1237 continue;
1238 }
1239
1240 MCOperand MCOp;
1241 switch (MO.getType()) {
1242 default:
1243 llvm_unreachable("Unknown operand type");
1244 case MachineOperand::MO_Register: {
1245 Register Reg = MO.getReg();
1246
1247 if (RISCV::VRM2RegClass.contains(Reg) ||
1248 RISCV::VRM4RegClass.contains(Reg) ||
1249 RISCV::VRM8RegClass.contains(Reg)) {
1250 Reg = TRI->getSubReg(Reg, Idx: RISCV::sub_vrm1_0);
1251 assert(Reg && "Subregister does not exist");
1252 } else if (RISCV::FPR16RegClass.contains(Reg)) {
1253 Reg =
1254 TRI->getMatchingSuperReg(Reg, SubIdx: RISCV::sub_16, RC: &RISCV::FPR32RegClass);
1255 assert(Reg && "Subregister does not exist");
1256 } else if (RISCV::FPR64RegClass.contains(Reg)) {
1257 Reg = TRI->getSubReg(Reg, Idx: RISCV::sub_32);
1258 assert(Reg && "Superregister does not exist");
1259 } else if (RISCV::VRN2M1RegClass.contains(Reg) ||
1260 RISCV::VRN2M2RegClass.contains(Reg) ||
1261 RISCV::VRN2M4RegClass.contains(Reg) ||
1262 RISCV::VRN3M1RegClass.contains(Reg) ||
1263 RISCV::VRN3M2RegClass.contains(Reg) ||
1264 RISCV::VRN4M1RegClass.contains(Reg) ||
1265 RISCV::VRN4M2RegClass.contains(Reg) ||
1266 RISCV::VRN5M1RegClass.contains(Reg) ||
1267 RISCV::VRN6M1RegClass.contains(Reg) ||
1268 RISCV::VRN7M1RegClass.contains(Reg) ||
1269 RISCV::VRN8M1RegClass.contains(Reg)) {
1270 Reg = TRI->getSubReg(Reg, Idx: RISCV::sub_vrm1_0);
1271 assert(Reg && "Subregister does not exist");
1272 }
1273
1274 MCOp = MCOperand::createReg(Reg);
1275 break;
1276 }
1277 case MachineOperand::MO_Immediate:
1278 MCOp = MCOperand::createImm(Val: MO.getImm());
1279 break;
1280 }
1281 OutMI.addOperand(Op: MCOp);
1282 }
1283
1284 // Unmasked pseudo instructions need to append dummy mask operand to
1285 // V instructions. All V instructions are modeled as the masked version.
1286 const MCInstrDesc &OutMCID = TII->get(Opcode: OutMI.getOpcode());
1287 if (OutMI.getNumOperands() < OutMCID.getNumOperands()) {
1288 assert(OutMCID.operands()[OutMI.getNumOperands()].OperandType ==
1289 RISCVOp::OPERAND_VMASK &&
1290 "Expected only mask operand to be missing");
1291 OutMI.addOperand(Op: MCOperand::createReg(Reg: RISCV::NoRegister));
1292 }
1293
1294 assert(OutMI.getNumOperands() == OutMCID.getNumOperands());
1295 return true;
1296}
1297
1298void RISCVAsmPrinter::lowerToMCInst(const MachineInstr *MI, MCInst &OutMI) {
1299 if (lowerRISCVVMachineInstrToMCInst(MI, OutMI, STI))
1300 return;
1301
1302 OutMI.setOpcode(MI->getOpcode());
1303
1304 for (const MachineOperand &MO : MI->operands()) {
1305 MCOperand MCOp;
1306 if (lowerOperand(MO, MCOp))
1307 OutMI.addOperand(Op: MCOp);
1308 }
1309}
1310
1311void RISCVAsmPrinter::emitMachineConstantPoolValue(
1312 MachineConstantPoolValue *MCPV) {
1313 auto *RCPV = static_cast<RISCVConstantPoolValue *>(MCPV);
1314 MCSymbol *MCSym;
1315
1316 if (RCPV->isGlobalValue()) {
1317 auto *GV = RCPV->getGlobalValue();
1318 MCSym = getSymbol(GV);
1319 } else {
1320 assert(RCPV->isExtSymbol() && "unrecognized constant pool type");
1321 auto Sym = RCPV->getSymbol();
1322 MCSym = GetExternalSymbolSymbol(Sym);
1323 }
1324
1325 const MCExpr *Expr = MCSymbolRefExpr::create(Symbol: MCSym, Ctx&: OutContext);
1326 uint64_t Size = getDataLayout().getTypeAllocSize(Ty: RCPV->getType());
1327 OutStreamer->emitValue(Value: Expr, Size);
1328}
1329
1330MaybeAlign
1331RISCVAsmPrinter::getRequiredGlobalAlignmentGranule(const GlobalVariable &GV) {
1332 const MCSubtargetInfo &MCSTI = TM.getMCSubtargetInfo();
1333 if (!GV.getValueType()->isSized())
1334 return std::nullopt;
1335
1336 uint64_t Size = GV.getGlobalSize(DL: getDataLayout());
1337 if (MCSTI.hasFeature(Feature: RISCV::FeatureVendorXCheriot))
1338 return CHERIoTCapabilityFormat::getRequiredAlignment(Length: Size);
1339
1340 if (MCSTI.hasFeature(Feature: RISCV::FeatureStdExtY)) {
1341 if (MCSTI.hasFeature(Feature: RISCV::Feature64Bit))
1342 return RV64YCapabilityFormat::getRequiredAlignment(Length: Size);
1343 else
1344 return RV32YCapabilityFormat::getRequiredAlignment(Length: Size);
1345 }
1346
1347 return std::nullopt;
1348}
1349
1350char RISCVAsmPrinter::ID = 0;
1351
1352INITIALIZE_PASS(RISCVAsmPrinter, "riscv-asm-printer", "RISC-V Assembly Printer",
1353 false, false)
1354
1355PreservedAnalyses RISCVAsmPrinterBeginPass::run(Module &M,
1356 ModuleAnalysisManager &MAM) {
1357 RISCVAsmPrinter &AsmPrinter = static_cast<RISCVAsmPrinter &>(
1358 MAM.getResult<AsmPrinterAnalysis>(IR&: M).getPrinter());
1359 setupModuleAsmPrinter(M, MAM, AsmPrinter);
1360 AsmPrinter.doInitialization(M);
1361 return PreservedAnalyses::all();
1362}
1363
1364PreservedAnalyses
1365RISCVAsmPrinterPass::run(MachineFunction &MF,
1366 MachineFunctionAnalysisManager &MFAM) {
1367 RISCVAsmPrinter &AsmPrinter = static_cast<RISCVAsmPrinter &>(
1368 MFAM.getResult<ModuleAnalysisManagerMachineFunctionProxy>(IR&: MF)
1369 .getCachedResult<AsmPrinterAnalysis>(IR&: *MF.getFunction().getParent())
1370 ->getPrinter());
1371 setupMachineFunctionAsmPrinter(MFAM, MF, AsmPrinter);
1372 AsmPrinter.runOnMachineFunction(MF);
1373 return PreservedAnalyses::all();
1374}
1375
1376PreservedAnalyses RISCVAsmPrinterEndPass::run(Module &M,
1377 ModuleAnalysisManager &MAM) {
1378 RISCVAsmPrinter &AsmPrinter = static_cast<RISCVAsmPrinter &>(
1379 MAM.getResult<AsmPrinterAnalysis>(IR&: M).getPrinter());
1380 setupModuleAsmPrinter(M, MAM, AsmPrinter);
1381 AsmPrinter.doFinalization(M);
1382 return PreservedAnalyses::all();
1383}
1384