1//===-- RISCVAsmPrinter.cpp - RISC-V LLVM assembly writer -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a printer that converts from our internal representation
10// of machine-dependent LLVM code to the RISC-V assembly language.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MCTargetDesc/RISCVBaseInfo.h"
15#include "MCTargetDesc/RISCVELFStreamer.h"
16#include "MCTargetDesc/RISCVInstPrinter.h"
17#include "MCTargetDesc/RISCVMCAsmInfo.h"
18#include "MCTargetDesc/RISCVMatInt.h"
19#include "MCTargetDesc/RISCVTargetStreamer.h"
20#include "RISCV.h"
21#include "RISCVConstantPoolValue.h"
22#include "RISCVMachineFunctionInfo.h"
23#include "RISCVRegisterInfo.h"
24#include "TargetInfo/RISCVTargetInfo.h"
25#include "llvm/ADT/APInt.h"
26#include "llvm/ADT/Statistic.h"
27#include "llvm/BinaryFormat/ELF.h"
28#include "llvm/CodeGen/AsmPrinter.h"
29#include "llvm/CodeGen/MachineConstantPool.h"
30#include "llvm/CodeGen/MachineInstr.h"
31#include "llvm/CodeGen/MachineModuleInfo.h"
32#include "llvm/IR/Module.h"
33#include "llvm/MC/MCAsmInfo.h"
34#include "llvm/MC/MCContext.h"
35#include "llvm/MC/MCInst.h"
36#include "llvm/MC/MCInstBuilder.h"
37#include "llvm/MC/MCObjectFileInfo.h"
38#include "llvm/MC/MCSectionELF.h"
39#include "llvm/MC/MCStreamer.h"
40#include "llvm/MC/MCSymbol.h"
41#include "llvm/MC/TargetRegistry.h"
42#include "llvm/Support/Compiler.h"
43#include "llvm/Support/raw_ostream.h"
44#include "llvm/TargetParser/RISCVISAInfo.h"
45#include "llvm/Transforms/Instrumentation/HWAddressSanitizer.h"
46
47using namespace llvm;
48
49#define DEBUG_TYPE "asm-printer"
50
51STATISTIC(RISCVNumInstrsCompressed,
52 "Number of RISC-V Compressed instructions emitted");
53
54namespace llvm {
55extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures];
56} // namespace llvm
57
58namespace {
59class RISCVAsmPrinter : public AsmPrinter {
60public:
61 static char ID;
62
63private:
64 const RISCVSubtarget *STI;
65
66public:
67 explicit RISCVAsmPrinter(TargetMachine &TM,
68 std::unique_ptr<MCStreamer> Streamer)
69 : AsmPrinter(TM, std::move(Streamer), ID) {}
70
71 StringRef getPassName() const override { return "RISC-V Assembly Printer"; }
72
73 void LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
74 const MachineInstr &MI);
75
76 void LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
77 const MachineInstr &MI);
78
79 void LowerSTATEPOINT(MCStreamer &OutStreamer, StackMaps &SM,
80 const MachineInstr &MI);
81
82 bool runOnMachineFunction(MachineFunction &MF) override;
83
84 void emitInstruction(const MachineInstr *MI) override;
85
86 void emitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override;
87
88 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
89 const char *ExtraCode, raw_ostream &OS) override;
90 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
91 const char *ExtraCode, raw_ostream &OS) override;
92
93 // Returns whether Inst is compressed.
94 bool EmitToStreamer(MCStreamer &S, const MCInst &Inst,
95 const MCSubtargetInfo &SubtargetInfo);
96 bool EmitToStreamer(MCStreamer &S, const MCInst &Inst) {
97 return EmitToStreamer(S, Inst, SubtargetInfo: *STI);
98 }
99
100 bool lowerPseudoInstExpansion(const MachineInstr *MI, MCInst &Inst);
101
102 typedef std::tuple<unsigned, uint32_t> HwasanMemaccessTuple;
103 std::map<HwasanMemaccessTuple, MCSymbol *> HwasanMemaccessSymbols;
104 void LowerHWASAN_CHECK_MEMACCESS(const MachineInstr &MI);
105 void LowerKCFI_CHECK(const MachineInstr &MI);
106 void EmitHwasanMemaccessSymbols(Module &M);
107
108 // Wrapper needed for tblgenned pseudo lowering.
109 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const;
110
111 void emitStartOfAsmFile(Module &M) override;
112 void emitEndOfAsmFile(Module &M) override;
113
114 void emitFunctionEntryLabel() override;
115 bool emitDirectiveOptionArch();
116
117 void emitNoteGnuProperty(const Module &M);
118
119private:
120 void emitAttributes(const MCSubtargetInfo &SubtargetInfo);
121
122 void emitNTLHint(const MachineInstr *MI);
123
124 // XRay Support
125 void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr *MI);
126 void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr *MI);
127 void LowerPATCHABLE_TAIL_CALL(const MachineInstr *MI);
128 void emitSled(const MachineInstr *MI, SledKind Kind);
129
130 void lowerToMCInst(const MachineInstr *MI, MCInst &OutMI);
131};
132}
133
134void RISCVAsmPrinter::LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
135 const MachineInstr &MI) {
136 unsigned NOPBytes = STI->hasStdExtZca() ? 2 : 4;
137 unsigned NumNOPBytes = StackMapOpers(&MI).getNumPatchBytes();
138
139 auto &Ctx = OutStreamer.getContext();
140 MCSymbol *MILabel = Ctx.createTempSymbol();
141 OutStreamer.emitLabel(Symbol: MILabel);
142
143 SM.recordStackMap(L: *MILabel, MI);
144 assert(NumNOPBytes % NOPBytes == 0 &&
145 "Invalid number of NOP bytes requested!");
146
147 // Scan ahead to trim the shadow.
148 const MachineBasicBlock &MBB = *MI.getParent();
149 MachineBasicBlock::const_iterator MII(MI);
150 ++MII;
151 while (NumNOPBytes > 0) {
152 if (MII == MBB.end() || MII->isCall() ||
153 MII->getOpcode() == RISCV::DBG_VALUE ||
154 MII->getOpcode() == TargetOpcode::PATCHPOINT ||
155 MII->getOpcode() == TargetOpcode::STACKMAP)
156 break;
157 ++MII;
158 NumNOPBytes -= 4;
159 }
160
161 // Emit nops.
162 emitNops(N: NumNOPBytes / NOPBytes);
163}
164
165// Lower a patchpoint of the form:
166// [<def>], <id>, <numBytes>, <target>, <numArgs>
167void RISCVAsmPrinter::LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
168 const MachineInstr &MI) {
169 unsigned NOPBytes = STI->hasStdExtZca() ? 2 : 4;
170
171 auto &Ctx = OutStreamer.getContext();
172 MCSymbol *MILabel = Ctx.createTempSymbol();
173 OutStreamer.emitLabel(Symbol: MILabel);
174 SM.recordPatchPoint(L: *MILabel, MI);
175
176 PatchPointOpers Opers(&MI);
177
178 const MachineOperand &CalleeMO = Opers.getCallTarget();
179 unsigned EncodedBytes = 0;
180
181 if (CalleeMO.isImm()) {
182 uint64_t CallTarget = CalleeMO.getImm();
183 if (CallTarget) {
184 assert((CallTarget & 0xFFFF'FFFF'FFFF) == CallTarget &&
185 "High 16 bits of call target should be zero.");
186 // Materialize the jump address:
187 SmallVector<MCInst, 8> Seq;
188 RISCVMatInt::generateMCInstSeq(Val: CallTarget, STI: *STI, DestReg: RISCV::X1, Insts&: Seq);
189 for (MCInst &Inst : Seq) {
190 bool Compressed = EmitToStreamer(S&: OutStreamer, Inst);
191 EncodedBytes += Compressed ? 2 : 4;
192 }
193 bool Compressed = EmitToStreamer(S&: OutStreamer, Inst: MCInstBuilder(RISCV::JALR)
194 .addReg(Reg: RISCV::X1)
195 .addReg(Reg: RISCV::X1)
196 .addImm(Val: 0));
197 EncodedBytes += Compressed ? 2 : 4;
198 }
199 } else if (CalleeMO.isGlobal()) {
200 MCOperand CallTargetMCOp;
201 lowerOperand(MO: CalleeMO, MCOp&: CallTargetMCOp);
202 EmitToStreamer(S&: OutStreamer,
203 Inst: MCInstBuilder(RISCV::PseudoCALL).addOperand(Op: CallTargetMCOp));
204 EncodedBytes += 8;
205 }
206
207 // Emit padding.
208 unsigned NumBytes = Opers.getNumPatchBytes();
209 assert(NumBytes >= EncodedBytes &&
210 "Patchpoint can't request size less than the length of a call.");
211 assert((NumBytes - EncodedBytes) % NOPBytes == 0 &&
212 "Invalid number of NOP bytes requested!");
213 emitNops(N: (NumBytes - EncodedBytes) / NOPBytes);
214}
215
216void RISCVAsmPrinter::LowerSTATEPOINT(MCStreamer &OutStreamer, StackMaps &SM,
217 const MachineInstr &MI) {
218 unsigned NOPBytes = STI->hasStdExtZca() ? 2 : 4;
219
220 StatepointOpers SOpers(&MI);
221 if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
222 assert(PatchBytes % NOPBytes == 0 &&
223 "Invalid number of NOP bytes requested!");
224 emitNops(N: PatchBytes / NOPBytes);
225 } else {
226 // Lower call target and choose correct opcode
227 const MachineOperand &CallTarget = SOpers.getCallTarget();
228 MCOperand CallTargetMCOp;
229 switch (CallTarget.getType()) {
230 case MachineOperand::MO_GlobalAddress:
231 case MachineOperand::MO_ExternalSymbol:
232 lowerOperand(MO: CallTarget, MCOp&: CallTargetMCOp);
233 EmitToStreamer(
234 S&: OutStreamer,
235 Inst: MCInstBuilder(RISCV::PseudoCALL).addOperand(Op: CallTargetMCOp));
236 break;
237 case MachineOperand::MO_Immediate:
238 CallTargetMCOp = MCOperand::createImm(Val: CallTarget.getImm());
239 EmitToStreamer(S&: OutStreamer, Inst: MCInstBuilder(RISCV::JAL)
240 .addReg(Reg: RISCV::X1)
241 .addOperand(Op: CallTargetMCOp));
242 break;
243 case MachineOperand::MO_Register:
244 CallTargetMCOp = MCOperand::createReg(Reg: CallTarget.getReg());
245 EmitToStreamer(S&: OutStreamer, Inst: MCInstBuilder(RISCV::JALR)
246 .addReg(Reg: RISCV::X1)
247 .addOperand(Op: CallTargetMCOp)
248 .addImm(Val: 0));
249 break;
250 default:
251 llvm_unreachable("Unsupported operand type in statepoint call target");
252 break;
253 }
254 }
255
256 auto &Ctx = OutStreamer.getContext();
257 MCSymbol *MILabel = Ctx.createTempSymbol();
258 OutStreamer.emitLabel(Symbol: MILabel);
259 SM.recordStatepoint(L: *MILabel, MI);
260}
261
262bool RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst,
263 const MCSubtargetInfo &SubtargetInfo) {
264 MCInst CInst;
265 bool Res = RISCVRVC::compress(OutInst&: CInst, MI: Inst, STI: SubtargetInfo);
266 if (Res)
267 ++RISCVNumInstrsCompressed;
268 S.emitInstruction(Inst: Res ? CInst : Inst, STI: SubtargetInfo);
269 return Res;
270}
271
272// Simple pseudo-instructions have their lowering (with expansion to real
273// instructions) auto-generated.
274#include "RISCVGenMCPseudoLowering.inc"
275
276// If the target supports Zihintntl and the instruction has a nontemporal
277// MachineMemOperand, emit an NTLH hint instruction before it.
278void RISCVAsmPrinter::emitNTLHint(const MachineInstr *MI) {
279 if (!STI->hasStdExtZihintntl())
280 return;
281
282 if (MI->memoperands_empty())
283 return;
284
285 MachineMemOperand *MMO = *(MI->memoperands_begin());
286 if (!MMO->isNonTemporal())
287 return;
288
289 unsigned NontemporalMode = 0;
290 if (MMO->getFlags() & MONontemporalBit0)
291 NontemporalMode += 0b1;
292 if (MMO->getFlags() & MONontemporalBit1)
293 NontemporalMode += 0b10;
294
295 MCInst Hint;
296 if (STI->hasStdExtZca())
297 Hint.setOpcode(RISCV::C_ADD);
298 else
299 Hint.setOpcode(RISCV::ADD);
300
301 Hint.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
302 Hint.addOperand(Op: MCOperand::createReg(Reg: RISCV::X0));
303 Hint.addOperand(Op: MCOperand::createReg(Reg: RISCV::X2 + NontemporalMode));
304
305 EmitToStreamer(S&: *OutStreamer, Inst: Hint);
306}
307
308void RISCVAsmPrinter::emitInstruction(const MachineInstr *MI) {
309 RISCV_MC::verifyInstructionPredicates(Opcode: MI->getOpcode(), Features: STI->getFeatureBits());
310
311 emitNTLHint(MI);
312
313 // Do any auto-generated pseudo lowerings.
314 if (MCInst OutInst; lowerPseudoInstExpansion(MI, Inst&: OutInst)) {
315 EmitToStreamer(S&: *OutStreamer, Inst: OutInst);
316 return;
317 }
318
319 switch (MI->getOpcode()) {
320 case RISCV::HWASAN_CHECK_MEMACCESS_SHORTGRANULES:
321 LowerHWASAN_CHECK_MEMACCESS(MI: *MI);
322 return;
323 case RISCV::KCFI_CHECK:
324 LowerKCFI_CHECK(MI: *MI);
325 return;
326 case TargetOpcode::STACKMAP:
327 return LowerSTACKMAP(OutStreamer&: *OutStreamer, SM, MI: *MI);
328 case TargetOpcode::PATCHPOINT:
329 return LowerPATCHPOINT(OutStreamer&: *OutStreamer, SM, MI: *MI);
330 case TargetOpcode::STATEPOINT:
331 return LowerSTATEPOINT(OutStreamer&: *OutStreamer, SM, MI: *MI);
332 case TargetOpcode::PATCHABLE_FUNCTION_ENTER: {
333 const Function &F = MI->getParent()->getParent()->getFunction();
334 if (F.hasFnAttribute(Kind: "patchable-function-entry")) {
335 unsigned Num;
336 [[maybe_unused]] bool Result =
337 F.getFnAttribute(Kind: "patchable-function-entry")
338 .getValueAsString()
339 .getAsInteger(Radix: 10, Result&: Num);
340 assert(!Result && "Enforced by the verifier");
341 emitNops(N: Num);
342 return;
343 }
344 LowerPATCHABLE_FUNCTION_ENTER(MI);
345 return;
346 }
347 case TargetOpcode::PATCHABLE_FUNCTION_EXIT:
348 LowerPATCHABLE_FUNCTION_EXIT(MI);
349 return;
350 case TargetOpcode::PATCHABLE_TAIL_CALL:
351 LowerPATCHABLE_TAIL_CALL(MI);
352 return;
353 }
354
355 MCInst OutInst;
356 lowerToMCInst(MI, OutMI&: OutInst);
357 EmitToStreamer(S&: *OutStreamer, Inst: OutInst);
358}
359
360bool RISCVAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
361 const char *ExtraCode, raw_ostream &OS) {
362 // First try the generic code, which knows about modifiers like 'c' and 'n'.
363 if (!AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS))
364 return false;
365
366 const MachineOperand &MO = MI->getOperand(i: OpNo);
367 if (ExtraCode && ExtraCode[0]) {
368 if (ExtraCode[1] != 0)
369 return true; // Unknown modifier.
370
371 switch (ExtraCode[0]) {
372 default:
373 return true; // Unknown modifier.
374 case 'z': // Print zero register if zero, regular printing otherwise.
375 if (MO.isImm() && MO.getImm() == 0) {
376 OS << RISCVInstPrinter::getRegisterName(Reg: RISCV::X0);
377 return false;
378 }
379 break;
380 case 'i': // Literal 'i' if operand is not a register.
381 if (!MO.isReg())
382 OS << 'i';
383 return false;
384 case 'N': // Print the register encoding as an integer (0-31)
385 if (!MO.isReg())
386 return true;
387
388 const RISCVRegisterInfo *TRI = STI->getRegisterInfo();
389 OS << TRI->getEncodingValue(Reg: MO.getReg());
390 return false;
391 }
392 }
393
394 switch (MO.getType()) {
395 case MachineOperand::MO_Immediate:
396 OS << MO.getImm();
397 return false;
398 case MachineOperand::MO_Register:
399 OS << RISCVInstPrinter::getRegisterName(Reg: MO.getReg());
400 return false;
401 case MachineOperand::MO_GlobalAddress:
402 PrintSymbolOperand(MO, OS);
403 return false;
404 case MachineOperand::MO_BlockAddress: {
405 MCSymbol *Sym = GetBlockAddressSymbol(BA: MO.getBlockAddress());
406 Sym->print(OS, MAI);
407 return false;
408 }
409 default:
410 break;
411 }
412
413 return true;
414}
415
416bool RISCVAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
417 unsigned OpNo,
418 const char *ExtraCode,
419 raw_ostream &OS) {
420 if (ExtraCode)
421 return AsmPrinter::PrintAsmMemoryOperand(MI, OpNo, ExtraCode, OS);
422
423 const MachineOperand &AddrReg = MI->getOperand(i: OpNo);
424 assert(MI->getNumOperands() > OpNo + 1 && "Expected additional operand");
425 const MachineOperand &Offset = MI->getOperand(i: OpNo + 1);
426 // All memory operands should have a register and an immediate operand (see
427 // RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand).
428 if (!AddrReg.isReg())
429 return true;
430 if (!Offset.isImm() && !Offset.isGlobal() && !Offset.isBlockAddress() &&
431 !Offset.isMCSymbol())
432 return true;
433
434 MCOperand MCO;
435 if (!lowerOperand(MO: Offset, MCOp&: MCO))
436 return true;
437
438 if (Offset.isImm())
439 OS << MCO.getImm();
440 else if (Offset.isGlobal() || Offset.isBlockAddress() || Offset.isMCSymbol())
441 MAI->printExpr(OS, *MCO.getExpr());
442
443 if (Offset.isMCSymbol())
444 MMI->getContext().registerInlineAsmLabel(Sym: Offset.getMCSymbol());
445 if (Offset.isBlockAddress()) {
446 const BlockAddress *BA = Offset.getBlockAddress();
447 MCSymbol *Sym = GetBlockAddressSymbol(BA);
448 MMI->getContext().registerInlineAsmLabel(Sym);
449 }
450
451 OS << "(" << RISCVInstPrinter::getRegisterName(Reg: AddrReg.getReg()) << ")";
452 return false;
453}
454
455bool RISCVAsmPrinter::emitDirectiveOptionArch() {
456 RISCVTargetStreamer &RTS =
457 static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
458 SmallVector<RISCVOptionArchArg> NeedEmitStdOptionArgs;
459 const MCSubtargetInfo &MCSTI = *TM.getMCSubtargetInfo();
460 for (const auto &Feature : RISCVFeatureKV) {
461 if (STI->hasFeature(Feature: Feature.Value) == MCSTI.hasFeature(Feature: Feature.Value))
462 continue;
463
464 if (!llvm::RISCVISAInfo::isSupportedExtensionFeature(Ext: Feature.Key))
465 continue;
466
467 auto Delta = STI->hasFeature(Feature: Feature.Value) ? RISCVOptionArchArgType::Plus
468 : RISCVOptionArchArgType::Minus;
469 NeedEmitStdOptionArgs.emplace_back(Args&: Delta, Args: Feature.Key);
470 }
471 if (!NeedEmitStdOptionArgs.empty()) {
472 RTS.emitDirectiveOptionPush();
473 RTS.emitDirectiveOptionArch(Args: NeedEmitStdOptionArgs);
474 return true;
475 }
476
477 return false;
478}
479
480bool RISCVAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
481 STI = &MF.getSubtarget<RISCVSubtarget>();
482 RISCVTargetStreamer &RTS =
483 static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
484
485 bool EmittedOptionArch = emitDirectiveOptionArch();
486
487 SetupMachineFunction(MF);
488 emitFunctionBody();
489
490 // Emit the XRay table
491 emitXRayTable();
492
493 if (EmittedOptionArch)
494 RTS.emitDirectiveOptionPop();
495 return false;
496}
497
498void RISCVAsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr *MI) {
499 emitSled(MI, Kind: SledKind::FUNCTION_ENTER);
500}
501
502void RISCVAsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr *MI) {
503 emitSled(MI, Kind: SledKind::FUNCTION_EXIT);
504}
505
506void RISCVAsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr *MI) {
507 emitSled(MI, Kind: SledKind::TAIL_CALL);
508}
509
510void RISCVAsmPrinter::emitSled(const MachineInstr *MI, SledKind Kind) {
511 // We want to emit the jump instruction and the nops constituting the sled.
512 // The format is as follows:
513 // .Lxray_sled_N
514 // ALIGN
515 // J .tmpN
516 // 21 or 33 C.NOP instructions
517 // .tmpN
518
519 // The following variable holds the count of the number of NOPs to be patched
520 // in for XRay instrumentation during compilation.
521 // Note that RV64 and RV32 each has a sled of 68 and 44 bytes, respectively.
522 // Assuming we're using JAL to jump to .tmpN, then we only need
523 // (68 - 4)/2 = 32 NOPs for RV64 and (44 - 4)/2 = 20 for RV32. However, there
524 // is a chance that we'll use C.JAL instead, so an additional NOP is needed.
525 const uint8_t NoopsInSledCount = STI->is64Bit() ? 33 : 21;
526
527 OutStreamer->emitCodeAlignment(Alignment: Align(4), STI);
528 auto CurSled = OutContext.createTempSymbol(Name: "xray_sled_", AlwaysAddSuffix: true);
529 OutStreamer->emitLabel(Symbol: CurSled);
530 auto Target = OutContext.createTempSymbol();
531
532 const MCExpr *TargetExpr = MCSymbolRefExpr::create(Symbol: Target, Ctx&: OutContext);
533
534 // Emit "J bytes" instruction, which jumps over the nop sled to the actual
535 // start of function.
536 EmitToStreamer(
537 S&: *OutStreamer,
538 Inst: MCInstBuilder(RISCV::JAL).addReg(Reg: RISCV::X0).addExpr(Val: TargetExpr));
539
540 // Emit NOP instructions
541 for (int8_t I = 0; I < NoopsInSledCount; ++I)
542 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(RISCV::ADDI)
543 .addReg(Reg: RISCV::X0)
544 .addReg(Reg: RISCV::X0)
545 .addImm(Val: 0));
546
547 OutStreamer->emitLabel(Symbol: Target);
548 recordSled(Sled: CurSled, MI: *MI, Kind, Version: 2);
549}
550
551void RISCVAsmPrinter::emitStartOfAsmFile(Module &M) {
552 assert(OutStreamer->getTargetStreamer() &&
553 "target streamer is uninitialized");
554 RISCVTargetStreamer &RTS =
555 static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
556 if (const MDString *ModuleTargetABI =
557 dyn_cast_or_null<MDString>(Val: M.getModuleFlag(Key: "target-abi")))
558 RTS.setTargetABI(RISCVABI::getTargetABI(ABIName: ModuleTargetABI->getString()));
559
560 MCSubtargetInfo SubtargetInfo = *TM.getMCSubtargetInfo();
561
562 // Use module flag to update feature bits.
563 if (auto *MD = dyn_cast_or_null<MDNode>(Val: M.getModuleFlag(Key: "riscv-isa"))) {
564 for (auto &ISA : MD->operands()) {
565 if (auto *ISAString = dyn_cast_or_null<MDString>(Val: ISA)) {
566 auto ParseResult = llvm::RISCVISAInfo::parseArchString(
567 Arch: ISAString->getString(), /*EnableExperimentalExtension=*/true,
568 /*ExperimentalExtensionVersionCheck=*/true);
569 if (!errorToBool(Err: ParseResult.takeError())) {
570 auto &ISAInfo = *ParseResult;
571 for (const auto &Feature : RISCVFeatureKV) {
572 if (ISAInfo->hasExtension(Ext: Feature.Key) &&
573 !SubtargetInfo.hasFeature(Feature: Feature.Value))
574 SubtargetInfo.ToggleFeature(FS: Feature.Key);
575 }
576 }
577 }
578 }
579
580 RTS.setFlagsFromFeatures(SubtargetInfo);
581 }
582
583 if (TM.getTargetTriple().isOSBinFormatELF())
584 emitAttributes(SubtargetInfo);
585}
586
587void RISCVAsmPrinter::emitEndOfAsmFile(Module &M) {
588 RISCVTargetStreamer &RTS =
589 static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
590
591 if (TM.getTargetTriple().isOSBinFormatELF()) {
592 RTS.finishAttributeSection();
593 emitNoteGnuProperty(M);
594 }
595 EmitHwasanMemaccessSymbols(M);
596}
597
598void RISCVAsmPrinter::emitAttributes(const MCSubtargetInfo &SubtargetInfo) {
599 RISCVTargetStreamer &RTS =
600 static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
601 // Use MCSubtargetInfo from TargetMachine. Individual functions may have
602 // attributes that differ from other functions in the module and we have no
603 // way to know which function is correct.
604 RTS.emitTargetAttributes(STI: SubtargetInfo, /*EmitStackAlign*/ true);
605}
606
607void RISCVAsmPrinter::emitFunctionEntryLabel() {
608 const auto *RMFI = MF->getInfo<RISCVMachineFunctionInfo>();
609 if (RMFI->isVectorCall()) {
610 auto &RTS =
611 static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
612 RTS.emitDirectiveVariantCC(Symbol&: *CurrentFnSym);
613 }
614 return AsmPrinter::emitFunctionEntryLabel();
615}
616
617// Force static initialization.
618extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
619LLVMInitializeRISCVAsmPrinter() {
620 RegisterAsmPrinter<RISCVAsmPrinter> X(getTheRISCV32Target());
621 RegisterAsmPrinter<RISCVAsmPrinter> Y(getTheRISCV64Target());
622 RegisterAsmPrinter<RISCVAsmPrinter> A(getTheRISCV32beTarget());
623 RegisterAsmPrinter<RISCVAsmPrinter> B(getTheRISCV64beTarget());
624}
625
626void RISCVAsmPrinter::LowerHWASAN_CHECK_MEMACCESS(const MachineInstr &MI) {
627 Register Reg = MI.getOperand(i: 0).getReg();
628 uint32_t AccessInfo = MI.getOperand(i: 1).getImm();
629 MCSymbol *&Sym =
630 HwasanMemaccessSymbols[HwasanMemaccessTuple(Reg, AccessInfo)];
631 if (!Sym) {
632 // FIXME: Make this work on non-ELF.
633 if (!TM.getTargetTriple().isOSBinFormatELF())
634 report_fatal_error(reason: "llvm.hwasan.check.memaccess only supported on ELF");
635
636 std::string SymName = "__hwasan_check_x" + utostr(X: Reg - RISCV::X0) + "_" +
637 utostr(X: AccessInfo) + "_short";
638 Sym = OutContext.getOrCreateSymbol(Name: SymName);
639 }
640 auto Res = MCSymbolRefExpr::create(Symbol: Sym, Ctx&: OutContext);
641 auto Expr = MCSpecifierExpr::create(Expr: Res, S: RISCV::S_CALL_PLT, Ctx&: OutContext);
642
643 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(RISCV::PseudoCALL).addExpr(Val: Expr));
644}
645
646void RISCVAsmPrinter::LowerKCFI_CHECK(const MachineInstr &MI) {
647 Register AddrReg = MI.getOperand(i: 0).getReg();
648 assert(std::next(MI.getIterator())->isCall() &&
649 "KCFI_CHECK not followed by a call instruction");
650 assert(std::next(MI.getIterator())->getOperand(0).getReg() == AddrReg &&
651 "KCFI_CHECK call target doesn't match call operand");
652
653 // Temporary registers for comparing the hashes. If a register is used
654 // for the call target, or reserved by the user, we can clobber another
655 // temporary register as the check is immediately followed by the
656 // call. The check defaults to X6/X7, but can fall back to X28-X31 if
657 // needed.
658 unsigned ScratchRegs[] = {RISCV::X6, RISCV::X7};
659 unsigned NextReg = RISCV::X28;
660 auto isRegAvailable = [&](unsigned Reg) {
661 return Reg != AddrReg && !STI->isRegisterReservedByUser(i: Reg);
662 };
663 for (auto &Reg : ScratchRegs) {
664 if (isRegAvailable(Reg))
665 continue;
666 while (!isRegAvailable(NextReg))
667 ++NextReg;
668 Reg = NextReg++;
669 if (Reg > RISCV::X31)
670 report_fatal_error(reason: "Unable to find scratch registers for KCFI_CHECK");
671 }
672
673 if (AddrReg == RISCV::X0) {
674 // Checking X0 makes no sense. Instead of emitting a load, zero
675 // ScratchRegs[0].
676 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(RISCV::ADDI)
677 .addReg(Reg: ScratchRegs[0])
678 .addReg(Reg: RISCV::X0)
679 .addImm(Val: 0));
680 } else {
681 // Adjust the offset for patchable-function-prefix. This assumes that
682 // patchable-function-prefix is the same for all functions.
683 int NopSize = STI->hasStdExtZca() ? 2 : 4;
684 int64_t PrefixNops = 0;
685 (void)MI.getMF()
686 ->getFunction()
687 .getFnAttribute(Kind: "patchable-function-prefix")
688 .getValueAsString()
689 .getAsInteger(Radix: 10, Result&: PrefixNops);
690
691 // Load the target function type hash.
692 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(RISCV::LW)
693 .addReg(Reg: ScratchRegs[0])
694 .addReg(Reg: AddrReg)
695 .addImm(Val: -(PrefixNops * NopSize + 4)));
696 }
697
698 // Load the expected 32-bit type hash.
699 const int64_t Type = MI.getOperand(i: 1).getImm();
700 const int64_t Hi20 = ((Type + 0x800) >> 12) & 0xFFFFF;
701 const int64_t Lo12 = SignExtend64<12>(x: Type);
702 if (Hi20) {
703 EmitToStreamer(
704 S&: *OutStreamer,
705 Inst: MCInstBuilder(RISCV::LUI).addReg(Reg: ScratchRegs[1]).addImm(Val: Hi20));
706 }
707 if (Lo12 || Hi20 == 0) {
708 EmitToStreamer(S&: *OutStreamer,
709 Inst: MCInstBuilder((STI->hasFeature(Feature: RISCV::Feature64Bit) && Hi20)
710 ? RISCV::ADDIW
711 : RISCV::ADDI)
712 .addReg(Reg: ScratchRegs[1])
713 .addReg(Reg: ScratchRegs[1])
714 .addImm(Val: Lo12));
715 }
716
717 // Compare the hashes and trap if there's a mismatch.
718 MCSymbol *Pass = OutContext.createTempSymbol();
719 EmitToStreamer(S&: *OutStreamer,
720 Inst: MCInstBuilder(RISCV::BEQ)
721 .addReg(Reg: ScratchRegs[0])
722 .addReg(Reg: ScratchRegs[1])
723 .addExpr(Val: MCSymbolRefExpr::create(Symbol: Pass, Ctx&: OutContext)));
724
725 MCSymbol *Trap = OutContext.createTempSymbol();
726 OutStreamer->emitLabel(Symbol: Trap);
727 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(RISCV::EBREAK));
728 emitKCFITrapEntry(MF: *MI.getMF(), Symbol: Trap);
729 OutStreamer->emitLabel(Symbol: Pass);
730}
731
732void RISCVAsmPrinter::EmitHwasanMemaccessSymbols(Module &M) {
733 if (HwasanMemaccessSymbols.empty())
734 return;
735
736 assert(TM.getTargetTriple().isOSBinFormatELF());
737 // Use MCSubtargetInfo from TargetMachine. Individual functions may have
738 // attributes that differ from other functions in the module and we have no
739 // way to know which function is correct.
740 const MCSubtargetInfo &MCSTI = *TM.getMCSubtargetInfo();
741
742 MCSymbol *HwasanTagMismatchV2Sym =
743 OutContext.getOrCreateSymbol(Name: "__hwasan_tag_mismatch_v2");
744 // Annotate symbol as one having incompatible calling convention, so
745 // run-time linkers can instead eagerly bind this function.
746 auto &RTS =
747 static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
748 RTS.emitDirectiveVariantCC(Symbol&: *HwasanTagMismatchV2Sym);
749
750 const MCSymbolRefExpr *HwasanTagMismatchV2Ref =
751 MCSymbolRefExpr::create(Symbol: HwasanTagMismatchV2Sym, Ctx&: OutContext);
752 auto Expr = MCSpecifierExpr::create(Expr: HwasanTagMismatchV2Ref, S: RISCV::S_CALL_PLT,
753 Ctx&: OutContext);
754
755 for (auto &P : HwasanMemaccessSymbols) {
756 unsigned Reg = std::get<0>(t: P.first);
757 uint32_t AccessInfo = std::get<1>(t: P.first);
758 MCSymbol *Sym = P.second;
759
760 unsigned Size =
761 1 << ((AccessInfo >> HWASanAccessInfo::AccessSizeShift) & 0xf);
762 OutStreamer->switchSection(Section: OutContext.getELFSection(
763 Section: ".text.hot", Type: ELF::SHT_PROGBITS,
764 Flags: ELF::SHF_EXECINSTR | ELF::SHF_ALLOC | ELF::SHF_GROUP, EntrySize: 0, Group: Sym->getName(),
765 /*IsComdat=*/true));
766
767 OutStreamer->emitSymbolAttribute(Symbol: Sym, Attribute: MCSA_ELF_TypeFunction);
768 OutStreamer->emitSymbolAttribute(Symbol: Sym, Attribute: MCSA_Weak);
769 OutStreamer->emitSymbolAttribute(Symbol: Sym, Attribute: MCSA_Hidden);
770 OutStreamer->emitLabel(Symbol: Sym);
771
772 // Extract shadow offset from ptr
773 EmitToStreamer(
774 S&: *OutStreamer,
775 Inst: MCInstBuilder(RISCV::SLLI).addReg(Reg: RISCV::X6).addReg(Reg).addImm(Val: 8),
776 SubtargetInfo: MCSTI);
777 EmitToStreamer(S&: *OutStreamer,
778 Inst: MCInstBuilder(RISCV::SRLI)
779 .addReg(Reg: RISCV::X6)
780 .addReg(Reg: RISCV::X6)
781 .addImm(Val: 12),
782 SubtargetInfo: MCSTI);
783 // load shadow tag in X6, X5 contains shadow base
784 EmitToStreamer(S&: *OutStreamer,
785 Inst: MCInstBuilder(RISCV::ADD)
786 .addReg(Reg: RISCV::X6)
787 .addReg(Reg: RISCV::X5)
788 .addReg(Reg: RISCV::X6),
789 SubtargetInfo: MCSTI);
790 EmitToStreamer(
791 S&: *OutStreamer,
792 Inst: MCInstBuilder(RISCV::LBU).addReg(Reg: RISCV::X6).addReg(Reg: RISCV::X6).addImm(Val: 0),
793 SubtargetInfo: MCSTI);
794 // Extract tag from pointer and compare it with loaded tag from shadow
795 EmitToStreamer(
796 S&: *OutStreamer,
797 Inst: MCInstBuilder(RISCV::SRLI).addReg(Reg: RISCV::X7).addReg(Reg).addImm(Val: 56),
798 SubtargetInfo: MCSTI);
799 MCSymbol *HandleMismatchOrPartialSym = OutContext.createTempSymbol();
800 // X7 contains tag from the pointer, while X6 contains tag from memory
801 EmitToStreamer(S&: *OutStreamer,
802 Inst: MCInstBuilder(RISCV::BNE)
803 .addReg(Reg: RISCV::X7)
804 .addReg(Reg: RISCV::X6)
805 .addExpr(Val: MCSymbolRefExpr::create(
806 Symbol: HandleMismatchOrPartialSym, Ctx&: OutContext)),
807 SubtargetInfo: MCSTI);
808 MCSymbol *ReturnSym = OutContext.createTempSymbol();
809 OutStreamer->emitLabel(Symbol: ReturnSym);
810 EmitToStreamer(S&: *OutStreamer,
811 Inst: MCInstBuilder(RISCV::JALR)
812 .addReg(Reg: RISCV::X0)
813 .addReg(Reg: RISCV::X1)
814 .addImm(Val: 0),
815 SubtargetInfo: MCSTI);
816 OutStreamer->emitLabel(Symbol: HandleMismatchOrPartialSym);
817
818 EmitToStreamer(S&: *OutStreamer,
819 Inst: MCInstBuilder(RISCV::ADDI)
820 .addReg(Reg: RISCV::X28)
821 .addReg(Reg: RISCV::X0)
822 .addImm(Val: 16),
823 SubtargetInfo: MCSTI);
824 MCSymbol *HandleMismatchSym = OutContext.createTempSymbol();
825 EmitToStreamer(
826 S&: *OutStreamer,
827 Inst: MCInstBuilder(RISCV::BGEU)
828 .addReg(Reg: RISCV::X6)
829 .addReg(Reg: RISCV::X28)
830 .addExpr(Val: MCSymbolRefExpr::create(Symbol: HandleMismatchSym, Ctx&: OutContext)),
831 SubtargetInfo: MCSTI);
832
833 EmitToStreamer(
834 S&: *OutStreamer,
835 Inst: MCInstBuilder(RISCV::ANDI).addReg(Reg: RISCV::X28).addReg(Reg).addImm(Val: 0xF),
836 SubtargetInfo: MCSTI);
837
838 if (Size != 1)
839 EmitToStreamer(S&: *OutStreamer,
840 Inst: MCInstBuilder(RISCV::ADDI)
841 .addReg(Reg: RISCV::X28)
842 .addReg(Reg: RISCV::X28)
843 .addImm(Val: Size - 1),
844 SubtargetInfo: MCSTI);
845 EmitToStreamer(
846 S&: *OutStreamer,
847 Inst: MCInstBuilder(RISCV::BGE)
848 .addReg(Reg: RISCV::X28)
849 .addReg(Reg: RISCV::X6)
850 .addExpr(Val: MCSymbolRefExpr::create(Symbol: HandleMismatchSym, Ctx&: OutContext)),
851 SubtargetInfo: MCSTI);
852
853 EmitToStreamer(
854 S&: *OutStreamer,
855 Inst: MCInstBuilder(RISCV::ORI).addReg(Reg: RISCV::X6).addReg(Reg).addImm(Val: 0xF),
856 SubtargetInfo: MCSTI);
857 EmitToStreamer(
858 S&: *OutStreamer,
859 Inst: MCInstBuilder(RISCV::LBU).addReg(Reg: RISCV::X6).addReg(Reg: RISCV::X6).addImm(Val: 0),
860 SubtargetInfo: MCSTI);
861 EmitToStreamer(S&: *OutStreamer,
862 Inst: MCInstBuilder(RISCV::BEQ)
863 .addReg(Reg: RISCV::X6)
864 .addReg(Reg: RISCV::X7)
865 .addExpr(Val: MCSymbolRefExpr::create(Symbol: ReturnSym, Ctx&: OutContext)),
866 SubtargetInfo: MCSTI);
867
868 OutStreamer->emitLabel(Symbol: HandleMismatchSym);
869
870 // | Previous stack frames... |
871 // +=================================+ <-- [SP + 256]
872 // | ... |
873 // | |
874 // | Stack frame space for x12 - x31.|
875 // | |
876 // | ... |
877 // +---------------------------------+ <-- [SP + 96]
878 // | Saved x11(arg1), as |
879 // | __hwasan_check_* clobbers it. |
880 // +---------------------------------+ <-- [SP + 88]
881 // | Saved x10(arg0), as |
882 // | __hwasan_check_* clobbers it. |
883 // +---------------------------------+ <-- [SP + 80]
884 // | |
885 // | Stack frame space for x9. |
886 // +---------------------------------+ <-- [SP + 72]
887 // | |
888 // | Saved x8(fp), as |
889 // | __hwasan_check_* clobbers it. |
890 // +---------------------------------+ <-- [SP + 64]
891 // | ... |
892 // | |
893 // | Stack frame space for x2 - x7. |
894 // | |
895 // | ... |
896 // +---------------------------------+ <-- [SP + 16]
897 // | Return address (x1) for caller |
898 // | of __hwasan_check_*. |
899 // +---------------------------------+ <-- [SP + 8]
900 // | Reserved place for x0, possibly |
901 // | junk, since we don't save it. |
902 // +---------------------------------+ <-- [x2 / SP]
903
904 // Adjust sp
905 EmitToStreamer(S&: *OutStreamer,
906 Inst: MCInstBuilder(RISCV::ADDI)
907 .addReg(Reg: RISCV::X2)
908 .addReg(Reg: RISCV::X2)
909 .addImm(Val: -256),
910 SubtargetInfo: MCSTI);
911
912 // store x10(arg0) by new sp
913 EmitToStreamer(S&: *OutStreamer,
914 Inst: MCInstBuilder(RISCV::SD)
915 .addReg(Reg: RISCV::X10)
916 .addReg(Reg: RISCV::X2)
917 .addImm(Val: 8 * 10),
918 SubtargetInfo: MCSTI);
919 // store x11(arg1) by new sp
920 EmitToStreamer(S&: *OutStreamer,
921 Inst: MCInstBuilder(RISCV::SD)
922 .addReg(Reg: RISCV::X11)
923 .addReg(Reg: RISCV::X2)
924 .addImm(Val: 8 * 11),
925 SubtargetInfo: MCSTI);
926
927 // store x8(fp) by new sp
928 EmitToStreamer(
929 S&: *OutStreamer,
930 Inst: MCInstBuilder(RISCV::SD).addReg(Reg: RISCV::X8).addReg(Reg: RISCV::X2).addImm(Val: 8 *
931 8),
932 SubtargetInfo: MCSTI);
933 // store x1(ra) by new sp
934 EmitToStreamer(
935 S&: *OutStreamer,
936 Inst: MCInstBuilder(RISCV::SD).addReg(Reg: RISCV::X1).addReg(Reg: RISCV::X2).addImm(Val: 1 *
937 8),
938 SubtargetInfo: MCSTI);
939 if (Reg != RISCV::X10)
940 EmitToStreamer(
941 S&: *OutStreamer,
942 Inst: MCInstBuilder(RISCV::ADDI).addReg(Reg: RISCV::X10).addReg(Reg).addImm(Val: 0),
943 SubtargetInfo: MCSTI);
944 EmitToStreamer(S&: *OutStreamer,
945 Inst: MCInstBuilder(RISCV::ADDI)
946 .addReg(Reg: RISCV::X11)
947 .addReg(Reg: RISCV::X0)
948 .addImm(Val: AccessInfo & HWASanAccessInfo::RuntimeMask),
949 SubtargetInfo: MCSTI);
950
951 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(RISCV::PseudoCALL).addExpr(Val: Expr),
952 SubtargetInfo: MCSTI);
953 }
954}
955
956void RISCVAsmPrinter::emitNoteGnuProperty(const Module &M) {
957 assert(TM.getTargetTriple().isOSBinFormatELF() && "invalid binary format");
958 if (const Metadata *const Flag = M.getModuleFlag(Key: "cf-protection-return");
959 Flag && !mdconst::extract<ConstantInt>(MD: Flag)->isZero()) {
960 RISCVTargetELFStreamer &RTS = static_cast<RISCVTargetELFStreamer &>(
961 *OutStreamer->getTargetStreamer());
962 RTS.emitNoteGnuPropertySection(Feature1And: ELF::GNU_PROPERTY_RISCV_FEATURE_1_CFI_SS);
963 }
964}
965
966static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym,
967 const AsmPrinter &AP) {
968 MCContext &Ctx = AP.OutContext;
969 RISCV::Specifier Kind;
970
971 switch (MO.getTargetFlags()) {
972 default:
973 llvm_unreachable("Unknown target flag on GV operand");
974 case RISCVII::MO_None:
975 Kind = RISCV::S_None;
976 break;
977 case RISCVII::MO_CALL:
978 Kind = RISCV::S_CALL_PLT;
979 break;
980 case RISCVII::MO_LO:
981 Kind = RISCV::S_LO;
982 break;
983 case RISCVII::MO_HI:
984 Kind = ELF::R_RISCV_HI20;
985 break;
986 case RISCVII::MO_PCREL_LO:
987 Kind = RISCV::S_PCREL_LO;
988 break;
989 case RISCVII::MO_PCREL_HI:
990 Kind = RISCV::S_PCREL_HI;
991 break;
992 case RISCVII::MO_GOT_HI:
993 Kind = RISCV::S_GOT_HI;
994 break;
995 case RISCVII::MO_TPREL_LO:
996 Kind = RISCV::S_TPREL_LO;
997 break;
998 case RISCVII::MO_TPREL_HI:
999 Kind = ELF::R_RISCV_TPREL_HI20;
1000 break;
1001 case RISCVII::MO_TPREL_ADD:
1002 Kind = ELF::R_RISCV_TPREL_ADD;
1003 break;
1004 case RISCVII::MO_TLS_GOT_HI:
1005 Kind = ELF::R_RISCV_TLS_GOT_HI20;
1006 break;
1007 case RISCVII::MO_TLS_GD_HI:
1008 Kind = ELF::R_RISCV_TLS_GD_HI20;
1009 break;
1010 case RISCVII::MO_TLSDESC_HI:
1011 Kind = ELF::R_RISCV_TLSDESC_HI20;
1012 break;
1013 case RISCVII::MO_TLSDESC_LOAD_LO:
1014 Kind = ELF::R_RISCV_TLSDESC_LOAD_LO12;
1015 break;
1016 case RISCVII::MO_TLSDESC_ADD_LO:
1017 Kind = ELF::R_RISCV_TLSDESC_ADD_LO12;
1018 break;
1019 case RISCVII::MO_TLSDESC_CALL:
1020 Kind = ELF::R_RISCV_TLSDESC_CALL;
1021 break;
1022 }
1023
1024 const MCExpr *ME = MCSymbolRefExpr::create(Symbol: Sym, Ctx);
1025
1026 if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
1027 ME = MCBinaryExpr::createAdd(
1028 LHS: ME, RHS: MCConstantExpr::create(Value: MO.getOffset(), Ctx), Ctx);
1029
1030 if (Kind != RISCV::S_None)
1031 ME = MCSpecifierExpr::create(Expr: ME, S: Kind, Ctx);
1032 return MCOperand::createExpr(Val: ME);
1033}
1034
1035bool RISCVAsmPrinter::lowerOperand(const MachineOperand &MO,
1036 MCOperand &MCOp) const {
1037 switch (MO.getType()) {
1038 default:
1039 report_fatal_error(reason: "lowerOperand: unknown operand type");
1040 case MachineOperand::MO_Register:
1041 // Ignore all implicit register operands.
1042 if (MO.isImplicit())
1043 return false;
1044 MCOp = MCOperand::createReg(Reg: MO.getReg());
1045 break;
1046 case MachineOperand::MO_RegisterMask:
1047 // Regmasks are like implicit defs.
1048 return false;
1049 case MachineOperand::MO_Immediate:
1050 MCOp = MCOperand::createImm(Val: MO.getImm());
1051 break;
1052 case MachineOperand::MO_MachineBasicBlock:
1053 MCOp = lowerSymbolOperand(MO, Sym: MO.getMBB()->getSymbol(), AP: *this);
1054 break;
1055 case MachineOperand::MO_GlobalAddress:
1056 MCOp = lowerSymbolOperand(MO, Sym: getSymbolPreferLocal(GV: *MO.getGlobal()), AP: *this);
1057 break;
1058 case MachineOperand::MO_BlockAddress:
1059 MCOp = lowerSymbolOperand(MO, Sym: GetBlockAddressSymbol(BA: MO.getBlockAddress()),
1060 AP: *this);
1061 break;
1062 case MachineOperand::MO_ExternalSymbol:
1063 MCOp = lowerSymbolOperand(MO, Sym: GetExternalSymbolSymbol(Sym: MO.getSymbolName()),
1064 AP: *this);
1065 break;
1066 case MachineOperand::MO_ConstantPoolIndex:
1067 MCOp = lowerSymbolOperand(MO, Sym: GetCPISymbol(CPID: MO.getIndex()), AP: *this);
1068 break;
1069 case MachineOperand::MO_JumpTableIndex:
1070 MCOp = lowerSymbolOperand(MO, Sym: GetJTISymbol(JTID: MO.getIndex()), AP: *this);
1071 break;
1072 case MachineOperand::MO_MCSymbol:
1073 MCOp = lowerSymbolOperand(MO, Sym: MO.getMCSymbol(), AP: *this);
1074 break;
1075 }
1076 return true;
1077}
1078
1079static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI,
1080 MCInst &OutMI,
1081 const RISCVSubtarget *STI) {
1082 const RISCVVPseudosTable::PseudoInfo *RVV =
1083 RISCVVPseudosTable::getPseudoInfo(Pseudo: MI->getOpcode());
1084 if (!RVV)
1085 return false;
1086
1087 OutMI.setOpcode(RVV->BaseInstr);
1088
1089 const TargetInstrInfo *TII = STI->getInstrInfo();
1090 const TargetRegisterInfo *TRI = STI->getRegisterInfo();
1091 assert(TRI && "TargetRegisterInfo expected");
1092
1093 const MCInstrDesc &MCID = MI->getDesc();
1094 uint64_t TSFlags = MCID.TSFlags;
1095 unsigned NumOps = MI->getNumExplicitOperands();
1096
1097 // Skip policy, SEW, VL, VXRM/FRM operands which are the last operands if
1098 // present.
1099 if (RISCVII::hasVecPolicyOp(TSFlags))
1100 --NumOps;
1101 if (RISCVII::hasSEWOp(TSFlags))
1102 --NumOps;
1103 if (RISCVII::hasVLOp(TSFlags))
1104 --NumOps;
1105 if (RISCVII::hasRoundModeOp(TSFlags))
1106 --NumOps;
1107 if (RISCVII::hasTWidenOp(TSFlags))
1108 --NumOps;
1109 if (RISCVII::hasTMOp(TSFlags))
1110 --NumOps;
1111 if (RISCVII::hasTKOp(TSFlags))
1112 --NumOps;
1113
1114 bool hasVLOutput = RISCVInstrInfo::isFaultOnlyFirstLoad(MI: *MI);
1115 for (unsigned OpNo = 0; OpNo != NumOps; ++OpNo) {
1116 const MachineOperand &MO = MI->getOperand(i: OpNo);
1117 // Skip vl output. It should be the second output.
1118 if (hasVLOutput && OpNo == 1)
1119 continue;
1120
1121 // Skip passthru op. It should be the first operand after the defs.
1122 if (OpNo == MI->getNumExplicitDefs() && MO.isReg() && MO.isTied()) {
1123 assert(MCID.getOperandConstraint(OpNo, MCOI::TIED_TO) == 0 &&
1124 "Expected tied to first def.");
1125 const MCInstrDesc &OutMCID = TII->get(Opcode: OutMI.getOpcode());
1126 // Skip if the next operand in OutMI is not supposed to be tied. Unless it
1127 // is a _TIED instruction.
1128 if (OutMCID.getOperandConstraint(OpNum: OutMI.getNumOperands(), Constraint: MCOI::TIED_TO) <
1129 0 &&
1130 !RISCVII::isTiedPseudo(TSFlags))
1131 continue;
1132 }
1133
1134 MCOperand MCOp;
1135 switch (MO.getType()) {
1136 default:
1137 llvm_unreachable("Unknown operand type");
1138 case MachineOperand::MO_Register: {
1139 Register Reg = MO.getReg();
1140
1141 if (RISCV::VRM2RegClass.contains(Reg) ||
1142 RISCV::VRM4RegClass.contains(Reg) ||
1143 RISCV::VRM8RegClass.contains(Reg)) {
1144 Reg = TRI->getSubReg(Reg, Idx: RISCV::sub_vrm1_0);
1145 assert(Reg && "Subregister does not exist");
1146 } else if (RISCV::FPR16RegClass.contains(Reg)) {
1147 Reg =
1148 TRI->getMatchingSuperReg(Reg, SubIdx: RISCV::sub_16, RC: &RISCV::FPR32RegClass);
1149 assert(Reg && "Subregister does not exist");
1150 } else if (RISCV::FPR64RegClass.contains(Reg)) {
1151 Reg = TRI->getSubReg(Reg, Idx: RISCV::sub_32);
1152 assert(Reg && "Superregister does not exist");
1153 } else if (RISCV::VRN2M1RegClass.contains(Reg) ||
1154 RISCV::VRN2M2RegClass.contains(Reg) ||
1155 RISCV::VRN2M4RegClass.contains(Reg) ||
1156 RISCV::VRN3M1RegClass.contains(Reg) ||
1157 RISCV::VRN3M2RegClass.contains(Reg) ||
1158 RISCV::VRN4M1RegClass.contains(Reg) ||
1159 RISCV::VRN4M2RegClass.contains(Reg) ||
1160 RISCV::VRN5M1RegClass.contains(Reg) ||
1161 RISCV::VRN6M1RegClass.contains(Reg) ||
1162 RISCV::VRN7M1RegClass.contains(Reg) ||
1163 RISCV::VRN8M1RegClass.contains(Reg)) {
1164 Reg = TRI->getSubReg(Reg, Idx: RISCV::sub_vrm1_0);
1165 assert(Reg && "Subregister does not exist");
1166 }
1167
1168 MCOp = MCOperand::createReg(Reg);
1169 break;
1170 }
1171 case MachineOperand::MO_Immediate:
1172 MCOp = MCOperand::createImm(Val: MO.getImm());
1173 break;
1174 }
1175 OutMI.addOperand(Op: MCOp);
1176 }
1177
1178 // Unmasked pseudo instructions need to append dummy mask operand to
1179 // V instructions. All V instructions are modeled as the masked version.
1180 const MCInstrDesc &OutMCID = TII->get(Opcode: OutMI.getOpcode());
1181 if (OutMI.getNumOperands() < OutMCID.getNumOperands()) {
1182 assert(OutMCID.operands()[OutMI.getNumOperands()].OperandType ==
1183 RISCVOp::OPERAND_VMASK &&
1184 "Expected only mask operand to be missing");
1185 OutMI.addOperand(Op: MCOperand::createReg(Reg: RISCV::NoRegister));
1186 }
1187
1188 assert(OutMI.getNumOperands() == OutMCID.getNumOperands());
1189 return true;
1190}
1191
1192void RISCVAsmPrinter::lowerToMCInst(const MachineInstr *MI, MCInst &OutMI) {
1193 if (lowerRISCVVMachineInstrToMCInst(MI, OutMI, STI))
1194 return;
1195
1196 OutMI.setOpcode(MI->getOpcode());
1197
1198 for (const MachineOperand &MO : MI->operands()) {
1199 MCOperand MCOp;
1200 if (lowerOperand(MO, MCOp))
1201 OutMI.addOperand(Op: MCOp);
1202 }
1203}
1204
1205void RISCVAsmPrinter::emitMachineConstantPoolValue(
1206 MachineConstantPoolValue *MCPV) {
1207 auto *RCPV = static_cast<RISCVConstantPoolValue *>(MCPV);
1208 MCSymbol *MCSym;
1209
1210 if (RCPV->isGlobalValue()) {
1211 auto *GV = RCPV->getGlobalValue();
1212 MCSym = getSymbol(GV);
1213 } else {
1214 assert(RCPV->isExtSymbol() && "unrecognized constant pool type");
1215 auto Sym = RCPV->getSymbol();
1216 MCSym = GetExternalSymbolSymbol(Sym);
1217 }
1218
1219 const MCExpr *Expr = MCSymbolRefExpr::create(Symbol: MCSym, Ctx&: OutContext);
1220 uint64_t Size = getDataLayout().getTypeAllocSize(Ty: RCPV->getType());
1221 OutStreamer->emitValue(Value: Expr, Size);
1222}
1223
1224char RISCVAsmPrinter::ID = 0;
1225
1226INITIALIZE_PASS(RISCVAsmPrinter, "riscv-asm-printer", "RISC-V Assembly Printer",
1227 false, false)
1228