1//===-- SparcFrameLowering.cpp - Sparc Frame Information ------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Sparc implementation of TargetFrameLowering class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "SparcFrameLowering.h"
14#include "SparcInstrInfo.h"
15#include "SparcMachineFunctionInfo.h"
16#include "SparcSubtarget.h"
17#include "llvm/CodeGen/CFIInstBuilder.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineModuleInfo.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23
24using namespace llvm;
25
26SparcFrameLowering::SparcFrameLowering(const SparcSubtarget &ST)
27 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
28 ST.is64Bit() ? Align(16) : Align(8), 0,
29 ST.is64Bit() ? Align(16) : Align(8),
30 /*StackRealignable=*/false) {}
31
32void SparcFrameLowering::emitSPAdjustment(MachineFunction &MF,
33 MachineBasicBlock &MBB,
34 MachineBasicBlock::iterator MBBI,
35 int NumBytes,
36 unsigned ADDrr,
37 unsigned ADDri) const {
38
39 DebugLoc dl;
40 const SparcInstrInfo &TII =
41 *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
42
43 if (NumBytes >= -4096 && NumBytes < 4096) {
44 BuildMI(BB&: MBB, I: MBBI, MIMD: dl, MCID: TII.get(Opcode: ADDri), DestReg: SP::O6)
45 .addReg(RegNo: SP::O6).addImm(Val: NumBytes);
46 return;
47 }
48
49 // Emit this the hard way. This clobbers G1 which we always know is
50 // available here.
51 if (NumBytes >= 0) {
52 // Emit nonnegative numbers with sethi + or.
53 // sethi %hi(NumBytes), %g1
54 // or %g1, %lo(NumBytes), %g1
55 // add %sp, %g1, %sp
56 BuildMI(BB&: MBB, I: MBBI, MIMD: dl, MCID: TII.get(Opcode: SP::SETHIi), DestReg: SP::G1)
57 .addImm(Val: HI22(imm: NumBytes));
58 BuildMI(BB&: MBB, I: MBBI, MIMD: dl, MCID: TII.get(Opcode: SP::ORri), DestReg: SP::G1)
59 .addReg(RegNo: SP::G1).addImm(Val: LO10(imm: NumBytes));
60 BuildMI(BB&: MBB, I: MBBI, MIMD: dl, MCID: TII.get(Opcode: ADDrr), DestReg: SP::O6)
61 .addReg(RegNo: SP::O6).addReg(RegNo: SP::G1);
62 return ;
63 }
64
65 // Emit negative numbers with sethi + xor.
66 // sethi %hix(NumBytes), %g1
67 // xor %g1, %lox(NumBytes), %g1
68 // add %sp, %g1, %sp
69 BuildMI(BB&: MBB, I: MBBI, MIMD: dl, MCID: TII.get(Opcode: SP::SETHIi), DestReg: SP::G1)
70 .addImm(Val: HIX22(imm: NumBytes));
71 BuildMI(BB&: MBB, I: MBBI, MIMD: dl, MCID: TII.get(Opcode: SP::XORri), DestReg: SP::G1)
72 .addReg(RegNo: SP::G1).addImm(Val: LOX10(imm: NumBytes));
73 BuildMI(BB&: MBB, I: MBBI, MIMD: dl, MCID: TII.get(Opcode: ADDrr), DestReg: SP::O6)
74 .addReg(RegNo: SP::O6).addReg(RegNo: SP::G1);
75}
76
77void SparcFrameLowering::emitPrologue(MachineFunction &MF,
78 MachineBasicBlock &MBB) const {
79 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
80
81 assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
82 MachineFrameInfo &MFI = MF.getFrameInfo();
83 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
84 MachineBasicBlock::iterator MBBI = MBB.begin();
85
86 // Get the number of bytes to allocate from the FrameInfo
87 int NumBytes = (int) MFI.getStackSize();
88
89 unsigned SAVEri = SP::SAVEri;
90 unsigned SAVErr = SP::SAVErr;
91 if (FuncInfo->isLeafProc()) {
92 if (NumBytes == 0)
93 return;
94 SAVEri = SP::ADDri;
95 SAVErr = SP::ADDrr;
96 }
97
98 // The SPARC ABI is a bit odd in that it requires a reserved 92-byte
99 // (128 in v9) area in the user's stack, starting at %sp. Thus, the
100 // first part of the stack that can actually be used is located at
101 // %sp + 92.
102 //
103 // We therefore need to add that offset to the total stack size
104 // after all the stack objects are placed by
105 // PrologEpilogInserter calculateFrameObjectOffsets. However, since the stack needs to be
106 // aligned *after* the extra size is added, we need to disable
107 // calculateFrameObjectOffsets's built-in stack alignment, by having
108 // targetHandlesStackFrameRounding return true.
109
110
111 // Add the extra call frame stack size, if needed. (This is the same
112 // code as in PrologEpilogInserter, but also gets disabled by
113 // targetHandlesStackFrameRounding)
114 if (MFI.adjustsStack() && hasReservedCallFrame(MF))
115 NumBytes += MFI.getMaxCallFrameSize();
116
117 // Adds the SPARC subtarget-specific spill area to the stack
118 // size. Also ensures target-required alignment.
119 NumBytes = Subtarget.getAdjustedFrameSize(stackSize: NumBytes);
120
121 // Finally, ensure that the size is sufficiently aligned for the
122 // data on the stack.
123 NumBytes = alignTo(Size: NumBytes, A: MFI.getMaxAlign());
124
125 // Update stack size with corrected value.
126 MFI.setStackSize(NumBytes);
127
128 emitSPAdjustment(MF, MBB, MBBI, NumBytes: -NumBytes, ADDrr: SAVErr, ADDri: SAVEri);
129
130 if (MF.needsFrameMoves()) {
131 CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::NoFlags);
132 CFIBuilder.buildDefCFARegister(Reg: SP::I6);
133 CFIBuilder.buildWindowSave();
134 CFIBuilder.buildRegister(Reg1: SP::O7, Reg2: SP::I7);
135 }
136}
137
138MachineBasicBlock::iterator SparcFrameLowering::
139eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
140 MachineBasicBlock::iterator I) const {
141 if (!hasReservedCallFrame(MF)) {
142 MachineInstr &MI = *I;
143 int Size = MI.getOperand(i: 0).getImm();
144 if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
145 Size = -Size;
146
147 if (Size)
148 emitSPAdjustment(MF, MBB, MBBI: I, NumBytes: Size, ADDrr: SP::ADDrr, ADDri: SP::ADDri);
149 }
150 return MBB.erase(I);
151}
152
153
154void SparcFrameLowering::emitEpilogue(MachineFunction &MF,
155 MachineBasicBlock &MBB) const {
156 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
157 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
158 const SparcInstrInfo &TII =
159 *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
160 DebugLoc dl = MBBI->getDebugLoc();
161 assert((MBBI->getOpcode() == SP::RETL || MBBI->getOpcode() == SP::TAIL_CALL ||
162 MBBI->getOpcode() == SP::TAIL_CALLri) &&
163 "Can only put epilog before 'retl' or 'tail_call' instruction!");
164 if (!FuncInfo->isLeafProc()) {
165 BuildMI(BB&: MBB, I: MBBI, MIMD: dl, MCID: TII.get(Opcode: SP::RESTORErr), DestReg: SP::G0).addReg(RegNo: SP::G0)
166 .addReg(RegNo: SP::G0);
167 return;
168 }
169 MachineFrameInfo &MFI = MF.getFrameInfo();
170
171 int NumBytes = (int) MFI.getStackSize();
172 if (NumBytes != 0)
173 emitSPAdjustment(MF, MBB, MBBI, NumBytes, ADDrr: SP::ADDrr, ADDri: SP::ADDri);
174
175 // Preserve return address in %o7
176 if (MBBI->getOpcode() == SP::TAIL_CALL) {
177 MBB.addLiveIn(PhysReg: SP::O7);
178 BuildMI(BB&: MBB, I: MBBI, MIMD: dl, MCID: TII.get(Opcode: SP::ORrr), DestReg: SP::G1)
179 .addReg(RegNo: SP::G0)
180 .addReg(RegNo: SP::O7);
181 BuildMI(BB&: MBB, I: MBBI, MIMD: dl, MCID: TII.get(Opcode: SP::ORrr), DestReg: SP::O7)
182 .addReg(RegNo: SP::G0)
183 .addReg(RegNo: SP::G1);
184 }
185}
186
187bool SparcFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
188 // Reserve call frame if there are no variable sized objects on the stack.
189 return !MF.getFrameInfo().hasVarSizedObjects();
190}
191
192// hasFPImpl - Return true if the specified function should have a dedicated
193// frame pointer register. This is true if the function has variable sized
194// allocas or if frame pointer elimination is disabled.
195bool SparcFrameLowering::hasFPImpl(const MachineFunction &MF) const {
196 const MachineFrameInfo &MFI = MF.getFrameInfo();
197 return MF.disableFramePointerElim() || MFI.hasVarSizedObjects() ||
198 MFI.isFrameAddressTaken();
199}
200
201StackOffset
202SparcFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
203 Register &FrameReg) const {
204 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
205 const MachineFrameInfo &MFI = MF.getFrameInfo();
206 const SparcRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
207 const SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
208 bool isFixed = MFI.isFixedObjectIndex(ObjectIdx: FI);
209
210 // Addressable stack objects are accessed using neg. offsets from
211 // %fp, or positive offsets from %sp.
212 bool UseFP;
213
214 // Sparc uses FP-based references in general, even when "hasFP" is
215 // false. That function is rather a misnomer, because %fp is
216 // actually always available, unless isLeafProc.
217 if (FuncInfo->isLeafProc()) {
218 // If there's a leaf proc, all offsets need to be %sp-based,
219 // because we haven't caused %fp to actually point to our frame.
220 UseFP = false;
221 } else if (isFixed) {
222 // Otherwise, argument access should always use %fp.
223 UseFP = true;
224 } else {
225 // Finally, default to using %fp.
226 UseFP = true;
227 }
228
229 int64_t FrameOffset = MF.getFrameInfo().getObjectOffset(ObjectIdx: FI) +
230 Subtarget.getStackPointerBias();
231
232 if (UseFP) {
233 FrameReg = RegInfo->getFrameRegister(MF);
234 return StackOffset::getFixed(Fixed: FrameOffset);
235 } else {
236 FrameReg = SP::O6; // %sp
237 return StackOffset::getFixed(Fixed: FrameOffset + MF.getFrameInfo().getStackSize());
238 }
239}
240
241[[maybe_unused]] static bool verifyLeafProcRegUse(MachineRegisterInfo *MRI) {
242
243 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg)
244 if (MRI->isPhysRegUsed(PhysReg: reg))
245 return false;
246
247 for (unsigned reg = SP::L0; reg <= SP::L7; ++reg)
248 if (MRI->isPhysRegUsed(PhysReg: reg))
249 return false;
250
251 return true;
252}
253
254bool SparcFrameLowering::isLeafProc(MachineFunction &MF) const
255{
256
257 MachineRegisterInfo &MRI = MF.getRegInfo();
258 MachineFrameInfo &MFI = MF.getFrameInfo();
259
260 return !(MFI.hasCalls() // has calls
261 || MRI.isPhysRegUsed(PhysReg: SP::L0) // Too many registers needed
262 || MRI.isPhysRegUsed(PhysReg: SP::O6) // %sp is used
263 || hasFP(MF) // need %fp
264 || MF.hasInlineAsm()); // has inline assembly
265}
266
267void SparcFrameLowering::remapRegsForLeafProc(MachineFunction &MF) const {
268 MachineRegisterInfo &MRI = MF.getRegInfo();
269 // Remap %i[0-7] to %o[0-7].
270 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
271 if (!MRI.isPhysRegUsed(PhysReg: reg))
272 continue;
273
274 unsigned mapped_reg = reg - SP::I0 + SP::O0;
275
276 // Replace I register with O register.
277 MRI.replaceRegWith(FromReg: reg, ToReg: mapped_reg);
278
279 // Also replace register pair super-registers.
280 if ((reg - SP::I0) % 2 == 0) {
281 unsigned preg = (reg - SP::I0) / 2 + SP::I0_I1;
282 unsigned mapped_preg = preg - SP::I0_I1 + SP::O0_O1;
283 MRI.replaceRegWith(FromReg: preg, ToReg: mapped_preg);
284 }
285 }
286
287 // Rewrite MBB's Live-ins.
288 for (MachineBasicBlock &MBB : MF) {
289 for (unsigned reg = SP::I0_I1; reg <= SP::I6_I7; ++reg) {
290 if (!MBB.isLiveIn(Reg: reg))
291 continue;
292 MBB.removeLiveIn(Reg: reg);
293 MBB.addLiveIn(PhysReg: reg - SP::I0_I1 + SP::O0_O1);
294 }
295 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
296 if (!MBB.isLiveIn(Reg: reg))
297 continue;
298 MBB.removeLiveIn(Reg: reg);
299 MBB.addLiveIn(PhysReg: reg - SP::I0 + SP::O0);
300 }
301 }
302
303 assert(verifyLeafProcRegUse(&MRI));
304#ifdef EXPENSIVE_CHECKS
305 MF.verify(0, "After LeafProc Remapping");
306#endif
307}
308
309void SparcFrameLowering::determineCalleeSaves(MachineFunction &MF,
310 BitVector &SavedRegs,
311 RegScavenger *RS) const {
312 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
313 const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
314 if (!Subtarget.getCLOpts().disable_sparc_leaf_proc && isLeafProc(MF)) {
315 SparcMachineFunctionInfo *MFI = MF.getInfo<SparcMachineFunctionInfo>();
316 MFI->setLeafProc(true);
317
318 remapRegsForLeafProc(MF);
319 }
320}
321