1//===- X86AvoidStoreForwardingBlocks.cpp - Avoid HW Store Forward Block ---===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// If a load follows a store and reloads data that the store has written to
10// memory, Intel microarchitectures can in many cases forward the data directly
11// from the store to the load, This "store forwarding" saves cycles by enabling
12// the load to directly obtain the data instead of accessing the data from
13// cache or memory.
14// A "store forward block" occurs in cases that a store cannot be forwarded to
15// the load. The most typical case of store forward block on Intel Core
16// microarchitecture that a small store cannot be forwarded to a large load.
17// The estimated penalty for a store forward block is ~13 cycles.
18//
19// This pass tries to recognize and handle cases where "store forward block"
20// is created by the compiler when lowering memcpy calls to a sequence
21// of a load and a store.
22//
23// The pass currently only handles cases where memcpy is lowered to
24// XMM/YMM registers, it tries to break the memcpy into smaller copies.
25// breaking the memcpy should be possible since there is no atomicity
26// guarantee for loads and stores to XMM/YMM.
27//
28// It could be better for performance to solve the problem by loading
29// to XMM/YMM then inserting the partial store before storing back from XMM/YMM
30// to memory, but this will result in a more conservative optimization since it
31// requires we prove that all memory accesses between the blocking store and the
32// load must alias/don't alias before we can move the store, whereas the
33// transformation done here is correct regardless to other memory accesses.
34//===----------------------------------------------------------------------===//
35
36#include "X86.h"
37#include "X86InstrInfo.h"
38#include "X86Subtarget.h"
39#include "llvm/Analysis/AliasAnalysis.h"
40#include "llvm/CodeGen/MachineBasicBlock.h"
41#include "llvm/CodeGen/MachineFunction.h"
42#include "llvm/CodeGen/MachineFunctionPass.h"
43#include "llvm/CodeGen/MachineInstr.h"
44#include "llvm/CodeGen/MachineInstrBuilder.h"
45#include "llvm/CodeGen/MachineOperand.h"
46#include "llvm/CodeGen/MachineRegisterInfo.h"
47#include "llvm/IR/DebugLoc.h"
48#include "llvm/IR/Function.h"
49#include "llvm/InitializePasses.h"
50#include "llvm/MC/MCInstrDesc.h"
51
52using namespace llvm;
53
54#define DEBUG_TYPE "x86-avoid-sfb"
55
56static cl::opt<bool> DisableX86AvoidStoreForwardBlocks(
57 "x86-disable-avoid-SFB", cl::Hidden,
58 cl::desc("X86: Disable Store Forwarding Blocks fixup."), cl::init(Val: false));
59
60static cl::opt<unsigned> X86AvoidSFBInspectionLimit(
61 "x86-sfb-inspection-limit",
62 cl::desc("X86: Number of instructions backward to "
63 "inspect for store forwarding blocks."),
64 cl::init(Val: 20), cl::Hidden);
65
66namespace {
67
68using DisplacementSizeMap = std::map<int64_t, unsigned>;
69
70class X86AvoidSFBImpl {
71public:
72 X86AvoidSFBImpl(AliasAnalysis *AA) : AA(AA) {};
73 bool runOnMachineFunction(MachineFunction &MF);
74
75private:
76 MachineRegisterInfo *MRI = nullptr;
77 const X86InstrInfo *TII = nullptr;
78 const X86RegisterInfo *TRI = nullptr;
79 SmallVector<std::pair<MachineInstr *, MachineInstr *>, 2>
80 BlockedLoadsStoresPairs;
81 SmallVector<MachineInstr *, 2> ForRemoval;
82 AliasAnalysis *AA = nullptr;
83
84 /// Returns couples of Load then Store to memory which look
85 /// like a memcpy.
86 void findPotentiallylBlockedCopies(MachineFunction &MF);
87 /// Break the memcpy's load and store into smaller copies
88 /// such that each memory load that was blocked by a smaller store
89 /// would now be copied separately.
90 void breakBlockedCopies(MachineInstr *LoadInst, MachineInstr *StoreInst,
91 const DisplacementSizeMap &BlockingStoresDispSizeMap);
92 /// Break a copy of size Size to smaller copies.
93 void buildCopies(int Size, MachineInstr *LoadInst, int64_t LdDispImm,
94 MachineInstr *StoreInst, int64_t StDispImm,
95 int64_t LMMOffset, int64_t SMMOffset);
96
97 void buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode, int64_t LoadDisp,
98 MachineInstr *StoreInst, unsigned NStoreOpcode,
99 int64_t StoreDisp, unsigned Size, int64_t LMMOffset,
100 int64_t SMMOffset);
101
102 bool alias(const MachineMemOperand &Op1, const MachineMemOperand &Op2) const;
103
104 unsigned getRegSizeInBytes(MachineInstr *Inst);
105};
106
107class X86AvoidSFBLegacy : public MachineFunctionPass {
108public:
109 static char ID;
110 X86AvoidSFBLegacy() : MachineFunctionPass(ID) {}
111
112 StringRef getPassName() const override {
113 return "X86 Avoid Store Forwarding Blocks";
114 }
115
116 bool runOnMachineFunction(MachineFunction &MF) override;
117
118 void getAnalysisUsage(AnalysisUsage &AU) const override {
119 MachineFunctionPass::getAnalysisUsage(AU);
120 AU.addRequired<AAResultsWrapperPass>();
121 }
122};
123
124} // end anonymous namespace
125
126char X86AvoidSFBLegacy::ID = 0;
127
128INITIALIZE_PASS_BEGIN(X86AvoidSFBLegacy, DEBUG_TYPE, "Machine code sinking",
129 false, false)
130INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
131INITIALIZE_PASS_END(X86AvoidSFBLegacy, DEBUG_TYPE, "Machine code sinking",
132 false, false)
133
134FunctionPass *llvm::createX86AvoidStoreForwardingBlocksLegacyPass() {
135 return new X86AvoidSFBLegacy();
136}
137
138static bool isXMMLoadOpcode(unsigned Opcode) {
139 return Opcode == X86::MOVUPSrm || Opcode == X86::MOVAPSrm ||
140 Opcode == X86::VMOVUPSrm || Opcode == X86::VMOVAPSrm ||
141 Opcode == X86::VMOVUPDrm || Opcode == X86::VMOVAPDrm ||
142 Opcode == X86::VMOVDQUrm || Opcode == X86::VMOVDQArm ||
143 Opcode == X86::VMOVUPSZ128rm || Opcode == X86::VMOVAPSZ128rm ||
144 Opcode == X86::VMOVUPDZ128rm || Opcode == X86::VMOVAPDZ128rm ||
145 Opcode == X86::VMOVDQU64Z128rm || Opcode == X86::VMOVDQA64Z128rm ||
146 Opcode == X86::VMOVDQU32Z128rm || Opcode == X86::VMOVDQA32Z128rm;
147}
148static bool isYMMLoadOpcode(unsigned Opcode) {
149 return Opcode == X86::VMOVUPSYrm || Opcode == X86::VMOVAPSYrm ||
150 Opcode == X86::VMOVUPDYrm || Opcode == X86::VMOVAPDYrm ||
151 Opcode == X86::VMOVDQUYrm || Opcode == X86::VMOVDQAYrm ||
152 Opcode == X86::VMOVUPSZ256rm || Opcode == X86::VMOVAPSZ256rm ||
153 Opcode == X86::VMOVUPDZ256rm || Opcode == X86::VMOVAPDZ256rm ||
154 Opcode == X86::VMOVDQU64Z256rm || Opcode == X86::VMOVDQA64Z256rm ||
155 Opcode == X86::VMOVDQU32Z256rm || Opcode == X86::VMOVDQA32Z256rm;
156}
157
158static bool isPotentialBlockedMemCpyLd(unsigned Opcode) {
159 return isXMMLoadOpcode(Opcode) || isYMMLoadOpcode(Opcode);
160}
161
162static bool isPotentialBlockedMemCpyPair(unsigned LdOpcode, unsigned StOpcode) {
163 switch (LdOpcode) {
164 case X86::MOVUPSrm:
165 case X86::MOVAPSrm:
166 return StOpcode == X86::MOVUPSmr || StOpcode == X86::MOVAPSmr;
167 case X86::VMOVUPSrm:
168 case X86::VMOVAPSrm:
169 return StOpcode == X86::VMOVUPSmr || StOpcode == X86::VMOVAPSmr;
170 case X86::VMOVUPDrm:
171 case X86::VMOVAPDrm:
172 return StOpcode == X86::VMOVUPDmr || StOpcode == X86::VMOVAPDmr;
173 case X86::VMOVDQUrm:
174 case X86::VMOVDQArm:
175 return StOpcode == X86::VMOVDQUmr || StOpcode == X86::VMOVDQAmr;
176 case X86::VMOVUPSZ128rm:
177 case X86::VMOVAPSZ128rm:
178 return StOpcode == X86::VMOVUPSZ128mr || StOpcode == X86::VMOVAPSZ128mr;
179 case X86::VMOVUPDZ128rm:
180 case X86::VMOVAPDZ128rm:
181 return StOpcode == X86::VMOVUPDZ128mr || StOpcode == X86::VMOVAPDZ128mr;
182 case X86::VMOVUPSYrm:
183 case X86::VMOVAPSYrm:
184 return StOpcode == X86::VMOVUPSYmr || StOpcode == X86::VMOVAPSYmr;
185 case X86::VMOVUPDYrm:
186 case X86::VMOVAPDYrm:
187 return StOpcode == X86::VMOVUPDYmr || StOpcode == X86::VMOVAPDYmr;
188 case X86::VMOVDQUYrm:
189 case X86::VMOVDQAYrm:
190 return StOpcode == X86::VMOVDQUYmr || StOpcode == X86::VMOVDQAYmr;
191 case X86::VMOVUPSZ256rm:
192 case X86::VMOVAPSZ256rm:
193 return StOpcode == X86::VMOVUPSZ256mr || StOpcode == X86::VMOVAPSZ256mr;
194 case X86::VMOVUPDZ256rm:
195 case X86::VMOVAPDZ256rm:
196 return StOpcode == X86::VMOVUPDZ256mr || StOpcode == X86::VMOVAPDZ256mr;
197 case X86::VMOVDQU64Z128rm:
198 case X86::VMOVDQA64Z128rm:
199 return StOpcode == X86::VMOVDQU64Z128mr || StOpcode == X86::VMOVDQA64Z128mr;
200 case X86::VMOVDQU32Z128rm:
201 case X86::VMOVDQA32Z128rm:
202 return StOpcode == X86::VMOVDQU32Z128mr || StOpcode == X86::VMOVDQA32Z128mr;
203 case X86::VMOVDQU64Z256rm:
204 case X86::VMOVDQA64Z256rm:
205 return StOpcode == X86::VMOVDQU64Z256mr || StOpcode == X86::VMOVDQA64Z256mr;
206 case X86::VMOVDQU32Z256rm:
207 case X86::VMOVDQA32Z256rm:
208 return StOpcode == X86::VMOVDQU32Z256mr || StOpcode == X86::VMOVDQA32Z256mr;
209 default:
210 return false;
211 }
212}
213
214static bool isPotentialBlockingStoreInst(unsigned Opcode, unsigned LoadOpcode) {
215 bool PBlock = false;
216 PBlock |= Opcode == X86::MOV64mr || Opcode == X86::MOV64mi32 ||
217 Opcode == X86::MOV32mr || Opcode == X86::MOV32mi ||
218 Opcode == X86::MOV16mr || Opcode == X86::MOV16mi ||
219 Opcode == X86::MOV8mr || Opcode == X86::MOV8mi;
220 if (isYMMLoadOpcode(Opcode: LoadOpcode))
221 PBlock |= Opcode == X86::VMOVUPSmr || Opcode == X86::VMOVAPSmr ||
222 Opcode == X86::VMOVUPDmr || Opcode == X86::VMOVAPDmr ||
223 Opcode == X86::VMOVDQUmr || Opcode == X86::VMOVDQAmr ||
224 Opcode == X86::VMOVUPSZ128mr || Opcode == X86::VMOVAPSZ128mr ||
225 Opcode == X86::VMOVUPDZ128mr || Opcode == X86::VMOVAPDZ128mr ||
226 Opcode == X86::VMOVDQU64Z128mr ||
227 Opcode == X86::VMOVDQA64Z128mr ||
228 Opcode == X86::VMOVDQU32Z128mr || Opcode == X86::VMOVDQA32Z128mr;
229 return PBlock;
230}
231
232static const int MOV128SZ = 16;
233static const int MOV64SZ = 8;
234static const int MOV32SZ = 4;
235static const int MOV16SZ = 2;
236static const int MOV8SZ = 1;
237
238static unsigned getYMMtoXMMLoadOpcode(unsigned LoadOpcode) {
239 switch (LoadOpcode) {
240 case X86::VMOVUPSYrm:
241 case X86::VMOVAPSYrm:
242 return X86::VMOVUPSrm;
243 case X86::VMOVUPDYrm:
244 case X86::VMOVAPDYrm:
245 return X86::VMOVUPDrm;
246 case X86::VMOVDQUYrm:
247 case X86::VMOVDQAYrm:
248 return X86::VMOVDQUrm;
249 case X86::VMOVUPSZ256rm:
250 case X86::VMOVAPSZ256rm:
251 return X86::VMOVUPSZ128rm;
252 case X86::VMOVUPDZ256rm:
253 case X86::VMOVAPDZ256rm:
254 return X86::VMOVUPDZ128rm;
255 case X86::VMOVDQU64Z256rm:
256 case X86::VMOVDQA64Z256rm:
257 return X86::VMOVDQU64Z128rm;
258 case X86::VMOVDQU32Z256rm:
259 case X86::VMOVDQA32Z256rm:
260 return X86::VMOVDQU32Z128rm;
261 default:
262 llvm_unreachable("Unexpected Load Instruction Opcode");
263 }
264 return 0;
265}
266
267static unsigned getYMMtoXMMStoreOpcode(unsigned StoreOpcode) {
268 switch (StoreOpcode) {
269 case X86::VMOVUPSYmr:
270 case X86::VMOVAPSYmr:
271 return X86::VMOVUPSmr;
272 case X86::VMOVUPDYmr:
273 case X86::VMOVAPDYmr:
274 return X86::VMOVUPDmr;
275 case X86::VMOVDQUYmr:
276 case X86::VMOVDQAYmr:
277 return X86::VMOVDQUmr;
278 case X86::VMOVUPSZ256mr:
279 case X86::VMOVAPSZ256mr:
280 return X86::VMOVUPSZ128mr;
281 case X86::VMOVUPDZ256mr:
282 case X86::VMOVAPDZ256mr:
283 return X86::VMOVUPDZ128mr;
284 case X86::VMOVDQU64Z256mr:
285 case X86::VMOVDQA64Z256mr:
286 return X86::VMOVDQU64Z128mr;
287 case X86::VMOVDQU32Z256mr:
288 case X86::VMOVDQA32Z256mr:
289 return X86::VMOVDQU32Z128mr;
290 default:
291 llvm_unreachable("Unexpected Load Instruction Opcode");
292 }
293 return 0;
294}
295
296static int getAddrOffset(const MachineInstr *MI) {
297 const MCInstrDesc &Descl = MI->getDesc();
298 int AddrOffset = X86II::getMemoryOperandNo(TSFlags: Descl.TSFlags);
299 assert(AddrOffset != -1 && "Expected Memory Operand");
300 AddrOffset += X86II::getOperandBias(Desc: Descl);
301 return AddrOffset;
302}
303
304static MachineOperand &getBaseOperand(MachineInstr *MI) {
305 int AddrOffset = getAddrOffset(MI);
306 return MI->getOperand(i: AddrOffset + X86::AddrBaseReg);
307}
308
309static MachineOperand &getDispOperand(MachineInstr *MI) {
310 int AddrOffset = getAddrOffset(MI);
311 return MI->getOperand(i: AddrOffset + X86::AddrDisp);
312}
313
314// Relevant addressing modes contain only base register and immediate
315// displacement or frameindex and immediate displacement.
316// TODO: Consider expanding to other addressing modes in the future
317static bool isRelevantAddressingMode(MachineInstr *MI) {
318 int AddrOffset = getAddrOffset(MI);
319 const MachineOperand &Base = getBaseOperand(MI);
320 const MachineOperand &Disp = getDispOperand(MI);
321 const MachineOperand &Scale = MI->getOperand(i: AddrOffset + X86::AddrScaleAmt);
322 const MachineOperand &Index = MI->getOperand(i: AddrOffset + X86::AddrIndexReg);
323 const MachineOperand &Segment = MI->getOperand(i: AddrOffset + X86::AddrSegmentReg);
324
325 if (!((Base.isReg() && Base.getReg() != X86::NoRegister) || Base.isFI()))
326 return false;
327 if (!Disp.isImm())
328 return false;
329 if (Scale.getImm() != 1)
330 return false;
331 if (!(Index.isReg() && Index.getReg() == X86::NoRegister))
332 return false;
333 if (!(Segment.isReg() && Segment.getReg() == X86::NoRegister))
334 return false;
335 return true;
336}
337
338// Collect potentially blocking stores.
339// Limit the number of instructions backwards we want to inspect
340// since the effect of store block won't be visible if the store
341// and load instructions have enough instructions in between to
342// keep the core busy.
343static SmallVector<MachineInstr *, 2>
344findPotentialBlockers(MachineInstr *LoadInst) {
345 SmallVector<MachineInstr *, 2> PotentialBlockers;
346 unsigned BlockCount = 0;
347 const unsigned InspectionLimit = X86AvoidSFBInspectionLimit;
348 for (auto PBInst = std::next(x: MachineBasicBlock::reverse_iterator(LoadInst)),
349 E = LoadInst->getParent()->rend();
350 PBInst != E; ++PBInst) {
351 if (PBInst->isMetaInstruction())
352 continue;
353 BlockCount++;
354 if (BlockCount >= InspectionLimit)
355 break;
356 MachineInstr &MI = *PBInst;
357 if (MI.getDesc().isCall())
358 return PotentialBlockers;
359 PotentialBlockers.push_back(Elt: &MI);
360 }
361 // If we didn't get to the instructions limit try predecessing blocks.
362 // Ideally we should traverse the predecessor blocks in depth with some
363 // coloring algorithm, but for now let's just look at the first order
364 // predecessors.
365 if (BlockCount < InspectionLimit) {
366 MachineBasicBlock *MBB = LoadInst->getParent();
367 int LimitLeft = InspectionLimit - BlockCount;
368 for (MachineBasicBlock *PMBB : MBB->predecessors()) {
369 int PredCount = 0;
370 for (MachineInstr &PBInst : llvm::reverse(C&: *PMBB)) {
371 if (PBInst.isMetaInstruction())
372 continue;
373 PredCount++;
374 if (PredCount >= LimitLeft)
375 break;
376 if (PBInst.getDesc().isCall())
377 break;
378 PotentialBlockers.push_back(Elt: &PBInst);
379 }
380 }
381 }
382 return PotentialBlockers;
383}
384
385void X86AvoidSFBImpl::buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode,
386 int64_t LoadDisp, MachineInstr *StoreInst,
387 unsigned NStoreOpcode, int64_t StoreDisp,
388 unsigned Size, int64_t LMMOffset,
389 int64_t SMMOffset) {
390 MachineOperand &LoadBase = getBaseOperand(MI: LoadInst);
391 MachineOperand &StoreBase = getBaseOperand(MI: StoreInst);
392 MachineBasicBlock *MBB = LoadInst->getParent();
393 MachineMemOperand *LMMO = *LoadInst->memoperands_begin();
394 MachineMemOperand *SMMO = *StoreInst->memoperands_begin();
395
396 Register Reg1 =
397 MRI->createVirtualRegister(RegClass: TII->getRegClass(MCID: TII->get(Opcode: NLoadOpcode), OpNum: 0));
398 MachineInstr *NewLoad =
399 BuildMI(BB&: *MBB, I: LoadInst, MIMD: LoadInst->getDebugLoc(), MCID: TII->get(Opcode: NLoadOpcode),
400 DestReg: Reg1)
401 .add(MO: LoadBase)
402 .addImm(Val: 1)
403 .addReg(RegNo: X86::NoRegister)
404 .addImm(Val: LoadDisp)
405 .addReg(RegNo: X86::NoRegister)
406 .addMemOperand(
407 MMO: MBB->getParent()->getMachineMemOperand(MMO: LMMO, Offset: LMMOffset, Size));
408 if (LoadBase.isReg())
409 getBaseOperand(MI: NewLoad).setIsKill(false);
410 LLVM_DEBUG(NewLoad->dump());
411 // If the load and store are consecutive, use the loadInst location to
412 // reduce register pressure.
413 MachineInstr *StInst = StoreInst;
414 auto PrevInstrIt = prev_nodbg(It: MachineBasicBlock::instr_iterator(StoreInst),
415 Begin: MBB->instr_begin());
416 if (PrevInstrIt.getNodePtr() == LoadInst)
417 StInst = LoadInst;
418 MachineInstr *NewStore =
419 BuildMI(BB&: *MBB, I: StInst, MIMD: StInst->getDebugLoc(), MCID: TII->get(Opcode: NStoreOpcode))
420 .add(MO: StoreBase)
421 .addImm(Val: 1)
422 .addReg(RegNo: X86::NoRegister)
423 .addImm(Val: StoreDisp)
424 .addReg(RegNo: X86::NoRegister)
425 .addReg(RegNo: Reg1)
426 .addMemOperand(
427 MMO: MBB->getParent()->getMachineMemOperand(MMO: SMMO, Offset: SMMOffset, Size));
428 if (StoreBase.isReg())
429 getBaseOperand(MI: NewStore).setIsKill(false);
430 MachineOperand &StoreSrcVReg = StoreInst->getOperand(i: X86::AddrNumOperands);
431 assert(StoreSrcVReg.isReg() && "Expected virtual register");
432 NewStore->getOperand(i: X86::AddrNumOperands).setIsKill(StoreSrcVReg.isKill());
433 LLVM_DEBUG(NewStore->dump());
434}
435
436void X86AvoidSFBImpl::buildCopies(int Size, MachineInstr *LoadInst,
437 int64_t LdDispImm, MachineInstr *StoreInst,
438 int64_t StDispImm, int64_t LMMOffset,
439 int64_t SMMOffset) {
440 int LdDisp = LdDispImm;
441 int StDisp = StDispImm;
442 while (Size > 0) {
443 if ((Size - MOV128SZ >= 0) && isYMMLoadOpcode(Opcode: LoadInst->getOpcode())) {
444 Size = Size - MOV128SZ;
445 buildCopy(LoadInst, NLoadOpcode: getYMMtoXMMLoadOpcode(LoadOpcode: LoadInst->getOpcode()), LoadDisp: LdDisp,
446 StoreInst, NStoreOpcode: getYMMtoXMMStoreOpcode(StoreOpcode: StoreInst->getOpcode()),
447 StoreDisp: StDisp, Size: MOV128SZ, LMMOffset, SMMOffset);
448 LdDisp += MOV128SZ;
449 StDisp += MOV128SZ;
450 LMMOffset += MOV128SZ;
451 SMMOffset += MOV128SZ;
452 continue;
453 }
454 if (Size - MOV64SZ >= 0) {
455 Size = Size - MOV64SZ;
456 buildCopy(LoadInst, NLoadOpcode: X86::MOV64rm, LoadDisp: LdDisp, StoreInst, NStoreOpcode: X86::MOV64mr, StoreDisp: StDisp,
457 Size: MOV64SZ, LMMOffset, SMMOffset);
458 LdDisp += MOV64SZ;
459 StDisp += MOV64SZ;
460 LMMOffset += MOV64SZ;
461 SMMOffset += MOV64SZ;
462 continue;
463 }
464 if (Size - MOV32SZ >= 0) {
465 Size = Size - MOV32SZ;
466 buildCopy(LoadInst, NLoadOpcode: X86::MOV32rm, LoadDisp: LdDisp, StoreInst, NStoreOpcode: X86::MOV32mr, StoreDisp: StDisp,
467 Size: MOV32SZ, LMMOffset, SMMOffset);
468 LdDisp += MOV32SZ;
469 StDisp += MOV32SZ;
470 LMMOffset += MOV32SZ;
471 SMMOffset += MOV32SZ;
472 continue;
473 }
474 if (Size - MOV16SZ >= 0) {
475 Size = Size - MOV16SZ;
476 buildCopy(LoadInst, NLoadOpcode: X86::MOV16rm, LoadDisp: LdDisp, StoreInst, NStoreOpcode: X86::MOV16mr, StoreDisp: StDisp,
477 Size: MOV16SZ, LMMOffset, SMMOffset);
478 LdDisp += MOV16SZ;
479 StDisp += MOV16SZ;
480 LMMOffset += MOV16SZ;
481 SMMOffset += MOV16SZ;
482 continue;
483 }
484 if (Size - MOV8SZ >= 0) {
485 Size = Size - MOV8SZ;
486 buildCopy(LoadInst, NLoadOpcode: X86::MOV8rm, LoadDisp: LdDisp, StoreInst, NStoreOpcode: X86::MOV8mr, StoreDisp: StDisp,
487 Size: MOV8SZ, LMMOffset, SMMOffset);
488 LdDisp += MOV8SZ;
489 StDisp += MOV8SZ;
490 LMMOffset += MOV8SZ;
491 SMMOffset += MOV8SZ;
492 continue;
493 }
494 }
495 assert(Size == 0 && "Wrong size division");
496}
497
498static void updateKillStatus(MachineInstr *LoadInst, MachineInstr *StoreInst) {
499 MachineOperand &LoadBase = getBaseOperand(MI: LoadInst);
500 MachineOperand &StoreBase = getBaseOperand(MI: StoreInst);
501 auto *StorePrevNonDbgInstr =
502 prev_nodbg(It: MachineBasicBlock::instr_iterator(StoreInst),
503 Begin: LoadInst->getParent()->instr_begin())
504 .getNodePtr();
505 if (LoadBase.isReg()) {
506 MachineInstr *LastLoad = LoadInst->getPrevNode();
507 // If the original load and store to xmm/ymm were consecutive
508 // then the partial copies were also created in
509 // a consecutive order to reduce register pressure,
510 // and the location of the last load is before the last store.
511 if (StorePrevNonDbgInstr == LoadInst)
512 LastLoad = LoadInst->getPrevNode()->getPrevNode();
513 getBaseOperand(MI: LastLoad).setIsKill(LoadBase.isKill());
514 }
515 if (StoreBase.isReg()) {
516 MachineInstr *StInst = StoreInst;
517 if (StorePrevNonDbgInstr == LoadInst)
518 StInst = LoadInst;
519 getBaseOperand(MI: StInst->getPrevNode()).setIsKill(StoreBase.isKill());
520 }
521}
522
523bool X86AvoidSFBImpl::alias(const MachineMemOperand &Op1,
524 const MachineMemOperand &Op2) const {
525 if (!Op1.getValue() || !Op2.getValue())
526 return true;
527
528 int64_t MinOffset = std::min(a: Op1.getOffset(), b: Op2.getOffset());
529 int64_t Overlapa = Op1.getSize().getValue() + Op1.getOffset() - MinOffset;
530 int64_t Overlapb = Op2.getSize().getValue() + Op2.getOffset() - MinOffset;
531
532 return !AA->isNoAlias(
533 LocA: MemoryLocation(Op1.getValue(), Overlapa, Op1.getAAInfo()),
534 LocB: MemoryLocation(Op2.getValue(), Overlapb, Op2.getAAInfo()));
535}
536
537void X86AvoidSFBImpl::findPotentiallylBlockedCopies(MachineFunction &MF) {
538 for (auto &MBB : MF)
539 for (auto &MI : MBB) {
540 if (!isPotentialBlockedMemCpyLd(Opcode: MI.getOpcode()))
541 continue;
542 Register DefVR = MI.getOperand(i: 0).getReg();
543 if (!MRI->hasOneNonDBGUse(RegNo: DefVR))
544 continue;
545 for (MachineOperand &StoreMO :
546 llvm::make_early_inc_range(Range: MRI->use_nodbg_operands(Reg: DefVR))) {
547 MachineInstr &StoreMI = *StoreMO.getParent();
548 // Skip cases where the memcpy may overlap.
549 if (StoreMI.getParent() == MI.getParent() &&
550 isPotentialBlockedMemCpyPair(LdOpcode: MI.getOpcode(), StOpcode: StoreMI.getOpcode()) &&
551 isRelevantAddressingMode(MI: &MI) &&
552 isRelevantAddressingMode(MI: &StoreMI) &&
553 MI.hasOneMemOperand() && StoreMI.hasOneMemOperand()) {
554 if (!alias(Op1: **MI.memoperands_begin(), Op2: **StoreMI.memoperands_begin()))
555 BlockedLoadsStoresPairs.push_back(Elt: std::make_pair(x: &MI, y: &StoreMI));
556 }
557 }
558 }
559}
560
561unsigned X86AvoidSFBImpl::getRegSizeInBytes(MachineInstr *LoadInst) {
562 const auto *TRC = TII->getRegClass(MCID: TII->get(Opcode: LoadInst->getOpcode()), OpNum: 0);
563 return TRI->getRegSizeInBits(RC: *TRC) / 8;
564}
565
566void X86AvoidSFBImpl::breakBlockedCopies(
567 MachineInstr *LoadInst, MachineInstr *StoreInst,
568 const DisplacementSizeMap &BlockingStoresDispSizeMap) {
569 int64_t LdDispImm = getDispOperand(MI: LoadInst).getImm();
570 int64_t StDispImm = getDispOperand(MI: StoreInst).getImm();
571 int64_t LMMOffset = 0;
572 int64_t SMMOffset = 0;
573
574 int64_t LdDisp1 = LdDispImm;
575 int64_t LdDisp2 = 0;
576 int64_t StDisp1 = StDispImm;
577 int64_t StDisp2 = 0;
578 unsigned Size1 = 0;
579 unsigned Size2 = 0;
580 int64_t LdStDelta = StDispImm - LdDispImm;
581
582 for (auto DispSizePair : BlockingStoresDispSizeMap) {
583 LdDisp2 = DispSizePair.first;
584 StDisp2 = DispSizePair.first + LdStDelta;
585 Size2 = DispSizePair.second;
586 // Avoid copying overlapping areas.
587 if (LdDisp2 < LdDisp1) {
588 int OverlapDelta = LdDisp1 - LdDisp2;
589 LdDisp2 += OverlapDelta;
590 StDisp2 += OverlapDelta;
591 Size2 -= OverlapDelta;
592 }
593 Size1 = LdDisp2 - LdDisp1;
594
595 // Build a copy for the point until the current blocking store's
596 // displacement.
597 buildCopies(Size: Size1, LoadInst, LdDispImm: LdDisp1, StoreInst, StDispImm: StDisp1, LMMOffset,
598 SMMOffset);
599 // Build a copy for the current blocking store.
600 buildCopies(Size: Size2, LoadInst, LdDispImm: LdDisp2, StoreInst, StDispImm: StDisp2, LMMOffset: LMMOffset + Size1,
601 SMMOffset: SMMOffset + Size1);
602 LdDisp1 = LdDisp2 + Size2;
603 StDisp1 = StDisp2 + Size2;
604 LMMOffset += Size1 + Size2;
605 SMMOffset += Size1 + Size2;
606 }
607 unsigned Size3 = (LdDispImm + getRegSizeInBytes(LoadInst)) - LdDisp1;
608 buildCopies(Size: Size3, LoadInst, LdDispImm: LdDisp1, StoreInst, StDispImm: StDisp1, LMMOffset,
609 SMMOffset: LMMOffset);
610}
611
612static bool hasSameBaseOpValue(MachineInstr *LoadInst,
613 MachineInstr *StoreInst) {
614 const MachineOperand &LoadBase = getBaseOperand(MI: LoadInst);
615 const MachineOperand &StoreBase = getBaseOperand(MI: StoreInst);
616 if (LoadBase.isReg() != StoreBase.isReg())
617 return false;
618 if (LoadBase.isReg())
619 return LoadBase.getReg() == StoreBase.getReg();
620 return LoadBase.getIndex() == StoreBase.getIndex();
621}
622
623static bool isBlockingStore(int64_t LoadDispImm, unsigned LoadSize,
624 int64_t StoreDispImm, unsigned StoreSize) {
625 return ((StoreDispImm >= LoadDispImm) &&
626 (StoreDispImm <= LoadDispImm + (LoadSize - StoreSize)));
627}
628
629// Keep track of all stores blocking a load
630static void
631updateBlockingStoresDispSizeMap(DisplacementSizeMap &BlockingStoresDispSizeMap,
632 int64_t DispImm, unsigned Size) {
633 auto [It, Inserted] = BlockingStoresDispSizeMap.try_emplace(k: DispImm, args&: Size);
634 // Choose the smallest blocking store starting at this displacement.
635 if (!Inserted && It->second > Size)
636 It->second = Size;
637}
638
639// Remove blocking stores contained in each other.
640static void
641removeRedundantBlockingStores(DisplacementSizeMap &BlockingStoresDispSizeMap) {
642 if (BlockingStoresDispSizeMap.size() <= 1)
643 return;
644
645 SmallVector<std::pair<int64_t, unsigned>, 0> DispSizeStack;
646 for (auto DispSizePair : BlockingStoresDispSizeMap) {
647 int64_t CurrDisp = DispSizePair.first;
648 unsigned CurrSize = DispSizePair.second;
649 while (DispSizeStack.size()) {
650 int64_t PrevDisp = DispSizeStack.back().first;
651 unsigned PrevSize = DispSizeStack.back().second;
652 if (CurrDisp + CurrSize > PrevDisp + PrevSize)
653 break;
654 DispSizeStack.pop_back();
655 }
656 DispSizeStack.push_back(Elt: DispSizePair);
657 }
658 BlockingStoresDispSizeMap.clear();
659 for (auto Disp : DispSizeStack)
660 BlockingStoresDispSizeMap.insert(x&: Disp);
661}
662
663bool X86AvoidSFBImpl::runOnMachineFunction(MachineFunction &MF) {
664 bool Changed = false;
665
666 if (DisableX86AvoidStoreForwardBlocks ||
667 !MF.getSubtarget<X86Subtarget>().is64Bit())
668 return false;
669
670 MRI = &MF.getRegInfo();
671 assert(MRI->isSSA() && "Expected MIR to be in SSA form");
672 TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
673 TRI = MF.getSubtarget<X86Subtarget>().getRegisterInfo();
674 LLVM_DEBUG(dbgs() << "Start X86AvoidStoreForwardBlocks\n";);
675 // Look for a load then a store to XMM/YMM which look like a memcpy
676 findPotentiallylBlockedCopies(MF);
677
678 for (auto LoadStoreInstPair : BlockedLoadsStoresPairs) {
679 MachineInstr *LoadInst = LoadStoreInstPair.first;
680 int64_t LdDispImm = getDispOperand(MI: LoadInst).getImm();
681 DisplacementSizeMap BlockingStoresDispSizeMap;
682
683 SmallVector<MachineInstr *, 2> PotentialBlockers =
684 findPotentialBlockers(LoadInst);
685 for (auto *PBInst : PotentialBlockers) {
686 if (!isPotentialBlockingStoreInst(Opcode: PBInst->getOpcode(),
687 LoadOpcode: LoadInst->getOpcode()) ||
688 !isRelevantAddressingMode(MI: PBInst) || !PBInst->hasOneMemOperand())
689 continue;
690 int64_t PBstDispImm = getDispOperand(MI: PBInst).getImm();
691 unsigned PBstSize = (*PBInst->memoperands_begin())->getSize().getValue();
692 // This check doesn't cover all cases, but it will suffice for now.
693 // TODO: take branch probability into consideration, if the blocking
694 // store is in an unreached block, breaking the memcopy could lose
695 // performance.
696 if (hasSameBaseOpValue(LoadInst, StoreInst: PBInst) &&
697 isBlockingStore(LoadDispImm: LdDispImm, LoadSize: getRegSizeInBytes(LoadInst), StoreDispImm: PBstDispImm,
698 StoreSize: PBstSize))
699 updateBlockingStoresDispSizeMap(BlockingStoresDispSizeMap, DispImm: PBstDispImm,
700 Size: PBstSize);
701 }
702
703 if (BlockingStoresDispSizeMap.empty())
704 continue;
705
706 // We found a store forward block, break the memcpy's load and store
707 // into smaller copies such that each smaller store that was causing
708 // a store block would now be copied separately.
709 MachineInstr *StoreInst = LoadStoreInstPair.second;
710 LLVM_DEBUG(dbgs() << "Blocked load and store instructions: \n");
711 LLVM_DEBUG(LoadInst->dump());
712 LLVM_DEBUG(StoreInst->dump());
713 LLVM_DEBUG(dbgs() << "Replaced with:\n");
714 removeRedundantBlockingStores(BlockingStoresDispSizeMap);
715 breakBlockedCopies(LoadInst, StoreInst, BlockingStoresDispSizeMap);
716 updateKillStatus(LoadInst, StoreInst);
717 ForRemoval.push_back(Elt: LoadInst);
718 ForRemoval.push_back(Elt: StoreInst);
719 }
720 for (auto *RemovedInst : ForRemoval) {
721 RemovedInst->eraseFromParent();
722 }
723 ForRemoval.clear();
724 BlockedLoadsStoresPairs.clear();
725 LLVM_DEBUG(dbgs() << "End X86AvoidStoreForwardBlocks\n";);
726
727 return Changed;
728}
729
730bool X86AvoidSFBLegacy::runOnMachineFunction(MachineFunction &MF) {
731 if (skipFunction(F: MF.getFunction()))
732 return false;
733 AliasAnalysis *AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
734 X86AvoidSFBImpl Impl(AA);
735 return Impl.runOnMachineFunction(MF);
736}
737
738PreservedAnalyses
739X86AvoidStoreForwardingBlocksPass::run(MachineFunction &MF,
740 MachineFunctionAnalysisManager &MFAM) {
741 AliasAnalysis *AA =
742 &MFAM.getResult<FunctionAnalysisManagerMachineFunctionProxy>(IR&: MF)
743 .getManager()
744 .getResult<AAManager>(IR&: MF.getFunction());
745 X86AvoidSFBImpl Impl(AA);
746 bool Changed = Impl.runOnMachineFunction(MF);
747 return Changed ? getMachineFunctionPassPreservedAnalyses()
748 : PreservedAnalyses::all();
749}
750