1//===- X86FixupSetCC.cpp - fix zero-extension of setcc patterns -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines a pass that fixes zero-extension of setcc patterns.
10// X86 setcc instructions are modeled to have no input arguments, and a single
11// GR8 output argument. This is consistent with other similar instructions
12// (e.g. movb), but means it is impossible to directly generate a setcc into
13// the lower GR8 of a specified GR32.
14// This means that ISel must select (zext (setcc)) into something like
15// seta %al; movzbl %al, %eax.
16// Unfortunately, this can cause a stall due to the partial register write
17// performed by the setcc. Instead, we can use:
18// xor %eax, %eax; seta %al
19// This both avoids the stall, and encodes shorter.
20//
21// Furthurmore, we can use:
22// setzua %al
23// if feature zero-upper is available. It's faster than the xor+setcc sequence.
24// When r16-r31 is used, it even encodes shorter.
25//===----------------------------------------------------------------------===//
26
27#include "X86.h"
28#include "X86InstrInfo.h"
29#include "X86Subtarget.h"
30#include "llvm/ADT/Statistic.h"
31#include "llvm/CodeGen/MachineFunctionPass.h"
32#include "llvm/CodeGen/MachineInstrBuilder.h"
33#include "llvm/CodeGen/MachineRegisterInfo.h"
34#include "llvm/CodeGen/RegisterClassInfo.h"
35
36using namespace llvm;
37
38#define DEBUG_TYPE "x86-fixup-setcc"
39
40STATISTIC(NumSubstZexts, "Number of setcc + zext pairs substituted");
41
42namespace {
43class X86FixupSetCCLegacy : public MachineFunctionPass {
44public:
45 static char ID;
46
47 X86FixupSetCCLegacy() : MachineFunctionPass(ID) {}
48
49 StringRef getPassName() const override { return "X86 Fixup SetCC"; }
50
51 bool runOnMachineFunction(MachineFunction &MF) override;
52
53 void getAnalysisUsage(AnalysisUsage &AU) const override {
54 AU.addPreserved<MachineRegisterClassInfoWrapperPass>();
55 MachineFunctionPass::getAnalysisUsage(AU);
56 }
57};
58} // end anonymous namespace
59
60char X86FixupSetCCLegacy::ID = 0;
61
62INITIALIZE_PASS(X86FixupSetCCLegacy, DEBUG_TYPE, DEBUG_TYPE, false, false)
63
64FunctionPass *llvm::createX86FixupSetCCLegacyPass() {
65 return new X86FixupSetCCLegacy();
66}
67
68static bool fixupSetCC(MachineFunction &MF) {
69 bool Changed = false;
70 MachineRegisterInfo *MRI = &MF.getRegInfo();
71 const X86Subtarget *ST = &MF.getSubtarget<X86Subtarget>();
72 const X86InstrInfo *TII = ST->getInstrInfo();
73
74 SmallVector<MachineInstr*, 4> ToErase;
75
76 for (auto &MBB : MF) {
77 MachineInstr *FlagsDefMI = nullptr;
78 for (auto &MI : MBB) {
79 // Remember the most recent preceding eflags defining instruction.
80 if (MI.definesRegister(Reg: X86::EFLAGS, /*TRI=*/nullptr))
81 FlagsDefMI = &MI;
82
83 // Find a setcc/setzucc (if ZU is enabled) that is used by a zext.
84 // This doesn't have to be the only use, the transformation is safe
85 // regardless.
86 if (MI.getOpcode() != X86::SETCCr && MI.getOpcode() != X86::SETZUCCr)
87 continue;
88
89 MachineInstr *ZExt = nullptr;
90 Register Reg0 = MI.getOperand(i: 0).getReg();
91 for (auto &Use : MRI->use_instructions(Reg: Reg0))
92 if (Use.getOpcode() == X86::MOVZX32rr8)
93 ZExt = &Use;
94
95 if (!ZExt)
96 continue;
97
98 if (!FlagsDefMI)
99 continue;
100
101 // When ZU is available and not disabled by tuning, we rewrite to
102 // setzucc, which doesn't clobber eflags; otherwise we insert a MOV32r0
103 // (which does clobber eflags) before FlagsDefMI.
104 bool UseSetZUCC = ST->hasZU() && !ST->preferLegacySetCC();
105
106 // We'd like to put something that clobbers eflags directly before
107 // FlagsDefMI. This can't hurt anything after FlagsDefMI, because
108 // it, itself, by definition, clobbers eflags. But it may happen that
109 // FlagsDefMI also *uses* eflags, in which case the transformation is
110 // invalid.
111 if (!UseSetZUCC &&
112 FlagsDefMI->readsRegister(Reg: X86::EFLAGS, /*TRI=*/nullptr))
113 continue;
114
115 // On 32-bit, we need to be careful to force an ABCD register.
116 const TargetRegisterClass *RC =
117 ST->is64Bit() ? &X86::GR32RegClass : &X86::GR32_ABCDRegClass;
118 if (!MRI->constrainRegClass(Reg: ZExt->getOperand(i: 0).getReg(), RC)) {
119 // If we cannot constrain the register, we would need an additional copy
120 // and are better off keeping the MOVZX32rr8 we have now.
121 continue;
122 }
123
124 ++NumSubstZexts;
125 Changed = true;
126
127 // X86 setcc/setzucc only takes an output GR8, so fake a GR32 input by
128 // inserting the setcc/setzucc result into the low byte of the zeroed
129 // register.
130 Register ZeroReg = MRI->createVirtualRegister(RegClass: RC);
131 if (UseSetZUCC) {
132 MI.setDesc(TII->get(Opcode: X86::SETZUCCr));
133 BuildMI(BB&: *ZExt->getParent(), I: ZExt, MIMD: ZExt->getDebugLoc(),
134 MCID: TII->get(Opcode: TargetOpcode::IMPLICIT_DEF), DestReg: ZeroReg);
135 } else {
136 // Initialize a register with 0. This must go before the eflags def
137 BuildMI(BB&: MBB, I: FlagsDefMI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: X86::MOV32r0),
138 DestReg: ZeroReg);
139 }
140
141 BuildMI(BB&: *ZExt->getParent(), I: ZExt, MIMD: ZExt->getDebugLoc(),
142 MCID: TII->get(Opcode: X86::INSERT_SUBREG), DestReg: ZExt->getOperand(i: 0).getReg())
143 .addReg(RegNo: ZeroReg)
144 .addReg(RegNo: Reg0)
145 .addImm(Val: X86::sub_8bit);
146
147 // Redirect the debug-instr-number to the setcc.
148 if (unsigned InstrNum = ZExt->peekDebugInstrNum())
149 MF.makeDebugValueSubstitution({InstrNum, 0},
150 {MI.getDebugInstrNum(), 0});
151
152 ToErase.push_back(Elt: ZExt);
153 }
154 }
155
156 for (auto &I : ToErase)
157 I->eraseFromParent();
158
159 return Changed;
160}
161
162bool X86FixupSetCCLegacy::runOnMachineFunction(MachineFunction &MF) {
163 return fixupSetCC(MF);
164}
165
166PreservedAnalyses X86FixupSetCCPass::run(MachineFunction &MF,
167 MachineFunctionAnalysisManager &MFAM) {
168 return fixupSetCC(MF) ? getMachineFunctionPassPreservedAnalyses()
169 .preserveSet<CFGAnalyses>()
170 : PreservedAnalyses::all();
171}
172