1//===- X86FixupSetCC.cpp - fix zero-extension of setcc patterns -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines a pass that fixes zero-extension of setcc patterns.
10// X86 setcc instructions are modeled to have no input arguments, and a single
11// GR8 output argument. This is consistent with other similar instructions
12// (e.g. movb), but means it is impossible to directly generate a setcc into
13// the lower GR8 of a specified GR32.
14// This means that ISel must select (zext (setcc)) into something like
15// seta %al; movzbl %al, %eax.
16// Unfortunately, this can cause a stall due to the partial register write
17// performed by the setcc. Instead, we can use:
18// xor %eax, %eax; seta %al
19// This both avoids the stall, and encodes shorter.
20//
21// Furthurmore, we can use:
22// setzua %al
23// if feature zero-upper is available. It's faster than the xor+setcc sequence.
24// When r16-r31 is used, it even encodes shorter.
25//===----------------------------------------------------------------------===//
26
27#include "X86.h"
28#include "X86InstrInfo.h"
29#include "X86Subtarget.h"
30#include "llvm/ADT/Statistic.h"
31#include "llvm/CodeGen/MachineFunctionPass.h"
32#include "llvm/CodeGen/MachineInstrBuilder.h"
33#include "llvm/CodeGen/MachineRegisterInfo.h"
34
35using namespace llvm;
36
37#define DEBUG_TYPE "x86-fixup-setcc"
38
39STATISTIC(NumSubstZexts, "Number of setcc + zext pairs substituted");
40
41namespace {
42class X86FixupSetCCLegacy : public MachineFunctionPass {
43public:
44 static char ID;
45
46 X86FixupSetCCLegacy() : MachineFunctionPass(ID) {}
47
48 StringRef getPassName() const override { return "X86 Fixup SetCC"; }
49
50 bool runOnMachineFunction(MachineFunction &MF) override;
51};
52} // end anonymous namespace
53
54char X86FixupSetCCLegacy::ID = 0;
55
56INITIALIZE_PASS(X86FixupSetCCLegacy, DEBUG_TYPE, DEBUG_TYPE, false, false)
57
58FunctionPass *llvm::createX86FixupSetCCLegacyPass() {
59 return new X86FixupSetCCLegacy();
60}
61
62static bool fixupSetCC(MachineFunction &MF) {
63 bool Changed = false;
64 MachineRegisterInfo *MRI = &MF.getRegInfo();
65 const X86Subtarget *ST = &MF.getSubtarget<X86Subtarget>();
66 const X86InstrInfo *TII = ST->getInstrInfo();
67
68 SmallVector<MachineInstr*, 4> ToErase;
69
70 for (auto &MBB : MF) {
71 MachineInstr *FlagsDefMI = nullptr;
72 for (auto &MI : MBB) {
73 // Remember the most recent preceding eflags defining instruction.
74 if (MI.definesRegister(Reg: X86::EFLAGS, /*TRI=*/nullptr))
75 FlagsDefMI = &MI;
76
77 // Find a setcc/setzucc (if ZU is enabled) that is used by a zext.
78 // This doesn't have to be the only use, the transformation is safe
79 // regardless.
80 if (MI.getOpcode() != X86::SETCCr && MI.getOpcode() != X86::SETZUCCr)
81 continue;
82
83 MachineInstr *ZExt = nullptr;
84 Register Reg0 = MI.getOperand(i: 0).getReg();
85 for (auto &Use : MRI->use_instructions(Reg: Reg0))
86 if (Use.getOpcode() == X86::MOVZX32rr8)
87 ZExt = &Use;
88
89 if (!ZExt)
90 continue;
91
92 if (!FlagsDefMI)
93 continue;
94
95 // We'd like to put something that clobbers eflags directly before
96 // FlagsDefMI. This can't hurt anything after FlagsDefMI, because
97 // it, itself, by definition, clobbers eflags. But it may happen that
98 // FlagsDefMI also *uses* eflags, in which case the transformation is
99 // invalid.
100 if (!ST->hasZU() &&
101 FlagsDefMI->readsRegister(Reg: X86::EFLAGS, /*TRI=*/nullptr))
102 continue;
103
104 // On 32-bit, we need to be careful to force an ABCD register.
105 const TargetRegisterClass *RC =
106 ST->is64Bit() ? &X86::GR32RegClass : &X86::GR32_ABCDRegClass;
107 if (!MRI->constrainRegClass(Reg: ZExt->getOperand(i: 0).getReg(), RC)) {
108 // If we cannot constrain the register, we would need an additional copy
109 // and are better off keeping the MOVZX32rr8 we have now.
110 continue;
111 }
112
113 ++NumSubstZexts;
114 Changed = true;
115
116 // X86 setcc/setzucc only takes an output GR8, so fake a GR32 input by
117 // inserting the setcc/setzucc result into the low byte of the zeroed
118 // register.
119 Register ZeroReg = MRI->createVirtualRegister(RegClass: RC);
120 if (ST->hasZU()) {
121 if (!ST->preferLegacySetCC())
122 assert((MI.getOpcode() == X86::SETZUCCr) &&
123 "Expect setzucc instruction!");
124 else
125 MI.setDesc(TII->get(Opcode: X86::SETZUCCr));
126 BuildMI(BB&: *ZExt->getParent(), I: ZExt, MIMD: ZExt->getDebugLoc(),
127 MCID: TII->get(Opcode: TargetOpcode::IMPLICIT_DEF), DestReg: ZeroReg);
128 } else {
129 // Initialize a register with 0. This must go before the eflags def
130 BuildMI(BB&: MBB, I: FlagsDefMI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: X86::MOV32r0),
131 DestReg: ZeroReg);
132 }
133
134 BuildMI(BB&: *ZExt->getParent(), I: ZExt, MIMD: ZExt->getDebugLoc(),
135 MCID: TII->get(Opcode: X86::INSERT_SUBREG), DestReg: ZExt->getOperand(i: 0).getReg())
136 .addReg(RegNo: ZeroReg)
137 .addReg(RegNo: Reg0)
138 .addImm(Val: X86::sub_8bit);
139
140 // Redirect the debug-instr-number to the setcc.
141 if (unsigned InstrNum = ZExt->peekDebugInstrNum())
142 MF.makeDebugValueSubstitution({InstrNum, 0},
143 {MI.getDebugInstrNum(), 0});
144
145 ToErase.push_back(Elt: ZExt);
146 }
147 }
148
149 for (auto &I : ToErase)
150 I->eraseFromParent();
151
152 return Changed;
153}
154
155bool X86FixupSetCCLegacy::runOnMachineFunction(MachineFunction &MF) {
156 return fixupSetCC(MF);
157}
158
159PreservedAnalyses X86FixupSetCCPass::run(MachineFunction &MF,
160 MachineFunctionAnalysisManager &MFAM) {
161 return fixupSetCC(MF) ? getMachineFunctionPassPreservedAnalyses()
162 .preserveSet<CFGAnalyses>()
163 : PreservedAnalyses::all();
164}
165