1//===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains code to lower X86 MachineInstrs to their corresponding
10// MCInst records.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MCTargetDesc/X86ATTInstPrinter.h"
15#include "MCTargetDesc/X86BaseInfo.h"
16#include "MCTargetDesc/X86EncodingOptimization.h"
17#include "MCTargetDesc/X86InstComments.h"
18#include "MCTargetDesc/X86MCAsmInfo.h"
19#include "MCTargetDesc/X86ShuffleDecode.h"
20#include "MCTargetDesc/X86TargetStreamer.h"
21#include "X86AsmPrinter.h"
22#include "X86MachineFunctionInfo.h"
23#include "X86RegisterInfo.h"
24#include "X86ShuffleDecodeConstantPool.h"
25#include "X86Subtarget.h"
26#include "llvm/ADT/STLExtras.h"
27#include "llvm/ADT/SmallString.h"
28#include "llvm/ADT/StringExtras.h"
29#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
30#include "llvm/CodeGen/MachineConstantPool.h"
31#include "llvm/CodeGen/MachineFunction.h"
32#include "llvm/CodeGen/MachineModuleInfoImpls.h"
33#include "llvm/CodeGen/MachineOperand.h"
34#include "llvm/CodeGen/StackMaps.h"
35#include "llvm/CodeGen/WinEHFuncInfo.h"
36#include "llvm/IR/DataLayout.h"
37#include "llvm/IR/GlobalValue.h"
38#include "llvm/IR/Mangler.h"
39#include "llvm/MC/MCAsmInfo.h"
40#include "llvm/MC/MCCodeEmitter.h"
41#include "llvm/MC/MCContext.h"
42#include "llvm/MC/MCExpr.h"
43#include "llvm/MC/MCFixup.h"
44#include "llvm/MC/MCInst.h"
45#include "llvm/MC/MCInstBuilder.h"
46#include "llvm/MC/MCSection.h"
47#include "llvm/MC/MCStreamer.h"
48#include "llvm/MC/MCSymbol.h"
49#include "llvm/MC/TargetRegistry.h"
50#include "llvm/Target/TargetLoweringObjectFile.h"
51#include "llvm/Target/TargetMachine.h"
52#include "llvm/Transforms/CFGuard.h"
53#include "llvm/Transforms/Instrumentation/AddressSanitizer.h"
54#include "llvm/Transforms/Instrumentation/AddressSanitizerCommon.h"
55#include <string>
56
57using namespace llvm;
58
59static cl::opt<bool> EnableBranchHint("enable-branch-hint",
60 cl::desc("Enable branch hint."),
61 cl::init(Val: false), cl::Hidden);
62static cl::opt<unsigned> BranchHintProbabilityThreshold(
63 "branch-hint-probability-threshold",
64 cl::desc("The probability threshold of enabling branch hint."),
65 cl::init(Val: 50), cl::Hidden);
66
67namespace {
68
69/// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
70class X86MCInstLower {
71 MCContext &Ctx;
72 const MachineFunction &MF;
73 const TargetMachine &TM;
74 const MCAsmInfo &MAI;
75 X86AsmPrinter &AsmPrinter;
76
77public:
78 X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
79
80 MCOperand LowerMachineOperand(const MachineInstr *MI,
81 const MachineOperand &MO) const;
82 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
83
84 MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
85 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
86
87private:
88 MachineModuleInfoMachO &getMachOMMI() const;
89};
90
91} // end anonymous namespace
92
93/// A RAII helper which defines a region of instructions which can't have
94/// padding added between them for correctness.
95struct NoAutoPaddingScope {
96 MCStreamer &OS;
97 const bool OldAllowAutoPadding;
98 NoAutoPaddingScope(MCStreamer &OS)
99 : OS(OS), OldAllowAutoPadding(OS.getAllowAutoPadding()) {
100 changeAndComment(b: false);
101 }
102 ~NoAutoPaddingScope() { changeAndComment(b: OldAllowAutoPadding); }
103 void changeAndComment(bool b) {
104 if (b == OS.getAllowAutoPadding())
105 return;
106 OS.setAllowAutoPadding(b);
107 if (b)
108 OS.emitRawComment(T: "autopadding");
109 else
110 OS.emitRawComment(T: "noautopadding");
111 }
112};
113
114// Emit a minimal sequence of nops spanning NumBytes bytes.
115static void emitX86Nops(MCStreamer &OS, unsigned NumBytes,
116 const X86Subtarget *Subtarget);
117
118void X86AsmPrinter::StackMapShadowTracker::count(const MCInst &Inst,
119 const MCSubtargetInfo &STI,
120 MCCodeEmitter *CodeEmitter) {
121 if (InShadow) {
122 SmallString<256> Code;
123 SmallVector<MCFixup, 4> Fixups;
124 CodeEmitter->encodeInstruction(Inst, CB&: Code, Fixups, STI);
125 CurrentShadowSize += Code.size();
126 if (CurrentShadowSize >= RequiredShadowSize)
127 InShadow = false; // The shadow is big enough. Stop counting.
128 }
129}
130
131void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
132 MCStreamer &OutStreamer, const MCSubtargetInfo &STI) {
133 if (InShadow && CurrentShadowSize < RequiredShadowSize) {
134 InShadow = false;
135 emitX86Nops(OS&: OutStreamer, NumBytes: RequiredShadowSize - CurrentShadowSize,
136 Subtarget: &MF->getSubtarget<X86Subtarget>());
137 }
138}
139
140void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) {
141 OutStreamer->emitInstruction(Inst, STI: getSubtargetInfo());
142 SMShadowTracker.count(Inst, STI: getSubtargetInfo(), CodeEmitter: CodeEmitter.get());
143}
144
145X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
146 X86AsmPrinter &asmprinter)
147 : Ctx(asmprinter.OutContext), MF(mf), TM(mf.getTarget()),
148 MAI(*TM.getMCAsmInfo()), AsmPrinter(asmprinter) {}
149
150MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
151 return AsmPrinter.MMI->getObjFileInfo<MachineModuleInfoMachO>();
152}
153
154/// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
155/// operand to an MCSymbol.
156MCSymbol *X86MCInstLower::GetSymbolFromOperand(const MachineOperand &MO) const {
157 const Triple &TT = TM.getTargetTriple();
158 if (MO.isGlobal() && TT.isOSBinFormatELF())
159 return AsmPrinter.getSymbolPreferLocal(GV: *MO.getGlobal());
160
161 const DataLayout &DL = MF.getDataLayout();
162 assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) &&
163 "Isn't a symbol reference");
164
165 MCSymbol *Sym = nullptr;
166 SmallString<128> Name;
167 StringRef Suffix;
168
169 switch (MO.getTargetFlags()) {
170 case X86II::MO_DLLIMPORT:
171 // Handle dllimport linkage.
172 Name += "__imp_";
173 break;
174 case X86II::MO_COFFSTUB:
175 Name += ".refptr.";
176 break;
177 case X86II::MO_DARWIN_NONLAZY:
178 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
179 Suffix = "$non_lazy_ptr";
180 break;
181 }
182
183 if (!Suffix.empty())
184 Name += DL.getPrivateGlobalPrefix();
185
186 if (MO.isGlobal()) {
187 const GlobalValue *GV = MO.getGlobal();
188 AsmPrinter.getNameWithPrefix(Name, GV);
189 } else if (MO.isSymbol()) {
190 Mangler::getNameWithPrefix(OutName&: Name, GVName: MO.getSymbolName(), DL);
191 } else if (MO.isMBB()) {
192 assert(Suffix.empty());
193 Sym = MO.getMBB()->getSymbol();
194 }
195
196 Name += Suffix;
197 if (!Sym)
198 Sym = Ctx.getOrCreateSymbol(Name);
199
200 // If the target flags on the operand changes the name of the symbol, do that
201 // before we return the symbol.
202 switch (MO.getTargetFlags()) {
203 default:
204 break;
205 case X86II::MO_COFFSTUB: {
206 MachineModuleInfoCOFF &MMICOFF =
207 AsmPrinter.MMI->getObjFileInfo<MachineModuleInfoCOFF>();
208 MachineModuleInfoImpl::StubValueTy &StubSym = MMICOFF.getGVStubEntry(Sym);
209 if (!StubSym.getPointer()) {
210 assert(MO.isGlobal() && "Extern symbol not handled yet");
211 StubSym = MachineModuleInfoImpl::StubValueTy(
212 AsmPrinter.getSymbol(GV: MO.getGlobal()), true);
213 }
214 break;
215 }
216 case X86II::MO_DARWIN_NONLAZY:
217 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
218 MachineModuleInfoImpl::StubValueTy &StubSym =
219 getMachOMMI().getGVStubEntry(Sym);
220 if (!StubSym.getPointer()) {
221 assert(MO.isGlobal() && "Extern symbol not handled yet");
222 StubSym = MachineModuleInfoImpl::StubValueTy(
223 AsmPrinter.getSymbol(GV: MO.getGlobal()),
224 !MO.getGlobal()->hasInternalLinkage());
225 }
226 break;
227 }
228 }
229
230 return Sym;
231}
232
233MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
234 MCSymbol *Sym) const {
235 // FIXME: We would like an efficient form for this, so we don't have to do a
236 // lot of extra uniquing.
237 const MCExpr *Expr = nullptr;
238 uint16_t Specifier = X86::S_None;
239
240 switch (MO.getTargetFlags()) {
241 default:
242 llvm_unreachable("Unknown target flag on GV operand");
243 case X86II::MO_NO_FLAG: // No flag.
244 // These affect the name of the symbol, not any suffix.
245 case X86II::MO_DARWIN_NONLAZY:
246 case X86II::MO_DLLIMPORT:
247 case X86II::MO_COFFSTUB:
248 break;
249
250 case X86II::MO_TLVP:
251 Specifier = X86::S_TLVP;
252 break;
253 case X86II::MO_TLVP_PIC_BASE:
254 Expr = MCSymbolRefExpr::create(Symbol: Sym, specifier: X86::S_TLVP, Ctx);
255 // Subtract the pic base.
256 Expr = MCBinaryExpr::createSub(
257 LHS: Expr, RHS: MCSymbolRefExpr::create(Symbol: MF.getPICBaseSymbol(), Ctx), Ctx);
258 break;
259 case X86II::MO_SECREL:
260 Specifier = uint16_t(X86::S_COFF_SECREL);
261 break;
262 case X86II::MO_TLSGD:
263 Specifier = X86::S_TLSGD;
264 break;
265 case X86II::MO_TLSLD:
266 Specifier = X86::S_TLSLD;
267 break;
268 case X86II::MO_TLSLDM:
269 Specifier = X86::S_TLSLDM;
270 break;
271 case X86II::MO_GOTTPOFF:
272 Specifier = X86::S_GOTTPOFF;
273 break;
274 case X86II::MO_INDNTPOFF:
275 Specifier = X86::S_INDNTPOFF;
276 break;
277 case X86II::MO_TPOFF:
278 Specifier = X86::S_TPOFF;
279 break;
280 case X86II::MO_DTPOFF:
281 Specifier = X86::S_DTPOFF;
282 break;
283 case X86II::MO_NTPOFF:
284 Specifier = X86::S_NTPOFF;
285 break;
286 case X86II::MO_GOTNTPOFF:
287 Specifier = X86::S_GOTNTPOFF;
288 break;
289 case X86II::MO_GOTPCREL:
290 Specifier = X86::S_GOTPCREL;
291 break;
292 case X86II::MO_GOTPCREL_NORELAX:
293 Specifier = X86::S_GOTPCREL_NORELAX;
294 break;
295 case X86II::MO_GOT:
296 Specifier = X86::S_GOT;
297 break;
298 case X86II::MO_GOTOFF:
299 Specifier = X86::S_GOTOFF;
300 break;
301 case X86II::MO_PLT:
302 Specifier = X86::S_PLT;
303 break;
304 case X86II::MO_ABS8:
305 Specifier = X86::S_ABS8;
306 break;
307 case X86II::MO_PIC_BASE_OFFSET:
308 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
309 Expr = MCSymbolRefExpr::create(Symbol: Sym, Ctx);
310 // Subtract the pic base.
311 Expr = MCBinaryExpr::createSub(
312 LHS: Expr, RHS: MCSymbolRefExpr::create(Symbol: MF.getPICBaseSymbol(), Ctx), Ctx);
313 if (MO.isJTI()) {
314 assert(MAI.doesSetDirectiveSuppressReloc());
315 // If .set directive is supported, use it to reduce the number of
316 // relocations the assembler will generate for differences between
317 // local labels. This is only safe when the symbols are in the same
318 // section so we are restricting it to jumptable references.
319 MCSymbol *Label = Ctx.createTempSymbol();
320 AsmPrinter.OutStreamer->emitAssignment(Symbol: Label, Value: Expr);
321 Expr = MCSymbolRefExpr::create(Symbol: Label, Ctx);
322 }
323 break;
324 }
325
326 if (!Expr)
327 Expr = MCSymbolRefExpr::create(Symbol: Sym, specifier: Specifier, Ctx);
328
329 if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
330 Expr = MCBinaryExpr::createAdd(
331 LHS: Expr, RHS: MCConstantExpr::create(Value: MO.getOffset(), Ctx), Ctx);
332 return MCOperand::createExpr(Val: Expr);
333}
334
335static unsigned getRetOpcode(const X86Subtarget &Subtarget) {
336 return Subtarget.is64Bit() ? X86::RET64 : X86::RET32;
337}
338
339MCOperand X86MCInstLower::LowerMachineOperand(const MachineInstr *MI,
340 const MachineOperand &MO) const {
341 switch (MO.getType()) {
342 default:
343 MI->print(OS&: errs());
344 llvm_unreachable("unknown operand type");
345 case MachineOperand::MO_Register:
346 // Ignore all implicit register operands.
347 if (MO.isImplicit())
348 return MCOperand();
349 return MCOperand::createReg(Reg: MO.getReg());
350 case MachineOperand::MO_Immediate:
351 return MCOperand::createImm(Val: MO.getImm());
352 case MachineOperand::MO_MachineBasicBlock:
353 case MachineOperand::MO_GlobalAddress:
354 case MachineOperand::MO_ExternalSymbol:
355 return LowerSymbolOperand(MO, Sym: GetSymbolFromOperand(MO));
356 case MachineOperand::MO_MCSymbol:
357 return LowerSymbolOperand(MO, Sym: MO.getMCSymbol());
358 case MachineOperand::MO_JumpTableIndex:
359 return LowerSymbolOperand(MO, Sym: AsmPrinter.GetJTISymbol(JTID: MO.getIndex()));
360 case MachineOperand::MO_ConstantPoolIndex:
361 return LowerSymbolOperand(MO, Sym: AsmPrinter.GetCPISymbol(CPID: MO.getIndex()));
362 case MachineOperand::MO_BlockAddress:
363 return LowerSymbolOperand(
364 MO, Sym: AsmPrinter.GetBlockAddressSymbol(BA: MO.getBlockAddress()));
365 case MachineOperand::MO_RegisterMask:
366 // Ignore call clobbers.
367 return MCOperand();
368 }
369}
370
371// Replace TAILJMP opcodes with their equivalent opcodes that have encoding
372// information.
373static unsigned convertTailJumpOpcode(unsigned Opcode) {
374 switch (Opcode) {
375 case X86::TAILJMPr:
376 Opcode = X86::JMP32r;
377 break;
378 case X86::TAILJMPm:
379 Opcode = X86::JMP32m;
380 break;
381 case X86::TAILJMPr64:
382 Opcode = X86::JMP64r;
383 break;
384 case X86::TAILJMPm64:
385 Opcode = X86::JMP64m;
386 break;
387 case X86::TAILJMPr64_REX:
388 Opcode = X86::JMP64r_REX;
389 break;
390 case X86::TAILJMPm64_REX:
391 Opcode = X86::JMP64m_REX;
392 break;
393 case X86::TAILJMPd:
394 case X86::TAILJMPd64:
395 Opcode = X86::JMP_1;
396 break;
397 case X86::TAILJMPd_CC:
398 case X86::TAILJMPd64_CC:
399 Opcode = X86::JCC_1;
400 break;
401 }
402
403 return Opcode;
404}
405
406void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
407 OutMI.setOpcode(MI->getOpcode());
408
409 for (const MachineOperand &MO : MI->operands())
410 if (auto Op = LowerMachineOperand(MI, MO); Op.isValid())
411 OutMI.addOperand(Op);
412
413 bool In64BitMode = AsmPrinter.getSubtarget().is64Bit();
414 if (X86::optimizeInstFromVEX3ToVEX2(MI&: OutMI, Desc: MI->getDesc()) ||
415 X86::optimizeShiftRotateWithImmediateOne(MI&: OutMI) ||
416 X86::optimizeVPCMPWithImmediateOneOrSix(MI&: OutMI) ||
417 X86::optimizeMOVSX(MI&: OutMI) || X86::optimizeINCDEC(MI&: OutMI, In64BitMode) ||
418 X86::optimizeMOV(MI&: OutMI, In64BitMode) ||
419 X86::optimizeToFixedRegisterOrShortImmediateForm(MI&: OutMI))
420 return;
421
422 // Handle a few special cases to eliminate operand modifiers.
423 switch (OutMI.getOpcode()) {
424 case X86::LEA64_32r:
425 case X86::LEA64r:
426 case X86::LEA16r:
427 case X86::LEA32r:
428 // LEA should have a segment register, but it must be empty.
429 assert(OutMI.getNumOperands() == 1 + X86::AddrNumOperands &&
430 "Unexpected # of LEA operands");
431 assert(OutMI.getOperand(1 + X86::AddrSegmentReg).getReg() == 0 &&
432 "LEA has segment specified!");
433 break;
434 case X86::MULX32Hrr:
435 case X86::MULX32Hrm:
436 case X86::MULX64Hrr:
437 case X86::MULX64Hrm: {
438 // Turn into regular MULX by duplicating the destination.
439 unsigned NewOpc;
440 switch (OutMI.getOpcode()) {
441 default: llvm_unreachable("Invalid opcode");
442 case X86::MULX32Hrr: NewOpc = X86::MULX32rr; break;
443 case X86::MULX32Hrm: NewOpc = X86::MULX32rm; break;
444 case X86::MULX64Hrr: NewOpc = X86::MULX64rr; break;
445 case X86::MULX64Hrm: NewOpc = X86::MULX64rm; break;
446 }
447 OutMI.setOpcode(NewOpc);
448 // Duplicate the destination.
449 MCRegister DestReg = OutMI.getOperand(i: 0).getReg();
450 OutMI.insert(I: OutMI.begin(), Op: MCOperand::createReg(Reg: DestReg));
451 break;
452 }
453 // CALL64r, CALL64pcrel32 - These instructions used to have
454 // register inputs modeled as normal uses instead of implicit uses. As such,
455 // they we used to truncate off all but the first operand (the callee). This
456 // issue seems to have been fixed at some point. This assert verifies that.
457 case X86::CALL64r:
458 case X86::CALL64pcrel32:
459 assert(OutMI.getNumOperands() == 1 && "Unexpected number of operands!");
460 break;
461 case X86::EH_RETURN:
462 case X86::EH_RETURN64: {
463 OutMI = MCInst();
464 OutMI.setOpcode(getRetOpcode(Subtarget: AsmPrinter.getSubtarget()));
465 break;
466 }
467 case X86::CLEANUPRET: {
468 // Replace CLEANUPRET with the appropriate RET.
469 OutMI = MCInst();
470 OutMI.setOpcode(getRetOpcode(Subtarget: AsmPrinter.getSubtarget()));
471 break;
472 }
473 case X86::CATCHRET: {
474 // Replace CATCHRET with the appropriate RET.
475 const X86Subtarget &Subtarget = AsmPrinter.getSubtarget();
476 unsigned ReturnReg = In64BitMode ? X86::RAX : X86::EAX;
477 OutMI = MCInst();
478 OutMI.setOpcode(getRetOpcode(Subtarget));
479 OutMI.addOperand(Op: MCOperand::createReg(Reg: ReturnReg));
480 break;
481 }
482 // TAILJMPd, TAILJMPd64, TailJMPd_cc - Lower to the correct jump
483 // instruction.
484 case X86::TAILJMPr:
485 case X86::TAILJMPr64:
486 case X86::TAILJMPr64_REX:
487 case X86::TAILJMPd:
488 case X86::TAILJMPd64:
489 assert(OutMI.getNumOperands() == 1 && "Unexpected number of operands!");
490 OutMI.setOpcode(convertTailJumpOpcode(Opcode: OutMI.getOpcode()));
491 break;
492 case X86::TAILJMPd_CC:
493 case X86::TAILJMPd64_CC:
494 assert(OutMI.getNumOperands() == 2 && "Unexpected number of operands!");
495 OutMI.setOpcode(convertTailJumpOpcode(Opcode: OutMI.getOpcode()));
496 break;
497 case X86::TAILJMPm:
498 case X86::TAILJMPm64:
499 case X86::TAILJMPm64_REX:
500 assert(OutMI.getNumOperands() == X86::AddrNumOperands &&
501 "Unexpected number of operands!");
502 OutMI.setOpcode(convertTailJumpOpcode(Opcode: OutMI.getOpcode()));
503 break;
504 case X86::MASKMOVDQU:
505 case X86::VMASKMOVDQU:
506 if (In64BitMode)
507 OutMI.setFlags(X86::IP_HAS_AD_SIZE);
508 break;
509 case X86::BSF16rm:
510 case X86::BSF16rr:
511 case X86::BSF32rm:
512 case X86::BSF32rr:
513 case X86::BSF64rm:
514 case X86::BSF64rr: {
515 // Add an REP prefix to BSF instructions so that new processors can
516 // recognize as TZCNT, which has better performance than BSF.
517 // BSF and TZCNT have different interpretations on ZF bit. So make sure
518 // it won't be used later.
519 const MachineOperand *FlagDef =
520 MI->findRegisterDefOperand(Reg: X86::EFLAGS, /*TRI=*/nullptr);
521 if (!MF.getFunction().hasOptSize() && FlagDef && FlagDef->isDead())
522 OutMI.setFlags(X86::IP_HAS_REPEAT);
523 break;
524 }
525 default:
526 break;
527 }
528}
529
530void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
531 const MachineInstr &MI) {
532 NoAutoPaddingScope NoPadScope(*OutStreamer);
533 bool Is64Bits = getSubtarget().is64Bit();
534 bool Is64BitsLP64 = getSubtarget().isTarget64BitLP64();
535 MCContext &Ctx = OutStreamer->getContext();
536
537 X86::Specifier Specifier;
538 switch (MI.getOpcode()) {
539 case X86::TLS_addr32:
540 case X86::TLS_addr64:
541 case X86::TLS_addrX32:
542 Specifier = X86::S_TLSGD;
543 break;
544 case X86::TLS_base_addr32:
545 Specifier = X86::S_TLSLDM;
546 break;
547 case X86::TLS_base_addr64:
548 case X86::TLS_base_addrX32:
549 Specifier = X86::S_TLSLD;
550 break;
551 case X86::TLS_desc32:
552 case X86::TLS_desc64:
553 Specifier = X86::S_TLSDESC;
554 break;
555 default:
556 llvm_unreachable("unexpected opcode");
557 }
558
559 const MCSymbolRefExpr *Sym = MCSymbolRefExpr::create(
560 Symbol: MCInstLowering.GetSymbolFromOperand(MO: MI.getOperand(i: 3)), specifier: Specifier, Ctx);
561
562 // Before binutils 2.41, ld has a bogus TLS relaxation error when the GD/LD
563 // code sequence using R_X86_64_GOTPCREL (instead of R_X86_64_GOTPCRELX) is
564 // attempted to be relaxed to IE/LE (binutils PR24784). Work around the bug by
565 // only using GOT when GOTPCRELX is enabled.
566 // TODO Delete the workaround when rustc no longer relies on the hack
567 bool UseGot = MMI->getModule()->getRtLibUseGOT() &&
568 Ctx.getTargetOptions()->X86RelaxRelocations;
569
570 if (Specifier == X86::S_TLSDESC) {
571 const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(
572 Symbol: MCInstLowering.GetSymbolFromOperand(MO: MI.getOperand(i: 3)), specifier: X86::S_TLSCALL,
573 Ctx);
574 EmitAndCountInstruction(
575 Inst&: MCInstBuilder(Is64BitsLP64 ? X86::LEA64r : X86::LEA32r)
576 .addReg(Reg: Is64BitsLP64 ? X86::RAX : X86::EAX)
577 .addReg(Reg: Is64Bits ? X86::RIP : X86::EBX)
578 .addImm(Val: 1)
579 .addReg(Reg: 0)
580 .addExpr(Val: Sym)
581 .addReg(Reg: 0));
582 EmitAndCountInstruction(
583 Inst&: MCInstBuilder(Is64Bits ? X86::CALL64m : X86::CALL32m)
584 .addReg(Reg: Is64BitsLP64 ? X86::RAX : X86::EAX)
585 .addImm(Val: 1)
586 .addReg(Reg: 0)
587 .addExpr(Val: Expr)
588 .addReg(Reg: 0));
589 } else if (Is64Bits) {
590 bool NeedsPadding = Specifier == X86::S_TLSGD;
591 if (NeedsPadding && Is64BitsLP64)
592 EmitAndCountInstruction(Inst&: MCInstBuilder(X86::DATA16_PREFIX));
593 EmitAndCountInstruction(Inst&: MCInstBuilder(X86::LEA64r)
594 .addReg(Reg: X86::RDI)
595 .addReg(Reg: X86::RIP)
596 .addImm(Val: 1)
597 .addReg(Reg: 0)
598 .addExpr(Val: Sym)
599 .addReg(Reg: 0));
600 const MCSymbol *TlsGetAddr = Ctx.getOrCreateSymbol(Name: "__tls_get_addr");
601 if (NeedsPadding) {
602 if (!UseGot)
603 EmitAndCountInstruction(Inst&: MCInstBuilder(X86::DATA16_PREFIX));
604 EmitAndCountInstruction(Inst&: MCInstBuilder(X86::DATA16_PREFIX));
605 EmitAndCountInstruction(Inst&: MCInstBuilder(X86::REX64_PREFIX));
606 }
607 if (UseGot) {
608 const MCExpr *Expr =
609 MCSymbolRefExpr::create(Symbol: TlsGetAddr, specifier: X86::S_GOTPCREL, Ctx);
610 EmitAndCountInstruction(Inst&: MCInstBuilder(X86::CALL64m)
611 .addReg(Reg: X86::RIP)
612 .addImm(Val: 1)
613 .addReg(Reg: 0)
614 .addExpr(Val: Expr)
615 .addReg(Reg: 0));
616 } else {
617 EmitAndCountInstruction(
618 Inst&: MCInstBuilder(X86::CALL64pcrel32)
619 .addExpr(Val: MCSymbolRefExpr::create(Symbol: TlsGetAddr, specifier: X86::S_PLT, Ctx)));
620 }
621 } else {
622 if (Specifier == X86::S_TLSGD && !UseGot) {
623 EmitAndCountInstruction(Inst&: MCInstBuilder(X86::LEA32r)
624 .addReg(Reg: X86::EAX)
625 .addReg(Reg: 0)
626 .addImm(Val: 1)
627 .addReg(Reg: X86::EBX)
628 .addExpr(Val: Sym)
629 .addReg(Reg: 0));
630 } else {
631 EmitAndCountInstruction(Inst&: MCInstBuilder(X86::LEA32r)
632 .addReg(Reg: X86::EAX)
633 .addReg(Reg: X86::EBX)
634 .addImm(Val: 1)
635 .addReg(Reg: 0)
636 .addExpr(Val: Sym)
637 .addReg(Reg: 0));
638 }
639
640 const MCSymbol *TlsGetAddr = Ctx.getOrCreateSymbol(Name: "___tls_get_addr");
641 if (UseGot) {
642 const MCExpr *Expr = MCSymbolRefExpr::create(Symbol: TlsGetAddr, specifier: X86::S_GOT, Ctx);
643 EmitAndCountInstruction(Inst&: MCInstBuilder(X86::CALL32m)
644 .addReg(Reg: X86::EBX)
645 .addImm(Val: 1)
646 .addReg(Reg: 0)
647 .addExpr(Val: Expr)
648 .addReg(Reg: 0));
649 } else {
650 EmitAndCountInstruction(
651 Inst&: MCInstBuilder(X86::CALLpcrel32)
652 .addExpr(Val: MCSymbolRefExpr::create(Symbol: TlsGetAddr, specifier: X86::S_PLT, Ctx)));
653 }
654 }
655}
656
657/// Emit the largest nop instruction smaller than or equal to \p NumBytes
658/// bytes. Return the size of nop emitted.
659static unsigned emitNop(MCStreamer &OS, unsigned NumBytes,
660 const X86Subtarget *Subtarget) {
661 // Determine the longest nop which can be efficiently decoded for the given
662 // target cpu. 15-bytes is the longest single NOP instruction, but some
663 // platforms can't decode the longest forms efficiently.
664 unsigned MaxNopLength = 1;
665 if (Subtarget->is64Bit()) {
666 // FIXME: We can use NOOPL on 32-bit targets with FeatureNOPL, but the
667 // IndexReg/BaseReg below need to be updated.
668 if (Subtarget->hasFeature(Feature: X86::TuningFast7ByteNOP))
669 MaxNopLength = 7;
670 else if (Subtarget->hasFeature(Feature: X86::TuningFast15ByteNOP))
671 MaxNopLength = 15;
672 else if (Subtarget->hasFeature(Feature: X86::TuningFast11ByteNOP))
673 MaxNopLength = 11;
674 else
675 MaxNopLength = 10;
676 } if (Subtarget->is32Bit())
677 MaxNopLength = 2;
678
679 // Cap a single nop emission at the profitable value for the target
680 NumBytes = std::min(a: NumBytes, b: MaxNopLength);
681
682 unsigned NopSize;
683 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
684 IndexReg = Displacement = SegmentReg = 0;
685 BaseReg = X86::RAX;
686 ScaleVal = 1;
687 switch (NumBytes) {
688 case 0:
689 llvm_unreachable("Zero nops?");
690 break;
691 case 1:
692 NopSize = 1;
693 Opc = X86::NOOP;
694 break;
695 case 2:
696 NopSize = 2;
697 Opc = X86::XCHG16ar;
698 break;
699 case 3:
700 NopSize = 3;
701 Opc = X86::NOOPL;
702 break;
703 case 4:
704 NopSize = 4;
705 Opc = X86::NOOPL;
706 Displacement = 8;
707 break;
708 case 5:
709 NopSize = 5;
710 Opc = X86::NOOPL;
711 Displacement = 8;
712 IndexReg = X86::RAX;
713 break;
714 case 6:
715 NopSize = 6;
716 Opc = X86::NOOPW;
717 Displacement = 8;
718 IndexReg = X86::RAX;
719 break;
720 case 7:
721 NopSize = 7;
722 Opc = X86::NOOPL;
723 Displacement = 512;
724 break;
725 case 8:
726 NopSize = 8;
727 Opc = X86::NOOPL;
728 Displacement = 512;
729 IndexReg = X86::RAX;
730 break;
731 case 9:
732 NopSize = 9;
733 Opc = X86::NOOPW;
734 Displacement = 512;
735 IndexReg = X86::RAX;
736 break;
737 default:
738 NopSize = 10;
739 Opc = X86::NOOPW;
740 Displacement = 512;
741 IndexReg = X86::RAX;
742 SegmentReg = X86::CS;
743 break;
744 }
745
746 unsigned NumPrefixes = std::min(a: NumBytes - NopSize, b: 5U);
747 NopSize += NumPrefixes;
748 for (unsigned i = 0; i != NumPrefixes; ++i)
749 OS.emitBytes(Data: "\x66");
750
751 switch (Opc) {
752 default: llvm_unreachable("Unexpected opcode");
753 case X86::NOOP:
754 OS.emitInstruction(Inst: MCInstBuilder(Opc), STI: *Subtarget);
755 break;
756 case X86::XCHG16ar:
757 OS.emitInstruction(Inst: MCInstBuilder(Opc).addReg(Reg: X86::AX).addReg(Reg: X86::AX),
758 STI: *Subtarget);
759 break;
760 case X86::NOOPL:
761 case X86::NOOPW:
762 OS.emitInstruction(Inst: MCInstBuilder(Opc)
763 .addReg(Reg: BaseReg)
764 .addImm(Val: ScaleVal)
765 .addReg(Reg: IndexReg)
766 .addImm(Val: Displacement)
767 .addReg(Reg: SegmentReg),
768 STI: *Subtarget);
769 break;
770 }
771 assert(NopSize <= NumBytes && "We overemitted?");
772 return NopSize;
773}
774
775/// Emit the optimal amount of multi-byte nops on X86.
776static void emitX86Nops(MCStreamer &OS, unsigned NumBytes,
777 const X86Subtarget *Subtarget) {
778 unsigned NopsToEmit = NumBytes;
779 (void)NopsToEmit;
780 while (NumBytes) {
781 NumBytes -= emitNop(OS, NumBytes, Subtarget);
782 assert(NopsToEmit >= NumBytes && "Emitted more than I asked for!");
783 }
784}
785
786void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI,
787 X86MCInstLower &MCIL) {
788 assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64");
789
790 NoAutoPaddingScope NoPadScope(*OutStreamer);
791
792 StatepointOpers SOpers(&MI);
793 if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
794 emitX86Nops(OS&: *OutStreamer, NumBytes: PatchBytes, Subtarget);
795 } else {
796 // Lower call target and choose correct opcode
797 const MachineOperand &CallTarget = SOpers.getCallTarget();
798 MCOperand CallTargetMCOp;
799 unsigned CallOpcode;
800 switch (CallTarget.getType()) {
801 case MachineOperand::MO_GlobalAddress:
802 case MachineOperand::MO_ExternalSymbol:
803 CallTargetMCOp = MCIL.LowerSymbolOperand(
804 MO: CallTarget, Sym: MCIL.GetSymbolFromOperand(MO: CallTarget));
805 CallOpcode = X86::CALL64pcrel32;
806 // Currently, we only support relative addressing with statepoints.
807 // Otherwise, we'll need a scratch register to hold the target
808 // address. You'll fail asserts during load & relocation if this
809 // symbol is to far away. (TODO: support non-relative addressing)
810 break;
811 case MachineOperand::MO_Immediate:
812 CallTargetMCOp = MCOperand::createImm(Val: CallTarget.getImm());
813 CallOpcode = X86::CALL64pcrel32;
814 // Currently, we only support relative addressing with statepoints.
815 // Otherwise, we'll need a scratch register to hold the target
816 // immediate. You'll fail asserts during load & relocation if this
817 // address is to far away. (TODO: support non-relative addressing)
818 break;
819 case MachineOperand::MO_Register:
820 // FIXME: Add retpoline support and remove this.
821 if (Subtarget->useIndirectThunkCalls())
822 report_fatal_error(reason: "Lowering register statepoints with thunks not "
823 "yet implemented.");
824 CallTargetMCOp = MCOperand::createReg(Reg: CallTarget.getReg());
825 CallOpcode = X86::CALL64r;
826 break;
827 default:
828 llvm_unreachable("Unsupported operand type in statepoint call target");
829 break;
830 }
831
832 // Emit call
833 MCInst CallInst;
834 CallInst.setOpcode(CallOpcode);
835 CallInst.addOperand(Op: CallTargetMCOp);
836 OutStreamer->emitInstruction(Inst: CallInst, STI: getSubtargetInfo());
837 maybeEmitNopAfterCallForWindowsEH(MI: &MI);
838 }
839
840 // Record our statepoint node in the same section used by STACKMAP
841 // and PATCHPOINT
842 auto &Ctx = OutStreamer->getContext();
843 MCSymbol *MILabel = Ctx.createTempSymbol();
844 OutStreamer->emitLabel(Symbol: MILabel);
845 SM.recordStatepoint(L: *MILabel, MI);
846}
847
848void X86AsmPrinter::LowerFAULTING_OP(const MachineInstr &FaultingMI,
849 X86MCInstLower &MCIL) {
850 // FAULTING_LOAD_OP <def>, <faltinf type>, <MBB handler>,
851 // <opcode>, <operands>
852
853 NoAutoPaddingScope NoPadScope(*OutStreamer);
854
855 Register DefRegister = FaultingMI.getOperand(i: 0).getReg();
856 FaultMaps::FaultKind FK =
857 static_cast<FaultMaps::FaultKind>(FaultingMI.getOperand(i: 1).getImm());
858 MCSymbol *HandlerLabel = FaultingMI.getOperand(i: 2).getMBB()->getSymbol();
859 unsigned Opcode = FaultingMI.getOperand(i: 3).getImm();
860 unsigned OperandsBeginIdx = 4;
861
862 auto &Ctx = OutStreamer->getContext();
863 MCSymbol *FaultingLabel = Ctx.createTempSymbol();
864 OutStreamer->emitLabel(Symbol: FaultingLabel);
865
866 assert(FK < FaultMaps::FaultKindMax && "Invalid Faulting Kind!");
867 FM.recordFaultingOp(FaultTy: FK, FaultingLabel, HandlerLabel);
868
869 MCInst MI;
870 MI.setOpcode(Opcode);
871
872 if (DefRegister != X86::NoRegister)
873 MI.addOperand(Op: MCOperand::createReg(Reg: DefRegister));
874
875 for (const MachineOperand &MO :
876 llvm::drop_begin(RangeOrContainer: FaultingMI.operands(), N: OperandsBeginIdx))
877 if (auto Op = MCIL.LowerMachineOperand(MI: &FaultingMI, MO); Op.isValid())
878 MI.addOperand(Op);
879
880 OutStreamer->AddComment(T: "on-fault: " + HandlerLabel->getName());
881 OutStreamer->emitInstruction(Inst: MI, STI: getSubtargetInfo());
882}
883
884void X86AsmPrinter::LowerFENTRY_CALL(const MachineInstr &MI,
885 X86MCInstLower &MCIL) {
886 bool Is64Bits = Subtarget->is64Bit();
887 MCContext &Ctx = OutStreamer->getContext();
888 MCSymbol *fentry = Ctx.getOrCreateSymbol(Name: "__fentry__");
889 const MCSymbolRefExpr *Op = MCSymbolRefExpr::create(Symbol: fentry, Ctx);
890
891 EmitAndCountInstruction(
892 Inst&: MCInstBuilder(Is64Bits ? X86::CALL64pcrel32 : X86::CALLpcrel32)
893 .addExpr(Val: Op));
894}
895
896void X86AsmPrinter::LowerKCFI_CHECK(const MachineInstr &MI) {
897 assert(std::next(MI.getIterator())->isCall() &&
898 "KCFI_CHECK not followed by a call instruction");
899
900 // Adjust the offset for patchable-function-prefix. X86InstrInfo::getNop()
901 // returns a 1-byte X86::NOOP, which means the offset is the same in
902 // bytes. This assumes that patchable-function-prefix is the same for all
903 // functions.
904 const MachineFunction &MF = *MI.getMF();
905 int64_t PrefixNops = 0;
906 (void)MF.getFunction()
907 .getFnAttribute(Kind: "patchable-function-prefix")
908 .getValueAsString()
909 .getAsInteger(Radix: 10, Result&: PrefixNops);
910
911 // KCFI allows indirect calls to any location that's preceded by a valid
912 // type identifier. To avoid encoding the full constant into an instruction,
913 // and thus emitting potential call target gadgets at each indirect call
914 // site, load a negated constant to a register and compare that to the
915 // expected value at the call target.
916 const Register AddrReg = MI.getOperand(i: 0).getReg();
917 const uint32_t Type = MI.getOperand(i: 1).getImm();
918 // The check is immediately before the call. If the call target is in R10,
919 // we can clobber R11 for the check instead.
920 unsigned TempReg = AddrReg == X86::R10 ? X86::R11D : X86::R10D;
921 EmitAndCountInstruction(
922 Inst&: MCInstBuilder(X86::MOV32ri).addReg(Reg: TempReg).addImm(Val: -MaskKCFIType(Value: Type)));
923 EmitAndCountInstruction(Inst&: MCInstBuilder(X86::ADD32rm)
924 .addReg(Reg: X86::NoRegister)
925 .addReg(Reg: TempReg)
926 .addReg(Reg: AddrReg)
927 .addImm(Val: 1)
928 .addReg(Reg: X86::NoRegister)
929 .addImm(Val: -(PrefixNops + 4))
930 .addReg(Reg: X86::NoRegister));
931
932 MCSymbol *Pass = OutContext.createTempSymbol();
933 EmitAndCountInstruction(
934 Inst&: MCInstBuilder(X86::JCC_1)
935 .addExpr(Val: MCSymbolRefExpr::create(Symbol: Pass, Ctx&: OutContext))
936 .addImm(Val: X86::COND_E));
937
938 MCSymbol *Trap = OutContext.createTempSymbol();
939 OutStreamer->emitLabel(Symbol: Trap);
940 EmitAndCountInstruction(Inst&: MCInstBuilder(X86::TRAP));
941 emitKCFITrapEntry(MF, Symbol: Trap);
942 OutStreamer->emitLabel(Symbol: Pass);
943}
944
945void X86AsmPrinter::LowerASAN_CHECK_MEMACCESS(const MachineInstr &MI) {
946 // FIXME: Make this work on non-ELF.
947 if (!TM.getTargetTriple().isOSBinFormatELF()) {
948 report_fatal_error(reason: "llvm.asan.check.memaccess only supported on ELF");
949 return;
950 }
951
952 const auto &Reg = MI.getOperand(i: 0).getReg();
953 ASanAccessInfo AccessInfo(MI.getOperand(i: 1).getImm());
954
955 uint64_t ShadowBase;
956 int MappingScale;
957 bool OrShadowOffset;
958 getAddressSanitizerParams(TargetTriple: TM.getTargetTriple(), LongSize: 64, IsKasan: AccessInfo.CompileKernel,
959 ShadowBase: &ShadowBase, MappingScale: &MappingScale, OrShadowOffset: &OrShadowOffset);
960
961 StringRef Name = AccessInfo.IsWrite ? "store" : "load";
962 StringRef Op = OrShadowOffset ? "or" : "add";
963 std::string SymName = ("__asan_check_" + Name + "_" + Op + "_" +
964 Twine(1ULL << AccessInfo.AccessSizeIndex) + "_" +
965 TM.getMCRegisterInfo()->getName(RegNo: Reg.asMCReg()))
966 .str();
967 if (OrShadowOffset)
968 report_fatal_error(
969 reason: "OrShadowOffset is not supported with optimized callbacks");
970
971 EmitAndCountInstruction(
972 Inst&: MCInstBuilder(X86::CALL64pcrel32)
973 .addExpr(Val: MCSymbolRefExpr::create(
974 Symbol: OutContext.getOrCreateSymbol(Name: SymName), Ctx&: OutContext)));
975}
976
977void X86AsmPrinter::LowerPATCHABLE_OP(const MachineInstr &MI,
978 X86MCInstLower &MCIL) {
979 // PATCHABLE_OP minsize
980
981 NoAutoPaddingScope NoPadScope(*OutStreamer);
982
983 auto NextMI = std::find_if(first: std::next(x: MI.getIterator()),
984 last: MI.getParent()->end().getInstrIterator(),
985 pred: [](auto &II) { return !II.isMetaInstruction(); });
986
987 SmallString<256> Code;
988 unsigned MinSize = MI.getOperand(i: 0).getImm();
989
990 if (NextMI != MI.getParent()->end() && !NextMI->isInlineAsm()) {
991 // Lower the next MachineInstr to find its byte size.
992 // If the next instruction is inline assembly, we skip lowering it for now,
993 // and assume we should always generate NOPs.
994 MCInst MCI;
995 MCIL.Lower(MI: &*NextMI, OutMI&: MCI);
996
997 SmallVector<MCFixup, 4> Fixups;
998 CodeEmitter->encodeInstruction(Inst: MCI, CB&: Code, Fixups, STI: getSubtargetInfo());
999 }
1000
1001 if (Code.size() < MinSize) {
1002 if (MinSize == 2 && Subtarget->is32Bit() &&
1003 Subtarget->isTargetWindowsMSVC() &&
1004 (Subtarget->getCPU().empty() || Subtarget->getCPU() == "pentium3")) {
1005 // For compatibility reasons, when targetting MSVC, it is important to
1006 // generate a 'legacy' NOP in the form of a 8B FF MOV EDI, EDI. Some tools
1007 // rely specifically on this pattern to be able to patch a function.
1008 // This is only for 32-bit targets, when using /arch:IA32 or /arch:SSE.
1009 OutStreamer->emitInstruction(
1010 Inst: MCInstBuilder(X86::MOV32rr_REV).addReg(Reg: X86::EDI).addReg(Reg: X86::EDI),
1011 STI: *Subtarget);
1012 } else {
1013 unsigned NopSize = emitNop(OS&: *OutStreamer, NumBytes: MinSize, Subtarget);
1014 assert(NopSize == MinSize && "Could not implement MinSize!");
1015 (void)NopSize;
1016 }
1017 }
1018}
1019
1020// Lower a stackmap of the form:
1021// <id>, <shadowBytes>, ...
1022void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
1023 SMShadowTracker.emitShadowPadding(OutStreamer&: *OutStreamer, STI: getSubtargetInfo());
1024
1025 auto &Ctx = OutStreamer->getContext();
1026 MCSymbol *MILabel = Ctx.createTempSymbol();
1027 OutStreamer->emitLabel(Symbol: MILabel);
1028
1029 SM.recordStackMap(L: *MILabel, MI);
1030 unsigned NumShadowBytes = MI.getOperand(i: 1).getImm();
1031 SMShadowTracker.reset(RequiredSize: NumShadowBytes);
1032}
1033
1034// Lower a patchpoint of the form:
1035// [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
1036void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
1037 X86MCInstLower &MCIL) {
1038 assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64");
1039
1040 SMShadowTracker.emitShadowPadding(OutStreamer&: *OutStreamer, STI: getSubtargetInfo());
1041
1042 NoAutoPaddingScope NoPadScope(*OutStreamer);
1043
1044 auto &Ctx = OutStreamer->getContext();
1045 MCSymbol *MILabel = Ctx.createTempSymbol();
1046 OutStreamer->emitLabel(Symbol: MILabel);
1047 SM.recordPatchPoint(L: *MILabel, MI);
1048
1049 PatchPointOpers opers(&MI);
1050 unsigned ScratchIdx = opers.getNextScratchIdx();
1051 unsigned EncodedBytes = 0;
1052 const MachineOperand &CalleeMO = opers.getCallTarget();
1053
1054 // Check for null target. If target is non-null (i.e. is non-zero or is
1055 // symbolic) then emit a call.
1056 if (!(CalleeMO.isImm() && !CalleeMO.getImm())) {
1057 MCOperand CalleeMCOp;
1058 switch (CalleeMO.getType()) {
1059 default:
1060 /// FIXME: Add a verifier check for bad callee types.
1061 llvm_unreachable("Unrecognized callee operand type.");
1062 case MachineOperand::MO_Immediate:
1063 if (CalleeMO.getImm())
1064 CalleeMCOp = MCOperand::createImm(Val: CalleeMO.getImm());
1065 break;
1066 case MachineOperand::MO_ExternalSymbol:
1067 case MachineOperand::MO_GlobalAddress:
1068 CalleeMCOp = MCIL.LowerSymbolOperand(MO: CalleeMO,
1069 Sym: MCIL.GetSymbolFromOperand(MO: CalleeMO));
1070 break;
1071 }
1072
1073 // Emit MOV to materialize the target address and the CALL to target.
1074 // This is encoded with 12-13 bytes, depending on which register is used.
1075 Register ScratchReg = MI.getOperand(i: ScratchIdx).getReg();
1076 if (X86II::isX86_64ExtendedReg(Reg: ScratchReg))
1077 EncodedBytes = 13;
1078 else
1079 EncodedBytes = 12;
1080
1081 EmitAndCountInstruction(
1082 Inst&: MCInstBuilder(X86::MOV64ri).addReg(Reg: ScratchReg).addOperand(Op: CalleeMCOp));
1083 // FIXME: Add retpoline support and remove this.
1084 if (Subtarget->useIndirectThunkCalls())
1085 report_fatal_error(
1086 reason: "Lowering patchpoint with thunks not yet implemented.");
1087 EmitAndCountInstruction(Inst&: MCInstBuilder(X86::CALL64r).addReg(Reg: ScratchReg));
1088 }
1089
1090 // Emit padding.
1091 unsigned NumBytes = opers.getNumPatchBytes();
1092 assert(NumBytes >= EncodedBytes &&
1093 "Patchpoint can't request size less than the length of a call.");
1094
1095 emitX86Nops(OS&: *OutStreamer, NumBytes: NumBytes - EncodedBytes, Subtarget);
1096}
1097
1098void X86AsmPrinter::LowerPATCHABLE_EVENT_CALL(const MachineInstr &MI,
1099 X86MCInstLower &MCIL) {
1100 assert(Subtarget->is64Bit() && "XRay custom events only supports X86-64");
1101
1102 NoAutoPaddingScope NoPadScope(*OutStreamer);
1103
1104 // We want to emit the following pattern, which follows the x86 calling
1105 // convention to prepare for the trampoline call to be patched in.
1106 //
1107 // .p2align 1, ...
1108 // .Lxray_event_sled_N:
1109 // jmp +N // jump across the instrumentation sled
1110 // ... // set up arguments in register
1111 // callq __xray_CustomEvent@plt // force dependency to symbol
1112 // ...
1113 // <jump here>
1114 //
1115 // After patching, it would look something like:
1116 //
1117 // nopw (2-byte nop)
1118 // ...
1119 // callq __xrayCustomEvent // already lowered
1120 // ...
1121 //
1122 // ---
1123 // First we emit the label and the jump.
1124 auto CurSled = OutContext.createTempSymbol(Name: "xray_event_sled_", AlwaysAddSuffix: true);
1125 OutStreamer->AddComment(T: "# XRay Custom Event Log");
1126 OutStreamer->emitCodeAlignment(Alignment: Align(2), STI: &getSubtargetInfo());
1127 OutStreamer->emitLabel(Symbol: CurSled);
1128
1129 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1130 // an operand (computed as an offset from the jmp instruction).
1131 // FIXME: Find another less hacky way do force the relative jump.
1132 OutStreamer->emitBinaryData(Data: "\xeb\x0f");
1133
1134 // The default C calling convention will place two arguments into %rcx and
1135 // %rdx -- so we only work with those.
1136 const Register DestRegs[] = {X86::RDI, X86::RSI};
1137 bool UsedMask[] = {false, false};
1138 // Filled out in loop.
1139 Register SrcRegs[] = {0, 0};
1140
1141 // Then we put the operands in the %rdi and %rsi registers. We spill the
1142 // values in the register before we clobber them, and mark them as used in
1143 // UsedMask. In case the arguments are already in the correct register, we use
1144 // emit nops appropriately sized to keep the sled the same size in every
1145 // situation.
1146 for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1147 if (auto Op = MCIL.LowerMachineOperand(MI: &MI, MO: MI.getOperand(i: I));
1148 Op.isValid()) {
1149 assert(Op.isReg() && "Only support arguments in registers");
1150 SrcRegs[I] = getX86SubSuperRegister(Reg: Op.getReg(), Size: 64);
1151 assert(SrcRegs[I].isValid() && "Invalid operand");
1152 if (SrcRegs[I] != DestRegs[I]) {
1153 UsedMask[I] = true;
1154 EmitAndCountInstruction(
1155 Inst&: MCInstBuilder(X86::PUSH64r).addReg(Reg: DestRegs[I]));
1156 } else {
1157 emitX86Nops(OS&: *OutStreamer, NumBytes: 4, Subtarget);
1158 }
1159 }
1160
1161 // Now that the register values are stashed, mov arguments into place.
1162 // FIXME: This doesn't work if one of the later SrcRegs is equal to an
1163 // earlier DestReg. We will have already overwritten over the register before
1164 // we can copy from it.
1165 for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1166 if (SrcRegs[I] != DestRegs[I])
1167 EmitAndCountInstruction(
1168 Inst&: MCInstBuilder(X86::MOV64rr).addReg(Reg: DestRegs[I]).addReg(Reg: SrcRegs[I]));
1169
1170 // We emit a hard dependency on the __xray_CustomEvent symbol, which is the
1171 // name of the trampoline to be implemented by the XRay runtime.
1172 auto TSym = OutContext.getOrCreateSymbol(Name: "__xray_CustomEvent");
1173 MachineOperand TOp = MachineOperand::CreateMCSymbol(Sym: TSym);
1174 if (isPositionIndependent())
1175 TOp.setTargetFlags(X86II::MO_PLT);
1176
1177 // Emit the call instruction.
1178 EmitAndCountInstruction(Inst&: MCInstBuilder(X86::CALL64pcrel32)
1179 .addOperand(Op: MCIL.LowerSymbolOperand(MO: TOp, Sym: TSym)));
1180
1181 // Restore caller-saved and used registers.
1182 for (unsigned I = sizeof UsedMask; I-- > 0;)
1183 if (UsedMask[I])
1184 EmitAndCountInstruction(Inst&: MCInstBuilder(X86::POP64r).addReg(Reg: DestRegs[I]));
1185 else
1186 emitX86Nops(OS&: *OutStreamer, NumBytes: 1, Subtarget);
1187
1188 OutStreamer->AddComment(T: "xray custom event end.");
1189
1190 // Record the sled version. Version 0 of this sled was spelled differently, so
1191 // we let the runtime handle the different offsets we're using. Version 2
1192 // changed the absolute address to a PC-relative address.
1193 recordSled(Sled: CurSled, MI, Kind: SledKind::CUSTOM_EVENT, Version: 2);
1194}
1195
1196void X86AsmPrinter::LowerPATCHABLE_TYPED_EVENT_CALL(const MachineInstr &MI,
1197 X86MCInstLower &MCIL) {
1198 assert(Subtarget->is64Bit() && "XRay typed events only supports X86-64");
1199
1200 NoAutoPaddingScope NoPadScope(*OutStreamer);
1201
1202 // We want to emit the following pattern, which follows the x86 calling
1203 // convention to prepare for the trampoline call to be patched in.
1204 //
1205 // .p2align 1, ...
1206 // .Lxray_event_sled_N:
1207 // jmp +N // jump across the instrumentation sled
1208 // ... // set up arguments in register
1209 // callq __xray_TypedEvent@plt // force dependency to symbol
1210 // ...
1211 // <jump here>
1212 //
1213 // After patching, it would look something like:
1214 //
1215 // nopw (2-byte nop)
1216 // ...
1217 // callq __xrayTypedEvent // already lowered
1218 // ...
1219 //
1220 // ---
1221 // First we emit the label and the jump.
1222 auto CurSled = OutContext.createTempSymbol(Name: "xray_typed_event_sled_", AlwaysAddSuffix: true);
1223 OutStreamer->AddComment(T: "# XRay Typed Event Log");
1224 OutStreamer->emitCodeAlignment(Alignment: Align(2), STI: &getSubtargetInfo());
1225 OutStreamer->emitLabel(Symbol: CurSled);
1226
1227 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1228 // an operand (computed as an offset from the jmp instruction).
1229 // FIXME: Find another less hacky way do force the relative jump.
1230 OutStreamer->emitBinaryData(Data: "\xeb\x14");
1231
1232 // An x86-64 convention may place three arguments into %rcx, %rdx, and R8,
1233 // so we'll work with those. Or we may be called via SystemV, in which case
1234 // we don't have to do any translation.
1235 const Register DestRegs[] = {X86::RDI, X86::RSI, X86::RDX};
1236 bool UsedMask[] = {false, false, false};
1237
1238 // Will fill out src regs in the loop.
1239 Register SrcRegs[] = {0, 0, 0};
1240
1241 // Then we put the operands in the SystemV registers. We spill the values in
1242 // the registers before we clobber them, and mark them as used in UsedMask.
1243 // In case the arguments are already in the correct register, we emit nops
1244 // appropriately sized to keep the sled the same size in every situation.
1245 for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1246 if (auto Op = MCIL.LowerMachineOperand(MI: &MI, MO: MI.getOperand(i: I));
1247 Op.isValid()) {
1248 // TODO: Is register only support adequate?
1249 assert(Op.isReg() && "Only supports arguments in registers");
1250 SrcRegs[I] = getX86SubSuperRegister(Reg: Op.getReg(), Size: 64);
1251 assert(SrcRegs[I].isValid() && "Invalid operand");
1252 if (SrcRegs[I] != DestRegs[I]) {
1253 UsedMask[I] = true;
1254 EmitAndCountInstruction(
1255 Inst&: MCInstBuilder(X86::PUSH64r).addReg(Reg: DestRegs[I]));
1256 } else {
1257 emitX86Nops(OS&: *OutStreamer, NumBytes: 4, Subtarget);
1258 }
1259 }
1260
1261 // In the above loop we only stash all of the destination registers or emit
1262 // nops if the arguments are already in the right place. Doing the actually
1263 // moving is postponed until after all the registers are stashed so nothing
1264 // is clobbers. We've already added nops to account for the size of mov and
1265 // push if the register is in the right place, so we only have to worry about
1266 // emitting movs.
1267 // FIXME: This doesn't work if one of the later SrcRegs is equal to an
1268 // earlier DestReg. We will have already overwritten over the register before
1269 // we can copy from it.
1270 for (unsigned I = 0; I < MI.getNumOperands(); ++I)
1271 if (UsedMask[I])
1272 EmitAndCountInstruction(
1273 Inst&: MCInstBuilder(X86::MOV64rr).addReg(Reg: DestRegs[I]).addReg(Reg: SrcRegs[I]));
1274
1275 // We emit a hard dependency on the __xray_TypedEvent symbol, which is the
1276 // name of the trampoline to be implemented by the XRay runtime.
1277 auto TSym = OutContext.getOrCreateSymbol(Name: "__xray_TypedEvent");
1278 MachineOperand TOp = MachineOperand::CreateMCSymbol(Sym: TSym);
1279 if (isPositionIndependent())
1280 TOp.setTargetFlags(X86II::MO_PLT);
1281
1282 // Emit the call instruction.
1283 EmitAndCountInstruction(Inst&: MCInstBuilder(X86::CALL64pcrel32)
1284 .addOperand(Op: MCIL.LowerSymbolOperand(MO: TOp, Sym: TSym)));
1285
1286 // Restore caller-saved and used registers.
1287 for (unsigned I = sizeof UsedMask; I-- > 0;)
1288 if (UsedMask[I])
1289 EmitAndCountInstruction(Inst&: MCInstBuilder(X86::POP64r).addReg(Reg: DestRegs[I]));
1290 else
1291 emitX86Nops(OS&: *OutStreamer, NumBytes: 1, Subtarget);
1292
1293 OutStreamer->AddComment(T: "xray typed event end.");
1294
1295 // Record the sled version.
1296 recordSled(Sled: CurSled, MI, Kind: SledKind::TYPED_EVENT, Version: 2);
1297}
1298
1299void X86AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI,
1300 X86MCInstLower &MCIL) {
1301
1302 NoAutoPaddingScope NoPadScope(*OutStreamer);
1303
1304 const Function &F = MF->getFunction();
1305 if (F.hasFnAttribute(Kind: "patchable-function-entry")) {
1306 unsigned Num;
1307 if (F.getFnAttribute(Kind: "patchable-function-entry")
1308 .getValueAsString()
1309 .getAsInteger(Radix: 10, Result&: Num))
1310 return;
1311 emitX86Nops(OS&: *OutStreamer, NumBytes: Num, Subtarget);
1312 return;
1313 }
1314 // We want to emit the following pattern:
1315 //
1316 // .p2align 1, ...
1317 // .Lxray_sled_N:
1318 // jmp .tmpN
1319 // # 9 bytes worth of noops
1320 //
1321 // We need the 9 bytes because at runtime, we'd be patching over the full 11
1322 // bytes with the following pattern:
1323 //
1324 // mov %r10, <function id, 32-bit> // 6 bytes
1325 // call <relative offset, 32-bits> // 5 bytes
1326 //
1327 auto CurSled = OutContext.createTempSymbol(Name: "xray_sled_", AlwaysAddSuffix: true);
1328 OutStreamer->emitCodeAlignment(Alignment: Align(2), STI: &getSubtargetInfo());
1329 OutStreamer->emitLabel(Symbol: CurSled);
1330
1331 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1332 // an operand (computed as an offset from the jmp instruction).
1333 // FIXME: Find another less hacky way do force the relative jump.
1334 OutStreamer->emitBytes(Data: "\xeb\x09");
1335 emitX86Nops(OS&: *OutStreamer, NumBytes: 9, Subtarget);
1336 recordSled(Sled: CurSled, MI, Kind: SledKind::FUNCTION_ENTER, Version: 2);
1337}
1338
1339void X86AsmPrinter::LowerPATCHABLE_RET(const MachineInstr &MI,
1340 X86MCInstLower &MCIL) {
1341 NoAutoPaddingScope NoPadScope(*OutStreamer);
1342
1343 // Since PATCHABLE_RET takes the opcode of the return statement as an
1344 // argument, we use that to emit the correct form of the RET that we want.
1345 // i.e. when we see this:
1346 //
1347 // PATCHABLE_RET X86::RET ...
1348 //
1349 // We should emit the RET followed by sleds.
1350 //
1351 // .p2align 1, ...
1352 // .Lxray_sled_N:
1353 // ret # or equivalent instruction
1354 // # 10 bytes worth of noops
1355 //
1356 // This just makes sure that the alignment for the next instruction is 2.
1357 auto CurSled = OutContext.createTempSymbol(Name: "xray_sled_", AlwaysAddSuffix: true);
1358 OutStreamer->emitCodeAlignment(Alignment: Align(2), STI: &getSubtargetInfo());
1359 OutStreamer->emitLabel(Symbol: CurSled);
1360 unsigned OpCode = MI.getOperand(i: 0).getImm();
1361 MCInst Ret;
1362 Ret.setOpcode(OpCode);
1363 for (auto &MO : drop_begin(RangeOrContainer: MI.operands()))
1364 if (auto Op = MCIL.LowerMachineOperand(MI: &MI, MO); Op.isValid())
1365 Ret.addOperand(Op);
1366 OutStreamer->emitInstruction(Inst: Ret, STI: getSubtargetInfo());
1367 emitX86Nops(OS&: *OutStreamer, NumBytes: 10, Subtarget);
1368 recordSled(Sled: CurSled, MI, Kind: SledKind::FUNCTION_EXIT, Version: 2);
1369}
1370
1371void X86AsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI,
1372 X86MCInstLower &MCIL) {
1373 MCInst TC;
1374 TC.setOpcode(convertTailJumpOpcode(Opcode: MI.getOperand(i: 0).getImm()));
1375 // Drop the tail jump opcode.
1376 auto TCOperands = drop_begin(RangeOrContainer: MI.operands());
1377 bool IsConditional = TC.getOpcode() == X86::JCC_1;
1378 MCSymbol *FallthroughLabel;
1379 if (IsConditional) {
1380 // Rewrite:
1381 // je target
1382 //
1383 // To:
1384 // jne .fallthrough
1385 // .p2align 1, ...
1386 // .Lxray_sled_N:
1387 // SLED_CODE
1388 // jmp target
1389 // .fallthrough:
1390 FallthroughLabel = OutContext.createTempSymbol();
1391 EmitToStreamer(
1392 S&: *OutStreamer,
1393 Inst: MCInstBuilder(X86::JCC_1)
1394 .addExpr(Val: MCSymbolRefExpr::create(Symbol: FallthroughLabel, Ctx&: OutContext))
1395 .addImm(Val: X86::GetOppositeBranchCondition(
1396 CC: static_cast<X86::CondCode>(MI.getOperand(i: 2).getImm()))));
1397 TC.setOpcode(X86::JMP_1);
1398 // Drop the condition code.
1399 TCOperands = drop_end(RangeOrContainer&: TCOperands);
1400 }
1401
1402 NoAutoPaddingScope NoPadScope(*OutStreamer);
1403
1404 // Like PATCHABLE_RET, we have the actual instruction in the operands to this
1405 // instruction so we lower that particular instruction and its operands.
1406 // Unlike PATCHABLE_RET though, we put the sled before the JMP, much like how
1407 // we do it for PATCHABLE_FUNCTION_ENTER. The sled should be very similar to
1408 // the PATCHABLE_FUNCTION_ENTER case, followed by the lowering of the actual
1409 // tail call much like how we have it in PATCHABLE_RET.
1410 auto CurSled = OutContext.createTempSymbol(Name: "xray_sled_", AlwaysAddSuffix: true);
1411 OutStreamer->emitCodeAlignment(Alignment: Align(2), STI: &getSubtargetInfo());
1412 OutStreamer->emitLabel(Symbol: CurSled);
1413 auto Target = OutContext.createTempSymbol();
1414
1415 // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as
1416 // an operand (computed as an offset from the jmp instruction).
1417 // FIXME: Find another less hacky way do force the relative jump.
1418 OutStreamer->emitBytes(Data: "\xeb\x09");
1419 emitX86Nops(OS&: *OutStreamer, NumBytes: 9, Subtarget);
1420 OutStreamer->emitLabel(Symbol: Target);
1421 recordSled(Sled: CurSled, MI, Kind: SledKind::TAIL_CALL, Version: 2);
1422
1423 // Before emitting the instruction, add a comment to indicate that this is
1424 // indeed a tail call.
1425 OutStreamer->AddComment(T: "TAILCALL");
1426 for (auto &MO : TCOperands)
1427 if (auto Op = MCIL.LowerMachineOperand(MI: &MI, MO); Op.isValid())
1428 TC.addOperand(Op);
1429 OutStreamer->emitInstruction(Inst: TC, STI: getSubtargetInfo());
1430
1431 if (IsConditional)
1432 OutStreamer->emitLabel(Symbol: FallthroughLabel);
1433}
1434
1435static unsigned getSrcIdx(const MachineInstr* MI, unsigned SrcIdx) {
1436 if (X86II::isKMasked(TSFlags: MI->getDesc().TSFlags)) {
1437 // Skip mask operand.
1438 ++SrcIdx;
1439 if (X86II::isKMergeMasked(TSFlags: MI->getDesc().TSFlags)) {
1440 // Skip passthru operand.
1441 ++SrcIdx;
1442 }
1443 }
1444 return SrcIdx;
1445}
1446
1447static void printDstRegisterName(raw_ostream &CS, const MachineInstr *MI,
1448 unsigned SrcOpIdx) {
1449 const MachineOperand &DstOp = MI->getOperand(i: 0);
1450 CS << X86ATTInstPrinter::getRegisterName(Reg: DstOp.getReg());
1451
1452 // Handle AVX512 MASK/MASXZ write mask comments.
1453 // MASK: zmmX {%kY}
1454 // MASKZ: zmmX {%kY} {z}
1455 if (X86II::isKMasked(TSFlags: MI->getDesc().TSFlags)) {
1456 const MachineOperand &WriteMaskOp = MI->getOperand(i: SrcOpIdx - 1);
1457 StringRef Mask = X86ATTInstPrinter::getRegisterName(Reg: WriteMaskOp.getReg());
1458 CS << " {%" << Mask << "}";
1459 if (!X86II::isKMergeMasked(TSFlags: MI->getDesc().TSFlags)) {
1460 CS << " {z}";
1461 }
1462 }
1463}
1464
1465static void printShuffleMask(raw_ostream &CS, StringRef Src1Name,
1466 StringRef Src2Name, ArrayRef<int> Mask) {
1467 // One source operand, fix the mask to print all elements in one span.
1468 SmallVector<int, 8> ShuffleMask(Mask);
1469 if (Src1Name == Src2Name)
1470 for (int i = 0, e = ShuffleMask.size(); i != e; ++i)
1471 if (ShuffleMask[i] >= e)
1472 ShuffleMask[i] -= e;
1473
1474 for (int i = 0, e = ShuffleMask.size(); i != e; ++i) {
1475 if (i != 0)
1476 CS << ",";
1477 if (ShuffleMask[i] == SM_SentinelZero) {
1478 CS << "zero";
1479 continue;
1480 }
1481
1482 // Otherwise, it must come from src1 or src2. Print the span of elements
1483 // that comes from this src.
1484 bool isSrc1 = ShuffleMask[i] < (int)e;
1485 CS << (isSrc1 ? Src1Name : Src2Name) << '[';
1486
1487 bool IsFirst = true;
1488 while (i != e && ShuffleMask[i] != SM_SentinelZero &&
1489 (ShuffleMask[i] < (int)e) == isSrc1) {
1490 if (!IsFirst)
1491 CS << ',';
1492 else
1493 IsFirst = false;
1494 if (ShuffleMask[i] == SM_SentinelUndef)
1495 CS << "u";
1496 else
1497 CS << ShuffleMask[i] % (int)e;
1498 ++i;
1499 }
1500 CS << ']';
1501 --i; // For loop increments element #.
1502 }
1503}
1504
1505static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx,
1506 unsigned SrcOp2Idx, ArrayRef<int> Mask) {
1507 std::string Comment;
1508
1509 const MachineOperand &SrcOp1 = MI->getOperand(i: SrcOp1Idx);
1510 const MachineOperand &SrcOp2 = MI->getOperand(i: SrcOp2Idx);
1511 StringRef Src1Name = SrcOp1.isReg()
1512 ? X86ATTInstPrinter::getRegisterName(Reg: SrcOp1.getReg())
1513 : "mem";
1514 StringRef Src2Name = SrcOp2.isReg()
1515 ? X86ATTInstPrinter::getRegisterName(Reg: SrcOp2.getReg())
1516 : "mem";
1517
1518 raw_string_ostream CS(Comment);
1519 printDstRegisterName(CS, MI, SrcOpIdx: SrcOp1Idx);
1520 CS << " = ";
1521 printShuffleMask(CS, Src1Name, Src2Name, Mask);
1522
1523 return Comment;
1524}
1525
1526static void printConstant(const APInt &Val, raw_ostream &CS,
1527 bool PrintZero = false) {
1528 if (Val.getBitWidth() <= 64) {
1529 CS << (PrintZero ? 0ULL : Val.getZExtValue());
1530 } else {
1531 // print multi-word constant as (w0,w1)
1532 CS << "(";
1533 for (int i = 0, N = Val.getNumWords(); i < N; ++i) {
1534 if (i > 0)
1535 CS << ",";
1536 CS << (PrintZero ? 0ULL : Val.getRawData()[i]);
1537 }
1538 CS << ")";
1539 }
1540}
1541
1542static void printConstant(const APFloat &Flt, raw_ostream &CS,
1543 bool PrintZero = false) {
1544 SmallString<32> Str;
1545 // Force scientific notation to distinguish from integers.
1546 if (PrintZero)
1547 APFloat::getZero(Sem: Flt.getSemantics()).toString(Str, FormatPrecision: 0, FormatMaxPadding: 0);
1548 else
1549 Flt.toString(Str, FormatPrecision: 0, FormatMaxPadding: 0);
1550 CS << Str;
1551}
1552
1553static void printConstant(const Constant *COp, unsigned BitWidth,
1554 raw_ostream &CS, bool PrintZero = false) {
1555 if (isa<UndefValue>(Val: COp)) {
1556 CS << "u";
1557 } else if (auto *CI = dyn_cast<ConstantInt>(Val: COp)) {
1558 if (auto VTy = dyn_cast<FixedVectorType>(Val: CI->getType())) {
1559 for (unsigned I = 0, E = VTy->getNumElements(); I != E; ++I) {
1560 if (I != 0)
1561 CS << ',';
1562 printConstant(Val: CI->getValue(), CS, PrintZero);
1563 }
1564 } else
1565 printConstant(Val: CI->getValue(), CS, PrintZero);
1566 } else if (auto *CF = dyn_cast<ConstantFP>(Val: COp)) {
1567 if (auto VTy = dyn_cast<FixedVectorType>(Val: CF->getType())) {
1568 unsigned EltBits = VTy->getScalarSizeInBits();
1569 unsigned E = std::min(a: BitWidth / EltBits, b: VTy->getNumElements());
1570 if ((BitWidth % EltBits) == 0) {
1571 for (unsigned I = 0; I != E; ++I) {
1572 if (I != 0)
1573 CS << ",";
1574 printConstant(Flt: CF->getValueAPF(), CS, PrintZero);
1575 }
1576 } else {
1577 CS << "?";
1578 }
1579 } else
1580 printConstant(Flt: CF->getValueAPF(), CS, PrintZero);
1581 } else if (auto *CDS = dyn_cast<ConstantDataSequential>(Val: COp)) {
1582 Type *EltTy = CDS->getElementType();
1583 bool IsInteger = EltTy->isIntegerTy();
1584 bool IsFP = EltTy->isHalfTy() || EltTy->isFloatTy() || EltTy->isDoubleTy();
1585 unsigned EltBits = EltTy->getPrimitiveSizeInBits();
1586 unsigned E = std::min(a: BitWidth / EltBits, b: (unsigned)CDS->getNumElements());
1587 if ((BitWidth % EltBits) == 0) {
1588 for (unsigned I = 0; I != E; ++I) {
1589 if (I != 0)
1590 CS << ",";
1591 if (IsInteger)
1592 printConstant(Val: CDS->getElementAsAPInt(i: I), CS, PrintZero);
1593 else if (IsFP)
1594 printConstant(Flt: CDS->getElementAsAPFloat(i: I), CS, PrintZero);
1595 else
1596 CS << "?";
1597 }
1598 } else {
1599 CS << "?";
1600 }
1601 } else if (auto *CV = dyn_cast<ConstantVector>(Val: COp)) {
1602 unsigned EltBits = CV->getType()->getScalarSizeInBits();
1603 unsigned E = std::min(a: BitWidth / EltBits, b: CV->getNumOperands());
1604 if ((BitWidth % EltBits) == 0) {
1605 for (unsigned I = 0; I != E; ++I) {
1606 if (I != 0)
1607 CS << ",";
1608 printConstant(COp: CV->getOperand(i_nocapture: I), BitWidth: EltBits, CS, PrintZero);
1609 }
1610 } else {
1611 CS << "?";
1612 }
1613 } else {
1614 CS << "?";
1615 }
1616}
1617
1618static void printZeroUpperMove(const MachineInstr *MI, MCStreamer &OutStreamer,
1619 int SclWidth, int VecWidth,
1620 const char *ShuffleComment) {
1621 unsigned SrcIdx = getSrcIdx(MI, SrcIdx: 1);
1622
1623 std::string Comment;
1624 raw_string_ostream CS(Comment);
1625 printDstRegisterName(CS, MI, SrcOpIdx: SrcIdx);
1626 CS << " = ";
1627
1628 if (auto *C = X86::getConstantFromPool(MI: *MI, OpNo: SrcIdx)) {
1629 CS << "[";
1630 printConstant(COp: C, BitWidth: SclWidth, CS);
1631 for (int I = 1, E = VecWidth / SclWidth; I < E; ++I) {
1632 CS << ",";
1633 printConstant(COp: C, BitWidth: SclWidth, CS, PrintZero: true);
1634 }
1635 CS << "]";
1636 OutStreamer.AddComment(T: CS.str());
1637 return; // early-out
1638 }
1639
1640 // We didn't find a constant load, fallback to a shuffle mask decode.
1641 CS << ShuffleComment;
1642 OutStreamer.AddComment(T: CS.str());
1643}
1644
1645static void printBroadcast(const MachineInstr *MI, MCStreamer &OutStreamer,
1646 int Repeats, int BitWidth) {
1647 unsigned SrcIdx = getSrcIdx(MI, SrcIdx: 1);
1648 if (auto *C = X86::getConstantFromPool(MI: *MI, OpNo: SrcIdx)) {
1649 std::string Comment;
1650 raw_string_ostream CS(Comment);
1651 printDstRegisterName(CS, MI, SrcOpIdx: SrcIdx);
1652 CS << " = [";
1653 for (int l = 0; l != Repeats; ++l) {
1654 if (l != 0)
1655 CS << ",";
1656 printConstant(COp: C, BitWidth, CS);
1657 }
1658 CS << "]";
1659 OutStreamer.AddComment(T: CS.str());
1660 }
1661}
1662
1663static bool printExtend(const MachineInstr *MI, MCStreamer &OutStreamer,
1664 int SrcEltBits, int DstEltBits, bool IsSext) {
1665 unsigned SrcIdx = getSrcIdx(MI, SrcIdx: 1);
1666 auto *C = X86::getConstantFromPool(MI: *MI, OpNo: SrcIdx);
1667 if (C && C->getType()->getScalarSizeInBits() == unsigned(SrcEltBits)) {
1668 if (auto *CDS = dyn_cast<ConstantDataSequential>(Val: C)) {
1669 int NumElts = CDS->getNumElements();
1670 std::string Comment;
1671 raw_string_ostream CS(Comment);
1672 printDstRegisterName(CS, MI, SrcOpIdx: SrcIdx);
1673 CS << " = [";
1674 for (int i = 0; i != NumElts; ++i) {
1675 if (i != 0)
1676 CS << ",";
1677 if (CDS->getElementType()->isIntegerTy()) {
1678 APInt Elt = CDS->getElementAsAPInt(i);
1679 Elt = IsSext ? Elt.sext(width: DstEltBits) : Elt.zext(width: DstEltBits);
1680 printConstant(Val: Elt, CS);
1681 } else
1682 CS << "?";
1683 }
1684 CS << "]";
1685 OutStreamer.AddComment(T: CS.str());
1686 return true;
1687 }
1688 }
1689
1690 return false;
1691}
1692static void printSignExtend(const MachineInstr *MI, MCStreamer &OutStreamer,
1693 int SrcEltBits, int DstEltBits) {
1694 printExtend(MI, OutStreamer, SrcEltBits, DstEltBits, IsSext: true);
1695}
1696static void printZeroExtend(const MachineInstr *MI, MCStreamer &OutStreamer,
1697 int SrcEltBits, int DstEltBits) {
1698 if (printExtend(MI, OutStreamer, SrcEltBits, DstEltBits, IsSext: false))
1699 return;
1700
1701 // We didn't find a constant load, fallback to a shuffle mask decode.
1702 std::string Comment;
1703 raw_string_ostream CS(Comment);
1704 printDstRegisterName(CS, MI, SrcOpIdx: getSrcIdx(MI, SrcIdx: 1));
1705 CS << " = ";
1706
1707 SmallVector<int> Mask;
1708 unsigned Width = X86::getVectorRegisterWidth(Info: MI->getDesc().operands()[0]);
1709 assert((Width % DstEltBits) == 0 && (DstEltBits % SrcEltBits) == 0 &&
1710 "Illegal extension ratio");
1711 DecodeZeroExtendMask(SrcScalarBits: SrcEltBits, DstScalarBits: DstEltBits, NumDstElts: Width / DstEltBits, IsAnyExtend: false, ShuffleMask&: Mask);
1712 printShuffleMask(CS, Src1Name: "mem", Src2Name: "", Mask);
1713
1714 OutStreamer.AddComment(T: CS.str());
1715}
1716
1717void X86AsmPrinter::EmitSEHInstruction(const MachineInstr *MI) {
1718 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
1719 assert((getSubtarget().isOSWindows() || getSubtarget().isUEFI()) &&
1720 "SEH_ instruction Windows and UEFI only");
1721
1722 // Use the .cv_fpo directives if we're emitting CodeView on 32-bit x86.
1723 if (EmitFPOData) {
1724 X86TargetStreamer *XTS =
1725 static_cast<X86TargetStreamer *>(OutStreamer->getTargetStreamer());
1726 switch (MI->getOpcode()) {
1727 case X86::SEH_PushReg:
1728 XTS->emitFPOPushReg(Reg: MI->getOperand(i: 0).getImm());
1729 break;
1730 case X86::SEH_StackAlloc:
1731 XTS->emitFPOStackAlloc(StackAlloc: MI->getOperand(i: 0).getImm());
1732 break;
1733 case X86::SEH_StackAlign:
1734 XTS->emitFPOStackAlign(Align: MI->getOperand(i: 0).getImm());
1735 break;
1736 case X86::SEH_SetFrame:
1737 assert(MI->getOperand(1).getImm() == 0 &&
1738 ".cv_fpo_setframe takes no offset");
1739 XTS->emitFPOSetFrame(Reg: MI->getOperand(i: 0).getImm());
1740 break;
1741 case X86::SEH_EndPrologue:
1742 XTS->emitFPOEndPrologue();
1743 break;
1744 case X86::SEH_SaveReg:
1745 case X86::SEH_SaveXMM:
1746 case X86::SEH_PushFrame:
1747 llvm_unreachable("SEH_ directive incompatible with FPO");
1748 break;
1749 default:
1750 llvm_unreachable("expected SEH_ instruction");
1751 }
1752 return;
1753 }
1754
1755 // Otherwise, use the .seh_ directives for all other Windows platforms.
1756 switch (MI->getOpcode()) {
1757 case X86::SEH_PushReg:
1758 OutStreamer->emitWinCFIPushReg(Register: MI->getOperand(i: 0).getImm());
1759 break;
1760
1761 case X86::SEH_SaveReg:
1762 OutStreamer->emitWinCFISaveReg(Register: MI->getOperand(i: 0).getImm(),
1763 Offset: MI->getOperand(i: 1).getImm());
1764 break;
1765
1766 case X86::SEH_SaveXMM:
1767 OutStreamer->emitWinCFISaveXMM(Register: MI->getOperand(i: 0).getImm(),
1768 Offset: MI->getOperand(i: 1).getImm());
1769 break;
1770
1771 case X86::SEH_StackAlloc:
1772 OutStreamer->emitWinCFIAllocStack(Size: MI->getOperand(i: 0).getImm());
1773 break;
1774
1775 case X86::SEH_SetFrame:
1776 OutStreamer->emitWinCFISetFrame(Register: MI->getOperand(i: 0).getImm(),
1777 Offset: MI->getOperand(i: 1).getImm());
1778 break;
1779
1780 case X86::SEH_PushFrame:
1781 OutStreamer->emitWinCFIPushFrame(Code: MI->getOperand(i: 0).getImm());
1782 break;
1783
1784 case X86::SEH_EndPrologue:
1785 OutStreamer->emitWinCFIEndProlog();
1786 break;
1787
1788 case X86::SEH_BeginEpilogue:
1789 OutStreamer->emitWinCFIBeginEpilogue();
1790 break;
1791
1792 case X86::SEH_EndEpilogue:
1793 OutStreamer->emitWinCFIEndEpilogue();
1794 break;
1795
1796 case X86::SEH_UnwindV2Start:
1797 OutStreamer->emitWinCFIUnwindV2Start();
1798 break;
1799
1800 case X86::SEH_UnwindVersion:
1801 OutStreamer->emitWinCFIUnwindVersion(Version: MI->getOperand(i: 0).getImm());
1802 break;
1803
1804 default:
1805 llvm_unreachable("expected SEH_ instruction");
1806 }
1807}
1808
1809static void addConstantComments(const MachineInstr *MI,
1810 MCStreamer &OutStreamer) {
1811 switch (MI->getOpcode()) {
1812 // Lower PSHUFB and VPERMILP normally but add a comment if we can find
1813 // a constant shuffle mask. We won't be able to do this at the MC layer
1814 // because the mask isn't an immediate.
1815 case X86::PSHUFBrm:
1816 case X86::VPSHUFBrm:
1817 case X86::VPSHUFBYrm:
1818 case X86::VPSHUFBZ128rm:
1819 case X86::VPSHUFBZ128rmk:
1820 case X86::VPSHUFBZ128rmkz:
1821 case X86::VPSHUFBZ256rm:
1822 case X86::VPSHUFBZ256rmk:
1823 case X86::VPSHUFBZ256rmkz:
1824 case X86::VPSHUFBZrm:
1825 case X86::VPSHUFBZrmk:
1826 case X86::VPSHUFBZrmkz: {
1827 unsigned SrcIdx = getSrcIdx(MI, SrcIdx: 1);
1828 if (auto *C = X86::getConstantFromPool(MI: *MI, OpNo: SrcIdx + 1)) {
1829 unsigned Width = X86::getVectorRegisterWidth(Info: MI->getDesc().operands()[0]);
1830 SmallVector<int, 64> Mask;
1831 DecodePSHUFBMask(C, Width, ShuffleMask&: Mask);
1832 if (!Mask.empty())
1833 OutStreamer.AddComment(T: getShuffleComment(MI, SrcOp1Idx: SrcIdx, SrcOp2Idx: SrcIdx, Mask));
1834 }
1835 break;
1836 }
1837
1838 case X86::VPERMILPSrm:
1839 case X86::VPERMILPSYrm:
1840 case X86::VPERMILPSZ128rm:
1841 case X86::VPERMILPSZ128rmk:
1842 case X86::VPERMILPSZ128rmkz:
1843 case X86::VPERMILPSZ256rm:
1844 case X86::VPERMILPSZ256rmk:
1845 case X86::VPERMILPSZ256rmkz:
1846 case X86::VPERMILPSZrm:
1847 case X86::VPERMILPSZrmk:
1848 case X86::VPERMILPSZrmkz: {
1849 unsigned SrcIdx = getSrcIdx(MI, SrcIdx: 1);
1850 if (auto *C = X86::getConstantFromPool(MI: *MI, OpNo: SrcIdx + 1)) {
1851 unsigned Width = X86::getVectorRegisterWidth(Info: MI->getDesc().operands()[0]);
1852 SmallVector<int, 16> Mask;
1853 DecodeVPERMILPMask(C, ElSize: 32, Width, ShuffleMask&: Mask);
1854 if (!Mask.empty())
1855 OutStreamer.AddComment(T: getShuffleComment(MI, SrcOp1Idx: SrcIdx, SrcOp2Idx: SrcIdx, Mask));
1856 }
1857 break;
1858 }
1859 case X86::VPERMILPDrm:
1860 case X86::VPERMILPDYrm:
1861 case X86::VPERMILPDZ128rm:
1862 case X86::VPERMILPDZ128rmk:
1863 case X86::VPERMILPDZ128rmkz:
1864 case X86::VPERMILPDZ256rm:
1865 case X86::VPERMILPDZ256rmk:
1866 case X86::VPERMILPDZ256rmkz:
1867 case X86::VPERMILPDZrm:
1868 case X86::VPERMILPDZrmk:
1869 case X86::VPERMILPDZrmkz: {
1870 unsigned SrcIdx = getSrcIdx(MI, SrcIdx: 1);
1871 if (auto *C = X86::getConstantFromPool(MI: *MI, OpNo: SrcIdx + 1)) {
1872 unsigned Width = X86::getVectorRegisterWidth(Info: MI->getDesc().operands()[0]);
1873 SmallVector<int, 16> Mask;
1874 DecodeVPERMILPMask(C, ElSize: 64, Width, ShuffleMask&: Mask);
1875 if (!Mask.empty())
1876 OutStreamer.AddComment(T: getShuffleComment(MI, SrcOp1Idx: SrcIdx, SrcOp2Idx: SrcIdx, Mask));
1877 }
1878 break;
1879 }
1880
1881 case X86::VPERMIL2PDrm:
1882 case X86::VPERMIL2PSrm:
1883 case X86::VPERMIL2PDYrm:
1884 case X86::VPERMIL2PSYrm: {
1885 assert(MI->getNumOperands() >= (3 + X86::AddrNumOperands + 1) &&
1886 "Unexpected number of operands!");
1887
1888 const MachineOperand &CtrlOp = MI->getOperand(i: MI->getNumOperands() - 1);
1889 if (!CtrlOp.isImm())
1890 break;
1891
1892 unsigned ElSize;
1893 switch (MI->getOpcode()) {
1894 default: llvm_unreachable("Invalid opcode");
1895 case X86::VPERMIL2PSrm: case X86::VPERMIL2PSYrm: ElSize = 32; break;
1896 case X86::VPERMIL2PDrm: case X86::VPERMIL2PDYrm: ElSize = 64; break;
1897 }
1898
1899 if (auto *C = X86::getConstantFromPool(MI: *MI, OpNo: 3)) {
1900 unsigned Width = X86::getVectorRegisterWidth(Info: MI->getDesc().operands()[0]);
1901 SmallVector<int, 16> Mask;
1902 DecodeVPERMIL2PMask(C, M2Z: (unsigned)CtrlOp.getImm(), ElSize, Width, ShuffleMask&: Mask);
1903 if (!Mask.empty())
1904 OutStreamer.AddComment(T: getShuffleComment(MI, SrcOp1Idx: 1, SrcOp2Idx: 2, Mask));
1905 }
1906 break;
1907 }
1908
1909 case X86::VPPERMrrm: {
1910 if (auto *C = X86::getConstantFromPool(MI: *MI, OpNo: 3)) {
1911 unsigned Width = X86::getVectorRegisterWidth(Info: MI->getDesc().operands()[0]);
1912 SmallVector<int, 16> Mask;
1913 DecodeVPPERMMask(C, Width, ShuffleMask&: Mask);
1914 if (!Mask.empty())
1915 OutStreamer.AddComment(T: getShuffleComment(MI, SrcOp1Idx: 1, SrcOp2Idx: 2, Mask));
1916 }
1917 break;
1918 }
1919
1920 case X86::MMX_MOVQ64rm: {
1921 if (auto *C = X86::getConstantFromPool(MI: *MI, OpNo: 1)) {
1922 std::string Comment;
1923 raw_string_ostream CS(Comment);
1924 const MachineOperand &DstOp = MI->getOperand(i: 0);
1925 CS << X86ATTInstPrinter::getRegisterName(Reg: DstOp.getReg()) << " = ";
1926 if (auto *CF = dyn_cast<ConstantFP>(Val: C)) {
1927 CS << "0x" << toString(I: CF->getValueAPF().bitcastToAPInt(), Radix: 16, Signed: false);
1928 OutStreamer.AddComment(T: CS.str());
1929 }
1930 }
1931 break;
1932 }
1933
1934#define INSTR_CASE(Prefix, Instr, Suffix, Postfix) \
1935 case X86::Prefix##Instr##Suffix##rm##Postfix:
1936
1937#define CASE_AVX512_ARITH_RM(Instr) \
1938 INSTR_CASE(V, Instr, Z128, ) \
1939 INSTR_CASE(V, Instr, Z128, k) \
1940 INSTR_CASE(V, Instr, Z128, kz) \
1941 INSTR_CASE(V, Instr, Z256, ) \
1942 INSTR_CASE(V, Instr, Z256, k) \
1943 INSTR_CASE(V, Instr, Z256, kz) \
1944 INSTR_CASE(V, Instr, Z, ) \
1945 INSTR_CASE(V, Instr, Z, k) \
1946 INSTR_CASE(V, Instr, Z, kz)
1947
1948#define CASE_ARITH_RM(Instr) \
1949 INSTR_CASE(, Instr, , ) /* SSE */ \
1950 INSTR_CASE(V, Instr, , ) /* AVX-128 */ \
1951 INSTR_CASE(V, Instr, Y, ) /* AVX-256 */ \
1952 INSTR_CASE(V, Instr, Z128, ) \
1953 INSTR_CASE(V, Instr, Z128, k) \
1954 INSTR_CASE(V, Instr, Z128, kz) \
1955 INSTR_CASE(V, Instr, Z256, ) \
1956 INSTR_CASE(V, Instr, Z256, k) \
1957 INSTR_CASE(V, Instr, Z256, kz) \
1958 INSTR_CASE(V, Instr, Z, ) \
1959 INSTR_CASE(V, Instr, Z, k) \
1960 INSTR_CASE(V, Instr, Z, kz)
1961
1962 // TODO: Add additional instructions when useful.
1963 CASE_ARITH_RM(PMADDUBSW)
1964 CASE_ARITH_RM(PMADDWD)
1965 CASE_ARITH_RM(PMULDQ)
1966 CASE_ARITH_RM(PMULUDQ)
1967 CASE_ARITH_RM(PMULLD)
1968 CASE_AVX512_ARITH_RM(PMULLQ)
1969 CASE_ARITH_RM(PMULLW)
1970 CASE_ARITH_RM(PMULHW)
1971 CASE_ARITH_RM(PMULHUW)
1972 CASE_ARITH_RM(PMULHRSW) {
1973 unsigned SrcIdx = getSrcIdx(MI, SrcIdx: 1);
1974 if (auto *C = X86::getConstantFromPool(MI: *MI, OpNo: SrcIdx + 1)) {
1975 std::string Comment;
1976 raw_string_ostream CS(Comment);
1977 unsigned VectorWidth =
1978 X86::getVectorRegisterWidth(Info: MI->getDesc().operands()[0]);
1979 CS << "[";
1980 printConstant(COp: C, BitWidth: VectorWidth, CS);
1981 CS << "]";
1982 OutStreamer.AddComment(T: CS.str());
1983 }
1984 break;
1985 }
1986
1987#define MASK_AVX512_CASE(Instr) \
1988 case Instr: \
1989 case Instr##k: \
1990 case Instr##kz:
1991
1992 case X86::MOVSDrm:
1993 case X86::VMOVSDrm:
1994 MASK_AVX512_CASE(X86::VMOVSDZrm)
1995 case X86::MOVSDrm_alt:
1996 case X86::VMOVSDrm_alt:
1997 case X86::VMOVSDZrm_alt:
1998 case X86::MOVQI2PQIrm:
1999 case X86::VMOVQI2PQIrm:
2000 case X86::VMOVQI2PQIZrm:
2001 printZeroUpperMove(MI, OutStreamer, SclWidth: 64, VecWidth: 128, ShuffleComment: "mem[0],zero");
2002 break;
2003
2004 MASK_AVX512_CASE(X86::VMOVSHZrm)
2005 case X86::VMOVSHZrm_alt:
2006 printZeroUpperMove(MI, OutStreamer, SclWidth: 16, VecWidth: 128,
2007 ShuffleComment: "mem[0],zero,zero,zero,zero,zero,zero,zero");
2008 break;
2009
2010 case X86::MOVSSrm:
2011 case X86::VMOVSSrm:
2012 MASK_AVX512_CASE(X86::VMOVSSZrm)
2013 case X86::MOVSSrm_alt:
2014 case X86::VMOVSSrm_alt:
2015 case X86::VMOVSSZrm_alt:
2016 case X86::MOVDI2PDIrm:
2017 case X86::VMOVDI2PDIrm:
2018 case X86::VMOVDI2PDIZrm:
2019 printZeroUpperMove(MI, OutStreamer, SclWidth: 32, VecWidth: 128, ShuffleComment: "mem[0],zero,zero,zero");
2020 break;
2021
2022#define MOV_CASE(Prefix, Suffix) \
2023 case X86::Prefix##MOVAPD##Suffix##rm: \
2024 case X86::Prefix##MOVAPS##Suffix##rm: \
2025 case X86::Prefix##MOVUPD##Suffix##rm: \
2026 case X86::Prefix##MOVUPS##Suffix##rm: \
2027 case X86::Prefix##MOVDQA##Suffix##rm: \
2028 case X86::Prefix##MOVDQU##Suffix##rm:
2029
2030#define MOV_AVX512_CASE(Suffix, Postfix) \
2031 case X86::VMOVDQA64##Suffix##rm##Postfix: \
2032 case X86::VMOVDQA32##Suffix##rm##Postfix: \
2033 case X86::VMOVDQU64##Suffix##rm##Postfix: \
2034 case X86::VMOVDQU32##Suffix##rm##Postfix: \
2035 case X86::VMOVDQU16##Suffix##rm##Postfix: \
2036 case X86::VMOVDQU8##Suffix##rm##Postfix: \
2037 case X86::VMOVAPS##Suffix##rm##Postfix: \
2038 case X86::VMOVAPD##Suffix##rm##Postfix: \
2039 case X86::VMOVUPS##Suffix##rm##Postfix: \
2040 case X86::VMOVUPD##Suffix##rm##Postfix:
2041
2042#define CASE_128_MOV_RM() \
2043 MOV_CASE(, ) /* SSE */ \
2044 MOV_CASE(V, ) /* AVX-128 */ \
2045 MOV_AVX512_CASE(Z128, ) \
2046 MOV_AVX512_CASE(Z128, k) \
2047 MOV_AVX512_CASE(Z128, kz)
2048
2049#define CASE_256_MOV_RM() \
2050 MOV_CASE(V, Y) /* AVX-256 */ \
2051 MOV_AVX512_CASE(Z256, ) \
2052 MOV_AVX512_CASE(Z256, k) \
2053 MOV_AVX512_CASE(Z256, kz) \
2054
2055#define CASE_512_MOV_RM() \
2056 MOV_AVX512_CASE(Z, ) \
2057 MOV_AVX512_CASE(Z, k) \
2058 MOV_AVX512_CASE(Z, kz) \
2059
2060 // For loads from a constant pool to a vector register, print the constant
2061 // loaded.
2062 CASE_128_MOV_RM()
2063 printBroadcast(MI, OutStreamer, Repeats: 1, BitWidth: 128);
2064 break;
2065 CASE_256_MOV_RM()
2066 printBroadcast(MI, OutStreamer, Repeats: 1, BitWidth: 256);
2067 break;
2068 CASE_512_MOV_RM()
2069 printBroadcast(MI, OutStreamer, Repeats: 1, BitWidth: 512);
2070 break;
2071 case X86::VBROADCASTF128rm:
2072 case X86::VBROADCASTI128rm:
2073 MASK_AVX512_CASE(X86::VBROADCASTF32X4Z256rm)
2074 MASK_AVX512_CASE(X86::VBROADCASTF64X2Z256rm)
2075 MASK_AVX512_CASE(X86::VBROADCASTI32X4Z256rm)
2076 MASK_AVX512_CASE(X86::VBROADCASTI64X2Z256rm)
2077 printBroadcast(MI, OutStreamer, Repeats: 2, BitWidth: 128);
2078 break;
2079 MASK_AVX512_CASE(X86::VBROADCASTF32X4Zrm)
2080 MASK_AVX512_CASE(X86::VBROADCASTF64X2Zrm)
2081 MASK_AVX512_CASE(X86::VBROADCASTI32X4Zrm)
2082 MASK_AVX512_CASE(X86::VBROADCASTI64X2Zrm)
2083 printBroadcast(MI, OutStreamer, Repeats: 4, BitWidth: 128);
2084 break;
2085 MASK_AVX512_CASE(X86::VBROADCASTF32X8Zrm)
2086 MASK_AVX512_CASE(X86::VBROADCASTF64X4Zrm)
2087 MASK_AVX512_CASE(X86::VBROADCASTI32X8Zrm)
2088 MASK_AVX512_CASE(X86::VBROADCASTI64X4Zrm)
2089 printBroadcast(MI, OutStreamer, Repeats: 2, BitWidth: 256);
2090 break;
2091
2092 // For broadcast loads from a constant pool to a vector register, repeatedly
2093 // print the constant loaded.
2094 case X86::MOVDDUPrm:
2095 case X86::VMOVDDUPrm:
2096 MASK_AVX512_CASE(X86::VMOVDDUPZ128rm)
2097 case X86::VPBROADCASTQrm:
2098 MASK_AVX512_CASE(X86::VPBROADCASTQZ128rm)
2099 printBroadcast(MI, OutStreamer, Repeats: 2, BitWidth: 64);
2100 break;
2101 case X86::VBROADCASTSDYrm:
2102 MASK_AVX512_CASE(X86::VBROADCASTSDZ256rm)
2103 case X86::VPBROADCASTQYrm:
2104 MASK_AVX512_CASE(X86::VPBROADCASTQZ256rm)
2105 printBroadcast(MI, OutStreamer, Repeats: 4, BitWidth: 64);
2106 break;
2107 MASK_AVX512_CASE(X86::VBROADCASTSDZrm)
2108 MASK_AVX512_CASE(X86::VPBROADCASTQZrm)
2109 printBroadcast(MI, OutStreamer, Repeats: 8, BitWidth: 64);
2110 break;
2111 case X86::VBROADCASTSSrm:
2112 MASK_AVX512_CASE(X86::VBROADCASTSSZ128rm)
2113 case X86::VPBROADCASTDrm:
2114 MASK_AVX512_CASE(X86::VPBROADCASTDZ128rm)
2115 printBroadcast(MI, OutStreamer, Repeats: 4, BitWidth: 32);
2116 break;
2117 case X86::VBROADCASTSSYrm:
2118 MASK_AVX512_CASE(X86::VBROADCASTSSZ256rm)
2119 case X86::VPBROADCASTDYrm:
2120 MASK_AVX512_CASE(X86::VPBROADCASTDZ256rm)
2121 printBroadcast(MI, OutStreamer, Repeats: 8, BitWidth: 32);
2122 break;
2123 MASK_AVX512_CASE(X86::VBROADCASTSSZrm)
2124 MASK_AVX512_CASE(X86::VPBROADCASTDZrm)
2125 printBroadcast(MI, OutStreamer, Repeats: 16, BitWidth: 32);
2126 break;
2127 case X86::VPBROADCASTWrm:
2128 MASK_AVX512_CASE(X86::VPBROADCASTWZ128rm)
2129 printBroadcast(MI, OutStreamer, Repeats: 8, BitWidth: 16);
2130 break;
2131 case X86::VPBROADCASTWYrm:
2132 MASK_AVX512_CASE(X86::VPBROADCASTWZ256rm)
2133 printBroadcast(MI, OutStreamer, Repeats: 16, BitWidth: 16);
2134 break;
2135 MASK_AVX512_CASE(X86::VPBROADCASTWZrm)
2136 printBroadcast(MI, OutStreamer, Repeats: 32, BitWidth: 16);
2137 break;
2138 case X86::VPBROADCASTBrm:
2139 MASK_AVX512_CASE(X86::VPBROADCASTBZ128rm)
2140 printBroadcast(MI, OutStreamer, Repeats: 16, BitWidth: 8);
2141 break;
2142 case X86::VPBROADCASTBYrm:
2143 MASK_AVX512_CASE(X86::VPBROADCASTBZ256rm)
2144 printBroadcast(MI, OutStreamer, Repeats: 32, BitWidth: 8);
2145 break;
2146 MASK_AVX512_CASE(X86::VPBROADCASTBZrm)
2147 printBroadcast(MI, OutStreamer, Repeats: 64, BitWidth: 8);
2148 break;
2149
2150#define MOVX_CASE(Prefix, Ext, Type, Suffix, Postfix) \
2151 case X86::Prefix##PMOV##Ext##Type##Suffix##rm##Postfix:
2152
2153#define CASE_MOVX_RM(Ext, Type) \
2154 MOVX_CASE(, Ext, Type, , ) \
2155 MOVX_CASE(V, Ext, Type, , ) \
2156 MOVX_CASE(V, Ext, Type, Y, ) \
2157 MOVX_CASE(V, Ext, Type, Z128, ) \
2158 MOVX_CASE(V, Ext, Type, Z128, k ) \
2159 MOVX_CASE(V, Ext, Type, Z128, kz ) \
2160 MOVX_CASE(V, Ext, Type, Z256, ) \
2161 MOVX_CASE(V, Ext, Type, Z256, k ) \
2162 MOVX_CASE(V, Ext, Type, Z256, kz ) \
2163 MOVX_CASE(V, Ext, Type, Z, ) \
2164 MOVX_CASE(V, Ext, Type, Z, k ) \
2165 MOVX_CASE(V, Ext, Type, Z, kz )
2166
2167 CASE_MOVX_RM(SX, BD)
2168 printSignExtend(MI, OutStreamer, SrcEltBits: 8, DstEltBits: 32);
2169 break;
2170 CASE_MOVX_RM(SX, BQ)
2171 printSignExtend(MI, OutStreamer, SrcEltBits: 8, DstEltBits: 64);
2172 break;
2173 CASE_MOVX_RM(SX, BW)
2174 printSignExtend(MI, OutStreamer, SrcEltBits: 8, DstEltBits: 16);
2175 break;
2176 CASE_MOVX_RM(SX, DQ)
2177 printSignExtend(MI, OutStreamer, SrcEltBits: 32, DstEltBits: 64);
2178 break;
2179 CASE_MOVX_RM(SX, WD)
2180 printSignExtend(MI, OutStreamer, SrcEltBits: 16, DstEltBits: 32);
2181 break;
2182 CASE_MOVX_RM(SX, WQ)
2183 printSignExtend(MI, OutStreamer, SrcEltBits: 16, DstEltBits: 64);
2184 break;
2185
2186 CASE_MOVX_RM(ZX, BD)
2187 printZeroExtend(MI, OutStreamer, SrcEltBits: 8, DstEltBits: 32);
2188 break;
2189 CASE_MOVX_RM(ZX, BQ)
2190 printZeroExtend(MI, OutStreamer, SrcEltBits: 8, DstEltBits: 64);
2191 break;
2192 CASE_MOVX_RM(ZX, BW)
2193 printZeroExtend(MI, OutStreamer, SrcEltBits: 8, DstEltBits: 16);
2194 break;
2195 CASE_MOVX_RM(ZX, DQ)
2196 printZeroExtend(MI, OutStreamer, SrcEltBits: 32, DstEltBits: 64);
2197 break;
2198 CASE_MOVX_RM(ZX, WD)
2199 printZeroExtend(MI, OutStreamer, SrcEltBits: 16, DstEltBits: 32);
2200 break;
2201 CASE_MOVX_RM(ZX, WQ)
2202 printZeroExtend(MI, OutStreamer, SrcEltBits: 16, DstEltBits: 64);
2203 break;
2204 }
2205}
2206
2207// Does the given operand refer to a DLLIMPORT function?
2208bool isImportedFunction(const MachineOperand &MO) {
2209 return MO.isGlobal() && (MO.getTargetFlags() == X86II::MO_DLLIMPORT);
2210}
2211
2212// Is the given instruction a call to a CFGuard function?
2213bool isCallToCFGuardFunction(const MachineInstr *MI) {
2214 assert(MI->getOpcode() == X86::TAILJMPm64_REX ||
2215 MI->getOpcode() == X86::CALL64m);
2216 const MachineOperand &MO = MI->getOperand(i: 3);
2217 return MO.isGlobal() && (MO.getTargetFlags() == X86II::MO_NO_FLAG) &&
2218 isCFGuardFunction(GV: MO.getGlobal());
2219}
2220
2221// Does the containing block for the given instruction contain any jump table
2222// info (indicating that the block is a dispatch for a jump table)?
2223bool hasJumpTableInfoInBlock(const llvm::MachineInstr *MI) {
2224 const MachineBasicBlock &MBB = *MI->getParent();
2225 for (auto I = MBB.instr_rbegin(), E = MBB.instr_rend(); I != E; ++I)
2226 if (I->isJumpTableDebugInfo())
2227 return true;
2228
2229 return false;
2230}
2231
2232void X86AsmPrinter::emitInstruction(const MachineInstr *MI) {
2233 // FIXME: Enable feature predicate checks once all the test pass.
2234 // X86_MC::verifyInstructionPredicates(MI->getOpcode(),
2235 // Subtarget->getFeatureBits());
2236
2237 X86MCInstLower MCInstLowering(*MF, *this);
2238 const X86RegisterInfo *RI =
2239 MF->getSubtarget<X86Subtarget>().getRegisterInfo();
2240
2241 if (MI->getOpcode() == X86::OR64rm) {
2242 for (auto &Opd : MI->operands()) {
2243 if (Opd.isSymbol() && StringRef(Opd.getSymbolName()) ==
2244 "swift_async_extendedFramePointerFlags") {
2245 ShouldEmitWeakSwiftAsyncExtendedFramePointerFlags = true;
2246 }
2247 }
2248 }
2249
2250 // Add comments for values loaded from constant pool.
2251 if (OutStreamer->isVerboseAsm())
2252 addConstantComments(MI, OutStreamer&: *OutStreamer);
2253
2254 // Add a comment about EVEX compression
2255 if (TM.Options.MCOptions.ShowMCEncoding) {
2256 if (MI->getAsmPrinterFlags() & X86::AC_EVEX_2_LEGACY)
2257 OutStreamer->AddComment(T: "EVEX TO LEGACY Compression ", EOL: false);
2258 else if (MI->getAsmPrinterFlags() & X86::AC_EVEX_2_VEX)
2259 OutStreamer->AddComment(T: "EVEX TO VEX Compression ", EOL: false);
2260 else if (MI->getAsmPrinterFlags() & X86::AC_EVEX_2_EVEX)
2261 OutStreamer->AddComment(T: "EVEX TO EVEX Compression ", EOL: false);
2262 }
2263
2264 // We use this to suppress NOP padding for Windows EH.
2265 bool IsTailJump = false;
2266
2267 switch (MI->getOpcode()) {
2268 case TargetOpcode::DBG_VALUE:
2269 llvm_unreachable("Should be handled target independently");
2270
2271 case X86::EH_RETURN:
2272 case X86::EH_RETURN64: {
2273 // Lower these as normal, but add some comments.
2274 Register Reg = MI->getOperand(i: 0).getReg();
2275 OutStreamer->AddComment(T: StringRef("eh_return, addr: %") +
2276 X86ATTInstPrinter::getRegisterName(Reg));
2277 break;
2278 }
2279 case X86::CLEANUPRET: {
2280 // Lower these as normal, but add some comments.
2281 OutStreamer->AddComment(T: "CLEANUPRET");
2282 break;
2283 }
2284
2285 case X86::CATCHRET: {
2286 // Lower these as normal, but add some comments.
2287 OutStreamer->AddComment(T: "CATCHRET");
2288 break;
2289 }
2290
2291 case X86::ENDBR32:
2292 case X86::ENDBR64: {
2293 // CurrentPatchableFunctionEntrySym can be CurrentFnBegin only for
2294 // -fpatchable-function-entry=N,0. The entry MBB is guaranteed to be
2295 // non-empty. If MI is the initial ENDBR, place the
2296 // __patchable_function_entries label after ENDBR.
2297 if (CurrentPatchableFunctionEntrySym &&
2298 CurrentPatchableFunctionEntrySym == CurrentFnBegin &&
2299 MI == &MF->front().front()) {
2300 MCInst Inst;
2301 MCInstLowering.Lower(MI, OutMI&: Inst);
2302 EmitAndCountInstruction(Inst);
2303 CurrentPatchableFunctionEntrySym = createTempSymbol(Name: "patch");
2304 OutStreamer->emitLabel(Symbol: CurrentPatchableFunctionEntrySym);
2305 return;
2306 }
2307 break;
2308 }
2309
2310 case X86::TAILJMPd64:
2311 if (IndCSPrefix && MI->hasRegisterImplicitUseOperand(Reg: X86::R11))
2312 EmitAndCountInstruction(Inst&: MCInstBuilder(X86::CS_PREFIX));
2313
2314 if (EnableImportCallOptimization && isImportedFunction(MO: MI->getOperand(i: 0))) {
2315 emitLabelAndRecordForImportCallOptimization(
2316 Kind: IMAGE_RETPOLINE_AMD64_IMPORT_BR);
2317 }
2318
2319 // Lower this as normal, but add a comment.
2320 OutStreamer->AddComment(T: "TAILCALL");
2321 IsTailJump = true;
2322 break;
2323
2324 case X86::TAILJMPr:
2325 case X86::TAILJMPm:
2326 case X86::TAILJMPd:
2327 case X86::TAILJMPd_CC:
2328 case X86::TAILJMPr64:
2329 case X86::TAILJMPm64:
2330 case X86::TAILJMPd64_CC:
2331 if (EnableImportCallOptimization)
2332 report_fatal_error(reason: "Unexpected TAILJMP instruction was emitted when "
2333 "import call optimization was enabled");
2334
2335 // Lower these as normal, but add some comments.
2336 OutStreamer->AddComment(T: "TAILCALL");
2337 IsTailJump = true;
2338 break;
2339
2340 case X86::TAILJMPm64_REX:
2341 if (EnableImportCallOptimization && isCallToCFGuardFunction(MI)) {
2342 emitLabelAndRecordForImportCallOptimization(
2343 Kind: IMAGE_RETPOLINE_AMD64_CFG_BR_REX);
2344 }
2345
2346 OutStreamer->AddComment(T: "TAILCALL");
2347 IsTailJump = true;
2348 break;
2349
2350 case X86::TAILJMPr64_REX: {
2351 if (EnableImportCallOptimization) {
2352 assert(MI->getOperand(0).getReg() == X86::RAX &&
2353 "Indirect tail calls with impcall enabled must go through RAX (as "
2354 "enforced by TCRETURNImpCallri64)");
2355 emitLabelAndRecordForImportCallOptimization(
2356 Kind: IMAGE_RETPOLINE_AMD64_INDIR_BR);
2357 }
2358
2359 OutStreamer->AddComment(T: "TAILCALL");
2360 IsTailJump = true;
2361 break;
2362 }
2363
2364 case X86::JMP64r:
2365 if (EnableImportCallOptimization && hasJumpTableInfoInBlock(MI)) {
2366 uint16_t EncodedReg =
2367 this->getSubtarget().getRegisterInfo()->getEncodingValue(
2368 Reg: MI->getOperand(i: 0).getReg().asMCReg());
2369 emitLabelAndRecordForImportCallOptimization(
2370 Kind: (ImportCallKind)(IMAGE_RETPOLINE_AMD64_SWITCHTABLE_FIRST +
2371 EncodedReg));
2372 }
2373 break;
2374
2375 case X86::JMP16r:
2376 case X86::JMP16m:
2377 case X86::JMP32r:
2378 case X86::JMP32m:
2379 case X86::JMP64m:
2380 if (EnableImportCallOptimization && hasJumpTableInfoInBlock(MI))
2381 report_fatal_error(
2382 reason: "Unexpected JMP instruction was emitted for a jump-table when import "
2383 "call optimization was enabled");
2384 break;
2385
2386 case X86::TLS_addr32:
2387 case X86::TLS_addr64:
2388 case X86::TLS_addrX32:
2389 case X86::TLS_base_addr32:
2390 case X86::TLS_base_addr64:
2391 case X86::TLS_base_addrX32:
2392 case X86::TLS_desc32:
2393 case X86::TLS_desc64:
2394 return LowerTlsAddr(MCInstLowering, MI: *MI);
2395
2396 case X86::MOVPC32r: {
2397 // This is a pseudo op for a two instruction sequence with a label, which
2398 // looks like:
2399 // call "L1$pb"
2400 // "L1$pb":
2401 // popl %esi
2402
2403 // Emit the call.
2404 MCSymbol *PICBase = MF->getPICBaseSymbol();
2405 // FIXME: We would like an efficient form for this, so we don't have to do a
2406 // lot of extra uniquing.
2407 EmitAndCountInstruction(
2408 Inst&: MCInstBuilder(X86::CALLpcrel32)
2409 .addExpr(Val: MCSymbolRefExpr::create(Symbol: PICBase, Ctx&: OutContext)));
2410
2411 const X86FrameLowering *FrameLowering =
2412 MF->getSubtarget<X86Subtarget>().getFrameLowering();
2413 bool hasFP = FrameLowering->hasFP(MF: *MF);
2414
2415 // TODO: This is needed only if we require precise CFA.
2416 bool HasActiveDwarfFrame = OutStreamer->getNumFrameInfos() &&
2417 !OutStreamer->getDwarfFrameInfos().back().End;
2418
2419 int stackGrowth = -RI->getSlotSize();
2420
2421 if (HasActiveDwarfFrame && !hasFP) {
2422 OutStreamer->emitCFIAdjustCfaOffset(Adjustment: -stackGrowth);
2423 MF->getInfo<X86MachineFunctionInfo>()->setHasCFIAdjustCfa(true);
2424 }
2425
2426 // Emit the label.
2427 OutStreamer->emitLabel(Symbol: PICBase);
2428
2429 // popl $reg
2430 EmitAndCountInstruction(
2431 Inst&: MCInstBuilder(X86::POP32r).addReg(Reg: MI->getOperand(i: 0).getReg()));
2432
2433 if (HasActiveDwarfFrame && !hasFP) {
2434 OutStreamer->emitCFIAdjustCfaOffset(Adjustment: stackGrowth);
2435 }
2436 return;
2437 }
2438
2439 case X86::ADD32ri: {
2440 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
2441 if (MI->getOperand(i: 2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
2442 break;
2443
2444 // Okay, we have something like:
2445 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
2446
2447 // For this, we want to print something like:
2448 // MYGLOBAL + (. - PICBASE)
2449 // However, we can't generate a ".", so just emit a new label here and refer
2450 // to it.
2451 MCSymbol *DotSym = OutContext.createTempSymbol();
2452 OutStreamer->emitLabel(Symbol: DotSym);
2453
2454 // Now that we have emitted the label, lower the complex operand expression.
2455 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MO: MI->getOperand(i: 2));
2456
2457 const MCExpr *DotExpr = MCSymbolRefExpr::create(Symbol: DotSym, Ctx&: OutContext);
2458 const MCExpr *PICBase =
2459 MCSymbolRefExpr::create(Symbol: MF->getPICBaseSymbol(), Ctx&: OutContext);
2460 DotExpr = MCBinaryExpr::createSub(LHS: DotExpr, RHS: PICBase, Ctx&: OutContext);
2461
2462 DotExpr = MCBinaryExpr::createAdd(
2463 LHS: MCSymbolRefExpr::create(Symbol: OpSym, Ctx&: OutContext), RHS: DotExpr, Ctx&: OutContext);
2464
2465 EmitAndCountInstruction(Inst&: MCInstBuilder(X86::ADD32ri)
2466 .addReg(Reg: MI->getOperand(i: 0).getReg())
2467 .addReg(Reg: MI->getOperand(i: 1).getReg())
2468 .addExpr(Val: DotExpr));
2469 return;
2470 }
2471 case TargetOpcode::STATEPOINT:
2472 return LowerSTATEPOINT(MI: *MI, MCIL&: MCInstLowering);
2473
2474 case TargetOpcode::FAULTING_OP:
2475 return LowerFAULTING_OP(FaultingMI: *MI, MCIL&: MCInstLowering);
2476
2477 case TargetOpcode::FENTRY_CALL:
2478 return LowerFENTRY_CALL(MI: *MI, MCIL&: MCInstLowering);
2479
2480 case TargetOpcode::PATCHABLE_OP:
2481 return LowerPATCHABLE_OP(MI: *MI, MCIL&: MCInstLowering);
2482
2483 case TargetOpcode::STACKMAP:
2484 return LowerSTACKMAP(MI: *MI);
2485
2486 case TargetOpcode::PATCHPOINT:
2487 return LowerPATCHPOINT(MI: *MI, MCIL&: MCInstLowering);
2488
2489 case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
2490 return LowerPATCHABLE_FUNCTION_ENTER(MI: *MI, MCIL&: MCInstLowering);
2491
2492 case TargetOpcode::PATCHABLE_RET:
2493 return LowerPATCHABLE_RET(MI: *MI, MCIL&: MCInstLowering);
2494
2495 case TargetOpcode::PATCHABLE_TAIL_CALL:
2496 return LowerPATCHABLE_TAIL_CALL(MI: *MI, MCIL&: MCInstLowering);
2497
2498 case TargetOpcode::PATCHABLE_EVENT_CALL:
2499 return LowerPATCHABLE_EVENT_CALL(MI: *MI, MCIL&: MCInstLowering);
2500
2501 case TargetOpcode::PATCHABLE_TYPED_EVENT_CALL:
2502 return LowerPATCHABLE_TYPED_EVENT_CALL(MI: *MI, MCIL&: MCInstLowering);
2503
2504 case X86::MORESTACK_RET:
2505 EmitAndCountInstruction(Inst&: MCInstBuilder(getRetOpcode(Subtarget: *Subtarget)));
2506 return;
2507
2508 case X86::KCFI_CHECK:
2509 return LowerKCFI_CHECK(MI: *MI);
2510
2511 case X86::ASAN_CHECK_MEMACCESS:
2512 return LowerASAN_CHECK_MEMACCESS(MI: *MI);
2513
2514 case X86::MORESTACK_RET_RESTORE_R10:
2515 // Return, then restore R10.
2516 EmitAndCountInstruction(Inst&: MCInstBuilder(getRetOpcode(Subtarget: *Subtarget)));
2517 EmitAndCountInstruction(
2518 Inst&: MCInstBuilder(X86::MOV64rr).addReg(Reg: X86::R10).addReg(Reg: X86::RAX));
2519 return;
2520
2521 case X86::SEH_PushReg:
2522 case X86::SEH_SaveReg:
2523 case X86::SEH_SaveXMM:
2524 case X86::SEH_StackAlloc:
2525 case X86::SEH_StackAlign:
2526 case X86::SEH_SetFrame:
2527 case X86::SEH_PushFrame:
2528 case X86::SEH_EndPrologue:
2529 case X86::SEH_EndEpilogue:
2530 case X86::SEH_UnwindV2Start:
2531 case X86::SEH_UnwindVersion:
2532 EmitSEHInstruction(MI);
2533 return;
2534
2535 case X86::SEH_SplitChainedAtEndOfBlock:
2536 assert(!SplitChainedAtEndOfBlock &&
2537 "Duplicate SEH_SplitChainedAtEndOfBlock in a current block");
2538 SplitChainedAtEndOfBlock = true;
2539 return;
2540
2541 case X86::SEH_BeginEpilogue: {
2542 assert(MF->hasWinCFI() && "SEH_ instruction in function without WinCFI?");
2543 EmitSEHInstruction(MI);
2544 return;
2545 }
2546 case X86::UBSAN_UD1:
2547 EmitAndCountInstruction(Inst&: MCInstBuilder(X86::UD1Lm)
2548 .addReg(Reg: X86::EAX)
2549 .addReg(Reg: X86::EAX)
2550 .addImm(Val: 1)
2551 .addReg(Reg: X86::NoRegister)
2552 .addImm(Val: MI->getOperand(i: 0).getImm())
2553 .addReg(Reg: X86::NoRegister));
2554 return;
2555 case X86::CALL64pcrel32:
2556 if (IndCSPrefix && MI->hasRegisterImplicitUseOperand(Reg: X86::R11))
2557 EmitAndCountInstruction(Inst&: MCInstBuilder(X86::CS_PREFIX));
2558
2559 if (EnableImportCallOptimization && isImportedFunction(MO: MI->getOperand(i: 0))) {
2560 emitLabelAndRecordForImportCallOptimization(
2561 Kind: IMAGE_RETPOLINE_AMD64_IMPORT_CALL);
2562
2563 MCInst TmpInst;
2564 MCInstLowering.Lower(MI, OutMI&: TmpInst);
2565
2566 // For Import Call Optimization to work, we need a the call instruction
2567 // with a rex prefix, and a 5-byte nop after the call instruction.
2568 EmitAndCountInstruction(Inst&: MCInstBuilder(X86::REX64_PREFIX));
2569 emitCallInstruction(MCI: TmpInst);
2570 emitNop(OS&: *OutStreamer, NumBytes: 5, Subtarget);
2571 maybeEmitNopAfterCallForWindowsEH(MI);
2572 return;
2573 }
2574
2575 break;
2576
2577 case X86::CALL64r:
2578 if (EnableImportCallOptimization) {
2579 assert(MI->getOperand(0).getReg() == X86::RAX &&
2580 "Indirect calls with impcall enabled must go through RAX (as "
2581 "enforced by CALL64r_ImpCall)");
2582
2583 emitLabelAndRecordForImportCallOptimization(
2584 Kind: IMAGE_RETPOLINE_AMD64_INDIR_CALL);
2585 MCInst TmpInst;
2586 MCInstLowering.Lower(MI, OutMI&: TmpInst);
2587 emitCallInstruction(MCI: TmpInst);
2588
2589 // For Import Call Optimization to work, we need a 3-byte nop after the
2590 // call instruction.
2591 emitNop(OS&: *OutStreamer, NumBytes: 3, Subtarget);
2592 maybeEmitNopAfterCallForWindowsEH(MI);
2593 return;
2594 }
2595 break;
2596
2597 case X86::CALL64m:
2598 if (EnableImportCallOptimization && isCallToCFGuardFunction(MI)) {
2599 emitLabelAndRecordForImportCallOptimization(
2600 Kind: IMAGE_RETPOLINE_AMD64_CFG_CALL);
2601 }
2602 break;
2603
2604 case X86::JCC_1:
2605 // Two instruction prefixes (2EH for branch not-taken and 3EH for branch
2606 // taken) are used as branch hints. Here we add branch taken prefix for
2607 // jump instruction with higher probability than threshold.
2608 if (getSubtarget().hasBranchHint() && EnableBranchHint) {
2609 const MachineBranchProbabilityInfo *MBPI =
2610 &getAnalysis<MachineBranchProbabilityInfoWrapperPass>().getMBPI();
2611 MachineBasicBlock *DestBB = MI->getOperand(i: 0).getMBB();
2612 BranchProbability EdgeProb =
2613 MBPI->getEdgeProbability(Src: MI->getParent(), Dst: DestBB);
2614 BranchProbability Threshold(BranchHintProbabilityThreshold, 100);
2615 if (EdgeProb > Threshold)
2616 EmitAndCountInstruction(Inst&: MCInstBuilder(X86::DS_PREFIX));
2617 }
2618 break;
2619 }
2620
2621 MCInst TmpInst;
2622 MCInstLowering.Lower(MI, OutMI&: TmpInst);
2623
2624 if (MI->isCall()) {
2625 emitCallInstruction(MCI: TmpInst);
2626 // Since tail calls transfer control without leaving a stack frame, there is
2627 // never a need for NOP padding tail calls.
2628 if (!IsTailJump)
2629 maybeEmitNopAfterCallForWindowsEH(MI);
2630 return;
2631 }
2632
2633 EmitAndCountInstruction(Inst&: TmpInst);
2634}
2635
2636void X86AsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
2637 const MCSubtargetInfo *EndInfo,
2638 const MachineInstr *MI) {
2639 if (MI) {
2640 // If unwinding inline asm ends on a call, wineh may require insertion of
2641 // a nop.
2642 unsigned ExtraInfo = MI->getOperand(i: InlineAsm::MIOp_ExtraInfo).getImm();
2643 if (ExtraInfo & InlineAsm::Extra_MayUnwind)
2644 maybeEmitNopAfterCallForWindowsEH(MI);
2645 }
2646}
2647
2648void X86AsmPrinter::emitCallInstruction(const llvm::MCInst &MCI) {
2649 // Stackmap shadows cannot include branch targets, so we can count the bytes
2650 // in a call towards the shadow, but must ensure that the no thread returns
2651 // in to the stackmap shadow. The only way to achieve this is if the call
2652 // is at the end of the shadow.
2653
2654 // Count then size of the call towards the shadow
2655 SMShadowTracker.count(Inst: MCI, STI: getSubtargetInfo(), CodeEmitter: CodeEmitter.get());
2656 // Then flush the shadow so that we fill with nops before the call, not
2657 // after it.
2658 SMShadowTracker.emitShadowPadding(OutStreamer&: *OutStreamer, STI: getSubtargetInfo());
2659 // Then emit the call
2660 OutStreamer->emitInstruction(Inst: MCI, STI: getSubtargetInfo());
2661}
2662
2663// Determines whether a NOP is required after a CALL, so that Windows EH
2664// IP2State tables have the correct information.
2665//
2666// On most Windows platforms (AMD64, ARM64, ARM32, IA64, but *not* x86-32),
2667// exception handling works by looking up instruction pointers in lookup
2668// tables. These lookup tables are stored in .xdata sections in executables.
2669// One element of the lookup tables are the "IP2State" tables (Instruction
2670// Pointer to State).
2671//
2672// If a function has any instructions that require cleanup during exception
2673// unwinding, then it will have an IP2State table. Each entry in the IP2State
2674// table describes a range of bytes in the function's instruction stream, and
2675// associates an "EH state number" with that range of instructions. A value of
2676// -1 means "the null state", which does not require any code to execute.
2677// A value other than -1 is an index into the State table.
2678//
2679// The entries in the IP2State table contain byte offsets within the instruction
2680// stream of the function. The Windows ABI requires that these offsets are
2681// aligned to instruction boundaries; they are not permitted to point to a byte
2682// that is not the first byte of an instruction.
2683//
2684// Unfortunately, CALL instructions present a problem during unwinding. CALL
2685// instructions push the address of the instruction after the CALL instruction,
2686// so that execution can resume after the CALL. If the CALL is the last
2687// instruction within an IP2State region, then the return address (on the stack)
2688// points to the *next* IP2State region. This means that the unwinder will
2689// use the wrong cleanup funclet during unwinding.
2690//
2691// To fix this problem, the Windows AMD64 ABI requires that CALL instructions
2692// are never placed at the end of an IP2State region. Stated equivalently, the
2693// end of a CALL instruction cannot be aligned to an IP2State boundary. If a
2694// CALL instruction would occur at the end of an IP2State region, then the
2695// compiler must insert a NOP instruction after the CALL. The NOP instruction
2696// is placed in the same EH region as the CALL instruction, so that the return
2697// address points to the NOP and the unwinder will locate the correct region.
2698//
2699// NOP padding is only necessary on Windows AMD64 targets. On ARM64 and ARM32,
2700// instructions have a fixed size so the unwinder knows how to "back up" by
2701// one instruction.
2702//
2703// Interaction with Import Call Optimization (ICO):
2704//
2705// Import Call Optimization (ICO) is a compiler + OS feature on Windows which
2706// improves the performance and security of DLL imports. ICO relies on using a
2707// specific CALL idiom that can be replaced by the OS DLL loader. This removes
2708// a load and indirect CALL and replaces it with a single direct CALL.
2709//
2710// To achieve this, ICO also inserts NOPs after the CALL instruction. If the
2711// end of the CALL is aligned with an EH state transition, we *also* insert
2712// a single-byte NOP. **Both forms of NOPs must be preserved.** They cannot
2713// be combined into a single larger NOP; nor can the second NOP be removed.
2714//
2715// This is necessary because, if ICO is active and the call site is modified
2716// by the loader, the loader will end up overwriting the NOPs that were inserted
2717// for ICO. That means that those NOPs cannot be used for the correct
2718// termination of the exception handling region (the IP2State transition),
2719// so we still need an additional NOP instruction. The NOPs cannot be combined
2720// into a longer NOP (which is ordinarily desirable) because then ICO would
2721// split one instruction, producing a malformed instruction after the ICO call.
2722void X86AsmPrinter::maybeEmitNopAfterCallForWindowsEH(const MachineInstr *MI) {
2723 // We only need to insert NOPs after CALLs when targeting Windows on AMD64.
2724 // (Don't let the name fool you: Itanium refers to table-based exception
2725 // handling, not the Itanium architecture.)
2726 if (MAI->getExceptionHandlingType() != ExceptionHandling::WinEH ||
2727 MAI->getWinEHEncodingType() != WinEH::EncodingType::Itanium) {
2728 return;
2729 }
2730
2731 bool HasEHPersonality = MF->getWinEHFuncInfo() != nullptr;
2732
2733 // Set up MBB iterator, initially positioned on the same MBB as MI.
2734 MachineFunction::const_iterator MFI(MI->getParent());
2735 MachineFunction::const_iterator MFE(MF->end());
2736
2737 // Set up instruction iterator, positioned immediately *after* MI.
2738 MachineBasicBlock::const_iterator MBBI(MI);
2739 MachineBasicBlock::const_iterator MBBE = MI->getParent()->end();
2740 ++MBBI; // Step over MI
2741
2742 // This loop iterates MBBs
2743 for (;;) {
2744 // This loop iterates instructions
2745 for (; MBBI != MBBE; ++MBBI) {
2746 // Check the instruction that follows this CALL.
2747 const MachineInstr &NextMI = *MBBI;
2748
2749 // If there is an EH_LABEL after this CALL, then there is an EH state
2750 // transition after this CALL. This is exactly the situation which
2751 // requires NOP padding.
2752 if (NextMI.isEHLabel()) {
2753 if (HasEHPersonality) {
2754 EmitAndCountInstruction(Inst&: MCInstBuilder(X86::NOOP));
2755 return;
2756 }
2757 // We actually want to continue, in case there is an SEH_BeginEpilogue
2758 // instruction after the EH_LABEL. In some situations, IR is produced
2759 // that contains EH_LABEL pseudo-instructions, even when we are not
2760 // generating IP2State tables. We still need to insert a NOP before
2761 // SEH_BeginEpilogue in that case.
2762 continue;
2763 }
2764
2765 // Somewhat similarly, if the CALL is the last instruction before the
2766 // SEH prologue, then we also need a NOP. This is necessary because the
2767 // Windows stack unwinder will not invoke a function's exception handler
2768 // if the instruction pointer is in the function prologue or epilogue.
2769 //
2770 // We always emit a NOP before SEH_BeginEpilogue, even if there is no
2771 // personality function (unwind info) for this frame. This is the same
2772 // behavior as MSVC.
2773 if (NextMI.getOpcode() == X86::SEH_BeginEpilogue) {
2774 EmitAndCountInstruction(Inst&: MCInstBuilder(X86::NOOP));
2775 return;
2776 }
2777
2778 if (!NextMI.isPseudo() && !NextMI.isMetaInstruction()) {
2779 // We found a real instruction. During the CALL, the return IP will
2780 // point to this instruction. Since this instruction has the same EH
2781 // state as the call itself (because there is no intervening EH_LABEL),
2782 // the IP2State table will be accurate; there is no need to insert a
2783 // NOP.
2784 return;
2785 }
2786
2787 // The next instruction is a pseudo-op. Ignore it and keep searching.
2788 // Because these instructions do not generate any machine code, they
2789 // cannot prevent the IP2State table from pointing at the wrong
2790 // instruction during a CALL.
2791 }
2792
2793 // We've reached the end of this MBB. Find the next MBB in program order.
2794 // MBB order should be finalized by this point, so falling across MBBs is
2795 // expected.
2796 ++MFI;
2797 if (MFI == MFE) {
2798 // No more blocks; we've reached the end of the function. This should
2799 // only happen with no-return functions, but double-check to be sure.
2800 if (HasEHPersonality) {
2801 // If the CALL has no successors, then it is a noreturn function.
2802 // Insert an INT3 instead of a NOP. This accomplishes the same purpose,
2803 // but is more clear to read. Also, analysis tools will understand
2804 // that they should not continue disassembling after the CALL (unless
2805 // there are other branches to that label).
2806 if (MI->getParent()->succ_empty())
2807 EmitAndCountInstruction(Inst&: MCInstBuilder(X86::INT3));
2808 else
2809 EmitAndCountInstruction(Inst&: MCInstBuilder(X86::NOOP));
2810 }
2811 return;
2812 }
2813
2814 // Set up iterator to scan the next basic block.
2815 const MachineBasicBlock *NextMBB = &*MFI;
2816 MBBI = NextMBB->instr_begin();
2817 MBBE = NextMBB->instr_end();
2818 }
2819}
2820
2821void X86AsmPrinter::emitLabelAndRecordForImportCallOptimization(
2822 ImportCallKind Kind) {
2823 assert(EnableImportCallOptimization);
2824
2825 MCSymbol *CallSiteSymbol = MMI->getContext().createNamedTempSymbol(Name: "impcall");
2826 OutStreamer->emitLabel(Symbol: CallSiteSymbol);
2827
2828 SectionToImportedFunctionCalls[OutStreamer->getCurrentSectionOnly()]
2829 .push_back(x: {.CalleeSymbol: CallSiteSymbol, .Kind: Kind});
2830}
2831