1//===-- AVRISelLowering.cpp - AVR DAG Lowering Implementation -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that AVR uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "AVRISelLowering.h"
15
16#include "llvm/ADT/ArrayRef.h"
17#include "llvm/ADT/StringSwitch.h"
18#include "llvm/CodeGen/CallingConvLower.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/CodeGen/SelectionDAG.h"
23#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
24#include "llvm/IR/Function.h"
25#include "llvm/Support/ErrorHandling.h"
26
27#include "AVR.h"
28#include "AVRMachineFunctionInfo.h"
29#include "AVRSubtarget.h"
30#include "AVRTargetMachine.h"
31#include "MCTargetDesc/AVRMCTargetDesc.h"
32
33namespace llvm {
34
35AVRTargetLowering::AVRTargetLowering(const AVRTargetMachine &TM,
36 const AVRSubtarget &STI)
37 : TargetLowering(TM), Subtarget(STI) {
38 // Set up the register classes.
39 addRegisterClass(VT: MVT::i8, RC: &AVR::GPR8RegClass);
40 addRegisterClass(VT: MVT::i16, RC: &AVR::DREGSRegClass);
41
42 // Compute derived properties from the register classes.
43 computeRegisterProperties(TRI: Subtarget.getRegisterInfo());
44
45 setBooleanContents(ZeroOrOneBooleanContent);
46 setBooleanVectorContents(ZeroOrOneBooleanContent);
47 setSchedulingPreference(Sched::RegPressure);
48 setStackPointerRegisterToSaveRestore(AVR::SP);
49 setSupportsUnalignedAtomics(true);
50
51 setOperationAction(Op: ISD::GlobalAddress, VT: MVT::i16, Action: Custom);
52 setOperationAction(Op: ISD::BlockAddress, VT: MVT::i16, Action: Custom);
53
54 setOperationAction(Op: ISD::STACKSAVE, VT: MVT::Other, Action: Expand);
55 setOperationAction(Op: ISD::STACKRESTORE, VT: MVT::Other, Action: Expand);
56 setOperationAction(Op: ISD::DYNAMIC_STACKALLOC, VT: MVT::i8, Action: Expand);
57 setOperationAction(Op: ISD::DYNAMIC_STACKALLOC, VT: MVT::i16, Action: Expand);
58
59 setOperationAction(Op: ISD::INLINEASM, VT: MVT::Other, Action: Custom);
60
61 for (MVT VT : MVT::integer_valuetypes()) {
62 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
63 setLoadExtAction(ExtType: N, ValVT: VT, MemVT: MVT::i1, Action: Promote);
64 setLoadExtAction(ExtType: N, ValVT: VT, MemVT: MVT::i8, Action: Expand);
65 }
66 }
67
68 setTruncStoreAction(ValVT: MVT::i16, MemVT: MVT::i8, Action: Expand);
69
70 for (MVT VT : MVT::integer_valuetypes()) {
71 setOperationAction(Op: ISD::ADDC, VT, Action: Legal);
72 setOperationAction(Op: ISD::SUBC, VT, Action: Legal);
73 setOperationAction(Op: ISD::ADDE, VT, Action: Legal);
74 setOperationAction(Op: ISD::SUBE, VT, Action: Legal);
75 }
76
77 // sub (x, imm) gets canonicalized to add (x, -imm), so for illegal types
78 // revert into a sub since we don't have an add with immediate instruction.
79 setOperationAction(Op: ISD::ADD, VT: MVT::i32, Action: Custom);
80 setOperationAction(Op: ISD::ADD, VT: MVT::i64, Action: Custom);
81
82 // our shift instructions are only able to shift 1 bit at a time, so handle
83 // this in a custom way.
84 setOperationAction(Op: ISD::SRA, VT: MVT::i8, Action: Custom);
85 setOperationAction(Op: ISD::SHL, VT: MVT::i8, Action: Custom);
86 setOperationAction(Op: ISD::SRL, VT: MVT::i8, Action: Custom);
87 setOperationAction(Op: ISD::SRA, VT: MVT::i16, Action: Custom);
88 setOperationAction(Op: ISD::SHL, VT: MVT::i16, Action: Custom);
89 setOperationAction(Op: ISD::SRL, VT: MVT::i16, Action: Custom);
90 setOperationAction(Op: ISD::SRA, VT: MVT::i32, Action: Custom);
91 setOperationAction(Op: ISD::SHL, VT: MVT::i32, Action: Custom);
92 setOperationAction(Op: ISD::SRL, VT: MVT::i32, Action: Custom);
93 setOperationAction(Op: ISD::SHL_PARTS, VT: MVT::i16, Action: Expand);
94 setOperationAction(Op: ISD::SRA_PARTS, VT: MVT::i16, Action: Expand);
95 setOperationAction(Op: ISD::SRL_PARTS, VT: MVT::i16, Action: Expand);
96
97 setOperationAction(Op: ISD::ROTL, VT: MVT::i8, Action: Custom);
98 setOperationAction(Op: ISD::ROTL, VT: MVT::i16, Action: Expand);
99 setOperationAction(Op: ISD::ROTR, VT: MVT::i8, Action: Custom);
100 setOperationAction(Op: ISD::ROTR, VT: MVT::i16, Action: Expand);
101
102 setOperationAction(Op: ISD::BR_CC, VT: MVT::i8, Action: Custom);
103 setOperationAction(Op: ISD::BR_CC, VT: MVT::i16, Action: Custom);
104 setOperationAction(Op: ISD::BR_CC, VT: MVT::i32, Action: Custom);
105 setOperationAction(Op: ISD::BR_CC, VT: MVT::i64, Action: Custom);
106 setOperationAction(Op: ISD::BRCOND, VT: MVT::Other, Action: Expand);
107
108 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::i8, Action: Custom);
109 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::i16, Action: Custom);
110 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::i32, Action: Expand);
111 setOperationAction(Op: ISD::SELECT_CC, VT: MVT::i64, Action: Expand);
112 setOperationAction(Op: ISD::SETCC, VT: MVT::i8, Action: Custom);
113 setOperationAction(Op: ISD::SETCC, VT: MVT::i16, Action: Custom);
114 setOperationAction(Op: ISD::SETCC, VT: MVT::i32, Action: Custom);
115 setOperationAction(Op: ISD::SETCC, VT: MVT::i64, Action: Custom);
116 setOperationAction(Op: ISD::SELECT, VT: MVT::i8, Action: Expand);
117 setOperationAction(Op: ISD::SELECT, VT: MVT::i16, Action: Expand);
118
119 setOperationAction(Op: ISD::BSWAP, VT: MVT::i16, Action: Expand);
120
121 // Add support for postincrement and predecrement load/stores.
122 setIndexedLoadAction(IdxModes: ISD::POST_INC, VT: MVT::i8, Action: Legal);
123 setIndexedLoadAction(IdxModes: ISD::POST_INC, VT: MVT::i16, Action: Legal);
124 setIndexedLoadAction(IdxModes: ISD::PRE_DEC, VT: MVT::i8, Action: Legal);
125 setIndexedLoadAction(IdxModes: ISD::PRE_DEC, VT: MVT::i16, Action: Legal);
126 setIndexedStoreAction(IdxModes: ISD::POST_INC, VT: MVT::i8, Action: Legal);
127 setIndexedStoreAction(IdxModes: ISD::POST_INC, VT: MVT::i16, Action: Legal);
128 setIndexedStoreAction(IdxModes: ISD::PRE_DEC, VT: MVT::i8, Action: Legal);
129 setIndexedStoreAction(IdxModes: ISD::PRE_DEC, VT: MVT::i16, Action: Legal);
130
131 setOperationAction(Op: ISD::BR_JT, VT: MVT::Other, Action: Expand);
132
133 setOperationAction(Op: ISD::VASTART, VT: MVT::Other, Action: Custom);
134 setOperationAction(Op: ISD::VAEND, VT: MVT::Other, Action: Expand);
135 setOperationAction(Op: ISD::VAARG, VT: MVT::Other, Action: Expand);
136 setOperationAction(Op: ISD::VACOPY, VT: MVT::Other, Action: Expand);
137
138 // Atomic operations which must be lowered to rtlib calls
139 for (MVT VT : MVT::integer_valuetypes()) {
140 setOperationAction(Op: ISD::ATOMIC_SWAP, VT, Action: Expand);
141 setOperationAction(Op: ISD::ATOMIC_CMP_SWAP, VT, Action: Expand);
142 setOperationAction(Op: ISD::ATOMIC_LOAD_NAND, VT, Action: Expand);
143 setOperationAction(Op: ISD::ATOMIC_LOAD_MAX, VT, Action: Expand);
144 setOperationAction(Op: ISD::ATOMIC_LOAD_MIN, VT, Action: Expand);
145 setOperationAction(Op: ISD::ATOMIC_LOAD_UMAX, VT, Action: Expand);
146 setOperationAction(Op: ISD::ATOMIC_LOAD_UMIN, VT, Action: Expand);
147 }
148
149 // Division/remainder
150 setOperationAction(Op: ISD::UDIV, VT: MVT::i8, Action: Expand);
151 setOperationAction(Op: ISD::UDIV, VT: MVT::i16, Action: Expand);
152 setOperationAction(Op: ISD::UREM, VT: MVT::i8, Action: Expand);
153 setOperationAction(Op: ISD::UREM, VT: MVT::i16, Action: Expand);
154 setOperationAction(Op: ISD::SDIV, VT: MVT::i8, Action: Expand);
155 setOperationAction(Op: ISD::SDIV, VT: MVT::i16, Action: Expand);
156 setOperationAction(Op: ISD::SREM, VT: MVT::i8, Action: Expand);
157 setOperationAction(Op: ISD::SREM, VT: MVT::i16, Action: Expand);
158
159 // Make division and modulus custom
160 setOperationAction(Op: ISD::UDIVREM, VT: MVT::i8, Action: Custom);
161 setOperationAction(Op: ISD::UDIVREM, VT: MVT::i16, Action: Custom);
162 setOperationAction(Op: ISD::UDIVREM, VT: MVT::i32, Action: Custom);
163 setOperationAction(Op: ISD::SDIVREM, VT: MVT::i8, Action: Custom);
164 setOperationAction(Op: ISD::SDIVREM, VT: MVT::i16, Action: Custom);
165 setOperationAction(Op: ISD::SDIVREM, VT: MVT::i32, Action: Custom);
166
167 // Do not use MUL. The AVR instructions are closer to SMUL_LOHI &co.
168 setOperationAction(Op: ISD::MUL, VT: MVT::i8, Action: Expand);
169 setOperationAction(Op: ISD::MUL, VT: MVT::i16, Action: Expand);
170
171 // Expand 16 bit multiplications.
172 setOperationAction(Op: ISD::SMUL_LOHI, VT: MVT::i16, Action: Expand);
173 setOperationAction(Op: ISD::UMUL_LOHI, VT: MVT::i16, Action: Expand);
174
175 // Expand multiplications to libcalls when there is
176 // no hardware MUL.
177 if (!Subtarget.supportsMultiplication()) {
178 setOperationAction(Op: ISD::SMUL_LOHI, VT: MVT::i8, Action: Expand);
179 setOperationAction(Op: ISD::UMUL_LOHI, VT: MVT::i8, Action: Expand);
180 }
181
182 for (MVT VT : MVT::integer_valuetypes()) {
183 setOperationAction(Op: ISD::MULHS, VT, Action: Expand);
184 setOperationAction(Op: ISD::MULHU, VT, Action: Expand);
185 }
186
187 for (MVT VT : MVT::integer_valuetypes()) {
188 setOperationAction(Op: ISD::CTPOP, VT, Action: Expand);
189 setOperationAction(Op: ISD::CTLZ, VT, Action: Expand);
190 setOperationAction(Op: ISD::CTTZ, VT, Action: Expand);
191 }
192
193 for (MVT VT : MVT::integer_valuetypes()) {
194 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT, Action: Expand);
195 // TODO: The generated code is pretty poor. Investigate using the
196 // same "shift and subtract with carry" trick that we do for
197 // extending 8-bit to 16-bit. This may require infrastructure
198 // improvements in how we treat 16-bit "registers" to be feasible.
199 }
200
201 setMinFunctionAlignment(Align(2));
202 setMinimumJumpTableEntries(UINT_MAX);
203}
204
205EVT AVRTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
206 EVT VT) const {
207 assert(!VT.isVector() && "No AVR SetCC type for vectors!");
208 return MVT::i8;
209}
210
211SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
212 unsigned Opc8;
213 const SDNode *N = Op.getNode();
214 EVT VT = Op.getValueType();
215 SDLoc dl(N);
216 assert(llvm::has_single_bit<uint32_t>(VT.getSizeInBits()) &&
217 "Expected power-of-2 shift amount");
218
219 if (VT.getSizeInBits() == 32) {
220 if (!isa<ConstantSDNode>(Val: N->getOperand(Num: 1))) {
221 // 32-bit shifts are converted to a loop in IR.
222 // This should be unreachable.
223 report_fatal_error(reason: "Expected a constant shift amount!");
224 }
225 SDVTList ResTys = DAG.getVTList(VT1: MVT::i16, VT2: MVT::i16);
226 SDValue SrcLo =
227 DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL: dl, VT: MVT::i16, N1: Op.getOperand(i: 0),
228 N2: DAG.getConstant(Val: 0, DL: dl, VT: MVT::i16));
229 SDValue SrcHi =
230 DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL: dl, VT: MVT::i16, N1: Op.getOperand(i: 0),
231 N2: DAG.getConstant(Val: 1, DL: dl, VT: MVT::i16));
232 uint64_t ShiftAmount = N->getConstantOperandVal(Num: 1);
233 if (ShiftAmount == 16) {
234 // Special case these two operations because they appear to be used by the
235 // generic codegen parts to lower 32-bit numbers.
236 // TODO: perhaps we can lower shift amounts bigger than 16 to a 16-bit
237 // shift of a part of the 32-bit value?
238 switch (Op.getOpcode()) {
239 case ISD::SHL: {
240 SDValue Zero = DAG.getConstant(Val: 0, DL: dl, VT: MVT::i16);
241 return DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: MVT::i32, N1: Zero, N2: SrcLo);
242 }
243 case ISD::SRL: {
244 SDValue Zero = DAG.getConstant(Val: 0, DL: dl, VT: MVT::i16);
245 return DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: MVT::i32, N1: SrcHi, N2: Zero);
246 }
247 }
248 }
249 SDValue Cnt = DAG.getTargetConstant(Val: ShiftAmount, DL: dl, VT: MVT::i8);
250 unsigned Opc;
251 switch (Op.getOpcode()) {
252 default:
253 llvm_unreachable("Invalid 32-bit shift opcode!");
254 case ISD::SHL:
255 Opc = AVRISD::LSLW;
256 break;
257 case ISD::SRL:
258 Opc = AVRISD::LSRW;
259 break;
260 case ISD::SRA:
261 Opc = AVRISD::ASRW;
262 break;
263 }
264 SDValue Result = DAG.getNode(Opcode: Opc, DL: dl, VTList: ResTys, N1: SrcLo, N2: SrcHi, N3: Cnt);
265 return DAG.getNode(Opcode: ISD::BUILD_PAIR, DL: dl, VT: MVT::i32, N1: Result.getValue(R: 0),
266 N2: Result.getValue(R: 1));
267 }
268
269 // Expand non-constant shifts to loops.
270 if (!isa<ConstantSDNode>(Val: N->getOperand(Num: 1))) {
271 switch (Op.getOpcode()) {
272 default:
273 llvm_unreachable("Invalid shift opcode!");
274 case ISD::SHL:
275 return DAG.getNode(Opcode: AVRISD::LSLLOOP, DL: dl, VT, N1: N->getOperand(Num: 0),
276 N2: N->getOperand(Num: 1));
277 case ISD::SRL:
278 return DAG.getNode(Opcode: AVRISD::LSRLOOP, DL: dl, VT, N1: N->getOperand(Num: 0),
279 N2: N->getOperand(Num: 1));
280 case ISD::ROTL: {
281 SDValue Amt = N->getOperand(Num: 1);
282 EVT AmtVT = Amt.getValueType();
283 Amt = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: AmtVT, N1: Amt,
284 N2: DAG.getConstant(Val: VT.getSizeInBits() - 1, DL: dl, VT: AmtVT));
285 return DAG.getNode(Opcode: AVRISD::ROLLOOP, DL: dl, VT, N1: N->getOperand(Num: 0), N2: Amt);
286 }
287 case ISD::ROTR: {
288 SDValue Amt = N->getOperand(Num: 1);
289 EVT AmtVT = Amt.getValueType();
290 Amt = DAG.getNode(Opcode: ISD::AND, DL: dl, VT: AmtVT, N1: Amt,
291 N2: DAG.getConstant(Val: VT.getSizeInBits() - 1, DL: dl, VT: AmtVT));
292 return DAG.getNode(Opcode: AVRISD::RORLOOP, DL: dl, VT, N1: N->getOperand(Num: 0), N2: Amt);
293 }
294 case ISD::SRA:
295 return DAG.getNode(Opcode: AVRISD::ASRLOOP, DL: dl, VT, N1: N->getOperand(Num: 0),
296 N2: N->getOperand(Num: 1));
297 }
298 }
299
300 uint64_t ShiftAmount = N->getConstantOperandVal(Num: 1);
301 SDValue Victim = N->getOperand(Num: 0);
302
303 switch (Op.getOpcode()) {
304 case ISD::SRA:
305 Opc8 = AVRISD::ASR;
306 break;
307 case ISD::ROTL:
308 Opc8 = AVRISD::ROL;
309 ShiftAmount = ShiftAmount % VT.getSizeInBits();
310 break;
311 case ISD::ROTR:
312 Opc8 = AVRISD::ROR;
313 ShiftAmount = ShiftAmount % VT.getSizeInBits();
314 break;
315 case ISD::SRL:
316 Opc8 = AVRISD::LSR;
317 break;
318 case ISD::SHL:
319 Opc8 = AVRISD::LSL;
320 break;
321 default:
322 llvm_unreachable("Invalid shift opcode");
323 }
324
325 // Optimize int8/int16 shifts.
326 if (VT.getSizeInBits() == 8) {
327 if (Op.getOpcode() == ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) {
328 // Optimize LSL when 4 <= ShiftAmount <= 6.
329 Victim = DAG.getNode(Opcode: AVRISD::SWAP, DL: dl, VT, Operand: Victim);
330 Victim =
331 DAG.getNode(Opcode: ISD::AND, DL: dl, VT, N1: Victim, N2: DAG.getConstant(Val: 0xf0, DL: dl, VT));
332 ShiftAmount -= 4;
333 } else if (Op.getOpcode() == ISD::SRL && 4 <= ShiftAmount &&
334 ShiftAmount < 7) {
335 // Optimize LSR when 4 <= ShiftAmount <= 6.
336 Victim = DAG.getNode(Opcode: AVRISD::SWAP, DL: dl, VT, Operand: Victim);
337 Victim =
338 DAG.getNode(Opcode: ISD::AND, DL: dl, VT, N1: Victim, N2: DAG.getConstant(Val: 0x0f, DL: dl, VT));
339 ShiftAmount -= 4;
340 } else if (Op.getOpcode() == ISD::SHL && ShiftAmount == 7) {
341 // Optimize LSL when ShiftAmount == 7.
342 Victim = DAG.getNode(Opcode: AVRISD::LSLBN, DL: dl, VT, N1: Victim,
343 N2: DAG.getConstant(Val: 7, DL: dl, VT));
344 ShiftAmount = 0;
345 } else if (Op.getOpcode() == ISD::SRL && ShiftAmount == 7) {
346 // Optimize LSR when ShiftAmount == 7.
347 Victim = DAG.getNode(Opcode: AVRISD::LSRBN, DL: dl, VT, N1: Victim,
348 N2: DAG.getConstant(Val: 7, DL: dl, VT));
349 ShiftAmount = 0;
350 } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 6) {
351 // Optimize ASR when ShiftAmount == 6.
352 Victim = DAG.getNode(Opcode: AVRISD::ASRBN, DL: dl, VT, N1: Victim,
353 N2: DAG.getConstant(Val: 6, DL: dl, VT));
354 ShiftAmount = 0;
355 } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 7) {
356 // Optimize ASR when ShiftAmount == 7.
357 Victim = DAG.getNode(Opcode: AVRISD::ASRBN, DL: dl, VT, N1: Victim,
358 N2: DAG.getConstant(Val: 7, DL: dl, VT));
359 ShiftAmount = 0;
360 } else if (Op.getOpcode() == ISD::ROTL && ShiftAmount == 3) {
361 // Optimize left rotation 3 bits to swap then right rotation 1 bit.
362 Victim = DAG.getNode(Opcode: AVRISD::SWAP, DL: dl, VT, Operand: Victim);
363 Victim = DAG.getNode(Opcode: AVRISD::ROR, DL: dl, VT, Operand: Victim);
364 ShiftAmount = 0;
365 } else if (Op.getOpcode() == ISD::ROTR && ShiftAmount == 3) {
366 // Optimize right rotation 3 bits to swap then left rotation 1 bit.
367 Victim = DAG.getNode(Opcode: AVRISD::SWAP, DL: dl, VT, Operand: Victim);
368 Victim = DAG.getNode(Opcode: AVRISD::ROL, DL: dl, VT, Operand: Victim);
369 ShiftAmount = 0;
370 } else if (Op.getOpcode() == ISD::ROTL && ShiftAmount == 7) {
371 // Optimize left rotation 7 bits to right rotation 1 bit.
372 Victim = DAG.getNode(Opcode: AVRISD::ROR, DL: dl, VT, Operand: Victim);
373 ShiftAmount = 0;
374 } else if (Op.getOpcode() == ISD::ROTR && ShiftAmount == 7) {
375 // Optimize right rotation 7 bits to left rotation 1 bit.
376 Victim = DAG.getNode(Opcode: AVRISD::ROL, DL: dl, VT, Operand: Victim);
377 ShiftAmount = 0;
378 } else if ((Op.getOpcode() == ISD::ROTR || Op.getOpcode() == ISD::ROTL) &&
379 ShiftAmount >= 4) {
380 // Optimize left/right rotation with the SWAP instruction.
381 Victim = DAG.getNode(Opcode: AVRISD::SWAP, DL: dl, VT, Operand: Victim);
382 ShiftAmount -= 4;
383 }
384 } else if (VT.getSizeInBits() == 16) {
385 if (Op.getOpcode() == ISD::SRA)
386 // Special optimization for int16 arithmetic right shift.
387 switch (ShiftAmount) {
388 case 15:
389 Victim = DAG.getNode(Opcode: AVRISD::ASRWN, DL: dl, VT, N1: Victim,
390 N2: DAG.getConstant(Val: 15, DL: dl, VT));
391 ShiftAmount = 0;
392 break;
393 case 14:
394 Victim = DAG.getNode(Opcode: AVRISD::ASRWN, DL: dl, VT, N1: Victim,
395 N2: DAG.getConstant(Val: 14, DL: dl, VT));
396 ShiftAmount = 0;
397 break;
398 case 7:
399 Victim = DAG.getNode(Opcode: AVRISD::ASRWN, DL: dl, VT, N1: Victim,
400 N2: DAG.getConstant(Val: 7, DL: dl, VT));
401 ShiftAmount = 0;
402 break;
403 default:
404 break;
405 }
406 if (4 <= ShiftAmount && ShiftAmount < 8)
407 switch (Op.getOpcode()) {
408 case ISD::SHL:
409 Victim = DAG.getNode(Opcode: AVRISD::LSLWN, DL: dl, VT, N1: Victim,
410 N2: DAG.getConstant(Val: 4, DL: dl, VT));
411 ShiftAmount -= 4;
412 break;
413 case ISD::SRL:
414 Victim = DAG.getNode(Opcode: AVRISD::LSRWN, DL: dl, VT, N1: Victim,
415 N2: DAG.getConstant(Val: 4, DL: dl, VT));
416 ShiftAmount -= 4;
417 break;
418 default:
419 break;
420 }
421 else if (8 <= ShiftAmount && ShiftAmount < 12)
422 switch (Op.getOpcode()) {
423 case ISD::SHL:
424 Victim = DAG.getNode(Opcode: AVRISD::LSLWN, DL: dl, VT, N1: Victim,
425 N2: DAG.getConstant(Val: 8, DL: dl, VT));
426 ShiftAmount -= 8;
427 // Only operate on the higher byte for remaining shift bits.
428 Opc8 = AVRISD::LSLHI;
429 break;
430 case ISD::SRL:
431 Victim = DAG.getNode(Opcode: AVRISD::LSRWN, DL: dl, VT, N1: Victim,
432 N2: DAG.getConstant(Val: 8, DL: dl, VT));
433 ShiftAmount -= 8;
434 // Only operate on the lower byte for remaining shift bits.
435 Opc8 = AVRISD::LSRLO;
436 break;
437 case ISD::SRA:
438 Victim = DAG.getNode(Opcode: AVRISD::ASRWN, DL: dl, VT, N1: Victim,
439 N2: DAG.getConstant(Val: 8, DL: dl, VT));
440 ShiftAmount -= 8;
441 // Only operate on the lower byte for remaining shift bits.
442 Opc8 = AVRISD::ASRLO;
443 break;
444 default:
445 break;
446 }
447 else if (12 <= ShiftAmount)
448 switch (Op.getOpcode()) {
449 case ISD::SHL:
450 Victim = DAG.getNode(Opcode: AVRISD::LSLWN, DL: dl, VT, N1: Victim,
451 N2: DAG.getConstant(Val: 12, DL: dl, VT));
452 ShiftAmount -= 12;
453 // Only operate on the higher byte for remaining shift bits.
454 Opc8 = AVRISD::LSLHI;
455 break;
456 case ISD::SRL:
457 Victim = DAG.getNode(Opcode: AVRISD::LSRWN, DL: dl, VT, N1: Victim,
458 N2: DAG.getConstant(Val: 12, DL: dl, VT));
459 ShiftAmount -= 12;
460 // Only operate on the lower byte for remaining shift bits.
461 Opc8 = AVRISD::LSRLO;
462 break;
463 case ISD::SRA:
464 Victim = DAG.getNode(Opcode: AVRISD::ASRWN, DL: dl, VT, N1: Victim,
465 N2: DAG.getConstant(Val: 8, DL: dl, VT));
466 ShiftAmount -= 8;
467 // Only operate on the lower byte for remaining shift bits.
468 Opc8 = AVRISD::ASRLO;
469 break;
470 default:
471 break;
472 }
473 }
474
475 while (ShiftAmount--) {
476 Victim = DAG.getNode(Opcode: Opc8, DL: dl, VT, Operand: Victim);
477 }
478
479 return Victim;
480}
481
482SDValue AVRTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
483 unsigned Opcode = Op->getOpcode();
484 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
485 "Invalid opcode for Div/Rem lowering");
486 bool IsSigned = (Opcode == ISD::SDIVREM);
487 EVT VT = Op->getValueType(ResNo: 0);
488 Type *Ty = VT.getTypeForEVT(Context&: *DAG.getContext());
489
490 RTLIB::Libcall LC;
491 switch (VT.getSimpleVT().SimpleTy) {
492 default:
493 llvm_unreachable("Unexpected request for libcall!");
494 case MVT::i8:
495 LC = IsSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8;
496 break;
497 case MVT::i16:
498 LC = IsSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16;
499 break;
500 case MVT::i32:
501 LC = IsSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
502 break;
503 }
504
505 SDValue InChain = DAG.getEntryNode();
506
507 TargetLowering::ArgListTy Args;
508 TargetLowering::ArgListEntry Entry;
509 for (SDValue const &Value : Op->op_values()) {
510 Entry.Node = Value;
511 Entry.Ty = Value.getValueType().getTypeForEVT(Context&: *DAG.getContext());
512 Entry.IsSExt = IsSigned;
513 Entry.IsZExt = !IsSigned;
514 Args.push_back(x: Entry);
515 }
516
517 SDValue Callee = DAG.getExternalSymbol(Sym: getLibcallName(Call: LC),
518 VT: getPointerTy(DL: DAG.getDataLayout()));
519
520 Type *RetTy = (Type *)StructType::get(elt1: Ty, elts: Ty);
521
522 SDLoc dl(Op);
523 TargetLowering::CallLoweringInfo CLI(DAG);
524 CLI.setDebugLoc(dl)
525 .setChain(InChain)
526 .setLibCallee(CC: getLibcallCallingConv(Call: LC), ResultType: RetTy, Target: Callee, ArgsList: std::move(Args))
527 .setInRegister()
528 .setSExtResult(IsSigned)
529 .setZExtResult(!IsSigned);
530
531 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
532 return CallInfo.first;
533}
534
535SDValue AVRTargetLowering::LowerGlobalAddress(SDValue Op,
536 SelectionDAG &DAG) const {
537 auto DL = DAG.getDataLayout();
538
539 const GlobalValue *GV = cast<GlobalAddressSDNode>(Val&: Op)->getGlobal();
540 int64_t Offset = cast<GlobalAddressSDNode>(Val&: Op)->getOffset();
541
542 // Create the TargetGlobalAddress node, folding in the constant offset.
543 SDValue Result =
544 DAG.getTargetGlobalAddress(GV, DL: SDLoc(Op), VT: getPointerTy(DL), offset: Offset);
545 return DAG.getNode(Opcode: AVRISD::WRAPPER, DL: SDLoc(Op), VT: getPointerTy(DL), Operand: Result);
546}
547
548SDValue AVRTargetLowering::LowerBlockAddress(SDValue Op,
549 SelectionDAG &DAG) const {
550 auto DL = DAG.getDataLayout();
551 const BlockAddress *BA = cast<BlockAddressSDNode>(Val&: Op)->getBlockAddress();
552
553 SDValue Result = DAG.getTargetBlockAddress(BA, VT: getPointerTy(DL));
554
555 return DAG.getNode(Opcode: AVRISD::WRAPPER, DL: SDLoc(Op), VT: getPointerTy(DL), Operand: Result);
556}
557
558/// IntCCToAVRCC - Convert a DAG integer condition code to an AVR CC.
559static AVRCC::CondCodes intCCToAVRCC(ISD::CondCode CC) {
560 switch (CC) {
561 default:
562 llvm_unreachable("Unknown condition code!");
563 case ISD::SETEQ:
564 return AVRCC::COND_EQ;
565 case ISD::SETNE:
566 return AVRCC::COND_NE;
567 case ISD::SETGE:
568 return AVRCC::COND_GE;
569 case ISD::SETLT:
570 return AVRCC::COND_LT;
571 case ISD::SETUGE:
572 return AVRCC::COND_SH;
573 case ISD::SETULT:
574 return AVRCC::COND_LO;
575 }
576}
577
578/// Returns appropriate CP/CPI/CPC nodes code for the given 8/16-bit operands.
579SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS,
580 SelectionDAG &DAG, SDLoc DL) const {
581 assert((LHS.getSimpleValueType() == RHS.getSimpleValueType()) &&
582 "LHS and RHS have different types");
583 assert(((LHS.getSimpleValueType() == MVT::i16) ||
584 (LHS.getSimpleValueType() == MVT::i8)) &&
585 "invalid comparison type");
586
587 SDValue Cmp;
588
589 if (LHS.getSimpleValueType() == MVT::i16 && isa<ConstantSDNode>(Val: RHS)) {
590 uint64_t Imm = RHS->getAsZExtVal();
591 // Generate a CPI/CPC pair if RHS is a 16-bit constant. Use the zero
592 // register for the constant RHS if its lower or higher byte is zero.
593 SDValue LHSlo = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8, N1: LHS,
594 N2: DAG.getIntPtrConstant(Val: 0, DL));
595 SDValue LHShi = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8, N1: LHS,
596 N2: DAG.getIntPtrConstant(Val: 1, DL));
597 SDValue RHSlo = (Imm & 0xff) == 0
598 ? DAG.getRegister(Reg: Subtarget.getZeroRegister(), VT: MVT::i8)
599 : DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8, N1: RHS,
600 N2: DAG.getIntPtrConstant(Val: 0, DL));
601 SDValue RHShi = (Imm & 0xff00) == 0
602 ? DAG.getRegister(Reg: Subtarget.getZeroRegister(), VT: MVT::i8)
603 : DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8, N1: RHS,
604 N2: DAG.getIntPtrConstant(Val: 1, DL));
605 Cmp = DAG.getNode(Opcode: AVRISD::CMP, DL, VT: MVT::Glue, N1: LHSlo, N2: RHSlo);
606 Cmp = DAG.getNode(Opcode: AVRISD::CMPC, DL, VT: MVT::Glue, N1: LHShi, N2: RHShi, N3: Cmp);
607 } else if (RHS.getSimpleValueType() == MVT::i16 && isa<ConstantSDNode>(Val: LHS)) {
608 // Generate a CPI/CPC pair if LHS is a 16-bit constant. Use the zero
609 // register for the constant LHS if its lower or higher byte is zero.
610 uint64_t Imm = LHS->getAsZExtVal();
611 SDValue LHSlo = (Imm & 0xff) == 0
612 ? DAG.getRegister(Reg: Subtarget.getZeroRegister(), VT: MVT::i8)
613 : DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8, N1: LHS,
614 N2: DAG.getIntPtrConstant(Val: 0, DL));
615 SDValue LHShi = (Imm & 0xff00) == 0
616 ? DAG.getRegister(Reg: Subtarget.getZeroRegister(), VT: MVT::i8)
617 : DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8, N1: LHS,
618 N2: DAG.getIntPtrConstant(Val: 1, DL));
619 SDValue RHSlo = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8, N1: RHS,
620 N2: DAG.getIntPtrConstant(Val: 0, DL));
621 SDValue RHShi = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8, N1: RHS,
622 N2: DAG.getIntPtrConstant(Val: 1, DL));
623 Cmp = DAG.getNode(Opcode: AVRISD::CMP, DL, VT: MVT::Glue, N1: LHSlo, N2: RHSlo);
624 Cmp = DAG.getNode(Opcode: AVRISD::CMPC, DL, VT: MVT::Glue, N1: LHShi, N2: RHShi, N3: Cmp);
625 } else {
626 // Generate ordinary 16-bit comparison.
627 Cmp = DAG.getNode(Opcode: AVRISD::CMP, DL, VT: MVT::Glue, N1: LHS, N2: RHS);
628 }
629
630 return Cmp;
631}
632
633/// Returns appropriate AVR CMP/CMPC nodes and corresponding condition code for
634/// the given operands.
635SDValue AVRTargetLowering::getAVRCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
636 SDValue &AVRcc, SelectionDAG &DAG,
637 SDLoc DL) const {
638 SDValue Cmp;
639 EVT VT = LHS.getValueType();
640 bool UseTest = false;
641
642 switch (CC) {
643 default:
644 break;
645 case ISD::SETLE: {
646 // Swap operands and reverse the branching condition.
647 std::swap(a&: LHS, b&: RHS);
648 CC = ISD::SETGE;
649 break;
650 }
651 case ISD::SETGT: {
652 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val&: RHS)) {
653 switch (C->getSExtValue()) {
654 case -1: {
655 // When doing lhs > -1 use a tst instruction on the top part of lhs
656 // and use brpl instead of using a chain of cp/cpc.
657 UseTest = true;
658 AVRcc = DAG.getConstant(Val: AVRCC::COND_PL, DL, VT: MVT::i8);
659 break;
660 }
661 case 0: {
662 // Turn lhs > 0 into 0 < lhs since 0 can be materialized with
663 // __zero_reg__ in lhs.
664 RHS = LHS;
665 LHS = DAG.getConstant(Val: 0, DL, VT);
666 CC = ISD::SETLT;
667 break;
668 }
669 default: {
670 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows
671 // us to fold the constant into the cmp instruction.
672 RHS = DAG.getConstant(Val: C->getSExtValue() + 1, DL, VT);
673 CC = ISD::SETGE;
674 break;
675 }
676 }
677 break;
678 }
679 // Swap operands and reverse the branching condition.
680 std::swap(a&: LHS, b&: RHS);
681 CC = ISD::SETLT;
682 break;
683 }
684 case ISD::SETLT: {
685 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val&: RHS)) {
686 switch (C->getSExtValue()) {
687 case 1: {
688 // Turn lhs < 1 into 0 >= lhs since 0 can be materialized with
689 // __zero_reg__ in lhs.
690 RHS = LHS;
691 LHS = DAG.getConstant(Val: 0, DL, VT);
692 CC = ISD::SETGE;
693 break;
694 }
695 case 0: {
696 // When doing lhs < 0 use a tst instruction on the top part of lhs
697 // and use brmi instead of using a chain of cp/cpc.
698 UseTest = true;
699 AVRcc = DAG.getConstant(Val: AVRCC::COND_MI, DL, VT: MVT::i8);
700 break;
701 }
702 }
703 }
704 break;
705 }
706 case ISD::SETULE: {
707 // Swap operands and reverse the branching condition.
708 std::swap(a&: LHS, b&: RHS);
709 CC = ISD::SETUGE;
710 break;
711 }
712 case ISD::SETUGT: {
713 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
714 // fold the constant into the cmp instruction.
715 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val&: RHS)) {
716 RHS = DAG.getConstant(Val: C->getSExtValue() + 1, DL, VT);
717 CC = ISD::SETUGE;
718 break;
719 }
720 // Swap operands and reverse the branching condition.
721 std::swap(a&: LHS, b&: RHS);
722 CC = ISD::SETULT;
723 break;
724 }
725 }
726
727 // Expand 32 and 64 bit comparisons with custom CMP and CMPC nodes instead of
728 // using the default and/or/xor expansion code which is much longer.
729 if (VT == MVT::i32) {
730 SDValue LHSlo = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: LHS,
731 N2: DAG.getIntPtrConstant(Val: 0, DL));
732 SDValue LHShi = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: LHS,
733 N2: DAG.getIntPtrConstant(Val: 1, DL));
734 SDValue RHSlo = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: RHS,
735 N2: DAG.getIntPtrConstant(Val: 0, DL));
736 SDValue RHShi = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: RHS,
737 N2: DAG.getIntPtrConstant(Val: 1, DL));
738
739 if (UseTest) {
740 // When using tst we only care about the highest part.
741 SDValue Top = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8, N1: LHShi,
742 N2: DAG.getIntPtrConstant(Val: 1, DL));
743 Cmp = DAG.getNode(Opcode: AVRISD::TST, DL, VT: MVT::Glue, Operand: Top);
744 } else {
745 Cmp = getAVRCmp(LHS: LHSlo, RHS: RHSlo, DAG, DL);
746 Cmp = DAG.getNode(Opcode: AVRISD::CMPC, DL, VT: MVT::Glue, N1: LHShi, N2: RHShi, N3: Cmp);
747 }
748 } else if (VT == MVT::i64) {
749 SDValue LHS_0 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i32, N1: LHS,
750 N2: DAG.getIntPtrConstant(Val: 0, DL));
751 SDValue LHS_1 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i32, N1: LHS,
752 N2: DAG.getIntPtrConstant(Val: 1, DL));
753
754 SDValue LHS0 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: LHS_0,
755 N2: DAG.getIntPtrConstant(Val: 0, DL));
756 SDValue LHS1 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: LHS_0,
757 N2: DAG.getIntPtrConstant(Val: 1, DL));
758 SDValue LHS2 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: LHS_1,
759 N2: DAG.getIntPtrConstant(Val: 0, DL));
760 SDValue LHS3 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: LHS_1,
761 N2: DAG.getIntPtrConstant(Val: 1, DL));
762
763 SDValue RHS_0 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i32, N1: RHS,
764 N2: DAG.getIntPtrConstant(Val: 0, DL));
765 SDValue RHS_1 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i32, N1: RHS,
766 N2: DAG.getIntPtrConstant(Val: 1, DL));
767
768 SDValue RHS0 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: RHS_0,
769 N2: DAG.getIntPtrConstant(Val: 0, DL));
770 SDValue RHS1 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: RHS_0,
771 N2: DAG.getIntPtrConstant(Val: 1, DL));
772 SDValue RHS2 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: RHS_1,
773 N2: DAG.getIntPtrConstant(Val: 0, DL));
774 SDValue RHS3 = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i16, N1: RHS_1,
775 N2: DAG.getIntPtrConstant(Val: 1, DL));
776
777 if (UseTest) {
778 // When using tst we only care about the highest part.
779 SDValue Top = DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8, N1: LHS3,
780 N2: DAG.getIntPtrConstant(Val: 1, DL));
781 Cmp = DAG.getNode(Opcode: AVRISD::TST, DL, VT: MVT::Glue, Operand: Top);
782 } else {
783 Cmp = getAVRCmp(LHS: LHS0, RHS: RHS0, DAG, DL);
784 Cmp = DAG.getNode(Opcode: AVRISD::CMPC, DL, VT: MVT::Glue, N1: LHS1, N2: RHS1, N3: Cmp);
785 Cmp = DAG.getNode(Opcode: AVRISD::CMPC, DL, VT: MVT::Glue, N1: LHS2, N2: RHS2, N3: Cmp);
786 Cmp = DAG.getNode(Opcode: AVRISD::CMPC, DL, VT: MVT::Glue, N1: LHS3, N2: RHS3, N3: Cmp);
787 }
788 } else if (VT == MVT::i8 || VT == MVT::i16) {
789 if (UseTest) {
790 // When using tst we only care about the highest part.
791 Cmp = DAG.getNode(Opcode: AVRISD::TST, DL, VT: MVT::Glue,
792 Operand: (VT == MVT::i8)
793 ? LHS
794 : DAG.getNode(Opcode: ISD::EXTRACT_ELEMENT, DL, VT: MVT::i8,
795 N1: LHS, N2: DAG.getIntPtrConstant(Val: 1, DL)));
796 } else {
797 Cmp = getAVRCmp(LHS, RHS, DAG, DL);
798 }
799 } else {
800 llvm_unreachable("Invalid comparison size");
801 }
802
803 // When using a test instruction AVRcc is already set.
804 if (!UseTest) {
805 AVRcc = DAG.getConstant(Val: intCCToAVRCC(CC), DL, VT: MVT::i8);
806 }
807
808 return Cmp;
809}
810
811SDValue AVRTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
812 SDValue Chain = Op.getOperand(i: 0);
813 ISD::CondCode CC = cast<CondCodeSDNode>(Val: Op.getOperand(i: 1))->get();
814 SDValue LHS = Op.getOperand(i: 2);
815 SDValue RHS = Op.getOperand(i: 3);
816 SDValue Dest = Op.getOperand(i: 4);
817 SDLoc dl(Op);
818
819 SDValue TargetCC;
820 SDValue Cmp = getAVRCmp(LHS, RHS, CC, AVRcc&: TargetCC, DAG, DL: dl);
821
822 return DAG.getNode(Opcode: AVRISD::BRCOND, DL: dl, VT: MVT::Other, N1: Chain, N2: Dest, N3: TargetCC,
823 N4: Cmp);
824}
825
826SDValue AVRTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
827 SDValue LHS = Op.getOperand(i: 0);
828 SDValue RHS = Op.getOperand(i: 1);
829 SDValue TrueV = Op.getOperand(i: 2);
830 SDValue FalseV = Op.getOperand(i: 3);
831 ISD::CondCode CC = cast<CondCodeSDNode>(Val: Op.getOperand(i: 4))->get();
832 SDLoc dl(Op);
833
834 SDValue TargetCC;
835 SDValue Cmp = getAVRCmp(LHS, RHS, CC, AVRcc&: TargetCC, DAG, DL: dl);
836
837 SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
838
839 return DAG.getNode(Opcode: AVRISD::SELECT_CC, DL: dl, VT: Op.getValueType(), Ops);
840}
841
842SDValue AVRTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
843 SDValue LHS = Op.getOperand(i: 0);
844 SDValue RHS = Op.getOperand(i: 1);
845 ISD::CondCode CC = cast<CondCodeSDNode>(Val: Op.getOperand(i: 2))->get();
846 SDLoc DL(Op);
847
848 SDValue TargetCC;
849 SDValue Cmp = getAVRCmp(LHS, RHS, CC, AVRcc&: TargetCC, DAG, DL);
850
851 SDValue TrueV = DAG.getConstant(Val: 1, DL, VT: Op.getValueType());
852 SDValue FalseV = DAG.getConstant(Val: 0, DL, VT: Op.getValueType());
853 SDValue Ops[] = {TrueV, FalseV, TargetCC, Cmp};
854
855 return DAG.getNode(Opcode: AVRISD::SELECT_CC, DL, VT: Op.getValueType(), Ops);
856}
857
858SDValue AVRTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
859 const MachineFunction &MF = DAG.getMachineFunction();
860 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
861 const Value *SV = cast<SrcValueSDNode>(Val: Op.getOperand(i: 2))->getValue();
862 auto DL = DAG.getDataLayout();
863 SDLoc dl(Op);
864
865 // Vastart just stores the address of the VarArgsFrameIndex slot into the
866 // memory location argument.
867 SDValue FI = DAG.getFrameIndex(FI: AFI->getVarArgsFrameIndex(), VT: getPointerTy(DL));
868
869 return DAG.getStore(Chain: Op.getOperand(i: 0), dl, Val: FI, Ptr: Op.getOperand(i: 1),
870 PtrInfo: MachinePointerInfo(SV));
871}
872
873// Modify the existing ISD::INLINEASM node to add the implicit zero register.
874SDValue AVRTargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const {
875 SDValue ZeroReg = DAG.getRegister(Reg: Subtarget.getZeroRegister(), VT: MVT::i8);
876 if (Op.getOperand(i: Op.getNumOperands() - 1) == ZeroReg ||
877 Op.getOperand(i: Op.getNumOperands() - 2) == ZeroReg) {
878 // Zero register has already been added. Don't add it again.
879 // If this isn't handled, we get called over and over again.
880 return Op;
881 }
882
883 // Get a list of operands to the new INLINEASM node. This is mostly a copy,
884 // with some edits.
885 // Add the following operands at the end (but before the glue node, if it's
886 // there):
887 // - The flags of the implicit zero register operand.
888 // - The implicit zero register operand itself.
889 SDLoc dl(Op);
890 SmallVector<SDValue, 8> Ops;
891 SDNode *N = Op.getNode();
892 SDValue Glue;
893 for (unsigned I = 0; I < N->getNumOperands(); I++) {
894 SDValue Operand = N->getOperand(Num: I);
895 if (Operand.getValueType() == MVT::Glue) {
896 // The glue operand always needs to be at the end, so we need to treat it
897 // specially.
898 Glue = Operand;
899 } else {
900 Ops.push_back(Elt: Operand);
901 }
902 }
903 InlineAsm::Flag Flags(InlineAsm::Kind::RegUse, 1);
904 Ops.push_back(Elt: DAG.getTargetConstant(Val: Flags, DL: dl, VT: MVT::i32));
905 Ops.push_back(Elt: ZeroReg);
906 if (Glue) {
907 Ops.push_back(Elt: Glue);
908 }
909
910 // Replace the current INLINEASM node with a new one that has the zero
911 // register as implicit parameter.
912 SDValue New = DAG.getNode(Opcode: N->getOpcode(), DL: dl, VTList: N->getVTList(), Ops);
913 DAG.ReplaceAllUsesOfValueWith(From: Op, To: New);
914 DAG.ReplaceAllUsesOfValueWith(From: Op.getValue(R: 1), To: New.getValue(R: 1));
915
916 return New;
917}
918
919SDValue AVRTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
920 switch (Op.getOpcode()) {
921 default:
922 llvm_unreachable("Don't know how to custom lower this!");
923 case ISD::SHL:
924 case ISD::SRA:
925 case ISD::SRL:
926 case ISD::ROTL:
927 case ISD::ROTR:
928 return LowerShifts(Op, DAG);
929 case ISD::GlobalAddress:
930 return LowerGlobalAddress(Op, DAG);
931 case ISD::BlockAddress:
932 return LowerBlockAddress(Op, DAG);
933 case ISD::BR_CC:
934 return LowerBR_CC(Op, DAG);
935 case ISD::SELECT_CC:
936 return LowerSELECT_CC(Op, DAG);
937 case ISD::SETCC:
938 return LowerSETCC(Op, DAG);
939 case ISD::VASTART:
940 return LowerVASTART(Op, DAG);
941 case ISD::SDIVREM:
942 case ISD::UDIVREM:
943 return LowerDivRem(Op, DAG);
944 case ISD::INLINEASM:
945 return LowerINLINEASM(Op, DAG);
946 }
947
948 return SDValue();
949}
950
951/// Replace a node with an illegal result type
952/// with a new node built out of custom code.
953void AVRTargetLowering::ReplaceNodeResults(SDNode *N,
954 SmallVectorImpl<SDValue> &Results,
955 SelectionDAG &DAG) const {
956 SDLoc DL(N);
957
958 switch (N->getOpcode()) {
959 case ISD::ADD: {
960 // Convert add (x, imm) into sub (x, -imm).
961 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val: N->getOperand(Num: 1))) {
962 SDValue Sub = DAG.getNode(
963 Opcode: ISD::SUB, DL, VT: N->getValueType(ResNo: 0), N1: N->getOperand(Num: 0),
964 N2: DAG.getConstant(Val: -C->getAPIntValue(), DL, VT: C->getValueType(ResNo: 0)));
965 Results.push_back(Elt: Sub);
966 }
967 break;
968 }
969 default: {
970 SDValue Res = LowerOperation(Op: SDValue(N, 0), DAG);
971
972 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
973 Results.push_back(Elt: Res.getValue(R: I));
974
975 break;
976 }
977 }
978}
979
980/// Return true if the addressing mode represented
981/// by AM is legal for this target, for a load/store of the specified type.
982bool AVRTargetLowering::isLegalAddressingMode(const DataLayout &DL,
983 const AddrMode &AM, Type *Ty,
984 unsigned AS,
985 Instruction *I) const {
986 int64_t Offs = AM.BaseOffs;
987
988 // Allow absolute addresses.
989 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && Offs == 0) {
990 return true;
991 }
992
993 // Flash memory instructions only allow zero offsets.
994 if (isa<PointerType>(Val: Ty) && AS == AVR::ProgramMemory) {
995 return false;
996 }
997
998 // Allow reg+<6bit> offset.
999 if (Offs < 0)
1000 Offs = -Offs;
1001 if (AM.BaseGV == nullptr && AM.HasBaseReg && AM.Scale == 0 &&
1002 isUInt<6>(x: Offs)) {
1003 return true;
1004 }
1005
1006 return false;
1007}
1008
1009/// Returns true by value, base pointer and
1010/// offset pointer and addressing mode by reference if the node's address
1011/// can be legally represented as pre-indexed load / store address.
1012bool AVRTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1013 SDValue &Offset,
1014 ISD::MemIndexedMode &AM,
1015 SelectionDAG &DAG) const {
1016 EVT VT;
1017 const SDNode *Op;
1018 SDLoc DL(N);
1019
1020 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(Val: N)) {
1021 VT = LD->getMemoryVT();
1022 Op = LD->getBasePtr().getNode();
1023 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
1024 return false;
1025 if (AVR::isProgramMemoryAccess(N: LD)) {
1026 return false;
1027 }
1028 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(Val: N)) {
1029 VT = ST->getMemoryVT();
1030 Op = ST->getBasePtr().getNode();
1031 if (AVR::isProgramMemoryAccess(N: ST)) {
1032 return false;
1033 }
1034 } else {
1035 return false;
1036 }
1037
1038 if (VT != MVT::i8 && VT != MVT::i16) {
1039 return false;
1040 }
1041
1042 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
1043 return false;
1044 }
1045
1046 if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Val: Op->getOperand(Num: 1))) {
1047 int RHSC = RHS->getSExtValue();
1048 if (Op->getOpcode() == ISD::SUB)
1049 RHSC = -RHSC;
1050
1051 if ((VT == MVT::i16 && RHSC != -2) || (VT == MVT::i8 && RHSC != -1)) {
1052 return false;
1053 }
1054
1055 Base = Op->getOperand(Num: 0);
1056 Offset = DAG.getSignedConstant(Val: RHSC, DL, VT: MVT::i8);
1057 AM = ISD::PRE_DEC;
1058
1059 return true;
1060 }
1061
1062 return false;
1063}
1064
1065/// Returns true by value, base pointer and
1066/// offset pointer and addressing mode by reference if this node can be
1067/// combined with a load / store to form a post-indexed load / store.
1068bool AVRTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1069 SDValue &Base,
1070 SDValue &Offset,
1071 ISD::MemIndexedMode &AM,
1072 SelectionDAG &DAG) const {
1073 EVT VT;
1074 SDValue Ptr;
1075 SDLoc DL(N);
1076
1077 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(Val: N)) {
1078 VT = LD->getMemoryVT();
1079 Ptr = LD->getBasePtr();
1080 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
1081 return false;
1082 } else if (const StoreSDNode *ST = dyn_cast<StoreSDNode>(Val: N)) {
1083 VT = ST->getMemoryVT();
1084 Ptr = ST->getBasePtr();
1085 // We can not store to program memory.
1086 if (AVR::isProgramMemoryAccess(N: ST))
1087 return false;
1088 // Since the high byte need to be stored first, we can not emit
1089 // i16 post increment store like:
1090 // st X+, r24
1091 // st X+, r25
1092 if (VT == MVT::i16 && !Subtarget.hasLowByteFirst())
1093 return false;
1094 } else {
1095 return false;
1096 }
1097
1098 if (VT != MVT::i8 && VT != MVT::i16) {
1099 return false;
1100 }
1101
1102 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB) {
1103 return false;
1104 }
1105
1106 if (const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Val: Op->getOperand(Num: 1))) {
1107 int RHSC = RHS->getSExtValue();
1108 if (Op->getOpcode() == ISD::SUB)
1109 RHSC = -RHSC;
1110 if ((VT == MVT::i16 && RHSC != 2) || (VT == MVT::i8 && RHSC != 1)) {
1111 return false;
1112 }
1113
1114 // FIXME: We temporarily disable post increment load from program memory,
1115 // due to bug https://github.com/llvm/llvm-project/issues/59914.
1116 if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(Val: N))
1117 if (AVR::isProgramMemoryAccess(N: LD))
1118 return false;
1119
1120 Base = Op->getOperand(Num: 0);
1121
1122 // Post-indexing updates the base, so it's not a valid transform
1123 // if that's not the same as the load's pointer.
1124 if (Ptr != Base)
1125 return false;
1126
1127 Offset = DAG.getConstant(Val: RHSC, DL, VT: MVT::i8);
1128 AM = ISD::POST_INC;
1129
1130 return true;
1131 }
1132
1133 return false;
1134}
1135
1136bool AVRTargetLowering::isOffsetFoldingLegal(
1137 const GlobalAddressSDNode *GA) const {
1138 return true;
1139}
1140
1141//===----------------------------------------------------------------------===//
1142// Formal Arguments Calling Convention Implementation
1143//===----------------------------------------------------------------------===//
1144
1145#include "AVRGenCallingConv.inc"
1146
1147/// Registers for calling conventions, ordered in reverse as required by ABI.
1148/// Both arrays must be of the same length.
1149static const MCPhysReg RegList8AVR[] = {
1150 AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20,
1151 AVR::R19, AVR::R18, AVR::R17, AVR::R16, AVR::R15, AVR::R14,
1152 AVR::R13, AVR::R12, AVR::R11, AVR::R10, AVR::R9, AVR::R8};
1153static const MCPhysReg RegList8Tiny[] = {AVR::R25, AVR::R24, AVR::R23,
1154 AVR::R22, AVR::R21, AVR::R20};
1155static const MCPhysReg RegList16AVR[] = {
1156 AVR::R26R25, AVR::R25R24, AVR::R24R23, AVR::R23R22, AVR::R22R21,
1157 AVR::R21R20, AVR::R20R19, AVR::R19R18, AVR::R18R17, AVR::R17R16,
1158 AVR::R16R15, AVR::R15R14, AVR::R14R13, AVR::R13R12, AVR::R12R11,
1159 AVR::R11R10, AVR::R10R9, AVR::R9R8};
1160static const MCPhysReg RegList16Tiny[] = {AVR::R26R25, AVR::R25R24,
1161 AVR::R24R23, AVR::R23R22,
1162 AVR::R22R21, AVR::R21R20};
1163
1164static_assert(std::size(RegList8AVR) == std::size(RegList16AVR),
1165 "8-bit and 16-bit register arrays must be of equal length");
1166static_assert(std::size(RegList8Tiny) == std::size(RegList16Tiny),
1167 "8-bit and 16-bit register arrays must be of equal length");
1168
1169/// Analyze incoming and outgoing function arguments. We need custom C++ code
1170/// to handle special constraints in the ABI.
1171/// In addition, all pieces of a certain argument have to be passed either
1172/// using registers or the stack but never mixing both.
1173template <typename ArgT>
1174static void analyzeArguments(TargetLowering::CallLoweringInfo *CLI,
1175 const Function *F, const DataLayout *TD,
1176 const SmallVectorImpl<ArgT> &Args,
1177 SmallVectorImpl<CCValAssign> &ArgLocs,
1178 CCState &CCInfo, bool Tiny) {
1179 // Choose the proper register list for argument passing according to the ABI.
1180 ArrayRef<MCPhysReg> RegList8;
1181 ArrayRef<MCPhysReg> RegList16;
1182 if (Tiny) {
1183 RegList8 = ArrayRef(RegList8Tiny);
1184 RegList16 = ArrayRef(RegList16Tiny);
1185 } else {
1186 RegList8 = ArrayRef(RegList8AVR);
1187 RegList16 = ArrayRef(RegList16AVR);
1188 }
1189
1190 unsigned NumArgs = Args.size();
1191 // This is the index of the last used register, in RegList*.
1192 // -1 means R26 (R26 is never actually used in CC).
1193 int RegLastIdx = -1;
1194 // Once a value is passed to the stack it will always be used
1195 bool UseStack = false;
1196 for (unsigned i = 0; i != NumArgs;) {
1197 MVT VT = Args[i].VT;
1198 // We have to count the number of bytes for each function argument, that is
1199 // those Args with the same OrigArgIndex. This is important in case the
1200 // function takes an aggregate type.
1201 // Current argument will be between [i..j).
1202 unsigned ArgIndex = Args[i].OrigArgIndex;
1203 unsigned TotalBytes = VT.getStoreSize();
1204 unsigned j = i + 1;
1205 for (; j != NumArgs; ++j) {
1206 if (Args[j].OrigArgIndex != ArgIndex)
1207 break;
1208 TotalBytes += Args[j].VT.getStoreSize();
1209 }
1210 // Round up to even number of bytes.
1211 TotalBytes = alignTo(Value: TotalBytes, Align: 2);
1212 // Skip zero sized arguments
1213 if (TotalBytes == 0)
1214 continue;
1215 // The index of the first register to be used
1216 unsigned RegIdx = RegLastIdx + TotalBytes;
1217 RegLastIdx = RegIdx;
1218 // If there are not enough registers, use the stack
1219 if (RegIdx >= RegList8.size()) {
1220 UseStack = true;
1221 }
1222 for (; i != j; ++i) {
1223 MVT VT = Args[i].VT;
1224
1225 if (UseStack) {
1226 auto evt = EVT(VT).getTypeForEVT(Context&: CCInfo.getContext());
1227 unsigned Offset = CCInfo.AllocateStack(Size: TD->getTypeAllocSize(Ty: evt),
1228 Alignment: TD->getABITypeAlign(Ty: evt));
1229 CCInfo.addLoc(
1230 V: CCValAssign::getMem(ValNo: i, ValVT: VT, Offset, LocVT: VT, HTP: CCValAssign::Full));
1231 } else {
1232 unsigned Reg;
1233 if (VT == MVT::i8) {
1234 Reg = CCInfo.AllocateReg(Reg: RegList8[RegIdx]);
1235 } else if (VT == MVT::i16) {
1236 Reg = CCInfo.AllocateReg(Reg: RegList16[RegIdx]);
1237 } else {
1238 llvm_unreachable(
1239 "calling convention can only manage i8 and i16 types");
1240 }
1241 assert(Reg && "register not available in calling convention");
1242 CCInfo.addLoc(V: CCValAssign::getReg(ValNo: i, ValVT: VT, Reg, LocVT: VT, HTP: CCValAssign::Full));
1243 // Registers inside a particular argument are sorted in increasing order
1244 // (remember the array is reversed).
1245 RegIdx -= VT.getStoreSize();
1246 }
1247 }
1248 }
1249}
1250
1251/// Count the total number of bytes needed to pass or return these arguments.
1252template <typename ArgT>
1253static unsigned
1254getTotalArgumentsSizeInBytes(const SmallVectorImpl<ArgT> &Args) {
1255 unsigned TotalBytes = 0;
1256
1257 for (const ArgT &Arg : Args) {
1258 TotalBytes += Arg.VT.getStoreSize();
1259 }
1260 return TotalBytes;
1261}
1262
1263/// Analyze incoming and outgoing value of returning from a function.
1264/// The algorithm is similar to analyzeArguments, but there can only be
1265/// one value, possibly an aggregate, and it is limited to 8 bytes.
1266template <typename ArgT>
1267static void analyzeReturnValues(const SmallVectorImpl<ArgT> &Args,
1268 CCState &CCInfo, bool Tiny) {
1269 unsigned NumArgs = Args.size();
1270 unsigned TotalBytes = getTotalArgumentsSizeInBytes(Args);
1271 // CanLowerReturn() guarantees this assertion.
1272 if (Tiny)
1273 assert(TotalBytes <= 4 &&
1274 "return values greater than 4 bytes cannot be lowered on AVRTiny");
1275 else
1276 assert(TotalBytes <= 8 &&
1277 "return values greater than 8 bytes cannot be lowered on AVR");
1278
1279 // Choose the proper register list for argument passing according to the ABI.
1280 ArrayRef<MCPhysReg> RegList8;
1281 ArrayRef<MCPhysReg> RegList16;
1282 if (Tiny) {
1283 RegList8 = ArrayRef(RegList8Tiny);
1284 RegList16 = ArrayRef(RegList16Tiny);
1285 } else {
1286 RegList8 = ArrayRef(RegList8AVR);
1287 RegList16 = ArrayRef(RegList16AVR);
1288 }
1289
1290 // GCC-ABI says that the size is rounded up to the next even number,
1291 // but actually once it is more than 4 it will always round up to 8.
1292 if (TotalBytes > 4) {
1293 TotalBytes = 8;
1294 } else {
1295 TotalBytes = alignTo(Value: TotalBytes, Align: 2);
1296 }
1297
1298 // The index of the first register to use.
1299 int RegIdx = TotalBytes - 1;
1300 for (unsigned i = 0; i != NumArgs; ++i) {
1301 MVT VT = Args[i].VT;
1302 unsigned Reg;
1303 if (VT == MVT::i8) {
1304 Reg = CCInfo.AllocateReg(Reg: RegList8[RegIdx]);
1305 } else if (VT == MVT::i16) {
1306 Reg = CCInfo.AllocateReg(Reg: RegList16[RegIdx]);
1307 } else {
1308 llvm_unreachable("calling convention can only manage i8 and i16 types");
1309 }
1310 assert(Reg && "register not available in calling convention");
1311 CCInfo.addLoc(V: CCValAssign::getReg(ValNo: i, ValVT: VT, Reg, LocVT: VT, HTP: CCValAssign::Full));
1312 // Registers sort in increasing order
1313 RegIdx -= VT.getStoreSize();
1314 }
1315}
1316
1317SDValue AVRTargetLowering::LowerFormalArguments(
1318 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1319 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1320 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1321 MachineFunction &MF = DAG.getMachineFunction();
1322 MachineFrameInfo &MFI = MF.getFrameInfo();
1323 auto DL = DAG.getDataLayout();
1324
1325 // Assign locations to all of the incoming arguments.
1326 SmallVector<CCValAssign, 16> ArgLocs;
1327 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1328 *DAG.getContext());
1329
1330 // Variadic functions do not need all the analysis below.
1331 if (isVarArg) {
1332 CCInfo.AnalyzeFormalArguments(Ins, Fn: ArgCC_AVR_Vararg);
1333 } else {
1334 analyzeArguments(CLI: nullptr, F: &MF.getFunction(), TD: &DL, Args: Ins, ArgLocs, CCInfo,
1335 Tiny: Subtarget.hasTinyEncoding());
1336 }
1337
1338 SDValue ArgValue;
1339 for (CCValAssign &VA : ArgLocs) {
1340
1341 // Arguments stored on registers.
1342 if (VA.isRegLoc()) {
1343 EVT RegVT = VA.getLocVT();
1344 const TargetRegisterClass *RC;
1345 if (RegVT == MVT::i8) {
1346 RC = &AVR::GPR8RegClass;
1347 } else if (RegVT == MVT::i16) {
1348 RC = &AVR::DREGSRegClass;
1349 } else {
1350 llvm_unreachable("Unknown argument type!");
1351 }
1352
1353 Register Reg = MF.addLiveIn(PReg: VA.getLocReg(), RC);
1354 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, VT: RegVT);
1355
1356 // :NOTE: Clang should not promote any i8 into i16 but for safety the
1357 // following code will handle zexts or sexts generated by other
1358 // front ends. Otherwise:
1359 // If this is an 8 bit value, it is really passed promoted
1360 // to 16 bits. Insert an assert[sz]ext to capture this, then
1361 // truncate to the right size.
1362 switch (VA.getLocInfo()) {
1363 default:
1364 llvm_unreachable("Unknown loc info!");
1365 case CCValAssign::Full:
1366 break;
1367 case CCValAssign::BCvt:
1368 ArgValue = DAG.getNode(Opcode: ISD::BITCAST, DL: dl, VT: VA.getValVT(), Operand: ArgValue);
1369 break;
1370 case CCValAssign::SExt:
1371 ArgValue = DAG.getNode(Opcode: ISD::AssertSext, DL: dl, VT: RegVT, N1: ArgValue,
1372 N2: DAG.getValueType(VA.getValVT()));
1373 ArgValue = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: VA.getValVT(), Operand: ArgValue);
1374 break;
1375 case CCValAssign::ZExt:
1376 ArgValue = DAG.getNode(Opcode: ISD::AssertZext, DL: dl, VT: RegVT, N1: ArgValue,
1377 N2: DAG.getValueType(VA.getValVT()));
1378 ArgValue = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: VA.getValVT(), Operand: ArgValue);
1379 break;
1380 }
1381
1382 InVals.push_back(Elt: ArgValue);
1383 } else {
1384 // Only arguments passed on the stack should make it here.
1385 assert(VA.isMemLoc());
1386
1387 EVT LocVT = VA.getLocVT();
1388
1389 // Create the frame index object for this incoming parameter.
1390 int FI = MFI.CreateFixedObject(Size: LocVT.getSizeInBits() / 8,
1391 SPOffset: VA.getLocMemOffset(), IsImmutable: true);
1392
1393 // Create the SelectionDAG nodes corresponding to a load
1394 // from this parameter.
1395 SDValue FIN = DAG.getFrameIndex(FI, VT: getPointerTy(DL));
1396 InVals.push_back(Elt: DAG.getLoad(VT: LocVT, dl, Chain, Ptr: FIN,
1397 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI)));
1398 }
1399 }
1400
1401 // If the function takes variable number of arguments, make a frame index for
1402 // the start of the first vararg value... for expansion of llvm.va_start.
1403 if (isVarArg) {
1404 unsigned StackSize = CCInfo.getStackSize();
1405 AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1406
1407 AFI->setVarArgsFrameIndex(MFI.CreateFixedObject(Size: 2, SPOffset: StackSize, IsImmutable: true));
1408 }
1409
1410 return Chain;
1411}
1412
1413//===----------------------------------------------------------------------===//
1414// Call Calling Convention Implementation
1415//===----------------------------------------------------------------------===//
1416
1417SDValue AVRTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1418 SmallVectorImpl<SDValue> &InVals) const {
1419 SelectionDAG &DAG = CLI.DAG;
1420 SDLoc &DL = CLI.DL;
1421 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1422 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1423 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1424 SDValue Chain = CLI.Chain;
1425 SDValue Callee = CLI.Callee;
1426 bool &isTailCall = CLI.IsTailCall;
1427 CallingConv::ID CallConv = CLI.CallConv;
1428 bool isVarArg = CLI.IsVarArg;
1429
1430 MachineFunction &MF = DAG.getMachineFunction();
1431
1432 // AVR does not yet support tail call optimization.
1433 isTailCall = false;
1434
1435 // Analyze operands of the call, assigning locations to each operand.
1436 SmallVector<CCValAssign, 16> ArgLocs;
1437 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1438 *DAG.getContext());
1439
1440 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1441 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1442 // node so that legalize doesn't hack it.
1443 const Function *F = nullptr;
1444 if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Val&: Callee)) {
1445 const GlobalValue *GV = G->getGlobal();
1446 if (isa<Function>(Val: GV))
1447 F = cast<Function>(Val: GV);
1448 Callee =
1449 DAG.getTargetGlobalAddress(GV, DL, VT: getPointerTy(DL: DAG.getDataLayout()));
1450 } else if (const ExternalSymbolSDNode *ES =
1451 dyn_cast<ExternalSymbolSDNode>(Val&: Callee)) {
1452 Callee = DAG.getTargetExternalSymbol(Sym: ES->getSymbol(),
1453 VT: getPointerTy(DL: DAG.getDataLayout()));
1454 }
1455
1456 // Variadic functions do not need all the analysis below.
1457 if (isVarArg) {
1458 CCInfo.AnalyzeCallOperands(Outs, Fn: ArgCC_AVR_Vararg);
1459 } else {
1460 analyzeArguments(CLI: &CLI, F, TD: &DAG.getDataLayout(), Args: Outs, ArgLocs, CCInfo,
1461 Tiny: Subtarget.hasTinyEncoding());
1462 }
1463
1464 // Get a count of how many bytes are to be pushed on the stack.
1465 unsigned NumBytes = CCInfo.getStackSize();
1466
1467 Chain = DAG.getCALLSEQ_START(Chain, InSize: NumBytes, OutSize: 0, DL);
1468
1469 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1470
1471 // First, walk the register assignments, inserting copies.
1472 unsigned AI, AE;
1473 bool HasStackArgs = false;
1474 for (AI = 0, AE = ArgLocs.size(); AI != AE; ++AI) {
1475 CCValAssign &VA = ArgLocs[AI];
1476 EVT RegVT = VA.getLocVT();
1477 SDValue Arg = OutVals[AI];
1478
1479 // Promote the value if needed. With Clang this should not happen.
1480 switch (VA.getLocInfo()) {
1481 default:
1482 llvm_unreachable("Unknown loc info!");
1483 case CCValAssign::Full:
1484 break;
1485 case CCValAssign::SExt:
1486 Arg = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL, VT: RegVT, Operand: Arg);
1487 break;
1488 case CCValAssign::ZExt:
1489 Arg = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL, VT: RegVT, Operand: Arg);
1490 break;
1491 case CCValAssign::AExt:
1492 Arg = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: RegVT, Operand: Arg);
1493 break;
1494 case CCValAssign::BCvt:
1495 Arg = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: RegVT, Operand: Arg);
1496 break;
1497 }
1498
1499 // Stop when we encounter a stack argument, we need to process them
1500 // in reverse order in the loop below.
1501 if (VA.isMemLoc()) {
1502 HasStackArgs = true;
1503 break;
1504 }
1505
1506 // Arguments that can be passed on registers must be kept in the RegsToPass
1507 // vector.
1508 RegsToPass.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: Arg));
1509 }
1510
1511 // Second, stack arguments have to walked.
1512 // Previously this code created chained stores but those chained stores appear
1513 // to be unchained in the legalization phase. Therefore, do not attempt to
1514 // chain them here. In fact, chaining them here somehow causes the first and
1515 // second store to be reversed which is the exact opposite of the intended
1516 // effect.
1517 if (HasStackArgs) {
1518 SmallVector<SDValue, 8> MemOpChains;
1519 for (; AI != AE; AI++) {
1520 CCValAssign &VA = ArgLocs[AI];
1521 SDValue Arg = OutVals[AI];
1522
1523 assert(VA.isMemLoc());
1524
1525 // SP points to one stack slot further so add one to adjust it.
1526 SDValue PtrOff = DAG.getNode(
1527 Opcode: ISD::ADD, DL, VT: getPointerTy(DL: DAG.getDataLayout()),
1528 N1: DAG.getRegister(Reg: AVR::SP, VT: getPointerTy(DL: DAG.getDataLayout())),
1529 N2: DAG.getIntPtrConstant(Val: VA.getLocMemOffset() + 1, DL));
1530
1531 MemOpChains.push_back(
1532 Elt: DAG.getStore(Chain, dl: DL, Val: Arg, Ptr: PtrOff,
1533 PtrInfo: MachinePointerInfo::getStack(MF, Offset: VA.getLocMemOffset())));
1534 }
1535
1536 if (!MemOpChains.empty())
1537 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, Ops: MemOpChains);
1538 }
1539
1540 // Build a sequence of copy-to-reg nodes chained together with token chain and
1541 // flag operands which copy the outgoing args into registers. The InGlue in
1542 // necessary since all emited instructions must be stuck together.
1543 SDValue InGlue;
1544 for (auto Reg : RegsToPass) {
1545 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: Reg.first, N: Reg.second, Glue: InGlue);
1546 InGlue = Chain.getValue(R: 1);
1547 }
1548
1549 // Returns a chain & a flag for retval copy to use.
1550 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
1551 SmallVector<SDValue, 8> Ops;
1552 Ops.push_back(Elt: Chain);
1553 Ops.push_back(Elt: Callee);
1554
1555 // Add argument registers to the end of the list so that they are known live
1556 // into the call.
1557 for (auto Reg : RegsToPass) {
1558 Ops.push_back(Elt: DAG.getRegister(Reg: Reg.first, VT: Reg.second.getValueType()));
1559 }
1560
1561 // The zero register (usually R1) must be passed as an implicit register so
1562 // that this register is correctly zeroed in interrupts.
1563 Ops.push_back(Elt: DAG.getRegister(Reg: Subtarget.getZeroRegister(), VT: MVT::i8));
1564
1565 // Add a register mask operand representing the call-preserved registers.
1566 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1567 const uint32_t *Mask =
1568 TRI->getCallPreservedMask(MF: DAG.getMachineFunction(), CallConv);
1569 assert(Mask && "Missing call preserved mask for calling convention");
1570 Ops.push_back(Elt: DAG.getRegisterMask(RegMask: Mask));
1571
1572 if (InGlue.getNode()) {
1573 Ops.push_back(Elt: InGlue);
1574 }
1575
1576 Chain = DAG.getNode(Opcode: AVRISD::CALL, DL, VTList: NodeTys, Ops);
1577 InGlue = Chain.getValue(R: 1);
1578
1579 // Create the CALLSEQ_END node.
1580 Chain = DAG.getCALLSEQ_END(Chain, Size1: NumBytes, Size2: 0, Glue: InGlue, DL);
1581
1582 if (!Ins.empty()) {
1583 InGlue = Chain.getValue(R: 1);
1584 }
1585
1586 // Handle result values, copying them out of physregs into vregs that we
1587 // return.
1588 return LowerCallResult(Chain, InGlue, CallConv, isVarArg, Ins, dl: DL, DAG,
1589 InVals);
1590}
1591
1592/// Lower the result values of a call into the
1593/// appropriate copies out of appropriate physical registers.
1594///
1595SDValue AVRTargetLowering::LowerCallResult(
1596 SDValue Chain, SDValue InGlue, CallingConv::ID CallConv, bool isVarArg,
1597 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1598 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1599
1600 // Assign locations to each value returned by this call.
1601 SmallVector<CCValAssign, 16> RVLocs;
1602 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1603 *DAG.getContext());
1604
1605 // Handle runtime calling convs.
1606 if (CallConv == CallingConv::AVR_BUILTIN) {
1607 CCInfo.AnalyzeCallResult(Ins, Fn: RetCC_AVR_BUILTIN);
1608 } else {
1609 analyzeReturnValues(Args: Ins, CCInfo, Tiny: Subtarget.hasTinyEncoding());
1610 }
1611
1612 // Copy all of the result registers out of their specified physreg.
1613 for (CCValAssign const &RVLoc : RVLocs) {
1614 Chain = DAG.getCopyFromReg(Chain, dl, Reg: RVLoc.getLocReg(), VT: RVLoc.getValVT(),
1615 Glue: InGlue)
1616 .getValue(R: 1);
1617 InGlue = Chain.getValue(R: 2);
1618 InVals.push_back(Elt: Chain.getValue(R: 0));
1619 }
1620
1621 return Chain;
1622}
1623
1624//===----------------------------------------------------------------------===//
1625// Return Value Calling Convention Implementation
1626//===----------------------------------------------------------------------===//
1627
1628bool AVRTargetLowering::CanLowerReturn(
1629 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
1630 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
1631 const Type *RetTy) const {
1632 if (CallConv == CallingConv::AVR_BUILTIN) {
1633 SmallVector<CCValAssign, 16> RVLocs;
1634 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1635 return CCInfo.CheckReturn(Outs, Fn: RetCC_AVR_BUILTIN);
1636 }
1637
1638 unsigned TotalBytes = getTotalArgumentsSizeInBytes(Args: Outs);
1639 return TotalBytes <= (unsigned)(Subtarget.hasTinyEncoding() ? 4 : 8);
1640}
1641
1642SDValue
1643AVRTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1644 bool isVarArg,
1645 const SmallVectorImpl<ISD::OutputArg> &Outs,
1646 const SmallVectorImpl<SDValue> &OutVals,
1647 const SDLoc &dl, SelectionDAG &DAG) const {
1648 // CCValAssign - represent the assignment of the return value to locations.
1649 SmallVector<CCValAssign, 16> RVLocs;
1650
1651 // CCState - Info about the registers and stack slot.
1652 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1653 *DAG.getContext());
1654
1655 MachineFunction &MF = DAG.getMachineFunction();
1656
1657 // Analyze return values.
1658 if (CallConv == CallingConv::AVR_BUILTIN) {
1659 CCInfo.AnalyzeReturn(Outs, Fn: RetCC_AVR_BUILTIN);
1660 } else {
1661 analyzeReturnValues(Args: Outs, CCInfo, Tiny: Subtarget.hasTinyEncoding());
1662 }
1663
1664 SDValue Glue;
1665 SmallVector<SDValue, 4> RetOps(1, Chain);
1666 // Copy the result values into the output registers.
1667 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1668 CCValAssign &VA = RVLocs[i];
1669 assert(VA.isRegLoc() && "Can only return in registers!");
1670
1671 Chain = DAG.getCopyToReg(Chain, dl, Reg: VA.getLocReg(), N: OutVals[i], Glue);
1672
1673 // Guarantee that all emitted copies are stuck together with flags.
1674 Glue = Chain.getValue(R: 1);
1675 RetOps.push_back(Elt: DAG.getRegister(Reg: VA.getLocReg(), VT: VA.getLocVT()));
1676 }
1677
1678 // Don't emit the ret/reti instruction when the naked attribute is present in
1679 // the function being compiled.
1680 if (MF.getFunction().getAttributes().hasFnAttr(Kind: Attribute::Naked)) {
1681 return Chain;
1682 }
1683
1684 const AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
1685
1686 if (!AFI->isInterruptOrSignalHandler()) {
1687 // The return instruction has an implicit zero register operand: it must
1688 // contain zero on return.
1689 // This is not needed in interrupts however, where the zero register is
1690 // handled specially (only pushed/popped when needed).
1691 RetOps.push_back(Elt: DAG.getRegister(Reg: Subtarget.getZeroRegister(), VT: MVT::i8));
1692 }
1693
1694 unsigned RetOpc =
1695 AFI->isInterruptOrSignalHandler() ? AVRISD::RETI_GLUE : AVRISD::RET_GLUE;
1696
1697 RetOps[0] = Chain; // Update chain.
1698
1699 if (Glue.getNode()) {
1700 RetOps.push_back(Elt: Glue);
1701 }
1702
1703 return DAG.getNode(Opcode: RetOpc, DL: dl, VT: MVT::Other, Ops: RetOps);
1704}
1705
1706//===----------------------------------------------------------------------===//
1707// Custom Inserters
1708//===----------------------------------------------------------------------===//
1709
1710MachineBasicBlock *AVRTargetLowering::insertShift(MachineInstr &MI,
1711 MachineBasicBlock *BB,
1712 bool Tiny) const {
1713 unsigned Opc;
1714 const TargetRegisterClass *RC;
1715 bool HasRepeatedOperand = false;
1716 MachineFunction *F = BB->getParent();
1717 MachineRegisterInfo &RI = F->getRegInfo();
1718 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1719 DebugLoc dl = MI.getDebugLoc();
1720
1721 switch (MI.getOpcode()) {
1722 default:
1723 llvm_unreachable("Invalid shift opcode!");
1724 case AVR::Lsl8:
1725 Opc = AVR::ADDRdRr; // LSL is an alias of ADD Rd, Rd
1726 RC = &AVR::GPR8RegClass;
1727 HasRepeatedOperand = true;
1728 break;
1729 case AVR::Lsl16:
1730 Opc = AVR::LSLWRd;
1731 RC = &AVR::DREGSRegClass;
1732 break;
1733 case AVR::Asr8:
1734 Opc = AVR::ASRRd;
1735 RC = &AVR::GPR8RegClass;
1736 break;
1737 case AVR::Asr16:
1738 Opc = AVR::ASRWRd;
1739 RC = &AVR::DREGSRegClass;
1740 break;
1741 case AVR::Lsr8:
1742 Opc = AVR::LSRRd;
1743 RC = &AVR::GPR8RegClass;
1744 break;
1745 case AVR::Lsr16:
1746 Opc = AVR::LSRWRd;
1747 RC = &AVR::DREGSRegClass;
1748 break;
1749 case AVR::Rol8:
1750 Opc = Tiny ? AVR::ROLBRdR17 : AVR::ROLBRdR1;
1751 RC = &AVR::GPR8RegClass;
1752 break;
1753 case AVR::Rol16:
1754 Opc = AVR::ROLWRd;
1755 RC = &AVR::DREGSRegClass;
1756 break;
1757 case AVR::Ror8:
1758 Opc = AVR::RORBRd;
1759 RC = &AVR::GPR8RegClass;
1760 break;
1761 case AVR::Ror16:
1762 Opc = AVR::RORWRd;
1763 RC = &AVR::DREGSRegClass;
1764 break;
1765 }
1766
1767 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1768
1769 MachineFunction::iterator I;
1770 for (I = BB->getIterator(); I != F->end() && &(*I) != BB; ++I)
1771 ;
1772 if (I != F->end())
1773 ++I;
1774
1775 // Create loop block.
1776 MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(BB: LLVM_BB);
1777 MachineBasicBlock *CheckBB = F->CreateMachineBasicBlock(BB: LLVM_BB);
1778 MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(BB: LLVM_BB);
1779
1780 F->insert(MBBI: I, MBB: LoopBB);
1781 F->insert(MBBI: I, MBB: CheckBB);
1782 F->insert(MBBI: I, MBB: RemBB);
1783
1784 // Update machine-CFG edges by transferring all successors of the current
1785 // block to the block containing instructions after shift.
1786 RemBB->splice(Where: RemBB->begin(), Other: BB, From: std::next(x: MachineBasicBlock::iterator(MI)),
1787 To: BB->end());
1788 RemBB->transferSuccessorsAndUpdatePHIs(FromMBB: BB);
1789
1790 // Add edges BB => LoopBB => CheckBB => RemBB, CheckBB => LoopBB.
1791 BB->addSuccessor(Succ: CheckBB);
1792 LoopBB->addSuccessor(Succ: CheckBB);
1793 CheckBB->addSuccessor(Succ: LoopBB);
1794 CheckBB->addSuccessor(Succ: RemBB);
1795
1796 Register ShiftAmtReg = RI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
1797 Register ShiftAmtReg2 = RI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
1798 Register ShiftReg = RI.createVirtualRegister(RegClass: RC);
1799 Register ShiftReg2 = RI.createVirtualRegister(RegClass: RC);
1800 Register ShiftAmtSrcReg = MI.getOperand(i: 2).getReg();
1801 Register SrcReg = MI.getOperand(i: 1).getReg();
1802 Register DstReg = MI.getOperand(i: 0).getReg();
1803
1804 // BB:
1805 // rjmp CheckBB
1806 BuildMI(BB, MIMD: dl, MCID: TII.get(Opcode: AVR::RJMPk)).addMBB(MBB: CheckBB);
1807
1808 // LoopBB:
1809 // ShiftReg2 = shift ShiftReg
1810 auto ShiftMI = BuildMI(BB: LoopBB, MIMD: dl, MCID: TII.get(Opcode: Opc), DestReg: ShiftReg2).addReg(RegNo: ShiftReg);
1811 if (HasRepeatedOperand)
1812 ShiftMI.addReg(RegNo: ShiftReg);
1813
1814 // CheckBB:
1815 // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1816 // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1817 // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1818 // ShiftAmt2 = ShiftAmt - 1;
1819 // if (ShiftAmt2 >= 0) goto LoopBB;
1820 BuildMI(BB: CheckBB, MIMD: dl, MCID: TII.get(Opcode: AVR::PHI), DestReg: ShiftReg)
1821 .addReg(RegNo: SrcReg)
1822 .addMBB(MBB: BB)
1823 .addReg(RegNo: ShiftReg2)
1824 .addMBB(MBB: LoopBB);
1825 BuildMI(BB: CheckBB, MIMD: dl, MCID: TII.get(Opcode: AVR::PHI), DestReg: ShiftAmtReg)
1826 .addReg(RegNo: ShiftAmtSrcReg)
1827 .addMBB(MBB: BB)
1828 .addReg(RegNo: ShiftAmtReg2)
1829 .addMBB(MBB: LoopBB);
1830 BuildMI(BB: CheckBB, MIMD: dl, MCID: TII.get(Opcode: AVR::PHI), DestReg: DstReg)
1831 .addReg(RegNo: SrcReg)
1832 .addMBB(MBB: BB)
1833 .addReg(RegNo: ShiftReg2)
1834 .addMBB(MBB: LoopBB);
1835
1836 BuildMI(BB: CheckBB, MIMD: dl, MCID: TII.get(Opcode: AVR::DECRd), DestReg: ShiftAmtReg2).addReg(RegNo: ShiftAmtReg);
1837 BuildMI(BB: CheckBB, MIMD: dl, MCID: TII.get(Opcode: AVR::BRPLk)).addMBB(MBB: LoopBB);
1838
1839 MI.eraseFromParent(); // The pseudo instruction is gone now.
1840 return RemBB;
1841}
1842
1843// Do a multibyte AVR shift. Insert shift instructions and put the output
1844// registers in the Regs array.
1845// Because AVR does not have a normal shift instruction (only a single bit shift
1846// instruction), we have to emulate this behavior with other instructions.
1847// It first tries large steps (moving registers around) and then smaller steps
1848// like single bit shifts.
1849// Large shifts actually reduce the number of shifted registers, so the below
1850// algorithms have to work independently of the number of registers that are
1851// shifted.
1852// For more information and background, see this blogpost:
1853// https://aykevl.nl/2021/02/avr-bitshift
1854static void insertMultibyteShift(MachineInstr &MI, MachineBasicBlock *BB,
1855 MutableArrayRef<std::pair<Register, int>> Regs,
1856 ISD::NodeType Opc, int64_t ShiftAmt) {
1857 const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
1858 const AVRSubtarget &STI = BB->getParent()->getSubtarget<AVRSubtarget>();
1859 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
1860 const DebugLoc &dl = MI.getDebugLoc();
1861
1862 const bool ShiftLeft = Opc == ISD::SHL;
1863 const bool ArithmeticShift = Opc == ISD::SRA;
1864
1865 // Zero a register, for use in later operations.
1866 Register ZeroReg = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
1867 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::COPY), DestReg: ZeroReg)
1868 .addReg(RegNo: STI.getZeroRegister());
1869
1870 // Do a shift modulo 6 or 7. This is a bit more complicated than most shifts
1871 // and is hard to compose with the rest, so these are special cased.
1872 // The basic idea is to shift one or two bits in the opposite direction and
1873 // then move registers around to get the correct end result.
1874 if (ShiftLeft && (ShiftAmt % 8) >= 6) {
1875 // Left shift modulo 6 or 7.
1876
1877 // Create a slice of the registers we're going to modify, to ease working
1878 // with them.
1879 size_t ShiftRegsOffset = ShiftAmt / 8;
1880 size_t ShiftRegsSize = Regs.size() - ShiftRegsOffset;
1881 MutableArrayRef<std::pair<Register, int>> ShiftRegs =
1882 Regs.slice(N: ShiftRegsOffset, M: ShiftRegsSize);
1883
1884 // Shift one to the right, keeping the least significant bit as the carry
1885 // bit.
1886 insertMultibyteShift(MI, BB, Regs: ShiftRegs, Opc: ISD::SRL, ShiftAmt: 1);
1887
1888 // Rotate the least significant bit from the carry bit into a new register
1889 // (that starts out zero).
1890 Register LowByte = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
1891 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::RORRd), DestReg: LowByte).addReg(RegNo: ZeroReg);
1892
1893 // Shift one more to the right if this is a modulo-6 shift.
1894 if (ShiftAmt % 8 == 6) {
1895 insertMultibyteShift(MI, BB, Regs: ShiftRegs, Opc: ISD::SRL, ShiftAmt: 1);
1896 Register NewLowByte = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
1897 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::RORRd), DestReg: NewLowByte).addReg(RegNo: LowByte);
1898 LowByte = NewLowByte;
1899 }
1900
1901 // Move all registers to the left, zeroing the bottom registers as needed.
1902 for (size_t I = 0; I < Regs.size(); I++) {
1903 int ShiftRegsIdx = I + 1;
1904 if (ShiftRegsIdx < (int)ShiftRegs.size()) {
1905 Regs[I] = ShiftRegs[ShiftRegsIdx];
1906 } else if (ShiftRegsIdx == (int)ShiftRegs.size()) {
1907 Regs[I] = std::pair(LowByte, 0);
1908 } else {
1909 Regs[I] = std::pair(ZeroReg, 0);
1910 }
1911 }
1912
1913 return;
1914 }
1915
1916 // Right shift modulo 6 or 7.
1917 if (!ShiftLeft && (ShiftAmt % 8) >= 6) {
1918 // Create a view on the registers we're going to modify, to ease working
1919 // with them.
1920 size_t ShiftRegsSize = Regs.size() - (ShiftAmt / 8);
1921 MutableArrayRef<std::pair<Register, int>> ShiftRegs =
1922 Regs.slice(N: 0, M: ShiftRegsSize);
1923
1924 // Shift one to the left.
1925 insertMultibyteShift(MI, BB, Regs: ShiftRegs, Opc: ISD::SHL, ShiftAmt: 1);
1926
1927 // Sign or zero extend the most significant register into a new register.
1928 // The HighByte is the byte that still has one (or two) bits from the
1929 // original value. The ExtByte is purely a zero/sign extend byte (all bits
1930 // are either 0 or 1).
1931 Register HighByte = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
1932 Register ExtByte = 0;
1933 if (ArithmeticShift) {
1934 // Sign-extend bit that was shifted out last.
1935 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::SBCRdRr), DestReg: HighByte)
1936 .addReg(RegNo: HighByte, flags: RegState::Undef)
1937 .addReg(RegNo: HighByte, flags: RegState::Undef);
1938 ExtByte = HighByte;
1939 // The highest bit of the original value is the same as the zero-extend
1940 // byte, so HighByte and ExtByte are the same.
1941 } else {
1942 // Use the zero register for zero extending.
1943 ExtByte = ZeroReg;
1944 // Rotate most significant bit into a new register (that starts out zero).
1945 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::ADCRdRr), DestReg: HighByte)
1946 .addReg(RegNo: ExtByte)
1947 .addReg(RegNo: ExtByte);
1948 }
1949
1950 // Shift one more to the left for modulo 6 shifts.
1951 if (ShiftAmt % 8 == 6) {
1952 insertMultibyteShift(MI, BB, Regs: ShiftRegs, Opc: ISD::SHL, ShiftAmt: 1);
1953 // Shift the topmost bit into the HighByte.
1954 Register NewExt = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
1955 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::ADCRdRr), DestReg: NewExt)
1956 .addReg(RegNo: HighByte)
1957 .addReg(RegNo: HighByte);
1958 HighByte = NewExt;
1959 }
1960
1961 // Move all to the right, while sign or zero extending.
1962 for (int I = Regs.size() - 1; I >= 0; I--) {
1963 int ShiftRegsIdx = I - (Regs.size() - ShiftRegs.size()) - 1;
1964 if (ShiftRegsIdx >= 0) {
1965 Regs[I] = ShiftRegs[ShiftRegsIdx];
1966 } else if (ShiftRegsIdx == -1) {
1967 Regs[I] = std::pair(HighByte, 0);
1968 } else {
1969 Regs[I] = std::pair(ExtByte, 0);
1970 }
1971 }
1972
1973 return;
1974 }
1975
1976 // For shift amounts of at least one register, simply rename the registers and
1977 // zero the bottom registers.
1978 while (ShiftLeft && ShiftAmt >= 8) {
1979 // Move all registers one to the left.
1980 for (size_t I = 0; I < Regs.size() - 1; I++) {
1981 Regs[I] = Regs[I + 1];
1982 }
1983
1984 // Zero the least significant register.
1985 Regs[Regs.size() - 1] = std::pair(ZeroReg, 0);
1986
1987 // Continue shifts with the leftover registers.
1988 Regs = Regs.drop_back(N: 1);
1989
1990 ShiftAmt -= 8;
1991 }
1992
1993 // And again, the same for right shifts.
1994 Register ShrExtendReg = 0;
1995 if (!ShiftLeft && ShiftAmt >= 8) {
1996 if (ArithmeticShift) {
1997 // Sign extend the most significant register into ShrExtendReg.
1998 ShrExtendReg = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
1999 Register Tmp = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
2000 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::ADDRdRr), DestReg: Tmp)
2001 .addReg(RegNo: Regs[0].first, flags: 0, SubReg: Regs[0].second)
2002 .addReg(RegNo: Regs[0].first, flags: 0, SubReg: Regs[0].second);
2003 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::SBCRdRr), DestReg: ShrExtendReg)
2004 .addReg(RegNo: Tmp)
2005 .addReg(RegNo: Tmp);
2006 } else {
2007 ShrExtendReg = ZeroReg;
2008 }
2009 for (; ShiftAmt >= 8; ShiftAmt -= 8) {
2010 // Move all registers one to the right.
2011 for (size_t I = Regs.size() - 1; I != 0; I--) {
2012 Regs[I] = Regs[I - 1];
2013 }
2014
2015 // Zero or sign extend the most significant register.
2016 Regs[0] = std::pair(ShrExtendReg, 0);
2017
2018 // Continue shifts with the leftover registers.
2019 Regs = Regs.drop_front(N: 1);
2020 }
2021 }
2022
2023 // The bigger shifts are already handled above.
2024 assert((ShiftAmt < 8) && "Unexpect shift amount");
2025
2026 // Shift by four bits, using a complicated swap/eor/andi/eor sequence.
2027 // It only works for logical shifts because the bits shifted in are all
2028 // zeroes.
2029 // To shift a single byte right, it produces code like this:
2030 // swap r0
2031 // andi r0, 0x0f
2032 // For a two-byte (16-bit) shift, it adds the following instructions to shift
2033 // the upper byte into the lower byte:
2034 // swap r1
2035 // eor r0, r1
2036 // andi r1, 0x0f
2037 // eor r0, r1
2038 // For bigger shifts, it repeats the above sequence. For example, for a 3-byte
2039 // (24-bit) shift it adds:
2040 // swap r2
2041 // eor r1, r2
2042 // andi r2, 0x0f
2043 // eor r1, r2
2044 if (!ArithmeticShift && ShiftAmt >= 4) {
2045 Register Prev = 0;
2046 for (size_t I = 0; I < Regs.size(); I++) {
2047 size_t Idx = ShiftLeft ? I : Regs.size() - I - 1;
2048 Register SwapReg = MRI.createVirtualRegister(RegClass: &AVR::LD8RegClass);
2049 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::SWAPRd), DestReg: SwapReg)
2050 .addReg(RegNo: Regs[Idx].first, flags: 0, SubReg: Regs[Idx].second);
2051 if (I != 0) {
2052 Register R = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
2053 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::EORRdRr), DestReg: R)
2054 .addReg(RegNo: Prev)
2055 .addReg(RegNo: SwapReg);
2056 Prev = R;
2057 }
2058 Register AndReg = MRI.createVirtualRegister(RegClass: &AVR::LD8RegClass);
2059 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::ANDIRdK), DestReg: AndReg)
2060 .addReg(RegNo: SwapReg)
2061 .addImm(Val: ShiftLeft ? 0xf0 : 0x0f);
2062 if (I != 0) {
2063 Register R = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
2064 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::EORRdRr), DestReg: R)
2065 .addReg(RegNo: Prev)
2066 .addReg(RegNo: AndReg);
2067 size_t PrevIdx = ShiftLeft ? Idx - 1 : Idx + 1;
2068 Regs[PrevIdx] = std::pair(R, 0);
2069 }
2070 Prev = AndReg;
2071 Regs[Idx] = std::pair(AndReg, 0);
2072 }
2073 ShiftAmt -= 4;
2074 }
2075
2076 // Shift by one. This is the fallback that always works, and the shift
2077 // operation that is used for 1, 2, and 3 bit shifts.
2078 while (ShiftLeft && ShiftAmt) {
2079 // Shift one to the left.
2080 for (ssize_t I = Regs.size() - 1; I >= 0; I--) {
2081 Register Out = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
2082 Register In = Regs[I].first;
2083 Register InSubreg = Regs[I].second;
2084 if (I == (ssize_t)Regs.size() - 1) { // first iteration
2085 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::ADDRdRr), DestReg: Out)
2086 .addReg(RegNo: In, flags: 0, SubReg: InSubreg)
2087 .addReg(RegNo: In, flags: 0, SubReg: InSubreg);
2088 } else {
2089 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::ADCRdRr), DestReg: Out)
2090 .addReg(RegNo: In, flags: 0, SubReg: InSubreg)
2091 .addReg(RegNo: In, flags: 0, SubReg: InSubreg);
2092 }
2093 Regs[I] = std::pair(Out, 0);
2094 }
2095 ShiftAmt--;
2096 }
2097 while (!ShiftLeft && ShiftAmt) {
2098 // Shift one to the right.
2099 for (size_t I = 0; I < Regs.size(); I++) {
2100 Register Out = MRI.createVirtualRegister(RegClass: &AVR::GPR8RegClass);
2101 Register In = Regs[I].first;
2102 Register InSubreg = Regs[I].second;
2103 if (I == 0) {
2104 unsigned Opc = ArithmeticShift ? AVR::ASRRd : AVR::LSRRd;
2105 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: Opc), DestReg: Out).addReg(RegNo: In, flags: 0, SubReg: InSubreg);
2106 } else {
2107 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::RORRd), DestReg: Out).addReg(RegNo: In, flags: 0, SubReg: InSubreg);
2108 }
2109 Regs[I] = std::pair(Out, 0);
2110 }
2111 ShiftAmt--;
2112 }
2113
2114 if (ShiftAmt != 0) {
2115 llvm_unreachable("don't know how to shift!"); // sanity check
2116 }
2117}
2118
2119// Do a wide (32-bit) shift.
2120MachineBasicBlock *
2121AVRTargetLowering::insertWideShift(MachineInstr &MI,
2122 MachineBasicBlock *BB) const {
2123 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
2124 const DebugLoc &dl = MI.getDebugLoc();
2125
2126 // How much to shift to the right (meaning: a negative number indicates a left
2127 // shift).
2128 int64_t ShiftAmt = MI.getOperand(i: 4).getImm();
2129 ISD::NodeType Opc;
2130 switch (MI.getOpcode()) {
2131 case AVR::Lsl32:
2132 Opc = ISD::SHL;
2133 break;
2134 case AVR::Lsr32:
2135 Opc = ISD::SRL;
2136 break;
2137 case AVR::Asr32:
2138 Opc = ISD::SRA;
2139 break;
2140 }
2141
2142 // Read the input registers, with the most significant register at index 0.
2143 std::array<std::pair<Register, int>, 4> Registers = {
2144 std::pair(MI.getOperand(i: 3).getReg(), AVR::sub_hi),
2145 std::pair(MI.getOperand(i: 3).getReg(), AVR::sub_lo),
2146 std::pair(MI.getOperand(i: 2).getReg(), AVR::sub_hi),
2147 std::pair(MI.getOperand(i: 2).getReg(), AVR::sub_lo),
2148 };
2149
2150 // Do the shift. The registers are modified in-place.
2151 insertMultibyteShift(MI, BB, Regs: Registers, Opc, ShiftAmt);
2152
2153 // Combine the 8-bit registers into 16-bit register pairs.
2154 // This done either from LSB to MSB or from MSB to LSB, depending on the
2155 // shift. It's an optimization so that the register allocator will use the
2156 // fewest movs possible (which order we use isn't a correctness issue, just an
2157 // optimization issue).
2158 // - lsl prefers starting from the most significant byte (2nd case).
2159 // - lshr prefers starting from the least significant byte (1st case).
2160 // - for ashr it depends on the number of shifted bytes.
2161 // Some shift operations still don't get the most optimal mov sequences even
2162 // with this distinction. TODO: figure out why and try to fix it (but we're
2163 // already equal to or faster than avr-gcc in all cases except ashr 8).
2164 if (Opc != ISD::SHL &&
2165 (Opc != ISD::SRA || (ShiftAmt < 16 || ShiftAmt >= 22))) {
2166 // Use the resulting registers starting with the least significant byte.
2167 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::REG_SEQUENCE), DestReg: MI.getOperand(i: 0).getReg())
2168 .addReg(RegNo: Registers[3].first, flags: 0, SubReg: Registers[3].second)
2169 .addImm(Val: AVR::sub_lo)
2170 .addReg(RegNo: Registers[2].first, flags: 0, SubReg: Registers[2].second)
2171 .addImm(Val: AVR::sub_hi);
2172 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::REG_SEQUENCE), DestReg: MI.getOperand(i: 1).getReg())
2173 .addReg(RegNo: Registers[1].first, flags: 0, SubReg: Registers[1].second)
2174 .addImm(Val: AVR::sub_lo)
2175 .addReg(RegNo: Registers[0].first, flags: 0, SubReg: Registers[0].second)
2176 .addImm(Val: AVR::sub_hi);
2177 } else {
2178 // Use the resulting registers starting with the most significant byte.
2179 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::REG_SEQUENCE), DestReg: MI.getOperand(i: 1).getReg())
2180 .addReg(RegNo: Registers[0].first, flags: 0, SubReg: Registers[0].second)
2181 .addImm(Val: AVR::sub_hi)
2182 .addReg(RegNo: Registers[1].first, flags: 0, SubReg: Registers[1].second)
2183 .addImm(Val: AVR::sub_lo);
2184 BuildMI(BB&: *BB, I&: MI, MIMD: dl, MCID: TII.get(Opcode: AVR::REG_SEQUENCE), DestReg: MI.getOperand(i: 0).getReg())
2185 .addReg(RegNo: Registers[2].first, flags: 0, SubReg: Registers[2].second)
2186 .addImm(Val: AVR::sub_hi)
2187 .addReg(RegNo: Registers[3].first, flags: 0, SubReg: Registers[3].second)
2188 .addImm(Val: AVR::sub_lo);
2189 }
2190
2191 // Remove the pseudo instruction.
2192 MI.eraseFromParent();
2193 return BB;
2194}
2195
2196static bool isCopyMulResult(MachineBasicBlock::iterator const &I) {
2197 if (I->getOpcode() == AVR::COPY) {
2198 Register SrcReg = I->getOperand(i: 1).getReg();
2199 return (SrcReg == AVR::R0 || SrcReg == AVR::R1);
2200 }
2201
2202 return false;
2203}
2204
2205// The mul instructions wreak havock on our zero_reg R1. We need to clear it
2206// after the result has been evacuated. This is probably not the best way to do
2207// it, but it works for now.
2208MachineBasicBlock *AVRTargetLowering::insertMul(MachineInstr &MI,
2209 MachineBasicBlock *BB) const {
2210 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
2211 MachineBasicBlock::iterator I(MI);
2212 ++I; // in any case insert *after* the mul instruction
2213 if (isCopyMulResult(I))
2214 ++I;
2215 if (isCopyMulResult(I))
2216 ++I;
2217 BuildMI(BB&: *BB, I, MIMD: MI.getDebugLoc(), MCID: TII.get(Opcode: AVR::EORRdRr), DestReg: AVR::R1)
2218 .addReg(RegNo: AVR::R1)
2219 .addReg(RegNo: AVR::R1);
2220 return BB;
2221}
2222
2223// Insert a read from the zero register.
2224MachineBasicBlock *
2225AVRTargetLowering::insertCopyZero(MachineInstr &MI,
2226 MachineBasicBlock *BB) const {
2227 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
2228 MachineBasicBlock::iterator I(MI);
2229 BuildMI(BB&: *BB, I, MIMD: MI.getDebugLoc(), MCID: TII.get(Opcode: AVR::COPY))
2230 .add(MO: MI.getOperand(i: 0))
2231 .addReg(RegNo: Subtarget.getZeroRegister());
2232 MI.eraseFromParent();
2233 return BB;
2234}
2235
2236// Lower atomicrmw operation to disable interrupts, do operation, and restore
2237// interrupts. This works because all AVR microcontrollers are single core.
2238MachineBasicBlock *AVRTargetLowering::insertAtomicArithmeticOp(
2239 MachineInstr &MI, MachineBasicBlock *BB, unsigned Opcode, int Width) const {
2240 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
2241 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
2242 MachineBasicBlock::iterator I(MI);
2243 DebugLoc dl = MI.getDebugLoc();
2244
2245 // Example instruction sequence, for an atomic 8-bit add:
2246 // ldi r25, 5
2247 // in r0, SREG
2248 // cli
2249 // ld r24, X
2250 // add r25, r24
2251 // st X, r25
2252 // out SREG, r0
2253
2254 const TargetRegisterClass *RC =
2255 (Width == 8) ? &AVR::GPR8RegClass : &AVR::DREGSRegClass;
2256 unsigned LoadOpcode = (Width == 8) ? AVR::LDRdPtr : AVR::LDWRdPtr;
2257 unsigned StoreOpcode = (Width == 8) ? AVR::STPtrRr : AVR::STWPtrRr;
2258
2259 // Disable interrupts.
2260 BuildMI(BB&: *BB, I, MIMD: dl, MCID: TII.get(Opcode: AVR::INRdA), DestReg: Subtarget.getTmpRegister())
2261 .addImm(Val: Subtarget.getIORegSREG());
2262 BuildMI(BB&: *BB, I, MIMD: dl, MCID: TII.get(Opcode: AVR::BCLRs)).addImm(Val: 7);
2263
2264 // Load the original value.
2265 BuildMI(BB&: *BB, I, MIMD: dl, MCID: TII.get(Opcode: LoadOpcode), DestReg: MI.getOperand(i: 0).getReg())
2266 .add(MO: MI.getOperand(i: 1));
2267
2268 // Do the arithmetic operation.
2269 Register Result = MRI.createVirtualRegister(RegClass: RC);
2270 BuildMI(BB&: *BB, I, MIMD: dl, MCID: TII.get(Opcode), DestReg: Result)
2271 .addReg(RegNo: MI.getOperand(i: 0).getReg())
2272 .add(MO: MI.getOperand(i: 2));
2273
2274 // Store the result.
2275 BuildMI(BB&: *BB, I, MIMD: dl, MCID: TII.get(Opcode: StoreOpcode))
2276 .add(MO: MI.getOperand(i: 1))
2277 .addReg(RegNo: Result);
2278
2279 // Restore interrupts.
2280 BuildMI(BB&: *BB, I, MIMD: dl, MCID: TII.get(Opcode: AVR::OUTARr))
2281 .addImm(Val: Subtarget.getIORegSREG())
2282 .addReg(RegNo: Subtarget.getTmpRegister());
2283
2284 // Remove the pseudo instruction.
2285 MI.eraseFromParent();
2286 return BB;
2287}
2288
2289MachineBasicBlock *
2290AVRTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
2291 MachineBasicBlock *MBB) const {
2292 int Opc = MI.getOpcode();
2293 const AVRSubtarget &STI = MBB->getParent()->getSubtarget<AVRSubtarget>();
2294
2295 // Pseudo shift instructions with a non constant shift amount are expanded
2296 // into a loop.
2297 switch (Opc) {
2298 case AVR::Lsl8:
2299 case AVR::Lsl16:
2300 case AVR::Lsr8:
2301 case AVR::Lsr16:
2302 case AVR::Rol8:
2303 case AVR::Rol16:
2304 case AVR::Ror8:
2305 case AVR::Ror16:
2306 case AVR::Asr8:
2307 case AVR::Asr16:
2308 return insertShift(MI, BB: MBB, Tiny: STI.hasTinyEncoding());
2309 case AVR::Lsl32:
2310 case AVR::Lsr32:
2311 case AVR::Asr32:
2312 return insertWideShift(MI, BB: MBB);
2313 case AVR::MULRdRr:
2314 case AVR::MULSRdRr:
2315 return insertMul(MI, BB: MBB);
2316 case AVR::CopyZero:
2317 return insertCopyZero(MI, BB: MBB);
2318 case AVR::AtomicLoadAdd8:
2319 return insertAtomicArithmeticOp(MI, BB: MBB, Opcode: AVR::ADDRdRr, Width: 8);
2320 case AVR::AtomicLoadAdd16:
2321 return insertAtomicArithmeticOp(MI, BB: MBB, Opcode: AVR::ADDWRdRr, Width: 16);
2322 case AVR::AtomicLoadSub8:
2323 return insertAtomicArithmeticOp(MI, BB: MBB, Opcode: AVR::SUBRdRr, Width: 8);
2324 case AVR::AtomicLoadSub16:
2325 return insertAtomicArithmeticOp(MI, BB: MBB, Opcode: AVR::SUBWRdRr, Width: 16);
2326 case AVR::AtomicLoadAnd8:
2327 return insertAtomicArithmeticOp(MI, BB: MBB, Opcode: AVR::ANDRdRr, Width: 8);
2328 case AVR::AtomicLoadAnd16:
2329 return insertAtomicArithmeticOp(MI, BB: MBB, Opcode: AVR::ANDWRdRr, Width: 16);
2330 case AVR::AtomicLoadOr8:
2331 return insertAtomicArithmeticOp(MI, BB: MBB, Opcode: AVR::ORRdRr, Width: 8);
2332 case AVR::AtomicLoadOr16:
2333 return insertAtomicArithmeticOp(MI, BB: MBB, Opcode: AVR::ORWRdRr, Width: 16);
2334 case AVR::AtomicLoadXor8:
2335 return insertAtomicArithmeticOp(MI, BB: MBB, Opcode: AVR::EORRdRr, Width: 8);
2336 case AVR::AtomicLoadXor16:
2337 return insertAtomicArithmeticOp(MI, BB: MBB, Opcode: AVR::EORWRdRr, Width: 16);
2338 }
2339
2340 assert((Opc == AVR::Select16 || Opc == AVR::Select8) &&
2341 "Unexpected instr type to insert");
2342
2343 const AVRInstrInfo &TII = (const AVRInstrInfo &)*MI.getParent()
2344 ->getParent()
2345 ->getSubtarget()
2346 .getInstrInfo();
2347 DebugLoc dl = MI.getDebugLoc();
2348
2349 // To "insert" a SELECT instruction, we insert the diamond
2350 // control-flow pattern. The incoming instruction knows the
2351 // destination vreg to set, the condition code register to branch
2352 // on, the true/false values to select between, and a branch opcode
2353 // to use.
2354
2355 MachineFunction *MF = MBB->getParent();
2356 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
2357 MachineBasicBlock *FallThrough = MBB->getFallThrough();
2358
2359 // If the current basic block falls through to another basic block,
2360 // we must insert an unconditional branch to the fallthrough destination
2361 // if we are to insert basic blocks at the prior fallthrough point.
2362 if (FallThrough != nullptr) {
2363 BuildMI(BB: MBB, MIMD: dl, MCID: TII.get(Opcode: AVR::RJMPk)).addMBB(MBB: FallThrough);
2364 }
2365
2366 MachineBasicBlock *trueMBB = MF->CreateMachineBasicBlock(BB: LLVM_BB);
2367 MachineBasicBlock *falseMBB = MF->CreateMachineBasicBlock(BB: LLVM_BB);
2368
2369 MachineFunction::iterator I;
2370 for (I = MF->begin(); I != MF->end() && &(*I) != MBB; ++I)
2371 ;
2372 if (I != MF->end())
2373 ++I;
2374 MF->insert(MBBI: I, MBB: trueMBB);
2375 MF->insert(MBBI: I, MBB: falseMBB);
2376
2377 // Set the call frame size on entry to the new basic blocks.
2378 unsigned CallFrameSize = TII.getCallFrameSizeAt(MI);
2379 trueMBB->setCallFrameSize(CallFrameSize);
2380 falseMBB->setCallFrameSize(CallFrameSize);
2381
2382 // Transfer remaining instructions and all successors of the current
2383 // block to the block which will contain the Phi node for the
2384 // select.
2385 trueMBB->splice(Where: trueMBB->begin(), Other: MBB,
2386 From: std::next(x: MachineBasicBlock::iterator(MI)), To: MBB->end());
2387 trueMBB->transferSuccessorsAndUpdatePHIs(FromMBB: MBB);
2388
2389 AVRCC::CondCodes CC = (AVRCC::CondCodes)MI.getOperand(i: 3).getImm();
2390 BuildMI(BB: MBB, MIMD: dl, MCID: TII.getBrCond(CC)).addMBB(MBB: trueMBB);
2391 BuildMI(BB: MBB, MIMD: dl, MCID: TII.get(Opcode: AVR::RJMPk)).addMBB(MBB: falseMBB);
2392 MBB->addSuccessor(Succ: falseMBB);
2393 MBB->addSuccessor(Succ: trueMBB);
2394
2395 // Unconditionally flow back to the true block
2396 BuildMI(BB: falseMBB, MIMD: dl, MCID: TII.get(Opcode: AVR::RJMPk)).addMBB(MBB: trueMBB);
2397 falseMBB->addSuccessor(Succ: trueMBB);
2398
2399 // Set up the Phi node to determine where we came from
2400 BuildMI(BB&: *trueMBB, I: trueMBB->begin(), MIMD: dl, MCID: TII.get(Opcode: AVR::PHI),
2401 DestReg: MI.getOperand(i: 0).getReg())
2402 .addReg(RegNo: MI.getOperand(i: 1).getReg())
2403 .addMBB(MBB)
2404 .addReg(RegNo: MI.getOperand(i: 2).getReg())
2405 .addMBB(MBB: falseMBB);
2406
2407 MI.eraseFromParent(); // The pseudo instruction is gone now.
2408 return trueMBB;
2409}
2410
2411//===----------------------------------------------------------------------===//
2412// Inline Asm Support
2413//===----------------------------------------------------------------------===//
2414
2415AVRTargetLowering::ConstraintType
2416AVRTargetLowering::getConstraintType(StringRef Constraint) const {
2417 if (Constraint.size() == 1) {
2418 // See http://www.nongnu.org/avr-libc/user-manual/inline_asm.html
2419 switch (Constraint[0]) {
2420 default:
2421 break;
2422 case 'a': // Simple upper registers
2423 case 'b': // Base pointer registers pairs
2424 case 'd': // Upper register
2425 case 'l': // Lower registers
2426 case 'e': // Pointer register pairs
2427 case 'q': // Stack pointer register
2428 case 'r': // Any register
2429 case 'w': // Special upper register pairs
2430 return C_RegisterClass;
2431 case 't': // Temporary register
2432 case 'x':
2433 case 'X': // Pointer register pair X
2434 case 'y':
2435 case 'Y': // Pointer register pair Y
2436 case 'z':
2437 case 'Z': // Pointer register pair Z
2438 return C_Register;
2439 case 'Q': // A memory address based on Y or Z pointer with displacement.
2440 return C_Memory;
2441 case 'G': // Floating point constant
2442 case 'I': // 6-bit positive integer constant
2443 case 'J': // 6-bit negative integer constant
2444 case 'K': // Integer constant (Range: 2)
2445 case 'L': // Integer constant (Range: 0)
2446 case 'M': // 8-bit integer constant
2447 case 'N': // Integer constant (Range: -1)
2448 case 'O': // Integer constant (Range: 8, 16, 24)
2449 case 'P': // Integer constant (Range: 1)
2450 case 'R': // Integer constant (Range: -6 to 5)x
2451 return C_Immediate;
2452 }
2453 }
2454
2455 return TargetLowering::getConstraintType(Constraint);
2456}
2457
2458InlineAsm::ConstraintCode
2459AVRTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {
2460 // Not sure if this is actually the right thing to do, but we got to do
2461 // *something* [agnat]
2462 switch (ConstraintCode[0]) {
2463 case 'Q':
2464 return InlineAsm::ConstraintCode::Q;
2465 }
2466 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
2467}
2468
2469AVRTargetLowering::ConstraintWeight
2470AVRTargetLowering::getSingleConstraintMatchWeight(
2471 AsmOperandInfo &info, const char *constraint) const {
2472 ConstraintWeight weight = CW_Invalid;
2473 Value *CallOperandVal = info.CallOperandVal;
2474
2475 // If we don't have a value, we can't do a match,
2476 // but allow it at the lowest weight.
2477 // (this behaviour has been copied from the ARM backend)
2478 if (!CallOperandVal) {
2479 return CW_Default;
2480 }
2481
2482 // Look at the constraint type.
2483 switch (*constraint) {
2484 default:
2485 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
2486 break;
2487 case 'd':
2488 case 'r':
2489 case 'l':
2490 weight = CW_Register;
2491 break;
2492 case 'a':
2493 case 'b':
2494 case 'e':
2495 case 'q':
2496 case 't':
2497 case 'w':
2498 case 'x':
2499 case 'X':
2500 case 'y':
2501 case 'Y':
2502 case 'z':
2503 case 'Z':
2504 weight = CW_SpecificReg;
2505 break;
2506 case 'G':
2507 if (const ConstantFP *C = dyn_cast<ConstantFP>(Val: CallOperandVal)) {
2508 if (C->isZero()) {
2509 weight = CW_Constant;
2510 }
2511 }
2512 break;
2513 case 'I':
2514 if (const ConstantInt *C = dyn_cast<ConstantInt>(Val: CallOperandVal)) {
2515 if (isUInt<6>(x: C->getZExtValue())) {
2516 weight = CW_Constant;
2517 }
2518 }
2519 break;
2520 case 'J':
2521 if (const ConstantInt *C = dyn_cast<ConstantInt>(Val: CallOperandVal)) {
2522 if ((C->getSExtValue() >= -63) && (C->getSExtValue() <= 0)) {
2523 weight = CW_Constant;
2524 }
2525 }
2526 break;
2527 case 'K':
2528 if (const ConstantInt *C = dyn_cast<ConstantInt>(Val: CallOperandVal)) {
2529 if (C->getZExtValue() == 2) {
2530 weight = CW_Constant;
2531 }
2532 }
2533 break;
2534 case 'L':
2535 if (const ConstantInt *C = dyn_cast<ConstantInt>(Val: CallOperandVal)) {
2536 if (C->getZExtValue() == 0) {
2537 weight = CW_Constant;
2538 }
2539 }
2540 break;
2541 case 'M':
2542 if (const ConstantInt *C = dyn_cast<ConstantInt>(Val: CallOperandVal)) {
2543 if (isUInt<8>(x: C->getZExtValue())) {
2544 weight = CW_Constant;
2545 }
2546 }
2547 break;
2548 case 'N':
2549 if (const ConstantInt *C = dyn_cast<ConstantInt>(Val: CallOperandVal)) {
2550 if (C->getSExtValue() == -1) {
2551 weight = CW_Constant;
2552 }
2553 }
2554 break;
2555 case 'O':
2556 if (const ConstantInt *C = dyn_cast<ConstantInt>(Val: CallOperandVal)) {
2557 if ((C->getZExtValue() == 8) || (C->getZExtValue() == 16) ||
2558 (C->getZExtValue() == 24)) {
2559 weight = CW_Constant;
2560 }
2561 }
2562 break;
2563 case 'P':
2564 if (const ConstantInt *C = dyn_cast<ConstantInt>(Val: CallOperandVal)) {
2565 if (C->getZExtValue() == 1) {
2566 weight = CW_Constant;
2567 }
2568 }
2569 break;
2570 case 'R':
2571 if (const ConstantInt *C = dyn_cast<ConstantInt>(Val: CallOperandVal)) {
2572 if ((C->getSExtValue() >= -6) && (C->getSExtValue() <= 5)) {
2573 weight = CW_Constant;
2574 }
2575 }
2576 break;
2577 case 'Q':
2578 weight = CW_Memory;
2579 break;
2580 }
2581
2582 return weight;
2583}
2584
2585std::pair<unsigned, const TargetRegisterClass *>
2586AVRTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
2587 StringRef Constraint,
2588 MVT VT) const {
2589 if (Constraint.size() == 1) {
2590 switch (Constraint[0]) {
2591 case 'a': // Simple upper registers r16..r23.
2592 if (VT == MVT::i8)
2593 return std::make_pair(x: 0U, y: &AVR::LD8loRegClass);
2594 else if (VT == MVT::i16)
2595 return std::make_pair(x: 0U, y: &AVR::DREGSLD8loRegClass);
2596 break;
2597 case 'b': // Base pointer registers: y, z.
2598 if (VT == MVT::i8 || VT == MVT::i16)
2599 return std::make_pair(x: 0U, y: &AVR::PTRDISPREGSRegClass);
2600 break;
2601 case 'd': // Upper registers r16..r31.
2602 if (VT == MVT::i8)
2603 return std::make_pair(x: 0U, y: &AVR::LD8RegClass);
2604 else if (VT == MVT::i16)
2605 return std::make_pair(x: 0U, y: &AVR::DLDREGSRegClass);
2606 break;
2607 case 'l': // Lower registers r0..r15.
2608 if (VT == MVT::i8)
2609 return std::make_pair(x: 0U, y: &AVR::GPR8loRegClass);
2610 else if (VT == MVT::i16)
2611 return std::make_pair(x: 0U, y: &AVR::DREGSloRegClass);
2612 break;
2613 case 'e': // Pointer register pairs: x, y, z.
2614 if (VT == MVT::i8 || VT == MVT::i16)
2615 return std::make_pair(x: 0U, y: &AVR::PTRREGSRegClass);
2616 break;
2617 case 'q': // Stack pointer register: SPH:SPL.
2618 return std::make_pair(x: 0U, y: &AVR::GPRSPRegClass);
2619 case 'r': // Any register: r0..r31.
2620 if (VT == MVT::i8)
2621 return std::make_pair(x: 0U, y: &AVR::GPR8RegClass);
2622 else if (VT == MVT::i16)
2623 return std::make_pair(x: 0U, y: &AVR::DREGSRegClass);
2624 break;
2625 case 't': // Temporary register: r0.
2626 if (VT == MVT::i8)
2627 return std::make_pair(x: unsigned(Subtarget.getTmpRegister()),
2628 y: &AVR::GPR8RegClass);
2629 break;
2630 case 'w': // Special upper register pairs: r24, r26, r28, r30.
2631 if (VT == MVT::i8 || VT == MVT::i16)
2632 return std::make_pair(x: 0U, y: &AVR::IWREGSRegClass);
2633 break;
2634 case 'x': // Pointer register pair X: r27:r26.
2635 case 'X':
2636 if (VT == MVT::i8 || VT == MVT::i16)
2637 return std::make_pair(x: unsigned(AVR::R27R26), y: &AVR::PTRREGSRegClass);
2638 break;
2639 case 'y': // Pointer register pair Y: r29:r28.
2640 case 'Y':
2641 if (VT == MVT::i8 || VT == MVT::i16)
2642 return std::make_pair(x: unsigned(AVR::R29R28), y: &AVR::PTRREGSRegClass);
2643 break;
2644 case 'z': // Pointer register pair Z: r31:r30.
2645 case 'Z':
2646 if (VT == MVT::i8 || VT == MVT::i16)
2647 return std::make_pair(x: unsigned(AVR::R31R30), y: &AVR::PTRREGSRegClass);
2648 break;
2649 default:
2650 break;
2651 }
2652 }
2653
2654 return TargetLowering::getRegForInlineAsmConstraint(
2655 TRI: Subtarget.getRegisterInfo(), Constraint, VT);
2656}
2657
2658void AVRTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2659 StringRef Constraint,
2660 std::vector<SDValue> &Ops,
2661 SelectionDAG &DAG) const {
2662 SDValue Result;
2663 SDLoc DL(Op);
2664 EVT Ty = Op.getValueType();
2665
2666 // Currently only support length 1 constraints.
2667 if (Constraint.size() != 1) {
2668 return;
2669 }
2670
2671 char ConstraintLetter = Constraint[0];
2672 switch (ConstraintLetter) {
2673 default:
2674 break;
2675 // Deal with integers first:
2676 case 'I':
2677 case 'J':
2678 case 'K':
2679 case 'L':
2680 case 'M':
2681 case 'N':
2682 case 'O':
2683 case 'P':
2684 case 'R': {
2685 const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val&: Op);
2686 if (!C) {
2687 return;
2688 }
2689
2690 int64_t CVal64 = C->getSExtValue();
2691 uint64_t CUVal64 = C->getZExtValue();
2692 switch (ConstraintLetter) {
2693 case 'I': // 0..63
2694 if (!isUInt<6>(x: CUVal64))
2695 return;
2696 Result = DAG.getTargetConstant(Val: CUVal64, DL, VT: Ty);
2697 break;
2698 case 'J': // -63..0
2699 if (CVal64 < -63 || CVal64 > 0)
2700 return;
2701 Result = DAG.getTargetConstant(Val: CVal64, DL, VT: Ty);
2702 break;
2703 case 'K': // 2
2704 if (CUVal64 != 2)
2705 return;
2706 Result = DAG.getTargetConstant(Val: CUVal64, DL, VT: Ty);
2707 break;
2708 case 'L': // 0
2709 if (CUVal64 != 0)
2710 return;
2711 Result = DAG.getTargetConstant(Val: CUVal64, DL, VT: Ty);
2712 break;
2713 case 'M': // 0..255
2714 if (!isUInt<8>(x: CUVal64))
2715 return;
2716 // i8 type may be printed as a negative number,
2717 // e.g. 254 would be printed as -2,
2718 // so we force it to i16 at least.
2719 if (Ty.getSimpleVT() == MVT::i8) {
2720 Ty = MVT::i16;
2721 }
2722 Result = DAG.getTargetConstant(Val: CUVal64, DL, VT: Ty);
2723 break;
2724 case 'N': // -1
2725 if (CVal64 != -1)
2726 return;
2727 Result = DAG.getTargetConstant(Val: CVal64, DL, VT: Ty);
2728 break;
2729 case 'O': // 8, 16, 24
2730 if (CUVal64 != 8 && CUVal64 != 16 && CUVal64 != 24)
2731 return;
2732 Result = DAG.getTargetConstant(Val: CUVal64, DL, VT: Ty);
2733 break;
2734 case 'P': // 1
2735 if (CUVal64 != 1)
2736 return;
2737 Result = DAG.getTargetConstant(Val: CUVal64, DL, VT: Ty);
2738 break;
2739 case 'R': // -6..5
2740 if (CVal64 < -6 || CVal64 > 5)
2741 return;
2742 Result = DAG.getTargetConstant(Val: CVal64, DL, VT: Ty);
2743 break;
2744 }
2745
2746 break;
2747 }
2748 case 'G':
2749 const ConstantFPSDNode *FC = dyn_cast<ConstantFPSDNode>(Val&: Op);
2750 if (!FC || !FC->isZero())
2751 return;
2752 // Soften float to i8 0
2753 Result = DAG.getTargetConstant(Val: 0, DL, VT: MVT::i8);
2754 break;
2755 }
2756
2757 if (Result.getNode()) {
2758 Ops.push_back(x: Result);
2759 return;
2760 }
2761
2762 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2763}
2764
2765Register AVRTargetLowering::getRegisterByName(const char *RegName, LLT VT,
2766 const MachineFunction &MF) const {
2767 Register Reg;
2768
2769 if (VT == LLT::scalar(SizeInBits: 8)) {
2770 Reg = StringSwitch<unsigned>(RegName)
2771 .Case(S: "r0", Value: AVR::R0)
2772 .Case(S: "r1", Value: AVR::R1)
2773 .Default(Value: 0);
2774 } else {
2775 Reg = StringSwitch<unsigned>(RegName)
2776 .Case(S: "r0", Value: AVR::R1R0)
2777 .Case(S: "sp", Value: AVR::SP)
2778 .Default(Value: 0);
2779 }
2780
2781 if (Reg)
2782 return Reg;
2783
2784 report_fatal_error(
2785 reason: Twine("Invalid register name \"" + StringRef(RegName) + "\"."));
2786}
2787
2788} // end of namespace llvm
2789