1//===-- SIShrinkInstructions.cpp - Shrink Instructions --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7/// The pass tries to use the 32-bit encoding for instructions when possible.
8//===----------------------------------------------------------------------===//
9//
10
11#include "SIShrinkInstructions.h"
12#include "AMDGPU.h"
13#include "GCNSubtarget.h"
14#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
15#include "Utils/AMDGPUBaseInfo.h"
16#include "llvm/ADT/Statistic.h"
17#include "llvm/CodeGen/MachineFunctionPass.h"
18
19#define DEBUG_TYPE "si-shrink-instructions"
20
21STATISTIC(NumInstructionsShrunk,
22 "Number of 64-bit instruction reduced to 32-bit.");
23STATISTIC(NumLiteralConstantsFolded,
24 "Number of literal constants folded into 32-bit instructions.");
25
26using namespace llvm;
27
28namespace {
29
30enum ChangeKind { None, UpdateHint, UpdateInst };
31
32class SIShrinkInstructions {
33 MachineFunction *MF;
34 MachineRegisterInfo *MRI;
35 const GCNSubtarget *ST;
36 const SIInstrInfo *TII;
37 const SIRegisterInfo *TRI;
38 bool IsPostRA;
39
40 bool foldImmediates(MachineInstr &MI, bool TryToCommute = true) const;
41 bool shouldShrinkTrue16(MachineInstr &MI) const;
42 bool isKImmOperand(const MachineOperand &Src) const;
43 bool isKUImmOperand(const MachineOperand &Src) const;
44 bool isKImmOrKUImmOperand(const MachineOperand &Src, bool &IsUnsigned) const;
45 void copyExtraImplicitOps(MachineInstr &NewMI, MachineInstr &MI) const;
46 bool shrinkScalarCompare(MachineInstr &MI) const;
47 bool shrinkMIMG(MachineInstr &MI) const;
48 bool shrinkMadFma(MachineInstr &MI) const;
49 ChangeKind shrinkScalarLogicOp(MachineInstr &MI) const;
50 bool tryReplaceDeadSDST(MachineInstr &MI) const;
51 bool instAccessReg(MachineInstr::filtered_const_mop_range &&R, Register Reg,
52 unsigned SubReg) const;
53 bool instReadsReg(const MachineInstr *MI, unsigned Reg,
54 unsigned SubReg) const;
55 bool instModifiesReg(const MachineInstr *MI, unsigned Reg,
56 unsigned SubReg) const;
57 TargetInstrInfo::RegSubRegPair getSubRegForIndex(Register Reg, unsigned Sub,
58 unsigned I) const;
59 void dropInstructionKeepingImpDefs(MachineInstr &MI) const;
60 MachineInstr *matchSwap(MachineInstr &MovT) const;
61
62public:
63 SIShrinkInstructions() = default;
64 bool run(MachineFunction &MF);
65};
66
67class SIShrinkInstructionsLegacy : public MachineFunctionPass {
68
69public:
70 static char ID;
71
72 SIShrinkInstructionsLegacy() : MachineFunctionPass(ID) {}
73
74 bool runOnMachineFunction(MachineFunction &MF) override;
75
76 StringRef getPassName() const override { return "SI Shrink Instructions"; }
77
78 void getAnalysisUsage(AnalysisUsage &AU) const override {
79 AU.setPreservesCFG();
80 MachineFunctionPass::getAnalysisUsage(AU);
81 }
82};
83
84} // End anonymous namespace.
85
86INITIALIZE_PASS(SIShrinkInstructionsLegacy, DEBUG_TYPE,
87 "SI Shrink Instructions", false, false)
88
89char SIShrinkInstructionsLegacy::ID = 0;
90
91FunctionPass *llvm::createSIShrinkInstructionsLegacyPass() {
92 return new SIShrinkInstructionsLegacy();
93}
94
95/// This function checks \p MI for operands defined by a move immediate
96/// instruction and then folds the literal constant into the instruction if it
97/// can. This function assumes that \p MI is a VOP1, VOP2, or VOPC instructions.
98bool SIShrinkInstructions::foldImmediates(MachineInstr &MI,
99 bool TryToCommute) const {
100 assert(TII->isVOP1(MI) || TII->isVOP2(MI) || TII->isVOPC(MI));
101
102 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode: MI.getOpcode(), Name: AMDGPU::OpName::src0);
103
104 // Try to fold Src0
105 MachineOperand &Src0 = MI.getOperand(i: Src0Idx);
106 if (Src0.isReg()) {
107 Register Reg = Src0.getReg();
108 if (Reg.isVirtual()) {
109 MachineInstr *Def = MRI->getUniqueVRegDef(Reg);
110 if (Def && Def->isMoveImmediate()) {
111 MachineOperand &MovSrc = Def->getOperand(i: 1);
112 bool ConstantFolded = false;
113
114 if (TII->isOperandLegal(MI, OpIdx: Src0Idx, MO: &MovSrc)) {
115 if (MovSrc.isImm()) {
116 Src0.ChangeToImmediate(ImmVal: MovSrc.getImm());
117 ConstantFolded = true;
118 } else if (MovSrc.isFI()) {
119 Src0.ChangeToFrameIndex(Idx: MovSrc.getIndex());
120 ConstantFolded = true;
121 } else if (MovSrc.isGlobal()) {
122 Src0.ChangeToGA(GV: MovSrc.getGlobal(), Offset: MovSrc.getOffset(),
123 TargetFlags: MovSrc.getTargetFlags());
124 ConstantFolded = true;
125 }
126 }
127
128 if (ConstantFolded) {
129 if (MRI->use_nodbg_empty(RegNo: Reg))
130 Def->eraseFromParent();
131 ++NumLiteralConstantsFolded;
132 return true;
133 }
134 }
135 }
136 }
137
138 // We have failed to fold src0, so commute the instruction and try again.
139 if (TryToCommute && MI.isCommutable()) {
140 if (TII->commuteInstruction(MI)) {
141 if (foldImmediates(MI, TryToCommute: false))
142 return true;
143
144 // Commute back.
145 TII->commuteInstruction(MI);
146 }
147 }
148
149 return false;
150}
151
152/// Do not shrink the instruction if its registers are not expressible in the
153/// shrunk encoding.
154bool SIShrinkInstructions::shouldShrinkTrue16(MachineInstr &MI) const {
155 for (unsigned I = 0, E = MI.getNumExplicitOperands(); I != E; ++I) {
156 const MachineOperand &MO = MI.getOperand(i: I);
157 if (MO.isReg()) {
158 Register Reg = MO.getReg();
159 assert(!Reg.isVirtual() && "Prior checks should ensure we only shrink "
160 "True16 Instructions post-RA");
161 if (AMDGPU::VGPR_32RegClass.contains(Reg) &&
162 !AMDGPU::VGPR_32_Lo128RegClass.contains(Reg))
163 return false;
164
165 if (AMDGPU::VGPR_16RegClass.contains(Reg) &&
166 !AMDGPU::VGPR_16_Lo128RegClass.contains(Reg))
167 return false;
168 }
169 }
170 return true;
171}
172
173bool SIShrinkInstructions::isKImmOperand(const MachineOperand &Src) const {
174 return isInt<16>(x: SignExtend64(X: Src.getImm(), B: 32)) &&
175 !TII->isInlineConstant(MI: *Src.getParent(), OpIdx: Src.getOperandNo());
176}
177
178bool SIShrinkInstructions::isKUImmOperand(const MachineOperand &Src) const {
179 return isUInt<16>(x: Src.getImm()) &&
180 !TII->isInlineConstant(MI: *Src.getParent(), OpIdx: Src.getOperandNo());
181}
182
183bool SIShrinkInstructions::isKImmOrKUImmOperand(const MachineOperand &Src,
184 bool &IsUnsigned) const {
185 if (isInt<16>(x: SignExtend64(X: Src.getImm(), B: 32))) {
186 IsUnsigned = false;
187 return !TII->isInlineConstant(MO: Src);
188 }
189
190 if (isUInt<16>(x: Src.getImm())) {
191 IsUnsigned = true;
192 return !TII->isInlineConstant(MO: Src);
193 }
194
195 return false;
196}
197
198/// \returns the opcode of an instruction a move immediate of the constant \p
199/// Src can be replaced with if the constant is replaced with \p ModifiedImm.
200/// i.e.
201///
202/// If the bitreverse of a constant is an inline immediate, reverse the
203/// immediate and return the bitreverse opcode.
204///
205/// If the bitwise negation of a constant is an inline immediate, reverse the
206/// immediate and return the bitwise not opcode.
207static unsigned canModifyToInlineImmOp32(const SIInstrInfo *TII,
208 const MachineOperand &Src,
209 int32_t &ModifiedImm, bool Scalar) {
210 if (TII->isInlineConstant(MO: Src))
211 return 0;
212 int32_t SrcImm = static_cast<int32_t>(Src.getImm());
213
214 if (!Scalar) {
215 // We could handle the scalar case with here, but we would need to check
216 // that SCC is not live as S_NOT_B32 clobbers it. It's probably not worth
217 // it, as the reasonable values are already covered by s_movk_i32.
218 ModifiedImm = ~SrcImm;
219 if (TII->isInlineConstant(Imm: APInt(32, ModifiedImm, true)))
220 return AMDGPU::V_NOT_B32_e32;
221 }
222
223 ModifiedImm = reverseBits<int32_t>(Val: SrcImm);
224 if (TII->isInlineConstant(Imm: APInt(32, ModifiedImm, true)))
225 return Scalar ? AMDGPU::S_BREV_B32 : AMDGPU::V_BFREV_B32_e32;
226
227 return 0;
228}
229
230/// Copy implicit register operands from specified instruction to this
231/// instruction that are not part of the instruction definition.
232void SIShrinkInstructions::copyExtraImplicitOps(MachineInstr &NewMI,
233 MachineInstr &MI) const {
234 MachineFunction &MF = *MI.getMF();
235 for (unsigned i = MI.getDesc().getNumOperands() +
236 MI.getDesc().implicit_uses().size() +
237 MI.getDesc().implicit_defs().size(),
238 e = MI.getNumOperands();
239 i != e; ++i) {
240 const MachineOperand &MO = MI.getOperand(i);
241 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
242 NewMI.addOperand(MF, Op: MO);
243 }
244}
245
246bool SIShrinkInstructions::shrinkScalarCompare(MachineInstr &MI) const {
247 if (!ST->hasSCmpK())
248 return false;
249
250 // cmpk instructions do scc = dst <cc op> imm16, so commute the instruction to
251 // get constants on the RHS.
252 bool Changed = false;
253 if (!MI.getOperand(i: 0).isReg()) {
254 if (TII->commuteInstruction(MI, NewMI: false, OpIdx1: 0, OpIdx2: 1))
255 Changed = true;
256 }
257
258 // cmpk requires src0 to be a register
259 const MachineOperand &Src0 = MI.getOperand(i: 0);
260 if (!Src0.isReg())
261 return Changed;
262
263 MachineOperand &Src1 = MI.getOperand(i: 1);
264 if (!Src1.isImm())
265 return Changed;
266
267 int SOPKOpc = AMDGPU::getSOPKOp(Opcode: MI.getOpcode());
268 if (SOPKOpc == -1)
269 return Changed;
270
271 // eq/ne is special because the imm16 can be treated as signed or unsigned,
272 // and initially selected to the unsigned versions.
273 if (SOPKOpc == AMDGPU::S_CMPK_EQ_U32 || SOPKOpc == AMDGPU::S_CMPK_LG_U32) {
274 bool HasUImm;
275 if (isKImmOrKUImmOperand(Src: Src1, IsUnsigned&: HasUImm)) {
276 if (!HasUImm) {
277 SOPKOpc = (SOPKOpc == AMDGPU::S_CMPK_EQ_U32) ?
278 AMDGPU::S_CMPK_EQ_I32 : AMDGPU::S_CMPK_LG_I32;
279 Src1.setImm(SignExtend32(X: Src1.getImm(), B: 32));
280 }
281
282 MI.setDesc(TII->get(Opcode: SOPKOpc));
283 Changed = true;
284 }
285
286 return Changed;
287 }
288
289 const MCInstrDesc &NewDesc = TII->get(Opcode: SOPKOpc);
290
291 if ((SIInstrInfo::sopkIsZext(Opcode: SOPKOpc) && isKUImmOperand(Src: Src1)) ||
292 (!SIInstrInfo::sopkIsZext(Opcode: SOPKOpc) && isKImmOperand(Src: Src1))) {
293 if (!SIInstrInfo::sopkIsZext(Opcode: SOPKOpc))
294 Src1.setImm(SignExtend64(X: Src1.getImm(), B: 32));
295 MI.setDesc(NewDesc);
296 Changed = true;
297 }
298 return Changed;
299}
300
301// Shrink NSA encoded instructions with contiguous VGPRs to non-NSA encoding.
302bool SIShrinkInstructions::shrinkMIMG(MachineInstr &MI) const {
303 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc: MI.getOpcode());
304 if (!Info)
305 return false;
306
307 uint8_t NewEncoding;
308 switch (Info->MIMGEncoding) {
309 case AMDGPU::MIMGEncGfx10NSA:
310 NewEncoding = AMDGPU::MIMGEncGfx10Default;
311 break;
312 case AMDGPU::MIMGEncGfx11NSA:
313 NewEncoding = AMDGPU::MIMGEncGfx11Default;
314 break;
315 default:
316 return false;
317 }
318
319 int VAddr0Idx =
320 AMDGPU::getNamedOperandIdx(Opcode: MI.getOpcode(), Name: AMDGPU::OpName::vaddr0);
321 unsigned NewAddrDwords = Info->VAddrDwords;
322 const TargetRegisterClass *RC;
323
324 if (Info->VAddrDwords == 2) {
325 RC = &AMDGPU::VReg_64RegClass;
326 } else if (Info->VAddrDwords == 3) {
327 RC = &AMDGPU::VReg_96RegClass;
328 } else if (Info->VAddrDwords == 4) {
329 RC = &AMDGPU::VReg_128RegClass;
330 } else if (Info->VAddrDwords == 5) {
331 RC = &AMDGPU::VReg_160RegClass;
332 } else if (Info->VAddrDwords == 6) {
333 RC = &AMDGPU::VReg_192RegClass;
334 } else if (Info->VAddrDwords == 7) {
335 RC = &AMDGPU::VReg_224RegClass;
336 } else if (Info->VAddrDwords == 8) {
337 RC = &AMDGPU::VReg_256RegClass;
338 } else if (Info->VAddrDwords == 9) {
339 RC = &AMDGPU::VReg_288RegClass;
340 } else if (Info->VAddrDwords == 10) {
341 RC = &AMDGPU::VReg_320RegClass;
342 } else if (Info->VAddrDwords == 11) {
343 RC = &AMDGPU::VReg_352RegClass;
344 } else if (Info->VAddrDwords == 12) {
345 RC = &AMDGPU::VReg_384RegClass;
346 } else {
347 RC = &AMDGPU::VReg_512RegClass;
348 NewAddrDwords = 16;
349 }
350
351 unsigned VgprBase = 0;
352 unsigned NextVgpr = 0;
353 bool IsUndef = true;
354 bool IsKill = NewAddrDwords == Info->VAddrDwords;
355 const unsigned NSAMaxSize = ST->getNSAMaxSize();
356 const bool IsPartialNSA = NewAddrDwords > NSAMaxSize;
357 const unsigned EndVAddr = IsPartialNSA ? NSAMaxSize : Info->VAddrOperands;
358 for (unsigned Idx = 0; Idx < EndVAddr; ++Idx) {
359 const MachineOperand &Op = MI.getOperand(i: VAddr0Idx + Idx);
360 unsigned Vgpr = TRI->getHWRegIndex(Reg: Op.getReg());
361 unsigned Dwords = TRI->getRegSizeInBits(Reg: Op.getReg(), MRI: *MRI) / 32;
362 assert(Dwords > 0 && "Un-implemented for less than 32 bit regs");
363
364 if (Idx == 0) {
365 VgprBase = Vgpr;
366 NextVgpr = Vgpr + Dwords;
367 } else if (Vgpr == NextVgpr) {
368 NextVgpr = Vgpr + Dwords;
369 } else {
370 return false;
371 }
372
373 if (!Op.isUndef())
374 IsUndef = false;
375 if (!Op.isKill())
376 IsKill = false;
377 }
378
379 if (VgprBase + NewAddrDwords > 256)
380 return false;
381
382 // Further check for implicit tied operands - this may be present if TFE is
383 // enabled
384 int TFEIdx = AMDGPU::getNamedOperandIdx(Opcode: MI.getOpcode(), Name: AMDGPU::OpName::tfe);
385 int LWEIdx = AMDGPU::getNamedOperandIdx(Opcode: MI.getOpcode(), Name: AMDGPU::OpName::lwe);
386 unsigned TFEVal = (TFEIdx == -1) ? 0 : MI.getOperand(i: TFEIdx).getImm();
387 unsigned LWEVal = (LWEIdx == -1) ? 0 : MI.getOperand(i: LWEIdx).getImm();
388 int ToUntie = -1;
389 if (TFEVal || LWEVal) {
390 // TFE/LWE is enabled so we need to deal with an implicit tied operand
391 for (unsigned i = LWEIdx + 1, e = MI.getNumOperands(); i != e; ++i) {
392 if (MI.getOperand(i).isReg() && MI.getOperand(i).isTied() &&
393 MI.getOperand(i).isImplicit()) {
394 // This is the tied operand
395 assert(
396 ToUntie == -1 &&
397 "found more than one tied implicit operand when expecting only 1");
398 ToUntie = i;
399 MI.untieRegOperand(OpIdx: ToUntie);
400 }
401 }
402 }
403
404 unsigned NewOpcode = AMDGPU::getMIMGOpcode(BaseOpcode: Info->BaseOpcode, MIMGEncoding: NewEncoding,
405 VDataDwords: Info->VDataDwords, VAddrDwords: NewAddrDwords);
406 MI.setDesc(TII->get(Opcode: NewOpcode));
407 MI.getOperand(i: VAddr0Idx).setReg(RC->getRegister(i: VgprBase));
408 MI.getOperand(i: VAddr0Idx).setIsUndef(IsUndef);
409 MI.getOperand(i: VAddr0Idx).setIsKill(IsKill);
410
411 for (unsigned i = 1; i < EndVAddr; ++i)
412 MI.removeOperand(OpNo: VAddr0Idx + 1);
413
414 if (ToUntie >= 0) {
415 MI.tieOperands(
416 DefIdx: AMDGPU::getNamedOperandIdx(Opcode: MI.getOpcode(), Name: AMDGPU::OpName::vdata),
417 UseIdx: ToUntie - (EndVAddr - 1));
418 }
419 return true;
420}
421
422// Shrink MAD to MADAK/MADMK and FMA to FMAAK/FMAMK.
423bool SIShrinkInstructions::shrinkMadFma(MachineInstr &MI) const {
424 // Pre-GFX10 VOP3 instructions like MAD/FMA cannot take a literal operand so
425 // there is no reason to try to shrink them.
426 if (!ST->hasVOP3Literal())
427 return false;
428
429 // There is no advantage to doing this pre-RA.
430 if (!IsPostRA)
431 return false;
432
433 if (TII->hasAnyModifiersSet(MI))
434 return false;
435
436 const unsigned Opcode = MI.getOpcode();
437 MachineOperand &Src0 = *TII->getNamedOperand(MI, OperandName: AMDGPU::OpName::src0);
438 MachineOperand &Src1 = *TII->getNamedOperand(MI, OperandName: AMDGPU::OpName::src1);
439 MachineOperand &Src2 = *TII->getNamedOperand(MI, OperandName: AMDGPU::OpName::src2);
440 unsigned NewOpcode = AMDGPU::INSTRUCTION_LIST_END;
441
442 bool Swap;
443
444 // Detect "Dst = VSrc * VGPR + Imm" and convert to AK form.
445 if (Src2.isImm() && !TII->isInlineConstant(MO: Src2)) {
446 if (Src1.isReg() && TRI->isVGPR(MRI: *MRI, Reg: Src1.getReg()))
447 Swap = false;
448 else if (Src0.isReg() && TRI->isVGPR(MRI: *MRI, Reg: Src0.getReg()))
449 Swap = true;
450 else
451 return false;
452
453 switch (Opcode) {
454 default:
455 llvm_unreachable("Unexpected mad/fma opcode!");
456 case AMDGPU::V_MAD_F32_e64:
457 NewOpcode = AMDGPU::V_MADAK_F32;
458 break;
459 case AMDGPU::V_FMA_F32_e64:
460 NewOpcode = AMDGPU::V_FMAAK_F32;
461 break;
462 case AMDGPU::V_MAD_F16_e64:
463 NewOpcode = AMDGPU::V_MADAK_F16;
464 break;
465 case AMDGPU::V_FMA_F16_e64:
466 case AMDGPU::V_FMA_F16_gfx9_e64:
467 NewOpcode = AMDGPU::V_FMAAK_F16;
468 break;
469 case AMDGPU::V_FMA_F16_gfx9_t16_e64:
470 NewOpcode = AMDGPU::V_FMAAK_F16_t16;
471 break;
472 case AMDGPU::V_FMA_F16_gfx9_fake16_e64:
473 NewOpcode = AMDGPU::V_FMAAK_F16_fake16;
474 break;
475 case AMDGPU::V_FMA_F64_e64:
476 if (ST->hasFmaakFmamkF64Insts())
477 NewOpcode = AMDGPU::V_FMAAK_F64;
478 break;
479 }
480 }
481
482 // Detect "Dst = VSrc * Imm + VGPR" and convert to MK form.
483 if (Src2.isReg() && TRI->isVGPR(MRI: *MRI, Reg: Src2.getReg())) {
484 if (Src1.isImm() && !TII->isInlineConstant(MO: Src1))
485 Swap = false;
486 else if (Src0.isImm() && !TII->isInlineConstant(MO: Src0))
487 Swap = true;
488 else
489 return false;
490
491 switch (Opcode) {
492 default:
493 llvm_unreachable("Unexpected mad/fma opcode!");
494 case AMDGPU::V_MAD_F32_e64:
495 NewOpcode = AMDGPU::V_MADMK_F32;
496 break;
497 case AMDGPU::V_FMA_F32_e64:
498 NewOpcode = AMDGPU::V_FMAMK_F32;
499 break;
500 case AMDGPU::V_MAD_F16_e64:
501 NewOpcode = AMDGPU::V_MADMK_F16;
502 break;
503 case AMDGPU::V_FMA_F16_e64:
504 case AMDGPU::V_FMA_F16_gfx9_e64:
505 NewOpcode = AMDGPU::V_FMAMK_F16;
506 break;
507 case AMDGPU::V_FMA_F16_gfx9_t16_e64:
508 NewOpcode = AMDGPU::V_FMAMK_F16_t16;
509 break;
510 case AMDGPU::V_FMA_F16_gfx9_fake16_e64:
511 NewOpcode = AMDGPU::V_FMAMK_F16_fake16;
512 break;
513 case AMDGPU::V_FMA_F64_e64:
514 if (ST->hasFmaakFmamkF64Insts())
515 NewOpcode = AMDGPU::V_FMAMK_F64;
516 break;
517 }
518 }
519
520 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END)
521 return false;
522
523 if (AMDGPU::isTrue16Inst(Opc: NewOpcode) && !shouldShrinkTrue16(MI))
524 return false;
525
526 if (Swap) {
527 // Swap Src0 and Src1 by building a new instruction.
528 BuildMI(BB&: *MI.getParent(), I&: MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: NewOpcode),
529 DestReg: MI.getOperand(i: 0).getReg())
530 .add(MO: Src1)
531 .add(MO: Src0)
532 .add(MO: Src2)
533 .setMIFlags(MI.getFlags());
534 MI.eraseFromParent();
535 } else {
536 TII->removeModOperands(MI);
537 MI.setDesc(TII->get(Opcode: NewOpcode));
538 }
539 return true;
540}
541
542/// Attempt to shrink AND/OR/XOR operations requiring non-inlineable literals.
543/// For AND or OR, try using S_BITSET{0,1} to clear or set bits.
544/// If the inverse of the immediate is legal, use ANDN2, ORN2 or
545/// XNOR (as a ^ b == ~(a ^ ~b)).
546/// \return ChangeKind::None if no changes were made.
547/// ChangeKind::UpdateHint if regalloc hints were updated.
548/// ChangeKind::UpdateInst if the instruction was modified.
549ChangeKind SIShrinkInstructions::shrinkScalarLogicOp(MachineInstr &MI) const {
550 unsigned Opc = MI.getOpcode();
551 const MachineOperand *Dest = &MI.getOperand(i: 0);
552 MachineOperand *Src0 = &MI.getOperand(i: 1);
553 MachineOperand *Src1 = &MI.getOperand(i: 2);
554 MachineOperand *SrcReg = Src0;
555 MachineOperand *SrcImm = Src1;
556
557 if (!SrcImm->isImm() ||
558 AMDGPU::isInlinableLiteral32(Literal: SrcImm->getImm(), HasInv2Pi: ST->hasInv2PiInlineImm()))
559 return ChangeKind::None;
560
561 uint32_t Imm = static_cast<uint32_t>(SrcImm->getImm());
562 uint32_t NewImm = 0;
563
564 if (Opc == AMDGPU::S_AND_B32) {
565 if (isPowerOf2_32(Value: ~Imm) &&
566 MI.findRegisterDefOperand(Reg: AMDGPU::SCC, /*TRI=*/nullptr)->isDead()) {
567 NewImm = llvm::countr_one(Value: Imm);
568 Opc = AMDGPU::S_BITSET0_B32;
569 } else if (AMDGPU::isInlinableLiteral32(Literal: ~Imm, HasInv2Pi: ST->hasInv2PiInlineImm())) {
570 NewImm = ~Imm;
571 Opc = AMDGPU::S_ANDN2_B32;
572 }
573 } else if (Opc == AMDGPU::S_OR_B32) {
574 if (isPowerOf2_32(Value: Imm) &&
575 MI.findRegisterDefOperand(Reg: AMDGPU::SCC, /*TRI=*/nullptr)->isDead()) {
576 NewImm = llvm::countr_zero(Val: Imm);
577 Opc = AMDGPU::S_BITSET1_B32;
578 } else if (AMDGPU::isInlinableLiteral32(Literal: ~Imm, HasInv2Pi: ST->hasInv2PiInlineImm())) {
579 NewImm = ~Imm;
580 Opc = AMDGPU::S_ORN2_B32;
581 }
582 } else if (Opc == AMDGPU::S_XOR_B32) {
583 if (AMDGPU::isInlinableLiteral32(Literal: ~Imm, HasInv2Pi: ST->hasInv2PiInlineImm())) {
584 NewImm = ~Imm;
585 Opc = AMDGPU::S_XNOR_B32;
586 }
587 } else {
588 llvm_unreachable("unexpected opcode");
589 }
590
591 if (NewImm != 0) {
592 if (Dest->getReg().isVirtual() && SrcReg->isReg()) {
593 MRI->setRegAllocationHint(VReg: Dest->getReg(), Type: 0, PrefReg: SrcReg->getReg());
594 MRI->setRegAllocationHint(VReg: SrcReg->getReg(), Type: 0, PrefReg: Dest->getReg());
595 return ChangeKind::UpdateHint;
596 }
597
598 if (SrcReg->isReg() && SrcReg->getReg() == Dest->getReg()) {
599 const bool IsUndef = SrcReg->isUndef();
600 const bool IsKill = SrcReg->isKill();
601 TII->mutateAndCleanupImplicit(MI, NewDesc: TII->get(Opcode: Opc));
602 if (Opc == AMDGPU::S_BITSET0_B32 ||
603 Opc == AMDGPU::S_BITSET1_B32) {
604 Src0->ChangeToImmediate(ImmVal: NewImm);
605 // Remove the immediate and add the tied input.
606 MI.getOperand(i: 2).ChangeToRegister(Reg: Dest->getReg(), /*IsDef*/ isDef: false,
607 /*isImp*/ false, isKill: IsKill,
608 /*isDead*/ false, isUndef: IsUndef);
609 MI.tieOperands(DefIdx: 0, UseIdx: 2);
610 } else {
611 SrcImm->setImm(NewImm);
612 }
613 return ChangeKind::UpdateInst;
614 }
615 }
616
617 return ChangeKind::None;
618}
619
620// This is the same as MachineInstr::readsRegister/modifiesRegister except
621// it takes subregs into account.
622bool SIShrinkInstructions::instAccessReg(
623 MachineInstr::filtered_const_mop_range &&R, Register Reg,
624 unsigned SubReg) const {
625 for (const MachineOperand &MO : R) {
626 if (Reg.isPhysical() && MO.getReg().isPhysical()) {
627 if (TRI->regsOverlap(RegA: Reg, RegB: MO.getReg()))
628 return true;
629 } else if (MO.getReg() == Reg && Reg.isVirtual()) {
630 LaneBitmask Overlap = TRI->getSubRegIndexLaneMask(SubIdx: SubReg) &
631 TRI->getSubRegIndexLaneMask(SubIdx: MO.getSubReg());
632 if (Overlap.any())
633 return true;
634 }
635 }
636 return false;
637}
638
639bool SIShrinkInstructions::instReadsReg(const MachineInstr *MI, unsigned Reg,
640 unsigned SubReg) const {
641 return instAccessReg(R: MI->all_uses(), Reg, SubReg);
642}
643
644bool SIShrinkInstructions::instModifiesReg(const MachineInstr *MI, unsigned Reg,
645 unsigned SubReg) const {
646 return instAccessReg(R: MI->all_defs(), Reg, SubReg);
647}
648
649TargetInstrInfo::RegSubRegPair
650SIShrinkInstructions::getSubRegForIndex(Register Reg, unsigned Sub,
651 unsigned I) const {
652 if (TRI->getRegSizeInBits(Reg, MRI: *MRI) != 32) {
653 if (Reg.isPhysical()) {
654 Reg = TRI->getSubReg(Reg, Idx: TRI->getSubRegFromChannel(Channel: I));
655 } else {
656 Sub = TRI->getSubRegFromChannel(Channel: I + TRI->getChannelFromSubReg(SubReg: Sub));
657 }
658 }
659 return TargetInstrInfo::RegSubRegPair(Reg, Sub);
660}
661
662void SIShrinkInstructions::dropInstructionKeepingImpDefs(
663 MachineInstr &MI) const {
664 for (unsigned i = MI.getDesc().getNumOperands() +
665 MI.getDesc().implicit_uses().size() +
666 MI.getDesc().implicit_defs().size(),
667 e = MI.getNumOperands();
668 i != e; ++i) {
669 const MachineOperand &Op = MI.getOperand(i);
670 if (!Op.isDef())
671 continue;
672 BuildMI(BB&: *MI.getParent(), I: MI.getIterator(), MIMD: MI.getDebugLoc(),
673 MCID: TII->get(Opcode: AMDGPU::IMPLICIT_DEF), DestReg: Op.getReg());
674 }
675
676 MI.eraseFromParent();
677}
678
679// Match:
680// mov t, x
681// mov x, y
682// mov y, t
683//
684// =>
685//
686// mov t, x (t is potentially dead and move eliminated)
687// v_swap_b32 x, y
688//
689// Returns next valid instruction pointer if was able to create v_swap_b32.
690//
691// This shall not be done too early not to prevent possible folding which may
692// remove matched moves, and this should preferably be done before RA to
693// release saved registers and also possibly after RA which can insert copies
694// too.
695//
696// This is really just a generic peephole that is not a canonical shrinking,
697// although requirements match the pass placement and it reduces code size too.
698MachineInstr *SIShrinkInstructions::matchSwap(MachineInstr &MovT) const {
699 assert(MovT.getOpcode() == AMDGPU::V_MOV_B32_e32 ||
700 MovT.getOpcode() == AMDGPU::V_MOV_B16_t16_e32 ||
701 MovT.getOpcode() == AMDGPU::COPY);
702
703 Register T = MovT.getOperand(i: 0).getReg();
704 unsigned Tsub = MovT.getOperand(i: 0).getSubReg();
705 MachineOperand &Xop = MovT.getOperand(i: 1);
706
707 if (!Xop.isReg())
708 return nullptr;
709 Register X = Xop.getReg();
710 unsigned Xsub = Xop.getSubReg();
711 Register Y;
712 unsigned Ysub;
713
714 unsigned Size = TII->getOpSize(MI: MovT, OpNo: 0);
715
716 // We can't match v_swap_b16 pre-RA, because VGPR_16_Lo128 registers
717 // are not allocatble.
718 if (Size == 2 && X.isVirtual())
719 return nullptr;
720
721 if (!TRI->isVGPR(MRI: *MRI, Reg: X))
722 return nullptr;
723
724 const unsigned SearchLimit = 16;
725 unsigned Count = 0;
726
727 MachineInstr *MovX = nullptr;
728 MachineInstr *InsertionPt = nullptr;
729 MachineInstr *MovY = nullptr;
730
731 for (auto Iter = std::next(x: MovT.getIterator()),
732 E = MovT.getParent()->instr_end();
733 Iter != E && Count < SearchLimit; ++Iter) {
734 if (Iter->isDebugInstr())
735 continue;
736 ++Count;
737
738 if (!MovX) {
739 // Search for mov x, y.
740 if ((Iter->getOpcode() == AMDGPU::V_MOV_B32_e32 ||
741 Iter->getOpcode() == AMDGPU::V_MOV_B16_t16_e32 ||
742 Iter->getOpcode() == AMDGPU::COPY) &&
743 Iter->getOperand(i: 0).getReg() == X &&
744 Iter->getOperand(i: 0).getSubReg() == Xsub &&
745 Iter->getOperand(i: 1).isReg()) {
746 MovX = &*Iter;
747 Y = MovX->getOperand(i: 1).getReg();
748 Ysub = MovX->getOperand(i: 1).getSubReg();
749 } else if (instModifiesReg(MI: &*Iter, Reg: X, SubReg: Xsub)) {
750 // Writes to x are not allowed until mov x, y has been found
751 return nullptr;
752 }
753 } else {
754 // mov x, y has been found.
755 // Search for mov y, t.
756 if ((Iter->getOpcode() == AMDGPU::V_MOV_B32_e32 ||
757 Iter->getOpcode() == AMDGPU::V_MOV_B16_t16_e32 ||
758 Iter->getOpcode() == AMDGPU::COPY) &&
759 Iter->getOperand(i: 0).getReg() == Y &&
760 Iter->getOperand(i: 0).getSubReg() == Ysub &&
761 Iter->getOperand(i: 1).isReg() && Iter->getOperand(i: 1).getReg() == T &&
762 Iter->getOperand(i: 1).getSubReg() == Tsub) {
763 MovY = &*Iter;
764 break;
765 }
766
767 // Effectively, mov x, y must be moved downward
768 // and mov y, t must be moved upward so that they can be fused into a
769 // swap. A write to y creates a barrier that prevents the two moves from
770 // being moved adjacent to each other.
771 if (instModifiesReg(MI: &*Iter, Reg: Y, SubReg: Ysub))
772 return nullptr;
773
774 // Reads or writes to x prevent mov x, y from being moved farther
775 // downward. Select this to be the insertion point.
776 if (!InsertionPt &&
777 (instReadsReg(MI: &*Iter, Reg: X, SubReg: Xsub) || instModifiesReg(MI: &*Iter, Reg: X, SubReg: Xsub))) {
778 InsertionPt = &*Iter;
779 }
780 // If the insertion point has been found, then mov y, t must be moved
781 // upward past all subsequent instructions. A read of y will block this
782 // movement.
783 if (InsertionPt) {
784 if (instReadsReg(MI: &*Iter, Reg: Y, SubReg: Ysub))
785 return nullptr;
786 }
787 }
788
789 if (instModifiesReg(MI: &*Iter, Reg: T, SubReg: Tsub))
790 return nullptr;
791 }
792 if (MovY) {
793 LLVM_DEBUG(dbgs() << "Matched v_swap:\n" << MovT << *MovX << *MovY);
794
795 MachineBasicBlock &MBB = *MovT.getParent();
796 SmallVector<MachineInstr *, 4> Swaps;
797
798 if (!InsertionPt)
799 InsertionPt = MovY;
800 if (Size == 2) {
801 auto *MIB = BuildMI(BB&: MBB, I: InsertionPt->getIterator(), MIMD: MovT.getDebugLoc(),
802 MCID: TII->get(Opcode: AMDGPU::V_SWAP_B16))
803 .addDef(RegNo: X)
804 .addDef(RegNo: Y)
805 .addReg(RegNo: Y)
806 .addReg(RegNo: X)
807 .getInstr();
808 Swaps.push_back(Elt: MIB);
809 } else {
810 assert(Size > 0 && Size % 4 == 0);
811 for (unsigned I = 0; I < Size / 4; ++I) {
812 TargetInstrInfo::RegSubRegPair X1, Y1;
813 X1 = getSubRegForIndex(Reg: X, Sub: Xsub, I);
814 Y1 = getSubRegForIndex(Reg: Y, Sub: Ysub, I);
815 auto *MIB = BuildMI(BB&: MBB, I: InsertionPt->getIterator(), MIMD: MovT.getDebugLoc(),
816 MCID: TII->get(Opcode: AMDGPU::V_SWAP_B32))
817 .addDef(RegNo: X1.Reg, Flags: {}, SubReg: X1.SubReg)
818 .addDef(RegNo: Y1.Reg, Flags: {}, SubReg: Y1.SubReg)
819 .addReg(RegNo: Y1.Reg, Flags: {}, SubReg: Y1.SubReg)
820 .addReg(RegNo: X1.Reg, Flags: {}, SubReg: X1.SubReg)
821 .getInstr();
822 Swaps.push_back(Elt: MIB);
823 }
824 }
825 // Drop implicit EXEC.
826 if (MovX->hasRegisterImplicitUseOperand(Reg: AMDGPU::EXEC)) {
827 for (MachineInstr *Swap : Swaps) {
828 Swap->removeOperand(OpNo: Swap->getNumExplicitOperands());
829 Swap->copyImplicitOps(MF&: *MBB.getParent(), MI: *MovX);
830 }
831 }
832 MovX->eraseFromParent();
833 dropInstructionKeepingImpDefs(MI&: *MovY);
834 MachineInstr *Next = &*std::next(x: MovT.getIterator());
835
836 if (T.isVirtual() && MRI->use_nodbg_empty(RegNo: T)) {
837 dropInstructionKeepingImpDefs(MI&: MovT);
838 } else {
839 Xop.setIsKill(false);
840 for (int I = MovT.getNumImplicitOperands() - 1; I >= 0; --I ) {
841 unsigned OpNo = MovT.getNumExplicitOperands() + I;
842 const MachineOperand &Op = MovT.getOperand(i: OpNo);
843 if (Op.isKill() && TRI->regsOverlap(RegA: X, RegB: Op.getReg()))
844 MovT.removeOperand(OpNo);
845 }
846 }
847
848 return Next;
849 }
850 return nullptr;
851}
852
853// If an instruction has dead sdst replace it with NULL register on gfx1030+
854bool SIShrinkInstructions::tryReplaceDeadSDST(MachineInstr &MI) const {
855 if (!ST->hasGFX10_3Insts())
856 return false;
857
858 MachineOperand *Op = TII->getNamedOperand(MI, OperandName: AMDGPU::OpName::sdst);
859 if (!Op)
860 return false;
861 Register SDstReg = Op->getReg();
862 if (SDstReg.isPhysical() || !MRI->use_nodbg_empty(RegNo: SDstReg))
863 return false;
864
865 Op->setReg(ST->isWave32() ? AMDGPU::SGPR_NULL : AMDGPU::SGPR_NULL64);
866 return true;
867}
868
869bool SIShrinkInstructions::run(MachineFunction &MF) {
870
871 this->MF = &MF;
872 MRI = &MF.getRegInfo();
873 ST = &MF.getSubtarget<GCNSubtarget>();
874 TII = ST->getInstrInfo();
875 TRI = &TII->getRegisterInfo();
876 IsPostRA = MF.getProperties().hasNoVRegs();
877
878 unsigned VCCReg = ST->isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC;
879 bool Changed = false;
880
881 for (MachineBasicBlock &MBB : MF) {
882 MachineBasicBlock::iterator I, Next;
883 for (I = MBB.begin(); I != MBB.end(); I = Next) {
884 Next = std::next(x: I);
885 MachineInstr &MI = *I;
886
887 if (MI.getOpcode() == AMDGPU::V_MOV_B32_e32) {
888 // If this has a literal constant source that is the same as the
889 // reversed bits of an inline immediate, replace with a bitreverse of
890 // that constant. This saves 4 bytes in the common case of materializing
891 // sign bits.
892
893 // Test if we are after regalloc. We only want to do this after any
894 // optimizations happen because this will confuse them.
895 MachineOperand &Src = MI.getOperand(i: 1);
896 if (Src.isImm() && IsPostRA) {
897 int32_t ModImm;
898 unsigned ModOpcode =
899 canModifyToInlineImmOp32(TII, Src, ModifiedImm&: ModImm, /*Scalar=*/false);
900 if (ModOpcode != 0) {
901 MI.setDesc(TII->get(Opcode: ModOpcode));
902 Src.setImm(static_cast<int64_t>(ModImm));
903 Changed = true;
904 continue;
905 }
906 }
907 }
908
909 if (ST->hasSwap() && (MI.getOpcode() == AMDGPU::V_MOV_B32_e32 ||
910 MI.getOpcode() == AMDGPU::V_MOV_B16_t16_e32 ||
911 MI.getOpcode() == AMDGPU::COPY)) {
912 if (auto *NextMI = matchSwap(MovT&: MI)) {
913 Next = NextMI->getIterator();
914 Changed = true;
915 continue;
916 }
917 }
918
919 // Shrink scalar logic operations.
920 if (MI.getOpcode() == AMDGPU::S_AND_B32 ||
921 MI.getOpcode() == AMDGPU::S_OR_B32 ||
922 MI.getOpcode() == AMDGPU::S_XOR_B32) {
923 ChangeKind CK = shrinkScalarLogicOp(MI);
924 if (CK == ChangeKind::UpdateHint)
925 continue;
926 Changed |= (CK == ChangeKind::UpdateInst);
927 }
928
929 // Try to use S_ADDK_I32 and S_MULK_I32.
930 if (MI.getOpcode() == AMDGPU::S_ADD_I32 ||
931 MI.getOpcode() == AMDGPU::S_MUL_I32 ||
932 (MI.getOpcode() == AMDGPU::S_OR_B32 &&
933 MI.getFlag(Flag: MachineInstr::MIFlag::Disjoint))) {
934 const MachineOperand *Dest = &MI.getOperand(i: 0);
935 MachineOperand *Src0 = &MI.getOperand(i: 1);
936 MachineOperand *Src1 = &MI.getOperand(i: 2);
937
938 if (!Src0->isReg() && Src1->isReg()) {
939 if (TII->commuteInstruction(MI, NewMI: false, OpIdx1: 1, OpIdx2: 2)) {
940 std::swap(a&: Src0, b&: Src1);
941 Changed = true;
942 }
943 }
944
945 // FIXME: This could work better if hints worked with subregisters. If
946 // we have a vector add of a constant, we usually don't get the correct
947 // allocation due to the subregister usage.
948 if (Dest->getReg().isVirtual() && Src0->isReg()) {
949 MRI->setRegAllocationHint(VReg: Dest->getReg(), Type: 0, PrefReg: Src0->getReg());
950 MRI->setRegAllocationHint(VReg: Src0->getReg(), Type: 0, PrefReg: Dest->getReg());
951 continue;
952 }
953 if (Src0->isReg() && Src0->getReg() == Dest->getReg()) {
954 if (Src1->isImm() && isKImmOperand(Src: *Src1)) {
955 unsigned Opc = (MI.getOpcode() == AMDGPU::S_MUL_I32)
956 ? AMDGPU::S_MULK_I32
957 : AMDGPU::S_ADDK_I32;
958 Src1->setImm(SignExtend64(X: Src1->getImm(), B: 32));
959 MI.setDesc(TII->get(Opcode: Opc));
960 MI.tieOperands(DefIdx: 0, UseIdx: 1);
961 Changed = true;
962 }
963 }
964 }
965
966 // Try to use s_cmpk_*
967 if (MI.isCompare() && TII->isSOPC(MI)) {
968 Changed |= shrinkScalarCompare(MI);
969 continue;
970 }
971
972 // Try to use S_MOVK_I32, which will save 4 bytes for small immediates.
973 if (MI.getOpcode() == AMDGPU::S_MOV_B32) {
974 const MachineOperand &Dst = MI.getOperand(i: 0);
975 MachineOperand &Src = MI.getOperand(i: 1);
976
977 if (Src.isImm() && Dst.getReg().isPhysical()) {
978 unsigned ModOpc;
979 int32_t ModImm;
980 if (isKImmOperand(Src)) {
981 MI.setDesc(TII->get(Opcode: AMDGPU::S_MOVK_I32));
982 Src.setImm(SignExtend64(X: Src.getImm(), B: 32));
983 Changed = true;
984 } else if ((ModOpc = canModifyToInlineImmOp32(TII, Src, ModifiedImm&: ModImm,
985 /*Scalar=*/true))) {
986 MI.setDesc(TII->get(Opcode: ModOpc));
987 Src.setImm(static_cast<int64_t>(ModImm));
988 Changed = true;
989 }
990 }
991
992 continue;
993 }
994
995 if (IsPostRA && TII->isMIMG(Opcode: MI.getOpcode()) &&
996 ST->getGeneration() >= AMDGPUSubtarget::GFX10) {
997 Changed |= shrinkMIMG(MI);
998 continue;
999 }
1000
1001 if (!TII->isVOP3(MI))
1002 continue;
1003
1004 if (MI.getOpcode() == AMDGPU::V_MAD_F32_e64 ||
1005 MI.getOpcode() == AMDGPU::V_FMA_F32_e64 ||
1006 MI.getOpcode() == AMDGPU::V_MAD_F16_e64 ||
1007 MI.getOpcode() == AMDGPU::V_FMA_F16_e64 ||
1008 MI.getOpcode() == AMDGPU::V_FMA_F16_gfx9_e64 ||
1009 MI.getOpcode() == AMDGPU::V_FMA_F16_gfx9_t16_e64 ||
1010 MI.getOpcode() == AMDGPU::V_FMA_F16_gfx9_fake16_e64 ||
1011 (MI.getOpcode() == AMDGPU::V_FMA_F64_e64 &&
1012 ST->hasFmaakFmamkF64Insts())) {
1013 Changed |= shrinkMadFma(MI);
1014 continue;
1015 }
1016
1017 // If there is no chance we will shrink it and use VCC as sdst to get
1018 // a 32 bit form try to replace dead sdst with NULL.
1019 if (TII->isVOP3(Opcode: MI.getOpcode())) {
1020 Changed |= tryReplaceDeadSDST(MI);
1021 if (!TII->hasVALU32BitEncoding(Opcode: MI.getOpcode())) {
1022 continue;
1023 }
1024 }
1025
1026 if (!TII->canShrink(MI, MRI: *MRI)) {
1027 // Try commuting the instruction and see if that enables us to shrink
1028 // it.
1029 if (!MI.isCommutable() || !TII->commuteInstruction(MI) ||
1030 !TII->canShrink(MI, MRI: *MRI)) {
1031 Changed |= tryReplaceDeadSDST(MI);
1032 continue;
1033 }
1034
1035 // Operands were commuted.
1036 Changed = true;
1037 }
1038
1039 int Op32 = AMDGPU::getVOPe32(Opcode: MI.getOpcode());
1040
1041 if (Op32 == AMDGPU::V_CNDMASK_B32_e32) {
1042 // We shrink V_CNDMASK_B32_e64 using regalloc hints like we do for VOPC
1043 // instructions.
1044 const MachineOperand *Src2 =
1045 TII->getNamedOperand(MI, OperandName: AMDGPU::OpName::src2);
1046 if (!Src2->isReg())
1047 continue;
1048 Register SReg = Src2->getReg();
1049 if (SReg.isVirtual()) {
1050 MRI->setRegAllocationHint(VReg: SReg, Type: 0, PrefReg: VCCReg);
1051 continue;
1052 }
1053 if (SReg != VCCReg)
1054 continue;
1055 }
1056
1057 // Check for the bool flag output for instructions like V_ADD_I32_e64.
1058 // For VOPC e64 this is also the dst operand. VOPCX (nosdst) variants
1059 // have no sdst, so they fall through to be shrunk directly.
1060 const MachineOperand *SDst =
1061 TII->getNamedOperand(MI, OperandName: AMDGPU::OpName::sdst);
1062
1063 if (SDst) {
1064 bool Next = false;
1065
1066 if (SDst->getReg() != VCCReg) {
1067 // VOPC instructions can only write to the VCC register. We can't
1068 // force them to use VCC here, because this is only one register and
1069 // cannot deal with sequences which would require multiple copies of
1070 // VCC, e.g. S_AND_B64 (vcc = V_CMP_...), (vcc = V_CMP_...)
1071 //
1072 // So, instead of forcing the instruction to write to VCC, we
1073 // provide a hint to the register allocator to use VCC and then we
1074 // will run this pass again after RA and shrink it if it outputs to
1075 // VCC.
1076 if (SDst->getReg().isVirtual())
1077 MRI->setRegAllocationHint(VReg: SDst->getReg(), Type: 0, PrefReg: VCCReg);
1078 Next = true;
1079 }
1080
1081 // All of the instructions with carry outs also have an SGPR input in
1082 // src2.
1083 const MachineOperand *Src2 = TII->getNamedOperand(MI,
1084 OperandName: AMDGPU::OpName::src2);
1085 if (Src2 && Src2->getReg() != VCCReg) {
1086 if (Src2->getReg().isVirtual())
1087 MRI->setRegAllocationHint(VReg: Src2->getReg(), Type: 0, PrefReg: VCCReg);
1088 Next = true;
1089 }
1090
1091 if (Next)
1092 continue;
1093 }
1094
1095 // Pre-GFX10, shrinking VOP3 instructions pre-RA gave us the chance to
1096 // fold an immediate into the shrunk instruction as a literal operand. In
1097 // GFX10 VOP3 instructions can take a literal operand anyway, so there is
1098 // no advantage to doing this.
1099 // However, if 64-bit literals are allowed we still need to shrink it
1100 // for such literal to be able to fold.
1101 if (ST->hasVOP3Literal() &&
1102 (!ST->has64BitLiterals() || AMDGPU::isTrue16Inst(Opc: MI.getOpcode())) &&
1103 !IsPostRA)
1104 continue;
1105
1106 if (ST->hasTrue16BitInsts() && AMDGPU::isTrue16Inst(Opc: MI.getOpcode()) &&
1107 !shouldShrinkTrue16(MI))
1108 continue;
1109
1110 // We can shrink this instruction
1111 LLVM_DEBUG(dbgs() << "Shrinking " << MI);
1112
1113 MachineInstr *Inst32 = TII->buildShrunkInst(MI, NewOpcode: Op32);
1114 ++NumInstructionsShrunk;
1115
1116 // Copy extra operands not present in the instruction definition.
1117 copyExtraImplicitOps(NewMI&: *Inst32, MI);
1118
1119 // Copy deadness from the old explicit vcc def to the new implicit def.
1120 if (SDst && SDst->isDead())
1121 Inst32->findRegisterDefOperand(Reg: VCCReg, /*TRI=*/nullptr)->setIsDead();
1122
1123 MI.eraseFromParent();
1124 foldImmediates(MI&: *Inst32);
1125
1126 LLVM_DEBUG(dbgs() << "e32 MI = " << *Inst32 << '\n');
1127 Changed = true;
1128 }
1129 }
1130 return Changed;
1131}
1132
1133bool SIShrinkInstructionsLegacy::runOnMachineFunction(MachineFunction &MF) {
1134 if (skipFunction(F: MF.getFunction()))
1135 return false;
1136
1137 return SIShrinkInstructions().run(MF);
1138}
1139
1140PreservedAnalyses
1141SIShrinkInstructionsPass::run(MachineFunction &MF,
1142 MachineFunctionAnalysisManager &) {
1143 if (MF.getFunction().hasOptNone() || !SIShrinkInstructions().run(MF))
1144 return PreservedAnalyses::all();
1145
1146 auto PA = getMachineFunctionPassPreservedAnalyses();
1147 PA.preserveSet<CFGAnalyses>();
1148 return PA;
1149}
1150