1//===-- SIShrinkInstructions.cpp - Shrink Instructions --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7/// The pass tries to use the 32-bit encoding for instructions when possible.
8//===----------------------------------------------------------------------===//
9//
10
11#include "SIShrinkInstructions.h"
12#include "AMDGPU.h"
13#include "GCNSubtarget.h"
14#include "Utils/AMDGPUBaseInfo.h"
15#include "llvm/ADT/Statistic.h"
16#include "llvm/CodeGen/MachineFunctionPass.h"
17
18#define DEBUG_TYPE "si-shrink-instructions"
19
20STATISTIC(NumInstructionsShrunk,
21 "Number of 64-bit instruction reduced to 32-bit.");
22STATISTIC(NumLiteralConstantsFolded,
23 "Number of literal constants folded into 32-bit instructions.");
24
25using namespace llvm;
26
27namespace {
28
29enum ChangeKind { None, UpdateHint, UpdateInst };
30
31class SIShrinkInstructions {
32 MachineFunction *MF;
33 MachineRegisterInfo *MRI;
34 const GCNSubtarget *ST;
35 const SIInstrInfo *TII;
36 const SIRegisterInfo *TRI;
37 bool IsPostRA;
38
39 bool foldImmediates(MachineInstr &MI, bool TryToCommute = true) const;
40 bool shouldShrinkTrue16(MachineInstr &MI) const;
41 bool isKImmOperand(const MachineInstr &MI, const MachineOperand &Src) const;
42 bool isKUImmOperand(const MachineInstr &MI, const MachineOperand &Src) const;
43 bool isKImmOrKUImmOperand(const MachineOperand &Src, bool &IsUnsigned) const;
44 void copyExtraImplicitOps(MachineInstr &NewMI, MachineInstr &MI) const;
45 bool shrinkScalarCompare(MachineInstr &MI) const;
46 bool shrinkMIMG(MachineInstr &MI) const;
47 bool shrinkMadFma(MachineInstr &MI) const;
48 ChangeKind shrinkScalarLogicOp(MachineInstr &MI) const;
49 bool tryReplaceDeadSDST(MachineInstr &MI) const;
50 bool instAccessReg(MachineInstr::filtered_const_mop_range &&R, Register Reg,
51 unsigned SubReg) const;
52 bool instReadsReg(const MachineInstr *MI, unsigned Reg,
53 unsigned SubReg) const;
54 bool instModifiesReg(const MachineInstr *MI, unsigned Reg,
55 unsigned SubReg) const;
56 TargetInstrInfo::RegSubRegPair getSubRegForIndex(Register Reg, unsigned Sub,
57 unsigned I) const;
58 void dropInstructionKeepingImpDefs(MachineInstr &MI) const;
59 MachineInstr *matchSwap(MachineInstr &MovT) const;
60
61public:
62 SIShrinkInstructions() = default;
63 bool run(MachineFunction &MF);
64};
65
66class SIShrinkInstructionsLegacy : public MachineFunctionPass {
67
68public:
69 static char ID;
70
71 SIShrinkInstructionsLegacy() : MachineFunctionPass(ID) {}
72
73 bool runOnMachineFunction(MachineFunction &MF) override;
74
75 StringRef getPassName() const override { return "SI Shrink Instructions"; }
76
77 void getAnalysisUsage(AnalysisUsage &AU) const override {
78 AU.setPreservesCFG();
79 MachineFunctionPass::getAnalysisUsage(AU);
80 }
81};
82
83} // End anonymous namespace.
84
85INITIALIZE_PASS(SIShrinkInstructionsLegacy, DEBUG_TYPE,
86 "SI Shrink Instructions", false, false)
87
88char SIShrinkInstructionsLegacy::ID = 0;
89
90FunctionPass *llvm::createSIShrinkInstructionsLegacyPass() {
91 return new SIShrinkInstructionsLegacy();
92}
93
94/// This function checks \p MI for operands defined by a move immediate
95/// instruction and then folds the literal constant into the instruction if it
96/// can. This function assumes that \p MI is a VOP1, VOP2, or VOPC instructions.
97bool SIShrinkInstructions::foldImmediates(MachineInstr &MI,
98 bool TryToCommute) const {
99 assert(TII->isVOP1(MI) || TII->isVOP2(MI) || TII->isVOPC(MI));
100
101 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode: MI.getOpcode(), Name: AMDGPU::OpName::src0);
102
103 // Try to fold Src0
104 MachineOperand &Src0 = MI.getOperand(i: Src0Idx);
105 if (Src0.isReg()) {
106 Register Reg = Src0.getReg();
107 if (Reg.isVirtual()) {
108 MachineInstr *Def = MRI->getUniqueVRegDef(Reg);
109 if (Def && Def->isMoveImmediate()) {
110 MachineOperand &MovSrc = Def->getOperand(i: 1);
111 bool ConstantFolded = false;
112
113 if (TII->isOperandLegal(MI, OpIdx: Src0Idx, MO: &MovSrc)) {
114 if (MovSrc.isImm()) {
115 Src0.ChangeToImmediate(ImmVal: MovSrc.getImm());
116 ConstantFolded = true;
117 } else if (MovSrc.isFI()) {
118 Src0.ChangeToFrameIndex(Idx: MovSrc.getIndex());
119 ConstantFolded = true;
120 } else if (MovSrc.isGlobal()) {
121 Src0.ChangeToGA(GV: MovSrc.getGlobal(), Offset: MovSrc.getOffset(),
122 TargetFlags: MovSrc.getTargetFlags());
123 ConstantFolded = true;
124 }
125 }
126
127 if (ConstantFolded) {
128 if (MRI->use_nodbg_empty(RegNo: Reg))
129 Def->eraseFromParent();
130 ++NumLiteralConstantsFolded;
131 return true;
132 }
133 }
134 }
135 }
136
137 // We have failed to fold src0, so commute the instruction and try again.
138 if (TryToCommute && MI.isCommutable()) {
139 if (TII->commuteInstruction(MI)) {
140 if (foldImmediates(MI, TryToCommute: false))
141 return true;
142
143 // Commute back.
144 TII->commuteInstruction(MI);
145 }
146 }
147
148 return false;
149}
150
151/// Do not shrink the instruction if its registers are not expressible in the
152/// shrunk encoding.
153bool SIShrinkInstructions::shouldShrinkTrue16(MachineInstr &MI) const {
154 for (unsigned I = 0, E = MI.getNumExplicitOperands(); I != E; ++I) {
155 const MachineOperand &MO = MI.getOperand(i: I);
156 if (MO.isReg()) {
157 Register Reg = MO.getReg();
158 assert(!Reg.isVirtual() && "Prior checks should ensure we only shrink "
159 "True16 Instructions post-RA");
160 if (AMDGPU::VGPR_32RegClass.contains(Reg) &&
161 !AMDGPU::VGPR_32_Lo128RegClass.contains(Reg))
162 return false;
163
164 if (AMDGPU::VGPR_16RegClass.contains(Reg) &&
165 !AMDGPU::VGPR_16_Lo128RegClass.contains(Reg))
166 return false;
167 }
168 }
169 return true;
170}
171
172bool SIShrinkInstructions::isKImmOperand(const MachineInstr &MI,
173 const MachineOperand &Src) const {
174 return isInt<16>(x: SignExtend64(X: Src.getImm(), B: 32)) &&
175 !TII->isInlineConstant(MI, OpIdx: MI.getOperandNo(I: &Src));
176}
177
178bool SIShrinkInstructions::isKUImmOperand(const MachineInstr &MI,
179 const MachineOperand &Src) const {
180 return isUInt<16>(x: Src.getImm()) &&
181 !TII->isInlineConstant(MI, OpIdx: MI.getOperandNo(I: &Src));
182}
183
184bool SIShrinkInstructions::isKImmOrKUImmOperand(const MachineOperand &Src,
185 bool &IsUnsigned) const {
186 if (isInt<16>(x: SignExtend64(X: Src.getImm(), B: 32))) {
187 IsUnsigned = false;
188 return !TII->isInlineConstant(MO: Src);
189 }
190
191 if (isUInt<16>(x: Src.getImm())) {
192 IsUnsigned = true;
193 return !TII->isInlineConstant(MO: Src);
194 }
195
196 return false;
197}
198
199/// \returns the opcode of an instruction a move immediate of the constant \p
200/// Src can be replaced with if the constant is replaced with \p ModifiedImm.
201/// i.e.
202///
203/// If the bitreverse of a constant is an inline immediate, reverse the
204/// immediate and return the bitreverse opcode.
205///
206/// If the bitwise negation of a constant is an inline immediate, reverse the
207/// immediate and return the bitwise not opcode.
208static unsigned canModifyToInlineImmOp32(const SIInstrInfo *TII,
209 const MachineOperand &Src,
210 int32_t &ModifiedImm, bool Scalar) {
211 if (TII->isInlineConstant(MO: Src))
212 return 0;
213 int32_t SrcImm = static_cast<int32_t>(Src.getImm());
214
215 if (!Scalar) {
216 // We could handle the scalar case with here, but we would need to check
217 // that SCC is not live as S_NOT_B32 clobbers it. It's probably not worth
218 // it, as the reasonable values are already covered by s_movk_i32.
219 ModifiedImm = ~SrcImm;
220 if (TII->isInlineConstant(Imm: APInt(32, ModifiedImm, true)))
221 return AMDGPU::V_NOT_B32_e32;
222 }
223
224 ModifiedImm = reverseBits<int32_t>(Val: SrcImm);
225 if (TII->isInlineConstant(Imm: APInt(32, ModifiedImm, true)))
226 return Scalar ? AMDGPU::S_BREV_B32 : AMDGPU::V_BFREV_B32_e32;
227
228 return 0;
229}
230
231/// Copy implicit register operands from specified instruction to this
232/// instruction that are not part of the instruction definition.
233void SIShrinkInstructions::copyExtraImplicitOps(MachineInstr &NewMI,
234 MachineInstr &MI) const {
235 MachineFunction &MF = *MI.getMF();
236 for (unsigned i = MI.getDesc().getNumOperands() +
237 MI.getDesc().implicit_uses().size() +
238 MI.getDesc().implicit_defs().size(),
239 e = MI.getNumOperands();
240 i != e; ++i) {
241 const MachineOperand &MO = MI.getOperand(i);
242 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
243 NewMI.addOperand(MF, Op: MO);
244 }
245}
246
247bool SIShrinkInstructions::shrinkScalarCompare(MachineInstr &MI) const {
248 if (!ST->hasSCmpK())
249 return false;
250
251 // cmpk instructions do scc = dst <cc op> imm16, so commute the instruction to
252 // get constants on the RHS.
253 bool Changed = false;
254 if (!MI.getOperand(i: 0).isReg()) {
255 if (TII->commuteInstruction(MI, NewMI: false, OpIdx1: 0, OpIdx2: 1))
256 Changed = true;
257 }
258
259 // cmpk requires src0 to be a register
260 const MachineOperand &Src0 = MI.getOperand(i: 0);
261 if (!Src0.isReg())
262 return Changed;
263
264 MachineOperand &Src1 = MI.getOperand(i: 1);
265 if (!Src1.isImm())
266 return Changed;
267
268 int SOPKOpc = AMDGPU::getSOPKOp(Opcode: MI.getOpcode());
269 if (SOPKOpc == -1)
270 return Changed;
271
272 // eq/ne is special because the imm16 can be treated as signed or unsigned,
273 // and initially selected to the unsigned versions.
274 if (SOPKOpc == AMDGPU::S_CMPK_EQ_U32 || SOPKOpc == AMDGPU::S_CMPK_LG_U32) {
275 bool HasUImm;
276 if (isKImmOrKUImmOperand(Src: Src1, IsUnsigned&: HasUImm)) {
277 if (!HasUImm) {
278 SOPKOpc = (SOPKOpc == AMDGPU::S_CMPK_EQ_U32) ?
279 AMDGPU::S_CMPK_EQ_I32 : AMDGPU::S_CMPK_LG_I32;
280 Src1.setImm(SignExtend32(X: Src1.getImm(), B: 32));
281 }
282
283 MI.setDesc(TII->get(Opcode: SOPKOpc));
284 Changed = true;
285 }
286
287 return Changed;
288 }
289
290 const MCInstrDesc &NewDesc = TII->get(Opcode: SOPKOpc);
291
292 if ((SIInstrInfo::sopkIsZext(Opcode: SOPKOpc) && isKUImmOperand(MI, Src: Src1)) ||
293 (!SIInstrInfo::sopkIsZext(Opcode: SOPKOpc) && isKImmOperand(MI, Src: Src1))) {
294 if (!SIInstrInfo::sopkIsZext(Opcode: SOPKOpc))
295 Src1.setImm(SignExtend64(X: Src1.getImm(), B: 32));
296 MI.setDesc(NewDesc);
297 Changed = true;
298 }
299 return Changed;
300}
301
302// Shrink NSA encoded instructions with contiguous VGPRs to non-NSA encoding.
303bool SIShrinkInstructions::shrinkMIMG(MachineInstr &MI) const {
304 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc: MI.getOpcode());
305 if (!Info)
306 return false;
307
308 uint8_t NewEncoding;
309 switch (Info->MIMGEncoding) {
310 case AMDGPU::MIMGEncGfx10NSA:
311 NewEncoding = AMDGPU::MIMGEncGfx10Default;
312 break;
313 case AMDGPU::MIMGEncGfx11NSA:
314 NewEncoding = AMDGPU::MIMGEncGfx11Default;
315 break;
316 default:
317 return false;
318 }
319
320 int VAddr0Idx =
321 AMDGPU::getNamedOperandIdx(Opcode: MI.getOpcode(), Name: AMDGPU::OpName::vaddr0);
322 unsigned NewAddrDwords = Info->VAddrDwords;
323 const TargetRegisterClass *RC;
324
325 if (Info->VAddrDwords == 2) {
326 RC = &AMDGPU::VReg_64RegClass;
327 } else if (Info->VAddrDwords == 3) {
328 RC = &AMDGPU::VReg_96RegClass;
329 } else if (Info->VAddrDwords == 4) {
330 RC = &AMDGPU::VReg_128RegClass;
331 } else if (Info->VAddrDwords == 5) {
332 RC = &AMDGPU::VReg_160RegClass;
333 } else if (Info->VAddrDwords == 6) {
334 RC = &AMDGPU::VReg_192RegClass;
335 } else if (Info->VAddrDwords == 7) {
336 RC = &AMDGPU::VReg_224RegClass;
337 } else if (Info->VAddrDwords == 8) {
338 RC = &AMDGPU::VReg_256RegClass;
339 } else if (Info->VAddrDwords == 9) {
340 RC = &AMDGPU::VReg_288RegClass;
341 } else if (Info->VAddrDwords == 10) {
342 RC = &AMDGPU::VReg_320RegClass;
343 } else if (Info->VAddrDwords == 11) {
344 RC = &AMDGPU::VReg_352RegClass;
345 } else if (Info->VAddrDwords == 12) {
346 RC = &AMDGPU::VReg_384RegClass;
347 } else {
348 RC = &AMDGPU::VReg_512RegClass;
349 NewAddrDwords = 16;
350 }
351
352 unsigned VgprBase = 0;
353 unsigned NextVgpr = 0;
354 bool IsUndef = true;
355 bool IsKill = NewAddrDwords == Info->VAddrDwords;
356 const unsigned NSAMaxSize = ST->getNSAMaxSize();
357 const bool IsPartialNSA = NewAddrDwords > NSAMaxSize;
358 const unsigned EndVAddr = IsPartialNSA ? NSAMaxSize : Info->VAddrOperands;
359 for (unsigned Idx = 0; Idx < EndVAddr; ++Idx) {
360 const MachineOperand &Op = MI.getOperand(i: VAddr0Idx + Idx);
361 unsigned Vgpr = TRI->getHWRegIndex(Reg: Op.getReg());
362 unsigned Dwords = TRI->getRegSizeInBits(Reg: Op.getReg(), MRI: *MRI) / 32;
363 assert(Dwords > 0 && "Un-implemented for less than 32 bit regs");
364
365 if (Idx == 0) {
366 VgprBase = Vgpr;
367 NextVgpr = Vgpr + Dwords;
368 } else if (Vgpr == NextVgpr) {
369 NextVgpr = Vgpr + Dwords;
370 } else {
371 return false;
372 }
373
374 if (!Op.isUndef())
375 IsUndef = false;
376 if (!Op.isKill())
377 IsKill = false;
378 }
379
380 if (VgprBase + NewAddrDwords > 256)
381 return false;
382
383 // Further check for implicit tied operands - this may be present if TFE is
384 // enabled
385 int TFEIdx = AMDGPU::getNamedOperandIdx(Opcode: MI.getOpcode(), Name: AMDGPU::OpName::tfe);
386 int LWEIdx = AMDGPU::getNamedOperandIdx(Opcode: MI.getOpcode(), Name: AMDGPU::OpName::lwe);
387 unsigned TFEVal = (TFEIdx == -1) ? 0 : MI.getOperand(i: TFEIdx).getImm();
388 unsigned LWEVal = (LWEIdx == -1) ? 0 : MI.getOperand(i: LWEIdx).getImm();
389 int ToUntie = -1;
390 if (TFEVal || LWEVal) {
391 // TFE/LWE is enabled so we need to deal with an implicit tied operand
392 for (unsigned i = LWEIdx + 1, e = MI.getNumOperands(); i != e; ++i) {
393 if (MI.getOperand(i).isReg() && MI.getOperand(i).isTied() &&
394 MI.getOperand(i).isImplicit()) {
395 // This is the tied operand
396 assert(
397 ToUntie == -1 &&
398 "found more than one tied implicit operand when expecting only 1");
399 ToUntie = i;
400 MI.untieRegOperand(OpIdx: ToUntie);
401 }
402 }
403 }
404
405 unsigned NewOpcode = AMDGPU::getMIMGOpcode(BaseOpcode: Info->BaseOpcode, MIMGEncoding: NewEncoding,
406 VDataDwords: Info->VDataDwords, VAddrDwords: NewAddrDwords);
407 MI.setDesc(TII->get(Opcode: NewOpcode));
408 MI.getOperand(i: VAddr0Idx).setReg(RC->getRegister(i: VgprBase));
409 MI.getOperand(i: VAddr0Idx).setIsUndef(IsUndef);
410 MI.getOperand(i: VAddr0Idx).setIsKill(IsKill);
411
412 for (unsigned i = 1; i < EndVAddr; ++i)
413 MI.removeOperand(OpNo: VAddr0Idx + 1);
414
415 if (ToUntie >= 0) {
416 MI.tieOperands(
417 DefIdx: AMDGPU::getNamedOperandIdx(Opcode: MI.getOpcode(), Name: AMDGPU::OpName::vdata),
418 UseIdx: ToUntie - (EndVAddr - 1));
419 }
420 return true;
421}
422
423// Shrink MAD to MADAK/MADMK and FMA to FMAAK/FMAMK.
424bool SIShrinkInstructions::shrinkMadFma(MachineInstr &MI) const {
425 // Pre-GFX10 VOP3 instructions like MAD/FMA cannot take a literal operand so
426 // there is no reason to try to shrink them.
427 if (!ST->hasVOP3Literal())
428 return false;
429
430 // There is no advantage to doing this pre-RA.
431 if (!IsPostRA)
432 return false;
433
434 if (TII->hasAnyModifiersSet(MI))
435 return false;
436
437 const unsigned Opcode = MI.getOpcode();
438 MachineOperand &Src0 = *TII->getNamedOperand(MI, OperandName: AMDGPU::OpName::src0);
439 MachineOperand &Src1 = *TII->getNamedOperand(MI, OperandName: AMDGPU::OpName::src1);
440 MachineOperand &Src2 = *TII->getNamedOperand(MI, OperandName: AMDGPU::OpName::src2);
441 unsigned NewOpcode = AMDGPU::INSTRUCTION_LIST_END;
442
443 bool Swap;
444
445 // Detect "Dst = VSrc * VGPR + Imm" and convert to AK form.
446 if (Src2.isImm() && !TII->isInlineConstant(MO: Src2)) {
447 if (Src1.isReg() && TRI->isVGPR(MRI: *MRI, Reg: Src1.getReg()))
448 Swap = false;
449 else if (Src0.isReg() && TRI->isVGPR(MRI: *MRI, Reg: Src0.getReg()))
450 Swap = true;
451 else
452 return false;
453
454 switch (Opcode) {
455 default:
456 llvm_unreachable("Unexpected mad/fma opcode!");
457 case AMDGPU::V_MAD_F32_e64:
458 NewOpcode = AMDGPU::V_MADAK_F32;
459 break;
460 case AMDGPU::V_FMA_F32_e64:
461 NewOpcode = AMDGPU::V_FMAAK_F32;
462 break;
463 case AMDGPU::V_MAD_F16_e64:
464 NewOpcode = AMDGPU::V_MADAK_F16;
465 break;
466 case AMDGPU::V_FMA_F16_e64:
467 case AMDGPU::V_FMA_F16_gfx9_e64:
468 NewOpcode = AMDGPU::V_FMAAK_F16;
469 break;
470 case AMDGPU::V_FMA_F16_gfx9_t16_e64:
471 NewOpcode = AMDGPU::V_FMAAK_F16_t16;
472 break;
473 case AMDGPU::V_FMA_F16_gfx9_fake16_e64:
474 NewOpcode = AMDGPU::V_FMAAK_F16_fake16;
475 break;
476 case AMDGPU::V_FMA_F64_e64:
477 if (ST->hasFmaakFmamkF64Insts())
478 NewOpcode = AMDGPU::V_FMAAK_F64;
479 break;
480 }
481 }
482
483 // Detect "Dst = VSrc * Imm + VGPR" and convert to MK form.
484 if (Src2.isReg() && TRI->isVGPR(MRI: *MRI, Reg: Src2.getReg())) {
485 if (Src1.isImm() && !TII->isInlineConstant(MO: Src1))
486 Swap = false;
487 else if (Src0.isImm() && !TII->isInlineConstant(MO: Src0))
488 Swap = true;
489 else
490 return false;
491
492 switch (Opcode) {
493 default:
494 llvm_unreachable("Unexpected mad/fma opcode!");
495 case AMDGPU::V_MAD_F32_e64:
496 NewOpcode = AMDGPU::V_MADMK_F32;
497 break;
498 case AMDGPU::V_FMA_F32_e64:
499 NewOpcode = AMDGPU::V_FMAMK_F32;
500 break;
501 case AMDGPU::V_MAD_F16_e64:
502 NewOpcode = AMDGPU::V_MADMK_F16;
503 break;
504 case AMDGPU::V_FMA_F16_e64:
505 case AMDGPU::V_FMA_F16_gfx9_e64:
506 NewOpcode = AMDGPU::V_FMAMK_F16;
507 break;
508 case AMDGPU::V_FMA_F16_gfx9_t16_e64:
509 NewOpcode = AMDGPU::V_FMAMK_F16_t16;
510 break;
511 case AMDGPU::V_FMA_F16_gfx9_fake16_e64:
512 NewOpcode = AMDGPU::V_FMAMK_F16_fake16;
513 break;
514 case AMDGPU::V_FMA_F64_e64:
515 if (ST->hasFmaakFmamkF64Insts())
516 NewOpcode = AMDGPU::V_FMAMK_F64;
517 break;
518 }
519 }
520
521 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END)
522 return false;
523
524 if (AMDGPU::isTrue16Inst(Opc: NewOpcode) && !shouldShrinkTrue16(MI))
525 return false;
526
527 if (Swap) {
528 // Swap Src0 and Src1 by building a new instruction.
529 BuildMI(BB&: *MI.getParent(), I&: MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: NewOpcode),
530 DestReg: MI.getOperand(i: 0).getReg())
531 .add(MO: Src1)
532 .add(MO: Src0)
533 .add(MO: Src2)
534 .setMIFlags(MI.getFlags());
535 MI.eraseFromParent();
536 } else {
537 TII->removeModOperands(MI);
538 MI.setDesc(TII->get(Opcode: NewOpcode));
539 }
540 return true;
541}
542
543/// Attempt to shrink AND/OR/XOR operations requiring non-inlineable literals.
544/// For AND or OR, try using S_BITSET{0,1} to clear or set bits.
545/// If the inverse of the immediate is legal, use ANDN2, ORN2 or
546/// XNOR (as a ^ b == ~(a ^ ~b)).
547/// \return ChangeKind::None if no changes were made.
548/// ChangeKind::UpdateHint if regalloc hints were updated.
549/// ChangeKind::UpdateInst if the instruction was modified.
550ChangeKind SIShrinkInstructions::shrinkScalarLogicOp(MachineInstr &MI) const {
551 unsigned Opc = MI.getOpcode();
552 const MachineOperand *Dest = &MI.getOperand(i: 0);
553 MachineOperand *Src0 = &MI.getOperand(i: 1);
554 MachineOperand *Src1 = &MI.getOperand(i: 2);
555 MachineOperand *SrcReg = Src0;
556 MachineOperand *SrcImm = Src1;
557
558 if (!SrcImm->isImm() ||
559 AMDGPU::isInlinableLiteral32(Literal: SrcImm->getImm(), HasInv2Pi: ST->hasInv2PiInlineImm()))
560 return ChangeKind::None;
561
562 uint32_t Imm = static_cast<uint32_t>(SrcImm->getImm());
563 uint32_t NewImm = 0;
564
565 if (Opc == AMDGPU::S_AND_B32) {
566 if (isPowerOf2_32(Value: ~Imm) &&
567 MI.findRegisterDefOperand(Reg: AMDGPU::SCC, /*TRI=*/nullptr)->isDead()) {
568 NewImm = llvm::countr_one(Value: Imm);
569 Opc = AMDGPU::S_BITSET0_B32;
570 } else if (AMDGPU::isInlinableLiteral32(Literal: ~Imm, HasInv2Pi: ST->hasInv2PiInlineImm())) {
571 NewImm = ~Imm;
572 Opc = AMDGPU::S_ANDN2_B32;
573 }
574 } else if (Opc == AMDGPU::S_OR_B32) {
575 if (isPowerOf2_32(Value: Imm) &&
576 MI.findRegisterDefOperand(Reg: AMDGPU::SCC, /*TRI=*/nullptr)->isDead()) {
577 NewImm = llvm::countr_zero(Val: Imm);
578 Opc = AMDGPU::S_BITSET1_B32;
579 } else if (AMDGPU::isInlinableLiteral32(Literal: ~Imm, HasInv2Pi: ST->hasInv2PiInlineImm())) {
580 NewImm = ~Imm;
581 Opc = AMDGPU::S_ORN2_B32;
582 }
583 } else if (Opc == AMDGPU::S_XOR_B32) {
584 if (AMDGPU::isInlinableLiteral32(Literal: ~Imm, HasInv2Pi: ST->hasInv2PiInlineImm())) {
585 NewImm = ~Imm;
586 Opc = AMDGPU::S_XNOR_B32;
587 }
588 } else {
589 llvm_unreachable("unexpected opcode");
590 }
591
592 if (NewImm != 0) {
593 if (Dest->getReg().isVirtual() && SrcReg->isReg()) {
594 MRI->setRegAllocationHint(VReg: Dest->getReg(), Type: 0, PrefReg: SrcReg->getReg());
595 MRI->setRegAllocationHint(VReg: SrcReg->getReg(), Type: 0, PrefReg: Dest->getReg());
596 return ChangeKind::UpdateHint;
597 }
598
599 if (SrcReg->isReg() && SrcReg->getReg() == Dest->getReg()) {
600 const bool IsUndef = SrcReg->isUndef();
601 const bool IsKill = SrcReg->isKill();
602 TII->mutateAndCleanupImplicit(MI, NewDesc: TII->get(Opcode: Opc));
603 if (Opc == AMDGPU::S_BITSET0_B32 ||
604 Opc == AMDGPU::S_BITSET1_B32) {
605 Src0->ChangeToImmediate(ImmVal: NewImm);
606 // Remove the immediate and add the tied input.
607 MI.getOperand(i: 2).ChangeToRegister(Reg: Dest->getReg(), /*IsDef*/ isDef: false,
608 /*isImp*/ false, isKill: IsKill,
609 /*isDead*/ false, isUndef: IsUndef);
610 MI.tieOperands(DefIdx: 0, UseIdx: 2);
611 } else {
612 SrcImm->setImm(NewImm);
613 }
614 return ChangeKind::UpdateInst;
615 }
616 }
617
618 return ChangeKind::None;
619}
620
621// This is the same as MachineInstr::readsRegister/modifiesRegister except
622// it takes subregs into account.
623bool SIShrinkInstructions::instAccessReg(
624 MachineInstr::filtered_const_mop_range &&R, Register Reg,
625 unsigned SubReg) const {
626 for (const MachineOperand &MO : R) {
627 if (Reg.isPhysical() && MO.getReg().isPhysical()) {
628 if (TRI->regsOverlap(RegA: Reg, RegB: MO.getReg()))
629 return true;
630 } else if (MO.getReg() == Reg && Reg.isVirtual()) {
631 LaneBitmask Overlap = TRI->getSubRegIndexLaneMask(SubIdx: SubReg) &
632 TRI->getSubRegIndexLaneMask(SubIdx: MO.getSubReg());
633 if (Overlap.any())
634 return true;
635 }
636 }
637 return false;
638}
639
640bool SIShrinkInstructions::instReadsReg(const MachineInstr *MI, unsigned Reg,
641 unsigned SubReg) const {
642 return instAccessReg(R: MI->all_uses(), Reg, SubReg);
643}
644
645bool SIShrinkInstructions::instModifiesReg(const MachineInstr *MI, unsigned Reg,
646 unsigned SubReg) const {
647 return instAccessReg(R: MI->all_defs(), Reg, SubReg);
648}
649
650TargetInstrInfo::RegSubRegPair
651SIShrinkInstructions::getSubRegForIndex(Register Reg, unsigned Sub,
652 unsigned I) const {
653 if (TRI->getRegSizeInBits(Reg, MRI: *MRI) != 32) {
654 if (Reg.isPhysical()) {
655 Reg = TRI->getSubReg(Reg, Idx: TRI->getSubRegFromChannel(Channel: I));
656 } else {
657 Sub = TRI->getSubRegFromChannel(Channel: I + TRI->getChannelFromSubReg(SubReg: Sub));
658 }
659 }
660 return TargetInstrInfo::RegSubRegPair(Reg, Sub);
661}
662
663void SIShrinkInstructions::dropInstructionKeepingImpDefs(
664 MachineInstr &MI) const {
665 for (unsigned i = MI.getDesc().getNumOperands() +
666 MI.getDesc().implicit_uses().size() +
667 MI.getDesc().implicit_defs().size(),
668 e = MI.getNumOperands();
669 i != e; ++i) {
670 const MachineOperand &Op = MI.getOperand(i);
671 if (!Op.isDef())
672 continue;
673 BuildMI(BB&: *MI.getParent(), I: MI.getIterator(), MIMD: MI.getDebugLoc(),
674 MCID: TII->get(Opcode: AMDGPU::IMPLICIT_DEF), DestReg: Op.getReg());
675 }
676
677 MI.eraseFromParent();
678}
679
680// Match:
681// mov t, x
682// mov x, y
683// mov y, t
684//
685// =>
686//
687// mov t, x (t is potentially dead and move eliminated)
688// v_swap_b32 x, y
689//
690// Returns next valid instruction pointer if was able to create v_swap_b32.
691//
692// This shall not be done too early not to prevent possible folding which may
693// remove matched moves, and this should preferably be done before RA to
694// release saved registers and also possibly after RA which can insert copies
695// too.
696//
697// This is really just a generic peephole that is not a canonical shrinking,
698// although requirements match the pass placement and it reduces code size too.
699MachineInstr *SIShrinkInstructions::matchSwap(MachineInstr &MovT) const {
700 assert(MovT.getOpcode() == AMDGPU::V_MOV_B32_e32 ||
701 MovT.getOpcode() == AMDGPU::V_MOV_B16_t16_e32 ||
702 MovT.getOpcode() == AMDGPU::COPY);
703
704 Register T = MovT.getOperand(i: 0).getReg();
705 unsigned Tsub = MovT.getOperand(i: 0).getSubReg();
706 MachineOperand &Xop = MovT.getOperand(i: 1);
707
708 if (!Xop.isReg())
709 return nullptr;
710 Register X = Xop.getReg();
711 unsigned Xsub = Xop.getSubReg();
712 Register Y;
713 unsigned Ysub;
714
715 unsigned Size = TII->getOpSize(MI: MovT, OpNo: 0);
716
717 // We can't match v_swap_b16 pre-RA, because VGPR_16_Lo128 registers
718 // are not allocatble.
719 if (Size == 2 && X.isVirtual())
720 return nullptr;
721
722 if (!TRI->isVGPR(MRI: *MRI, Reg: X))
723 return nullptr;
724
725 const unsigned SearchLimit = 16;
726 unsigned Count = 0;
727
728 MachineInstr *MovX = nullptr;
729 MachineInstr *InsertionPt = nullptr;
730 MachineInstr *MovY = nullptr;
731
732 for (auto Iter = std::next(x: MovT.getIterator()),
733 E = MovT.getParent()->instr_end();
734 Iter != E && Count < SearchLimit; ++Iter) {
735 if (Iter->isDebugInstr())
736 continue;
737 ++Count;
738
739 if (!MovX) {
740 // Search for mov x, y.
741 if ((Iter->getOpcode() == AMDGPU::V_MOV_B32_e32 ||
742 Iter->getOpcode() == AMDGPU::V_MOV_B16_t16_e32 ||
743 Iter->getOpcode() == AMDGPU::COPY) &&
744 Iter->getOperand(i: 0).getReg() == X &&
745 Iter->getOperand(i: 0).getSubReg() == Xsub &&
746 Iter->getOperand(i: 1).isReg()) {
747 MovX = &*Iter;
748 Y = MovX->getOperand(i: 1).getReg();
749 Ysub = MovX->getOperand(i: 1).getSubReg();
750 } else if (instModifiesReg(MI: &*Iter, Reg: X, SubReg: Xsub)) {
751 // Writes to x are not allowed until mov x, y has been found
752 return nullptr;
753 }
754 } else {
755 // mov x, y has been found.
756 // Search for mov y, t.
757 if ((Iter->getOpcode() == AMDGPU::V_MOV_B32_e32 ||
758 Iter->getOpcode() == AMDGPU::V_MOV_B16_t16_e32 ||
759 Iter->getOpcode() == AMDGPU::COPY) &&
760 Iter->getOperand(i: 0).getReg() == Y &&
761 Iter->getOperand(i: 0).getSubReg() == Ysub &&
762 Iter->getOperand(i: 1).isReg() && Iter->getOperand(i: 1).getReg() == T &&
763 Iter->getOperand(i: 1).getSubReg() == Tsub) {
764 MovY = &*Iter;
765 break;
766 }
767
768 // Effectively, mov x, y must be moved downward
769 // and mov y, t must be moved upward so that they can be fused into a
770 // swap. A write to y creates a barrier that prevents the two moves from
771 // being moved adjacent to each other.
772 if (instModifiesReg(MI: &*Iter, Reg: Y, SubReg: Ysub))
773 return nullptr;
774
775 // Reads or writes to x prevent mov x, y from being moved farther
776 // downward. Select this to be the insertion point.
777 if (!InsertionPt &&
778 (instReadsReg(MI: &*Iter, Reg: X, SubReg: Xsub) || instModifiesReg(MI: &*Iter, Reg: X, SubReg: Xsub))) {
779 InsertionPt = &*Iter;
780 }
781 // If the insertion point has been found, then mov y, t must be moved
782 // upward past all subsequent instructions. A read of y will block this
783 // movement.
784 if (InsertionPt) {
785 if (instReadsReg(MI: &*Iter, Reg: Y, SubReg: Ysub))
786 return nullptr;
787 }
788 }
789
790 if (instModifiesReg(MI: &*Iter, Reg: T, SubReg: Tsub))
791 return nullptr;
792 }
793 if (MovY) {
794 LLVM_DEBUG(dbgs() << "Matched v_swap:\n" << MovT << *MovX << *MovY);
795
796 MachineBasicBlock &MBB = *MovT.getParent();
797 SmallVector<MachineInstr *, 4> Swaps;
798
799 if (!InsertionPt)
800 InsertionPt = MovY;
801 if (Size == 2) {
802 auto *MIB = BuildMI(BB&: MBB, I: InsertionPt->getIterator(), MIMD: MovT.getDebugLoc(),
803 MCID: TII->get(Opcode: AMDGPU::V_SWAP_B16))
804 .addDef(RegNo: X)
805 .addDef(RegNo: Y)
806 .addReg(RegNo: Y)
807 .addReg(RegNo: X)
808 .getInstr();
809 Swaps.push_back(Elt: MIB);
810 } else {
811 assert(Size > 0 && Size % 4 == 0);
812 for (unsigned I = 0; I < Size / 4; ++I) {
813 TargetInstrInfo::RegSubRegPair X1, Y1;
814 X1 = getSubRegForIndex(Reg: X, Sub: Xsub, I);
815 Y1 = getSubRegForIndex(Reg: Y, Sub: Ysub, I);
816 auto *MIB = BuildMI(BB&: MBB, I: InsertionPt->getIterator(), MIMD: MovT.getDebugLoc(),
817 MCID: TII->get(Opcode: AMDGPU::V_SWAP_B32))
818 .addDef(RegNo: X1.Reg, Flags: {}, SubReg: X1.SubReg)
819 .addDef(RegNo: Y1.Reg, Flags: {}, SubReg: Y1.SubReg)
820 .addReg(RegNo: Y1.Reg, Flags: {}, SubReg: Y1.SubReg)
821 .addReg(RegNo: X1.Reg, Flags: {}, SubReg: X1.SubReg)
822 .getInstr();
823 Swaps.push_back(Elt: MIB);
824 }
825 }
826 // Drop implicit EXEC.
827 if (MovX->hasRegisterImplicitUseOperand(Reg: AMDGPU::EXEC)) {
828 for (MachineInstr *Swap : Swaps) {
829 Swap->removeOperand(OpNo: Swap->getNumExplicitOperands());
830 Swap->copyImplicitOps(MF&: *MBB.getParent(), MI: *MovX);
831 }
832 }
833 MovX->eraseFromParent();
834 dropInstructionKeepingImpDefs(MI&: *MovY);
835 MachineInstr *Next = &*std::next(x: MovT.getIterator());
836
837 if (T.isVirtual() && MRI->use_nodbg_empty(RegNo: T)) {
838 dropInstructionKeepingImpDefs(MI&: MovT);
839 } else {
840 Xop.setIsKill(false);
841 for (int I = MovT.getNumImplicitOperands() - 1; I >= 0; --I ) {
842 unsigned OpNo = MovT.getNumExplicitOperands() + I;
843 const MachineOperand &Op = MovT.getOperand(i: OpNo);
844 if (Op.isKill() && TRI->regsOverlap(RegA: X, RegB: Op.getReg()))
845 MovT.removeOperand(OpNo);
846 }
847 }
848
849 return Next;
850 }
851 return nullptr;
852}
853
854// If an instruction has dead sdst replace it with NULL register on gfx1030+
855bool SIShrinkInstructions::tryReplaceDeadSDST(MachineInstr &MI) const {
856 if (!ST->hasGFX10_3Insts())
857 return false;
858
859 MachineOperand *Op = TII->getNamedOperand(MI, OperandName: AMDGPU::OpName::sdst);
860 if (!Op)
861 return false;
862 Register SDstReg = Op->getReg();
863 if (SDstReg.isPhysical() || !MRI->use_nodbg_empty(RegNo: SDstReg))
864 return false;
865
866 Op->setReg(ST->isWave32() ? AMDGPU::SGPR_NULL : AMDGPU::SGPR_NULL64);
867 return true;
868}
869
870bool SIShrinkInstructions::run(MachineFunction &MF) {
871
872 this->MF = &MF;
873 MRI = &MF.getRegInfo();
874 ST = &MF.getSubtarget<GCNSubtarget>();
875 TII = ST->getInstrInfo();
876 TRI = &TII->getRegisterInfo();
877 IsPostRA = MF.getProperties().hasNoVRegs();
878
879 unsigned VCCReg = ST->isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC;
880 bool Changed = false;
881
882 for (MachineBasicBlock &MBB : MF) {
883 MachineBasicBlock::iterator I, Next;
884 for (I = MBB.begin(); I != MBB.end(); I = Next) {
885 Next = std::next(x: I);
886 MachineInstr &MI = *I;
887
888 if (MI.getOpcode() == AMDGPU::V_MOV_B32_e32) {
889 // If this has a literal constant source that is the same as the
890 // reversed bits of an inline immediate, replace with a bitreverse of
891 // that constant. This saves 4 bytes in the common case of materializing
892 // sign bits.
893
894 // Test if we are after regalloc. We only want to do this after any
895 // optimizations happen because this will confuse them.
896 MachineOperand &Src = MI.getOperand(i: 1);
897 if (Src.isImm() && IsPostRA) {
898 int32_t ModImm;
899 unsigned ModOpcode =
900 canModifyToInlineImmOp32(TII, Src, ModifiedImm&: ModImm, /*Scalar=*/false);
901 if (ModOpcode != 0) {
902 MI.setDesc(TII->get(Opcode: ModOpcode));
903 Src.setImm(static_cast<int64_t>(ModImm));
904 Changed = true;
905 continue;
906 }
907 }
908 }
909
910 if (ST->hasSwap() && (MI.getOpcode() == AMDGPU::V_MOV_B32_e32 ||
911 MI.getOpcode() == AMDGPU::V_MOV_B16_t16_e32 ||
912 MI.getOpcode() == AMDGPU::COPY)) {
913 if (auto *NextMI = matchSwap(MovT&: MI)) {
914 Next = NextMI->getIterator();
915 Changed = true;
916 continue;
917 }
918 }
919
920 // Shrink scalar logic operations.
921 if (MI.getOpcode() == AMDGPU::S_AND_B32 ||
922 MI.getOpcode() == AMDGPU::S_OR_B32 ||
923 MI.getOpcode() == AMDGPU::S_XOR_B32) {
924 ChangeKind CK = shrinkScalarLogicOp(MI);
925 if (CK == ChangeKind::UpdateHint)
926 continue;
927 Changed |= (CK == ChangeKind::UpdateInst);
928 }
929
930 // Try to use S_ADDK_I32 and S_MULK_I32.
931 if (MI.getOpcode() == AMDGPU::S_ADD_I32 ||
932 MI.getOpcode() == AMDGPU::S_MUL_I32 ||
933 (MI.getOpcode() == AMDGPU::S_OR_B32 &&
934 MI.getFlag(Flag: MachineInstr::MIFlag::Disjoint))) {
935 const MachineOperand *Dest = &MI.getOperand(i: 0);
936 MachineOperand *Src0 = &MI.getOperand(i: 1);
937 MachineOperand *Src1 = &MI.getOperand(i: 2);
938
939 if (!Src0->isReg() && Src1->isReg()) {
940 if (TII->commuteInstruction(MI, NewMI: false, OpIdx1: 1, OpIdx2: 2)) {
941 std::swap(a&: Src0, b&: Src1);
942 Changed = true;
943 }
944 }
945
946 // FIXME: This could work better if hints worked with subregisters. If
947 // we have a vector add of a constant, we usually don't get the correct
948 // allocation due to the subregister usage.
949 if (Dest->getReg().isVirtual() && Src0->isReg()) {
950 MRI->setRegAllocationHint(VReg: Dest->getReg(), Type: 0, PrefReg: Src0->getReg());
951 MRI->setRegAllocationHint(VReg: Src0->getReg(), Type: 0, PrefReg: Dest->getReg());
952 continue;
953 }
954 if (Src0->isReg() && Src0->getReg() == Dest->getReg()) {
955 if (Src1->isImm() && isKImmOperand(MI, Src: *Src1)) {
956 unsigned Opc = (MI.getOpcode() == AMDGPU::S_MUL_I32)
957 ? AMDGPU::S_MULK_I32
958 : AMDGPU::S_ADDK_I32;
959 Src1->setImm(SignExtend64(X: Src1->getImm(), B: 32));
960 MI.setDesc(TII->get(Opcode: Opc));
961 MI.tieOperands(DefIdx: 0, UseIdx: 1);
962 Changed = true;
963 }
964 }
965 }
966
967 // Try to use s_cmpk_*
968 if (MI.isCompare() && TII->isSOPC(MI)) {
969 Changed |= shrinkScalarCompare(MI);
970 continue;
971 }
972
973 // Try to use S_MOVK_I32, which will save 4 bytes for small immediates.
974 if (MI.getOpcode() == AMDGPU::S_MOV_B32) {
975 const MachineOperand &Dst = MI.getOperand(i: 0);
976 MachineOperand &Src = MI.getOperand(i: 1);
977
978 if (Src.isImm() && Dst.getReg().isPhysical()) {
979 unsigned ModOpc;
980 int32_t ModImm;
981 if (isKImmOperand(MI, Src)) {
982 MI.setDesc(TII->get(Opcode: AMDGPU::S_MOVK_I32));
983 Src.setImm(SignExtend64(X: Src.getImm(), B: 32));
984 Changed = true;
985 } else if ((ModOpc = canModifyToInlineImmOp32(TII, Src, ModifiedImm&: ModImm,
986 /*Scalar=*/true))) {
987 MI.setDesc(TII->get(Opcode: ModOpc));
988 Src.setImm(static_cast<int64_t>(ModImm));
989 Changed = true;
990 }
991 }
992
993 continue;
994 }
995
996 if (IsPostRA && TII->isMIMG(Opcode: MI.getOpcode()) &&
997 ST->getGeneration() >= AMDGPUSubtarget::GFX10) {
998 Changed |= shrinkMIMG(MI);
999 continue;
1000 }
1001
1002 if (!TII->isVOP3(MI))
1003 continue;
1004
1005 if (MI.getOpcode() == AMDGPU::V_MAD_F32_e64 ||
1006 MI.getOpcode() == AMDGPU::V_FMA_F32_e64 ||
1007 MI.getOpcode() == AMDGPU::V_MAD_F16_e64 ||
1008 MI.getOpcode() == AMDGPU::V_FMA_F16_e64 ||
1009 MI.getOpcode() == AMDGPU::V_FMA_F16_gfx9_e64 ||
1010 MI.getOpcode() == AMDGPU::V_FMA_F16_gfx9_t16_e64 ||
1011 MI.getOpcode() == AMDGPU::V_FMA_F16_gfx9_fake16_e64 ||
1012 (MI.getOpcode() == AMDGPU::V_FMA_F64_e64 &&
1013 ST->hasFmaakFmamkF64Insts())) {
1014 Changed |= shrinkMadFma(MI);
1015 continue;
1016 }
1017
1018 // If there is no chance we will shrink it and use VCC as sdst to get
1019 // a 32 bit form try to replace dead sdst with NULL.
1020 if (TII->isVOP3(Opcode: MI.getOpcode())) {
1021 Changed |= tryReplaceDeadSDST(MI);
1022 if (!TII->hasVALU32BitEncoding(Opcode: MI.getOpcode())) {
1023 continue;
1024 }
1025 }
1026
1027 if (!TII->canShrink(MI, MRI: *MRI)) {
1028 // Try commuting the instruction and see if that enables us to shrink
1029 // it.
1030 if (!MI.isCommutable() || !TII->commuteInstruction(MI) ||
1031 !TII->canShrink(MI, MRI: *MRI)) {
1032 Changed |= tryReplaceDeadSDST(MI);
1033 continue;
1034 }
1035
1036 // Operands were commuted.
1037 Changed = true;
1038 }
1039
1040 int Op32 = AMDGPU::getVOPe32(Opcode: MI.getOpcode());
1041
1042 if (Op32 == AMDGPU::V_CNDMASK_B32_e32) {
1043 // We shrink V_CNDMASK_B32_e64 using regalloc hints like we do for VOPC
1044 // instructions.
1045 const MachineOperand *Src2 =
1046 TII->getNamedOperand(MI, OperandName: AMDGPU::OpName::src2);
1047 if (!Src2->isReg())
1048 continue;
1049 Register SReg = Src2->getReg();
1050 if (SReg.isVirtual()) {
1051 MRI->setRegAllocationHint(VReg: SReg, Type: 0, PrefReg: VCCReg);
1052 continue;
1053 }
1054 if (SReg != VCCReg)
1055 continue;
1056 }
1057
1058 // Check for the bool flag output for instructions like V_ADD_I32_e64.
1059 // For VOPC e64 this is also the dst operand. VOPCX (nosdst) variants
1060 // have no sdst, so they fall through to be shrunk directly.
1061 const MachineOperand *SDst =
1062 TII->getNamedOperand(MI, OperandName: AMDGPU::OpName::sdst);
1063
1064 if (SDst) {
1065 bool Next = false;
1066
1067 if (SDst->getReg() != VCCReg) {
1068 // VOPC instructions can only write to the VCC register. We can't
1069 // force them to use VCC here, because this is only one register and
1070 // cannot deal with sequences which would require multiple copies of
1071 // VCC, e.g. S_AND_B64 (vcc = V_CMP_...), (vcc = V_CMP_...)
1072 //
1073 // So, instead of forcing the instruction to write to VCC, we
1074 // provide a hint to the register allocator to use VCC and then we
1075 // will run this pass again after RA and shrink it if it outputs to
1076 // VCC.
1077 if (SDst->getReg().isVirtual())
1078 MRI->setRegAllocationHint(VReg: SDst->getReg(), Type: 0, PrefReg: VCCReg);
1079 Next = true;
1080 }
1081
1082 // All of the instructions with carry outs also have an SGPR input in
1083 // src2.
1084 const MachineOperand *Src2 = TII->getNamedOperand(MI,
1085 OperandName: AMDGPU::OpName::src2);
1086 if (Src2 && Src2->getReg() != VCCReg) {
1087 if (Src2->getReg().isVirtual())
1088 MRI->setRegAllocationHint(VReg: Src2->getReg(), Type: 0, PrefReg: VCCReg);
1089 Next = true;
1090 }
1091
1092 if (Next)
1093 continue;
1094 }
1095
1096 // Pre-GFX10, shrinking VOP3 instructions pre-RA gave us the chance to
1097 // fold an immediate into the shrunk instruction as a literal operand. In
1098 // GFX10 VOP3 instructions can take a literal operand anyway, so there is
1099 // no advantage to doing this.
1100 // However, if 64-bit literals are allowed we still need to shrink it
1101 // for such literal to be able to fold.
1102 if (ST->hasVOP3Literal() &&
1103 (!ST->has64BitLiterals() || AMDGPU::isTrue16Inst(Opc: MI.getOpcode())) &&
1104 !IsPostRA)
1105 continue;
1106
1107 if (ST->hasTrue16BitInsts() && AMDGPU::isTrue16Inst(Opc: MI.getOpcode()) &&
1108 !shouldShrinkTrue16(MI))
1109 continue;
1110
1111 // We can shrink this instruction
1112 LLVM_DEBUG(dbgs() << "Shrinking " << MI);
1113
1114 MachineInstr *Inst32 = TII->buildShrunkInst(MI, NewOpcode: Op32);
1115 ++NumInstructionsShrunk;
1116
1117 // Copy extra operands not present in the instruction definition.
1118 copyExtraImplicitOps(NewMI&: *Inst32, MI);
1119
1120 // Copy deadness from the old explicit vcc def to the new implicit def.
1121 if (SDst && SDst->isDead())
1122 Inst32->findRegisterDefOperand(Reg: VCCReg, /*TRI=*/nullptr)->setIsDead();
1123
1124 MI.eraseFromParent();
1125 foldImmediates(MI&: *Inst32);
1126
1127 LLVM_DEBUG(dbgs() << "e32 MI = " << *Inst32 << '\n');
1128 Changed = true;
1129 }
1130 }
1131 return Changed;
1132}
1133
1134bool SIShrinkInstructionsLegacy::runOnMachineFunction(MachineFunction &MF) {
1135 if (skipFunction(F: MF.getFunction()))
1136 return false;
1137
1138 return SIShrinkInstructions().run(MF);
1139}
1140
1141PreservedAnalyses
1142SIShrinkInstructionsPass::run(MachineFunction &MF,
1143 MachineFunctionAnalysisManager &) {
1144 if (MF.getFunction().hasOptNone() || !SIShrinkInstructions().run(MF))
1145 return PreservedAnalyses::all();
1146
1147 auto PA = getMachineFunctionPassPreservedAnalyses();
1148 PA.preserveSet<CFGAnalyses>();
1149 return PA;
1150}
1151