1//===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a pass that expands pseudo instructions into target
10// instructions to allow proper scheduling, if-conversion, and other late
11// optimizations. This pass should be run after register allocation but before
12// the post-regalloc scheduling pass.
13//
14//===----------------------------------------------------------------------===//
15
16#include "ARM.h"
17#include "ARMBaseInstrInfo.h"
18#include "ARMBaseRegisterInfo.h"
19#include "ARMConstantPoolValue.h"
20#include "ARMMachineFunctionInfo.h"
21#include "ARMSubtarget.h"
22#include "MCTargetDesc/ARMAddressingModes.h"
23#include "llvm/CodeGen/LivePhysRegs.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineFunctionPass.h"
26#include "llvm/CodeGen/MachineJumpTableInfo.h"
27#include "llvm/MC/MCAsmInfo.h"
28#include "llvm/Support/Debug.h"
29
30#include <atomic>
31
32using namespace llvm;
33
34#define DEBUG_TYPE "arm-pseudo"
35
36static cl::opt<bool>
37VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
38 cl::desc("Verify machine code after expanding ARM pseudos"));
39
40#define ARM_EXPAND_PSEUDO_NAME "ARM pseudo instruction expansion pass"
41
42namespace {
43 class ARMExpandPseudo : public MachineFunctionPass {
44 public:
45 static char ID;
46 ARMExpandPseudo() : MachineFunctionPass(ID) {}
47
48 const ARMBaseInstrInfo *TII;
49 const TargetRegisterInfo *TRI;
50 const ARMSubtarget *STI;
51 ARMFunctionInfo *AFI;
52
53 bool runOnMachineFunction(MachineFunction &Fn) override;
54
55 MachineFunctionProperties getRequiredProperties() const override {
56 return MachineFunctionProperties().setNoVRegs();
57 }
58
59 StringRef getPassName() const override {
60 return ARM_EXPAND_PSEUDO_NAME;
61 }
62
63 private:
64 bool ExpandMI(MachineBasicBlock &MBB,
65 MachineBasicBlock::iterator MBBI,
66 MachineBasicBlock::iterator &NextMBBI);
67 bool ExpandMBB(MachineBasicBlock &MBB);
68 void ExpandVLD(MachineBasicBlock::iterator &MBBI);
69 void ExpandVST(MachineBasicBlock::iterator &MBBI);
70 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
71 void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
72 unsigned Opc, bool IsExt);
73 void ExpandMQQPRLoadStore(MachineBasicBlock::iterator &MBBI);
74 void ExpandTMOV32BitImm(MachineBasicBlock &MBB,
75 MachineBasicBlock::iterator &MBBI);
76 void ExpandMOV32BitImm(MachineBasicBlock &MBB,
77 MachineBasicBlock::iterator &MBBI);
78 void CMSEClearGPRegs(MachineBasicBlock &MBB,
79 MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
80 const SmallVectorImpl<unsigned> &ClearRegs,
81 unsigned ClobberReg);
82 MachineBasicBlock &CMSEClearFPRegs(MachineBasicBlock &MBB,
83 MachineBasicBlock::iterator MBBI);
84 MachineBasicBlock &CMSEClearFPRegsV8(MachineBasicBlock &MBB,
85 MachineBasicBlock::iterator MBBI,
86 const BitVector &ClearRegs);
87 MachineBasicBlock &CMSEClearFPRegsV81(MachineBasicBlock &MBB,
88 MachineBasicBlock::iterator MBBI,
89 const BitVector &ClearRegs);
90 void CMSESaveClearFPRegs(MachineBasicBlock &MBB,
91 MachineBasicBlock::iterator MBBI, DebugLoc &DL,
92 const LivePhysRegs &LiveRegs,
93 SmallVectorImpl<unsigned> &AvailableRegs);
94 void CMSESaveClearFPRegsV8(MachineBasicBlock &MBB,
95 MachineBasicBlock::iterator MBBI, DebugLoc &DL,
96 const LivePhysRegs &LiveRegs,
97 SmallVectorImpl<unsigned> &ScratchRegs);
98 void CMSESaveClearFPRegsV81(MachineBasicBlock &MBB,
99 MachineBasicBlock::iterator MBBI, DebugLoc &DL,
100 const LivePhysRegs &LiveRegs);
101 void CMSERestoreFPRegs(MachineBasicBlock &MBB,
102 MachineBasicBlock::iterator MBBI, DebugLoc &DL,
103 SmallVectorImpl<unsigned> &AvailableRegs);
104 void CMSERestoreFPRegsV8(MachineBasicBlock &MBB,
105 MachineBasicBlock::iterator MBBI, DebugLoc &DL,
106 SmallVectorImpl<unsigned> &AvailableRegs);
107 void CMSERestoreFPRegsV81(MachineBasicBlock &MBB,
108 MachineBasicBlock::iterator MBBI, DebugLoc &DL,
109 SmallVectorImpl<unsigned> &AvailableRegs);
110 bool ExpandCMP_SWAP(MachineBasicBlock &MBB,
111 MachineBasicBlock::iterator MBBI, unsigned LdrexOp,
112 unsigned StrexOp, unsigned UxtOp,
113 MachineBasicBlock::iterator &NextMBBI);
114
115 bool ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
116 MachineBasicBlock::iterator MBBI,
117 MachineBasicBlock::iterator &NextMBBI);
118 };
119 char ARMExpandPseudo::ID = 0;
120}
121
122INITIALIZE_PASS(ARMExpandPseudo, DEBUG_TYPE, ARM_EXPAND_PSEUDO_NAME, false,
123 false)
124
125namespace {
126 // Constants for register spacing in NEON load/store instructions.
127 // For quad-register load-lane and store-lane pseudo instructors, the
128 // spacing is initially assumed to be EvenDblSpc, and that is changed to
129 // OddDblSpc depending on the lane number operand.
130 enum NEONRegSpacing {
131 SingleSpc,
132 SingleLowSpc , // Single spacing, low registers, three and four vectors.
133 SingleHighQSpc, // Single spacing, high registers, four vectors.
134 SingleHighTSpc, // Single spacing, high registers, three vectors.
135 EvenDblSpc,
136 OddDblSpc
137 };
138
139 // Entries for NEON load/store information table. The table is sorted by
140 // PseudoOpc for fast binary-search lookups.
141 struct NEONLdStTableEntry {
142 uint16_t PseudoOpc;
143 uint16_t RealOpc;
144 bool IsLoad;
145 bool isUpdating;
146 bool hasWritebackOperand;
147 uint8_t RegSpacing; // One of type NEONRegSpacing
148 uint8_t NumRegs; // D registers loaded or stored
149 uint8_t RegElts; // elements per D register; used for lane ops
150 // FIXME: Temporary flag to denote whether the real instruction takes
151 // a single register (like the encoding) or all of the registers in
152 // the list (like the asm syntax and the isel DAG). When all definitions
153 // are converted to take only the single encoded register, this will
154 // go away.
155 bool copyAllListRegs;
156
157 // Comparison methods for binary search of the table.
158 bool operator<(const NEONLdStTableEntry &TE) const {
159 return PseudoOpc < TE.PseudoOpc;
160 }
161 friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) {
162 return TE.PseudoOpc < PseudoOpc;
163 }
164 [[maybe_unused]] friend bool operator<(unsigned PseudoOpc,
165 const NEONLdStTableEntry &TE) {
166 return PseudoOpc < TE.PseudoOpc;
167 }
168 };
169}
170
171static const NEONLdStTableEntry NEONLdStTable[] = {
172{ .PseudoOpc: ARM::VLD1LNq16Pseudo, .RealOpc: ARM::VLD1LNd16, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: EvenDblSpc, .NumRegs: 1, .RegElts: 4 ,.copyAllListRegs: true},
173{ .PseudoOpc: ARM::VLD1LNq16Pseudo_UPD, .RealOpc: ARM::VLD1LNd16_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: EvenDblSpc, .NumRegs: 1, .RegElts: 4 ,.copyAllListRegs: true},
174{ .PseudoOpc: ARM::VLD1LNq32Pseudo, .RealOpc: ARM::VLD1LNd32, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: EvenDblSpc, .NumRegs: 1, .RegElts: 2 ,.copyAllListRegs: true},
175{ .PseudoOpc: ARM::VLD1LNq32Pseudo_UPD, .RealOpc: ARM::VLD1LNd32_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: EvenDblSpc, .NumRegs: 1, .RegElts: 2 ,.copyAllListRegs: true},
176{ .PseudoOpc: ARM::VLD1LNq8Pseudo, .RealOpc: ARM::VLD1LNd8, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: EvenDblSpc, .NumRegs: 1, .RegElts: 8 ,.copyAllListRegs: true},
177{ .PseudoOpc: ARM::VLD1LNq8Pseudo_UPD, .RealOpc: ARM::VLD1LNd8_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: EvenDblSpc, .NumRegs: 1, .RegElts: 8 ,.copyAllListRegs: true},
178
179{ .PseudoOpc: ARM::VLD1d16QPseudo, .RealOpc: ARM::VLD1d16Q, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: false},
180{ .PseudoOpc: ARM::VLD1d16QPseudoWB_fixed, .RealOpc: ARM::VLD1d16Qwb_fixed, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: false},
181{ .PseudoOpc: ARM::VLD1d16QPseudoWB_register, .RealOpc: ARM::VLD1d16Qwb_register, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: false},
182{ .PseudoOpc: ARM::VLD1d16TPseudo, .RealOpc: ARM::VLD1d16T, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 4 ,.copyAllListRegs: false},
183{ .PseudoOpc: ARM::VLD1d16TPseudoWB_fixed, .RealOpc: ARM::VLD1d16Twb_fixed, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 4 ,.copyAllListRegs: false},
184{ .PseudoOpc: ARM::VLD1d16TPseudoWB_register, .RealOpc: ARM::VLD1d16Twb_register, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 4 ,.copyAllListRegs: false},
185
186{ .PseudoOpc: ARM::VLD1d32QPseudo, .RealOpc: ARM::VLD1d32Q, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: false},
187{ .PseudoOpc: ARM::VLD1d32QPseudoWB_fixed, .RealOpc: ARM::VLD1d32Qwb_fixed, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: false},
188{ .PseudoOpc: ARM::VLD1d32QPseudoWB_register, .RealOpc: ARM::VLD1d32Qwb_register, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: false},
189{ .PseudoOpc: ARM::VLD1d32TPseudo, .RealOpc: ARM::VLD1d32T, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 2 ,.copyAllListRegs: false},
190{ .PseudoOpc: ARM::VLD1d32TPseudoWB_fixed, .RealOpc: ARM::VLD1d32Twb_fixed, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 2 ,.copyAllListRegs: false},
191{ .PseudoOpc: ARM::VLD1d32TPseudoWB_register, .RealOpc: ARM::VLD1d32Twb_register, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 2 ,.copyAllListRegs: false},
192
193{ .PseudoOpc: ARM::VLD1d64QPseudo, .RealOpc: ARM::VLD1d64Q, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 1 ,.copyAllListRegs: false},
194{ .PseudoOpc: ARM::VLD1d64QPseudoWB_fixed, .RealOpc: ARM::VLD1d64Qwb_fixed, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 1 ,.copyAllListRegs: false},
195{ .PseudoOpc: ARM::VLD1d64QPseudoWB_register, .RealOpc: ARM::VLD1d64Qwb_register, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 1 ,.copyAllListRegs: false},
196{ .PseudoOpc: ARM::VLD1d64TPseudo, .RealOpc: ARM::VLD1d64T, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 1 ,.copyAllListRegs: false},
197{ .PseudoOpc: ARM::VLD1d64TPseudoWB_fixed, .RealOpc: ARM::VLD1d64Twb_fixed, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 1 ,.copyAllListRegs: false},
198{ .PseudoOpc: ARM::VLD1d64TPseudoWB_register, .RealOpc: ARM::VLD1d64Twb_register, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 1 ,.copyAllListRegs: false},
199
200{ .PseudoOpc: ARM::VLD1d8QPseudo, .RealOpc: ARM::VLD1d8Q, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: false},
201{ .PseudoOpc: ARM::VLD1d8QPseudoWB_fixed, .RealOpc: ARM::VLD1d8Qwb_fixed, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: false},
202{ .PseudoOpc: ARM::VLD1d8QPseudoWB_register, .RealOpc: ARM::VLD1d8Qwb_register, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: false},
203{ .PseudoOpc: ARM::VLD1d8TPseudo, .RealOpc: ARM::VLD1d8T, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 8 ,.copyAllListRegs: false},
204{ .PseudoOpc: ARM::VLD1d8TPseudoWB_fixed, .RealOpc: ARM::VLD1d8Twb_fixed, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 8 ,.copyAllListRegs: false},
205{ .PseudoOpc: ARM::VLD1d8TPseudoWB_register, .RealOpc: ARM::VLD1d8Twb_register, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 8 ,.copyAllListRegs: false},
206
207{ .PseudoOpc: ARM::VLD1q16HighQPseudo, .RealOpc: ARM::VLD1d16Q, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleHighQSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: false},
208{ .PseudoOpc: ARM::VLD1q16HighQPseudo_UPD, .RealOpc: ARM::VLD1d16Qwb_fixed, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleHighQSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: false},
209{ .PseudoOpc: ARM::VLD1q16HighTPseudo, .RealOpc: ARM::VLD1d16T, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleHighTSpc, .NumRegs: 3, .RegElts: 4 ,.copyAllListRegs: false},
210{ .PseudoOpc: ARM::VLD1q16HighTPseudo_UPD, .RealOpc: ARM::VLD1d16Twb_fixed, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleHighTSpc, .NumRegs: 3, .RegElts: 4 ,.copyAllListRegs: false},
211{ .PseudoOpc: ARM::VLD1q16LowQPseudo_UPD, .RealOpc: ARM::VLD1d16Qwb_fixed, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleLowSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: false},
212{ .PseudoOpc: ARM::VLD1q16LowTPseudo_UPD, .RealOpc: ARM::VLD1d16Twb_fixed, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleLowSpc, .NumRegs: 3, .RegElts: 4 ,.copyAllListRegs: false},
213
214{ .PseudoOpc: ARM::VLD1q32HighQPseudo, .RealOpc: ARM::VLD1d32Q, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleHighQSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: false},
215{ .PseudoOpc: ARM::VLD1q32HighQPseudo_UPD, .RealOpc: ARM::VLD1d32Qwb_fixed, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleHighQSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: false},
216{ .PseudoOpc: ARM::VLD1q32HighTPseudo, .RealOpc: ARM::VLD1d32T, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleHighTSpc, .NumRegs: 3, .RegElts: 2 ,.copyAllListRegs: false},
217{ .PseudoOpc: ARM::VLD1q32HighTPseudo_UPD, .RealOpc: ARM::VLD1d32Twb_fixed, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleHighTSpc, .NumRegs: 3, .RegElts: 2 ,.copyAllListRegs: false},
218{ .PseudoOpc: ARM::VLD1q32LowQPseudo_UPD, .RealOpc: ARM::VLD1d32Qwb_fixed, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleLowSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: false},
219{ .PseudoOpc: ARM::VLD1q32LowTPseudo_UPD, .RealOpc: ARM::VLD1d32Twb_fixed, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleLowSpc, .NumRegs: 3, .RegElts: 2 ,.copyAllListRegs: false},
220
221{ .PseudoOpc: ARM::VLD1q64HighQPseudo, .RealOpc: ARM::VLD1d64Q, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleHighQSpc, .NumRegs: 4, .RegElts: 1 ,.copyAllListRegs: false},
222{ .PseudoOpc: ARM::VLD1q64HighQPseudo_UPD, .RealOpc: ARM::VLD1d64Qwb_fixed, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleHighQSpc, .NumRegs: 4, .RegElts: 1 ,.copyAllListRegs: false},
223{ .PseudoOpc: ARM::VLD1q64HighTPseudo, .RealOpc: ARM::VLD1d64T, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleHighTSpc, .NumRegs: 3, .RegElts: 1 ,.copyAllListRegs: false},
224{ .PseudoOpc: ARM::VLD1q64HighTPseudo_UPD, .RealOpc: ARM::VLD1d64Twb_fixed, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleHighTSpc, .NumRegs: 3, .RegElts: 1 ,.copyAllListRegs: false},
225{ .PseudoOpc: ARM::VLD1q64LowQPseudo_UPD, .RealOpc: ARM::VLD1d64Qwb_fixed, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleLowSpc, .NumRegs: 4, .RegElts: 1 ,.copyAllListRegs: false},
226{ .PseudoOpc: ARM::VLD1q64LowTPseudo_UPD, .RealOpc: ARM::VLD1d64Twb_fixed, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleLowSpc, .NumRegs: 3, .RegElts: 1 ,.copyAllListRegs: false},
227
228{ .PseudoOpc: ARM::VLD1q8HighQPseudo, .RealOpc: ARM::VLD1d8Q, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleHighQSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: false},
229{ .PseudoOpc: ARM::VLD1q8HighQPseudo_UPD, .RealOpc: ARM::VLD1d8Qwb_fixed, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleHighQSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: false},
230{ .PseudoOpc: ARM::VLD1q8HighTPseudo, .RealOpc: ARM::VLD1d8T, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleHighTSpc, .NumRegs: 3, .RegElts: 8 ,.copyAllListRegs: false},
231{ .PseudoOpc: ARM::VLD1q8HighTPseudo_UPD, .RealOpc: ARM::VLD1d8Twb_fixed, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleHighTSpc, .NumRegs: 3, .RegElts: 8 ,.copyAllListRegs: false},
232{ .PseudoOpc: ARM::VLD1q8LowQPseudo_UPD, .RealOpc: ARM::VLD1d8Qwb_fixed, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleLowSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: false},
233{ .PseudoOpc: ARM::VLD1q8LowTPseudo_UPD, .RealOpc: ARM::VLD1d8Twb_fixed, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleLowSpc, .NumRegs: 3, .RegElts: 8 ,.copyAllListRegs: false},
234
235{ .PseudoOpc: ARM::VLD2DUPq16EvenPseudo, .RealOpc: ARM::VLD2DUPd16x2, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: EvenDblSpc, .NumRegs: 2, .RegElts: 4 ,.copyAllListRegs: false},
236{ .PseudoOpc: ARM::VLD2DUPq16OddPseudo, .RealOpc: ARM::VLD2DUPd16x2, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: OddDblSpc, .NumRegs: 2, .RegElts: 4 ,.copyAllListRegs: false},
237{ .PseudoOpc: ARM::VLD2DUPq16OddPseudoWB_fixed, .RealOpc: ARM::VLD2DUPd16x2wb_fixed, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: false, .RegSpacing: OddDblSpc, .NumRegs: 2, .RegElts: 4 ,.copyAllListRegs: false},
238{ .PseudoOpc: ARM::VLD2DUPq16OddPseudoWB_register, .RealOpc: ARM::VLD2DUPd16x2wb_register, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: OddDblSpc, .NumRegs: 2, .RegElts: 4 ,.copyAllListRegs: false},
239{ .PseudoOpc: ARM::VLD2DUPq32EvenPseudo, .RealOpc: ARM::VLD2DUPd32x2, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: EvenDblSpc, .NumRegs: 2, .RegElts: 2 ,.copyAllListRegs: false},
240{ .PseudoOpc: ARM::VLD2DUPq32OddPseudo, .RealOpc: ARM::VLD2DUPd32x2, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: OddDblSpc, .NumRegs: 2, .RegElts: 2 ,.copyAllListRegs: false},
241{ .PseudoOpc: ARM::VLD2DUPq32OddPseudoWB_fixed, .RealOpc: ARM::VLD2DUPd32x2wb_fixed, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: false, .RegSpacing: OddDblSpc, .NumRegs: 2, .RegElts: 2 ,.copyAllListRegs: false},
242{ .PseudoOpc: ARM::VLD2DUPq32OddPseudoWB_register, .RealOpc: ARM::VLD2DUPd32x2wb_register, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: OddDblSpc, .NumRegs: 2, .RegElts: 2 ,.copyAllListRegs: false},
243{ .PseudoOpc: ARM::VLD2DUPq8EvenPseudo, .RealOpc: ARM::VLD2DUPd8x2, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: EvenDblSpc, .NumRegs: 2, .RegElts: 8 ,.copyAllListRegs: false},
244{ .PseudoOpc: ARM::VLD2DUPq8OddPseudo, .RealOpc: ARM::VLD2DUPd8x2, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: OddDblSpc, .NumRegs: 2, .RegElts: 8 ,.copyAllListRegs: false},
245{ .PseudoOpc: ARM::VLD2DUPq8OddPseudoWB_fixed, .RealOpc: ARM::VLD2DUPd8x2wb_fixed, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: false, .RegSpacing: OddDblSpc, .NumRegs: 2, .RegElts: 8 ,.copyAllListRegs: false},
246{ .PseudoOpc: ARM::VLD2DUPq8OddPseudoWB_register, .RealOpc: ARM::VLD2DUPd8x2wb_register, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: OddDblSpc, .NumRegs: 2, .RegElts: 8 ,.copyAllListRegs: false},
247
248{ .PseudoOpc: ARM::VLD2LNd16Pseudo, .RealOpc: ARM::VLD2LNd16, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 2, .RegElts: 4 ,.copyAllListRegs: true},
249{ .PseudoOpc: ARM::VLD2LNd16Pseudo_UPD, .RealOpc: ARM::VLD2LNd16_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 2, .RegElts: 4 ,.copyAllListRegs: true},
250{ .PseudoOpc: ARM::VLD2LNd32Pseudo, .RealOpc: ARM::VLD2LNd32, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 2, .RegElts: 2 ,.copyAllListRegs: true},
251{ .PseudoOpc: ARM::VLD2LNd32Pseudo_UPD, .RealOpc: ARM::VLD2LNd32_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 2, .RegElts: 2 ,.copyAllListRegs: true},
252{ .PseudoOpc: ARM::VLD2LNd8Pseudo, .RealOpc: ARM::VLD2LNd8, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 2, .RegElts: 8 ,.copyAllListRegs: true},
253{ .PseudoOpc: ARM::VLD2LNd8Pseudo_UPD, .RealOpc: ARM::VLD2LNd8_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 2, .RegElts: 8 ,.copyAllListRegs: true},
254{ .PseudoOpc: ARM::VLD2LNq16Pseudo, .RealOpc: ARM::VLD2LNq16, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: EvenDblSpc, .NumRegs: 2, .RegElts: 4 ,.copyAllListRegs: true},
255{ .PseudoOpc: ARM::VLD2LNq16Pseudo_UPD, .RealOpc: ARM::VLD2LNq16_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: EvenDblSpc, .NumRegs: 2, .RegElts: 4 ,.copyAllListRegs: true},
256{ .PseudoOpc: ARM::VLD2LNq32Pseudo, .RealOpc: ARM::VLD2LNq32, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: EvenDblSpc, .NumRegs: 2, .RegElts: 2 ,.copyAllListRegs: true},
257{ .PseudoOpc: ARM::VLD2LNq32Pseudo_UPD, .RealOpc: ARM::VLD2LNq32_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: EvenDblSpc, .NumRegs: 2, .RegElts: 2 ,.copyAllListRegs: true},
258
259{ .PseudoOpc: ARM::VLD2q16Pseudo, .RealOpc: ARM::VLD2q16, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: false},
260{ .PseudoOpc: ARM::VLD2q16PseudoWB_fixed, .RealOpc: ARM::VLD2q16wb_fixed, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: false},
261{ .PseudoOpc: ARM::VLD2q16PseudoWB_register, .RealOpc: ARM::VLD2q16wb_register, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: false},
262{ .PseudoOpc: ARM::VLD2q32Pseudo, .RealOpc: ARM::VLD2q32, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: false},
263{ .PseudoOpc: ARM::VLD2q32PseudoWB_fixed, .RealOpc: ARM::VLD2q32wb_fixed, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: false},
264{ .PseudoOpc: ARM::VLD2q32PseudoWB_register, .RealOpc: ARM::VLD2q32wb_register, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: false},
265{ .PseudoOpc: ARM::VLD2q8Pseudo, .RealOpc: ARM::VLD2q8, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: false},
266{ .PseudoOpc: ARM::VLD2q8PseudoWB_fixed, .RealOpc: ARM::VLD2q8wb_fixed, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: false},
267{ .PseudoOpc: ARM::VLD2q8PseudoWB_register, .RealOpc: ARM::VLD2q8wb_register, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: false},
268
269{ .PseudoOpc: ARM::VLD3DUPd16Pseudo, .RealOpc: ARM::VLD3DUPd16, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 4,.copyAllListRegs: true},
270{ .PseudoOpc: ARM::VLD3DUPd16Pseudo_UPD, .RealOpc: ARM::VLD3DUPd16_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 4,.copyAllListRegs: true},
271{ .PseudoOpc: ARM::VLD3DUPd32Pseudo, .RealOpc: ARM::VLD3DUPd32, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 2,.copyAllListRegs: true},
272{ .PseudoOpc: ARM::VLD3DUPd32Pseudo_UPD, .RealOpc: ARM::VLD3DUPd32_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 2,.copyAllListRegs: true},
273{ .PseudoOpc: ARM::VLD3DUPd8Pseudo, .RealOpc: ARM::VLD3DUPd8, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 8,.copyAllListRegs: true},
274{ .PseudoOpc: ARM::VLD3DUPd8Pseudo_UPD, .RealOpc: ARM::VLD3DUPd8_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 8,.copyAllListRegs: true},
275{ .PseudoOpc: ARM::VLD3DUPq16EvenPseudo, .RealOpc: ARM::VLD3DUPq16, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: EvenDblSpc, .NumRegs: 3, .RegElts: 4 ,.copyAllListRegs: true},
276{ .PseudoOpc: ARM::VLD3DUPq16OddPseudo, .RealOpc: ARM::VLD3DUPq16, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: OddDblSpc, .NumRegs: 3, .RegElts: 4 ,.copyAllListRegs: true},
277{ .PseudoOpc: ARM::VLD3DUPq16OddPseudo_UPD, .RealOpc: ARM::VLD3DUPq16_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: OddDblSpc, .NumRegs: 3, .RegElts: 4 ,.copyAllListRegs: true},
278{ .PseudoOpc: ARM::VLD3DUPq32EvenPseudo, .RealOpc: ARM::VLD3DUPq32, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: EvenDblSpc, .NumRegs: 3, .RegElts: 2 ,.copyAllListRegs: true},
279{ .PseudoOpc: ARM::VLD3DUPq32OddPseudo, .RealOpc: ARM::VLD3DUPq32, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: OddDblSpc, .NumRegs: 3, .RegElts: 2 ,.copyAllListRegs: true},
280{ .PseudoOpc: ARM::VLD3DUPq32OddPseudo_UPD, .RealOpc: ARM::VLD3DUPq32_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: OddDblSpc, .NumRegs: 3, .RegElts: 2 ,.copyAllListRegs: true},
281{ .PseudoOpc: ARM::VLD3DUPq8EvenPseudo, .RealOpc: ARM::VLD3DUPq8, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: EvenDblSpc, .NumRegs: 3, .RegElts: 8 ,.copyAllListRegs: true},
282{ .PseudoOpc: ARM::VLD3DUPq8OddPseudo, .RealOpc: ARM::VLD3DUPq8, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: OddDblSpc, .NumRegs: 3, .RegElts: 8 ,.copyAllListRegs: true},
283{ .PseudoOpc: ARM::VLD3DUPq8OddPseudo_UPD, .RealOpc: ARM::VLD3DUPq8_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: OddDblSpc, .NumRegs: 3, .RegElts: 8 ,.copyAllListRegs: true},
284
285{ .PseudoOpc: ARM::VLD3LNd16Pseudo, .RealOpc: ARM::VLD3LNd16, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 4 ,.copyAllListRegs: true},
286{ .PseudoOpc: ARM::VLD3LNd16Pseudo_UPD, .RealOpc: ARM::VLD3LNd16_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 4 ,.copyAllListRegs: true},
287{ .PseudoOpc: ARM::VLD3LNd32Pseudo, .RealOpc: ARM::VLD3LNd32, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 2 ,.copyAllListRegs: true},
288{ .PseudoOpc: ARM::VLD3LNd32Pseudo_UPD, .RealOpc: ARM::VLD3LNd32_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 2 ,.copyAllListRegs: true},
289{ .PseudoOpc: ARM::VLD3LNd8Pseudo, .RealOpc: ARM::VLD3LNd8, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 8 ,.copyAllListRegs: true},
290{ .PseudoOpc: ARM::VLD3LNd8Pseudo_UPD, .RealOpc: ARM::VLD3LNd8_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 8 ,.copyAllListRegs: true},
291{ .PseudoOpc: ARM::VLD3LNq16Pseudo, .RealOpc: ARM::VLD3LNq16, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: EvenDblSpc, .NumRegs: 3, .RegElts: 4 ,.copyAllListRegs: true},
292{ .PseudoOpc: ARM::VLD3LNq16Pseudo_UPD, .RealOpc: ARM::VLD3LNq16_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: EvenDblSpc, .NumRegs: 3, .RegElts: 4 ,.copyAllListRegs: true},
293{ .PseudoOpc: ARM::VLD3LNq32Pseudo, .RealOpc: ARM::VLD3LNq32, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: EvenDblSpc, .NumRegs: 3, .RegElts: 2 ,.copyAllListRegs: true},
294{ .PseudoOpc: ARM::VLD3LNq32Pseudo_UPD, .RealOpc: ARM::VLD3LNq32_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: EvenDblSpc, .NumRegs: 3, .RegElts: 2 ,.copyAllListRegs: true},
295
296{ .PseudoOpc: ARM::VLD3d16Pseudo, .RealOpc: ARM::VLD3d16, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 4 ,.copyAllListRegs: true},
297{ .PseudoOpc: ARM::VLD3d16Pseudo_UPD, .RealOpc: ARM::VLD3d16_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 4 ,.copyAllListRegs: true},
298{ .PseudoOpc: ARM::VLD3d32Pseudo, .RealOpc: ARM::VLD3d32, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 2 ,.copyAllListRegs: true},
299{ .PseudoOpc: ARM::VLD3d32Pseudo_UPD, .RealOpc: ARM::VLD3d32_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 2 ,.copyAllListRegs: true},
300{ .PseudoOpc: ARM::VLD3d8Pseudo, .RealOpc: ARM::VLD3d8, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 8 ,.copyAllListRegs: true},
301{ .PseudoOpc: ARM::VLD3d8Pseudo_UPD, .RealOpc: ARM::VLD3d8_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 8 ,.copyAllListRegs: true},
302
303{ .PseudoOpc: ARM::VLD3q16Pseudo_UPD, .RealOpc: ARM::VLD3q16_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: EvenDblSpc, .NumRegs: 3, .RegElts: 4 ,.copyAllListRegs: true},
304{ .PseudoOpc: ARM::VLD3q16oddPseudo, .RealOpc: ARM::VLD3q16, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: OddDblSpc, .NumRegs: 3, .RegElts: 4 ,.copyAllListRegs: true},
305{ .PseudoOpc: ARM::VLD3q16oddPseudo_UPD, .RealOpc: ARM::VLD3q16_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: OddDblSpc, .NumRegs: 3, .RegElts: 4 ,.copyAllListRegs: true},
306{ .PseudoOpc: ARM::VLD3q32Pseudo_UPD, .RealOpc: ARM::VLD3q32_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: EvenDblSpc, .NumRegs: 3, .RegElts: 2 ,.copyAllListRegs: true},
307{ .PseudoOpc: ARM::VLD3q32oddPseudo, .RealOpc: ARM::VLD3q32, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: OddDblSpc, .NumRegs: 3, .RegElts: 2 ,.copyAllListRegs: true},
308{ .PseudoOpc: ARM::VLD3q32oddPseudo_UPD, .RealOpc: ARM::VLD3q32_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: OddDblSpc, .NumRegs: 3, .RegElts: 2 ,.copyAllListRegs: true},
309{ .PseudoOpc: ARM::VLD3q8Pseudo_UPD, .RealOpc: ARM::VLD3q8_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: EvenDblSpc, .NumRegs: 3, .RegElts: 8 ,.copyAllListRegs: true},
310{ .PseudoOpc: ARM::VLD3q8oddPseudo, .RealOpc: ARM::VLD3q8, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: OddDblSpc, .NumRegs: 3, .RegElts: 8 ,.copyAllListRegs: true},
311{ .PseudoOpc: ARM::VLD3q8oddPseudo_UPD, .RealOpc: ARM::VLD3q8_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: OddDblSpc, .NumRegs: 3, .RegElts: 8 ,.copyAllListRegs: true},
312
313{ .PseudoOpc: ARM::VLD4DUPd16Pseudo, .RealOpc: ARM::VLD4DUPd16, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 4,.copyAllListRegs: true},
314{ .PseudoOpc: ARM::VLD4DUPd16Pseudo_UPD, .RealOpc: ARM::VLD4DUPd16_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 4,.copyAllListRegs: true},
315{ .PseudoOpc: ARM::VLD4DUPd32Pseudo, .RealOpc: ARM::VLD4DUPd32, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 2,.copyAllListRegs: true},
316{ .PseudoOpc: ARM::VLD4DUPd32Pseudo_UPD, .RealOpc: ARM::VLD4DUPd32_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 2,.copyAllListRegs: true},
317{ .PseudoOpc: ARM::VLD4DUPd8Pseudo, .RealOpc: ARM::VLD4DUPd8, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 8,.copyAllListRegs: true},
318{ .PseudoOpc: ARM::VLD4DUPd8Pseudo_UPD, .RealOpc: ARM::VLD4DUPd8_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 8,.copyAllListRegs: true},
319{ .PseudoOpc: ARM::VLD4DUPq16EvenPseudo, .RealOpc: ARM::VLD4DUPq16, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: EvenDblSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: true},
320{ .PseudoOpc: ARM::VLD4DUPq16OddPseudo, .RealOpc: ARM::VLD4DUPq16, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: OddDblSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: true},
321{ .PseudoOpc: ARM::VLD4DUPq16OddPseudo_UPD, .RealOpc: ARM::VLD4DUPq16_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: OddDblSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: true},
322{ .PseudoOpc: ARM::VLD4DUPq32EvenPseudo, .RealOpc: ARM::VLD4DUPq32, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: EvenDblSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: true},
323{ .PseudoOpc: ARM::VLD4DUPq32OddPseudo, .RealOpc: ARM::VLD4DUPq32, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: OddDblSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: true},
324{ .PseudoOpc: ARM::VLD4DUPq32OddPseudo_UPD, .RealOpc: ARM::VLD4DUPq32_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: OddDblSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: true},
325{ .PseudoOpc: ARM::VLD4DUPq8EvenPseudo, .RealOpc: ARM::VLD4DUPq8, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: EvenDblSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: true},
326{ .PseudoOpc: ARM::VLD4DUPq8OddPseudo, .RealOpc: ARM::VLD4DUPq8, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: OddDblSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: true},
327{ .PseudoOpc: ARM::VLD4DUPq8OddPseudo_UPD, .RealOpc: ARM::VLD4DUPq8_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: OddDblSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: true},
328
329{ .PseudoOpc: ARM::VLD4LNd16Pseudo, .RealOpc: ARM::VLD4LNd16, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: true},
330{ .PseudoOpc: ARM::VLD4LNd16Pseudo_UPD, .RealOpc: ARM::VLD4LNd16_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: true},
331{ .PseudoOpc: ARM::VLD4LNd32Pseudo, .RealOpc: ARM::VLD4LNd32, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: true},
332{ .PseudoOpc: ARM::VLD4LNd32Pseudo_UPD, .RealOpc: ARM::VLD4LNd32_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: true},
333{ .PseudoOpc: ARM::VLD4LNd8Pseudo, .RealOpc: ARM::VLD4LNd8, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: true},
334{ .PseudoOpc: ARM::VLD4LNd8Pseudo_UPD, .RealOpc: ARM::VLD4LNd8_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: true},
335{ .PseudoOpc: ARM::VLD4LNq16Pseudo, .RealOpc: ARM::VLD4LNq16, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: EvenDblSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: true},
336{ .PseudoOpc: ARM::VLD4LNq16Pseudo_UPD, .RealOpc: ARM::VLD4LNq16_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: EvenDblSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: true},
337{ .PseudoOpc: ARM::VLD4LNq32Pseudo, .RealOpc: ARM::VLD4LNq32, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: EvenDblSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: true},
338{ .PseudoOpc: ARM::VLD4LNq32Pseudo_UPD, .RealOpc: ARM::VLD4LNq32_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: EvenDblSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: true},
339
340{ .PseudoOpc: ARM::VLD4d16Pseudo, .RealOpc: ARM::VLD4d16, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: true},
341{ .PseudoOpc: ARM::VLD4d16Pseudo_UPD, .RealOpc: ARM::VLD4d16_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: true},
342{ .PseudoOpc: ARM::VLD4d32Pseudo, .RealOpc: ARM::VLD4d32, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: true},
343{ .PseudoOpc: ARM::VLD4d32Pseudo_UPD, .RealOpc: ARM::VLD4d32_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: true},
344{ .PseudoOpc: ARM::VLD4d8Pseudo, .RealOpc: ARM::VLD4d8, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: true},
345{ .PseudoOpc: ARM::VLD4d8Pseudo_UPD, .RealOpc: ARM::VLD4d8_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: true},
346
347{ .PseudoOpc: ARM::VLD4q16Pseudo_UPD, .RealOpc: ARM::VLD4q16_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: EvenDblSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: true},
348{ .PseudoOpc: ARM::VLD4q16oddPseudo, .RealOpc: ARM::VLD4q16, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: OddDblSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: true},
349{ .PseudoOpc: ARM::VLD4q16oddPseudo_UPD, .RealOpc: ARM::VLD4q16_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: OddDblSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: true},
350{ .PseudoOpc: ARM::VLD4q32Pseudo_UPD, .RealOpc: ARM::VLD4q32_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: EvenDblSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: true},
351{ .PseudoOpc: ARM::VLD4q32oddPseudo, .RealOpc: ARM::VLD4q32, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: OddDblSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: true},
352{ .PseudoOpc: ARM::VLD4q32oddPseudo_UPD, .RealOpc: ARM::VLD4q32_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: OddDblSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: true},
353{ .PseudoOpc: ARM::VLD4q8Pseudo_UPD, .RealOpc: ARM::VLD4q8_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: EvenDblSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: true},
354{ .PseudoOpc: ARM::VLD4q8oddPseudo, .RealOpc: ARM::VLD4q8, .IsLoad: true, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: OddDblSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: true},
355{ .PseudoOpc: ARM::VLD4q8oddPseudo_UPD, .RealOpc: ARM::VLD4q8_UPD, .IsLoad: true, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: OddDblSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: true},
356
357{ .PseudoOpc: ARM::VST1LNq16Pseudo, .RealOpc: ARM::VST1LNd16, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: EvenDblSpc, .NumRegs: 1, .RegElts: 4 ,.copyAllListRegs: true},
358{ .PseudoOpc: ARM::VST1LNq16Pseudo_UPD, .RealOpc: ARM::VST1LNd16_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: EvenDblSpc, .NumRegs: 1, .RegElts: 4 ,.copyAllListRegs: true},
359{ .PseudoOpc: ARM::VST1LNq32Pseudo, .RealOpc: ARM::VST1LNd32, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: EvenDblSpc, .NumRegs: 1, .RegElts: 2 ,.copyAllListRegs: true},
360{ .PseudoOpc: ARM::VST1LNq32Pseudo_UPD, .RealOpc: ARM::VST1LNd32_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: EvenDblSpc, .NumRegs: 1, .RegElts: 2 ,.copyAllListRegs: true},
361{ .PseudoOpc: ARM::VST1LNq8Pseudo, .RealOpc: ARM::VST1LNd8, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: EvenDblSpc, .NumRegs: 1, .RegElts: 8 ,.copyAllListRegs: true},
362{ .PseudoOpc: ARM::VST1LNq8Pseudo_UPD, .RealOpc: ARM::VST1LNd8_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: EvenDblSpc, .NumRegs: 1, .RegElts: 8 ,.copyAllListRegs: true},
363
364{ .PseudoOpc: ARM::VST1d16QPseudo, .RealOpc: ARM::VST1d16Q, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: false},
365{ .PseudoOpc: ARM::VST1d16QPseudoWB_fixed, .RealOpc: ARM::VST1d16Qwb_fixed, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: false},
366{ .PseudoOpc: ARM::VST1d16QPseudoWB_register, .RealOpc: ARM::VST1d16Qwb_register, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: false},
367{ .PseudoOpc: ARM::VST1d16TPseudo, .RealOpc: ARM::VST1d16T, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 4 ,.copyAllListRegs: false},
368{ .PseudoOpc: ARM::VST1d16TPseudoWB_fixed, .RealOpc: ARM::VST1d16Twb_fixed, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 4 ,.copyAllListRegs: false},
369{ .PseudoOpc: ARM::VST1d16TPseudoWB_register, .RealOpc: ARM::VST1d16Twb_register, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 4 ,.copyAllListRegs: false},
370
371{ .PseudoOpc: ARM::VST1d32QPseudo, .RealOpc: ARM::VST1d32Q, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: false},
372{ .PseudoOpc: ARM::VST1d32QPseudoWB_fixed, .RealOpc: ARM::VST1d32Qwb_fixed, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: false},
373{ .PseudoOpc: ARM::VST1d32QPseudoWB_register, .RealOpc: ARM::VST1d32Qwb_register, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: false},
374{ .PseudoOpc: ARM::VST1d32TPseudo, .RealOpc: ARM::VST1d32T, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 2 ,.copyAllListRegs: false},
375{ .PseudoOpc: ARM::VST1d32TPseudoWB_fixed, .RealOpc: ARM::VST1d32Twb_fixed, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 2 ,.copyAllListRegs: false},
376{ .PseudoOpc: ARM::VST1d32TPseudoWB_register, .RealOpc: ARM::VST1d32Twb_register, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 2 ,.copyAllListRegs: false},
377
378{ .PseudoOpc: ARM::VST1d64QPseudo, .RealOpc: ARM::VST1d64Q, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 1 ,.copyAllListRegs: false},
379{ .PseudoOpc: ARM::VST1d64QPseudoWB_fixed, .RealOpc: ARM::VST1d64Qwb_fixed, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 1 ,.copyAllListRegs: false},
380{ .PseudoOpc: ARM::VST1d64QPseudoWB_register, .RealOpc: ARM::VST1d64Qwb_register, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 1 ,.copyAllListRegs: false},
381{ .PseudoOpc: ARM::VST1d64TPseudo, .RealOpc: ARM::VST1d64T, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 1 ,.copyAllListRegs: false},
382{ .PseudoOpc: ARM::VST1d64TPseudoWB_fixed, .RealOpc: ARM::VST1d64Twb_fixed, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 1 ,.copyAllListRegs: false},
383{ .PseudoOpc: ARM::VST1d64TPseudoWB_register, .RealOpc: ARM::VST1d64Twb_register, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 1 ,.copyAllListRegs: false},
384
385{ .PseudoOpc: ARM::VST1d8QPseudo, .RealOpc: ARM::VST1d8Q, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: false},
386{ .PseudoOpc: ARM::VST1d8QPseudoWB_fixed, .RealOpc: ARM::VST1d8Qwb_fixed, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: false},
387{ .PseudoOpc: ARM::VST1d8QPseudoWB_register, .RealOpc: ARM::VST1d8Qwb_register, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: false},
388{ .PseudoOpc: ARM::VST1d8TPseudo, .RealOpc: ARM::VST1d8T, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 8 ,.copyAllListRegs: false},
389{ .PseudoOpc: ARM::VST1d8TPseudoWB_fixed, .RealOpc: ARM::VST1d8Twb_fixed, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 8 ,.copyAllListRegs: false},
390{ .PseudoOpc: ARM::VST1d8TPseudoWB_register, .RealOpc: ARM::VST1d8Twb_register, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 8 ,.copyAllListRegs: false},
391
392{ .PseudoOpc: ARM::VST1q16HighQPseudo, .RealOpc: ARM::VST1d16Q, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleHighQSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: false},
393{ .PseudoOpc: ARM::VST1q16HighQPseudo_UPD, .RealOpc: ARM::VST1d16Qwb_fixed, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleHighQSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: false},
394{ .PseudoOpc: ARM::VST1q16HighTPseudo, .RealOpc: ARM::VST1d16T, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleHighTSpc, .NumRegs: 3, .RegElts: 4 ,.copyAllListRegs: false},
395{ .PseudoOpc: ARM::VST1q16HighTPseudo_UPD, .RealOpc: ARM::VST1d16Twb_fixed, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleHighTSpc, .NumRegs: 3, .RegElts: 4 ,.copyAllListRegs: false},
396{ .PseudoOpc: ARM::VST1q16LowQPseudo_UPD, .RealOpc: ARM::VST1d16Qwb_fixed, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleLowSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: false},
397{ .PseudoOpc: ARM::VST1q16LowTPseudo_UPD, .RealOpc: ARM::VST1d16Twb_fixed, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleLowSpc, .NumRegs: 3, .RegElts: 4 ,.copyAllListRegs: false},
398
399{ .PseudoOpc: ARM::VST1q32HighQPseudo, .RealOpc: ARM::VST1d32Q, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleHighQSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: false},
400{ .PseudoOpc: ARM::VST1q32HighQPseudo_UPD, .RealOpc: ARM::VST1d32Qwb_fixed, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleHighQSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: false},
401{ .PseudoOpc: ARM::VST1q32HighTPseudo, .RealOpc: ARM::VST1d32T, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleHighTSpc, .NumRegs: 3, .RegElts: 2 ,.copyAllListRegs: false},
402{ .PseudoOpc: ARM::VST1q32HighTPseudo_UPD, .RealOpc: ARM::VST1d32Twb_fixed, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleHighTSpc, .NumRegs: 3, .RegElts: 2 ,.copyAllListRegs: false},
403{ .PseudoOpc: ARM::VST1q32LowQPseudo_UPD, .RealOpc: ARM::VST1d32Qwb_fixed, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleLowSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: false},
404{ .PseudoOpc: ARM::VST1q32LowTPseudo_UPD, .RealOpc: ARM::VST1d32Twb_fixed, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleLowSpc, .NumRegs: 3, .RegElts: 2 ,.copyAllListRegs: false},
405
406{ .PseudoOpc: ARM::VST1q64HighQPseudo, .RealOpc: ARM::VST1d64Q, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleHighQSpc, .NumRegs: 4, .RegElts: 1 ,.copyAllListRegs: false},
407{ .PseudoOpc: ARM::VST1q64HighQPseudo_UPD, .RealOpc: ARM::VST1d64Qwb_fixed, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleHighQSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: false},
408{ .PseudoOpc: ARM::VST1q64HighTPseudo, .RealOpc: ARM::VST1d64T, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleHighTSpc, .NumRegs: 3, .RegElts: 1 ,.copyAllListRegs: false},
409{ .PseudoOpc: ARM::VST1q64HighTPseudo_UPD, .RealOpc: ARM::VST1d64Twb_fixed, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleHighTSpc, .NumRegs: 3, .RegElts: 1 ,.copyAllListRegs: false},
410{ .PseudoOpc: ARM::VST1q64LowQPseudo_UPD, .RealOpc: ARM::VST1d64Qwb_fixed, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleLowSpc, .NumRegs: 4, .RegElts: 1 ,.copyAllListRegs: false},
411{ .PseudoOpc: ARM::VST1q64LowTPseudo_UPD, .RealOpc: ARM::VST1d64Twb_fixed, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleLowSpc, .NumRegs: 3, .RegElts: 1 ,.copyAllListRegs: false},
412
413{ .PseudoOpc: ARM::VST1q8HighQPseudo, .RealOpc: ARM::VST1d8Q, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleHighQSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: false},
414{ .PseudoOpc: ARM::VST1q8HighQPseudo_UPD, .RealOpc: ARM::VST1d8Qwb_fixed, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleHighQSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: false},
415{ .PseudoOpc: ARM::VST1q8HighTPseudo, .RealOpc: ARM::VST1d8T, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleHighTSpc, .NumRegs: 3, .RegElts: 8 ,.copyAllListRegs: false},
416{ .PseudoOpc: ARM::VST1q8HighTPseudo_UPD, .RealOpc: ARM::VST1d8Twb_fixed, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleHighTSpc, .NumRegs: 3, .RegElts: 8 ,.copyAllListRegs: false},
417{ .PseudoOpc: ARM::VST1q8LowQPseudo_UPD, .RealOpc: ARM::VST1d8Qwb_fixed, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleLowSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: false},
418{ .PseudoOpc: ARM::VST1q8LowTPseudo_UPD, .RealOpc: ARM::VST1d8Twb_fixed, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleLowSpc, .NumRegs: 3, .RegElts: 8 ,.copyAllListRegs: false},
419
420{ .PseudoOpc: ARM::VST2LNd16Pseudo, .RealOpc: ARM::VST2LNd16, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 2, .RegElts: 4 ,.copyAllListRegs: true},
421{ .PseudoOpc: ARM::VST2LNd16Pseudo_UPD, .RealOpc: ARM::VST2LNd16_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 2, .RegElts: 4 ,.copyAllListRegs: true},
422{ .PseudoOpc: ARM::VST2LNd32Pseudo, .RealOpc: ARM::VST2LNd32, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 2, .RegElts: 2 ,.copyAllListRegs: true},
423{ .PseudoOpc: ARM::VST2LNd32Pseudo_UPD, .RealOpc: ARM::VST2LNd32_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 2, .RegElts: 2 ,.copyAllListRegs: true},
424{ .PseudoOpc: ARM::VST2LNd8Pseudo, .RealOpc: ARM::VST2LNd8, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 2, .RegElts: 8 ,.copyAllListRegs: true},
425{ .PseudoOpc: ARM::VST2LNd8Pseudo_UPD, .RealOpc: ARM::VST2LNd8_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 2, .RegElts: 8 ,.copyAllListRegs: true},
426{ .PseudoOpc: ARM::VST2LNq16Pseudo, .RealOpc: ARM::VST2LNq16, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: EvenDblSpc, .NumRegs: 2, .RegElts: 4,.copyAllListRegs: true},
427{ .PseudoOpc: ARM::VST2LNq16Pseudo_UPD, .RealOpc: ARM::VST2LNq16_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: EvenDblSpc, .NumRegs: 2, .RegElts: 4,.copyAllListRegs: true},
428{ .PseudoOpc: ARM::VST2LNq32Pseudo, .RealOpc: ARM::VST2LNq32, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: EvenDblSpc, .NumRegs: 2, .RegElts: 2,.copyAllListRegs: true},
429{ .PseudoOpc: ARM::VST2LNq32Pseudo_UPD, .RealOpc: ARM::VST2LNq32_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: EvenDblSpc, .NumRegs: 2, .RegElts: 2,.copyAllListRegs: true},
430
431{ .PseudoOpc: ARM::VST2q16Pseudo, .RealOpc: ARM::VST2q16, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: false},
432{ .PseudoOpc: ARM::VST2q16PseudoWB_fixed, .RealOpc: ARM::VST2q16wb_fixed, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: false},
433{ .PseudoOpc: ARM::VST2q16PseudoWB_register, .RealOpc: ARM::VST2q16wb_register, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: false},
434{ .PseudoOpc: ARM::VST2q32Pseudo, .RealOpc: ARM::VST2q32, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: false},
435{ .PseudoOpc: ARM::VST2q32PseudoWB_fixed, .RealOpc: ARM::VST2q32wb_fixed, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: false},
436{ .PseudoOpc: ARM::VST2q32PseudoWB_register, .RealOpc: ARM::VST2q32wb_register, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: false},
437{ .PseudoOpc: ARM::VST2q8Pseudo, .RealOpc: ARM::VST2q8, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: false},
438{ .PseudoOpc: ARM::VST2q8PseudoWB_fixed, .RealOpc: ARM::VST2q8wb_fixed, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: false},
439{ .PseudoOpc: ARM::VST2q8PseudoWB_register, .RealOpc: ARM::VST2q8wb_register, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: false},
440
441{ .PseudoOpc: ARM::VST3LNd16Pseudo, .RealOpc: ARM::VST3LNd16, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 4 ,.copyAllListRegs: true},
442{ .PseudoOpc: ARM::VST3LNd16Pseudo_UPD, .RealOpc: ARM::VST3LNd16_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 4 ,.copyAllListRegs: true},
443{ .PseudoOpc: ARM::VST3LNd32Pseudo, .RealOpc: ARM::VST3LNd32, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 2 ,.copyAllListRegs: true},
444{ .PseudoOpc: ARM::VST3LNd32Pseudo_UPD, .RealOpc: ARM::VST3LNd32_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 2 ,.copyAllListRegs: true},
445{ .PseudoOpc: ARM::VST3LNd8Pseudo, .RealOpc: ARM::VST3LNd8, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 8 ,.copyAllListRegs: true},
446{ .PseudoOpc: ARM::VST3LNd8Pseudo_UPD, .RealOpc: ARM::VST3LNd8_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 8 ,.copyAllListRegs: true},
447{ .PseudoOpc: ARM::VST3LNq16Pseudo, .RealOpc: ARM::VST3LNq16, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: EvenDblSpc, .NumRegs: 3, .RegElts: 4,.copyAllListRegs: true},
448{ .PseudoOpc: ARM::VST3LNq16Pseudo_UPD, .RealOpc: ARM::VST3LNq16_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: EvenDblSpc, .NumRegs: 3, .RegElts: 4,.copyAllListRegs: true},
449{ .PseudoOpc: ARM::VST3LNq32Pseudo, .RealOpc: ARM::VST3LNq32, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: EvenDblSpc, .NumRegs: 3, .RegElts: 2,.copyAllListRegs: true},
450{ .PseudoOpc: ARM::VST3LNq32Pseudo_UPD, .RealOpc: ARM::VST3LNq32_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: EvenDblSpc, .NumRegs: 3, .RegElts: 2,.copyAllListRegs: true},
451
452{ .PseudoOpc: ARM::VST3d16Pseudo, .RealOpc: ARM::VST3d16, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 4 ,.copyAllListRegs: true},
453{ .PseudoOpc: ARM::VST3d16Pseudo_UPD, .RealOpc: ARM::VST3d16_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 4 ,.copyAllListRegs: true},
454{ .PseudoOpc: ARM::VST3d32Pseudo, .RealOpc: ARM::VST3d32, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 2 ,.copyAllListRegs: true},
455{ .PseudoOpc: ARM::VST3d32Pseudo_UPD, .RealOpc: ARM::VST3d32_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 2 ,.copyAllListRegs: true},
456{ .PseudoOpc: ARM::VST3d8Pseudo, .RealOpc: ARM::VST3d8, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 8 ,.copyAllListRegs: true},
457{ .PseudoOpc: ARM::VST3d8Pseudo_UPD, .RealOpc: ARM::VST3d8_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 3, .RegElts: 8 ,.copyAllListRegs: true},
458
459{ .PseudoOpc: ARM::VST3q16Pseudo_UPD, .RealOpc: ARM::VST3q16_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: EvenDblSpc, .NumRegs: 3, .RegElts: 4 ,.copyAllListRegs: true},
460{ .PseudoOpc: ARM::VST3q16oddPseudo, .RealOpc: ARM::VST3q16, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: OddDblSpc, .NumRegs: 3, .RegElts: 4 ,.copyAllListRegs: true},
461{ .PseudoOpc: ARM::VST3q16oddPseudo_UPD, .RealOpc: ARM::VST3q16_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: OddDblSpc, .NumRegs: 3, .RegElts: 4 ,.copyAllListRegs: true},
462{ .PseudoOpc: ARM::VST3q32Pseudo_UPD, .RealOpc: ARM::VST3q32_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: EvenDblSpc, .NumRegs: 3, .RegElts: 2 ,.copyAllListRegs: true},
463{ .PseudoOpc: ARM::VST3q32oddPseudo, .RealOpc: ARM::VST3q32, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: OddDblSpc, .NumRegs: 3, .RegElts: 2 ,.copyAllListRegs: true},
464{ .PseudoOpc: ARM::VST3q32oddPseudo_UPD, .RealOpc: ARM::VST3q32_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: OddDblSpc, .NumRegs: 3, .RegElts: 2 ,.copyAllListRegs: true},
465{ .PseudoOpc: ARM::VST3q8Pseudo_UPD, .RealOpc: ARM::VST3q8_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: EvenDblSpc, .NumRegs: 3, .RegElts: 8 ,.copyAllListRegs: true},
466{ .PseudoOpc: ARM::VST3q8oddPseudo, .RealOpc: ARM::VST3q8, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: OddDblSpc, .NumRegs: 3, .RegElts: 8 ,.copyAllListRegs: true},
467{ .PseudoOpc: ARM::VST3q8oddPseudo_UPD, .RealOpc: ARM::VST3q8_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: OddDblSpc, .NumRegs: 3, .RegElts: 8 ,.copyAllListRegs: true},
468
469{ .PseudoOpc: ARM::VST4LNd16Pseudo, .RealOpc: ARM::VST4LNd16, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: true},
470{ .PseudoOpc: ARM::VST4LNd16Pseudo_UPD, .RealOpc: ARM::VST4LNd16_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: true},
471{ .PseudoOpc: ARM::VST4LNd32Pseudo, .RealOpc: ARM::VST4LNd32, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: true},
472{ .PseudoOpc: ARM::VST4LNd32Pseudo_UPD, .RealOpc: ARM::VST4LNd32_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: true},
473{ .PseudoOpc: ARM::VST4LNd8Pseudo, .RealOpc: ARM::VST4LNd8, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: true},
474{ .PseudoOpc: ARM::VST4LNd8Pseudo_UPD, .RealOpc: ARM::VST4LNd8_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: true},
475{ .PseudoOpc: ARM::VST4LNq16Pseudo, .RealOpc: ARM::VST4LNq16, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: EvenDblSpc, .NumRegs: 4, .RegElts: 4,.copyAllListRegs: true},
476{ .PseudoOpc: ARM::VST4LNq16Pseudo_UPD, .RealOpc: ARM::VST4LNq16_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: EvenDblSpc, .NumRegs: 4, .RegElts: 4,.copyAllListRegs: true},
477{ .PseudoOpc: ARM::VST4LNq32Pseudo, .RealOpc: ARM::VST4LNq32, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: EvenDblSpc, .NumRegs: 4, .RegElts: 2,.copyAllListRegs: true},
478{ .PseudoOpc: ARM::VST4LNq32Pseudo_UPD, .RealOpc: ARM::VST4LNq32_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: EvenDblSpc, .NumRegs: 4, .RegElts: 2,.copyAllListRegs: true},
479
480{ .PseudoOpc: ARM::VST4d16Pseudo, .RealOpc: ARM::VST4d16, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: true},
481{ .PseudoOpc: ARM::VST4d16Pseudo_UPD, .RealOpc: ARM::VST4d16_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: true},
482{ .PseudoOpc: ARM::VST4d32Pseudo, .RealOpc: ARM::VST4d32, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: true},
483{ .PseudoOpc: ARM::VST4d32Pseudo_UPD, .RealOpc: ARM::VST4d32_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: true},
484{ .PseudoOpc: ARM::VST4d8Pseudo, .RealOpc: ARM::VST4d8, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: true},
485{ .PseudoOpc: ARM::VST4d8Pseudo_UPD, .RealOpc: ARM::VST4d8_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: SingleSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: true},
486
487{ .PseudoOpc: ARM::VST4q16Pseudo_UPD, .RealOpc: ARM::VST4q16_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: EvenDblSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: true},
488{ .PseudoOpc: ARM::VST4q16oddPseudo, .RealOpc: ARM::VST4q16, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: OddDblSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: true},
489{ .PseudoOpc: ARM::VST4q16oddPseudo_UPD, .RealOpc: ARM::VST4q16_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: OddDblSpc, .NumRegs: 4, .RegElts: 4 ,.copyAllListRegs: true},
490{ .PseudoOpc: ARM::VST4q32Pseudo_UPD, .RealOpc: ARM::VST4q32_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: EvenDblSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: true},
491{ .PseudoOpc: ARM::VST4q32oddPseudo, .RealOpc: ARM::VST4q32, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: OddDblSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: true},
492{ .PseudoOpc: ARM::VST4q32oddPseudo_UPD, .RealOpc: ARM::VST4q32_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: OddDblSpc, .NumRegs: 4, .RegElts: 2 ,.copyAllListRegs: true},
493{ .PseudoOpc: ARM::VST4q8Pseudo_UPD, .RealOpc: ARM::VST4q8_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: EvenDblSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: true},
494{ .PseudoOpc: ARM::VST4q8oddPseudo, .RealOpc: ARM::VST4q8, .IsLoad: false, .isUpdating: false, .hasWritebackOperand: false, .RegSpacing: OddDblSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: true},
495{ .PseudoOpc: ARM::VST4q8oddPseudo_UPD, .RealOpc: ARM::VST4q8_UPD, .IsLoad: false, .isUpdating: true, .hasWritebackOperand: true, .RegSpacing: OddDblSpc, .NumRegs: 4, .RegElts: 8 ,.copyAllListRegs: true}
496};
497
498/// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON
499/// load or store pseudo instruction.
500static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
501#ifndef NDEBUG
502 // Make sure the table is sorted.
503 static std::atomic<bool> TableChecked(false);
504 if (!TableChecked.load(std::memory_order_relaxed)) {
505 assert(llvm::is_sorted(NEONLdStTable) && "NEONLdStTable is not sorted!");
506 TableChecked.store(true, std::memory_order_relaxed);
507 }
508#endif
509
510 auto I = llvm::lower_bound(Range: NEONLdStTable, Value&: Opcode);
511 if (I != std::end(arr: NEONLdStTable) && I->PseudoOpc == Opcode)
512 return I;
513 return nullptr;
514}
515
516/// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register,
517/// corresponding to the specified register spacing. Not all of the results
518/// are necessarily valid, e.g., a Q register only has 2 D subregisters.
519static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
520 const TargetRegisterInfo *TRI, MCRegister &D0,
521 MCRegister &D1, MCRegister &D2, MCRegister &D3) {
522 if (RegSpc == SingleSpc || RegSpc == SingleLowSpc) {
523 D0 = TRI->getSubReg(Reg, Idx: ARM::dsub_0);
524 D1 = TRI->getSubReg(Reg, Idx: ARM::dsub_1);
525 D2 = TRI->getSubReg(Reg, Idx: ARM::dsub_2);
526 D3 = TRI->getSubReg(Reg, Idx: ARM::dsub_3);
527 } else if (RegSpc == SingleHighQSpc) {
528 D0 = TRI->getSubReg(Reg, Idx: ARM::dsub_4);
529 D1 = TRI->getSubReg(Reg, Idx: ARM::dsub_5);
530 D2 = TRI->getSubReg(Reg, Idx: ARM::dsub_6);
531 D3 = TRI->getSubReg(Reg, Idx: ARM::dsub_7);
532 } else if (RegSpc == SingleHighTSpc) {
533 D0 = TRI->getSubReg(Reg, Idx: ARM::dsub_3);
534 D1 = TRI->getSubReg(Reg, Idx: ARM::dsub_4);
535 D2 = TRI->getSubReg(Reg, Idx: ARM::dsub_5);
536 D3 = TRI->getSubReg(Reg, Idx: ARM::dsub_6);
537 } else if (RegSpc == EvenDblSpc) {
538 D0 = TRI->getSubReg(Reg, Idx: ARM::dsub_0);
539 D1 = TRI->getSubReg(Reg, Idx: ARM::dsub_2);
540 D2 = TRI->getSubReg(Reg, Idx: ARM::dsub_4);
541 D3 = TRI->getSubReg(Reg, Idx: ARM::dsub_6);
542 } else {
543 assert(RegSpc == OddDblSpc && "unknown register spacing");
544 D0 = TRI->getSubReg(Reg, Idx: ARM::dsub_1);
545 D1 = TRI->getSubReg(Reg, Idx: ARM::dsub_3);
546 D2 = TRI->getSubReg(Reg, Idx: ARM::dsub_5);
547 D3 = TRI->getSubReg(Reg, Idx: ARM::dsub_7);
548 }
549}
550
551/// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
552/// operands to real VLD instructions with D register operands.
553void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
554 MachineInstr &MI = *MBBI;
555 MachineBasicBlock &MBB = *MI.getParent();
556 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump());
557
558 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(Opcode: MI.getOpcode());
559 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
560 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
561 unsigned NumRegs = TableEntry->NumRegs;
562
563 MachineInstrBuilder MIB = BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(),
564 MCID: TII->get(Opcode: TableEntry->RealOpc));
565 unsigned OpIdx = 0;
566
567 bool DstIsDead = MI.getOperand(i: OpIdx).isDead();
568 Register DstReg = MI.getOperand(i: OpIdx++).getReg();
569
570 bool IsVLD2DUP = TableEntry->RealOpc == ARM::VLD2DUPd8x2 ||
571 TableEntry->RealOpc == ARM::VLD2DUPd16x2 ||
572 TableEntry->RealOpc == ARM::VLD2DUPd32x2 ||
573 TableEntry->RealOpc == ARM::VLD2DUPd8x2wb_fixed ||
574 TableEntry->RealOpc == ARM::VLD2DUPd16x2wb_fixed ||
575 TableEntry->RealOpc == ARM::VLD2DUPd32x2wb_fixed ||
576 TableEntry->RealOpc == ARM::VLD2DUPd8x2wb_register ||
577 TableEntry->RealOpc == ARM::VLD2DUPd16x2wb_register ||
578 TableEntry->RealOpc == ARM::VLD2DUPd32x2wb_register;
579
580 if (IsVLD2DUP) {
581 unsigned SubRegIndex;
582 if (RegSpc == EvenDblSpc) {
583 SubRegIndex = ARM::dsub_0;
584 } else {
585 assert(RegSpc == OddDblSpc && "Unexpected spacing!");
586 SubRegIndex = ARM::dsub_1;
587 }
588 Register SubReg = TRI->getSubReg(Reg: DstReg, Idx: SubRegIndex);
589 MCRegister DstRegPair =
590 TRI->getMatchingSuperReg(Reg: SubReg, SubIdx: ARM::dsub_0, RC: &ARM::DPairSpcRegClass);
591 MIB.addReg(RegNo: DstRegPair, Flags: RegState::Define | getDeadRegState(B: DstIsDead));
592 } else {
593 MCRegister D0, D1, D2, D3;
594 GetDSubRegs(Reg: DstReg, RegSpc, TRI, D0, D1, D2, D3);
595 MIB.addReg(RegNo: D0, Flags: RegState::Define | getDeadRegState(B: DstIsDead));
596 if (NumRegs > 1 && TableEntry->copyAllListRegs)
597 MIB.addReg(RegNo: D1, Flags: RegState::Define | getDeadRegState(B: DstIsDead));
598 if (NumRegs > 2 && TableEntry->copyAllListRegs)
599 MIB.addReg(RegNo: D2, Flags: RegState::Define | getDeadRegState(B: DstIsDead));
600 if (NumRegs > 3 && TableEntry->copyAllListRegs)
601 MIB.addReg(RegNo: D3, Flags: RegState::Define | getDeadRegState(B: DstIsDead));
602 }
603
604 if (TableEntry->isUpdating)
605 MIB.add(MO: MI.getOperand(i: OpIdx++));
606
607 // Copy the addrmode6 operands.
608 MIB.add(MO: MI.getOperand(i: OpIdx++));
609 MIB.add(MO: MI.getOperand(i: OpIdx++));
610
611 // Copy the am6offset operand.
612 if (TableEntry->hasWritebackOperand) {
613 // TODO: The writing-back pseudo instructions we translate here are all
614 // defined to take am6offset nodes that are capable to represent both fixed
615 // and register forms. Some real instructions, however, do not rely on
616 // am6offset and have separate definitions for such forms. When this is the
617 // case, fixed forms do not take any offset nodes, so here we skip them for
618 // such instructions. Once all real and pseudo writing-back instructions are
619 // rewritten without use of am6offset nodes, this code will go away.
620 const MachineOperand &AM6Offset = MI.getOperand(i: OpIdx++);
621 if (TableEntry->RealOpc == ARM::VLD1d8Qwb_fixed ||
622 TableEntry->RealOpc == ARM::VLD1d16Qwb_fixed ||
623 TableEntry->RealOpc == ARM::VLD1d32Qwb_fixed ||
624 TableEntry->RealOpc == ARM::VLD1d64Qwb_fixed ||
625 TableEntry->RealOpc == ARM::VLD1d8Twb_fixed ||
626 TableEntry->RealOpc == ARM::VLD1d16Twb_fixed ||
627 TableEntry->RealOpc == ARM::VLD1d32Twb_fixed ||
628 TableEntry->RealOpc == ARM::VLD1d64Twb_fixed ||
629 TableEntry->RealOpc == ARM::VLD2DUPd8x2wb_fixed ||
630 TableEntry->RealOpc == ARM::VLD2DUPd16x2wb_fixed ||
631 TableEntry->RealOpc == ARM::VLD2DUPd32x2wb_fixed) {
632 assert(AM6Offset.getReg() == 0 &&
633 "A fixed writing-back pseudo instruction provides an offset "
634 "register!");
635 } else {
636 MIB.add(MO: AM6Offset);
637 }
638 }
639
640 // For an instruction writing double-spaced subregs, the pseudo instruction
641 // has an extra operand that is a use of the super-register. Record the
642 // operand index and skip over it.
643 unsigned SrcOpIdx = 0;
644 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc || RegSpc == SingleLowSpc ||
645 RegSpc == SingleHighQSpc || RegSpc == SingleHighTSpc)
646 SrcOpIdx = OpIdx++;
647
648 // Copy the predicate operands.
649 MIB.add(MO: MI.getOperand(i: OpIdx++));
650 MIB.add(MO: MI.getOperand(i: OpIdx++));
651
652 // Copy the super-register source operand used for double-spaced subregs over
653 // to the new instruction as an implicit operand.
654 if (SrcOpIdx != 0) {
655 MachineOperand MO = MI.getOperand(i: SrcOpIdx);
656 MO.setImplicit(true);
657 MIB.add(MO);
658 }
659 // Add an implicit def for the super-register.
660 MIB.addReg(RegNo: DstReg, Flags: RegState::ImplicitDefine | getDeadRegState(B: DstIsDead));
661 MIB.copyImplicitOps(OtherMI: MI);
662
663 // Transfer memoperands.
664 MIB.cloneMemRefs(OtherMI: MI);
665 MI.eraseFromParent();
666 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump(););
667}
668
669/// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register
670/// operands to real VST instructions with D register operands.
671void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
672 MachineInstr &MI = *MBBI;
673 MachineBasicBlock &MBB = *MI.getParent();
674 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump());
675
676 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(Opcode: MI.getOpcode());
677 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
678 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
679 unsigned NumRegs = TableEntry->NumRegs;
680
681 MachineInstrBuilder MIB = BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(),
682 MCID: TII->get(Opcode: TableEntry->RealOpc));
683 unsigned OpIdx = 0;
684 if (TableEntry->isUpdating)
685 MIB.add(MO: MI.getOperand(i: OpIdx++));
686
687 // Copy the addrmode6 operands.
688 MIB.add(MO: MI.getOperand(i: OpIdx++));
689 MIB.add(MO: MI.getOperand(i: OpIdx++));
690
691 if (TableEntry->hasWritebackOperand) {
692 // TODO: The writing-back pseudo instructions we translate here are all
693 // defined to take am6offset nodes that are capable to represent both fixed
694 // and register forms. Some real instructions, however, do not rely on
695 // am6offset and have separate definitions for such forms. When this is the
696 // case, fixed forms do not take any offset nodes, so here we skip them for
697 // such instructions. Once all real and pseudo writing-back instructions are
698 // rewritten without use of am6offset nodes, this code will go away.
699 const MachineOperand &AM6Offset = MI.getOperand(i: OpIdx++);
700 if (TableEntry->RealOpc == ARM::VST1d8Qwb_fixed ||
701 TableEntry->RealOpc == ARM::VST1d16Qwb_fixed ||
702 TableEntry->RealOpc == ARM::VST1d32Qwb_fixed ||
703 TableEntry->RealOpc == ARM::VST1d64Qwb_fixed ||
704 TableEntry->RealOpc == ARM::VST1d8Twb_fixed ||
705 TableEntry->RealOpc == ARM::VST1d16Twb_fixed ||
706 TableEntry->RealOpc == ARM::VST1d32Twb_fixed ||
707 TableEntry->RealOpc == ARM::VST1d64Twb_fixed) {
708 assert(AM6Offset.getReg() == 0 &&
709 "A fixed writing-back pseudo instruction provides an offset "
710 "register!");
711 } else {
712 MIB.add(MO: AM6Offset);
713 }
714 }
715
716 bool SrcIsKill = MI.getOperand(i: OpIdx).isKill();
717 bool SrcIsUndef = MI.getOperand(i: OpIdx).isUndef();
718 Register SrcReg = MI.getOperand(i: OpIdx++).getReg();
719 MCRegister D0, D1, D2, D3;
720 GetDSubRegs(Reg: SrcReg, RegSpc, TRI, D0, D1, D2, D3);
721 MIB.addReg(RegNo: D0, Flags: getUndefRegState(B: SrcIsUndef));
722 if (NumRegs > 1 && TableEntry->copyAllListRegs)
723 MIB.addReg(RegNo: D1, Flags: getUndefRegState(B: SrcIsUndef));
724 if (NumRegs > 2 && TableEntry->copyAllListRegs)
725 MIB.addReg(RegNo: D2, Flags: getUndefRegState(B: SrcIsUndef));
726 if (NumRegs > 3 && TableEntry->copyAllListRegs)
727 MIB.addReg(RegNo: D3, Flags: getUndefRegState(B: SrcIsUndef));
728
729 // Copy the predicate operands.
730 MIB.add(MO: MI.getOperand(i: OpIdx++));
731 MIB.add(MO: MI.getOperand(i: OpIdx++));
732
733 if (SrcIsKill && !SrcIsUndef) // Add an implicit kill for the super-reg.
734 MIB->addRegisterKilled(IncomingReg: SrcReg, RegInfo: TRI, AddIfNotFound: true);
735 else if (!SrcIsUndef)
736 MIB.addReg(RegNo: SrcReg, Flags: RegState::Implicit); // Add implicit uses for src reg.
737 MIB.copyImplicitOps(OtherMI: MI);
738
739 // Transfer memoperands.
740 MIB.cloneMemRefs(OtherMI: MI);
741 MI.eraseFromParent();
742 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump(););
743}
744
745/// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ
746/// register operands to real instructions with D register operands.
747void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
748 MachineInstr &MI = *MBBI;
749 MachineBasicBlock &MBB = *MI.getParent();
750 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump());
751
752 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(Opcode: MI.getOpcode());
753 assert(TableEntry && "NEONLdStTable lookup failed");
754 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
755 unsigned NumRegs = TableEntry->NumRegs;
756 unsigned RegElts = TableEntry->RegElts;
757
758 MachineInstrBuilder MIB = BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(),
759 MCID: TII->get(Opcode: TableEntry->RealOpc));
760 unsigned OpIdx = 0;
761 // The lane operand is always the 3rd from last operand, before the 2
762 // predicate operands.
763 unsigned Lane = MI.getOperand(i: MI.getDesc().getNumOperands() - 3).getImm();
764
765 // Adjust the lane and spacing as needed for Q registers.
766 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
767 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
768 RegSpc = OddDblSpc;
769 Lane -= RegElts;
770 }
771 assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
772
773 MCRegister D0, D1, D2, D3;
774 unsigned DstReg = 0;
775 bool DstIsDead = false;
776 if (TableEntry->IsLoad) {
777 DstIsDead = MI.getOperand(i: OpIdx).isDead();
778 DstReg = MI.getOperand(i: OpIdx++).getReg();
779 GetDSubRegs(Reg: DstReg, RegSpc, TRI, D0, D1, D2, D3);
780 MIB.addReg(RegNo: D0, Flags: RegState::Define | getDeadRegState(B: DstIsDead));
781 if (NumRegs > 1)
782 MIB.addReg(RegNo: D1, Flags: RegState::Define | getDeadRegState(B: DstIsDead));
783 if (NumRegs > 2)
784 MIB.addReg(RegNo: D2, Flags: RegState::Define | getDeadRegState(B: DstIsDead));
785 if (NumRegs > 3)
786 MIB.addReg(RegNo: D3, Flags: RegState::Define | getDeadRegState(B: DstIsDead));
787 }
788
789 if (TableEntry->isUpdating)
790 MIB.add(MO: MI.getOperand(i: OpIdx++));
791
792 // Copy the addrmode6 operands.
793 MIB.add(MO: MI.getOperand(i: OpIdx++));
794 MIB.add(MO: MI.getOperand(i: OpIdx++));
795 // Copy the am6offset operand.
796 if (TableEntry->hasWritebackOperand)
797 MIB.add(MO: MI.getOperand(i: OpIdx++));
798
799 // Grab the super-register source.
800 MachineOperand MO = MI.getOperand(i: OpIdx++);
801 if (!TableEntry->IsLoad)
802 GetDSubRegs(Reg: MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);
803
804 // Add the subregs as sources of the new instruction.
805 RegState SrcFlags =
806 (getUndefRegState(B: MO.isUndef()) | getKillRegState(B: MO.isKill()));
807 MIB.addReg(RegNo: D0, Flags: SrcFlags);
808 if (NumRegs > 1)
809 MIB.addReg(RegNo: D1, Flags: SrcFlags);
810 if (NumRegs > 2)
811 MIB.addReg(RegNo: D2, Flags: SrcFlags);
812 if (NumRegs > 3)
813 MIB.addReg(RegNo: D3, Flags: SrcFlags);
814
815 // Add the lane number operand.
816 MIB.addImm(Val: Lane);
817 OpIdx += 1;
818
819 // Copy the predicate operands.
820 MIB.add(MO: MI.getOperand(i: OpIdx++));
821 MIB.add(MO: MI.getOperand(i: OpIdx++));
822
823 // Copy the super-register source to be an implicit source.
824 MO.setImplicit(true);
825 MIB.add(MO);
826 if (TableEntry->IsLoad)
827 // Add an implicit def for the super-register.
828 MIB.addReg(RegNo: DstReg, Flags: RegState::ImplicitDefine | getDeadRegState(B: DstIsDead));
829 MIB.copyImplicitOps(OtherMI: MI);
830 // Transfer memoperands.
831 MIB.cloneMemRefs(OtherMI: MI);
832 MI.eraseFromParent();
833}
834
835/// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ
836/// register operands to real instructions with D register operands.
837void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
838 unsigned Opc, bool IsExt) {
839 MachineInstr &MI = *MBBI;
840 MachineBasicBlock &MBB = *MI.getParent();
841 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump());
842
843 MachineInstrBuilder MIB = BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: Opc));
844 unsigned OpIdx = 0;
845
846 // Transfer the destination register operand.
847 MIB.add(MO: MI.getOperand(i: OpIdx++));
848 if (IsExt) {
849 MachineOperand VdSrc(MI.getOperand(i: OpIdx++));
850 MIB.add(MO: VdSrc);
851 }
852
853 bool SrcIsKill = MI.getOperand(i: OpIdx).isKill();
854 Register SrcReg = MI.getOperand(i: OpIdx++).getReg();
855 MCRegister D0, D1, D2, D3;
856 GetDSubRegs(Reg: SrcReg, RegSpc: SingleSpc, TRI, D0, D1, D2, D3);
857 MIB.addReg(RegNo: D0);
858
859 // Copy the other source register operand.
860 MachineOperand VmSrc(MI.getOperand(i: OpIdx++));
861 MIB.add(MO: VmSrc);
862
863 // Copy the predicate operands.
864 MIB.add(MO: MI.getOperand(i: OpIdx++));
865 MIB.add(MO: MI.getOperand(i: OpIdx++));
866
867 // Add an implicit kill and use for the super-reg.
868 MIB.addReg(RegNo: SrcReg, Flags: RegState::Implicit | getKillRegState(B: SrcIsKill));
869 MIB.copyImplicitOps(OtherMI: MI);
870 MI.eraseFromParent();
871 LLVM_DEBUG(dbgs() << "To: "; MIB.getInstr()->dump(););
872}
873
874void ARMExpandPseudo::ExpandMQQPRLoadStore(MachineBasicBlock::iterator &MBBI) {
875 MachineInstr &MI = *MBBI;
876 MachineBasicBlock &MBB = *MI.getParent();
877 unsigned NewOpc =
878 MI.getOpcode() == ARM::MQQPRStore || MI.getOpcode() == ARM::MQQQQPRStore
879 ? ARM::VSTMDIA
880 : ARM::VLDMDIA;
881 MachineInstrBuilder MIB =
882 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: NewOpc));
883
884 RegState Flags = getKillRegState(B: MI.getOperand(i: 0).isKill()) |
885 getDefRegState(B: MI.getOperand(i: 0).isDef());
886 Register SrcReg = MI.getOperand(i: 0).getReg();
887
888 // Copy the destination register.
889 MIB.add(MO: MI.getOperand(i: 1));
890 MIB.add(MOs: predOps(Pred: ARMCC::AL));
891 MIB.addReg(RegNo: TRI->getSubReg(Reg: SrcReg, Idx: ARM::dsub_0), Flags);
892 MIB.addReg(RegNo: TRI->getSubReg(Reg: SrcReg, Idx: ARM::dsub_1), Flags);
893 MIB.addReg(RegNo: TRI->getSubReg(Reg: SrcReg, Idx: ARM::dsub_2), Flags);
894 MIB.addReg(RegNo: TRI->getSubReg(Reg: SrcReg, Idx: ARM::dsub_3), Flags);
895 if (MI.getOpcode() == ARM::MQQQQPRStore ||
896 MI.getOpcode() == ARM::MQQQQPRLoad) {
897 MIB.addReg(RegNo: TRI->getSubReg(Reg: SrcReg, Idx: ARM::dsub_4), Flags);
898 MIB.addReg(RegNo: TRI->getSubReg(Reg: SrcReg, Idx: ARM::dsub_5), Flags);
899 MIB.addReg(RegNo: TRI->getSubReg(Reg: SrcReg, Idx: ARM::dsub_6), Flags);
900 MIB.addReg(RegNo: TRI->getSubReg(Reg: SrcReg, Idx: ARM::dsub_7), Flags);
901 }
902
903 if (NewOpc == ARM::VSTMDIA)
904 MIB.addReg(RegNo: SrcReg, Flags: RegState::Implicit);
905
906 MIB.copyImplicitOps(OtherMI: MI);
907 MIB.cloneMemRefs(OtherMI: MI);
908 MI.eraseFromParent();
909}
910
911static bool IsAnAddressOperand(const MachineOperand &MO) {
912 // This check is overly conservative. Unless we are certain that the machine
913 // operand is not a symbol reference, we return that it is a symbol reference.
914 // This is important as the load pair may not be split up Windows.
915 switch (MO.getType()) {
916 case MachineOperand::MO_Register:
917 case MachineOperand::MO_Immediate:
918 case MachineOperand::MO_CImmediate:
919 case MachineOperand::MO_FPImmediate:
920 case MachineOperand::MO_ShuffleMask:
921 return false;
922 case MachineOperand::MO_MachineBasicBlock:
923 return true;
924 case MachineOperand::MO_FrameIndex:
925 return false;
926 case MachineOperand::MO_ConstantPoolIndex:
927 case MachineOperand::MO_TargetIndex:
928 case MachineOperand::MO_JumpTableIndex:
929 case MachineOperand::MO_ExternalSymbol:
930 case MachineOperand::MO_GlobalAddress:
931 case MachineOperand::MO_BlockAddress:
932 return true;
933 case MachineOperand::MO_RegisterMask:
934 case MachineOperand::MO_RegisterLiveOut:
935 case MachineOperand::MO_LaneMask:
936 return false;
937 case MachineOperand::MO_Metadata:
938 case MachineOperand::MO_MCSymbol:
939 return true;
940 case MachineOperand::MO_DbgInstrRef:
941 case MachineOperand::MO_CFIIndex:
942 return false;
943 case MachineOperand::MO_IntrinsicID:
944 case MachineOperand::MO_Predicate:
945 llvm_unreachable("should not exist post-isel");
946 }
947 llvm_unreachable("unhandled machine operand type");
948}
949
950static MachineOperand makeImplicit(const MachineOperand &MO) {
951 MachineOperand NewMO = MO;
952 NewMO.setImplicit();
953 return NewMO;
954}
955
956static MachineOperand getMovOperand(const MachineOperand &MO,
957 unsigned TargetFlag) {
958 unsigned TF = MO.getTargetFlags() | TargetFlag;
959 switch (MO.getType()) {
960 case MachineOperand::MO_Immediate: {
961 unsigned Imm = MO.getImm();
962 switch (TargetFlag) {
963 case ARMII::MO_HI_8_15:
964 Imm = (Imm >> 24) & 0xff;
965 break;
966 case ARMII::MO_HI_0_7:
967 Imm = (Imm >> 16) & 0xff;
968 break;
969 case ARMII::MO_LO_8_15:
970 Imm = (Imm >> 8) & 0xff;
971 break;
972 case ARMII::MO_LO_0_7:
973 Imm = Imm & 0xff;
974 break;
975 case ARMII::MO_HI16:
976 Imm = (Imm >> 16) & 0xffff;
977 break;
978 case ARMII::MO_LO16:
979 Imm = Imm & 0xffff;
980 break;
981 default:
982 llvm_unreachable("Only HI/LO target flags are expected");
983 }
984 return MachineOperand::CreateImm(Val: Imm);
985 }
986 case MachineOperand::MO_ExternalSymbol:
987 return MachineOperand::CreateES(SymName: MO.getSymbolName(), TargetFlags: TF);
988 case MachineOperand::MO_MCSymbol:
989 return MachineOperand::CreateMCSymbol(Sym: MO.getMCSymbol(), TargetFlags: TF);
990 case MachineOperand::MO_JumpTableIndex:
991 return MachineOperand::CreateJTI(Idx: MO.getIndex(), TargetFlags: TF);
992 default:
993 return MachineOperand::CreateGA(GV: MO.getGlobal(), Offset: MO.getOffset(), TargetFlags: TF);
994 }
995}
996
997void ARMExpandPseudo::ExpandTMOV32BitImm(MachineBasicBlock &MBB,
998 MachineBasicBlock::iterator &MBBI) {
999 MachineInstr &MI = *MBBI;
1000 Register DstReg = MI.getOperand(i: 0).getReg();
1001 bool DstIsDead = MI.getOperand(i: 0).isDead();
1002 const MachineOperand &MO = MI.getOperand(i: 1);
1003 unsigned MIFlags = MI.getFlags();
1004
1005 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump());
1006
1007 // Expand the mov into a sequence of mov/add+lsl of the individual bytes. We
1008 // want to avoid emitting any zero bytes, as they won't change the result, and
1009 // also don't want any pointless shifts, so instead of immediately emitting
1010 // the shift for a byte we keep track of how much we will need to shift and do
1011 // it before the next nonzero byte.
1012 unsigned PendingShift = 0;
1013 for (unsigned Byte = 0; Byte < 4; ++Byte) {
1014 unsigned Flag = Byte == 0 ? ARMII::MO_HI_8_15
1015 : Byte == 1 ? ARMII::MO_HI_0_7
1016 : Byte == 2 ? ARMII::MO_LO_8_15
1017 : ARMII::MO_LO_0_7;
1018 MachineOperand Operand = getMovOperand(MO, TargetFlag: Flag);
1019 bool ZeroImm = Operand.isImm() && Operand.getImm() == 0;
1020 unsigned Op = PendingShift ? ARM::tADDi8 : ARM::tMOVi8;
1021
1022 // Emit the pending shift if we're going to emit this byte or if we've
1023 // reached the end.
1024 if (PendingShift && (!ZeroImm || Byte == 3)) {
1025 MachineInstr *Lsl =
1026 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: ARM::tLSLri), DestReg: DstReg)
1027 .add(MO: t1CondCodeOp(isDead: true))
1028 .addReg(RegNo: DstReg)
1029 .addImm(Val: PendingShift)
1030 .add(MOs: predOps(Pred: ARMCC::AL))
1031 .setMIFlags(MIFlags);
1032 (void)Lsl;
1033 LLVM_DEBUG(dbgs() << "And: "; Lsl->dump(););
1034 PendingShift = 0;
1035 }
1036
1037 // Emit this byte if it's nonzero.
1038 if (!ZeroImm) {
1039 MachineInstrBuilder MIB =
1040 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: Op), DestReg: DstReg)
1041 .add(MO: t1CondCodeOp(isDead: true));
1042 if (Op == ARM::tADDi8)
1043 MIB.addReg(RegNo: DstReg);
1044 MIB.add(MO: Operand);
1045 MIB.add(MOs: predOps(Pred: ARMCC::AL));
1046 MIB.setMIFlags(MIFlags);
1047 LLVM_DEBUG(dbgs() << (Op == ARM::tMOVi8 ? "To: " : "And:") << " ";
1048 MIB.getInstr()->dump(););
1049 }
1050
1051 // Don't accumulate the shift value if we've not yet seen a nonzero byte.
1052 if (PendingShift || !ZeroImm)
1053 PendingShift += 8;
1054 }
1055
1056 // The dest is dead on the last instruction we emitted if it was dead on the
1057 // original instruction.
1058 (--MBBI)->getOperand(i: 0).setIsDead(DstIsDead);
1059
1060 MI.eraseFromParent();
1061}
1062
1063void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
1064 MachineBasicBlock::iterator &MBBI) {
1065 MachineInstr &MI = *MBBI;
1066 unsigned Opcode = MI.getOpcode();
1067 Register PredReg;
1068 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
1069 Register DstReg = MI.getOperand(i: 0).getReg();
1070 bool DstIsDead = MI.getOperand(i: 0).isDead();
1071 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
1072 const MachineOperand &MO = MI.getOperand(i: isCC ? 2 : 1);
1073 bool RequiresBundling = STI->isTargetWindows() && IsAnAddressOperand(MO);
1074 MachineInstrBuilder LO16, HI16;
1075 LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump());
1076
1077 if (!STI->hasV6T2Ops() &&
1078 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
1079 // FIXME Windows CE supports older ARM CPUs
1080 assert(!STI->isTargetWindows() && "Windows on ARM requires ARMv7+");
1081
1082 assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!");
1083 unsigned ImmVal = (unsigned)MO.getImm();
1084 unsigned SOImmValV1 = 0, SOImmValV2 = 0;
1085
1086 if (ARM_AM::isSOImmTwoPartVal(V: ImmVal)) { // Expand into a movi + orr.
1087 LO16 = BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: ARM::MOVi), DestReg: DstReg);
1088 HI16 = BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: ARM::ORRri))
1089 .addReg(RegNo: DstReg, Flags: RegState::Define | getDeadRegState(B: DstIsDead))
1090 .addReg(RegNo: DstReg);
1091 SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(V: ImmVal);
1092 SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(V: ImmVal);
1093 } else { // Expand into a mvn + sub.
1094 LO16 = BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: ARM::MVNi), DestReg: DstReg);
1095 HI16 = BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: ARM::SUBri))
1096 .addReg(RegNo: DstReg, Flags: RegState::Define | getDeadRegState(B: DstIsDead))
1097 .addReg(RegNo: DstReg);
1098 SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(V: -ImmVal);
1099 SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(V: -ImmVal);
1100 SOImmValV1 = ~(-SOImmValV1);
1101 }
1102
1103 unsigned MIFlags = MI.getFlags();
1104 LO16 = LO16.addImm(Val: SOImmValV1);
1105 HI16 = HI16.addImm(Val: SOImmValV2);
1106 LO16.cloneMemRefs(OtherMI: MI);
1107 HI16.cloneMemRefs(OtherMI: MI);
1108 LO16.setMIFlags(MIFlags);
1109 HI16.setMIFlags(MIFlags);
1110 LO16.addImm(Val: Pred).addReg(RegNo: PredReg).add(MO: condCodeOp());
1111 HI16.addImm(Val: Pred).addReg(RegNo: PredReg).add(MO: condCodeOp());
1112 if (isCC)
1113 LO16.add(MO: makeImplicit(MO: MI.getOperand(i: 1)));
1114 LO16.copyImplicitOps(OtherMI: MI);
1115 HI16.copyImplicitOps(OtherMI: MI);
1116 MI.eraseFromParent();
1117 return;
1118 }
1119
1120 unsigned LO16Opc = 0;
1121 unsigned HI16Opc = 0;
1122 unsigned MIFlags = MI.getFlags();
1123 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) {
1124 LO16Opc = ARM::t2MOVi16;
1125 HI16Opc = ARM::t2MOVTi16;
1126 } else {
1127 LO16Opc = ARM::MOVi16;
1128 HI16Opc = ARM::MOVTi16;
1129 }
1130
1131 LO16 = BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: LO16Opc), DestReg: DstReg);
1132 LO16.setMIFlags(MIFlags);
1133 LO16.add(MO: getMovOperand(MO, TargetFlag: ARMII::MO_LO16));
1134 LO16.cloneMemRefs(OtherMI: MI);
1135 LO16.addImm(Val: Pred).addReg(RegNo: PredReg);
1136 if (isCC)
1137 LO16.add(MO: makeImplicit(MO: MI.getOperand(i: 1)));
1138 LO16.copyImplicitOps(OtherMI: MI);
1139 LLVM_DEBUG(dbgs() << "To: "; LO16.getInstr()->dump(););
1140
1141 MachineOperand HIOperand = getMovOperand(MO, TargetFlag: ARMII::MO_HI16);
1142 if (!(HIOperand.isImm() && HIOperand.getImm() == 0)) {
1143 HI16 = BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: HI16Opc))
1144 .addReg(RegNo: DstReg, Flags: RegState::Define | getDeadRegState(B: DstIsDead))
1145 .addReg(RegNo: DstReg);
1146 HI16.setMIFlags(MIFlags);
1147 HI16.add(MO: HIOperand);
1148 HI16.cloneMemRefs(OtherMI: MI);
1149 HI16.addImm(Val: Pred).addReg(RegNo: PredReg);
1150 HI16.copyImplicitOps(OtherMI: MI);
1151 LLVM_DEBUG(dbgs() << "And: "; HI16.getInstr()->dump(););
1152 } else {
1153 LO16->getOperand(i: 0).setIsDead(DstIsDead);
1154 }
1155
1156 if (RequiresBundling)
1157 finalizeBundle(MBB, FirstMI: LO16->getIterator(), LastMI: MBBI->getIterator());
1158
1159 MI.eraseFromParent();
1160}
1161
1162// The size of the area, accessed by that VLSTM/VLLDM
1163// S0-S31 + FPSCR + 8 more bytes (VPR + pad, or just pad)
1164static const int CMSE_FP_SAVE_SIZE = 136;
1165
1166static void determineGPRegsToClear(const MachineInstr &MI,
1167 const std::initializer_list<unsigned> &Regs,
1168 SmallVectorImpl<unsigned> &ClearRegs) {
1169 SmallVector<unsigned, 4> OpRegs;
1170 for (const MachineOperand &Op : MI.operands()) {
1171 if (!Op.isReg() || !Op.isUse())
1172 continue;
1173 OpRegs.push_back(Elt: Op.getReg());
1174 }
1175 llvm::sort(C&: OpRegs);
1176
1177 std::set_difference(first1: Regs.begin(), last1: Regs.end(), first2: OpRegs.begin(), last2: OpRegs.end(),
1178 result: std::back_inserter(x&: ClearRegs));
1179}
1180
1181void ARMExpandPseudo::CMSEClearGPRegs(
1182 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
1183 const DebugLoc &DL, const SmallVectorImpl<unsigned> &ClearRegs,
1184 unsigned ClobberReg) {
1185
1186 if (STI->hasV8_1MMainlineOps()) {
1187 // Clear the registers using the CLRM instruction.
1188 MachineInstrBuilder CLRM =
1189 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::t2CLRM)).add(MOs: predOps(Pred: ARMCC::AL));
1190 for (unsigned R : ClearRegs)
1191 CLRM.addReg(RegNo: R, Flags: RegState::Define);
1192 CLRM.addReg(RegNo: ARM::APSR, Flags: RegState::Define);
1193 CLRM.addReg(RegNo: ARM::CPSR, Flags: RegState::Define | RegState::Implicit);
1194 } else {
1195 // Clear the registers and flags by copying ClobberReg into them.
1196 // (Baseline can't do a high register clear in one instruction).
1197 for (unsigned Reg : ClearRegs) {
1198 if (Reg == ClobberReg)
1199 continue;
1200 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::tMOVr), DestReg: Reg)
1201 .addReg(RegNo: ClobberReg)
1202 .add(MOs: predOps(Pred: ARMCC::AL));
1203 }
1204
1205 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::t2MSR_M))
1206 .addImm(Val: STI->hasDSP() ? 0xc00 : 0x800)
1207 .addReg(RegNo: ClobberReg)
1208 .add(MOs: predOps(Pred: ARMCC::AL));
1209 }
1210}
1211
1212// Find which FP registers need to be cleared. The parameter `ClearRegs` is
1213// initialised with all elements set to true, and this function resets all the
1214// bits, which correspond to register uses. Returns true if any floating point
1215// register is defined, false otherwise.
1216static bool determineFPRegsToClear(const MachineInstr &MI,
1217 BitVector &ClearRegs) {
1218 bool DefFP = false;
1219 for (const MachineOperand &Op : MI.operands()) {
1220 if (!Op.isReg())
1221 continue;
1222
1223 Register Reg = Op.getReg();
1224 if (Op.isDef()) {
1225 if ((Reg >= ARM::Q0 && Reg <= ARM::Q7) ||
1226 (Reg >= ARM::D0 && Reg <= ARM::D15) ||
1227 (Reg >= ARM::S0 && Reg <= ARM::S31))
1228 DefFP = true;
1229 continue;
1230 }
1231
1232 if (Reg >= ARM::Q0 && Reg <= ARM::Q7) {
1233 int R = Reg - ARM::Q0;
1234 ClearRegs.reset(I: R * 4, E: (R + 1) * 4);
1235 } else if (Reg >= ARM::D0 && Reg <= ARM::D15) {
1236 int R = Reg - ARM::D0;
1237 ClearRegs.reset(I: R * 2, E: (R + 1) * 2);
1238 } else if (Reg >= ARM::S0 && Reg <= ARM::S31) {
1239 ClearRegs[Reg - ARM::S0] = false;
1240 }
1241 }
1242 return DefFP;
1243}
1244
1245MachineBasicBlock &
1246ARMExpandPseudo::CMSEClearFPRegs(MachineBasicBlock &MBB,
1247 MachineBasicBlock::iterator MBBI) {
1248 BitVector ClearRegs(16, true);
1249 (void)determineFPRegsToClear(MI: *MBBI, ClearRegs);
1250
1251 if (STI->hasV8_1MMainlineOps())
1252 return CMSEClearFPRegsV81(MBB, MBBI, ClearRegs);
1253 else
1254 return CMSEClearFPRegsV8(MBB, MBBI, ClearRegs);
1255}
1256
1257// Clear the FP registers for v8.0-M, by copying over the content
1258// of LR. Uses R12 as a scratch register.
1259MachineBasicBlock &
1260ARMExpandPseudo::CMSEClearFPRegsV8(MachineBasicBlock &MBB,
1261 MachineBasicBlock::iterator MBBI,
1262 const BitVector &ClearRegs) {
1263 if (!STI->hasFPRegs())
1264 return MBB;
1265
1266 auto &RetI = *MBBI;
1267 const DebugLoc &DL = RetI.getDebugLoc();
1268
1269 // If optimising for minimum size, clear FP registers unconditionally.
1270 // Otherwise, check the CONTROL.SFPA (Secure Floating-Point Active) bit and
1271 // don't clear them if they belong to the non-secure state.
1272 MachineBasicBlock *ClearBB, *DoneBB;
1273 if (STI->hasMinSize()) {
1274 ClearBB = DoneBB = &MBB;
1275 } else {
1276 MachineFunction *MF = MBB.getParent();
1277 ClearBB = MF->CreateMachineBasicBlock(BB: MBB.getBasicBlock());
1278 DoneBB = MF->CreateMachineBasicBlock(BB: MBB.getBasicBlock());
1279
1280 MF->insert(MBBI: ++MBB.getIterator(), MBB: ClearBB);
1281 MF->insert(MBBI: ++ClearBB->getIterator(), MBB: DoneBB);
1282
1283 DoneBB->splice(Where: DoneBB->end(), Other: &MBB, From: MBBI, To: MBB.end());
1284 DoneBB->transferSuccessors(FromMBB: &MBB);
1285 MBB.addSuccessor(Succ: ClearBB);
1286 MBB.addSuccessor(Succ: DoneBB);
1287 ClearBB->addSuccessor(Succ: DoneBB);
1288
1289 // At the new basic blocks we need to have live-in the registers, used
1290 // for the return value as well as LR, used to clear registers.
1291 for (const MachineOperand &Op : RetI.operands()) {
1292 if (!Op.isReg())
1293 continue;
1294 Register Reg = Op.getReg();
1295 if (Reg == ARM::NoRegister || Reg == ARM::LR)
1296 continue;
1297 assert(Reg.isPhysical() && "Unallocated register");
1298 ClearBB->addLiveIn(PhysReg: Reg);
1299 DoneBB->addLiveIn(PhysReg: Reg);
1300 }
1301 ClearBB->addLiveIn(PhysReg: ARM::LR);
1302 DoneBB->addLiveIn(PhysReg: ARM::LR);
1303
1304 // Read the CONTROL register.
1305 BuildMI(BB&: MBB, I: MBB.end(), MIMD: DL, MCID: TII->get(Opcode: ARM::t2MRS_M), DestReg: ARM::R12)
1306 .addImm(Val: 20)
1307 .add(MOs: predOps(Pred: ARMCC::AL));
1308 // Check bit 3 (SFPA).
1309 BuildMI(BB&: MBB, I: MBB.end(), MIMD: DL, MCID: TII->get(Opcode: ARM::t2TSTri))
1310 .addReg(RegNo: ARM::R12)
1311 .addImm(Val: 8)
1312 .add(MOs: predOps(Pred: ARMCC::AL));
1313 // If SFPA is clear, jump over ClearBB to DoneBB.
1314 BuildMI(BB&: MBB, I: MBB.end(), MIMD: DL, MCID: TII->get(Opcode: ARM::tBcc))
1315 .addMBB(MBB: DoneBB)
1316 .addImm(Val: ARMCC::EQ)
1317 .addReg(RegNo: ARM::CPSR, Flags: RegState::Kill);
1318 }
1319
1320 // Emit the clearing sequence
1321 for (unsigned D = 0; D < 8; D++) {
1322 // Attempt to clear as double
1323 if (ClearRegs[D * 2 + 0] && ClearRegs[D * 2 + 1]) {
1324 unsigned Reg = ARM::D0 + D;
1325 BuildMI(BB: ClearBB, MIMD: DL, MCID: TII->get(Opcode: ARM::VMOVDRR), DestReg: Reg)
1326 .addReg(RegNo: ARM::LR)
1327 .addReg(RegNo: ARM::LR)
1328 .add(MOs: predOps(Pred: ARMCC::AL));
1329 } else {
1330 // Clear first part as single
1331 if (ClearRegs[D * 2 + 0]) {
1332 unsigned Reg = ARM::S0 + D * 2;
1333 BuildMI(BB: ClearBB, MIMD: DL, MCID: TII->get(Opcode: ARM::VMOVSR), DestReg: Reg)
1334 .addReg(RegNo: ARM::LR)
1335 .add(MOs: predOps(Pred: ARMCC::AL));
1336 }
1337 // Clear second part as single
1338 if (ClearRegs[D * 2 + 1]) {
1339 unsigned Reg = ARM::S0 + D * 2 + 1;
1340 BuildMI(BB: ClearBB, MIMD: DL, MCID: TII->get(Opcode: ARM::VMOVSR), DestReg: Reg)
1341 .addReg(RegNo: ARM::LR)
1342 .add(MOs: predOps(Pred: ARMCC::AL));
1343 }
1344 }
1345 }
1346
1347 // Clear FPSCR bits 0-4, 7, 28-31
1348 // The other bits are program global according to the AAPCS
1349 BuildMI(BB: ClearBB, MIMD: DL, MCID: TII->get(Opcode: ARM::VMRS), DestReg: ARM::R12)
1350 .add(MOs: predOps(Pred: ARMCC::AL));
1351 BuildMI(BB: ClearBB, MIMD: DL, MCID: TII->get(Opcode: ARM::t2BICri), DestReg: ARM::R12)
1352 .addReg(RegNo: ARM::R12)
1353 .addImm(Val: 0x0000009F)
1354 .add(MOs: predOps(Pred: ARMCC::AL))
1355 .add(MO: condCodeOp());
1356 BuildMI(BB: ClearBB, MIMD: DL, MCID: TII->get(Opcode: ARM::t2BICri), DestReg: ARM::R12)
1357 .addReg(RegNo: ARM::R12)
1358 .addImm(Val: 0xF0000000)
1359 .add(MOs: predOps(Pred: ARMCC::AL))
1360 .add(MO: condCodeOp());
1361 BuildMI(BB: ClearBB, MIMD: DL, MCID: TII->get(Opcode: ARM::VMSR))
1362 .addReg(RegNo: ARM::R12)
1363 .add(MOs: predOps(Pred: ARMCC::AL));
1364
1365 return *DoneBB;
1366}
1367
1368MachineBasicBlock &
1369ARMExpandPseudo::CMSEClearFPRegsV81(MachineBasicBlock &MBB,
1370 MachineBasicBlock::iterator MBBI,
1371 const BitVector &ClearRegs) {
1372 auto &RetI = *MBBI;
1373
1374 // Emit a sequence of VSCCLRM <sreglist> instructions, one instruction for
1375 // each contiguous sequence of S-registers.
1376 int Start = -1, End = -1;
1377 for (int S = 0, E = ClearRegs.size(); S != E; ++S) {
1378 if (ClearRegs[S] && S == End + 1) {
1379 End = S; // extend range
1380 continue;
1381 }
1382 // Emit current range.
1383 if (Start < End) {
1384 MachineInstrBuilder VSCCLRM =
1385 BuildMI(BB&: MBB, I: MBBI, MIMD: RetI.getDebugLoc(), MCID: TII->get(Opcode: ARM::VSCCLRMS))
1386 .add(MOs: predOps(Pred: ARMCC::AL));
1387 while (++Start <= End)
1388 VSCCLRM.addReg(RegNo: ARM::S0 + Start, Flags: RegState::Define);
1389 VSCCLRM.addReg(RegNo: ARM::VPR, Flags: RegState::Define);
1390 }
1391 Start = End = S;
1392 }
1393 // Emit last range.
1394 if (Start < End) {
1395 MachineInstrBuilder VSCCLRM =
1396 BuildMI(BB&: MBB, I: MBBI, MIMD: RetI.getDebugLoc(), MCID: TII->get(Opcode: ARM::VSCCLRMS))
1397 .add(MOs: predOps(Pred: ARMCC::AL));
1398 while (++Start <= End)
1399 VSCCLRM.addReg(RegNo: ARM::S0 + Start, Flags: RegState::Define);
1400 VSCCLRM.addReg(RegNo: ARM::VPR, Flags: RegState::Define);
1401 }
1402
1403 return MBB;
1404}
1405
1406void ARMExpandPseudo::CMSESaveClearFPRegs(
1407 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
1408 const LivePhysRegs &LiveRegs, SmallVectorImpl<unsigned> &ScratchRegs) {
1409 if (STI->hasV8_1MMainlineOps())
1410 CMSESaveClearFPRegsV81(MBB, MBBI, DL, LiveRegs);
1411 else if (STI->hasV8MMainlineOps())
1412 CMSESaveClearFPRegsV8(MBB, MBBI, DL, LiveRegs, ScratchRegs);
1413}
1414
1415// Save and clear FP registers if present
1416void ARMExpandPseudo::CMSESaveClearFPRegsV8(
1417 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
1418 const LivePhysRegs &LiveRegs, SmallVectorImpl<unsigned> &ScratchRegs) {
1419
1420 // Store an available register for FPSCR clearing
1421 assert(!ScratchRegs.empty());
1422 unsigned SpareReg = ScratchRegs.front();
1423
1424 // save space on stack for VLSTM
1425 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::tSUBspi), DestReg: ARM::SP)
1426 .addReg(RegNo: ARM::SP)
1427 .addImm(Val: CMSE_FP_SAVE_SIZE >> 2)
1428 .add(MOs: predOps(Pred: ARMCC::AL));
1429
1430 // Use ScratchRegs to store the fp regs
1431 std::vector<std::tuple<unsigned, unsigned, unsigned>> ClearedFPRegs;
1432 std::vector<unsigned> NonclearedFPRegs;
1433 bool ReturnsFPReg = false;
1434 for (const MachineOperand &Op : MBBI->operands()) {
1435 if (Op.isReg() && Op.isUse()) {
1436 Register Reg = Op.getReg();
1437 assert(!ARM::DPRRegClass.contains(Reg) ||
1438 ARM::DPR_VFP2RegClass.contains(Reg));
1439 assert(!ARM::QPRRegClass.contains(Reg));
1440 if (ARM::DPR_VFP2RegClass.contains(Reg)) {
1441 if (ScratchRegs.size() >= 2) {
1442 unsigned SaveReg2 = ScratchRegs.pop_back_val();
1443 unsigned SaveReg1 = ScratchRegs.pop_back_val();
1444 ClearedFPRegs.emplace_back(args&: Reg, args&: SaveReg1, args&: SaveReg2);
1445
1446 // Save the fp register to the normal registers
1447 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::VMOVRRD))
1448 .addReg(RegNo: SaveReg1, Flags: RegState::Define)
1449 .addReg(RegNo: SaveReg2, Flags: RegState::Define)
1450 .addReg(RegNo: Reg)
1451 .add(MOs: predOps(Pred: ARMCC::AL));
1452 } else {
1453 NonclearedFPRegs.push_back(x: Reg);
1454 }
1455 } else if (ARM::SPRRegClass.contains(Reg)) {
1456 if (ScratchRegs.size() >= 1) {
1457 unsigned SaveReg = ScratchRegs.pop_back_val();
1458 ClearedFPRegs.emplace_back(args&: Reg, args&: SaveReg, args: 0);
1459
1460 // Save the fp register to the normal registers
1461 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::VMOVRS), DestReg: SaveReg)
1462 .addReg(RegNo: Reg)
1463 .add(MOs: predOps(Pred: ARMCC::AL));
1464 } else {
1465 NonclearedFPRegs.push_back(x: Reg);
1466 }
1467 }
1468 } else if (Op.isReg() && Op.isDef()) {
1469 Register Reg = Op.getReg();
1470 if (ARM::SPRRegClass.contains(Reg) || ARM::DPRRegClass.contains(Reg) ||
1471 ARM::QPRRegClass.contains(Reg))
1472 ReturnsFPReg = true;
1473 }
1474 }
1475
1476 bool PassesFPReg = (!NonclearedFPRegs.empty() || !ClearedFPRegs.empty());
1477
1478 if (PassesFPReg || ReturnsFPReg)
1479 assert(STI->hasFPRegs() && "Subtarget needs fpregs");
1480
1481 // CVE-2024-7883
1482 //
1483 // The VLLDM/VLSTM instructions set up lazy state preservation, but they
1484 // execute as NOPs if the FP register file is not considered to contain
1485 // secure data, represented by the CONTROL_S.SFPA bit. This means that the
1486 // state of CONTROL_S.SFPA must be the same when these two instructions are
1487 // executed. That might not be the case if we haven't used any FP
1488 // instructions before the VLSTM, so CONTROL_S.SFPA is clear, but do have one
1489 // before the VLLDM, which sets it..
1490 //
1491 // If we can't prove that SFPA will be the same for the VLSTM and VLLDM, we
1492 // execute a "vmov s0, s0" instruction before the VLSTM to ensure that
1493 // CONTROL_S.SFPA is set for both.
1494 //
1495 // That can only happen for callees which take no FP arguments (or we'd have
1496 // inserted a VMOV above) and which return values in FP regs (so that we need
1497 // to use a VMOV to back-up the return value before the VLLDM). It also can't
1498 // happen if the call is dominated by other existing floating-point
1499 // instructions, but we don't currently check for that case.
1500 //
1501 // These conditions mean that we only emit this instruction when using the
1502 // hard-float ABI, which means we can assume that FP instructions are
1503 // available, and don't need to make it conditional like we do for the
1504 // CVE-2021-35465 workaround.
1505 if (ReturnsFPReg && !PassesFPReg) {
1506 bool S0Dead = !LiveRegs.contains(Reg: ARM::S0);
1507 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::VMOVS))
1508 .addReg(RegNo: ARM::S0, Flags: RegState::Define | getDeadRegState(B: S0Dead))
1509 .addReg(RegNo: ARM::S0, Flags: getUndefRegState(B: S0Dead))
1510 .add(MOs: predOps(Pred: ARMCC::AL));
1511 }
1512
1513 // Lazy store all fp registers to the stack.
1514 // This executes as NOP in the absence of floating-point support.
1515 MachineInstrBuilder VLSTM =
1516 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::VLSTM))
1517 .addReg(RegNo: ARM::SP)
1518 .add(MOs: predOps(Pred: ARMCC::AL))
1519 .addImm(Val: 0); // Represents a pseoudo register list, has no effect on
1520 // the encoding.
1521 // Mark non-live registers as undef
1522 for (MachineOperand &MO : VLSTM->implicit_operands()) {
1523 if (MO.isReg() && !MO.isDef()) {
1524 Register Reg = MO.getReg();
1525 MO.setIsUndef(!LiveRegs.contains(Reg));
1526 }
1527 }
1528
1529 // Restore all arguments
1530 for (const auto &Regs : ClearedFPRegs) {
1531 unsigned Reg, SaveReg1, SaveReg2;
1532 std::tie(args&: Reg, args&: SaveReg1, args&: SaveReg2) = Regs;
1533 if (ARM::DPR_VFP2RegClass.contains(Reg))
1534 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::VMOVDRR), DestReg: Reg)
1535 .addReg(RegNo: SaveReg1)
1536 .addReg(RegNo: SaveReg2)
1537 .add(MOs: predOps(Pred: ARMCC::AL));
1538 else if (ARM::SPRRegClass.contains(Reg))
1539 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::VMOVSR), DestReg: Reg)
1540 .addReg(RegNo: SaveReg1)
1541 .add(MOs: predOps(Pred: ARMCC::AL));
1542 }
1543
1544 for (unsigned Reg : NonclearedFPRegs) {
1545 if (ARM::DPR_VFP2RegClass.contains(Reg)) {
1546 if (STI->isLittle()) {
1547 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::VLDRD), DestReg: Reg)
1548 .addReg(RegNo: ARM::SP)
1549 .addImm(Val: (Reg - ARM::D0) * 2)
1550 .add(MOs: predOps(Pred: ARMCC::AL));
1551 } else {
1552 // For big-endian targets we need to load the two subregisters of Reg
1553 // manually because VLDRD would load them in wrong order
1554 MCRegister SReg0 = TRI->getSubReg(Reg, Idx: ARM::ssub_0);
1555 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::VLDRS), DestReg: SReg0)
1556 .addReg(RegNo: ARM::SP)
1557 .addImm(Val: (Reg - ARM::D0) * 2)
1558 .add(MOs: predOps(Pred: ARMCC::AL));
1559 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::VLDRS), DestReg: SReg0 + 1)
1560 .addReg(RegNo: ARM::SP)
1561 .addImm(Val: (Reg - ARM::D0) * 2 + 1)
1562 .add(MOs: predOps(Pred: ARMCC::AL));
1563 }
1564 } else if (ARM::SPRRegClass.contains(Reg)) {
1565 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::VLDRS), DestReg: Reg)
1566 .addReg(RegNo: ARM::SP)
1567 .addImm(Val: Reg - ARM::S0)
1568 .add(MOs: predOps(Pred: ARMCC::AL));
1569 }
1570 }
1571 // restore FPSCR from stack and clear bits 0-4, 7, 28-31
1572 // The other bits are program global according to the AAPCS
1573 if (PassesFPReg) {
1574 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::tLDRspi), DestReg: SpareReg)
1575 .addReg(RegNo: ARM::SP)
1576 .addImm(Val: 0x10)
1577 .add(MOs: predOps(Pred: ARMCC::AL));
1578 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::t2BICri), DestReg: SpareReg)
1579 .addReg(RegNo: SpareReg)
1580 .addImm(Val: 0x0000009F)
1581 .add(MOs: predOps(Pred: ARMCC::AL))
1582 .add(MO: condCodeOp());
1583 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::t2BICri), DestReg: SpareReg)
1584 .addReg(RegNo: SpareReg)
1585 .addImm(Val: 0xF0000000)
1586 .add(MOs: predOps(Pred: ARMCC::AL))
1587 .add(MO: condCodeOp());
1588 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::VMSR))
1589 .addReg(RegNo: SpareReg)
1590 .add(MOs: predOps(Pred: ARMCC::AL));
1591 // The ldr must happen after a floating point instruction. To prevent the
1592 // post-ra scheduler to mess with the order, we create a bundle.
1593 finalizeBundle(MBB, FirstMI: VLSTM->getIterator(), LastMI: MBBI->getIterator());
1594 }
1595}
1596
1597void ARMExpandPseudo::CMSESaveClearFPRegsV81(MachineBasicBlock &MBB,
1598 MachineBasicBlock::iterator MBBI,
1599 DebugLoc &DL,
1600 const LivePhysRegs &LiveRegs) {
1601 BitVector ClearRegs(32, true);
1602 bool DefFP = determineFPRegsToClear(MI: *MBBI, ClearRegs);
1603
1604 // If the instruction does not write to a FP register and no elements were
1605 // removed from the set, then no FP registers were used to pass
1606 // arguments/returns.
1607 if (!DefFP && ClearRegs.count() == ClearRegs.size()) {
1608 // save space on stack for VLSTM
1609 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::tSUBspi), DestReg: ARM::SP)
1610 .addReg(RegNo: ARM::SP)
1611 .addImm(Val: CMSE_FP_SAVE_SIZE >> 2)
1612 .add(MOs: predOps(Pred: ARMCC::AL));
1613
1614 // Lazy store all FP registers to the stack
1615 MachineInstrBuilder VLSTM =
1616 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::VLSTM))
1617 .addReg(RegNo: ARM::SP)
1618 .add(MOs: predOps(Pred: ARMCC::AL))
1619 .addImm(Val: 0); // Represents a pseoudo register list, has no effect on
1620 // the encoding.
1621 // Mark non-live registers as undef
1622 for (MachineOperand &MO : VLSTM->implicit_operands()) {
1623 if (MO.isReg() && !MO.isDef()) {
1624 Register Reg = MO.getReg();
1625 MO.setIsUndef(!LiveRegs.contains(Reg));
1626 }
1627 }
1628 } else {
1629 // Push all the callee-saved registers (s16-s31).
1630 MachineInstrBuilder VPUSH =
1631 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::VSTMSDB_UPD), DestReg: ARM::SP)
1632 .addReg(RegNo: ARM::SP)
1633 .add(MOs: predOps(Pred: ARMCC::AL));
1634 for (unsigned Reg = ARM::S16; Reg <= ARM::S31; ++Reg)
1635 VPUSH.addReg(RegNo: Reg);
1636
1637 // Clear FP registers with a VSCCLRM.
1638 (void)CMSEClearFPRegsV81(MBB, MBBI, ClearRegs);
1639
1640 // Save floating-point context.
1641 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::VSTR_FPCXTS_pre), DestReg: ARM::SP)
1642 .addReg(RegNo: ARM::SP)
1643 .addImm(Val: -8)
1644 .add(MOs: predOps(Pred: ARMCC::AL));
1645 }
1646}
1647
1648// Restore FP registers if present
1649void ARMExpandPseudo::CMSERestoreFPRegs(
1650 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
1651 SmallVectorImpl<unsigned> &AvailableRegs) {
1652 if (STI->hasV8_1MMainlineOps())
1653 CMSERestoreFPRegsV81(MBB, MBBI, DL, AvailableRegs);
1654 else if (STI->hasV8MMainlineOps())
1655 CMSERestoreFPRegsV8(MBB, MBBI, DL, AvailableRegs);
1656}
1657
1658void ARMExpandPseudo::CMSERestoreFPRegsV8(
1659 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
1660 SmallVectorImpl<unsigned> &AvailableRegs) {
1661
1662 // Keep a scratch register for the mitigation sequence.
1663 unsigned ScratchReg = ARM::NoRegister;
1664 if (STI->fixCMSE_CVE_2021_35465())
1665 ScratchReg = AvailableRegs.pop_back_val();
1666
1667 // Use AvailableRegs to store the fp regs
1668 std::vector<std::tuple<unsigned, unsigned, unsigned>> ClearedFPRegs;
1669 std::vector<unsigned> NonclearedFPRegs;
1670 for (const MachineOperand &Op : MBBI->operands()) {
1671 if (Op.isReg() && Op.isDef()) {
1672 Register Reg = Op.getReg();
1673 assert(!ARM::DPRRegClass.contains(Reg) ||
1674 ARM::DPR_VFP2RegClass.contains(Reg));
1675 assert(!ARM::QPRRegClass.contains(Reg));
1676 if (ARM::DPR_VFP2RegClass.contains(Reg)) {
1677 if (AvailableRegs.size() >= 2) {
1678 unsigned SaveReg2 = AvailableRegs.pop_back_val();
1679 unsigned SaveReg1 = AvailableRegs.pop_back_val();
1680 ClearedFPRegs.emplace_back(args&: Reg, args&: SaveReg1, args&: SaveReg2);
1681
1682 // Save the fp register to the normal registers
1683 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::VMOVRRD))
1684 .addReg(RegNo: SaveReg1, Flags: RegState::Define)
1685 .addReg(RegNo: SaveReg2, Flags: RegState::Define)
1686 .addReg(RegNo: Reg)
1687 .add(MOs: predOps(Pred: ARMCC::AL));
1688 } else {
1689 NonclearedFPRegs.push_back(x: Reg);
1690 }
1691 } else if (ARM::SPRRegClass.contains(Reg)) {
1692 if (AvailableRegs.size() >= 1) {
1693 unsigned SaveReg = AvailableRegs.pop_back_val();
1694 ClearedFPRegs.emplace_back(args&: Reg, args&: SaveReg, args: 0);
1695
1696 // Save the fp register to the normal registers
1697 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::VMOVRS), DestReg: SaveReg)
1698 .addReg(RegNo: Reg)
1699 .add(MOs: predOps(Pred: ARMCC::AL));
1700 } else {
1701 NonclearedFPRegs.push_back(x: Reg);
1702 }
1703 }
1704 }
1705 }
1706
1707 bool returnsFPReg = (!NonclearedFPRegs.empty() || !ClearedFPRegs.empty());
1708
1709 if (returnsFPReg)
1710 assert(STI->hasFPRegs() && "Subtarget needs fpregs");
1711
1712 // Push FP regs that cannot be restored via normal registers on the stack
1713 for (unsigned Reg : NonclearedFPRegs) {
1714 if (ARM::DPR_VFP2RegClass.contains(Reg))
1715 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::VSTRD))
1716 .addReg(RegNo: Reg)
1717 .addReg(RegNo: ARM::SP)
1718 .addImm(Val: (Reg - ARM::D0) * 2)
1719 .add(MOs: predOps(Pred: ARMCC::AL));
1720 else if (ARM::SPRRegClass.contains(Reg))
1721 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::VSTRS))
1722 .addReg(RegNo: Reg)
1723 .addReg(RegNo: ARM::SP)
1724 .addImm(Val: Reg - ARM::S0)
1725 .add(MOs: predOps(Pred: ARMCC::AL));
1726 }
1727
1728 // Lazy load fp regs from stack.
1729 // This executes as NOP in the absence of floating-point support.
1730 MachineInstrBuilder VLLDM =
1731 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::VLLDM))
1732 .addReg(RegNo: ARM::SP)
1733 .add(MOs: predOps(Pred: ARMCC::AL))
1734 .addImm(Val: 0); // Represents a pseoudo register list, has no effect on
1735 // the encoding.
1736
1737 if (STI->fixCMSE_CVE_2021_35465()) {
1738 auto Bundler = MIBundleBuilder(MBB, VLLDM);
1739 // Read the CONTROL register.
1740 Bundler.append(MI: BuildMI(MF&: *MBB.getParent(), MIMD: DL, MCID: TII->get(Opcode: ARM::t2MRS_M))
1741 .addReg(RegNo: ScratchReg, Flags: RegState::Define)
1742 .addImm(Val: 20)
1743 .add(MOs: predOps(Pred: ARMCC::AL)));
1744 // Check bit 3 (SFPA).
1745 Bundler.append(MI: BuildMI(MF&: *MBB.getParent(), MIMD: DL, MCID: TII->get(Opcode: ARM::t2TSTri))
1746 .addReg(RegNo: ScratchReg)
1747 .addImm(Val: 8)
1748 .add(MOs: predOps(Pred: ARMCC::AL)));
1749 // Emit the IT block.
1750 Bundler.append(MI: BuildMI(MF&: *MBB.getParent(), MIMD: DL, MCID: TII->get(Opcode: ARM::t2IT))
1751 .addImm(Val: ARMCC::NE)
1752 .addImm(Val: 8));
1753 // If SFPA is clear jump over to VLLDM, otherwise execute an instruction
1754 // which has no functional effect apart from causing context creation:
1755 // vmovne s0, s0. In the absence of FPU we emit .inst.w 0xeeb00a40,
1756 // which is defined as NOP if not executed.
1757 if (STI->hasFPRegs())
1758 Bundler.append(MI: BuildMI(MF&: *MBB.getParent(), MIMD: DL, MCID: TII->get(Opcode: ARM::VMOVS))
1759 .addReg(RegNo: ARM::S0, Flags: RegState::Define)
1760 .addReg(RegNo: ARM::S0, Flags: RegState::Undef)
1761 .add(MOs: predOps(Pred: ARMCC::NE)));
1762 else
1763 Bundler.append(MI: BuildMI(MF&: *MBB.getParent(), MIMD: DL, MCID: TII->get(Opcode: ARM::INLINEASM))
1764 .addExternalSymbol(FnName: ".inst.w 0xeeb00a40")
1765 .addImm(Val: InlineAsm::Extra_HasSideEffects));
1766 finalizeBundle(MBB, FirstMI: Bundler.begin(), LastMI: Bundler.end());
1767 }
1768
1769 // Restore all FP registers via normal registers
1770 for (const auto &Regs : ClearedFPRegs) {
1771 unsigned Reg, SaveReg1, SaveReg2;
1772 std::tie(args&: Reg, args&: SaveReg1, args&: SaveReg2) = Regs;
1773 if (ARM::DPR_VFP2RegClass.contains(Reg))
1774 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::VMOVDRR), DestReg: Reg)
1775 .addReg(RegNo: SaveReg1)
1776 .addReg(RegNo: SaveReg2)
1777 .add(MOs: predOps(Pred: ARMCC::AL));
1778 else if (ARM::SPRRegClass.contains(Reg))
1779 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::VMOVSR), DestReg: Reg)
1780 .addReg(RegNo: SaveReg1)
1781 .add(MOs: predOps(Pred: ARMCC::AL));
1782 }
1783
1784 // Pop the stack space
1785 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::tADDspi), DestReg: ARM::SP)
1786 .addReg(RegNo: ARM::SP)
1787 .addImm(Val: CMSE_FP_SAVE_SIZE >> 2)
1788 .add(MOs: predOps(Pred: ARMCC::AL));
1789}
1790
1791static bool definesOrUsesFPReg(const MachineInstr &MI) {
1792 for (const MachineOperand &Op : MI.operands()) {
1793 if (!Op.isReg())
1794 continue;
1795 Register Reg = Op.getReg();
1796 if ((Reg >= ARM::Q0 && Reg <= ARM::Q7) ||
1797 (Reg >= ARM::D0 && Reg <= ARM::D15) ||
1798 (Reg >= ARM::S0 && Reg <= ARM::S31))
1799 return true;
1800 }
1801 return false;
1802}
1803
1804void ARMExpandPseudo::CMSERestoreFPRegsV81(
1805 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc &DL,
1806 SmallVectorImpl<unsigned> &AvailableRegs) {
1807 if (!definesOrUsesFPReg(MI: *MBBI)) {
1808 if (STI->fixCMSE_CVE_2021_35465()) {
1809 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::VSCCLRMS))
1810 .add(MOs: predOps(Pred: ARMCC::AL))
1811 .addReg(RegNo: ARM::VPR, Flags: RegState::Define);
1812 }
1813
1814 // Load FP registers from stack.
1815 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::VLLDM))
1816 .addReg(RegNo: ARM::SP)
1817 .add(MOs: predOps(Pred: ARMCC::AL))
1818 .addImm(Val: 0); // Represents a pseoudo register list, has no effect on the
1819 // encoding.
1820
1821 // Pop the stack space
1822 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::tADDspi), DestReg: ARM::SP)
1823 .addReg(RegNo: ARM::SP)
1824 .addImm(Val: CMSE_FP_SAVE_SIZE >> 2)
1825 .add(MOs: predOps(Pred: ARMCC::AL));
1826 } else {
1827 // Restore the floating point context.
1828 BuildMI(BB&: MBB, I: MBBI, MIMD: MBBI->getDebugLoc(), MCID: TII->get(Opcode: ARM::VLDR_FPCXTS_post),
1829 DestReg: ARM::SP)
1830 .addReg(RegNo: ARM::SP)
1831 .addImm(Val: 8)
1832 .add(MOs: predOps(Pred: ARMCC::AL));
1833
1834 // Pop all the callee-saved registers (s16-s31).
1835 MachineInstrBuilder VPOP =
1836 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::VLDMSIA_UPD), DestReg: ARM::SP)
1837 .addReg(RegNo: ARM::SP)
1838 .add(MOs: predOps(Pred: ARMCC::AL));
1839 for (unsigned Reg = ARM::S16; Reg <= ARM::S31; ++Reg)
1840 VPOP.addReg(RegNo: Reg, Flags: RegState::Define);
1841 }
1842}
1843
1844static unsigned getCmpOpcode(bool IsThumb, Register LHS, Register RHS) {
1845 if (!IsThumb)
1846 return ARM::CMPrr;
1847 if (ARM::tGPRRegClass.contains(Reg: LHS) &&
1848 ARM::tGPRRegClass.contains(Reg: RHS))
1849 return ARM::tCMPr;
1850 return ARM::tCMPhir;
1851}
1852
1853/// Expand a CMP_SWAP pseudo-inst to an ldrex/strex loop as simply as
1854/// possible. This only gets used at -O0 so we don't care about efficiency of
1855/// the generated code.
1856bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock &MBB,
1857 MachineBasicBlock::iterator MBBI,
1858 unsigned LdrexOp, unsigned StrexOp,
1859 unsigned UxtOp,
1860 MachineBasicBlock::iterator &NextMBBI) {
1861 bool IsThumb = STI->isThumb();
1862 bool IsThumb1Only = STI->isThumb1Only();
1863 MachineInstr &MI = *MBBI;
1864 DebugLoc DL = MI.getDebugLoc();
1865 const MachineOperand &Dest = MI.getOperand(i: 0);
1866 Register TempReg = MI.getOperand(i: 1).getReg();
1867 // Duplicating undef operands into 2 instructions does not guarantee the same
1868 // value on both; However undef should be replaced by xzr anyway.
1869 assert(!MI.getOperand(2).isUndef() && "cannot handle undef");
1870 Register AddrReg = MI.getOperand(i: 2).getReg();
1871 Register DesiredReg = MI.getOperand(i: 3).getReg();
1872 Register NewReg = MI.getOperand(i: 4).getReg();
1873
1874 if (IsThumb) {
1875 assert(STI->hasV8MBaselineOps() &&
1876 "CMP_SWAP not expected to be custom expanded for Thumb1");
1877 assert((UxtOp == 0 || UxtOp == ARM::tUXTB || UxtOp == ARM::tUXTH) &&
1878 "ARMv8-M.baseline does not have t2UXTB/t2UXTH");
1879 assert((UxtOp == 0 || ARM::tGPRRegClass.contains(DesiredReg)) &&
1880 "DesiredReg used for UXT op must be tGPR");
1881 }
1882
1883 MachineFunction *MF = MBB.getParent();
1884 auto LoadCmpBB = MF->CreateMachineBasicBlock(BB: MBB.getBasicBlock());
1885 auto StoreBB = MF->CreateMachineBasicBlock(BB: MBB.getBasicBlock());
1886 auto DoneBB = MF->CreateMachineBasicBlock(BB: MBB.getBasicBlock());
1887
1888 MF->insert(MBBI: ++MBB.getIterator(), MBB: LoadCmpBB);
1889 MF->insert(MBBI: ++LoadCmpBB->getIterator(), MBB: StoreBB);
1890 MF->insert(MBBI: ++StoreBB->getIterator(), MBB: DoneBB);
1891
1892 if (UxtOp) {
1893 MachineInstrBuilder MIB =
1894 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: UxtOp), DestReg: DesiredReg)
1895 .addReg(RegNo: DesiredReg, Flags: RegState::Kill);
1896 if (!IsThumb)
1897 MIB.addImm(Val: 0);
1898 MIB.add(MOs: predOps(Pred: ARMCC::AL));
1899 }
1900
1901 // .Lloadcmp:
1902 // ldrex rDest, [rAddr]
1903 // cmp rDest, rDesired
1904 // bne .Ldone
1905
1906 MachineInstrBuilder MIB;
1907 MIB = BuildMI(BB: LoadCmpBB, MIMD: DL, MCID: TII->get(Opcode: LdrexOp), DestReg: Dest.getReg());
1908 MIB.addReg(RegNo: AddrReg);
1909 if (LdrexOp == ARM::t2LDREX)
1910 MIB.addImm(Val: 0); // a 32-bit Thumb ldrex (only) allows an offset.
1911 MIB.add(MOs: predOps(Pred: ARMCC::AL));
1912
1913 unsigned CMPrr = getCmpOpcode(IsThumb, LHS: Dest.getReg(), RHS: DesiredReg);
1914 BuildMI(BB: LoadCmpBB, MIMD: DL, MCID: TII->get(Opcode: CMPrr))
1915 .addReg(RegNo: Dest.getReg(), Flags: getKillRegState(B: Dest.isDead()))
1916 .addReg(RegNo: DesiredReg)
1917 .add(MOs: predOps(Pred: ARMCC::AL));
1918 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
1919 BuildMI(BB: LoadCmpBB, MIMD: DL, MCID: TII->get(Opcode: Bcc))
1920 .addMBB(MBB: DoneBB)
1921 .addImm(Val: ARMCC::NE)
1922 .addReg(RegNo: ARM::CPSR, Flags: RegState::Kill);
1923 LoadCmpBB->addSuccessor(Succ: DoneBB);
1924 LoadCmpBB->addSuccessor(Succ: StoreBB);
1925
1926 // .Lstore:
1927 // strex rTempReg, rNew, [rAddr]
1928 // cmp rTempReg, #0
1929 // bne .Lloadcmp
1930 MIB = BuildMI(BB: StoreBB, MIMD: DL, MCID: TII->get(Opcode: StrexOp), DestReg: TempReg)
1931 .addReg(RegNo: NewReg)
1932 .addReg(RegNo: AddrReg);
1933 if (StrexOp == ARM::t2STREX)
1934 MIB.addImm(Val: 0); // a 32-bit Thumb strex (only) allows an offset.
1935 MIB.add(MOs: predOps(Pred: ARMCC::AL));
1936
1937 unsigned CMPri =
1938 IsThumb ? (IsThumb1Only ? ARM::tCMPi8 : ARM::t2CMPri) : ARM::CMPri;
1939 BuildMI(BB: StoreBB, MIMD: DL, MCID: TII->get(Opcode: CMPri))
1940 .addReg(RegNo: TempReg, Flags: RegState::Kill)
1941 .addImm(Val: 0)
1942 .add(MOs: predOps(Pred: ARMCC::AL));
1943 BuildMI(BB: StoreBB, MIMD: DL, MCID: TII->get(Opcode: Bcc))
1944 .addMBB(MBB: LoadCmpBB)
1945 .addImm(Val: ARMCC::NE)
1946 .addReg(RegNo: ARM::CPSR, Flags: RegState::Kill);
1947 StoreBB->addSuccessor(Succ: LoadCmpBB);
1948 StoreBB->addSuccessor(Succ: DoneBB);
1949
1950 DoneBB->splice(Where: DoneBB->end(), Other: &MBB, From: MI, To: MBB.end());
1951 DoneBB->transferSuccessors(FromMBB: &MBB);
1952
1953 MBB.addSuccessor(Succ: LoadCmpBB);
1954
1955 NextMBBI = MBB.end();
1956 MI.eraseFromParent();
1957
1958 // Recompute livein lists.
1959 LivePhysRegs LiveRegs;
1960 computeAndAddLiveIns(LiveRegs, MBB&: *DoneBB);
1961 computeAndAddLiveIns(LiveRegs, MBB&: *StoreBB);
1962 computeAndAddLiveIns(LiveRegs, MBB&: *LoadCmpBB);
1963 // Do an extra pass around the loop to get loop carried registers right.
1964 StoreBB->clearLiveIns();
1965 computeAndAddLiveIns(LiveRegs, MBB&: *StoreBB);
1966 LoadCmpBB->clearLiveIns();
1967 computeAndAddLiveIns(LiveRegs, MBB&: *LoadCmpBB);
1968
1969 return true;
1970}
1971
1972/// ARM's ldrexd/strexd take a consecutive register pair (represented as a
1973/// single GPRPair register), Thumb's take two separate registers so we need to
1974/// extract the subregs from the pair.
1975static void addExclusiveRegPair(MachineInstrBuilder &MIB, MachineOperand &Reg,
1976 RegState Flags, bool IsThumb,
1977 const TargetRegisterInfo *TRI) {
1978 if (IsThumb) {
1979 Register RegLo = TRI->getSubReg(Reg: Reg.getReg(), Idx: ARM::gsub_0);
1980 Register RegHi = TRI->getSubReg(Reg: Reg.getReg(), Idx: ARM::gsub_1);
1981 MIB.addReg(RegNo: RegLo, Flags);
1982 MIB.addReg(RegNo: RegHi, Flags);
1983 } else
1984 MIB.addReg(RegNo: Reg.getReg(), Flags);
1985}
1986
1987/// Expand a 64-bit CMP_SWAP to an ldrexd/strexd loop.
1988bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
1989 MachineBasicBlock::iterator MBBI,
1990 MachineBasicBlock::iterator &NextMBBI) {
1991 bool IsThumb = STI->isThumb();
1992 assert(!STI->isThumb1Only() && "CMP_SWAP_64 unsupported under Thumb1!");
1993 MachineInstr &MI = *MBBI;
1994 DebugLoc DL = MI.getDebugLoc();
1995 MachineOperand &Dest = MI.getOperand(i: 0);
1996 // Duplicating undef operands into 2 instructions does not guarantee the same
1997 // value on both; However undef should be replaced by xzr anyway.
1998 assert(!MI.getOperand(1).isUndef() && "cannot handle undef");
1999 Register AddrAndTempReg = MI.getOperand(i: 1).getReg();
2000 Register AddrReg = TRI->getSubReg(Reg: AddrAndTempReg, Idx: ARM::gsub_0);
2001 Register TempReg = TRI->getSubReg(Reg: AddrAndTempReg, Idx: ARM::gsub_1);
2002 assert(MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
2003 "tied operands have different registers");
2004 Register DesiredReg = MI.getOperand(i: 3).getReg();
2005 MachineOperand New = MI.getOperand(i: 4);
2006 New.setIsKill(false);
2007
2008 Register DestLo = TRI->getSubReg(Reg: Dest.getReg(), Idx: ARM::gsub_0);
2009 Register DestHi = TRI->getSubReg(Reg: Dest.getReg(), Idx: ARM::gsub_1);
2010 Register DesiredLo = TRI->getSubReg(Reg: DesiredReg, Idx: ARM::gsub_0);
2011 Register DesiredHi = TRI->getSubReg(Reg: DesiredReg, Idx: ARM::gsub_1);
2012
2013 MachineFunction *MF = MBB.getParent();
2014 auto LoadCmpBB = MF->CreateMachineBasicBlock(BB: MBB.getBasicBlock());
2015 auto StoreBB = MF->CreateMachineBasicBlock(BB: MBB.getBasicBlock());
2016 auto DoneBB = MF->CreateMachineBasicBlock(BB: MBB.getBasicBlock());
2017
2018 MF->insert(MBBI: ++MBB.getIterator(), MBB: LoadCmpBB);
2019 MF->insert(MBBI: ++LoadCmpBB->getIterator(), MBB: StoreBB);
2020 MF->insert(MBBI: ++StoreBB->getIterator(), MBB: DoneBB);
2021
2022 // .Lloadcmp:
2023 // ldrexd rDestLo, rDestHi, [rAddr]
2024 // cmp rDestLo, rDesiredLo
2025 // sbcs dead rTempReg, rDestHi, rDesiredHi
2026 // bne .Ldone
2027 unsigned LDREXD = IsThumb ? ARM::t2LDREXD : ARM::LDREXD;
2028 MachineInstrBuilder MIB;
2029 MIB = BuildMI(BB: LoadCmpBB, MIMD: DL, MCID: TII->get(Opcode: LDREXD));
2030 addExclusiveRegPair(MIB, Reg&: Dest, Flags: RegState::Define, IsThumb, TRI);
2031 MIB.addReg(RegNo: AddrReg).add(MOs: predOps(Pred: ARMCC::AL));
2032
2033 unsigned CMPrrLo = getCmpOpcode(IsThumb, LHS: DestLo, RHS: DesiredLo);
2034 BuildMI(BB: LoadCmpBB, MIMD: DL, MCID: TII->get(Opcode: CMPrrLo))
2035 .addReg(RegNo: DestLo, Flags: getKillRegState(B: Dest.isDead()))
2036 .addReg(RegNo: DesiredLo)
2037 .add(MOs: predOps(Pred: ARMCC::AL));
2038
2039 unsigned CMPrrHi = getCmpOpcode(IsThumb, LHS: DestHi, RHS: DesiredHi);
2040 BuildMI(BB: LoadCmpBB, MIMD: DL, MCID: TII->get(Opcode: CMPrrHi))
2041 .addReg(RegNo: DestHi, Flags: getKillRegState(B: Dest.isDead()))
2042 .addReg(RegNo: DesiredHi)
2043 .addImm(Val: ARMCC::EQ)
2044 .addReg(RegNo: ARM::CPSR, Flags: RegState::Kill);
2045
2046 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
2047 BuildMI(BB: LoadCmpBB, MIMD: DL, MCID: TII->get(Opcode: Bcc))
2048 .addMBB(MBB: DoneBB)
2049 .addImm(Val: ARMCC::NE)
2050 .addReg(RegNo: ARM::CPSR, Flags: RegState::Kill);
2051 LoadCmpBB->addSuccessor(Succ: DoneBB);
2052 LoadCmpBB->addSuccessor(Succ: StoreBB);
2053
2054 // .Lstore:
2055 // strexd rTempReg, rNewLo, rNewHi, [rAddr]
2056 // cmp rTempReg, #0
2057 // bne .Lloadcmp
2058 unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD;
2059 MIB = BuildMI(BB: StoreBB, MIMD: DL, MCID: TII->get(Opcode: STREXD), DestReg: TempReg);
2060 RegState Flags = getKillRegState(B: New.isDead());
2061 addExclusiveRegPair(MIB, Reg&: New, Flags, IsThumb, TRI);
2062 MIB.addReg(RegNo: AddrReg).add(MOs: predOps(Pred: ARMCC::AL));
2063
2064 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri;
2065 BuildMI(BB: StoreBB, MIMD: DL, MCID: TII->get(Opcode: CMPri))
2066 .addReg(RegNo: TempReg, Flags: RegState::Kill)
2067 .addImm(Val: 0)
2068 .add(MOs: predOps(Pred: ARMCC::AL));
2069 BuildMI(BB: StoreBB, MIMD: DL, MCID: TII->get(Opcode: Bcc))
2070 .addMBB(MBB: LoadCmpBB)
2071 .addImm(Val: ARMCC::NE)
2072 .addReg(RegNo: ARM::CPSR, Flags: RegState::Kill);
2073 StoreBB->addSuccessor(Succ: LoadCmpBB);
2074 StoreBB->addSuccessor(Succ: DoneBB);
2075
2076 DoneBB->splice(Where: DoneBB->end(), Other: &MBB, From: MI, To: MBB.end());
2077 DoneBB->transferSuccessors(FromMBB: &MBB);
2078
2079 MBB.addSuccessor(Succ: LoadCmpBB);
2080
2081 NextMBBI = MBB.end();
2082 MI.eraseFromParent();
2083
2084 // Recompute livein lists.
2085 LivePhysRegs LiveRegs;
2086 computeAndAddLiveIns(LiveRegs, MBB&: *DoneBB);
2087 computeAndAddLiveIns(LiveRegs, MBB&: *StoreBB);
2088 computeAndAddLiveIns(LiveRegs, MBB&: *LoadCmpBB);
2089 // Do an extra pass around the loop to get loop carried registers right.
2090 StoreBB->clearLiveIns();
2091 computeAndAddLiveIns(LiveRegs, MBB&: *StoreBB);
2092 LoadCmpBB->clearLiveIns();
2093 computeAndAddLiveIns(LiveRegs, MBB&: *LoadCmpBB);
2094
2095 return true;
2096}
2097
2098static void CMSEPushCalleeSaves(const TargetInstrInfo &TII,
2099 MachineBasicBlock &MBB,
2100 MachineBasicBlock::iterator MBBI,
2101 Register JumpReg, const LivePhysRegs &LiveRegs,
2102 bool Thumb1Only) {
2103 const DebugLoc &DL = MBBI->getDebugLoc();
2104 if (Thumb1Only) { // push Lo and Hi regs separately
2105 MachineInstrBuilder PushMIB =
2106 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: ARM::tPUSH)).add(MOs: predOps(Pred: ARMCC::AL));
2107 for (unsigned Reg = ARM::R4; Reg < ARM::R8; ++Reg) {
2108 PushMIB.addReg(
2109 RegNo: Reg, Flags: getUndefRegState(B: Reg != JumpReg && !LiveRegs.contains(Reg)));
2110 }
2111
2112 // Thumb1 can only tPUSH low regs, so we copy the high regs to the low
2113 // regs that we just saved and push the low regs again, taking care to
2114 // not clobber JumpReg. If JumpReg is one of the low registers, push first
2115 // the values of r9-r11, and then r8. That would leave them ordered in
2116 // memory, and allow us to later pop them with a single instructions.
2117 // FIXME: Could also use any of r0-r3 that are free (including in the
2118 // first PUSH above).
2119 for (unsigned LoReg = ARM::R7, HiReg = ARM::R11; LoReg >= ARM::R4;
2120 --LoReg) {
2121 if (JumpReg == LoReg)
2122 continue;
2123 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: ARM::tMOVr), DestReg: LoReg)
2124 .addReg(RegNo: HiReg, Flags: getUndefRegState(B: !LiveRegs.contains(Reg: HiReg)))
2125 .add(MOs: predOps(Pred: ARMCC::AL));
2126 --HiReg;
2127 }
2128 MachineInstrBuilder PushMIB2 =
2129 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: ARM::tPUSH)).add(MOs: predOps(Pred: ARMCC::AL));
2130 for (unsigned Reg = ARM::R4; Reg < ARM::R8; ++Reg) {
2131 if (Reg == JumpReg)
2132 continue;
2133 PushMIB2.addReg(RegNo: Reg, Flags: RegState::Kill);
2134 }
2135
2136 // If we couldn't use a low register for temporary storage (because it was
2137 // the JumpReg), use r4 or r5, whichever is not JumpReg. It has already been
2138 // saved.
2139 if (JumpReg >= ARM::R4 && JumpReg <= ARM::R7) {
2140 Register LoReg = JumpReg == ARM::R4 ? ARM::R5 : ARM::R4;
2141 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: ARM::tMOVr), DestReg: LoReg)
2142 .addReg(RegNo: ARM::R8, Flags: getUndefRegState(B: !LiveRegs.contains(Reg: ARM::R8)))
2143 .add(MOs: predOps(Pred: ARMCC::AL));
2144 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: ARM::tPUSH))
2145 .add(MOs: predOps(Pred: ARMCC::AL))
2146 .addReg(RegNo: LoReg, Flags: RegState::Kill);
2147 }
2148 } else { // push Lo and Hi registers with a single instruction
2149 MachineInstrBuilder PushMIB =
2150 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: ARM::t2STMDB_UPD), DestReg: ARM::SP)
2151 .addReg(RegNo: ARM::SP)
2152 .add(MOs: predOps(Pred: ARMCC::AL));
2153 for (unsigned Reg = ARM::R4; Reg < ARM::R12; ++Reg) {
2154 PushMIB.addReg(
2155 RegNo: Reg, Flags: getUndefRegState(B: Reg != JumpReg && !LiveRegs.contains(Reg)));
2156 }
2157 }
2158}
2159
2160static void CMSEPopCalleeSaves(const TargetInstrInfo &TII,
2161 MachineBasicBlock &MBB,
2162 MachineBasicBlock::iterator MBBI,
2163 bool Thumb1Only) {
2164 const DebugLoc &DL = MBBI->getDebugLoc();
2165 if (Thumb1Only) {
2166 MachineInstrBuilder PopMIB =
2167 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: ARM::tPOP)).add(MOs: predOps(Pred: ARMCC::AL));
2168 for (int R = 0; R < 4; ++R) {
2169 PopMIB.addReg(RegNo: ARM::R4 + R, Flags: RegState::Define);
2170 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: ARM::tMOVr), DestReg: ARM::R8 + R)
2171 .addReg(RegNo: ARM::R4 + R, Flags: RegState::Kill)
2172 .add(MOs: predOps(Pred: ARMCC::AL));
2173 }
2174 MachineInstrBuilder PopMIB2 =
2175 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: ARM::tPOP)).add(MOs: predOps(Pred: ARMCC::AL));
2176 for (int R = 0; R < 4; ++R)
2177 PopMIB2.addReg(RegNo: ARM::R4 + R, Flags: RegState::Define);
2178 } else { // pop Lo and Hi registers with a single instruction
2179 MachineInstrBuilder PopMIB =
2180 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII.get(Opcode: ARM::t2LDMIA_UPD), DestReg: ARM::SP)
2181 .addReg(RegNo: ARM::SP)
2182 .add(MOs: predOps(Pred: ARMCC::AL));
2183 for (unsigned Reg = ARM::R4; Reg < ARM::R12; ++Reg)
2184 PopMIB.addReg(RegNo: Reg, Flags: RegState::Define);
2185 }
2186}
2187
2188bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
2189 MachineBasicBlock::iterator MBBI,
2190 MachineBasicBlock::iterator &NextMBBI) {
2191 MachineInstr &MI = *MBBI;
2192 unsigned Opcode = MI.getOpcode();
2193 switch (Opcode) {
2194 default:
2195 return false;
2196
2197 case ARM::VBSPd:
2198 case ARM::VBSPq: {
2199 Register DstReg = MI.getOperand(i: 0).getReg();
2200 if (DstReg == MI.getOperand(i: 3).getReg()) {
2201 // Expand to VBIT
2202 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBITd : ARM::VBITq;
2203 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: NewOpc))
2204 .add(MO: MI.getOperand(i: 0))
2205 .add(MO: MI.getOperand(i: 3))
2206 .add(MO: MI.getOperand(i: 2))
2207 .add(MO: MI.getOperand(i: 1))
2208 .addImm(Val: MI.getOperand(i: 4).getImm())
2209 .add(MO: MI.getOperand(i: 5));
2210 } else if (DstReg == MI.getOperand(i: 2).getReg()) {
2211 // Expand to VBIF
2212 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBIFd : ARM::VBIFq;
2213 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: NewOpc))
2214 .add(MO: MI.getOperand(i: 0))
2215 .add(MO: MI.getOperand(i: 2))
2216 .add(MO: MI.getOperand(i: 3))
2217 .add(MO: MI.getOperand(i: 1))
2218 .addImm(Val: MI.getOperand(i: 4).getImm())
2219 .add(MO: MI.getOperand(i: 5));
2220 } else {
2221 // Expand to VBSL
2222 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBSLd : ARM::VBSLq;
2223 if (DstReg == MI.getOperand(i: 1).getReg()) {
2224 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: NewOpc))
2225 .add(MO: MI.getOperand(i: 0))
2226 .add(MO: MI.getOperand(i: 1))
2227 .add(MO: MI.getOperand(i: 2))
2228 .add(MO: MI.getOperand(i: 3))
2229 .addImm(Val: MI.getOperand(i: 4).getImm())
2230 .add(MO: MI.getOperand(i: 5));
2231 } else {
2232 // Use move to satisfy constraints
2233 unsigned MoveOpc = Opcode == ARM::VBSPd ? ARM::VORRd : ARM::VORRq;
2234 RegState MO1Flags = getRegState(RegOp: MI.getOperand(i: 1)) & ~RegState::Kill;
2235 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: MoveOpc))
2236 .addReg(RegNo: DstReg,
2237 Flags: RegState::Define |
2238 getRenamableRegState(B: MI.getOperand(i: 0).isRenamable()))
2239 .addReg(RegNo: MI.getOperand(i: 1).getReg(), Flags: MO1Flags)
2240 .addReg(RegNo: MI.getOperand(i: 1).getReg(), Flags: MO1Flags)
2241 .addImm(Val: MI.getOperand(i: 4).getImm())
2242 .add(MO: MI.getOperand(i: 5));
2243 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: NewOpc))
2244 .add(MO: MI.getOperand(i: 0))
2245 .addReg(RegNo: DstReg,
2246 Flags: RegState::Kill |
2247 getRenamableRegState(B: MI.getOperand(i: 0).isRenamable()))
2248 .add(MO: MI.getOperand(i: 2))
2249 .add(MO: MI.getOperand(i: 3))
2250 .addImm(Val: MI.getOperand(i: 4).getImm())
2251 .add(MO: MI.getOperand(i: 5));
2252 }
2253 }
2254 MI.eraseFromParent();
2255 return true;
2256 }
2257
2258 case ARM::CLEANUPRET:
2259 case ARM::CATCHRET: {
2260 unsigned RetOpcode = STI->isThumb() ? ARM::tBX_RET : ARM::BX_RET;
2261 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: RetOpcode))
2262 .add(MOs: predOps(Pred: ARMCC::AL));
2263 MI.eraseFromParent();
2264 return true;
2265 }
2266 case ARM::TCRETURNdi:
2267 case ARM::TCRETURNri:
2268 case ARM::TCRETURNrinotr12: {
2269 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
2270 if (MBBI->getOpcode() == ARM::SEH_EpilogEnd)
2271 MBBI--;
2272 if (MBBI->getOpcode() == ARM::SEH_Nop_Ret)
2273 MBBI--;
2274 assert(MBBI->isReturn() &&
2275 "Can only insert epilog into returning blocks");
2276 unsigned RetOpcode = MBBI->getOpcode();
2277 DebugLoc dl = MBBI->getDebugLoc();
2278 const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>(
2279 MBB.getParent()->getSubtarget().getInstrInfo());
2280
2281 // Tail call return: adjust the stack pointer and jump to callee.
2282 MBBI = MBB.getLastNonDebugInstr();
2283 if (MBBI->getOpcode() == ARM::SEH_EpilogEnd)
2284 MBBI--;
2285 if (MBBI->getOpcode() == ARM::SEH_Nop_Ret)
2286 MBBI--;
2287 MachineOperand &JumpTarget = MBBI->getOperand(i: 0);
2288
2289 // Jump to label or value in register.
2290 if (RetOpcode == ARM::TCRETURNdi) {
2291 MachineFunction *MF = MBB.getParent();
2292 bool NeedsWinCFI = MF->getTarget().getMCAsmInfo().usesWindowsCFI() &&
2293 MF->getFunction().needsUnwindTableEntry();
2294 unsigned TCOpcode =
2295 STI->isThumb()
2296 ? ((STI->isTargetMachO() || NeedsWinCFI) ? ARM::tTAILJMPd
2297 : ARM::tTAILJMPdND)
2298 : ARM::TAILJMPd;
2299 MachineInstrBuilder MIB = BuildMI(BB&: MBB, I: MBBI, MIMD: dl, MCID: TII.get(Opcode: TCOpcode));
2300 if (JumpTarget.isGlobal())
2301 MIB.addGlobalAddress(GV: JumpTarget.getGlobal(), Offset: JumpTarget.getOffset(),
2302 TargetFlags: JumpTarget.getTargetFlags());
2303 else {
2304 assert(JumpTarget.isSymbol());
2305 MIB.addExternalSymbol(FnName: JumpTarget.getSymbolName(),
2306 TargetFlags: JumpTarget.getTargetFlags());
2307 }
2308
2309 // Add the default predicate in Thumb mode.
2310 if (STI->isThumb())
2311 MIB.add(MOs: predOps(Pred: ARMCC::AL));
2312 } else if (RetOpcode == ARM::TCRETURNri ||
2313 RetOpcode == ARM::TCRETURNrinotr12) {
2314 unsigned Opcode =
2315 STI->isThumb() ? ARM::tTAILJMPr
2316 : (STI->hasV4TOps() ? ARM::TAILJMPr : ARM::TAILJMPr4);
2317 BuildMI(BB&: MBB, I: MBBI, MIMD: dl,
2318 MCID: TII.get(Opcode))
2319 .addReg(RegNo: JumpTarget.getReg(), Flags: RegState::Kill);
2320 }
2321
2322 auto NewMI = std::prev(x: MBBI);
2323 for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i)
2324 NewMI->addOperand(Op: MBBI->getOperand(i));
2325
2326 NewMI->setCFIType(MF&: *MBB.getParent(), Type: MI.getCFIType());
2327
2328 // Update call info and delete the pseudo instruction TCRETURN.
2329 if (MI.isCandidateForAdditionalCallInfo())
2330 MI.getMF()->moveAdditionalCallInfo(Old: &MI, New: &*NewMI);
2331 // Copy nomerge flag over to new instruction.
2332 if (MI.getFlag(Flag: MachineInstr::NoMerge))
2333 NewMI->setFlag(MachineInstr::NoMerge);
2334 MBB.erase(I: MBBI);
2335
2336 MBBI = NewMI;
2337 return true;
2338 }
2339 case ARM::tBXNS_RET: {
2340 // For v8.0-M.Main we need to authenticate LR before clearing FPRs, which
2341 // uses R12 as a scratch register.
2342 if (!STI->hasV8_1MMainlineOps() && AFI->shouldSignReturnAddress())
2343 BuildMI(BB&: MBB, I: MBBI, MIMD: DebugLoc(), MCID: TII->get(Opcode: ARM::t2AUT));
2344
2345 MachineBasicBlock &AfterBB = CMSEClearFPRegs(MBB, MBBI);
2346
2347 if (STI->hasV8_1MMainlineOps()) {
2348 // Restore the non-secure floating point context.
2349 BuildMI(BB&: MBB, I: MBBI, MIMD: MBBI->getDebugLoc(),
2350 MCID: TII->get(Opcode: ARM::VLDR_FPCXTNS_post), DestReg: ARM::SP)
2351 .addReg(RegNo: ARM::SP)
2352 .addImm(Val: 4)
2353 .add(MOs: predOps(Pred: ARMCC::AL));
2354
2355 if (AFI->shouldSignReturnAddress())
2356 BuildMI(BB&: AfterBB, I: AfterBB.end(), MIMD: DebugLoc(), MCID: TII->get(Opcode: ARM::t2AUT));
2357 }
2358
2359 // Clear all GPR that are not a use of the return instruction.
2360 assert(llvm::all_of(MBBI->operands(), [](const MachineOperand &Op) {
2361 return !Op.isReg() || Op.getReg() != ARM::R12;
2362 }));
2363 SmallVector<unsigned, 5> ClearRegs;
2364 determineGPRegsToClear(
2365 MI: *MBBI, Regs: {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12}, ClearRegs);
2366 CMSEClearGPRegs(MBB&: AfterBB, MBBI: AfterBB.end(), DL: MBBI->getDebugLoc(), ClearRegs,
2367 ClobberReg: ARM::LR);
2368
2369 MachineInstrBuilder NewMI =
2370 BuildMI(BB&: AfterBB, I: AfterBB.end(), MIMD: MBBI->getDebugLoc(),
2371 MCID: TII->get(Opcode: ARM::tBXNS))
2372 .addReg(RegNo: ARM::LR)
2373 .add(MOs: predOps(Pred: ARMCC::AL));
2374 for (const MachineOperand &Op : MI.operands())
2375 NewMI->addOperand(Op);
2376 MI.eraseFromParent();
2377 return true;
2378 }
2379 case ARM::tBLXNS_CALL: {
2380 DebugLoc DL = MBBI->getDebugLoc();
2381 Register JumpReg = MBBI->getOperand(i: 0).getReg();
2382
2383 // Figure out which registers are live at the point immediately before the
2384 // call. When we indiscriminately push a set of registers, the live
2385 // registers are added as ordinary use operands, whereas dead registers
2386 // are "undef".
2387 LivePhysRegs LiveRegs(*TRI);
2388 LiveRegs.addLiveOuts(MBB);
2389 for (const MachineInstr &MI : make_range(x: MBB.rbegin(), y: MBBI.getReverse()))
2390 LiveRegs.stepBackward(MI);
2391 LiveRegs.stepBackward(MI: *MBBI);
2392
2393 CMSEPushCalleeSaves(TII: *TII, MBB, MBBI, JumpReg, LiveRegs,
2394 Thumb1Only: AFI->isThumb1OnlyFunction());
2395
2396 SmallVector<unsigned, 16> ClearRegs;
2397 determineGPRegsToClear(MI: *MBBI,
2398 Regs: {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4,
2399 ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9,
2400 ARM::R10, ARM::R11, ARM::R12},
2401 ClearRegs);
2402 auto OriginalClearRegs = ClearRegs;
2403
2404 // Get the first cleared register as a scratch (to use later with tBIC).
2405 // We need to use the first so we can ensure it is a low register.
2406 unsigned ScratchReg = ClearRegs.front();
2407
2408 // Clear LSB of JumpReg
2409 if (AFI->isThumb2Function()) {
2410 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::t2BICri), DestReg: JumpReg)
2411 .addReg(RegNo: JumpReg)
2412 .addImm(Val: 1)
2413 .add(MOs: predOps(Pred: ARMCC::AL))
2414 .add(MO: condCodeOp());
2415 } else {
2416 // We need to use an extra register to cope with 8M Baseline,
2417 // since we have saved all of the registers we are ok to trash a non
2418 // argument register here.
2419 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::tMOVi8), DestReg: ScratchReg)
2420 .add(MO: condCodeOp())
2421 .addImm(Val: 1)
2422 .add(MOs: predOps(Pred: ARMCC::AL));
2423 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::tBIC), DestReg: JumpReg)
2424 .addReg(RegNo: ARM::CPSR, Flags: RegState::Define)
2425 .addReg(RegNo: JumpReg)
2426 .addReg(RegNo: ScratchReg)
2427 .add(MOs: predOps(Pred: ARMCC::AL));
2428 }
2429
2430 CMSESaveClearFPRegs(MBB, MBBI, DL, LiveRegs,
2431 ScratchRegs&: ClearRegs); // save+clear FP regs with ClearRegs
2432 CMSEClearGPRegs(MBB, MBBI, DL, ClearRegs, ClobberReg: JumpReg);
2433
2434 const MachineInstrBuilder NewCall =
2435 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: ARM::tBLXNSr))
2436 .add(MOs: predOps(Pred: ARMCC::AL))
2437 .addReg(RegNo: JumpReg, Flags: RegState::Kill);
2438
2439 for (const MachineOperand &MO : llvm::drop_begin(RangeOrContainer: MI.operands()))
2440 NewCall->addOperand(Op: MO);
2441 if (MI.isCandidateForAdditionalCallInfo())
2442 MI.getMF()->moveAdditionalCallInfo(Old: &MI, New: NewCall.getInstr());
2443
2444 CMSERestoreFPRegs(MBB, MBBI, DL, AvailableRegs&: OriginalClearRegs); // restore FP registers
2445
2446 CMSEPopCalleeSaves(TII: *TII, MBB, MBBI, Thumb1Only: AFI->isThumb1OnlyFunction());
2447
2448 MI.eraseFromParent();
2449 return true;
2450 }
2451 case ARM::VMOVHcc:
2452 case ARM::VMOVScc:
2453 case ARM::VMOVDcc: {
2454 unsigned newOpc = Opcode != ARM::VMOVDcc ? ARM::VMOVS : ARM::VMOVD;
2455 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: newOpc),
2456 DestReg: MI.getOperand(i: 1).getReg())
2457 .add(MO: MI.getOperand(i: 2))
2458 .addImm(Val: MI.getOperand(i: 3).getImm()) // 'pred'
2459 .add(MO: MI.getOperand(i: 4))
2460 .add(MO: makeImplicit(MO: MI.getOperand(i: 1)));
2461
2462 MI.eraseFromParent();
2463 return true;
2464 }
2465 case ARM::t2MOVCCr:
2466 case ARM::MOVCCr: {
2467 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr;
2468 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: Opc),
2469 DestReg: MI.getOperand(i: 1).getReg())
2470 .add(MO: MI.getOperand(i: 2))
2471 .addImm(Val: MI.getOperand(i: 3).getImm()) // 'pred'
2472 .add(MO: MI.getOperand(i: 4))
2473 .add(MO: condCodeOp()) // 's' bit
2474 .add(MO: makeImplicit(MO: MI.getOperand(i: 1)));
2475
2476 MI.eraseFromParent();
2477 return true;
2478 }
2479 case ARM::MOVCCsi: {
2480 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: ARM::MOVsi),
2481 DestReg: (MI.getOperand(i: 1).getReg()))
2482 .add(MO: MI.getOperand(i: 2))
2483 .addImm(Val: MI.getOperand(i: 3).getImm())
2484 .addImm(Val: MI.getOperand(i: 4).getImm()) // 'pred'
2485 .add(MO: MI.getOperand(i: 5))
2486 .add(MO: condCodeOp()) // 's' bit
2487 .add(MO: makeImplicit(MO: MI.getOperand(i: 1)));
2488
2489 MI.eraseFromParent();
2490 return true;
2491 }
2492 case ARM::MOVCCsr: {
2493 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: ARM::MOVsr),
2494 DestReg: (MI.getOperand(i: 1).getReg()))
2495 .add(MO: MI.getOperand(i: 2))
2496 .add(MO: MI.getOperand(i: 3))
2497 .addImm(Val: MI.getOperand(i: 4).getImm())
2498 .addImm(Val: MI.getOperand(i: 5).getImm()) // 'pred'
2499 .add(MO: MI.getOperand(i: 6))
2500 .add(MO: condCodeOp()) // 's' bit
2501 .add(MO: makeImplicit(MO: MI.getOperand(i: 1)));
2502
2503 MI.eraseFromParent();
2504 return true;
2505 }
2506 case ARM::t2MOVCCi16:
2507 case ARM::MOVCCi16: {
2508 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16;
2509 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: NewOpc),
2510 DestReg: MI.getOperand(i: 1).getReg())
2511 .addImm(Val: MI.getOperand(i: 2).getImm())
2512 .addImm(Val: MI.getOperand(i: 3).getImm()) // 'pred'
2513 .add(MO: MI.getOperand(i: 4))
2514 .add(MO: makeImplicit(MO: MI.getOperand(i: 1)));
2515 MI.eraseFromParent();
2516 return true;
2517 }
2518 case ARM::t2MOVCCi:
2519 case ARM::MOVCCi: {
2520 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi;
2521 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: Opc),
2522 DestReg: MI.getOperand(i: 1).getReg())
2523 .addImm(Val: MI.getOperand(i: 2).getImm())
2524 .addImm(Val: MI.getOperand(i: 3).getImm()) // 'pred'
2525 .add(MO: MI.getOperand(i: 4))
2526 .add(MO: condCodeOp()) // 's' bit
2527 .add(MO: makeImplicit(MO: MI.getOperand(i: 1)));
2528
2529 MI.eraseFromParent();
2530 return true;
2531 }
2532 case ARM::t2MVNCCi:
2533 case ARM::MVNCCi: {
2534 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi;
2535 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: Opc),
2536 DestReg: MI.getOperand(i: 1).getReg())
2537 .addImm(Val: MI.getOperand(i: 2).getImm())
2538 .addImm(Val: MI.getOperand(i: 3).getImm()) // 'pred'
2539 .add(MO: MI.getOperand(i: 4))
2540 .add(MO: condCodeOp()) // 's' bit
2541 .add(MO: makeImplicit(MO: MI.getOperand(i: 1)));
2542
2543 MI.eraseFromParent();
2544 return true;
2545 }
2546 case ARM::t2MOVCClsl:
2547 case ARM::t2MOVCClsr:
2548 case ARM::t2MOVCCasr:
2549 case ARM::t2MOVCCror: {
2550 unsigned NewOpc;
2551 switch (Opcode) {
2552 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break;
2553 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break;
2554 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break;
2555 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break;
2556 default: llvm_unreachable("unexpected conditional move");
2557 }
2558 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: NewOpc),
2559 DestReg: MI.getOperand(i: 1).getReg())
2560 .add(MO: MI.getOperand(i: 2))
2561 .addImm(Val: MI.getOperand(i: 3).getImm())
2562 .addImm(Val: MI.getOperand(i: 4).getImm()) // 'pred'
2563 .add(MO: MI.getOperand(i: 5))
2564 .add(MO: condCodeOp()) // 's' bit
2565 .add(MO: makeImplicit(MO: MI.getOperand(i: 1)));
2566 MI.eraseFromParent();
2567 return true;
2568 }
2569 case ARM::Int_eh_sjlj_dispatchsetup: {
2570 MachineFunction &MF = *MI.getParent()->getParent();
2571 const ARMBaseRegisterInfo &RI = TII->getRegisterInfo();
2572 // For functions using a base pointer, we rematerialize it (via the frame
2573 // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it
2574 // for us. Otherwise, expand to nothing.
2575 if (RI.hasBasePointer(MF)) {
2576 int32_t NumBytes = AFI->getFramePtrSpillOffset();
2577 Register FramePtr = RI.getFrameRegister(MF);
2578 assert(MF.getSubtarget().getFrameLowering()->hasFP(MF) &&
2579 "base pointer without frame pointer?");
2580
2581 if (AFI->isThumb2Function()) {
2582 emitT2RegPlusImmediate(MBB, MBBI, dl: MI.getDebugLoc(), DestReg: ARM::R6,
2583 BaseReg: FramePtr, NumBytes: -NumBytes, Pred: ARMCC::AL, PredReg: 0, TII: *TII);
2584 } else if (AFI->isThumbFunction()) {
2585 emitThumbRegPlusImmediate(MBB, MBBI, dl: MI.getDebugLoc(), DestReg: ARM::R6,
2586 BaseReg: FramePtr, NumBytes: -NumBytes, TII: *TII, MRI: RI);
2587 } else {
2588 emitARMRegPlusImmediate(MBB, MBBI, dl: MI.getDebugLoc(), DestReg: ARM::R6,
2589 BaseReg: FramePtr, NumBytes: -NumBytes, Pred: ARMCC::AL, PredReg: 0,
2590 TII: *TII);
2591 }
2592 // If there's dynamic realignment, adjust for it.
2593 if (RI.hasStackRealignment(MF)) {
2594 MachineFrameInfo &MFI = MF.getFrameInfo();
2595 Align MaxAlign = MFI.getMaxAlign();
2596 assert (!AFI->isThumb1OnlyFunction());
2597 // Emit bic r6, r6, MaxAlign
2598 assert(MaxAlign <= Align(256) &&
2599 "The BIC instruction cannot encode "
2600 "immediates larger than 256 with all lower "
2601 "bits set.");
2602 unsigned bicOpc = AFI->isThumbFunction() ?
2603 ARM::t2BICri : ARM::BICri;
2604 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: bicOpc), DestReg: ARM::R6)
2605 .addReg(RegNo: ARM::R6, Flags: RegState::Kill)
2606 .addImm(Val: MaxAlign.value() - 1)
2607 .add(MOs: predOps(Pred: ARMCC::AL))
2608 .add(MO: condCodeOp());
2609 }
2610 }
2611 MI.eraseFromParent();
2612 return true;
2613 }
2614
2615 case ARM::LSRs1:
2616 case ARM::ASRs1: {
2617 // These are just fancy MOVs instructions.
2618 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: ARM::MOVsi),
2619 DestReg: MI.getOperand(i: 0).getReg())
2620 .add(MO: MI.getOperand(i: 1))
2621 .addImm(Val: ARM_AM::getSORegOpc(
2622 ShOp: (Opcode == ARM::LSRs1 ? ARM_AM::lsr : ARM_AM::asr), Imm: 1))
2623 .add(MOs: predOps(Pred: ARMCC::AL))
2624 .addReg(RegNo: ARM::CPSR, Flags: RegState::Define);
2625 MI.eraseFromParent();
2626 return true;
2627 }
2628 case ARM::RRX: {
2629 // This encodes as "MOVs Rd, Rm, rrx
2630 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: ARM::MOVsi),
2631 DestReg: MI.getOperand(i: 0).getReg())
2632 .add(MO: MI.getOperand(i: 1))
2633 .addImm(Val: ARM_AM::getSORegOpc(ShOp: ARM_AM::rrx, Imm: 0))
2634 .add(MOs: predOps(Pred: ARMCC::AL))
2635 .add(MO: condCodeOp())
2636 .copyImplicitOps(OtherMI: MI);
2637 MI.eraseFromParent();
2638 return true;
2639 }
2640 case ARM::tTPsoft:
2641 case ARM::TPsoft: {
2642 const bool Thumb = Opcode == ARM::tTPsoft;
2643
2644 MachineInstrBuilder MIB;
2645 MachineFunction *MF = MBB.getParent();
2646 if (STI->genLongCalls()) {
2647 MachineConstantPool *MCP = MF->getConstantPool();
2648 unsigned PCLabelID = AFI->createPICLabelUId();
2649 MachineConstantPoolValue *CPV =
2650 ARMConstantPoolSymbol::Create(C&: MF->getFunction().getContext(),
2651 s: "__aeabi_read_tp", ID: PCLabelID, PCAdj: 0);
2652 Register Reg = MI.getOperand(i: 0).getReg();
2653 MIB =
2654 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(),
2655 MCID: TII->get(Opcode: Thumb ? ARM::tLDRpci : ARM::LDRi12), DestReg: Reg)
2656 .addConstantPoolIndex(Idx: MCP->getConstantPoolIndex(V: CPV, Alignment: Align(4)));
2657 if (!Thumb)
2658 MIB.addImm(Val: 0);
2659 MIB.add(MOs: predOps(Pred: ARMCC::AL));
2660
2661 MIB =
2662 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(),
2663 MCID: TII->get(Opcode: Thumb ? gettBLXrOpcode(MF: *MF) : getBLXOpcode(MF: *MF)));
2664 if (Thumb)
2665 MIB.add(MOs: predOps(Pred: ARMCC::AL));
2666 MIB.addReg(RegNo: Reg, Flags: RegState::Kill);
2667 } else {
2668 MIB = BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(),
2669 MCID: TII->get(Opcode: Thumb ? ARM::tBL : ARM::BL));
2670 if (Thumb)
2671 MIB.add(MOs: predOps(Pred: ARMCC::AL));
2672 MIB.addExternalSymbol(FnName: "__aeabi_read_tp", TargetFlags: 0);
2673 }
2674
2675 MIB.cloneMemRefs(OtherMI: MI);
2676 MIB.copyImplicitOps(OtherMI: MI);
2677 // Update the call info.
2678 if (MI.isCandidateForAdditionalCallInfo())
2679 MF->moveAdditionalCallInfo(Old: &MI, New: &*MIB);
2680 MI.eraseFromParent();
2681 return true;
2682 }
2683 case ARM::tLDRpci_pic:
2684 case ARM::t2LDRpci_pic: {
2685 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
2686 ? ARM::tLDRpci : ARM::t2LDRpci;
2687 Register DstReg = MI.getOperand(i: 0).getReg();
2688 bool DstIsDead = MI.getOperand(i: 0).isDead();
2689 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: NewLdOpc), DestReg: DstReg)
2690 .add(MO: MI.getOperand(i: 1))
2691 .add(MOs: predOps(Pred: ARMCC::AL))
2692 .cloneMemRefs(OtherMI: MI)
2693 .copyImplicitOps(OtherMI: MI);
2694 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: ARM::tPICADD))
2695 .addReg(RegNo: DstReg, Flags: RegState::Define | getDeadRegState(B: DstIsDead))
2696 .addReg(RegNo: DstReg)
2697 .add(MO: MI.getOperand(i: 2))
2698 .copyImplicitOps(OtherMI: MI);
2699 MI.eraseFromParent();
2700 return true;
2701 }
2702
2703 case ARM::LDRLIT_ga_abs:
2704 case ARM::LDRLIT_ga_pcrel:
2705 case ARM::LDRLIT_ga_pcrel_ldr:
2706 case ARM::tLDRLIT_ga_abs:
2707 case ARM::t2LDRLIT_ga_pcrel:
2708 case ARM::tLDRLIT_ga_pcrel: {
2709 Register DstReg = MI.getOperand(i: 0).getReg();
2710 bool DstIsDead = MI.getOperand(i: 0).isDead();
2711 const MachineOperand &MO1 = MI.getOperand(i: 1);
2712 auto Flags = MO1.getTargetFlags();
2713 const GlobalValue *GV = MO1.getGlobal();
2714 bool IsARM = Opcode != ARM::tLDRLIT_ga_pcrel &&
2715 Opcode != ARM::tLDRLIT_ga_abs &&
2716 Opcode != ARM::t2LDRLIT_ga_pcrel;
2717 bool IsPIC =
2718 Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs;
2719 unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci;
2720 if (Opcode == ARM::t2LDRLIT_ga_pcrel)
2721 LDRLITOpc = ARM::t2LDRpci;
2722 unsigned PICAddOpc =
2723 IsARM
2724 ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
2725 : ARM::tPICADD;
2726
2727 // We need a new const-pool entry to load from.
2728 MachineConstantPool *MCP = MBB.getParent()->getConstantPool();
2729 unsigned ARMPCLabelIndex = 0;
2730 MachineConstantPoolValue *CPV;
2731
2732 if (IsPIC) {
2733 unsigned PCAdj = IsARM ? 8 : 4;
2734 auto Modifier = (Flags & ARMII::MO_GOT)
2735 ? ARMCP::GOT_PREL
2736 : ARMCP::no_modifier;
2737 ARMPCLabelIndex = AFI->createPICLabelUId();
2738 CPV = ARMConstantPoolConstant::Create(
2739 C: GV, ID: ARMPCLabelIndex, Kind: ARMCP::CPValue, PCAdj, Modifier,
2740 /*AddCurrentAddr*/ AddCurrentAddress: Modifier == ARMCP::GOT_PREL);
2741 } else
2742 CPV = ARMConstantPoolConstant::Create(GV, Modifier: ARMCP::no_modifier);
2743
2744 MachineInstrBuilder MIB =
2745 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: LDRLITOpc), DestReg: DstReg)
2746 .addConstantPoolIndex(Idx: MCP->getConstantPoolIndex(V: CPV, Alignment: Align(4)));
2747 if (IsARM)
2748 MIB.addImm(Val: 0);
2749 MIB.add(MOs: predOps(Pred: ARMCC::AL));
2750
2751 if (IsPIC) {
2752 MachineInstrBuilder MIB =
2753 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: PICAddOpc))
2754 .addReg(RegNo: DstReg, Flags: RegState::Define | getDeadRegState(B: DstIsDead))
2755 .addReg(RegNo: DstReg)
2756 .addImm(Val: ARMPCLabelIndex);
2757
2758 if (IsARM)
2759 MIB.add(MOs: predOps(Pred: ARMCC::AL));
2760 }
2761
2762 MI.eraseFromParent();
2763 return true;
2764 }
2765 case ARM::MOV_ga_pcrel:
2766 case ARM::MOV_ga_pcrel_ldr:
2767 case ARM::t2MOV_ga_pcrel: {
2768 // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode.
2769 unsigned LabelId = AFI->createPICLabelUId();
2770 Register DstReg = MI.getOperand(i: 0).getReg();
2771 bool DstIsDead = MI.getOperand(i: 0).isDead();
2772 const MachineOperand &MO1 = MI.getOperand(i: 1);
2773 const GlobalValue *GV = MO1.getGlobal();
2774 unsigned TF = MO1.getTargetFlags();
2775 bool isARM = Opcode != ARM::t2MOV_ga_pcrel;
2776 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel;
2777 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel;
2778 unsigned LO16TF = TF | ARMII::MO_LO16;
2779 unsigned HI16TF = TF | ARMII::MO_HI16;
2780 unsigned PICAddOpc = isARM
2781 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
2782 : ARM::tPICADD;
2783 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: LO16Opc), DestReg: DstReg)
2784 .addGlobalAddress(GV, Offset: MO1.getOffset(), TargetFlags: TF | LO16TF)
2785 .addImm(Val: LabelId)
2786 .copyImplicitOps(OtherMI: MI);
2787
2788 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: HI16Opc), DestReg: DstReg)
2789 .addReg(RegNo: DstReg)
2790 .addGlobalAddress(GV, Offset: MO1.getOffset(), TargetFlags: TF | HI16TF)
2791 .addImm(Val: LabelId)
2792 .copyImplicitOps(OtherMI: MI);
2793
2794 MachineInstrBuilder MIB3 = BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(),
2795 MCID: TII->get(Opcode: PICAddOpc))
2796 .addReg(RegNo: DstReg, Flags: RegState::Define | getDeadRegState(B: DstIsDead))
2797 .addReg(RegNo: DstReg).addImm(Val: LabelId);
2798 if (isARM) {
2799 MIB3.add(MOs: predOps(Pred: ARMCC::AL));
2800 if (Opcode == ARM::MOV_ga_pcrel_ldr)
2801 MIB3.cloneMemRefs(OtherMI: MI);
2802 }
2803 MIB3.copyImplicitOps(OtherMI: MI);
2804 MI.eraseFromParent();
2805 return true;
2806 }
2807
2808 case ARM::MOVi32imm:
2809 case ARM::MOVCCi32imm:
2810 case ARM::t2MOVi32imm:
2811 case ARM::t2MOVCCi32imm:
2812 ExpandMOV32BitImm(MBB, MBBI);
2813 return true;
2814
2815 case ARM::tMOVi32imm:
2816 ExpandTMOV32BitImm(MBB, MBBI);
2817 return true;
2818
2819 case ARM::tLEApcrelJT:
2820 // Inline jump tables are handled in ARMAsmPrinter.
2821 if (MI.getMF()->getJumpTableInfo()->getEntryKind() ==
2822 MachineJumpTableInfo::EK_Inline)
2823 return false;
2824
2825 // Use a 32-bit immediate move to generate the address of the jump table.
2826 assert(STI->isThumb() && "Non-inline jump tables expected only in thumb");
2827 ExpandTMOV32BitImm(MBB, MBBI);
2828 return true;
2829
2830 case ARM::SUBS_PC_LR: {
2831 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: ARM::SUBri), DestReg: ARM::PC)
2832 .addReg(RegNo: ARM::LR)
2833 .add(MO: MI.getOperand(i: 0))
2834 .add(MO: MI.getOperand(i: 1))
2835 .add(MO: MI.getOperand(i: 2))
2836 .addReg(RegNo: ARM::CPSR, Flags: RegState::Undef)
2837 .copyImplicitOps(OtherMI: MI);
2838 MI.eraseFromParent();
2839 return true;
2840 }
2841 case ARM::VLDMQIA: {
2842 unsigned NewOpc = ARM::VLDMDIA;
2843 MachineInstrBuilder MIB =
2844 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: NewOpc));
2845 unsigned OpIdx = 0;
2846
2847 // Grab the Q register destination.
2848 bool DstIsDead = MI.getOperand(i: OpIdx).isDead();
2849 Register DstReg = MI.getOperand(i: OpIdx++).getReg();
2850
2851 // Copy the source register.
2852 MIB.add(MO: MI.getOperand(i: OpIdx++));
2853
2854 // Copy the predicate operands.
2855 MIB.add(MO: MI.getOperand(i: OpIdx++));
2856 MIB.add(MO: MI.getOperand(i: OpIdx++));
2857
2858 // Add the destination operands (D subregs).
2859 Register D0 = TRI->getSubReg(Reg: DstReg, Idx: ARM::dsub_0);
2860 Register D1 = TRI->getSubReg(Reg: DstReg, Idx: ARM::dsub_1);
2861 MIB.addReg(RegNo: D0, Flags: RegState::Define | getDeadRegState(B: DstIsDead))
2862 .addReg(RegNo: D1, Flags: RegState::Define | getDeadRegState(B: DstIsDead));
2863
2864 // Add an implicit def for the super-register.
2865 MIB.addReg(RegNo: DstReg, Flags: RegState::ImplicitDefine | getDeadRegState(B: DstIsDead));
2866 MIB.copyImplicitOps(OtherMI: MI);
2867 MIB.cloneMemRefs(OtherMI: MI);
2868 MI.eraseFromParent();
2869 return true;
2870 }
2871
2872 case ARM::VSTMQIA: {
2873 unsigned NewOpc = ARM::VSTMDIA;
2874 MachineInstrBuilder MIB =
2875 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: NewOpc));
2876 unsigned OpIdx = 0;
2877
2878 // Grab the Q register source.
2879 bool SrcIsKill = MI.getOperand(i: OpIdx).isKill();
2880 Register SrcReg = MI.getOperand(i: OpIdx++).getReg();
2881
2882 // Copy the destination register.
2883 MachineOperand Dst(MI.getOperand(i: OpIdx++));
2884 MIB.add(MO: Dst);
2885
2886 // Copy the predicate operands.
2887 MIB.add(MO: MI.getOperand(i: OpIdx++));
2888 MIB.add(MO: MI.getOperand(i: OpIdx++));
2889
2890 // Add the source operands (D subregs).
2891 Register D0 = TRI->getSubReg(Reg: SrcReg, Idx: ARM::dsub_0);
2892 Register D1 = TRI->getSubReg(Reg: SrcReg, Idx: ARM::dsub_1);
2893 MIB.addReg(RegNo: D0, Flags: getKillRegState(B: SrcIsKill))
2894 .addReg(RegNo: D1, Flags: getKillRegState(B: SrcIsKill));
2895
2896 if (SrcIsKill) // Add an implicit kill for the Q register.
2897 MIB->addRegisterKilled(IncomingReg: SrcReg, RegInfo: TRI, AddIfNotFound: true);
2898
2899 MIB.copyImplicitOps(OtherMI: MI);
2900 MIB.cloneMemRefs(OtherMI: MI);
2901 MI.eraseFromParent();
2902 return true;
2903 }
2904
2905 case ARM::VLD2q8Pseudo:
2906 case ARM::VLD2q16Pseudo:
2907 case ARM::VLD2q32Pseudo:
2908 case ARM::VLD2q8PseudoWB_fixed:
2909 case ARM::VLD2q16PseudoWB_fixed:
2910 case ARM::VLD2q32PseudoWB_fixed:
2911 case ARM::VLD2q8PseudoWB_register:
2912 case ARM::VLD2q16PseudoWB_register:
2913 case ARM::VLD2q32PseudoWB_register:
2914 case ARM::VLD3d8Pseudo:
2915 case ARM::VLD3d16Pseudo:
2916 case ARM::VLD3d32Pseudo:
2917 case ARM::VLD1d8TPseudo:
2918 case ARM::VLD1d8TPseudoWB_fixed:
2919 case ARM::VLD1d8TPseudoWB_register:
2920 case ARM::VLD1d16TPseudo:
2921 case ARM::VLD1d16TPseudoWB_fixed:
2922 case ARM::VLD1d16TPseudoWB_register:
2923 case ARM::VLD1d32TPseudo:
2924 case ARM::VLD1d32TPseudoWB_fixed:
2925 case ARM::VLD1d32TPseudoWB_register:
2926 case ARM::VLD1d64TPseudo:
2927 case ARM::VLD1d64TPseudoWB_fixed:
2928 case ARM::VLD1d64TPseudoWB_register:
2929 case ARM::VLD3d8Pseudo_UPD:
2930 case ARM::VLD3d16Pseudo_UPD:
2931 case ARM::VLD3d32Pseudo_UPD:
2932 case ARM::VLD3q8Pseudo_UPD:
2933 case ARM::VLD3q16Pseudo_UPD:
2934 case ARM::VLD3q32Pseudo_UPD:
2935 case ARM::VLD3q8oddPseudo:
2936 case ARM::VLD3q16oddPseudo:
2937 case ARM::VLD3q32oddPseudo:
2938 case ARM::VLD3q8oddPseudo_UPD:
2939 case ARM::VLD3q16oddPseudo_UPD:
2940 case ARM::VLD3q32oddPseudo_UPD:
2941 case ARM::VLD4d8Pseudo:
2942 case ARM::VLD4d16Pseudo:
2943 case ARM::VLD4d32Pseudo:
2944 case ARM::VLD1d8QPseudo:
2945 case ARM::VLD1d8QPseudoWB_fixed:
2946 case ARM::VLD1d8QPseudoWB_register:
2947 case ARM::VLD1d16QPseudo:
2948 case ARM::VLD1d16QPseudoWB_fixed:
2949 case ARM::VLD1d16QPseudoWB_register:
2950 case ARM::VLD1d32QPseudo:
2951 case ARM::VLD1d32QPseudoWB_fixed:
2952 case ARM::VLD1d32QPseudoWB_register:
2953 case ARM::VLD1d64QPseudo:
2954 case ARM::VLD1d64QPseudoWB_fixed:
2955 case ARM::VLD1d64QPseudoWB_register:
2956 case ARM::VLD1q8HighQPseudo:
2957 case ARM::VLD1q8HighQPseudo_UPD:
2958 case ARM::VLD1q8LowQPseudo_UPD:
2959 case ARM::VLD1q8HighTPseudo:
2960 case ARM::VLD1q8HighTPseudo_UPD:
2961 case ARM::VLD1q8LowTPseudo_UPD:
2962 case ARM::VLD1q16HighQPseudo:
2963 case ARM::VLD1q16HighQPseudo_UPD:
2964 case ARM::VLD1q16LowQPseudo_UPD:
2965 case ARM::VLD1q16HighTPseudo:
2966 case ARM::VLD1q16HighTPseudo_UPD:
2967 case ARM::VLD1q16LowTPseudo_UPD:
2968 case ARM::VLD1q32HighQPseudo:
2969 case ARM::VLD1q32HighQPseudo_UPD:
2970 case ARM::VLD1q32LowQPseudo_UPD:
2971 case ARM::VLD1q32HighTPseudo:
2972 case ARM::VLD1q32HighTPseudo_UPD:
2973 case ARM::VLD1q32LowTPseudo_UPD:
2974 case ARM::VLD1q64HighQPseudo:
2975 case ARM::VLD1q64HighQPseudo_UPD:
2976 case ARM::VLD1q64LowQPseudo_UPD:
2977 case ARM::VLD1q64HighTPseudo:
2978 case ARM::VLD1q64HighTPseudo_UPD:
2979 case ARM::VLD1q64LowTPseudo_UPD:
2980 case ARM::VLD4d8Pseudo_UPD:
2981 case ARM::VLD4d16Pseudo_UPD:
2982 case ARM::VLD4d32Pseudo_UPD:
2983 case ARM::VLD4q8Pseudo_UPD:
2984 case ARM::VLD4q16Pseudo_UPD:
2985 case ARM::VLD4q32Pseudo_UPD:
2986 case ARM::VLD4q8oddPseudo:
2987 case ARM::VLD4q16oddPseudo:
2988 case ARM::VLD4q32oddPseudo:
2989 case ARM::VLD4q8oddPseudo_UPD:
2990 case ARM::VLD4q16oddPseudo_UPD:
2991 case ARM::VLD4q32oddPseudo_UPD:
2992 case ARM::VLD3DUPd8Pseudo:
2993 case ARM::VLD3DUPd16Pseudo:
2994 case ARM::VLD3DUPd32Pseudo:
2995 case ARM::VLD3DUPd8Pseudo_UPD:
2996 case ARM::VLD3DUPd16Pseudo_UPD:
2997 case ARM::VLD3DUPd32Pseudo_UPD:
2998 case ARM::VLD4DUPd8Pseudo:
2999 case ARM::VLD4DUPd16Pseudo:
3000 case ARM::VLD4DUPd32Pseudo:
3001 case ARM::VLD4DUPd8Pseudo_UPD:
3002 case ARM::VLD4DUPd16Pseudo_UPD:
3003 case ARM::VLD4DUPd32Pseudo_UPD:
3004 case ARM::VLD2DUPq8EvenPseudo:
3005 case ARM::VLD2DUPq8OddPseudo:
3006 case ARM::VLD2DUPq16EvenPseudo:
3007 case ARM::VLD2DUPq16OddPseudo:
3008 case ARM::VLD2DUPq32EvenPseudo:
3009 case ARM::VLD2DUPq32OddPseudo:
3010 case ARM::VLD2DUPq8OddPseudoWB_fixed:
3011 case ARM::VLD2DUPq8OddPseudoWB_register:
3012 case ARM::VLD2DUPq16OddPseudoWB_fixed:
3013 case ARM::VLD2DUPq16OddPseudoWB_register:
3014 case ARM::VLD2DUPq32OddPseudoWB_fixed:
3015 case ARM::VLD2DUPq32OddPseudoWB_register:
3016 case ARM::VLD3DUPq8EvenPseudo:
3017 case ARM::VLD3DUPq8OddPseudo:
3018 case ARM::VLD3DUPq16EvenPseudo:
3019 case ARM::VLD3DUPq16OddPseudo:
3020 case ARM::VLD3DUPq32EvenPseudo:
3021 case ARM::VLD3DUPq32OddPseudo:
3022 case ARM::VLD3DUPq8OddPseudo_UPD:
3023 case ARM::VLD3DUPq16OddPseudo_UPD:
3024 case ARM::VLD3DUPq32OddPseudo_UPD:
3025 case ARM::VLD4DUPq8EvenPseudo:
3026 case ARM::VLD4DUPq8OddPseudo:
3027 case ARM::VLD4DUPq16EvenPseudo:
3028 case ARM::VLD4DUPq16OddPseudo:
3029 case ARM::VLD4DUPq32EvenPseudo:
3030 case ARM::VLD4DUPq32OddPseudo:
3031 case ARM::VLD4DUPq8OddPseudo_UPD:
3032 case ARM::VLD4DUPq16OddPseudo_UPD:
3033 case ARM::VLD4DUPq32OddPseudo_UPD:
3034 ExpandVLD(MBBI);
3035 return true;
3036
3037 case ARM::VST2q8Pseudo:
3038 case ARM::VST2q16Pseudo:
3039 case ARM::VST2q32Pseudo:
3040 case ARM::VST2q8PseudoWB_fixed:
3041 case ARM::VST2q16PseudoWB_fixed:
3042 case ARM::VST2q32PseudoWB_fixed:
3043 case ARM::VST2q8PseudoWB_register:
3044 case ARM::VST2q16PseudoWB_register:
3045 case ARM::VST2q32PseudoWB_register:
3046 case ARM::VST3d8Pseudo:
3047 case ARM::VST3d16Pseudo:
3048 case ARM::VST3d32Pseudo:
3049 case ARM::VST1d8TPseudo:
3050 case ARM::VST1d8TPseudoWB_fixed:
3051 case ARM::VST1d8TPseudoWB_register:
3052 case ARM::VST1d16TPseudo:
3053 case ARM::VST1d16TPseudoWB_fixed:
3054 case ARM::VST1d16TPseudoWB_register:
3055 case ARM::VST1d32TPseudo:
3056 case ARM::VST1d32TPseudoWB_fixed:
3057 case ARM::VST1d32TPseudoWB_register:
3058 case ARM::VST1d64TPseudo:
3059 case ARM::VST1d64TPseudoWB_fixed:
3060 case ARM::VST1d64TPseudoWB_register:
3061 case ARM::VST3d8Pseudo_UPD:
3062 case ARM::VST3d16Pseudo_UPD:
3063 case ARM::VST3d32Pseudo_UPD:
3064 case ARM::VST3q8Pseudo_UPD:
3065 case ARM::VST3q16Pseudo_UPD:
3066 case ARM::VST3q32Pseudo_UPD:
3067 case ARM::VST3q8oddPseudo:
3068 case ARM::VST3q16oddPseudo:
3069 case ARM::VST3q32oddPseudo:
3070 case ARM::VST3q8oddPseudo_UPD:
3071 case ARM::VST3q16oddPseudo_UPD:
3072 case ARM::VST3q32oddPseudo_UPD:
3073 case ARM::VST4d8Pseudo:
3074 case ARM::VST4d16Pseudo:
3075 case ARM::VST4d32Pseudo:
3076 case ARM::VST1d8QPseudo:
3077 case ARM::VST1d8QPseudoWB_fixed:
3078 case ARM::VST1d8QPseudoWB_register:
3079 case ARM::VST1d16QPseudo:
3080 case ARM::VST1d16QPseudoWB_fixed:
3081 case ARM::VST1d16QPseudoWB_register:
3082 case ARM::VST1d32QPseudo:
3083 case ARM::VST1d32QPseudoWB_fixed:
3084 case ARM::VST1d32QPseudoWB_register:
3085 case ARM::VST1d64QPseudo:
3086 case ARM::VST1d64QPseudoWB_fixed:
3087 case ARM::VST1d64QPseudoWB_register:
3088 case ARM::VST4d8Pseudo_UPD:
3089 case ARM::VST4d16Pseudo_UPD:
3090 case ARM::VST4d32Pseudo_UPD:
3091 case ARM::VST1q8HighQPseudo:
3092 case ARM::VST1q8LowQPseudo_UPD:
3093 case ARM::VST1q8HighTPseudo:
3094 case ARM::VST1q8LowTPseudo_UPD:
3095 case ARM::VST1q16HighQPseudo:
3096 case ARM::VST1q16LowQPseudo_UPD:
3097 case ARM::VST1q16HighTPseudo:
3098 case ARM::VST1q16LowTPseudo_UPD:
3099 case ARM::VST1q32HighQPseudo:
3100 case ARM::VST1q32LowQPseudo_UPD:
3101 case ARM::VST1q32HighTPseudo:
3102 case ARM::VST1q32LowTPseudo_UPD:
3103 case ARM::VST1q64HighQPseudo:
3104 case ARM::VST1q64LowQPseudo_UPD:
3105 case ARM::VST1q64HighTPseudo:
3106 case ARM::VST1q64LowTPseudo_UPD:
3107 case ARM::VST1q8HighTPseudo_UPD:
3108 case ARM::VST1q16HighTPseudo_UPD:
3109 case ARM::VST1q32HighTPseudo_UPD:
3110 case ARM::VST1q64HighTPseudo_UPD:
3111 case ARM::VST1q8HighQPseudo_UPD:
3112 case ARM::VST1q16HighQPseudo_UPD:
3113 case ARM::VST1q32HighQPseudo_UPD:
3114 case ARM::VST1q64HighQPseudo_UPD:
3115 case ARM::VST4q8Pseudo_UPD:
3116 case ARM::VST4q16Pseudo_UPD:
3117 case ARM::VST4q32Pseudo_UPD:
3118 case ARM::VST4q8oddPseudo:
3119 case ARM::VST4q16oddPseudo:
3120 case ARM::VST4q32oddPseudo:
3121 case ARM::VST4q8oddPseudo_UPD:
3122 case ARM::VST4q16oddPseudo_UPD:
3123 case ARM::VST4q32oddPseudo_UPD:
3124 ExpandVST(MBBI);
3125 return true;
3126
3127 case ARM::VLD1LNq8Pseudo:
3128 case ARM::VLD1LNq16Pseudo:
3129 case ARM::VLD1LNq32Pseudo:
3130 case ARM::VLD1LNq8Pseudo_UPD:
3131 case ARM::VLD1LNq16Pseudo_UPD:
3132 case ARM::VLD1LNq32Pseudo_UPD:
3133 case ARM::VLD2LNd8Pseudo:
3134 case ARM::VLD2LNd16Pseudo:
3135 case ARM::VLD2LNd32Pseudo:
3136 case ARM::VLD2LNq16Pseudo:
3137 case ARM::VLD2LNq32Pseudo:
3138 case ARM::VLD2LNd8Pseudo_UPD:
3139 case ARM::VLD2LNd16Pseudo_UPD:
3140 case ARM::VLD2LNd32Pseudo_UPD:
3141 case ARM::VLD2LNq16Pseudo_UPD:
3142 case ARM::VLD2LNq32Pseudo_UPD:
3143 case ARM::VLD3LNd8Pseudo:
3144 case ARM::VLD3LNd16Pseudo:
3145 case ARM::VLD3LNd32Pseudo:
3146 case ARM::VLD3LNq16Pseudo:
3147 case ARM::VLD3LNq32Pseudo:
3148 case ARM::VLD3LNd8Pseudo_UPD:
3149 case ARM::VLD3LNd16Pseudo_UPD:
3150 case ARM::VLD3LNd32Pseudo_UPD:
3151 case ARM::VLD3LNq16Pseudo_UPD:
3152 case ARM::VLD3LNq32Pseudo_UPD:
3153 case ARM::VLD4LNd8Pseudo:
3154 case ARM::VLD4LNd16Pseudo:
3155 case ARM::VLD4LNd32Pseudo:
3156 case ARM::VLD4LNq16Pseudo:
3157 case ARM::VLD4LNq32Pseudo:
3158 case ARM::VLD4LNd8Pseudo_UPD:
3159 case ARM::VLD4LNd16Pseudo_UPD:
3160 case ARM::VLD4LNd32Pseudo_UPD:
3161 case ARM::VLD4LNq16Pseudo_UPD:
3162 case ARM::VLD4LNq32Pseudo_UPD:
3163 case ARM::VST1LNq8Pseudo:
3164 case ARM::VST1LNq16Pseudo:
3165 case ARM::VST1LNq32Pseudo:
3166 case ARM::VST1LNq8Pseudo_UPD:
3167 case ARM::VST1LNq16Pseudo_UPD:
3168 case ARM::VST1LNq32Pseudo_UPD:
3169 case ARM::VST2LNd8Pseudo:
3170 case ARM::VST2LNd16Pseudo:
3171 case ARM::VST2LNd32Pseudo:
3172 case ARM::VST2LNq16Pseudo:
3173 case ARM::VST2LNq32Pseudo:
3174 case ARM::VST2LNd8Pseudo_UPD:
3175 case ARM::VST2LNd16Pseudo_UPD:
3176 case ARM::VST2LNd32Pseudo_UPD:
3177 case ARM::VST2LNq16Pseudo_UPD:
3178 case ARM::VST2LNq32Pseudo_UPD:
3179 case ARM::VST3LNd8Pseudo:
3180 case ARM::VST3LNd16Pseudo:
3181 case ARM::VST3LNd32Pseudo:
3182 case ARM::VST3LNq16Pseudo:
3183 case ARM::VST3LNq32Pseudo:
3184 case ARM::VST3LNd8Pseudo_UPD:
3185 case ARM::VST3LNd16Pseudo_UPD:
3186 case ARM::VST3LNd32Pseudo_UPD:
3187 case ARM::VST3LNq16Pseudo_UPD:
3188 case ARM::VST3LNq32Pseudo_UPD:
3189 case ARM::VST4LNd8Pseudo:
3190 case ARM::VST4LNd16Pseudo:
3191 case ARM::VST4LNd32Pseudo:
3192 case ARM::VST4LNq16Pseudo:
3193 case ARM::VST4LNq32Pseudo:
3194 case ARM::VST4LNd8Pseudo_UPD:
3195 case ARM::VST4LNd16Pseudo_UPD:
3196 case ARM::VST4LNd32Pseudo_UPD:
3197 case ARM::VST4LNq16Pseudo_UPD:
3198 case ARM::VST4LNq32Pseudo_UPD:
3199 ExpandLaneOp(MBBI);
3200 return true;
3201
3202 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, Opc: ARM::VTBL3, IsExt: false); return true;
3203 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, Opc: ARM::VTBL4, IsExt: false); return true;
3204 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, Opc: ARM::VTBX3, IsExt: true); return true;
3205 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, Opc: ARM::VTBX4, IsExt: true); return true;
3206
3207 case ARM::MQQPRLoad:
3208 case ARM::MQQPRStore:
3209 case ARM::MQQQQPRLoad:
3210 case ARM::MQQQQPRStore:
3211 ExpandMQQPRLoadStore(MBBI);
3212 return true;
3213
3214 case ARM::tCMP_SWAP_8:
3215 assert(STI->isThumb());
3216 return ExpandCMP_SWAP(MBB, MBBI, LdrexOp: ARM::t2LDREXB, StrexOp: ARM::t2STREXB, UxtOp: ARM::tUXTB,
3217 NextMBBI);
3218 case ARM::tCMP_SWAP_16:
3219 assert(STI->isThumb());
3220 return ExpandCMP_SWAP(MBB, MBBI, LdrexOp: ARM::t2LDREXH, StrexOp: ARM::t2STREXH, UxtOp: ARM::tUXTH,
3221 NextMBBI);
3222 case ARM::tCMP_SWAP_32:
3223 assert(STI->isThumb());
3224 return ExpandCMP_SWAP(MBB, MBBI, LdrexOp: ARM::t2LDREX, StrexOp: ARM::t2STREX, UxtOp: 0, NextMBBI);
3225
3226 case ARM::CMP_SWAP_8:
3227 assert(!STI->isThumb());
3228 return ExpandCMP_SWAP(MBB, MBBI, LdrexOp: ARM::LDREXB, StrexOp: ARM::STREXB, UxtOp: ARM::UXTB,
3229 NextMBBI);
3230 case ARM::CMP_SWAP_16:
3231 assert(!STI->isThumb());
3232 return ExpandCMP_SWAP(MBB, MBBI, LdrexOp: ARM::LDREXH, StrexOp: ARM::STREXH, UxtOp: ARM::UXTH,
3233 NextMBBI);
3234 case ARM::CMP_SWAP_32:
3235 assert(!STI->isThumb());
3236 return ExpandCMP_SWAP(MBB, MBBI, LdrexOp: ARM::LDREX, StrexOp: ARM::STREX, UxtOp: 0, NextMBBI);
3237
3238 case ARM::CMP_SWAP_64:
3239 return ExpandCMP_SWAP_64(MBB, MBBI, NextMBBI);
3240
3241 case ARM::tBL_PUSHLR:
3242 case ARM::BL_PUSHLR: {
3243 const bool Thumb = Opcode == ARM::tBL_PUSHLR;
3244 Register Reg = MI.getOperand(i: 0).getReg();
3245 assert(Reg == ARM::LR && "expect LR register!");
3246 MachineInstrBuilder MIB;
3247 if (Thumb) {
3248 // push {lr}
3249 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: ARM::tPUSH))
3250 .add(MOs: predOps(Pred: ARMCC::AL))
3251 .addReg(RegNo: Reg);
3252
3253 // bl __gnu_mcount_nc
3254 MIB = BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: ARM::tBL));
3255 } else {
3256 // stmdb sp!, {lr}
3257 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: ARM::STMDB_UPD))
3258 .addReg(RegNo: ARM::SP, Flags: RegState::Define)
3259 .addReg(RegNo: ARM::SP)
3260 .add(MOs: predOps(Pred: ARMCC::AL))
3261 .addReg(RegNo: Reg);
3262
3263 // bl __gnu_mcount_nc
3264 MIB = BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: ARM::BL));
3265 }
3266 MIB.cloneMemRefs(OtherMI: MI);
3267 for (const MachineOperand &MO : llvm::drop_begin(RangeOrContainer: MI.operands()))
3268 MIB.add(MO);
3269 MI.eraseFromParent();
3270 return true;
3271 }
3272 case ARM::t2CALL_BTI: {
3273 MachineFunction &MF = *MI.getMF();
3274 MachineInstrBuilder MIB =
3275 BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: ARM::tBL));
3276 MIB.cloneMemRefs(OtherMI: MI);
3277 for (unsigned i = 0; i < MI.getNumOperands(); ++i)
3278 MIB.add(MO: MI.getOperand(i));
3279 if (MI.isCandidateForAdditionalCallInfo())
3280 MF.moveAdditionalCallInfo(Old: &MI, New: MIB.getInstr());
3281 MIBundleBuilder Bundler(MBB, MI);
3282 Bundler.append(MI: MIB);
3283 Bundler.append(MI: BuildMI(MF, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: ARM::t2BTI)));
3284 finalizeBundle(MBB, FirstMI: Bundler.begin(), LastMI: Bundler.end());
3285 MI.eraseFromParent();
3286 return true;
3287 }
3288 case ARM::LOADDUAL:
3289 case ARM::STOREDUAL: {
3290 Register PairReg = MI.getOperand(i: 0).getReg();
3291
3292 MachineInstrBuilder MIB =
3293 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(),
3294 MCID: TII->get(Opcode: Opcode == ARM::LOADDUAL ? ARM::LDRD : ARM::STRD))
3295 .addReg(RegNo: TRI->getSubReg(Reg: PairReg, Idx: ARM::gsub_0),
3296 Flags: getDefRegState(B: Opcode == ARM::LOADDUAL))
3297 .addReg(RegNo: TRI->getSubReg(Reg: PairReg, Idx: ARM::gsub_1),
3298 Flags: getDefRegState(B: Opcode == ARM::LOADDUAL));
3299 for (const MachineOperand &MO : llvm::drop_begin(RangeOrContainer: MI.operands()))
3300 MIB.add(MO);
3301 MIB.add(MOs: predOps(Pred: ARMCC::AL));
3302 MIB.cloneMemRefs(OtherMI: MI);
3303 MI.eraseFromParent();
3304 return true;
3305 }
3306 }
3307}
3308
3309bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
3310 bool Modified = false;
3311
3312 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
3313 while (MBBI != E) {
3314 MachineBasicBlock::iterator NMBBI = std::next(x: MBBI);
3315 Modified |= ExpandMI(MBB, MBBI, NextMBBI&: NMBBI);
3316 MBBI = NMBBI;
3317 }
3318
3319 return Modified;
3320}
3321
3322bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
3323 STI = &MF.getSubtarget<ARMSubtarget>();
3324 TII = STI->getInstrInfo();
3325 TRI = STI->getRegisterInfo();
3326 AFI = MF.getInfo<ARMFunctionInfo>();
3327
3328 LLVM_DEBUG(dbgs() << "********** ARM EXPAND PSEUDO INSTRUCTIONS **********\n"
3329 << "********** Function: " << MF.getName() << '\n');
3330
3331 bool Modified = false;
3332 for (MachineBasicBlock &MBB : MF)
3333 Modified |= ExpandMBB(MBB);
3334 if (VerifyARMPseudo)
3335 MF.verify(p: this, Banner: "After expanding ARM pseudo instructions.");
3336
3337 LLVM_DEBUG(dbgs() << "***************************************************\n");
3338 return Modified;
3339}
3340
3341/// createARMExpandPseudoPass - returns an instance of the pseudo instruction
3342/// expansion pass.
3343FunctionPass *llvm::createARMExpandPseudoPass() {
3344 return new ARMExpandPseudo();
3345}
3346