1//===-- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Thumb-1 implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "Thumb1InstrInfo.h"
14#include "ARMSubtarget.h"
15#include "llvm/ADT/BitVector.h"
16#include "llvm/CodeGen/LiveRegUnits.h"
17#include "llvm/CodeGen/MachineFrameInfo.h"
18#include "llvm/CodeGen/MachineInstrBuilder.h"
19#include "llvm/CodeGen/MachineMemOperand.h"
20#include "llvm/IR/Module.h"
21#include "llvm/MC/MCInst.h"
22#include "llvm/MC/MCInstBuilder.h"
23
24using namespace llvm;
25
26Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
27 : ARMBaseInstrInfo(STI, RI), RI(STI) {}
28
29/// Return the noop instruction to use for a noop.
30MCInst Thumb1InstrInfo::getNop() const {
31 return MCInstBuilder(ARM::tMOVr)
32 .addReg(Reg: ARM::R8)
33 .addReg(Reg: ARM::R8)
34 .addImm(Val: ARMCC::AL)
35 .addReg(Reg: 0);
36}
37
38unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
39 return 0;
40}
41
42void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
43 MachineBasicBlock::iterator I,
44 const DebugLoc &DL, Register DestReg,
45 Register SrcReg, bool KillSrc,
46 bool RenamableDest, bool RenamableSrc) const {
47 // Need to check the arch.
48 MachineFunction &MF = *MBB.getParent();
49 const ARMSubtarget &st = MF.getSubtarget<ARMSubtarget>();
50
51 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
52 "Thumb1 can only copy GPR registers");
53
54 if (st.hasV6Ops() || ARM::hGPRRegClass.contains(Reg: SrcReg) ||
55 !ARM::tGPRRegClass.contains(Reg: DestReg))
56 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: ARM::tMOVr), DestReg)
57 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrc))
58 .add(MOs: predOps(Pred: ARMCC::AL));
59 else {
60 const TargetRegisterInfo *RegInfo = st.getRegisterInfo();
61 LiveRegUnits UsedRegs(*RegInfo);
62 UsedRegs.addLiveOuts(MBB);
63
64 auto InstUpToI = MBB.end();
65 while (InstUpToI != I) {
66 // The pre-decrement is on purpose here.
67 // We want to have the liveness right before I.
68 --InstUpToI;
69 if (InstUpToI->isDebugInstr())
70 continue;
71 UsedRegs.stepBackward(MI: *InstUpToI);
72 }
73
74 if (UsedRegs.available(Reg: ARM::CPSR)) {
75 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: ARM::tMOVSr), DestReg)
76 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrc))
77 ->addRegisterDead(Reg: ARM::CPSR, RegInfo);
78 return;
79 }
80
81 // Use high register to move source to destination
82 // if movs is not an option.
83 BitVector Allocatable = RegInfo->getAllocatableSet(
84 MF, RC: RegInfo->getRegClass(i: ARM::hGPRRegClassID));
85
86 Register TmpReg = ARM::NoRegister;
87 // Prefer R12 as it is known to not be preserved anyway
88 if (UsedRegs.available(Reg: ARM::R12) && Allocatable.test(Idx: ARM::R12)) {
89 TmpReg = ARM::R12;
90 } else {
91 for (Register Reg : Allocatable.set_bits()) {
92 if (UsedRegs.available(Reg)) {
93 TmpReg = Reg;
94 break;
95 }
96 }
97 }
98
99 if (TmpReg) {
100 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: ARM::tMOVr), DestReg: TmpReg)
101 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrc))
102 .add(MOs: predOps(Pred: ARMCC::AL));
103 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: ARM::tMOVr), DestReg)
104 .addReg(RegNo: TmpReg, Flags: getKillRegState(B: true))
105 .add(MOs: predOps(Pred: ARMCC::AL));
106 return;
107 }
108
109 // 'MOV lo, lo' is unpredictable on < v6, so use the stack to do it
110 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: ARM::tPUSH))
111 .add(MOs: predOps(Pred: ARMCC::AL))
112 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrc));
113 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: ARM::tPOP))
114 .add(MOs: predOps(Pred: ARMCC::AL))
115 .addReg(RegNo: DestReg, Flags: getDefRegState(B: true));
116 }
117}
118
119void Thumb1InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
120 MachineBasicBlock::iterator I,
121 Register SrcReg, bool isKill, int FI,
122 const TargetRegisterClass *RC,
123 Register VReg,
124 MachineInstr::MIFlag Flags) const {
125 assert((RC == &ARM::tGPRRegClass ||
126 (SrcReg.isPhysical() && isARMLowRegister(SrcReg))) &&
127 "Unknown regclass!");
128
129 if (RC == &ARM::tGPRRegClass ||
130 (SrcReg.isPhysical() && isARMLowRegister(Reg: SrcReg))) {
131 DebugLoc DL;
132 if (I != MBB.end()) DL = I->getDebugLoc();
133
134 MachineFunction &MF = *MBB.getParent();
135 MachineFrameInfo &MFI = MF.getFrameInfo();
136 MachineMemOperand *MMO = MF.getMachineMemOperand(
137 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI), F: MachineMemOperand::MOStore,
138 Size: MFI.getObjectSize(ObjectIdx: FI), BaseAlignment: MFI.getObjectAlign(ObjectIdx: FI));
139 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: ARM::tSTRspi))
140 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill))
141 .addFrameIndex(Idx: FI)
142 .addImm(Val: 0)
143 .addMemOperand(MMO)
144 .add(MOs: predOps(Pred: ARMCC::AL));
145 }
146}
147
148void Thumb1InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
149 MachineBasicBlock::iterator I,
150 Register DestReg, int FI,
151 const TargetRegisterClass *RC,
152 Register VReg, unsigned SubReg,
153 MachineInstr::MIFlag Flags) const {
154 assert((RC->hasSuperClassEq(&ARM::tGPRRegClass) ||
155 (DestReg.isPhysical() && isARMLowRegister(DestReg))) &&
156 "Unknown regclass!");
157
158 if (RC->hasSuperClassEq(RC: &ARM::tGPRRegClass) ||
159 (DestReg.isPhysical() && isARMLowRegister(Reg: DestReg))) {
160 DebugLoc DL;
161 if (I != MBB.end()) DL = I->getDebugLoc();
162
163 MachineFunction &MF = *MBB.getParent();
164 MachineFrameInfo &MFI = MF.getFrameInfo();
165 MachineMemOperand *MMO = MF.getMachineMemOperand(
166 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI), F: MachineMemOperand::MOLoad,
167 Size: MFI.getObjectSize(ObjectIdx: FI), BaseAlignment: MFI.getObjectAlign(ObjectIdx: FI));
168 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: ARM::tLDRspi), DestReg)
169 .addFrameIndex(Idx: FI)
170 .addImm(Val: 0)
171 .addMemOperand(MMO)
172 .add(MOs: predOps(Pred: ARMCC::AL));
173 }
174}
175
176void Thumb1InstrInfo::expandLoadStackGuard(
177 MachineBasicBlock::iterator MI) const {
178 MachineFunction &MF = *MI->getParent()->getParent();
179 const ARMSubtarget &ST = MF.getSubtarget<ARMSubtarget>();
180 const auto *GV = cast<GlobalValue>(Val: (*MI->memoperands_begin())->getValue());
181
182 assert(MF.getFunction().getParent()->getStackProtectorGuard() != "tls" &&
183 "TLS stack protector not supported for Thumb1 targets");
184
185 unsigned Instr;
186 if (!GV->isDSOLocal())
187 Instr = ARM::tLDRLIT_ga_pcrel;
188 else if (ST.genExecuteOnly() && ST.hasV8MBaselineOps())
189 Instr = ARM::t2MOVi32imm;
190 else if (ST.genExecuteOnly())
191 Instr = ARM::tMOVi32imm;
192 else
193 Instr = ARM::tLDRLIT_ga_abs;
194 expandLoadStackGuardBase(MI, LoadImmOpc: Instr, LoadOpc: ARM::tLDRi);
195}
196
197bool Thumb1InstrInfo::canCopyGluedNodeDuringSchedule(SDNode *N) const {
198 // In Thumb1 the scheduler may need to schedule a cross-copy between GPRS and CPSR
199 // but this is not always possible there, so allow the Scheduler to clone tADCS and tSBCS
200 // even if they have glue.
201 // FIXME. Actually implement the cross-copy where it is possible (post v6)
202 // because these copies entail more spilling.
203 unsigned Opcode = N->getMachineOpcode();
204 if (Opcode == ARM::tADCS || Opcode == ARM::tSBCS)
205 return true;
206
207 return false;
208}
209