1//===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Hexagon implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "HexagonInstrInfo.h"
14#include "HexagonFrameLowering.h"
15#include "HexagonHazardRecognizer.h"
16#include "HexagonRegisterInfo.h"
17#include "HexagonSubtarget.h"
18#include "llvm/ADT/ArrayRef.h"
19#include "llvm/ADT/SmallPtrSet.h"
20#include "llvm/ADT/SmallVector.h"
21#include "llvm/ADT/StringExtras.h"
22#include "llvm/ADT/StringRef.h"
23#include "llvm/CodeGen/DFAPacketizer.h"
24#include "llvm/CodeGen/LiveIntervals.h"
25#include "llvm/CodeGen/LivePhysRegs.h"
26#include "llvm/CodeGen/MachineBasicBlock.h"
27#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineInstr.h"
31#include "llvm/CodeGen/MachineInstrBuilder.h"
32#include "llvm/CodeGen/MachineInstrBundle.h"
33#include "llvm/CodeGen/MachineMemOperand.h"
34#include "llvm/CodeGen/MachineOperand.h"
35#include "llvm/CodeGen/MachineRegisterInfo.h"
36#include "llvm/CodeGen/ScheduleDAG.h"
37#include "llvm/CodeGen/TargetInstrInfo.h"
38#include "llvm/CodeGen/TargetOpcodes.h"
39#include "llvm/CodeGen/TargetRegisterInfo.h"
40#include "llvm/CodeGen/TargetSubtargetInfo.h"
41#include "llvm/CodeGenTypes/MachineValueType.h"
42#include "llvm/IR/DebugLoc.h"
43#include "llvm/IR/GlobalVariable.h"
44#include "llvm/MC/MCAsmInfo.h"
45#include "llvm/MC/MCInstBuilder.h"
46#include "llvm/MC/MCInstrDesc.h"
47#include "llvm/MC/MCInstrItineraries.h"
48#include "llvm/Support/BranchProbability.h"
49#include "llvm/Support/CommandLine.h"
50#include "llvm/Support/Debug.h"
51#include "llvm/Support/ErrorHandling.h"
52#include "llvm/Support/MathExtras.h"
53#include "llvm/Support/raw_ostream.h"
54#include "llvm/Target/TargetMachine.h"
55#include <cassert>
56#include <cstdint>
57#include <cstring>
58#include <iterator>
59#include <optional>
60#include <string>
61#include <utility>
62
63using namespace llvm;
64
65#define DEBUG_TYPE "hexagon-instrinfo"
66
67#define GET_INSTRINFO_CTOR_DTOR
68#define GET_INSTRMAP_INFO
69#include "HexagonDepTimingClasses.h"
70#include "HexagonGenDFAPacketizer.inc"
71#include "HexagonGenInstrInfo.inc"
72
73cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
74 cl::init(Val: false), cl::desc("Do not consider inline-asm a scheduling/"
75 "packetization boundary."));
76
77static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction",
78 cl::Hidden, cl::init(Val: true), cl::desc("Enable branch prediction"));
79
80static cl::opt<bool> DisableNVSchedule(
81 "disable-hexagon-nv-schedule", cl::Hidden,
82 cl::desc("Disable schedule adjustment for new value stores."));
83
84static cl::opt<bool> EnableTimingClassLatency(
85 "enable-timing-class-latency", cl::Hidden, cl::init(Val: false),
86 cl::desc("Enable timing class latency"));
87
88static cl::opt<bool> EnableALUForwarding(
89 "enable-alu-forwarding", cl::Hidden, cl::init(Val: true),
90 cl::desc("Enable vec alu forwarding"));
91
92static cl::opt<bool> EnableACCForwarding(
93 "enable-acc-forwarding", cl::Hidden, cl::init(Val: true),
94 cl::desc("Enable vec acc forwarding"));
95
96static cl::opt<bool> BranchRelaxAsmLarge("branch-relax-asm-large",
97 cl::init(Val: true), cl::Hidden,
98 cl::desc("branch relax asm"));
99
100static cl::opt<bool>
101 UseDFAHazardRec("dfa-hazard-rec", cl::init(Val: true), cl::Hidden,
102 cl::desc("Use the DFA based hazard recognizer."));
103
104/// Constants for Hexagon instructions.
105const int Hexagon_MEMW_OFFSET_MAX = 4095;
106const int Hexagon_MEMW_OFFSET_MIN = -4096;
107const int Hexagon_MEMD_OFFSET_MAX = 8191;
108const int Hexagon_MEMD_OFFSET_MIN = -8192;
109const int Hexagon_MEMH_OFFSET_MAX = 2047;
110const int Hexagon_MEMH_OFFSET_MIN = -2048;
111const int Hexagon_MEMB_OFFSET_MAX = 1023;
112const int Hexagon_MEMB_OFFSET_MIN = -1024;
113const int Hexagon_ADDI_OFFSET_MAX = 32767;
114const int Hexagon_ADDI_OFFSET_MIN = -32768;
115
116// Pin the vtable to this file.
117void HexagonInstrInfo::anchor() {}
118
119HexagonInstrInfo::HexagonInstrInfo(const HexagonSubtarget &ST)
120 : HexagonGenInstrInfo(ST, RegInfo, Hexagon::ADJCALLSTACKDOWN,
121 Hexagon::ADJCALLSTACKUP),
122 RegInfo(ST.getHwMode()), Subtarget(ST) {}
123
124namespace llvm {
125namespace HexagonFUnits {
126 bool isSlot0Only(unsigned units);
127}
128}
129
130static bool isIntRegForSubInst(Register Reg) {
131 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
132 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
133}
134
135static bool isDblRegForSubInst(Register Reg, const HexagonRegisterInfo &HRI) {
136 return isIntRegForSubInst(Reg: HRI.getSubReg(Reg, Idx: Hexagon::isub_lo)) &&
137 isIntRegForSubInst(Reg: HRI.getSubReg(Reg, Idx: Hexagon::isub_hi));
138}
139
140/// Calculate number of instructions excluding the debug instructions.
141static unsigned nonDbgMICount(MachineBasicBlock::const_instr_iterator MIB,
142 MachineBasicBlock::const_instr_iterator MIE) {
143 unsigned Count = 0;
144 for (; MIB != MIE; ++MIB) {
145 if (!MIB->isDebugInstr())
146 ++Count;
147 }
148 return Count;
149}
150
151// Check if the A2_tfrsi instruction is cheap or not. If the operand has
152// to be constant-extendend it is not cheap since it occupies two slots
153// in a packet.
154bool HexagonInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
155 // Enable the following steps only at Os/Oz
156 if (!(MI.getMF()->getFunction().hasOptSize()))
157 return MI.isAsCheapAsAMove();
158
159 if (MI.getOpcode() == Hexagon::A2_tfrsi) {
160 auto Op = MI.getOperand(i: 1);
161 // If the instruction has a global address as operand, it is not cheap
162 // since the operand will be constant extended.
163 if (Op.isGlobal())
164 return false;
165 // If the instruction has an operand of size > 16bits, its will be
166 // const-extended and hence, it is not cheap.
167 if (Op.isImm()) {
168 int64_t Imm = Op.getImm();
169 if (!isInt<16>(x: Imm))
170 return false;
171 }
172 }
173 return MI.isAsCheapAsAMove();
174}
175
176// Do not sink floating point instructions that updates USR register.
177// Example:
178// feclearexcept
179// F2_conv_w2sf
180// fetestexcept
181// MachineSink sinks F2_conv_w2sf and we are not able to catch exceptions.
182// TODO: On some of these floating point instructions, USR is marked as Use.
183// In reality, these instructions also Def the USR. If USR is marked as Def,
184// some of the assumptions in assembler packetization are broken.
185bool HexagonInstrInfo::shouldSink(const MachineInstr &MI) const {
186 // Assumption: A floating point instruction that reads the USR will write
187 // the USR as well.
188 if (isFloat(MI) && MI.hasRegisterImplicitUseOperand(Reg: Hexagon::USR))
189 return false;
190 return true;
191}
192
193/// Find the hardware loop instruction used to set-up the specified loop.
194/// On Hexagon, we have two instructions used to set-up the hardware loop
195/// (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
196/// to indicate the end of a loop.
197MachineInstr *HexagonInstrInfo::findLoopInstr(MachineBasicBlock *BB,
198 unsigned EndLoopOp, MachineBasicBlock *TargetBB,
199 SmallPtrSet<MachineBasicBlock *, 8> &Visited) const {
200 unsigned LOOPi;
201 unsigned LOOPr;
202 if (EndLoopOp == Hexagon::ENDLOOP0) {
203 LOOPi = Hexagon::J2_loop0i;
204 LOOPr = Hexagon::J2_loop0r;
205 } else { // EndLoopOp == Hexagon::EndLOOP1
206 LOOPi = Hexagon::J2_loop1i;
207 LOOPr = Hexagon::J2_loop1r;
208 }
209
210 // The loop set-up instruction will be in a predecessor block
211 for (MachineBasicBlock *PB : BB->predecessors()) {
212 // If this has been visited, already skip it.
213 if (!Visited.insert(Ptr: PB).second)
214 continue;
215 if (PB == BB)
216 continue;
217 for (MachineInstr &I : llvm::reverse(C: PB->instrs())) {
218 unsigned Opc = I.getOpcode();
219 if (Opc == LOOPi || Opc == LOOPr)
220 return &I;
221 // We've reached a different loop, which means the loop01 has been
222 // removed.
223 if (Opc == EndLoopOp && I.getOperand(i: 0).getMBB() != TargetBB)
224 return nullptr;
225 }
226 // Check the predecessors for the LOOP instruction.
227 if (MachineInstr *Loop = findLoopInstr(BB: PB, EndLoopOp, TargetBB, Visited))
228 return Loop;
229 }
230 return nullptr;
231}
232
233/// Gather register def/uses from MI.
234/// This treats possible (predicated) defs as actually happening ones
235/// (conservatively).
236static inline void parseOperands(const MachineInstr &MI,
237 SmallVectorImpl<Register> &Defs, SmallVectorImpl<Register> &Uses) {
238 Defs.clear();
239 Uses.clear();
240
241 for (const MachineOperand &MO : MI.operands()) {
242 if (!MO.isReg())
243 continue;
244
245 Register Reg = MO.getReg();
246 if (!Reg)
247 continue;
248
249 if (MO.isUse())
250 Uses.push_back(Elt: MO.getReg());
251
252 if (MO.isDef())
253 Defs.push_back(Elt: MO.getReg());
254 }
255}
256
257// Position dependent, so check twice for swap.
258static bool isDuplexPairMatch(unsigned Ga, unsigned Gb) {
259 switch (Ga) {
260 case HexagonII::HSIG_None:
261 default:
262 return false;
263 case HexagonII::HSIG_L1:
264 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
265 case HexagonII::HSIG_L2:
266 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
267 Gb == HexagonII::HSIG_A);
268 case HexagonII::HSIG_S1:
269 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
270 Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_A);
271 case HexagonII::HSIG_S2:
272 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
273 Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_S2 ||
274 Gb == HexagonII::HSIG_A);
275 case HexagonII::HSIG_A:
276 return (Gb == HexagonII::HSIG_A);
277 case HexagonII::HSIG_Compound:
278 return (Gb == HexagonII::HSIG_Compound);
279 }
280 return false;
281}
282
283/// isLoadFromStackSlot - If the specified machine instruction is a direct
284/// load from a stack slot, return the virtual or physical register number of
285/// the destination along with the FrameIndex of the loaded stack slot. If
286/// not, return 0. This predicate must return 0 if the instruction has
287/// any side effects other than loading from the stack slot.
288Register HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
289 int &FrameIndex) const {
290 switch (MI.getOpcode()) {
291 default:
292 break;
293 case Hexagon::L2_loadri_io:
294 case Hexagon::L2_loadrd_io:
295 case Hexagon::V6_vL32b_ai:
296 case Hexagon::V6_vL32b_nt_ai:
297 case Hexagon::V6_vL32Ub_ai:
298 case Hexagon::LDriw_pred:
299 case Hexagon::LDriw_ctr:
300 case Hexagon::PS_vloadrq_ai:
301 case Hexagon::PS_vloadrw_ai:
302 case Hexagon::PS_vloadrw_nt_ai: {
303 const MachineOperand OpFI = MI.getOperand(i: 1);
304 if (!OpFI.isFI())
305 return 0;
306 const MachineOperand OpOff = MI.getOperand(i: 2);
307 if (!OpOff.isImm() || OpOff.getImm() != 0)
308 return 0;
309 FrameIndex = OpFI.getIndex();
310 return MI.getOperand(i: 0).getReg();
311 }
312
313 case Hexagon::L2_ploadrit_io:
314 case Hexagon::L2_ploadrif_io:
315 case Hexagon::L2_ploadrdt_io:
316 case Hexagon::L2_ploadrdf_io: {
317 const MachineOperand OpFI = MI.getOperand(i: 2);
318 if (!OpFI.isFI())
319 return 0;
320 const MachineOperand OpOff = MI.getOperand(i: 3);
321 if (!OpOff.isImm() || OpOff.getImm() != 0)
322 return 0;
323 FrameIndex = OpFI.getIndex();
324 return MI.getOperand(i: 0).getReg();
325 }
326 }
327
328 return 0;
329}
330
331/// isStoreToStackSlot - If the specified machine instruction is a direct
332/// store to a stack slot, return the virtual or physical register number of
333/// the source reg along with the FrameIndex of the loaded stack slot. If
334/// not, return 0. This predicate must return 0 if the instruction has
335/// any side effects other than storing to the stack slot.
336Register HexagonInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
337 int &FrameIndex) const {
338 switch (MI.getOpcode()) {
339 default:
340 break;
341 case Hexagon::S2_storerb_io:
342 case Hexagon::S2_storerh_io:
343 case Hexagon::S2_storeri_io:
344 case Hexagon::S2_storerd_io:
345 case Hexagon::V6_vS32b_ai:
346 case Hexagon::V6_vS32Ub_ai:
347 case Hexagon::STriw_pred:
348 case Hexagon::STriw_ctr:
349 case Hexagon::PS_vstorerq_ai:
350 case Hexagon::PS_vstorerw_ai: {
351 const MachineOperand &OpFI = MI.getOperand(i: 0);
352 if (!OpFI.isFI())
353 return 0;
354 const MachineOperand &OpOff = MI.getOperand(i: 1);
355 if (!OpOff.isImm() || OpOff.getImm() != 0)
356 return 0;
357 FrameIndex = OpFI.getIndex();
358 return MI.getOperand(i: 2).getReg();
359 }
360
361 case Hexagon::S2_pstorerbt_io:
362 case Hexagon::S2_pstorerbf_io:
363 case Hexagon::S2_pstorerht_io:
364 case Hexagon::S2_pstorerhf_io:
365 case Hexagon::S2_pstorerit_io:
366 case Hexagon::S2_pstorerif_io:
367 case Hexagon::S2_pstorerdt_io:
368 case Hexagon::S2_pstorerdf_io: {
369 const MachineOperand &OpFI = MI.getOperand(i: 1);
370 if (!OpFI.isFI())
371 return 0;
372 const MachineOperand &OpOff = MI.getOperand(i: 2);
373 if (!OpOff.isImm() || OpOff.getImm() != 0)
374 return 0;
375 FrameIndex = OpFI.getIndex();
376 return MI.getOperand(i: 3).getReg();
377 }
378 }
379
380 return 0;
381}
382
383/// This function checks if the instruction or bundle of instructions
384/// has load from stack slot and returns frameindex and machine memory
385/// operand of that instruction if true.
386bool HexagonInstrInfo::hasLoadFromStackSlot(
387 const MachineInstr &MI,
388 SmallVectorImpl<const MachineMemOperand *> &Accesses) const {
389 if (MI.isBundle()) {
390 const MachineBasicBlock *MBB = MI.getParent();
391 MachineBasicBlock::const_instr_iterator MII = MI.getIterator();
392 for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
393 if (TargetInstrInfo::hasLoadFromStackSlot(MI: *MII, Accesses))
394 return true;
395 return false;
396 }
397
398 return TargetInstrInfo::hasLoadFromStackSlot(MI, Accesses);
399}
400
401/// This function checks if the instruction or bundle of instructions
402/// has store to stack slot and returns frameindex and machine memory
403/// operand of that instruction if true.
404bool HexagonInstrInfo::hasStoreToStackSlot(
405 const MachineInstr &MI,
406 SmallVectorImpl<const MachineMemOperand *> &Accesses) const {
407 if (MI.isBundle()) {
408 const MachineBasicBlock *MBB = MI.getParent();
409 MachineBasicBlock::const_instr_iterator MII = MI.getIterator();
410 for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
411 if (TargetInstrInfo::hasStoreToStackSlot(MI: *MII, Accesses))
412 return true;
413 return false;
414 }
415
416 return TargetInstrInfo::hasStoreToStackSlot(MI, Accesses);
417}
418
419/// This function can analyze one/two way branching only and should (mostly) be
420/// called by target independent side.
421/// First entry is always the opcode of the branching instruction, except when
422/// the Cond vector is supposed to be empty, e.g., when analyzeBranch fails, a
423/// BB with only unconditional jump. Subsequent entries depend upon the opcode,
424/// e.g. Jump_c p will have
425/// Cond[0] = Jump_c
426/// Cond[1] = p
427/// HW-loop ENDLOOP:
428/// Cond[0] = ENDLOOP
429/// Cond[1] = MBB
430/// New value jump:
431/// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
432/// Cond[1] = R
433/// Cond[2] = Imm
434bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
435 MachineBasicBlock *&TBB,
436 MachineBasicBlock *&FBB,
437 SmallVectorImpl<MachineOperand> &Cond,
438 bool AllowModify) const {
439 TBB = nullptr;
440 FBB = nullptr;
441 Cond.clear();
442
443 // If the block has no terminators, it just falls into the block after it.
444 MachineBasicBlock::instr_iterator I = MBB.instr_end();
445 if (I == MBB.instr_begin())
446 return false;
447
448 // A basic block may looks like this:
449 //
450 // [ insn
451 // EH_LABEL
452 // insn
453 // insn
454 // insn
455 // EH_LABEL
456 // insn ]
457 //
458 // It has two succs but does not have a terminator
459 // Don't know how to handle it.
460 do {
461 --I;
462 if (I->isEHLabel())
463 // Don't analyze EH branches.
464 return true;
465 } while (I != MBB.instr_begin());
466
467 I = MBB.instr_end();
468 --I;
469
470 while (I->isDebugInstr()) {
471 if (I == MBB.instr_begin())
472 return false;
473 --I;
474 }
475
476 bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
477 I->getOperand(i: 0).isMBB();
478 // Delete the J2_jump if it's equivalent to a fall-through.
479 if (AllowModify && JumpToBlock &&
480 MBB.isLayoutSuccessor(MBB: I->getOperand(i: 0).getMBB())) {
481 LLVM_DEBUG(dbgs() << "\nErasing the jump to successor block\n";);
482 I->eraseFromParent();
483 I = MBB.instr_end();
484 if (I == MBB.instr_begin())
485 return false;
486 --I;
487 }
488 if (!isUnpredicatedTerminator(MI: *I))
489 return false;
490
491 // Get the last instruction in the block.
492 MachineInstr *LastInst = &*I;
493 MachineInstr *SecondLastInst = nullptr;
494 // Find one more terminator if present.
495 while (true) {
496 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(MI: *I)) {
497 if (!SecondLastInst)
498 SecondLastInst = &*I;
499 else
500 // This is a third branch.
501 return true;
502 }
503 if (I == MBB.instr_begin())
504 break;
505 --I;
506 }
507
508 int LastOpcode = LastInst->getOpcode();
509 int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
510 // If the branch target is not a basic block, it could be a tail call.
511 // (It is, if the target is a function.)
512 if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(i: 0).isMBB())
513 return true;
514 if (SecLastOpcode == Hexagon::J2_jump &&
515 !SecondLastInst->getOperand(i: 0).isMBB())
516 return true;
517
518 bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(Opcode: LastOpcode);
519 bool LastOpcodeHasNVJump = isNewValueJump(MI: *LastInst);
520
521 if (LastOpcodeHasJMP_c && !LastInst->getOperand(i: 1).isMBB())
522 return true;
523
524 // If there is only one terminator instruction, process it.
525 if (LastInst && !SecondLastInst) {
526 if (LastOpcode == Hexagon::J2_jump) {
527 TBB = LastInst->getOperand(i: 0).getMBB();
528 return false;
529 }
530 if (isEndLoopN(Opcode: LastOpcode)) {
531 TBB = LastInst->getOperand(i: 0).getMBB();
532 Cond.push_back(Elt: MachineOperand::CreateImm(Val: LastInst->getOpcode()));
533 Cond.push_back(Elt: LastInst->getOperand(i: 0));
534 return false;
535 }
536 if (LastOpcodeHasJMP_c) {
537 TBB = LastInst->getOperand(i: 1).getMBB();
538 Cond.push_back(Elt: MachineOperand::CreateImm(Val: LastInst->getOpcode()));
539 Cond.push_back(Elt: LastInst->getOperand(i: 0));
540 return false;
541 }
542 // Only supporting rr/ri versions of new-value jumps.
543 if (LastOpcodeHasNVJump && (LastInst->getNumExplicitOperands() == 3)) {
544 TBB = LastInst->getOperand(i: 2).getMBB();
545 Cond.push_back(Elt: MachineOperand::CreateImm(Val: LastInst->getOpcode()));
546 Cond.push_back(Elt: LastInst->getOperand(i: 0));
547 Cond.push_back(Elt: LastInst->getOperand(i: 1));
548 return false;
549 }
550 LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
551 << " with one jump\n";);
552 // Otherwise, don't know what this is.
553 return true;
554 }
555
556 bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(Opcode: SecLastOpcode);
557 bool SecLastOpcodeHasNVJump = isNewValueJump(MI: *SecondLastInst);
558 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
559 if (!SecondLastInst->getOperand(i: 1).isMBB())
560 return true;
561 TBB = SecondLastInst->getOperand(i: 1).getMBB();
562 Cond.push_back(Elt: MachineOperand::CreateImm(Val: SecondLastInst->getOpcode()));
563 Cond.push_back(Elt: SecondLastInst->getOperand(i: 0));
564 FBB = LastInst->getOperand(i: 0).getMBB();
565 return false;
566 }
567
568 // Only supporting rr/ri versions of new-value jumps.
569 if (SecLastOpcodeHasNVJump &&
570 (SecondLastInst->getNumExplicitOperands() == 3) &&
571 (LastOpcode == Hexagon::J2_jump)) {
572 TBB = SecondLastInst->getOperand(i: 2).getMBB();
573 Cond.push_back(Elt: MachineOperand::CreateImm(Val: SecondLastInst->getOpcode()));
574 Cond.push_back(Elt: SecondLastInst->getOperand(i: 0));
575 Cond.push_back(Elt: SecondLastInst->getOperand(i: 1));
576 FBB = LastInst->getOperand(i: 0).getMBB();
577 return false;
578 }
579
580 // If the block ends with two Hexagon:JMPs, handle it. The second one is not
581 // executed, so remove it.
582 if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
583 TBB = SecondLastInst->getOperand(i: 0).getMBB();
584 I = LastInst->getIterator();
585 if (AllowModify)
586 I->eraseFromParent();
587 return false;
588 }
589
590 // If the block ends with an ENDLOOP, and J2_jump, handle it.
591 if (isEndLoopN(Opcode: SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
592 TBB = SecondLastInst->getOperand(i: 0).getMBB();
593 Cond.push_back(Elt: MachineOperand::CreateImm(Val: SecondLastInst->getOpcode()));
594 Cond.push_back(Elt: SecondLastInst->getOperand(i: 0));
595 FBB = LastInst->getOperand(i: 0).getMBB();
596 return false;
597 }
598 LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
599 << " with two jumps";);
600 // Otherwise, can't handle this.
601 return true;
602}
603
604unsigned HexagonInstrInfo::removeBranch(MachineBasicBlock &MBB,
605 int *BytesRemoved) const {
606 assert(!BytesRemoved && "code size not handled");
607
608 LLVM_DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB));
609 MachineBasicBlock::iterator I = MBB.end();
610 unsigned Count = 0;
611 while (I != MBB.begin()) {
612 --I;
613 if (I->isDebugInstr())
614 continue;
615 // Only removing branches from end of MBB.
616 if (!I->isBranch())
617 return Count;
618 if (Count && (I->getOpcode() == Hexagon::J2_jump))
619 llvm_unreachable("Malformed basic block: unconditional branch not last");
620 MBB.erase(I: &MBB.back());
621 I = MBB.end();
622 ++Count;
623 }
624 return Count;
625}
626
627unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB,
628 MachineBasicBlock *TBB,
629 MachineBasicBlock *FBB,
630 ArrayRef<MachineOperand> Cond,
631 const DebugLoc &DL,
632 int *BytesAdded) const {
633 unsigned BOpc = Hexagon::J2_jump;
634 unsigned BccOpc = Hexagon::J2_jumpt;
635 assert(validateBranchCond(Cond) && "Invalid branching condition");
636 assert(TBB && "insertBranch must not be told to insert a fallthrough");
637 assert(!BytesAdded && "code size not handled");
638
639 // Check if reverseBranchCondition has asked to reverse this branch
640 // If we want to reverse the branch an odd number of times, we want
641 // J2_jumpf.
642 if (!Cond.empty() && Cond[0].isImm())
643 BccOpc = Cond[0].getImm();
644
645 if (!FBB) {
646 if (Cond.empty()) {
647 // Due to a bug in TailMerging/CFG Optimization, we need to add a
648 // special case handling of a predicated jump followed by an
649 // unconditional jump. If not, Tail Merging and CFG Optimization go
650 // into an infinite loop.
651 MachineBasicBlock *NewTBB, *NewFBB;
652 SmallVector<MachineOperand, 4> Cond;
653 auto Term = MBB.getFirstTerminator();
654 if (Term != MBB.end() && isPredicated(MI: *Term) &&
655 !analyzeBranch(MBB, TBB&: NewTBB, FBB&: NewFBB, Cond, AllowModify: false) &&
656 MachineFunction::iterator(NewTBB) == ++MBB.getIterator()) {
657 reverseBranchCondition(Cond);
658 removeBranch(MBB);
659 return insertBranch(MBB, TBB, FBB: nullptr, Cond, DL);
660 }
661 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: BOpc)).addMBB(MBB: TBB);
662 } else if (isEndLoopN(Opcode: Cond[0].getImm())) {
663 int EndLoopOp = Cond[0].getImm();
664 assert(Cond[1].isMBB());
665 // Since we're adding an ENDLOOP, there better be a LOOP instruction.
666 // Check for it, and change the BB target if needed.
667 SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
668 MachineInstr *Loop = findLoopInstr(BB: TBB, EndLoopOp, TargetBB: Cond[1].getMBB(),
669 Visited&: VisitedBBs);
670 assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
671 Loop->getOperand(i: 0).setMBB(TBB);
672 // Add the ENDLOOP after the finding the LOOP0.
673 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: EndLoopOp)).addMBB(MBB: TBB);
674 } else if (isNewValueJump(Opcode: Cond[0].getImm())) {
675 assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
676 // New value jump
677 // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
678 // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
679 RegState Flags1 = getUndefRegState(B: Cond[1].isUndef());
680 LLVM_DEBUG(dbgs() << "\nInserting NVJump for "
681 << printMBBReference(MBB););
682 if (Cond[2].isReg()) {
683 RegState Flags2 = getUndefRegState(B: Cond[2].isUndef());
684 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: BccOpc)).addReg(RegNo: Cond[1].getReg(), Flags: Flags1).
685 addReg(RegNo: Cond[2].getReg(), Flags: Flags2).addMBB(MBB: TBB);
686 } else if(Cond[2].isImm()) {
687 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: BccOpc)).addReg(RegNo: Cond[1].getReg(), Flags: Flags1).
688 addImm(Val: Cond[2].getImm()).addMBB(MBB: TBB);
689 } else
690 llvm_unreachable("Invalid condition for branching");
691 } else {
692 assert((Cond.size() == 2) && "Malformed cond vector");
693 const MachineOperand &RO = Cond[1];
694 RegState Flags = getUndefRegState(B: RO.isUndef());
695 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: BccOpc)).addReg(RegNo: RO.getReg(), Flags).addMBB(MBB: TBB);
696 }
697 return 1;
698 }
699 assert((!Cond.empty()) &&
700 "Cond. cannot be empty when multiple branchings are required");
701 assert((!isNewValueJump(Cond[0].getImm())) &&
702 "NV-jump cannot be inserted with another branch");
703 // Special case for hardware loops. The condition is a basic block.
704 if (isEndLoopN(Opcode: Cond[0].getImm())) {
705 int EndLoopOp = Cond[0].getImm();
706 assert(Cond[1].isMBB());
707 // Since we're adding an ENDLOOP, there better be a LOOP instruction.
708 // Check for it, and change the BB target if needed.
709 SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
710 MachineInstr *Loop = findLoopInstr(BB: TBB, EndLoopOp, TargetBB: Cond[1].getMBB(),
711 Visited&: VisitedBBs);
712 assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
713 Loop->getOperand(i: 0).setMBB(TBB);
714 // Add the ENDLOOP after the finding the LOOP0.
715 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: EndLoopOp)).addMBB(MBB: TBB);
716 } else {
717 const MachineOperand &RO = Cond[1];
718 RegState Flags = getUndefRegState(B: RO.isUndef());
719 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: BccOpc)).addReg(RegNo: RO.getReg(), Flags).addMBB(MBB: TBB);
720 }
721 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: BOpc)).addMBB(MBB: FBB);
722
723 return 2;
724}
725
726namespace {
727class HexagonPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
728 MachineInstr *Loop, *EndLoop;
729 MachineFunction *MF;
730 const HexagonInstrInfo *TII;
731 int64_t TripCount;
732 Register LoopCount;
733 DebugLoc DL;
734
735public:
736 HexagonPipelinerLoopInfo(MachineInstr *Loop, MachineInstr *EndLoop)
737 : Loop(Loop), EndLoop(EndLoop), MF(Loop->getParent()->getParent()),
738 TII(MF->getSubtarget<HexagonSubtarget>().getInstrInfo()),
739 DL(Loop->getDebugLoc()) {
740 // Inspect the Loop instruction up-front, as it may be deleted when we call
741 // createTripCountGreaterCondition.
742 TripCount = Loop->getOpcode() == Hexagon::J2_loop0r
743 ? -1
744 : Loop->getOperand(i: 1).getImm();
745 if (TripCount == -1)
746 LoopCount = Loop->getOperand(i: 1).getReg();
747 }
748
749 bool shouldIgnoreForPipelining(const MachineInstr *MI) const override {
750 // Only ignore the terminator.
751 return MI == EndLoop;
752 }
753
754 std::optional<bool> createTripCountGreaterCondition(
755 int TC, MachineBasicBlock &MBB,
756 SmallVectorImpl<MachineOperand> &Cond) override {
757 if (TripCount == -1) {
758 // Check if we're done with the loop.
759 Register Done = TII->createVR(MF, VT: MVT::i1);
760 MachineInstr *NewCmp = BuildMI(BB: &MBB, MIMD: DL,
761 MCID: TII->get(Opcode: Hexagon::C2_cmpgtui), DestReg: Done)
762 .addReg(RegNo: LoopCount)
763 .addImm(Val: TC);
764 Cond.push_back(Elt: MachineOperand::CreateImm(Val: Hexagon::J2_jumpf));
765 Cond.push_back(Elt: NewCmp->getOperand(i: 0));
766 return {};
767 }
768
769 return TripCount > TC;
770 }
771
772 void setPreheader(MachineBasicBlock *NewPreheader) override {
773 NewPreheader->splice(Where: NewPreheader->getFirstTerminator(), Other: Loop->getParent(),
774 From: Loop);
775 }
776
777 void adjustTripCount(int TripCountAdjust) override {
778 // If the loop trip count is a compile-time value, then just change the
779 // value.
780 if (Loop->getOpcode() == Hexagon::J2_loop0i ||
781 Loop->getOpcode() == Hexagon::J2_loop1i) {
782 int64_t TripCount = Loop->getOperand(i: 1).getImm() + TripCountAdjust;
783 assert(TripCount > 0 && "Can't create an empty or negative loop!");
784 Loop->getOperand(i: 1).setImm(TripCount);
785 return;
786 }
787
788 // The loop trip count is a run-time value. We generate code to subtract
789 // one from the trip count, and update the loop instruction.
790 Register LoopCount = Loop->getOperand(i: 1).getReg();
791 Register NewLoopCount = TII->createVR(MF, VT: MVT::i32);
792 BuildMI(BB&: *Loop->getParent(), I: Loop, MIMD: Loop->getDebugLoc(),
793 MCID: TII->get(Opcode: Hexagon::A2_addi), DestReg: NewLoopCount)
794 .addReg(RegNo: LoopCount)
795 .addImm(Val: TripCountAdjust);
796 Loop->getOperand(i: 1).setReg(NewLoopCount);
797 }
798
799 void disposed(LiveIntervals *LIS) override {
800 if (LIS)
801 LIS->RemoveMachineInstrFromMaps(MI&: *Loop);
802 Loop->eraseFromParent();
803 }
804};
805} // namespace
806
807std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
808HexagonInstrInfo::analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const {
809 // We really "analyze" only hardware loops right now.
810 MachineBasicBlock::iterator I = LoopBB->getFirstTerminator();
811
812 if (I != LoopBB->end() && isEndLoopN(Opcode: I->getOpcode())) {
813 SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
814 MachineInstr *LoopInst = findLoopInstr(
815 BB: LoopBB, EndLoopOp: I->getOpcode(), TargetBB: I->getOperand(i: 0).getMBB(), Visited&: VisitedBBs);
816 if (LoopInst)
817 return std::make_unique<HexagonPipelinerLoopInfo>(args&: LoopInst, args: &*I);
818 }
819 return nullptr;
820}
821
822bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
823 unsigned NumCycles, unsigned ExtraPredCycles,
824 BranchProbability Probability) const {
825 return nonDbgBBSize(BB: &MBB) <= 3;
826}
827
828bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
829 unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB,
830 unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability)
831 const {
832 return nonDbgBBSize(BB: &TMBB) <= 3 && nonDbgBBSize(BB: &FMBB) <= 3;
833}
834
835bool HexagonInstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
836 unsigned NumInstrs, BranchProbability Probability) const {
837 return NumInstrs <= 4;
838}
839
840static void getLiveInRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
841 SmallVector<std::pair<MCPhysReg, const MachineOperand*>,2> Clobbers;
842 const MachineBasicBlock &B = *MI.getParent();
843 Regs.addLiveIns(MBB: B);
844 auto E = MachineBasicBlock::const_iterator(MI.getIterator());
845 for (auto I = B.begin(); I != E; ++I) {
846 Clobbers.clear();
847 Regs.stepForward(MI: *I, Clobbers);
848 }
849}
850
851static void getLiveOutRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
852 const MachineBasicBlock &B = *MI.getParent();
853 Regs.addLiveOuts(MBB: B);
854 auto E = ++MachineBasicBlock::const_iterator(MI.getIterator()).getReverse();
855 for (auto I = B.rbegin(); I != E; ++I)
856 Regs.stepBackward(MI: *I);
857}
858
859void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
860 MachineBasicBlock::iterator I,
861 const DebugLoc &DL, Register DestReg,
862 Register SrcReg, bool KillSrc,
863 bool RenamableDest,
864 bool RenamableSrc) const {
865 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
866 RegState KillFlag = getKillRegState(B: KillSrc);
867
868 if (Hexagon::IntRegsRegClass.contains(Reg1: SrcReg, Reg2: DestReg)) {
869 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::A2_tfr), DestReg)
870 .addReg(RegNo: SrcReg, Flags: KillFlag);
871 return;
872 }
873 if (Hexagon::DoubleRegsRegClass.contains(Reg1: SrcReg, Reg2: DestReg)) {
874 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::A2_tfrp), DestReg)
875 .addReg(RegNo: SrcReg, Flags: KillFlag);
876 return;
877 }
878 if (Hexagon::PredRegsRegClass.contains(Reg1: SrcReg, Reg2: DestReg)) {
879 // Map Pd = Ps to Pd = or(Ps, Ps).
880 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::C2_or), DestReg)
881 .addReg(RegNo: SrcReg).addReg(RegNo: SrcReg, Flags: KillFlag);
882 return;
883 }
884 if (Hexagon::CtrRegsRegClass.contains(Reg: DestReg) &&
885 Hexagon::IntRegsRegClass.contains(Reg: SrcReg)) {
886 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::A2_tfrrcr), DestReg)
887 .addReg(RegNo: SrcReg, Flags: KillFlag);
888 return;
889 }
890 if (Hexagon::IntRegsRegClass.contains(Reg: DestReg) &&
891 Hexagon::CtrRegsRegClass.contains(Reg: SrcReg)) {
892 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::A2_tfrcrr), DestReg)
893 .addReg(RegNo: SrcReg, Flags: KillFlag);
894 return;
895 }
896 if (Hexagon::ModRegsRegClass.contains(Reg: DestReg) &&
897 Hexagon::IntRegsRegClass.contains(Reg: SrcReg)) {
898 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::A2_tfrrcr), DestReg)
899 .addReg(RegNo: SrcReg, Flags: KillFlag);
900 return;
901 }
902 if (Hexagon::PredRegsRegClass.contains(Reg: SrcReg) &&
903 Hexagon::IntRegsRegClass.contains(Reg: DestReg)) {
904 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::C2_tfrpr), DestReg)
905 .addReg(RegNo: SrcReg, Flags: KillFlag);
906 return;
907 }
908 if (Hexagon::IntRegsRegClass.contains(Reg: SrcReg) &&
909 Hexagon::PredRegsRegClass.contains(Reg: DestReg)) {
910 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::C2_tfrrp), DestReg)
911 .addReg(RegNo: SrcReg, Flags: KillFlag);
912 return;
913 }
914 if (Hexagon::PredRegsRegClass.contains(Reg: SrcReg) &&
915 Hexagon::IntRegsRegClass.contains(Reg: DestReg)) {
916 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::C2_tfrpr), DestReg)
917 .addReg(RegNo: SrcReg, Flags: KillFlag);
918 return;
919 }
920 if (Hexagon::HvxVRRegClass.contains(Reg1: SrcReg, Reg2: DestReg)) {
921 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vassign), DestReg).
922 addReg(RegNo: SrcReg, Flags: KillFlag);
923 return;
924 }
925 if (Hexagon::HvxWRRegClass.contains(Reg1: SrcReg, Reg2: DestReg)) {
926 LivePhysRegs LiveAtMI(HRI);
927 getLiveInRegsAt(Regs&: LiveAtMI, MI: *I);
928 Register SrcLo = HRI.getSubReg(Reg: SrcReg, Idx: Hexagon::vsub_lo);
929 Register SrcHi = HRI.getSubReg(Reg: SrcReg, Idx: Hexagon::vsub_hi);
930 RegState UndefLo = getUndefRegState(B: !LiveAtMI.contains(Reg: SrcLo));
931 RegState UndefHi = getUndefRegState(B: !LiveAtMI.contains(Reg: SrcHi));
932 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vcombine), DestReg)
933 .addReg(RegNo: SrcHi, Flags: KillFlag | UndefHi)
934 .addReg(RegNo: SrcLo, Flags: KillFlag | UndefLo);
935 return;
936 }
937 if (Hexagon::HvxQRRegClass.contains(Reg1: SrcReg, Reg2: DestReg)) {
938 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::V6_pred_and), DestReg)
939 .addReg(RegNo: SrcReg)
940 .addReg(RegNo: SrcReg, Flags: KillFlag);
941 return;
942 }
943 if (Hexagon::HvxQRRegClass.contains(Reg: SrcReg) &&
944 Hexagon::HvxVRRegClass.contains(Reg: DestReg)) {
945 llvm_unreachable("Unimplemented pred to vec");
946 return;
947 }
948 if (Hexagon::HvxQRRegClass.contains(Reg: DestReg) &&
949 Hexagon::HvxVRRegClass.contains(Reg: SrcReg)) {
950 llvm_unreachable("Unimplemented vec to pred");
951 return;
952 }
953
954#ifndef NDEBUG
955 // Show the invalid registers to ease debugging.
956 dbgs() << "Invalid registers for copy in " << printMBBReference(MBB) << ": "
957 << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n';
958#endif
959 llvm_unreachable("Unimplemented");
960}
961
962void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
963 MachineBasicBlock::iterator I,
964 Register SrcReg, bool isKill, int FI,
965 const TargetRegisterClass *RC,
966 Register VReg,
967 MachineInstr::MIFlag Flags) const {
968 DebugLoc DL = MBB.findDebugLoc(MBBI: I);
969 MachineFunction &MF = *MBB.getParent();
970 MachineFrameInfo &MFI = MF.getFrameInfo();
971 RegState KillFlag = getKillRegState(B: isKill);
972
973 MachineMemOperand *MMO = MF.getMachineMemOperand(
974 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI), F: MachineMemOperand::MOStore,
975 Size: MFI.getObjectSize(ObjectIdx: FI), BaseAlignment: MFI.getObjectAlign(ObjectIdx: FI));
976
977 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
978 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::S2_storeri_io))
979 .addFrameIndex(Idx: FI).addImm(Val: 0)
980 .addReg(RegNo: SrcReg, Flags: KillFlag).addMemOperand(MMO);
981 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
982 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::S2_storerd_io))
983 .addFrameIndex(Idx: FI).addImm(Val: 0)
984 .addReg(RegNo: SrcReg, Flags: KillFlag).addMemOperand(MMO);
985 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
986 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::STriw_pred))
987 .addFrameIndex(Idx: FI).addImm(Val: 0)
988 .addReg(RegNo: SrcReg, Flags: KillFlag).addMemOperand(MMO);
989 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
990 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::STriw_ctr))
991 .addFrameIndex(Idx: FI).addImm(Val: 0)
992 .addReg(RegNo: SrcReg, Flags: KillFlag).addMemOperand(MMO);
993 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
994 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::PS_vstorerq_ai))
995 .addFrameIndex(Idx: FI).addImm(Val: 0)
996 .addReg(RegNo: SrcReg, Flags: KillFlag).addMemOperand(MMO);
997 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
998 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::PS_vstorerv_ai))
999 .addFrameIndex(Idx: FI).addImm(Val: 0)
1000 .addReg(RegNo: SrcReg, Flags: KillFlag).addMemOperand(MMO);
1001 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
1002 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::PS_vstorerw_ai))
1003 .addFrameIndex(Idx: FI).addImm(Val: 0)
1004 .addReg(RegNo: SrcReg, Flags: KillFlag).addMemOperand(MMO);
1005 } else {
1006 llvm_unreachable("Unimplemented");
1007 }
1008}
1009
1010void HexagonInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1011 MachineBasicBlock::iterator I,
1012 Register DestReg, int FI,
1013 const TargetRegisterClass *RC,
1014 Register VReg, unsigned SubReg,
1015 MachineInstr::MIFlag Flags) const {
1016 DebugLoc DL = MBB.findDebugLoc(MBBI: I);
1017 MachineFunction &MF = *MBB.getParent();
1018 MachineFrameInfo &MFI = MF.getFrameInfo();
1019
1020 MachineMemOperand *MMO = MF.getMachineMemOperand(
1021 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI), F: MachineMemOperand::MOLoad,
1022 Size: MFI.getObjectSize(ObjectIdx: FI), BaseAlignment: MFI.getObjectAlign(ObjectIdx: FI));
1023
1024 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
1025 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::L2_loadri_io), DestReg)
1026 .addFrameIndex(Idx: FI).addImm(Val: 0).addMemOperand(MMO);
1027 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
1028 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::L2_loadrd_io), DestReg)
1029 .addFrameIndex(Idx: FI).addImm(Val: 0).addMemOperand(MMO);
1030 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
1031 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::LDriw_pred), DestReg)
1032 .addFrameIndex(Idx: FI).addImm(Val: 0).addMemOperand(MMO);
1033 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
1034 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::LDriw_ctr), DestReg)
1035 .addFrameIndex(Idx: FI).addImm(Val: 0).addMemOperand(MMO);
1036 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
1037 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::PS_vloadrq_ai), DestReg)
1038 .addFrameIndex(Idx: FI).addImm(Val: 0).addMemOperand(MMO);
1039 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
1040 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::PS_vloadrv_ai), DestReg)
1041 .addFrameIndex(Idx: FI).addImm(Val: 0).addMemOperand(MMO);
1042 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
1043 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::PS_vloadrw_ai), DestReg)
1044 .addFrameIndex(Idx: FI).addImm(Val: 0).addMemOperand(MMO);
1045 } else {
1046 llvm_unreachable("Can't store this register to stack slot");
1047 }
1048}
1049
1050/// expandPostRAPseudo - This function is called for all pseudo instructions
1051/// that remain after register allocation. Many pseudo instructions are
1052/// created to help register allocation. This is the place to convert them
1053/// into real instructions. The target can edit MI in place, or it can insert
1054/// new instructions and erase MI. The function should return true if
1055/// anything was changed.
1056bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1057 MachineBasicBlock &MBB = *MI.getParent();
1058 MachineFunction &MF = *MBB.getParent();
1059 MachineRegisterInfo &MRI = MF.getRegInfo();
1060 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1061 LivePhysRegs LiveIn(HRI), LiveOut(HRI);
1062 DebugLoc DL = MI.getDebugLoc();
1063 unsigned Opc = MI.getOpcode();
1064
1065 auto RealCirc = [&](unsigned Opc, bool HasImm, unsigned MxOp) {
1066 Register Mx = MI.getOperand(i: MxOp).getReg();
1067 Register CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1);
1068 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::A2_tfrrcr), DestReg: CSx)
1069 .add(MO: MI.getOperand(i: (HasImm ? 5 : 4)));
1070 auto MIB = BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Opc)).add(MO: MI.getOperand(i: 0))
1071 .add(MO: MI.getOperand(i: 1)).add(MO: MI.getOperand(i: 2)).add(MO: MI.getOperand(i: 3));
1072 if (HasImm)
1073 MIB.add(MO: MI.getOperand(i: 4));
1074 MIB.addReg(RegNo: CSx, Flags: RegState::Implicit);
1075 MBB.erase(I: MI);
1076 return true;
1077 };
1078
1079 auto UseAligned = [&](const MachineInstr &MI, Align NeedAlign) {
1080 if (MI.memoperands().empty())
1081 return false;
1082 return all_of(Range: MI.memoperands(), P: [NeedAlign](const MachineMemOperand *MMO) {
1083 return MMO->getAlign() >= NeedAlign;
1084 });
1085 };
1086
1087 switch (Opc) {
1088 case Hexagon::PS_call_instrprof_custom: {
1089 auto Op0 = MI.getOperand(i: 0);
1090 assert(Op0.isGlobal() &&
1091 "First operand must be a global containing handler name.");
1092 const GlobalValue *NameVar = Op0.getGlobal();
1093 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Val: NameVar);
1094 auto *Arr = cast<ConstantDataArray>(Val: GV->getInitializer());
1095 StringRef NameStr = Arr->isCString() ? Arr->getAsCString() : Arr->getAsString();
1096
1097 MachineOperand &Op1 = MI.getOperand(i: 1);
1098 // Set R0 with the imm value to be passed to the custom profiling handler.
1099 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::A2_tfrsi), DestReg: Hexagon::R0)
1100 .addImm(Val: Op1.getImm());
1101 // The call to the custom handler is being treated as a special one as the
1102 // callee is responsible for saving and restoring all the registers
1103 // (including caller saved registers) it needs to modify. This is
1104 // done to reduce the impact of instrumentation on the code being
1105 // instrumented/profiled.
1106 // NOTE: R14, R15 and R28 are reserved for PLT handling. These registers
1107 // are in the Def list of the Hexagon::PS_call_instrprof_custom and
1108 // therefore will be handled appropriately duing register allocation.
1109
1110 // TODO: It may be a good idea to add a separate pseudo instruction for
1111 // static relocation which doesn't need to reserve r14, r15 and r28.
1112
1113 auto MIB = BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::J2_call))
1114 .addUse(RegNo: Hexagon::R0, Flags: RegState::Implicit|RegState::InternalRead)
1115 .addDef(RegNo: Hexagon::R29, Flags: RegState::ImplicitDefine)
1116 .addDef(RegNo: Hexagon::R30, Flags: RegState::ImplicitDefine)
1117 .addDef(RegNo: Hexagon::R14, Flags: RegState::ImplicitDefine)
1118 .addDef(RegNo: Hexagon::R15, Flags: RegState::ImplicitDefine)
1119 .addDef(RegNo: Hexagon::R28, Flags: RegState::ImplicitDefine);
1120 const char *cstr = MF.createExternalSymbolName(Name: NameStr);
1121 MIB.addExternalSymbol(FnName: cstr);
1122 MBB.erase(I: MI);
1123 return true;
1124 }
1125 case TargetOpcode::COPY: {
1126 MachineOperand &MD = MI.getOperand(i: 0);
1127 MachineOperand &MS = MI.getOperand(i: 1);
1128 MachineBasicBlock::iterator MBBI = MI.getIterator();
1129 if (MD.getReg() != MS.getReg() && !MS.isUndef()) {
1130 copyPhysReg(MBB, I: MI, DL, DestReg: MD.getReg(), SrcReg: MS.getReg(), KillSrc: MS.isKill());
1131 std::prev(x: MBBI)->copyImplicitOps(MF&: *MBB.getParent(), MI);
1132 }
1133 MBB.erase(I: MBBI);
1134 return true;
1135 }
1136 case Hexagon::PS_aligna:
1137 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::A2_andir), DestReg: MI.getOperand(i: 0).getReg())
1138 .addReg(RegNo: HRI.getFrameRegister())
1139 .addImm(Val: -MI.getOperand(i: 1).getImm());
1140 MBB.erase(I: MI);
1141 return true;
1142 case Hexagon::V6_vassignp: {
1143 Register SrcReg = MI.getOperand(i: 1).getReg();
1144 Register DstReg = MI.getOperand(i: 0).getReg();
1145 Register SrcLo = HRI.getSubReg(Reg: SrcReg, Idx: Hexagon::vsub_lo);
1146 Register SrcHi = HRI.getSubReg(Reg: SrcReg, Idx: Hexagon::vsub_hi);
1147 getLiveInRegsAt(Regs&: LiveIn, MI);
1148 RegState UndefLo = getUndefRegState(B: !LiveIn.contains(Reg: SrcLo));
1149 RegState UndefHi = getUndefRegState(B: !LiveIn.contains(Reg: SrcHi));
1150 RegState Kill = getKillRegState(B: MI.getOperand(i: 1).isKill());
1151 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vcombine), DestReg: DstReg)
1152 .addReg(RegNo: SrcHi, Flags: UndefHi)
1153 .addReg(RegNo: SrcLo, Flags: Kill | UndefLo);
1154 MBB.erase(I: MI);
1155 return true;
1156 }
1157 case Hexagon::V6_lo: {
1158 Register SrcReg = MI.getOperand(i: 1).getReg();
1159 Register DstReg = MI.getOperand(i: 0).getReg();
1160 Register SrcSubLo = HRI.getSubReg(Reg: SrcReg, Idx: Hexagon::vsub_lo);
1161 copyPhysReg(MBB, I: MI, DL, DestReg: DstReg, SrcReg: SrcSubLo, KillSrc: MI.getOperand(i: 1).isKill());
1162 MBB.erase(I: MI);
1163 MRI.clearKillFlags(Reg: SrcSubLo);
1164 return true;
1165 }
1166 case Hexagon::V6_hi: {
1167 Register SrcReg = MI.getOperand(i: 1).getReg();
1168 Register DstReg = MI.getOperand(i: 0).getReg();
1169 Register SrcSubHi = HRI.getSubReg(Reg: SrcReg, Idx: Hexagon::vsub_hi);
1170 copyPhysReg(MBB, I: MI, DL, DestReg: DstReg, SrcReg: SrcSubHi, KillSrc: MI.getOperand(i: 1).isKill());
1171 MBB.erase(I: MI);
1172 MRI.clearKillFlags(Reg: SrcSubHi);
1173 return true;
1174 }
1175 case Hexagon::PS_vloadrv_ai: {
1176 Register DstReg = MI.getOperand(i: 0).getReg();
1177 const MachineOperand &BaseOp = MI.getOperand(i: 1);
1178 assert(BaseOp.getSubReg() == 0);
1179 int Offset = MI.getOperand(i: 2).getImm();
1180 Align NeedAlign = HRI.getSpillAlign(RC: Hexagon::HvxVRRegClass);
1181 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai
1182 : Hexagon::V6_vL32Ub_ai;
1183 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: NewOpc), DestReg: DstReg)
1184 .addReg(RegNo: BaseOp.getReg(), Flags: getRegState(RegOp: BaseOp))
1185 .addImm(Val: Offset)
1186 .cloneMemRefs(OtherMI: MI);
1187 MBB.erase(I: MI);
1188 return true;
1189 }
1190 case Hexagon::PS_vloadrw_ai: {
1191 Register DstReg = MI.getOperand(i: 0).getReg();
1192 const MachineOperand &BaseOp = MI.getOperand(i: 1);
1193 assert(BaseOp.getSubReg() == 0);
1194 int Offset = MI.getOperand(i: 2).getImm();
1195 unsigned VecOffset = HRI.getSpillSize(RC: Hexagon::HvxVRRegClass);
1196 Align NeedAlign = HRI.getSpillAlign(RC: Hexagon::HvxVRRegClass);
1197 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai
1198 : Hexagon::V6_vL32Ub_ai;
1199 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: NewOpc),
1200 DestReg: HRI.getSubReg(Reg: DstReg, Idx: Hexagon::vsub_lo))
1201 .addReg(RegNo: BaseOp.getReg(), Flags: getRegState(RegOp: BaseOp) & ~RegState::Kill)
1202 .addImm(Val: Offset)
1203 .cloneMemRefs(OtherMI: MI);
1204 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: NewOpc),
1205 DestReg: HRI.getSubReg(Reg: DstReg, Idx: Hexagon::vsub_hi))
1206 .addReg(RegNo: BaseOp.getReg(), Flags: getRegState(RegOp: BaseOp))
1207 .addImm(Val: Offset + VecOffset)
1208 .cloneMemRefs(OtherMI: MI);
1209 MBB.erase(I: MI);
1210 return true;
1211 }
1212 case Hexagon::PS_vstorerv_ai: {
1213 const MachineOperand &SrcOp = MI.getOperand(i: 2);
1214 assert(SrcOp.getSubReg() == 0);
1215 const MachineOperand &BaseOp = MI.getOperand(i: 0);
1216 assert(BaseOp.getSubReg() == 0);
1217 int Offset = MI.getOperand(i: 1).getImm();
1218 Align NeedAlign = HRI.getSpillAlign(RC: Hexagon::HvxVRRegClass);
1219 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai
1220 : Hexagon::V6_vS32Ub_ai;
1221 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: NewOpc))
1222 .addReg(RegNo: BaseOp.getReg(), Flags: getRegState(RegOp: BaseOp))
1223 .addImm(Val: Offset)
1224 .addReg(RegNo: SrcOp.getReg(), Flags: getRegState(RegOp: SrcOp))
1225 .cloneMemRefs(OtherMI: MI);
1226 MBB.erase(I: MI);
1227 return true;
1228 }
1229 case Hexagon::PS_vstorerw_ai: {
1230 Register SrcReg = MI.getOperand(i: 2).getReg();
1231 const MachineOperand &BaseOp = MI.getOperand(i: 0);
1232 assert(BaseOp.getSubReg() == 0);
1233 int Offset = MI.getOperand(i: 1).getImm();
1234 unsigned VecOffset = HRI.getSpillSize(RC: Hexagon::HvxVRRegClass);
1235 Align NeedAlign = HRI.getSpillAlign(RC: Hexagon::HvxVRRegClass);
1236 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai
1237 : Hexagon::V6_vS32Ub_ai;
1238 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: NewOpc))
1239 .addReg(RegNo: BaseOp.getReg(), Flags: getRegState(RegOp: BaseOp) & ~RegState::Kill)
1240 .addImm(Val: Offset)
1241 .addReg(RegNo: HRI.getSubReg(Reg: SrcReg, Idx: Hexagon::vsub_lo))
1242 .cloneMemRefs(OtherMI: MI);
1243 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: NewOpc))
1244 .addReg(RegNo: BaseOp.getReg(), Flags: getRegState(RegOp: BaseOp))
1245 .addImm(Val: Offset + VecOffset)
1246 .addReg(RegNo: HRI.getSubReg(Reg: SrcReg, Idx: Hexagon::vsub_hi))
1247 .cloneMemRefs(OtherMI: MI);
1248 MBB.erase(I: MI);
1249 return true;
1250 }
1251 case Hexagon::PS_true: {
1252 Register Reg = MI.getOperand(i: 0).getReg();
1253 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::C2_orn), DestReg: Reg)
1254 .addReg(RegNo: Reg, Flags: RegState::Undef)
1255 .addReg(RegNo: Reg, Flags: RegState::Undef);
1256 MBB.erase(I: MI);
1257 return true;
1258 }
1259 case Hexagon::PS_false: {
1260 Register Reg = MI.getOperand(i: 0).getReg();
1261 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::C2_andn), DestReg: Reg)
1262 .addReg(RegNo: Reg, Flags: RegState::Undef)
1263 .addReg(RegNo: Reg, Flags: RegState::Undef);
1264 MBB.erase(I: MI);
1265 return true;
1266 }
1267 case Hexagon::PS_qtrue: {
1268 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_veqw), DestReg: MI.getOperand(i: 0).getReg())
1269 .addReg(RegNo: Hexagon::V0, Flags: RegState::Undef)
1270 .addReg(RegNo: Hexagon::V0, Flags: RegState::Undef);
1271 MBB.erase(I: MI);
1272 return true;
1273 }
1274 case Hexagon::PS_qfalse: {
1275 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vgtw), DestReg: MI.getOperand(i: 0).getReg())
1276 .addReg(RegNo: Hexagon::V0, Flags: RegState::Undef)
1277 .addReg(RegNo: Hexagon::V0, Flags: RegState::Undef);
1278 MBB.erase(I: MI);
1279 return true;
1280 }
1281 case Hexagon::PS_vdd0: {
1282 Register Vd = MI.getOperand(i: 0).getReg();
1283 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vsubw_dv), DestReg: Vd)
1284 .addReg(RegNo: Vd, Flags: RegState::Undef)
1285 .addReg(RegNo: Vd, Flags: RegState::Undef);
1286 MBB.erase(I: MI);
1287 return true;
1288 }
1289 case Hexagon::PS_vmulw: {
1290 // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
1291 Register DstReg = MI.getOperand(i: 0).getReg();
1292 Register Src1Reg = MI.getOperand(i: 1).getReg();
1293 Register Src2Reg = MI.getOperand(i: 2).getReg();
1294 Register Src1SubHi = HRI.getSubReg(Reg: Src1Reg, Idx: Hexagon::isub_hi);
1295 Register Src1SubLo = HRI.getSubReg(Reg: Src1Reg, Idx: Hexagon::isub_lo);
1296 Register Src2SubHi = HRI.getSubReg(Reg: Src2Reg, Idx: Hexagon::isub_hi);
1297 Register Src2SubLo = HRI.getSubReg(Reg: Src2Reg, Idx: Hexagon::isub_lo);
1298 BuildMI(BB&: MBB, I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Hexagon::M2_mpyi),
1299 DestReg: HRI.getSubReg(Reg: DstReg, Idx: Hexagon::isub_hi))
1300 .addReg(RegNo: Src1SubHi)
1301 .addReg(RegNo: Src2SubHi);
1302 BuildMI(BB&: MBB, I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Hexagon::M2_mpyi),
1303 DestReg: HRI.getSubReg(Reg: DstReg, Idx: Hexagon::isub_lo))
1304 .addReg(RegNo: Src1SubLo)
1305 .addReg(RegNo: Src2SubLo);
1306 MBB.erase(I: MI);
1307 MRI.clearKillFlags(Reg: Src1SubHi);
1308 MRI.clearKillFlags(Reg: Src1SubLo);
1309 MRI.clearKillFlags(Reg: Src2SubHi);
1310 MRI.clearKillFlags(Reg: Src2SubLo);
1311 return true;
1312 }
1313 case Hexagon::PS_vmulw_acc: {
1314 // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
1315 Register DstReg = MI.getOperand(i: 0).getReg();
1316 Register Src1Reg = MI.getOperand(i: 1).getReg();
1317 Register Src2Reg = MI.getOperand(i: 2).getReg();
1318 Register Src3Reg = MI.getOperand(i: 3).getReg();
1319 Register Src1SubHi = HRI.getSubReg(Reg: Src1Reg, Idx: Hexagon::isub_hi);
1320 Register Src1SubLo = HRI.getSubReg(Reg: Src1Reg, Idx: Hexagon::isub_lo);
1321 Register Src2SubHi = HRI.getSubReg(Reg: Src2Reg, Idx: Hexagon::isub_hi);
1322 Register Src2SubLo = HRI.getSubReg(Reg: Src2Reg, Idx: Hexagon::isub_lo);
1323 Register Src3SubHi = HRI.getSubReg(Reg: Src3Reg, Idx: Hexagon::isub_hi);
1324 Register Src3SubLo = HRI.getSubReg(Reg: Src3Reg, Idx: Hexagon::isub_lo);
1325 BuildMI(BB&: MBB, I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Hexagon::M2_maci),
1326 DestReg: HRI.getSubReg(Reg: DstReg, Idx: Hexagon::isub_hi))
1327 .addReg(RegNo: Src1SubHi)
1328 .addReg(RegNo: Src2SubHi)
1329 .addReg(RegNo: Src3SubHi);
1330 BuildMI(BB&: MBB, I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Hexagon::M2_maci),
1331 DestReg: HRI.getSubReg(Reg: DstReg, Idx: Hexagon::isub_lo))
1332 .addReg(RegNo: Src1SubLo)
1333 .addReg(RegNo: Src2SubLo)
1334 .addReg(RegNo: Src3SubLo);
1335 MBB.erase(I: MI);
1336 MRI.clearKillFlags(Reg: Src1SubHi);
1337 MRI.clearKillFlags(Reg: Src1SubLo);
1338 MRI.clearKillFlags(Reg: Src2SubHi);
1339 MRI.clearKillFlags(Reg: Src2SubLo);
1340 MRI.clearKillFlags(Reg: Src3SubHi);
1341 MRI.clearKillFlags(Reg: Src3SubLo);
1342 return true;
1343 }
1344 case Hexagon::PS_pselect: {
1345 const MachineOperand &Op0 = MI.getOperand(i: 0);
1346 const MachineOperand &Op1 = MI.getOperand(i: 1);
1347 const MachineOperand &Op2 = MI.getOperand(i: 2);
1348 const MachineOperand &Op3 = MI.getOperand(i: 3);
1349 Register Rd = Op0.getReg();
1350 Register Pu = Op1.getReg();
1351 Register Rs = Op2.getReg();
1352 Register Rt = Op3.getReg();
1353 DebugLoc DL = MI.getDebugLoc();
1354 RegState K1 = getKillRegState(B: Op1.isKill());
1355 RegState K2 = getKillRegState(B: Op2.isKill());
1356 RegState K3 = getKillRegState(B: Op3.isKill());
1357 if (Rd != Rs)
1358 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::A2_tfrpt), DestReg: Rd)
1359 .addReg(RegNo: Pu, Flags: (Rd == Rt) ? K1 : RegState::NoFlags)
1360 .addReg(RegNo: Rs, Flags: K2);
1361 if (Rd != Rt)
1362 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::A2_tfrpf), DestReg: Rd)
1363 .addReg(RegNo: Pu, Flags: K1)
1364 .addReg(RegNo: Rt, Flags: K3);
1365 MBB.erase(I: MI);
1366 return true;
1367 }
1368 case Hexagon::PS_vselect: {
1369 const MachineOperand &Op0 = MI.getOperand(i: 0);
1370 const MachineOperand &Op1 = MI.getOperand(i: 1);
1371 const MachineOperand &Op2 = MI.getOperand(i: 2);
1372 const MachineOperand &Op3 = MI.getOperand(i: 3);
1373 getLiveOutRegsAt(Regs&: LiveOut, MI);
1374 bool IsDestLive = !LiveOut.available(MRI, Reg: Op0.getReg());
1375 Register PReg = Op1.getReg();
1376 assert(Op1.getSubReg() == 0);
1377 RegState PState = getRegState(RegOp: Op1);
1378
1379 if (Op0.getReg() != Op2.getReg()) {
1380 RegState S =
1381 Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill : PState;
1382 auto T = BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vcmov))
1383 .add(MO: Op0)
1384 .addReg(RegNo: PReg, Flags: S)
1385 .add(MO: Op2);
1386 if (IsDestLive)
1387 T.addReg(RegNo: Op0.getReg(), Flags: RegState::Implicit);
1388 IsDestLive = true;
1389 }
1390 if (Op0.getReg() != Op3.getReg()) {
1391 auto T = BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vncmov))
1392 .add(MO: Op0)
1393 .addReg(RegNo: PReg, Flags: PState)
1394 .add(MO: Op3);
1395 if (IsDestLive)
1396 T.addReg(RegNo: Op0.getReg(), Flags: RegState::Implicit);
1397 }
1398 MBB.erase(I: MI);
1399 return true;
1400 }
1401 case Hexagon::PS_wselect: {
1402 MachineOperand &Op0 = MI.getOperand(i: 0);
1403 MachineOperand &Op1 = MI.getOperand(i: 1);
1404 MachineOperand &Op2 = MI.getOperand(i: 2);
1405 MachineOperand &Op3 = MI.getOperand(i: 3);
1406 getLiveOutRegsAt(Regs&: LiveOut, MI);
1407 bool IsDestLive = !LiveOut.available(MRI, Reg: Op0.getReg());
1408 Register PReg = Op1.getReg();
1409 assert(Op1.getSubReg() == 0);
1410 RegState PState = getRegState(RegOp: Op1);
1411
1412 if (Op0.getReg() != Op2.getReg()) {
1413 RegState S =
1414 Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill : PState;
1415 Register SrcLo = HRI.getSubReg(Reg: Op2.getReg(), Idx: Hexagon::vsub_lo);
1416 Register SrcHi = HRI.getSubReg(Reg: Op2.getReg(), Idx: Hexagon::vsub_hi);
1417 auto T = BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vccombine))
1418 .add(MO: Op0)
1419 .addReg(RegNo: PReg, Flags: S)
1420 .addReg(RegNo: SrcHi)
1421 .addReg(RegNo: SrcLo);
1422 if (IsDestLive)
1423 T.addReg(RegNo: Op0.getReg(), Flags: RegState::Implicit);
1424 IsDestLive = true;
1425 }
1426 if (Op0.getReg() != Op3.getReg()) {
1427 Register SrcLo = HRI.getSubReg(Reg: Op3.getReg(), Idx: Hexagon::vsub_lo);
1428 Register SrcHi = HRI.getSubReg(Reg: Op3.getReg(), Idx: Hexagon::vsub_hi);
1429 auto T = BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vnccombine))
1430 .add(MO: Op0)
1431 .addReg(RegNo: PReg, Flags: PState)
1432 .addReg(RegNo: SrcHi)
1433 .addReg(RegNo: SrcLo);
1434 if (IsDestLive)
1435 T.addReg(RegNo: Op0.getReg(), Flags: RegState::Implicit);
1436 }
1437 MBB.erase(I: MI);
1438 return true;
1439 }
1440
1441 case Hexagon::PS_crash: {
1442 // Generate a misaligned load that is guaranteed to cause a crash.
1443 class CrashPseudoSourceValue : public PseudoSourceValue {
1444 public:
1445 CrashPseudoSourceValue(const TargetMachine &TM)
1446 : PseudoSourceValue(TargetCustom, TM) {}
1447
1448 bool isConstant(const MachineFrameInfo *) const override {
1449 return false;
1450 }
1451 bool isAliased(const MachineFrameInfo *) const override {
1452 return false;
1453 }
1454 bool mayAlias(const MachineFrameInfo *) const override {
1455 return false;
1456 }
1457 void printCustom(raw_ostream &OS) const override {
1458 OS << "MisalignedCrash";
1459 }
1460 };
1461
1462 static const CrashPseudoSourceValue CrashPSV(MF.getTarget());
1463 MachineMemOperand *MMO = MF.getMachineMemOperand(
1464 PtrInfo: MachinePointerInfo(&CrashPSV),
1465 F: MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile, Size: 8,
1466 BaseAlignment: Align(1));
1467 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::PS_loadrdabs), DestReg: Hexagon::D13)
1468 .addImm(Val: 0xBADC0FEE) // Misaligned load.
1469 .addMemOperand(MMO);
1470 MBB.erase(I: MI);
1471 return true;
1472 }
1473
1474 case Hexagon::PS_tailcall_i:
1475 MI.setDesc(get(Opcode: Hexagon::J2_jump));
1476 return true;
1477 case Hexagon::PS_tailcall_r:
1478 case Hexagon::PS_jmpret:
1479 MI.setDesc(get(Opcode: Hexagon::J2_jumpr));
1480 return true;
1481 case Hexagon::PS_jmprett:
1482 MI.setDesc(get(Opcode: Hexagon::J2_jumprt));
1483 return true;
1484 case Hexagon::PS_jmpretf:
1485 MI.setDesc(get(Opcode: Hexagon::J2_jumprf));
1486 return true;
1487 case Hexagon::PS_jmprettnewpt:
1488 MI.setDesc(get(Opcode: Hexagon::J2_jumprtnewpt));
1489 return true;
1490 case Hexagon::PS_jmpretfnewpt:
1491 MI.setDesc(get(Opcode: Hexagon::J2_jumprfnewpt));
1492 return true;
1493 case Hexagon::PS_jmprettnew:
1494 MI.setDesc(get(Opcode: Hexagon::J2_jumprtnew));
1495 return true;
1496 case Hexagon::PS_jmpretfnew:
1497 MI.setDesc(get(Opcode: Hexagon::J2_jumprfnew));
1498 return true;
1499
1500 case Hexagon::PS_loadrub_pci:
1501 return RealCirc(Hexagon::L2_loadrub_pci, /*HasImm*/true, /*MxOp*/4);
1502 case Hexagon::PS_loadrb_pci:
1503 return RealCirc(Hexagon::L2_loadrb_pci, /*HasImm*/true, /*MxOp*/4);
1504 case Hexagon::PS_loadruh_pci:
1505 return RealCirc(Hexagon::L2_loadruh_pci, /*HasImm*/true, /*MxOp*/4);
1506 case Hexagon::PS_loadrh_pci:
1507 return RealCirc(Hexagon::L2_loadrh_pci, /*HasImm*/true, /*MxOp*/4);
1508 case Hexagon::PS_loadri_pci:
1509 return RealCirc(Hexagon::L2_loadri_pci, /*HasImm*/true, /*MxOp*/4);
1510 case Hexagon::PS_loadrd_pci:
1511 return RealCirc(Hexagon::L2_loadrd_pci, /*HasImm*/true, /*MxOp*/4);
1512 case Hexagon::PS_loadrub_pcr:
1513 return RealCirc(Hexagon::L2_loadrub_pcr, /*HasImm*/false, /*MxOp*/3);
1514 case Hexagon::PS_loadrb_pcr:
1515 return RealCirc(Hexagon::L2_loadrb_pcr, /*HasImm*/false, /*MxOp*/3);
1516 case Hexagon::PS_loadruh_pcr:
1517 return RealCirc(Hexagon::L2_loadruh_pcr, /*HasImm*/false, /*MxOp*/3);
1518 case Hexagon::PS_loadrh_pcr:
1519 return RealCirc(Hexagon::L2_loadrh_pcr, /*HasImm*/false, /*MxOp*/3);
1520 case Hexagon::PS_loadri_pcr:
1521 return RealCirc(Hexagon::L2_loadri_pcr, /*HasImm*/false, /*MxOp*/3);
1522 case Hexagon::PS_loadrd_pcr:
1523 return RealCirc(Hexagon::L2_loadrd_pcr, /*HasImm*/false, /*MxOp*/3);
1524 case Hexagon::PS_storerb_pci:
1525 return RealCirc(Hexagon::S2_storerb_pci, /*HasImm*/true, /*MxOp*/3);
1526 case Hexagon::PS_storerh_pci:
1527 return RealCirc(Hexagon::S2_storerh_pci, /*HasImm*/true, /*MxOp*/3);
1528 case Hexagon::PS_storerf_pci:
1529 return RealCirc(Hexagon::S2_storerf_pci, /*HasImm*/true, /*MxOp*/3);
1530 case Hexagon::PS_storeri_pci:
1531 return RealCirc(Hexagon::S2_storeri_pci, /*HasImm*/true, /*MxOp*/3);
1532 case Hexagon::PS_storerd_pci:
1533 return RealCirc(Hexagon::S2_storerd_pci, /*HasImm*/true, /*MxOp*/3);
1534 case Hexagon::PS_storerb_pcr:
1535 return RealCirc(Hexagon::S2_storerb_pcr, /*HasImm*/false, /*MxOp*/2);
1536 case Hexagon::PS_storerh_pcr:
1537 return RealCirc(Hexagon::S2_storerh_pcr, /*HasImm*/false, /*MxOp*/2);
1538 case Hexagon::PS_storerf_pcr:
1539 return RealCirc(Hexagon::S2_storerf_pcr, /*HasImm*/false, /*MxOp*/2);
1540 case Hexagon::PS_storeri_pcr:
1541 return RealCirc(Hexagon::S2_storeri_pcr, /*HasImm*/false, /*MxOp*/2);
1542 case Hexagon::PS_storerd_pcr:
1543 return RealCirc(Hexagon::S2_storerd_pcr, /*HasImm*/false, /*MxOp*/2);
1544 }
1545
1546 return false;
1547}
1548
1549MachineBasicBlock::instr_iterator
1550HexagonInstrInfo::expandVGatherPseudo(MachineInstr &MI) const {
1551 MachineBasicBlock &MBB = *MI.getParent();
1552 const DebugLoc &DL = MI.getDebugLoc();
1553 unsigned Opc = MI.getOpcode();
1554 MachineBasicBlock::iterator First;
1555
1556 switch (Opc) {
1557 case Hexagon::V6_vgather_vscatter_mh_pseudo:
1558 // This is mainly a place holder. It will be extended.
1559 First = BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vgathermh))
1560 .add(MO: MI.getOperand(i: 2))
1561 .add(MO: MI.getOperand(i: 3))
1562 .add(MO: MI.getOperand(i: 4));
1563 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vscattermh))
1564 .add(MO: MI.getOperand(i: 2))
1565 .add(MO: MI.getOperand(i: 3))
1566 .add(MO: MI.getOperand(i: 4))
1567 .addReg(RegNo: Hexagon::VTMP);
1568 MBB.erase(I: MI);
1569 return First.getInstrIterator();
1570 case Hexagon::V6_vgathermh_pseudo:
1571 First = BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vgathermh))
1572 .add(MO: MI.getOperand(i: 2))
1573 .add(MO: MI.getOperand(i: 3))
1574 .add(MO: MI.getOperand(i: 4));
1575 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vS32b_new_ai))
1576 .add(MO: MI.getOperand(i: 0))
1577 .addImm(Val: MI.getOperand(i: 1).getImm())
1578 .addReg(RegNo: Hexagon::VTMP);
1579 MBB.erase(I: MI);
1580 return First.getInstrIterator();
1581
1582 case Hexagon::V6_vgathermw_pseudo:
1583 First = BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vgathermw))
1584 .add(MO: MI.getOperand(i: 2))
1585 .add(MO: MI.getOperand(i: 3))
1586 .add(MO: MI.getOperand(i: 4));
1587 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vS32b_new_ai))
1588 .add(MO: MI.getOperand(i: 0))
1589 .addImm(Val: MI.getOperand(i: 1).getImm())
1590 .addReg(RegNo: Hexagon::VTMP);
1591 MBB.erase(I: MI);
1592 return First.getInstrIterator();
1593
1594 case Hexagon::V6_vgathermhw_pseudo:
1595 First = BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vgathermhw))
1596 .add(MO: MI.getOperand(i: 2))
1597 .add(MO: MI.getOperand(i: 3))
1598 .add(MO: MI.getOperand(i: 4));
1599 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vS32b_new_ai))
1600 .add(MO: MI.getOperand(i: 0))
1601 .addImm(Val: MI.getOperand(i: 1).getImm())
1602 .addReg(RegNo: Hexagon::VTMP);
1603 MBB.erase(I: MI);
1604 return First.getInstrIterator();
1605
1606 case Hexagon::V6_vgathermhq_pseudo:
1607 First = BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vgathermhq))
1608 .add(MO: MI.getOperand(i: 2))
1609 .add(MO: MI.getOperand(i: 3))
1610 .add(MO: MI.getOperand(i: 4))
1611 .add(MO: MI.getOperand(i: 5));
1612 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vS32b_new_ai))
1613 .add(MO: MI.getOperand(i: 0))
1614 .addImm(Val: MI.getOperand(i: 1).getImm())
1615 .addReg(RegNo: Hexagon::VTMP);
1616 MBB.erase(I: MI);
1617 return First.getInstrIterator();
1618
1619 case Hexagon::V6_vgathermwq_pseudo:
1620 First = BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vgathermwq))
1621 .add(MO: MI.getOperand(i: 2))
1622 .add(MO: MI.getOperand(i: 3))
1623 .add(MO: MI.getOperand(i: 4))
1624 .add(MO: MI.getOperand(i: 5));
1625 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vS32b_new_ai))
1626 .add(MO: MI.getOperand(i: 0))
1627 .addImm(Val: MI.getOperand(i: 1).getImm())
1628 .addReg(RegNo: Hexagon::VTMP);
1629 MBB.erase(I: MI);
1630 return First.getInstrIterator();
1631
1632 case Hexagon::V6_vgathermhwq_pseudo:
1633 First = BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vgathermhwq))
1634 .add(MO: MI.getOperand(i: 2))
1635 .add(MO: MI.getOperand(i: 3))
1636 .add(MO: MI.getOperand(i: 4))
1637 .add(MO: MI.getOperand(i: 5));
1638 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vS32b_new_ai))
1639 .add(MO: MI.getOperand(i: 0))
1640 .addImm(Val: MI.getOperand(i: 1).getImm())
1641 .addReg(RegNo: Hexagon::VTMP);
1642 MBB.erase(I: MI);
1643 return First.getInstrIterator();
1644 }
1645
1646 return MI.getIterator();
1647}
1648
1649// We indicate that we want to reverse the branch by
1650// inserting the reversed branching opcode.
1651bool HexagonInstrInfo::reverseBranchCondition(
1652 SmallVectorImpl<MachineOperand> &Cond) const {
1653 if (Cond.empty())
1654 return true;
1655 assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
1656 unsigned opcode = Cond[0].getImm();
1657 //unsigned temp;
1658 assert(get(opcode).isBranch() && "Should be a branching condition.");
1659 if (isEndLoopN(Opcode: opcode))
1660 return true;
1661 unsigned NewOpcode = getInvertedPredicatedOpcode(Opc: opcode);
1662 Cond[0].setImm(NewOpcode);
1663 return false;
1664}
1665
1666void HexagonInstrInfo::insertNoop(MachineBasicBlock &MBB,
1667 MachineBasicBlock::iterator MI) const {
1668 DebugLoc DL;
1669 BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: get(Opcode: Hexagon::A2_nop));
1670}
1671
1672bool HexagonInstrInfo::isPostIncrement(const MachineInstr &MI) const {
1673 return getAddrMode(MI) == HexagonII::PostInc;
1674}
1675
1676bool HexagonInstrInfo::isPostIncWithImmOffset(const MachineInstr &MI) const {
1677 unsigned BasePos, OffsetPos;
1678 if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
1679 return false;
1680 return isPostIncrement(MI) && MI.getOperand(i: OffsetPos).isImm();
1681}
1682
1683// Returns true if an instruction is predicated irrespective of the predicate
1684// sense. For example, all of the following will return true.
1685// if (p0) R1 = add(R2, R3)
1686// if (!p0) R1 = add(R2, R3)
1687// if (p0.new) R1 = add(R2, R3)
1688// if (!p0.new) R1 = add(R2, R3)
1689// Note: New-value stores are not included here as in the current
1690// implementation, we don't need to check their predicate sense.
1691bool HexagonInstrInfo::isPredicated(const MachineInstr &MI) const {
1692 const uint64_t F = MI.getDesc().TSFlags;
1693 return (F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask;
1694}
1695
1696bool HexagonInstrInfo::PredicateInstruction(
1697 MachineInstr &MI, ArrayRef<MachineOperand> Cond) const {
1698 if (Cond.empty() || isNewValueJump(Opcode: Cond[0].getImm()) ||
1699 isEndLoopN(Opcode: Cond[0].getImm())) {
1700 LLVM_DEBUG(dbgs() << "\nCannot predicate:"; MI.dump(););
1701 return false;
1702 }
1703 int Opc = MI.getOpcode();
1704 assert (isPredicable(MI) && "Expected predicable instruction");
1705 bool invertJump = predOpcodeHasNot(Cond);
1706
1707 // We have to predicate MI "in place", i.e. after this function returns,
1708 // MI will need to be transformed into a predicated form. To avoid com-
1709 // plicated manipulations with the operands (handling tied operands,
1710 // etc.), build a new temporary instruction, then overwrite MI with it.
1711
1712 MachineBasicBlock &B = *MI.getParent();
1713 DebugLoc DL = MI.getDebugLoc();
1714 unsigned PredOpc = getCondOpcode(Opc, sense: invertJump);
1715 MachineInstrBuilder T = BuildMI(BB&: B, I&: MI, MIMD: DL, MCID: get(Opcode: PredOpc));
1716 unsigned NOp = 0, NumOps = MI.getNumOperands();
1717 while (NOp < NumOps) {
1718 MachineOperand &Op = MI.getOperand(i: NOp);
1719 if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1720 break;
1721 T.add(MO: Op);
1722 NOp++;
1723 }
1724
1725 Register PredReg;
1726 unsigned PredRegPos;
1727 RegState PredRegFlags = {};
1728 bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1729 (void)GotPredReg;
1730 assert(GotPredReg);
1731 T.addReg(RegNo: PredReg, Flags: PredRegFlags);
1732 while (NOp < NumOps)
1733 T.add(MO: MI.getOperand(i: NOp++));
1734
1735 MI.setDesc(get(Opcode: PredOpc));
1736 while (unsigned n = MI.getNumOperands())
1737 MI.removeOperand(OpNo: n-1);
1738 for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1739 MI.addOperand(Op: T->getOperand(i));
1740
1741 MachineBasicBlock::instr_iterator TI = T->getIterator();
1742 B.erase(I: TI);
1743
1744 MachineRegisterInfo &MRI = B.getParent()->getRegInfo();
1745 MRI.clearKillFlags(Reg: PredReg);
1746 return true;
1747}
1748
1749bool HexagonInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1750 ArrayRef<MachineOperand> Pred2) const {
1751 // TODO: Fix this
1752 return false;
1753}
1754
1755bool HexagonInstrInfo::ClobbersPredicate(MachineInstr &MI,
1756 std::vector<MachineOperand> &Pred,
1757 bool SkipDead) const {
1758 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1759
1760 for (const MachineOperand &MO : MI.operands()) {
1761 if (MO.isReg()) {
1762 if (!MO.isDef())
1763 continue;
1764 const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(Reg: MO.getReg());
1765 if (RC == &Hexagon::PredRegsRegClass) {
1766 Pred.push_back(x: MO);
1767 return true;
1768 }
1769 continue;
1770 } else if (MO.isRegMask()) {
1771 for (Register PR : Hexagon::PredRegsRegClass) {
1772 if (!MI.modifiesRegister(Reg: PR, TRI: &HRI))
1773 continue;
1774 Pred.push_back(x: MO);
1775 return true;
1776 }
1777 }
1778 }
1779 return false;
1780}
1781
1782bool HexagonInstrInfo::isPredicable(const MachineInstr &MI) const {
1783 if (!MI.getDesc().isPredicable())
1784 return false;
1785
1786 if (MI.isCall() || isTailCall(MI)) {
1787 if (!Subtarget.usePredicatedCalls())
1788 return false;
1789 }
1790
1791 // HVX loads are not predicable on v60, but are on v62.
1792 if (!Subtarget.hasV62Ops()) {
1793 switch (MI.getOpcode()) {
1794 case Hexagon::V6_vL32b_ai:
1795 case Hexagon::V6_vL32b_pi:
1796 case Hexagon::V6_vL32b_ppu:
1797 case Hexagon::V6_vL32b_cur_ai:
1798 case Hexagon::V6_vL32b_cur_pi:
1799 case Hexagon::V6_vL32b_cur_ppu:
1800 case Hexagon::V6_vL32b_nt_ai:
1801 case Hexagon::V6_vL32b_nt_pi:
1802 case Hexagon::V6_vL32b_nt_ppu:
1803 case Hexagon::V6_vL32b_tmp_ai:
1804 case Hexagon::V6_vL32b_tmp_pi:
1805 case Hexagon::V6_vL32b_tmp_ppu:
1806 case Hexagon::V6_vL32b_nt_cur_ai:
1807 case Hexagon::V6_vL32b_nt_cur_pi:
1808 case Hexagon::V6_vL32b_nt_cur_ppu:
1809 case Hexagon::V6_vL32b_nt_tmp_ai:
1810 case Hexagon::V6_vL32b_nt_tmp_pi:
1811 case Hexagon::V6_vL32b_nt_tmp_ppu:
1812 return false;
1813 }
1814 }
1815 return true;
1816}
1817
1818bool HexagonInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst,
1819 bool Invert) const {
1820 if (Invert)
1821 return false;
1822
1823 switch (Inst.getOpcode()) {
1824 // TODO: Add more instructions to be handled by MachineCombiner.
1825 case Hexagon::F2_sfadd:
1826 return Inst.getFlag(Flag: MachineInstr::MIFlag::FmReassoc);
1827 default:
1828 return false;
1829 }
1830}
1831
1832bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
1833 const MachineBasicBlock *MBB,
1834 const MachineFunction &MF) const {
1835 // Debug info is never a scheduling boundary. It's necessary to be explicit
1836 // due to the special treatment of IT instructions below, otherwise a
1837 // dbg_value followed by an IT will result in the IT instruction being
1838 // considered a scheduling hazard, which is wrong. It should be the actual
1839 // instruction preceding the dbg_value instruction(s), just like it is
1840 // when debug info is not present.
1841 if (MI.isDebugInstr())
1842 return false;
1843
1844 // Throwing call is a boundary.
1845 if (MI.isCall()) {
1846 // Don't mess around with no return calls.
1847 if (doesNotReturn(CallMI: MI))
1848 return true;
1849 // If any of the block's successors is a landing pad, this could be a
1850 // throwing call.
1851 for (auto *I : MBB->successors())
1852 if (I->isEHPad())
1853 return true;
1854 }
1855
1856 // Terminators and labels can't be scheduled around.
1857 if (MI.getDesc().isTerminator() || MI.isPosition())
1858 return true;
1859
1860 // INLINEASM_BR can jump to another block
1861 if (MI.getOpcode() == TargetOpcode::INLINEASM_BR)
1862 return true;
1863
1864 if (MI.isInlineAsm() && !ScheduleInlineAsm)
1865 return true;
1866
1867 return false;
1868}
1869
1870/// Measure the specified inline asm to determine an approximation of its
1871/// length.
1872/// Comments (which run till the next SeparatorString or newline) do not
1873/// count as an instruction.
1874/// Any other non-whitespace text is considered an instruction, with
1875/// multiple instructions separated by SeparatorString or newlines.
1876/// Variable-length instructions are not handled here; this function
1877/// may be overloaded in the target code to do that.
1878/// Hexagon counts the number of ##'s and adjust for that many
1879/// constant exenders.
1880unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str,
1881 const MCAsmInfo &MAI,
1882 const TargetSubtargetInfo *STI) const {
1883 StringRef AStr(Str);
1884 // Count the number of instructions in the asm.
1885 bool atInsnStart = true;
1886 unsigned Length = 0;
1887 const unsigned MaxInstLength = MAI.getMaxInstLength(STI);
1888 for (; *Str; ++Str) {
1889 if (*Str == '\n' || strncmp(s1: Str, s2: MAI.getSeparatorString(),
1890 n: strlen(s: MAI.getSeparatorString())) == 0)
1891 atInsnStart = true;
1892 if (atInsnStart && !isSpace(C: static_cast<unsigned char>(*Str))) {
1893 Length += MaxInstLength;
1894 atInsnStart = false;
1895 }
1896 if (atInsnStart && strncmp(s1: Str, s2: MAI.getCommentString().data(),
1897 n: MAI.getCommentString().size()) == 0)
1898 atInsnStart = false;
1899 }
1900
1901 // Add to size number of constant extenders seen * 4.
1902 StringRef Occ("##");
1903 Length += AStr.count(Str: Occ)*4;
1904 return Length;
1905}
1906
1907ScheduleHazardRecognizer*
1908HexagonInstrInfo::CreateTargetPostRAHazardRecognizer(
1909 const InstrItineraryData *II, const ScheduleDAG *DAG) const {
1910 if (UseDFAHazardRec)
1911 return new HexagonHazardRecognizer(II, this, Subtarget);
1912 return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
1913}
1914
1915/// For a comparison instruction, return the source registers in
1916/// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
1917/// compares against in CmpValue. Return true if the comparison instruction
1918/// can be analyzed.
1919bool HexagonInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
1920 Register &SrcReg2, int64_t &Mask,
1921 int64_t &Value) const {
1922 unsigned Opc = MI.getOpcode();
1923
1924 // Set mask and the first source register.
1925 switch (Opc) {
1926 case Hexagon::C2_cmpeq:
1927 case Hexagon::C2_cmpeqp:
1928 case Hexagon::C2_cmpgt:
1929 case Hexagon::C2_cmpgtp:
1930 case Hexagon::C2_cmpgtu:
1931 case Hexagon::C2_cmpgtup:
1932 case Hexagon::C4_cmpneq:
1933 case Hexagon::C4_cmplte:
1934 case Hexagon::C4_cmplteu:
1935 case Hexagon::C2_cmpeqi:
1936 case Hexagon::C2_cmpgti:
1937 case Hexagon::C2_cmpgtui:
1938 case Hexagon::C4_cmpneqi:
1939 case Hexagon::C4_cmplteui:
1940 case Hexagon::C4_cmpltei:
1941 SrcReg = MI.getOperand(i: 1).getReg();
1942 Mask = ~0;
1943 break;
1944 case Hexagon::A4_cmpbeq:
1945 case Hexagon::A4_cmpbgt:
1946 case Hexagon::A4_cmpbgtu:
1947 case Hexagon::A4_cmpbeqi:
1948 case Hexagon::A4_cmpbgti:
1949 case Hexagon::A4_cmpbgtui:
1950 SrcReg = MI.getOperand(i: 1).getReg();
1951 Mask = 0xFF;
1952 break;
1953 case Hexagon::A4_cmpheq:
1954 case Hexagon::A4_cmphgt:
1955 case Hexagon::A4_cmphgtu:
1956 case Hexagon::A4_cmpheqi:
1957 case Hexagon::A4_cmphgti:
1958 case Hexagon::A4_cmphgtui:
1959 SrcReg = MI.getOperand(i: 1).getReg();
1960 Mask = 0xFFFF;
1961 break;
1962 }
1963
1964 // Set the value/second source register.
1965 switch (Opc) {
1966 case Hexagon::C2_cmpeq:
1967 case Hexagon::C2_cmpeqp:
1968 case Hexagon::C2_cmpgt:
1969 case Hexagon::C2_cmpgtp:
1970 case Hexagon::C2_cmpgtu:
1971 case Hexagon::C2_cmpgtup:
1972 case Hexagon::A4_cmpbeq:
1973 case Hexagon::A4_cmpbgt:
1974 case Hexagon::A4_cmpbgtu:
1975 case Hexagon::A4_cmpheq:
1976 case Hexagon::A4_cmphgt:
1977 case Hexagon::A4_cmphgtu:
1978 case Hexagon::C4_cmpneq:
1979 case Hexagon::C4_cmplte:
1980 case Hexagon::C4_cmplteu:
1981 SrcReg2 = MI.getOperand(i: 2).getReg();
1982 Value = 0;
1983 return true;
1984
1985 case Hexagon::C2_cmpeqi:
1986 case Hexagon::C2_cmpgtui:
1987 case Hexagon::C2_cmpgti:
1988 case Hexagon::C4_cmpneqi:
1989 case Hexagon::C4_cmplteui:
1990 case Hexagon::C4_cmpltei:
1991 case Hexagon::A4_cmpbeqi:
1992 case Hexagon::A4_cmpbgti:
1993 case Hexagon::A4_cmpbgtui:
1994 case Hexagon::A4_cmpheqi:
1995 case Hexagon::A4_cmphgti:
1996 case Hexagon::A4_cmphgtui: {
1997 SrcReg2 = 0;
1998 const MachineOperand &Op2 = MI.getOperand(i: 2);
1999 if (!Op2.isImm())
2000 return false;
2001 Value = MI.getOperand(i: 2).getImm();
2002 return true;
2003 }
2004 }
2005
2006 return false;
2007}
2008
2009unsigned HexagonInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2010 const MachineInstr &MI,
2011 unsigned *PredCost) const {
2012 return getInstrTimingClassLatency(ItinData, MI);
2013}
2014
2015DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(
2016 const TargetSubtargetInfo &STI) const {
2017 const InstrItineraryData *II = STI.getInstrItineraryData();
2018 return static_cast<const HexagonSubtarget&>(STI).createDFAPacketizer(IID: II);
2019}
2020
2021// Inspired by this pair:
2022// %r13 = L2_loadri_io %r29, 136; mem:LD4[FixedStack0]
2023// S2_storeri_io %r29, 132, killed %r1; flags: mem:ST4[FixedStack1]
2024// Currently AA considers the addresses in these instructions to be aliasing.
2025bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(
2026 const MachineInstr &MIa, const MachineInstr &MIb) const {
2027 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
2028 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
2029 return false;
2030
2031 // Instructions that are pure loads, not loads and stores like memops are not
2032 // dependent.
2033 if (MIa.mayLoad() && !isMemOp(MI: MIa) && MIb.mayLoad() && !isMemOp(MI: MIb))
2034 return true;
2035
2036 // Get the base register in MIa.
2037 unsigned BasePosA, OffsetPosA;
2038 if (!getBaseAndOffsetPosition(MI: MIa, BasePos&: BasePosA, OffsetPos&: OffsetPosA))
2039 return false;
2040 const MachineOperand &BaseA = MIa.getOperand(i: BasePosA);
2041 Register BaseRegA = BaseA.getReg();
2042 unsigned BaseSubA = BaseA.getSubReg();
2043
2044 // Get the base register in MIb.
2045 unsigned BasePosB, OffsetPosB;
2046 if (!getBaseAndOffsetPosition(MI: MIb, BasePos&: BasePosB, OffsetPos&: OffsetPosB))
2047 return false;
2048 const MachineOperand &BaseB = MIb.getOperand(i: BasePosB);
2049 Register BaseRegB = BaseB.getReg();
2050 unsigned BaseSubB = BaseB.getSubReg();
2051
2052 if (BaseRegA != BaseRegB || BaseSubA != BaseSubB)
2053 return false;
2054
2055 // Get the access sizes.
2056 unsigned SizeA = getMemAccessSize(MI: MIa);
2057 unsigned SizeB = getMemAccessSize(MI: MIb);
2058
2059 // Get the offsets. Handle immediates only for now.
2060 const MachineOperand &OffA = MIa.getOperand(i: OffsetPosA);
2061 const MachineOperand &OffB = MIb.getOperand(i: OffsetPosB);
2062 if (!MIa.getOperand(i: OffsetPosA).isImm() ||
2063 !MIb.getOperand(i: OffsetPosB).isImm())
2064 return false;
2065 int OffsetA = isPostIncrement(MI: MIa) ? 0 : OffA.getImm();
2066 int OffsetB = isPostIncrement(MI: MIb) ? 0 : OffB.getImm();
2067
2068 // This is a mem access with the same base register and known offsets from it.
2069 // Reason about it.
2070 if (OffsetA > OffsetB) {
2071 uint64_t OffDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
2072 return SizeB <= OffDiff;
2073 }
2074 if (OffsetA < OffsetB) {
2075 uint64_t OffDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
2076 return SizeA <= OffDiff;
2077 }
2078
2079 return false;
2080}
2081
2082/// If the instruction is an increment of a constant value, return the amount.
2083bool HexagonInstrInfo::getIncrementValue(const MachineInstr &MI,
2084 int &Value) const {
2085 if (isPostIncrement(MI)) {
2086 unsigned BasePos = 0, OffsetPos = 0;
2087 if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
2088 return false;
2089 const MachineOperand &OffsetOp = MI.getOperand(i: OffsetPos);
2090 if (OffsetOp.isImm()) {
2091 Value = OffsetOp.getImm();
2092 return true;
2093 }
2094 } else if (MI.getOpcode() == Hexagon::A2_addi) {
2095 const MachineOperand &AddOp = MI.getOperand(i: 2);
2096 if (AddOp.isImm()) {
2097 Value = AddOp.getImm();
2098 return true;
2099 }
2100 }
2101
2102 return false;
2103}
2104
2105std::pair<unsigned, unsigned>
2106HexagonInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
2107 return std::make_pair(x: TF & ~HexagonII::MO_Bitmasks,
2108 y: TF & HexagonII::MO_Bitmasks);
2109}
2110
2111ArrayRef<std::pair<unsigned, const char*>>
2112HexagonInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
2113 using namespace HexagonII;
2114
2115 static const std::pair<unsigned, const char*> Flags[] = {
2116 {MO_PCREL, "hexagon-pcrel"},
2117 {MO_GOT, "hexagon-got"},
2118 {MO_LO16, "hexagon-lo16"},
2119 {MO_HI16, "hexagon-hi16"},
2120 {MO_GPREL, "hexagon-gprel"},
2121 {MO_GDGOT, "hexagon-gdgot"},
2122 {MO_GDPLT, "hexagon-gdplt"},
2123 {MO_IE, "hexagon-ie"},
2124 {MO_IEGOT, "hexagon-iegot"},
2125 {MO_TPREL, "hexagon-tprel"}
2126 };
2127 return ArrayRef(Flags);
2128}
2129
2130ArrayRef<std::pair<unsigned, const char*>>
2131HexagonInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
2132 using namespace HexagonII;
2133
2134 static const std::pair<unsigned, const char*> Flags[] = {
2135 {HMOTF_ConstExtended, "hexagon-ext"}
2136 };
2137 return ArrayRef(Flags);
2138}
2139
2140Register HexagonInstrInfo::createVR(MachineFunction *MF, MVT VT) const {
2141 MachineRegisterInfo &MRI = MF->getRegInfo();
2142 const TargetRegisterClass *TRC;
2143 if (VT == MVT::i1) {
2144 TRC = &Hexagon::PredRegsRegClass;
2145 } else if (VT == MVT::i32 || VT == MVT::f32) {
2146 TRC = &Hexagon::IntRegsRegClass;
2147 } else if (VT == MVT::i64 || VT == MVT::f64) {
2148 TRC = &Hexagon::DoubleRegsRegClass;
2149 } else {
2150 llvm_unreachable("Cannot handle this register class");
2151 }
2152
2153 Register NewReg = MRI.createVirtualRegister(RegClass: TRC);
2154 return NewReg;
2155}
2156
2157bool HexagonInstrInfo::isAbsoluteSet(const MachineInstr &MI) const {
2158 return (getAddrMode(MI) == HexagonII::AbsoluteSet);
2159}
2160
2161bool HexagonInstrInfo::isAccumulator(const MachineInstr &MI) const {
2162 const uint64_t F = MI.getDesc().TSFlags;
2163 return((F >> HexagonII::AccumulatorPos) & HexagonII::AccumulatorMask);
2164}
2165
2166bool HexagonInstrInfo::isBaseImmOffset(const MachineInstr &MI) const {
2167 return getAddrMode(MI) == HexagonII::BaseImmOffset;
2168}
2169
2170bool HexagonInstrInfo::isComplex(const MachineInstr &MI) const {
2171 return !isTC1(MI) && !isTC2Early(MI) && !MI.getDesc().mayLoad() &&
2172 !MI.getDesc().mayStore() &&
2173 MI.getDesc().getOpcode() != Hexagon::S2_allocframe &&
2174 MI.getDesc().getOpcode() != Hexagon::L2_deallocframe &&
2175 !isMemOp(MI) && !MI.isBranch() && !MI.isReturn() && !MI.isCall();
2176}
2177
2178// Return true if the instruction is a compound branch instruction.
2179bool HexagonInstrInfo::isCompoundBranchInstr(const MachineInstr &MI) const {
2180 return getType(MI) == HexagonII::TypeCJ && MI.isBranch();
2181}
2182
2183// TODO: In order to have isExtendable for fpimm/f32Ext, we need to handle
2184// isFPImm and later getFPImm as well.
2185bool HexagonInstrInfo::isConstExtended(const MachineInstr &MI) const {
2186 const uint64_t F = MI.getDesc().TSFlags;
2187 unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
2188 if (isExtended) // Instruction must be extended.
2189 return true;
2190
2191 unsigned isExtendable =
2192 (F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
2193 if (!isExtendable)
2194 return false;
2195
2196 if (MI.isCall())
2197 return false;
2198
2199 short ExtOpNum = getCExtOpNum(MI);
2200 const MachineOperand &MO = MI.getOperand(i: ExtOpNum);
2201 // Use MO operand flags to determine if MO
2202 // has the HMOTF_ConstExtended flag set.
2203 if (MO.getTargetFlags() & HexagonII::HMOTF_ConstExtended)
2204 return true;
2205 // If this is a Machine BB address we are talking about, and it is
2206 // not marked as extended, say so.
2207 if (MO.isMBB())
2208 return false;
2209
2210 // We could be using an instruction with an extendable immediate and shoehorn
2211 // a global address into it. If it is a global address it will be constant
2212 // extended. We do this for COMBINE.
2213 if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
2214 MO.isJTI() || MO.isCPI() || MO.isFPImm())
2215 return true;
2216
2217 // If the extendable operand is not 'Immediate' type, the instruction should
2218 // have 'isExtended' flag set.
2219 assert(MO.isImm() && "Extendable operand must be Immediate type");
2220
2221 int64_t Value = MO.getImm();
2222 if ((F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask) {
2223 int32_t SValue = Value;
2224 int32_t MinValue = getMinValue(MI);
2225 int32_t MaxValue = getMaxValue(MI);
2226 return SValue < MinValue || SValue > MaxValue;
2227 }
2228 uint32_t UValue = Value;
2229 uint32_t MinValue = getMinValue(MI);
2230 uint32_t MaxValue = getMaxValue(MI);
2231 return UValue < MinValue || UValue > MaxValue;
2232}
2233
2234bool HexagonInstrInfo::isDeallocRet(const MachineInstr &MI) const {
2235 switch (MI.getOpcode()) {
2236 case Hexagon::L4_return:
2237 case Hexagon::L4_return_t:
2238 case Hexagon::L4_return_f:
2239 case Hexagon::L4_return_tnew_pnt:
2240 case Hexagon::L4_return_fnew_pnt:
2241 case Hexagon::L4_return_tnew_pt:
2242 case Hexagon::L4_return_fnew_pt:
2243 return true;
2244 }
2245 return false;
2246}
2247
2248// Return true when ConsMI uses a register defined by ProdMI.
2249bool HexagonInstrInfo::isDependent(const MachineInstr &ProdMI,
2250 const MachineInstr &ConsMI) const {
2251 if (!ProdMI.getDesc().getNumDefs())
2252 return false;
2253 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
2254
2255 SmallVector<Register, 4> DefsA;
2256 SmallVector<Register, 4> DefsB;
2257 SmallVector<Register, 8> UsesA;
2258 SmallVector<Register, 8> UsesB;
2259
2260 parseOperands(MI: ProdMI, Defs&: DefsA, Uses&: UsesA);
2261 parseOperands(MI: ConsMI, Defs&: DefsB, Uses&: UsesB);
2262
2263 for (auto &RegA : DefsA)
2264 for (auto &RegB : UsesB) {
2265 // True data dependency.
2266 if (RegA == RegB)
2267 return true;
2268
2269 if (RegA.isPhysical() && llvm::is_contained(Range: HRI.subregs(Reg: RegA), Element: RegB))
2270 return true;
2271
2272 if (RegB.isPhysical() && llvm::is_contained(Range: HRI.subregs(Reg: RegB), Element: RegA))
2273 return true;
2274 }
2275
2276 return false;
2277}
2278
2279// Returns true if the instruction is already a .cur.
2280bool HexagonInstrInfo::isDotCurInst(const MachineInstr &MI) const {
2281 switch (MI.getOpcode()) {
2282 case Hexagon::V6_vL32b_cur_pi:
2283 case Hexagon::V6_vL32b_cur_ai:
2284 return true;
2285 }
2286 return false;
2287}
2288
2289// Returns true, if any one of the operands is a dot new
2290// insn, whether it is predicated dot new or register dot new.
2291bool HexagonInstrInfo::isDotNewInst(const MachineInstr &MI) const {
2292 if (isNewValueInst(MI) || (isPredicated(MI) && isPredicatedNew(MI)))
2293 return true;
2294
2295 return false;
2296}
2297
2298/// Symmetrical. See if these two instructions are fit for duplex pair.
2299bool HexagonInstrInfo::isDuplexPair(const MachineInstr &MIa,
2300 const MachineInstr &MIb) const {
2301 HexagonII::SubInstructionGroup MIaG = getDuplexCandidateGroup(MI: MIa);
2302 HexagonII::SubInstructionGroup MIbG = getDuplexCandidateGroup(MI: MIb);
2303 return (isDuplexPairMatch(Ga: MIaG, Gb: MIbG) || isDuplexPairMatch(Ga: MIbG, Gb: MIaG));
2304}
2305
2306bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {
2307 return (Opcode == Hexagon::ENDLOOP0 ||
2308 Opcode == Hexagon::ENDLOOP1);
2309}
2310
2311bool HexagonInstrInfo::isExpr(unsigned OpType) const {
2312 switch(OpType) {
2313 case MachineOperand::MO_MachineBasicBlock:
2314 case MachineOperand::MO_GlobalAddress:
2315 case MachineOperand::MO_ExternalSymbol:
2316 case MachineOperand::MO_JumpTableIndex:
2317 case MachineOperand::MO_ConstantPoolIndex:
2318 case MachineOperand::MO_BlockAddress:
2319 return true;
2320 default:
2321 return false;
2322 }
2323}
2324
2325bool HexagonInstrInfo::isExtendable(const MachineInstr &MI) const {
2326 const MCInstrDesc &MID = MI.getDesc();
2327 const uint64_t F = MID.TSFlags;
2328 if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
2329 return true;
2330
2331 // TODO: This is largely obsolete now. Will need to be removed
2332 // in consecutive patches.
2333 switch (MI.getOpcode()) {
2334 // PS_fi and PS_fia remain special cases.
2335 case Hexagon::PS_fi:
2336 case Hexagon::PS_fia:
2337 return true;
2338 default:
2339 return false;
2340 }
2341 return false;
2342}
2343
2344// This returns true in two cases:
2345// - The OP code itself indicates that this is an extended instruction.
2346// - One of MOs has been marked with HMOTF_ConstExtended flag.
2347bool HexagonInstrInfo::isExtended(const MachineInstr &MI) const {
2348 // First check if this is permanently extended op code.
2349 const uint64_t F = MI.getDesc().TSFlags;
2350 if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
2351 return true;
2352 // Use MO operand flags to determine if one of MI's operands
2353 // has HMOTF_ConstExtended flag set.
2354 for (const MachineOperand &MO : MI.operands())
2355 if (MO.getTargetFlags() & HexagonII::HMOTF_ConstExtended)
2356 return true;
2357 return false;
2358}
2359
2360bool HexagonInstrInfo::isFloat(const MachineInstr &MI) const {
2361 unsigned Opcode = MI.getOpcode();
2362 const uint64_t F = get(Opcode).TSFlags;
2363 return (F >> HexagonII::FPPos) & HexagonII::FPMask;
2364}
2365
2366// No V60 HVX VMEM with A_INDIRECT.
2367bool HexagonInstrInfo::isHVXMemWithAIndirect(const MachineInstr &I,
2368 const MachineInstr &J) const {
2369 if (!isHVXVec(MI: I))
2370 return false;
2371 if (!I.mayLoad() && !I.mayStore())
2372 return false;
2373 return J.isIndirectBranch() || isIndirectCall(MI: J) || isIndirectL4Return(MI: J);
2374}
2375
2376bool HexagonInstrInfo::isIndirectCall(const MachineInstr &MI) const {
2377 switch (MI.getOpcode()) {
2378 case Hexagon::J2_callr:
2379 case Hexagon::J2_callrf:
2380 case Hexagon::J2_callrt:
2381 case Hexagon::PS_call_nr:
2382 return true;
2383 }
2384 return false;
2385}
2386
2387bool HexagonInstrInfo::isIndirectL4Return(const MachineInstr &MI) const {
2388 switch (MI.getOpcode()) {
2389 case Hexagon::L4_return:
2390 case Hexagon::L4_return_t:
2391 case Hexagon::L4_return_f:
2392 case Hexagon::L4_return_fnew_pnt:
2393 case Hexagon::L4_return_fnew_pt:
2394 case Hexagon::L4_return_tnew_pnt:
2395 case Hexagon::L4_return_tnew_pt:
2396 return true;
2397 }
2398 return false;
2399}
2400
2401bool HexagonInstrInfo::isJumpR(const MachineInstr &MI) const {
2402 switch (MI.getOpcode()) {
2403 case Hexagon::J2_jumpr:
2404 case Hexagon::J2_jumprt:
2405 case Hexagon::J2_jumprf:
2406 case Hexagon::J2_jumprtnewpt:
2407 case Hexagon::J2_jumprfnewpt:
2408 case Hexagon::J2_jumprtnew:
2409 case Hexagon::J2_jumprfnew:
2410 return true;
2411 }
2412 return false;
2413}
2414
2415// Return true if a given MI can accommodate given offset.
2416// Use abs estimate as oppose to the exact number.
2417// TODO: This will need to be changed to use MC level
2418// definition of instruction extendable field size.
2419bool HexagonInstrInfo::isJumpWithinBranchRange(const MachineInstr &MI,
2420 unsigned offset) const {
2421 // This selection of jump instructions matches to that what
2422 // analyzeBranch can parse, plus NVJ.
2423 if (isNewValueJump(MI)) // r9:2
2424 return isInt<11>(x: offset);
2425
2426 switch (MI.getOpcode()) {
2427 // Still missing Jump to address condition on register value.
2428 default:
2429 return false;
2430 case Hexagon::J2_jump: // bits<24> dst; // r22:2
2431 case Hexagon::J2_call:
2432 case Hexagon::PS_call_nr:
2433 return isInt<24>(x: offset);
2434 case Hexagon::J2_jumpt: //bits<17> dst; // r15:2
2435 case Hexagon::J2_jumpf:
2436 case Hexagon::J2_jumptnew:
2437 case Hexagon::J2_jumptnewpt:
2438 case Hexagon::J2_jumpfnew:
2439 case Hexagon::J2_jumpfnewpt:
2440 case Hexagon::J2_callt:
2441 case Hexagon::J2_callf:
2442 return isInt<17>(x: offset);
2443 case Hexagon::J2_loop0i:
2444 case Hexagon::J2_loop0iext:
2445 case Hexagon::J2_loop0r:
2446 case Hexagon::J2_loop0rext:
2447 case Hexagon::J2_loop1i:
2448 case Hexagon::J2_loop1iext:
2449 case Hexagon::J2_loop1r:
2450 case Hexagon::J2_loop1rext:
2451 return isInt<9>(x: offset);
2452 // TODO: Add all the compound branches here. Can we do this in Relation model?
2453 case Hexagon::J4_cmpeqi_tp0_jump_nt:
2454 case Hexagon::J4_cmpeqi_tp1_jump_nt:
2455 case Hexagon::J4_cmpeqn1_tp0_jump_nt:
2456 case Hexagon::J4_cmpeqn1_tp1_jump_nt:
2457 return isInt<11>(x: offset);
2458 }
2459}
2460
2461bool HexagonInstrInfo::isLateSourceInstr(const MachineInstr &MI) const {
2462 // Instructions with iclass A_CVI_VX and attribute A_CVI_LATE uses a multiply
2463 // resource, but all operands can be received late like an ALU instruction.
2464 return getType(MI) == HexagonII::TypeCVI_VX_LATE;
2465}
2466
2467bool HexagonInstrInfo::isLoopN(const MachineInstr &MI) const {
2468 unsigned Opcode = MI.getOpcode();
2469 return Opcode == Hexagon::J2_loop0i ||
2470 Opcode == Hexagon::J2_loop0r ||
2471 Opcode == Hexagon::J2_loop0iext ||
2472 Opcode == Hexagon::J2_loop0rext ||
2473 Opcode == Hexagon::J2_loop1i ||
2474 Opcode == Hexagon::J2_loop1r ||
2475 Opcode == Hexagon::J2_loop1iext ||
2476 Opcode == Hexagon::J2_loop1rext;
2477}
2478
2479bool HexagonInstrInfo::isMemOp(const MachineInstr &MI) const {
2480 switch (MI.getOpcode()) {
2481 default: return false;
2482 case Hexagon::L4_iadd_memopw_io:
2483 case Hexagon::L4_isub_memopw_io:
2484 case Hexagon::L4_add_memopw_io:
2485 case Hexagon::L4_sub_memopw_io:
2486 case Hexagon::L4_and_memopw_io:
2487 case Hexagon::L4_or_memopw_io:
2488 case Hexagon::L4_iadd_memoph_io:
2489 case Hexagon::L4_isub_memoph_io:
2490 case Hexagon::L4_add_memoph_io:
2491 case Hexagon::L4_sub_memoph_io:
2492 case Hexagon::L4_and_memoph_io:
2493 case Hexagon::L4_or_memoph_io:
2494 case Hexagon::L4_iadd_memopb_io:
2495 case Hexagon::L4_isub_memopb_io:
2496 case Hexagon::L4_add_memopb_io:
2497 case Hexagon::L4_sub_memopb_io:
2498 case Hexagon::L4_and_memopb_io:
2499 case Hexagon::L4_or_memopb_io:
2500 case Hexagon::L4_ior_memopb_io:
2501 case Hexagon::L4_ior_memoph_io:
2502 case Hexagon::L4_ior_memopw_io:
2503 case Hexagon::L4_iand_memopb_io:
2504 case Hexagon::L4_iand_memoph_io:
2505 case Hexagon::L4_iand_memopw_io:
2506 return true;
2507 }
2508 return false;
2509}
2510
2511bool HexagonInstrInfo::isNewValue(const MachineInstr &MI) const {
2512 const uint64_t F = MI.getDesc().TSFlags;
2513 return (F >> HexagonII::NewValuePos) & HexagonII::NewValueMask;
2514}
2515
2516bool HexagonInstrInfo::isNewValue(unsigned Opcode) const {
2517 const uint64_t F = get(Opcode).TSFlags;
2518 return (F >> HexagonII::NewValuePos) & HexagonII::NewValueMask;
2519}
2520
2521bool HexagonInstrInfo::isNewValueInst(const MachineInstr &MI) const {
2522 return isNewValueJump(MI) || isNewValueStore(MI);
2523}
2524
2525bool HexagonInstrInfo::isNewValueJump(const MachineInstr &MI) const {
2526 return isNewValue(MI) && MI.isBranch();
2527}
2528
2529bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const {
2530 return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
2531}
2532
2533bool HexagonInstrInfo::isNewValueStore(const MachineInstr &MI) const {
2534 const uint64_t F = MI.getDesc().TSFlags;
2535 return (F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask;
2536}
2537
2538bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
2539 const uint64_t F = get(Opcode).TSFlags;
2540 return (F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask;
2541}
2542
2543// Returns true if a particular operand is extendable for an instruction.
2544bool HexagonInstrInfo::isOperandExtended(const MachineInstr &MI,
2545 unsigned OperandNum) const {
2546 const uint64_t F = MI.getDesc().TSFlags;
2547 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
2548 == OperandNum;
2549}
2550
2551bool HexagonInstrInfo::isPredicatedNew(const MachineInstr &MI) const {
2552 const uint64_t F = MI.getDesc().TSFlags;
2553 assert(isPredicated(MI));
2554 return (F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask;
2555}
2556
2557bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
2558 const uint64_t F = get(Opcode).TSFlags;
2559 assert(isPredicated(Opcode));
2560 return (F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask;
2561}
2562
2563bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr &MI) const {
2564 const uint64_t F = MI.getDesc().TSFlags;
2565 return !((F >> HexagonII::PredicatedFalsePos) &
2566 HexagonII::PredicatedFalseMask);
2567}
2568
2569bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
2570 const uint64_t F = get(Opcode).TSFlags;
2571 // Make sure that the instruction is predicated.
2572 assert((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
2573 return !((F >> HexagonII::PredicatedFalsePos) &
2574 HexagonII::PredicatedFalseMask);
2575}
2576
2577bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
2578 const uint64_t F = get(Opcode).TSFlags;
2579 return (F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask;
2580}
2581
2582bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const {
2583 const uint64_t F = get(Opcode).TSFlags;
2584 return (F >> HexagonII::PredicateLatePos) & HexagonII::PredicateLateMask;
2585}
2586
2587bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {
2588 const uint64_t F = get(Opcode).TSFlags;
2589 assert(get(Opcode).isBranch() &&
2590 (isPredicatedNew(Opcode) || isNewValue(Opcode)));
2591 return (F >> HexagonII::TakenPos) & HexagonII::TakenMask;
2592}
2593
2594bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr &MI) const {
2595 return MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
2596 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
2597 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
2598 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
2599}
2600
2601bool HexagonInstrInfo::isSignExtendingLoad(const MachineInstr &MI) const {
2602 switch (MI.getOpcode()) {
2603 // Byte
2604 case Hexagon::L2_loadrb_io:
2605 case Hexagon::L4_loadrb_ur:
2606 case Hexagon::L4_loadrb_ap:
2607 case Hexagon::L2_loadrb_pr:
2608 case Hexagon::L2_loadrb_pbr:
2609 case Hexagon::L2_loadrb_pi:
2610 case Hexagon::L2_loadrb_pci:
2611 case Hexagon::L2_loadrb_pcr:
2612 case Hexagon::L2_loadbsw2_io:
2613 case Hexagon::L4_loadbsw2_ur:
2614 case Hexagon::L4_loadbsw2_ap:
2615 case Hexagon::L2_loadbsw2_pr:
2616 case Hexagon::L2_loadbsw2_pbr:
2617 case Hexagon::L2_loadbsw2_pi:
2618 case Hexagon::L2_loadbsw2_pci:
2619 case Hexagon::L2_loadbsw2_pcr:
2620 case Hexagon::L2_loadbsw4_io:
2621 case Hexagon::L4_loadbsw4_ur:
2622 case Hexagon::L4_loadbsw4_ap:
2623 case Hexagon::L2_loadbsw4_pr:
2624 case Hexagon::L2_loadbsw4_pbr:
2625 case Hexagon::L2_loadbsw4_pi:
2626 case Hexagon::L2_loadbsw4_pci:
2627 case Hexagon::L2_loadbsw4_pcr:
2628 case Hexagon::L4_loadrb_rr:
2629 case Hexagon::L2_ploadrbt_io:
2630 case Hexagon::L2_ploadrbt_pi:
2631 case Hexagon::L2_ploadrbf_io:
2632 case Hexagon::L2_ploadrbf_pi:
2633 case Hexagon::L2_ploadrbtnew_io:
2634 case Hexagon::L2_ploadrbfnew_io:
2635 case Hexagon::L4_ploadrbt_rr:
2636 case Hexagon::L4_ploadrbf_rr:
2637 case Hexagon::L4_ploadrbtnew_rr:
2638 case Hexagon::L4_ploadrbfnew_rr:
2639 case Hexagon::L2_ploadrbtnew_pi:
2640 case Hexagon::L2_ploadrbfnew_pi:
2641 case Hexagon::L4_ploadrbt_abs:
2642 case Hexagon::L4_ploadrbf_abs:
2643 case Hexagon::L4_ploadrbtnew_abs:
2644 case Hexagon::L4_ploadrbfnew_abs:
2645 case Hexagon::L2_loadrbgp:
2646 // Half
2647 case Hexagon::L2_loadrh_io:
2648 case Hexagon::L4_loadrh_ur:
2649 case Hexagon::L4_loadrh_ap:
2650 case Hexagon::L2_loadrh_pr:
2651 case Hexagon::L2_loadrh_pbr:
2652 case Hexagon::L2_loadrh_pi:
2653 case Hexagon::L2_loadrh_pci:
2654 case Hexagon::L2_loadrh_pcr:
2655 case Hexagon::L4_loadrh_rr:
2656 case Hexagon::L2_ploadrht_io:
2657 case Hexagon::L2_ploadrht_pi:
2658 case Hexagon::L2_ploadrhf_io:
2659 case Hexagon::L2_ploadrhf_pi:
2660 case Hexagon::L2_ploadrhtnew_io:
2661 case Hexagon::L2_ploadrhfnew_io:
2662 case Hexagon::L4_ploadrht_rr:
2663 case Hexagon::L4_ploadrhf_rr:
2664 case Hexagon::L4_ploadrhtnew_rr:
2665 case Hexagon::L4_ploadrhfnew_rr:
2666 case Hexagon::L2_ploadrhtnew_pi:
2667 case Hexagon::L2_ploadrhfnew_pi:
2668 case Hexagon::L4_ploadrht_abs:
2669 case Hexagon::L4_ploadrhf_abs:
2670 case Hexagon::L4_ploadrhtnew_abs:
2671 case Hexagon::L4_ploadrhfnew_abs:
2672 case Hexagon::L2_loadrhgp:
2673 return true;
2674 default:
2675 return false;
2676 }
2677}
2678
2679bool HexagonInstrInfo::isSolo(const MachineInstr &MI) const {
2680 const uint64_t F = MI.getDesc().TSFlags;
2681 return (F >> HexagonII::SoloPos) & HexagonII::SoloMask;
2682}
2683
2684bool HexagonInstrInfo::isSpillPredRegOp(const MachineInstr &MI) const {
2685 switch (MI.getOpcode()) {
2686 case Hexagon::STriw_pred:
2687 case Hexagon::LDriw_pred:
2688 return true;
2689 default:
2690 return false;
2691 }
2692}
2693
2694bool HexagonInstrInfo::isTailCall(const MachineInstr &MI) const {
2695 if (!MI.isBranch())
2696 return false;
2697
2698 for (auto &Op : MI.operands())
2699 if (Op.isGlobal() || Op.isSymbol())
2700 return true;
2701 return false;
2702}
2703
2704// Returns true when SU has a timing class TC1.
2705bool HexagonInstrInfo::isTC1(const MachineInstr &MI) const {
2706 unsigned SchedClass = MI.getDesc().getSchedClass();
2707 return is_TC1(SchedClass);
2708}
2709
2710bool HexagonInstrInfo::isTC2(const MachineInstr &MI) const {
2711 unsigned SchedClass = MI.getDesc().getSchedClass();
2712 return is_TC2(SchedClass);
2713}
2714
2715bool HexagonInstrInfo::isTC2Early(const MachineInstr &MI) const {
2716 unsigned SchedClass = MI.getDesc().getSchedClass();
2717 return is_TC2early(SchedClass);
2718}
2719
2720bool HexagonInstrInfo::isTC4x(const MachineInstr &MI) const {
2721 unsigned SchedClass = MI.getDesc().getSchedClass();
2722 return is_TC4x(SchedClass);
2723}
2724
2725// Schedule this ASAP.
2726bool HexagonInstrInfo::isToBeScheduledASAP(const MachineInstr &MI1,
2727 const MachineInstr &MI2) const {
2728 if (mayBeCurLoad(MI: MI1)) {
2729 // if (result of SU is used in Next) return true;
2730 Register DstReg = MI1.getOperand(i: 0).getReg();
2731 int N = MI2.getNumOperands();
2732 for (int I = 0; I < N; I++)
2733 if (MI2.getOperand(i: I).isReg() && DstReg == MI2.getOperand(i: I).getReg())
2734 return true;
2735 }
2736 if (mayBeNewStore(MI: MI2))
2737 if (MI2.getOpcode() == Hexagon::V6_vS32b_pi)
2738 if (MI1.getOperand(i: 0).isReg() && MI2.getOperand(i: 3).isReg() &&
2739 MI1.getOperand(i: 0).getReg() == MI2.getOperand(i: 3).getReg())
2740 return true;
2741 return false;
2742}
2743
2744bool HexagonInstrInfo::isHVXVec(const MachineInstr &MI) const {
2745 const uint64_t V = getType(MI);
2746 return HexagonII::TypeCVI_FIRST <= V && V <= HexagonII::TypeCVI_LAST;
2747}
2748
2749// Check if the Offset is a valid auto-inc imm by Load/Store Type.
2750bool HexagonInstrInfo::isValidAutoIncImm(const EVT VT, int Offset) const {
2751 int Size = VT.getSizeInBits() / 8;
2752 if (Offset % Size != 0)
2753 return false;
2754 int Count = Offset / Size;
2755
2756 switch (VT.getSimpleVT().SimpleTy) {
2757 // For scalars the auto-inc is s4
2758 case MVT::i8:
2759 case MVT::i16:
2760 case MVT::i32:
2761 case MVT::i64:
2762 case MVT::f32:
2763 case MVT::f64:
2764 case MVT::v2i16:
2765 case MVT::v2i32:
2766 case MVT::v4i8:
2767 case MVT::v4i16:
2768 case MVT::v8i8:
2769 return isInt<4>(x: Count);
2770 // For HVX vectors the auto-inc is s3
2771 case MVT::v64i8:
2772 case MVT::v32i16:
2773 case MVT::v16i32:
2774 case MVT::v8i64:
2775 case MVT::v128i8:
2776 case MVT::v64i16:
2777 case MVT::v32i32:
2778 case MVT::v16i64:
2779 return isInt<3>(x: Count);
2780 default:
2781 break;
2782 }
2783
2784 llvm_unreachable("Not an valid type!");
2785}
2786
2787bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
2788 bool Extend) const {
2789 // This function is to check whether the "Offset" is in the correct range of
2790 // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
2791 // inserted to calculate the final address. Due to this reason, the function
2792 // assumes that the "Offset" has correct alignment.
2793 // We used to assert if the offset was not properly aligned, however,
2794 // there are cases where a misaligned pointer recast can cause this
2795 // problem, and we need to allow for it. The front end warns of such
2796 // misaligns with respect to load size.
2797 switch (Opcode) {
2798 case Hexagon::PS_vstorerq_ai:
2799 case Hexagon::PS_vstorerv_ai:
2800 case Hexagon::PS_vstorerw_ai:
2801 case Hexagon::PS_vstorerw_nt_ai:
2802 case Hexagon::PS_vloadrq_ai:
2803 case Hexagon::PS_vloadrv_ai:
2804 case Hexagon::PS_vloadrw_ai:
2805 case Hexagon::PS_vloadrw_nt_ai:
2806 case Hexagon::V6_vL32b_ai:
2807 case Hexagon::V6_vS32b_ai:
2808 case Hexagon::V6_vS32b_pred_ai:
2809 case Hexagon::V6_vS32b_npred_ai:
2810 case Hexagon::V6_vS32b_qpred_ai:
2811 case Hexagon::V6_vS32b_nqpred_ai:
2812 case Hexagon::V6_vS32b_new_ai:
2813 case Hexagon::V6_vS32b_new_pred_ai:
2814 case Hexagon::V6_vS32b_new_npred_ai:
2815 case Hexagon::V6_vS32b_nt_pred_ai:
2816 case Hexagon::V6_vS32b_nt_npred_ai:
2817 case Hexagon::V6_vS32b_nt_new_ai:
2818 case Hexagon::V6_vS32b_nt_new_pred_ai:
2819 case Hexagon::V6_vS32b_nt_new_npred_ai:
2820 case Hexagon::V6_vS32b_nt_qpred_ai:
2821 case Hexagon::V6_vS32b_nt_nqpred_ai:
2822 case Hexagon::V6_vL32b_nt_ai:
2823 case Hexagon::V6_vS32b_nt_ai:
2824 case Hexagon::V6_vL32Ub_ai:
2825 case Hexagon::V6_vS32Ub_ai:
2826 case Hexagon::V6_vL32b_cur_ai:
2827 case Hexagon::V6_vL32b_tmp_ai:
2828 case Hexagon::V6_vL32b_pred_ai:
2829 case Hexagon::V6_vL32b_npred_ai:
2830 case Hexagon::V6_vL32b_cur_pred_ai:
2831 case Hexagon::V6_vL32b_cur_npred_ai:
2832 case Hexagon::V6_vL32b_tmp_pred_ai:
2833 case Hexagon::V6_vL32b_tmp_npred_ai:
2834 case Hexagon::V6_vL32b_nt_cur_ai:
2835 case Hexagon::V6_vL32b_nt_tmp_ai:
2836 case Hexagon::V6_vL32b_nt_pred_ai:
2837 case Hexagon::V6_vL32b_nt_npred_ai:
2838 case Hexagon::V6_vL32b_nt_cur_pred_ai:
2839 case Hexagon::V6_vL32b_nt_cur_npred_ai:
2840 case Hexagon::V6_vL32b_nt_tmp_pred_ai:
2841 case Hexagon::V6_vL32b_nt_tmp_npred_ai:
2842 case Hexagon::V6_vS32Ub_pred_ai:
2843 case Hexagon::V6_vS32Ub_npred_ai:
2844 case Hexagon::V6_vgathermh_pseudo:
2845 case Hexagon::V6_vgather_vscatter_mh_pseudo:
2846 case Hexagon::V6_vgathermw_pseudo:
2847 case Hexagon::V6_vgathermhw_pseudo:
2848 case Hexagon::V6_vgathermhq_pseudo:
2849 case Hexagon::V6_vgathermwq_pseudo:
2850 case Hexagon::V6_vgathermhwq_pseudo: {
2851 unsigned VectorSize = RegInfo.getSpillSize(RC: Hexagon::HvxVRRegClass);
2852 assert(isPowerOf2_32(VectorSize));
2853 if (Offset & (VectorSize-1))
2854 return false;
2855 return isInt<4>(x: Offset >> Log2_32(Value: VectorSize));
2856 }
2857
2858 case Hexagon::J2_loop0i:
2859 case Hexagon::J2_loop1i:
2860 return isUInt<10>(x: Offset);
2861
2862 case Hexagon::S4_storeirb_io:
2863 case Hexagon::S4_storeirbt_io:
2864 case Hexagon::S4_storeirbf_io:
2865 return isUInt<6>(x: Offset);
2866
2867 case Hexagon::S4_storeirh_io:
2868 case Hexagon::S4_storeirht_io:
2869 case Hexagon::S4_storeirhf_io:
2870 return isShiftedUInt<6,1>(x: Offset);
2871
2872 case Hexagon::S4_storeiri_io:
2873 case Hexagon::S4_storeirit_io:
2874 case Hexagon::S4_storeirif_io:
2875 return isShiftedUInt<6,2>(x: Offset);
2876 // Handle these two compare instructions that are not extendable.
2877 case Hexagon::A4_cmpbeqi:
2878 return isUInt<8>(x: Offset);
2879 case Hexagon::A4_cmpbgti:
2880 return isInt<8>(x: Offset);
2881 }
2882
2883 if (Extend)
2884 return true;
2885
2886 switch (Opcode) {
2887 case Hexagon::L2_loadri_io:
2888 case Hexagon::S2_storeri_io:
2889 return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
2890 (Offset <= Hexagon_MEMW_OFFSET_MAX);
2891
2892 case Hexagon::L2_loadrd_io:
2893 case Hexagon::S2_storerd_io:
2894 return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
2895 (Offset <= Hexagon_MEMD_OFFSET_MAX);
2896
2897 case Hexagon::L2_loadrh_io:
2898 case Hexagon::L2_loadruh_io:
2899 case Hexagon::S2_storerh_io:
2900 case Hexagon::S2_storerf_io:
2901 return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2902 (Offset <= Hexagon_MEMH_OFFSET_MAX);
2903
2904 case Hexagon::L2_loadrb_io:
2905 case Hexagon::L2_loadrub_io:
2906 case Hexagon::S2_storerb_io:
2907 return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2908 (Offset <= Hexagon_MEMB_OFFSET_MAX);
2909
2910 case Hexagon::A2_addi:
2911 return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2912 (Offset <= Hexagon_ADDI_OFFSET_MAX);
2913
2914 case Hexagon::L4_iadd_memopw_io:
2915 case Hexagon::L4_isub_memopw_io:
2916 case Hexagon::L4_add_memopw_io:
2917 case Hexagon::L4_sub_memopw_io:
2918 case Hexagon::L4_iand_memopw_io:
2919 case Hexagon::L4_ior_memopw_io:
2920 case Hexagon::L4_and_memopw_io:
2921 case Hexagon::L4_or_memopw_io:
2922 return (0 <= Offset && Offset <= 255);
2923
2924 case Hexagon::L4_iadd_memoph_io:
2925 case Hexagon::L4_isub_memoph_io:
2926 case Hexagon::L4_add_memoph_io:
2927 case Hexagon::L4_sub_memoph_io:
2928 case Hexagon::L4_iand_memoph_io:
2929 case Hexagon::L4_ior_memoph_io:
2930 case Hexagon::L4_and_memoph_io:
2931 case Hexagon::L4_or_memoph_io:
2932 return (0 <= Offset && Offset <= 127);
2933
2934 case Hexagon::L4_iadd_memopb_io:
2935 case Hexagon::L4_isub_memopb_io:
2936 case Hexagon::L4_add_memopb_io:
2937 case Hexagon::L4_sub_memopb_io:
2938 case Hexagon::L4_iand_memopb_io:
2939 case Hexagon::L4_ior_memopb_io:
2940 case Hexagon::L4_and_memopb_io:
2941 case Hexagon::L4_or_memopb_io:
2942 return (0 <= Offset && Offset <= 63);
2943
2944 // LDriw_xxx and STriw_xxx are pseudo operations, so it has to take offset of
2945 // any size. Later pass knows how to handle it.
2946 case Hexagon::STriw_pred:
2947 case Hexagon::LDriw_pred:
2948 case Hexagon::STriw_ctr:
2949 case Hexagon::LDriw_ctr:
2950 return true;
2951
2952 case Hexagon::PS_fi:
2953 case Hexagon::PS_fia:
2954 case Hexagon::INLINEASM:
2955 return true;
2956
2957 case Hexagon::L2_ploadrbt_io:
2958 case Hexagon::L2_ploadrbf_io:
2959 case Hexagon::L2_ploadrubt_io:
2960 case Hexagon::L2_ploadrubf_io:
2961 case Hexagon::S2_pstorerbt_io:
2962 case Hexagon::S2_pstorerbf_io:
2963 return isUInt<6>(x: Offset);
2964
2965 case Hexagon::L2_ploadrht_io:
2966 case Hexagon::L2_ploadrhf_io:
2967 case Hexagon::L2_ploadruht_io:
2968 case Hexagon::L2_ploadruhf_io:
2969 case Hexagon::S2_pstorerht_io:
2970 case Hexagon::S2_pstorerhf_io:
2971 case Hexagon::S2_pstorerft_io:
2972 case Hexagon::S2_pstorerff_io:
2973 return isShiftedUInt<6,1>(x: Offset);
2974
2975 case Hexagon::L2_ploadrit_io:
2976 case Hexagon::L2_ploadrif_io:
2977 case Hexagon::S2_pstorerit_io:
2978 case Hexagon::S2_pstorerif_io:
2979 return isShiftedUInt<6,2>(x: Offset);
2980
2981 case Hexagon::L2_ploadrdt_io:
2982 case Hexagon::L2_ploadrdf_io:
2983 case Hexagon::S2_pstorerdt_io:
2984 case Hexagon::S2_pstorerdf_io:
2985 return isShiftedUInt<6,3>(x: Offset);
2986
2987 case Hexagon::L2_loadbsw2_io:
2988 case Hexagon::L2_loadbzw2_io:
2989 return isShiftedInt<11,1>(x: Offset);
2990
2991 case Hexagon::L2_loadbsw4_io:
2992 case Hexagon::L2_loadbzw4_io:
2993 return isShiftedInt<11,2>(x: Offset);
2994 } // switch
2995
2996 dbgs() << "Failed Opcode is : " << Opcode << " (" << getName(Opcode)
2997 << ")\n";
2998 llvm_unreachable("No offset range is defined for this opcode. "
2999 "Please define it in the above switch statement!");
3000}
3001
3002bool HexagonInstrInfo::isVecAcc(const MachineInstr &MI) const {
3003 return isHVXVec(MI) && isAccumulator(MI);
3004}
3005
3006bool HexagonInstrInfo::isVecALU(const MachineInstr &MI) const {
3007 const uint64_t F = get(Opcode: MI.getOpcode()).TSFlags;
3008 const uint64_t V = ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
3009 return
3010 V == HexagonII::TypeCVI_VA ||
3011 V == HexagonII::TypeCVI_VA_DV;
3012}
3013
3014bool HexagonInstrInfo::isVecUsableNextPacket(const MachineInstr &ProdMI,
3015 const MachineInstr &ConsMI) const {
3016 if (EnableACCForwarding && isVecAcc(MI: ProdMI) && isVecAcc(MI: ConsMI))
3017 return true;
3018
3019 if (EnableALUForwarding && (isVecALU(MI: ConsMI) || isLateSourceInstr(MI: ConsMI)))
3020 return true;
3021
3022 if (mayBeNewStore(MI: ConsMI))
3023 return true;
3024
3025 return false;
3026}
3027
3028bool HexagonInstrInfo::isZeroExtendingLoad(const MachineInstr &MI) const {
3029 switch (MI.getOpcode()) {
3030 // Byte
3031 case Hexagon::L2_loadrub_io:
3032 case Hexagon::L4_loadrub_ur:
3033 case Hexagon::L4_loadrub_ap:
3034 case Hexagon::L2_loadrub_pr:
3035 case Hexagon::L2_loadrub_pbr:
3036 case Hexagon::L2_loadrub_pi:
3037 case Hexagon::L2_loadrub_pci:
3038 case Hexagon::L2_loadrub_pcr:
3039 case Hexagon::L2_loadbzw2_io:
3040 case Hexagon::L4_loadbzw2_ur:
3041 case Hexagon::L4_loadbzw2_ap:
3042 case Hexagon::L2_loadbzw2_pr:
3043 case Hexagon::L2_loadbzw2_pbr:
3044 case Hexagon::L2_loadbzw2_pi:
3045 case Hexagon::L2_loadbzw2_pci:
3046 case Hexagon::L2_loadbzw2_pcr:
3047 case Hexagon::L2_loadbzw4_io:
3048 case Hexagon::L4_loadbzw4_ur:
3049 case Hexagon::L4_loadbzw4_ap:
3050 case Hexagon::L2_loadbzw4_pr:
3051 case Hexagon::L2_loadbzw4_pbr:
3052 case Hexagon::L2_loadbzw4_pi:
3053 case Hexagon::L2_loadbzw4_pci:
3054 case Hexagon::L2_loadbzw4_pcr:
3055 case Hexagon::L4_loadrub_rr:
3056 case Hexagon::L2_ploadrubt_io:
3057 case Hexagon::L2_ploadrubt_pi:
3058 case Hexagon::L2_ploadrubf_io:
3059 case Hexagon::L2_ploadrubf_pi:
3060 case Hexagon::L2_ploadrubtnew_io:
3061 case Hexagon::L2_ploadrubfnew_io:
3062 case Hexagon::L4_ploadrubt_rr:
3063 case Hexagon::L4_ploadrubf_rr:
3064 case Hexagon::L4_ploadrubtnew_rr:
3065 case Hexagon::L4_ploadrubfnew_rr:
3066 case Hexagon::L2_ploadrubtnew_pi:
3067 case Hexagon::L2_ploadrubfnew_pi:
3068 case Hexagon::L4_ploadrubt_abs:
3069 case Hexagon::L4_ploadrubf_abs:
3070 case Hexagon::L4_ploadrubtnew_abs:
3071 case Hexagon::L4_ploadrubfnew_abs:
3072 case Hexagon::L2_loadrubgp:
3073 // Half
3074 case Hexagon::L2_loadruh_io:
3075 case Hexagon::L4_loadruh_ur:
3076 case Hexagon::L4_loadruh_ap:
3077 case Hexagon::L2_loadruh_pr:
3078 case Hexagon::L2_loadruh_pbr:
3079 case Hexagon::L2_loadruh_pi:
3080 case Hexagon::L2_loadruh_pci:
3081 case Hexagon::L2_loadruh_pcr:
3082 case Hexagon::L4_loadruh_rr:
3083 case Hexagon::L2_ploadruht_io:
3084 case Hexagon::L2_ploadruht_pi:
3085 case Hexagon::L2_ploadruhf_io:
3086 case Hexagon::L2_ploadruhf_pi:
3087 case Hexagon::L2_ploadruhtnew_io:
3088 case Hexagon::L2_ploadruhfnew_io:
3089 case Hexagon::L4_ploadruht_rr:
3090 case Hexagon::L4_ploadruhf_rr:
3091 case Hexagon::L4_ploadruhtnew_rr:
3092 case Hexagon::L4_ploadruhfnew_rr:
3093 case Hexagon::L2_ploadruhtnew_pi:
3094 case Hexagon::L2_ploadruhfnew_pi:
3095 case Hexagon::L4_ploadruht_abs:
3096 case Hexagon::L4_ploadruhf_abs:
3097 case Hexagon::L4_ploadruhtnew_abs:
3098 case Hexagon::L4_ploadruhfnew_abs:
3099 case Hexagon::L2_loadruhgp:
3100 return true;
3101 default:
3102 return false;
3103 }
3104}
3105
3106// Add latency to instruction.
3107bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr &MI1,
3108 const MachineInstr &MI2) const {
3109 if (isHVXVec(MI: MI1) && isHVXVec(MI: MI2))
3110 if (!isVecUsableNextPacket(ProdMI: MI1, ConsMI: MI2))
3111 return true;
3112 return false;
3113}
3114
3115/// Get the base register and byte offset of a load/store instr.
3116bool HexagonInstrInfo::getMemOperandsWithOffsetWidth(
3117 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps,
3118 int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width) const {
3119 OffsetIsScalable = false;
3120 const MachineOperand *BaseOp = getBaseAndOffset(MI: LdSt, Offset, AccessSize&: Width);
3121 if (!BaseOp || !BaseOp->isReg())
3122 return false;
3123 BaseOps.push_back(Elt: BaseOp);
3124 return true;
3125}
3126
3127/// Can these instructions execute at the same time in a bundle.
3128bool HexagonInstrInfo::canExecuteInBundle(const MachineInstr &First,
3129 const MachineInstr &Second) const {
3130 if (Second.mayStore() && First.getOpcode() == Hexagon::S2_allocframe) {
3131 const MachineOperand &Op = Second.getOperand(i: 0);
3132 if (Op.isReg() && Op.isUse() && Op.getReg() == Hexagon::R29)
3133 return true;
3134 }
3135 if (DisableNVSchedule)
3136 return false;
3137 if (mayBeNewStore(MI: Second)) {
3138 // Make sure the definition of the first instruction is the value being
3139 // stored.
3140 const MachineOperand &Stored =
3141 Second.getOperand(i: Second.getNumOperands() - 1);
3142 if (!Stored.isReg())
3143 return false;
3144 for (unsigned i = 0, e = First.getNumOperands(); i < e; ++i) {
3145 const MachineOperand &Op = First.getOperand(i);
3146 if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
3147 return true;
3148 }
3149 }
3150 return false;
3151}
3152
3153bool HexagonInstrInfo::doesNotReturn(const MachineInstr &CallMI) const {
3154 unsigned Opc = CallMI.getOpcode();
3155 return Opc == Hexagon::PS_call_nr || Opc == Hexagon::PS_callr_nr;
3156}
3157
3158bool HexagonInstrInfo::hasEHLabel(const MachineBasicBlock *B) const {
3159 for (auto &I : *B)
3160 if (I.isEHLabel())
3161 return true;
3162 return false;
3163}
3164
3165// Returns true if an instruction can be converted into a non-extended
3166// equivalent instruction.
3167bool HexagonInstrInfo::hasNonExtEquivalent(const MachineInstr &MI) const {
3168 short NonExtOpcode;
3169 // Check if the instruction has a register form that uses register in place
3170 // of the extended operand, if so return that as the non-extended form.
3171 if (Hexagon::getRegForm(Opcode: MI.getOpcode()) >= 0)
3172 return true;
3173
3174 if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
3175 // Check addressing mode and retrieve non-ext equivalent instruction.
3176
3177 switch (getAddrMode(MI)) {
3178 case HexagonII::Absolute:
3179 // Load/store with absolute addressing mode can be converted into
3180 // base+offset mode.
3181 NonExtOpcode = Hexagon::changeAddrMode_abs_io(Opcode: MI.getOpcode());
3182 break;
3183 case HexagonII::BaseImmOffset:
3184 // Load/store with base+offset addressing mode can be converted into
3185 // base+register offset addressing mode. However left shift operand should
3186 // be set to 0.
3187 NonExtOpcode = Hexagon::changeAddrMode_io_rr(Opcode: MI.getOpcode());
3188 break;
3189 case HexagonII::BaseLongOffset:
3190 NonExtOpcode = Hexagon::changeAddrMode_ur_rr(Opcode: MI.getOpcode());
3191 break;
3192 default:
3193 return false;
3194 }
3195 if (NonExtOpcode < 0)
3196 return false;
3197 return true;
3198 }
3199 return false;
3200}
3201
3202bool HexagonInstrInfo::hasPseudoInstrPair(const MachineInstr &MI) const {
3203 return Hexagon::getRealHWInstr(Opcode: MI.getOpcode(),
3204 inInstrType: Hexagon::InstrType_Pseudo) >= 0;
3205}
3206
3207bool HexagonInstrInfo::hasUncondBranch(const MachineBasicBlock *B)
3208 const {
3209 MachineBasicBlock::const_iterator I = B->getFirstTerminator(), E = B->end();
3210 while (I != E) {
3211 if (I->isBarrier())
3212 return true;
3213 ++I;
3214 }
3215 return false;
3216}
3217
3218// Returns true, if a LD insn can be promoted to a cur load.
3219bool HexagonInstrInfo::mayBeCurLoad(const MachineInstr &MI) const {
3220 const uint64_t F = MI.getDesc().TSFlags;
3221 return ((F >> HexagonII::mayCVLoadPos) & HexagonII::mayCVLoadMask) &&
3222 Subtarget.hasV60Ops();
3223}
3224
3225// Returns true, if a ST insn can be promoted to a new-value store.
3226bool HexagonInstrInfo::mayBeNewStore(const MachineInstr &MI) const {
3227 if (MI.mayStore() && !Subtarget.useNewValueStores())
3228 return false;
3229
3230 const uint64_t F = MI.getDesc().TSFlags;
3231 return (F >> HexagonII::mayNVStorePos) & HexagonII::mayNVStoreMask;
3232}
3233
3234bool HexagonInstrInfo::producesStall(const MachineInstr &ProdMI,
3235 const MachineInstr &ConsMI) const {
3236 // There is no stall when ProdMI is not a V60 vector.
3237 if (!isHVXVec(MI: ProdMI))
3238 return false;
3239
3240 // There is no stall when ProdMI and ConsMI are not dependent.
3241 if (!isDependent(ProdMI, ConsMI))
3242 return false;
3243
3244 // When Forward Scheduling is enabled, there is no stall if ProdMI and ConsMI
3245 // are scheduled in consecutive packets.
3246 if (isVecUsableNextPacket(ProdMI, ConsMI))
3247 return false;
3248
3249 return true;
3250}
3251
3252bool HexagonInstrInfo::producesStall(const MachineInstr &MI,
3253 MachineBasicBlock::const_instr_iterator BII) const {
3254 // There is no stall when I is not a V60 vector.
3255 if (!isHVXVec(MI))
3256 return false;
3257
3258 MachineBasicBlock::const_instr_iterator MII = BII;
3259 MachineBasicBlock::const_instr_iterator MIE = MII->getParent()->instr_end();
3260
3261 if (!MII->isBundle())
3262 return producesStall(ProdMI: *MII, ConsMI: MI);
3263
3264 for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
3265 const MachineInstr &J = *MII;
3266 if (producesStall(ProdMI: J, ConsMI: MI))
3267 return true;
3268 }
3269 return false;
3270}
3271
3272bool HexagonInstrInfo::predCanBeUsedAsDotNew(const MachineInstr &MI,
3273 Register PredReg) const {
3274 for (const MachineOperand &MO : MI.operands()) {
3275 // Predicate register must be explicitly defined.
3276 if (MO.isRegMask() && MO.clobbersPhysReg(PhysReg: PredReg))
3277 return false;
3278 if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
3279 return false;
3280 }
3281
3282 // Instruction that produce late predicate cannot be used as sources of
3283 // dot-new.
3284 switch (MI.getOpcode()) {
3285 case Hexagon::A4_addp_c:
3286 case Hexagon::A4_subp_c:
3287 case Hexagon::A4_tlbmatch:
3288 case Hexagon::A5_ACS:
3289 case Hexagon::F2_sfinvsqrta:
3290 case Hexagon::F2_sfrecipa:
3291 case Hexagon::J2_endloop0:
3292 case Hexagon::J2_endloop01:
3293 case Hexagon::J2_ploop1si:
3294 case Hexagon::J2_ploop1sr:
3295 case Hexagon::J2_ploop2si:
3296 case Hexagon::J2_ploop2sr:
3297 case Hexagon::J2_ploop3si:
3298 case Hexagon::J2_ploop3sr:
3299 case Hexagon::S2_cabacdecbin:
3300 case Hexagon::S2_storew_locked:
3301 case Hexagon::S4_stored_locked:
3302 return false;
3303 }
3304 return true;
3305}
3306
3307bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {
3308 return Opcode == Hexagon::J2_jumpt ||
3309 Opcode == Hexagon::J2_jumptpt ||
3310 Opcode == Hexagon::J2_jumpf ||
3311 Opcode == Hexagon::J2_jumpfpt ||
3312 Opcode == Hexagon::J2_jumptnew ||
3313 Opcode == Hexagon::J2_jumpfnew ||
3314 Opcode == Hexagon::J2_jumptnewpt ||
3315 Opcode == Hexagon::J2_jumpfnewpt;
3316}
3317
3318bool HexagonInstrInfo::predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const {
3319 if (Cond.empty() || !isPredicated(Opcode: Cond[0].getImm()))
3320 return false;
3321 return !isPredicatedTrue(Opcode: Cond[0].getImm());
3322}
3323
3324unsigned HexagonInstrInfo::getAddrMode(const MachineInstr &MI) const {
3325 const uint64_t F = MI.getDesc().TSFlags;
3326 return (F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask;
3327}
3328
3329// Returns the base register in a memory access (load/store). The offset is
3330// returned in Offset and the access size is returned in AccessSize.
3331// If the base operand has a subregister or the offset field does not contain
3332// an immediate value, return nullptr.
3333MachineOperand *
3334HexagonInstrInfo::getBaseAndOffset(const MachineInstr &MI, int64_t &Offset,
3335 LocationSize &AccessSize) const {
3336 // Return if it is not a base+offset type instruction or a MemOp.
3337 if (getAddrMode(MI) != HexagonII::BaseImmOffset &&
3338 getAddrMode(MI) != HexagonII::BaseLongOffset && !isMemOp(MI) &&
3339 !isPostIncrement(MI))
3340 return nullptr;
3341
3342 AccessSize = LocationSize::precise(Value: getMemAccessSize(MI));
3343
3344 unsigned BasePos = 0, OffsetPos = 0;
3345 if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
3346 return nullptr;
3347
3348 // Post increment updates its EA after the mem access,
3349 // so we need to treat its offset as zero.
3350 if (isPostIncrement(MI)) {
3351 Offset = 0;
3352 } else {
3353 const MachineOperand &OffsetOp = MI.getOperand(i: OffsetPos);
3354 if (!OffsetOp.isImm())
3355 return nullptr;
3356 Offset = OffsetOp.getImm();
3357 }
3358
3359 const MachineOperand &BaseOp = MI.getOperand(i: BasePos);
3360 if (BaseOp.getSubReg() != 0)
3361 return nullptr;
3362 return &const_cast<MachineOperand&>(BaseOp);
3363}
3364
3365/// Return the position of the base and offset operands for this instruction.
3366bool HexagonInstrInfo::getBaseAndOffsetPosition(const MachineInstr &MI,
3367 unsigned &BasePos, unsigned &OffsetPos) const {
3368 if (!isAddrModeWithOffset(MI) && !isPostIncrement(MI))
3369 return false;
3370
3371 // Deal with memops first.
3372 if (isMemOp(MI)) {
3373 BasePos = 0;
3374 OffsetPos = 1;
3375 } else if (MI.mayStore()) {
3376 BasePos = 0;
3377 OffsetPos = 1;
3378 } else if (MI.mayLoad()) {
3379 BasePos = 1;
3380 OffsetPos = 2;
3381 } else
3382 return false;
3383
3384 if (isPredicated(MI)) {
3385 BasePos++;
3386 OffsetPos++;
3387 }
3388 if (isPostIncrement(MI)) {
3389 BasePos++;
3390 OffsetPos++;
3391 }
3392
3393 if (!MI.getOperand(i: BasePos).isReg() || !MI.getOperand(i: OffsetPos).isImm())
3394 return false;
3395
3396 return true;
3397}
3398
3399// Inserts branching instructions in reverse order of their occurrence.
3400// e.g. jump_t t1 (i1)
3401// jump t2 (i2)
3402// Jumpers = {i2, i1}
3403SmallVector<MachineInstr*, 2> HexagonInstrInfo::getBranchingInstrs(
3404 MachineBasicBlock& MBB) const {
3405 SmallVector<MachineInstr*, 2> Jumpers;
3406 // If the block has no terminators, it just falls into the block after it.
3407 MachineBasicBlock::instr_iterator I = MBB.instr_end();
3408 if (I == MBB.instr_begin())
3409 return Jumpers;
3410
3411 // A basic block may looks like this:
3412 //
3413 // [ insn
3414 // EH_LABEL
3415 // insn
3416 // insn
3417 // insn
3418 // EH_LABEL
3419 // insn ]
3420 //
3421 // It has two succs but does not have a terminator
3422 // Don't know how to handle it.
3423 do {
3424 --I;
3425 if (I->isEHLabel())
3426 return Jumpers;
3427 } while (I != MBB.instr_begin());
3428
3429 I = MBB.instr_end();
3430 --I;
3431
3432 while (I->isDebugInstr()) {
3433 if (I == MBB.instr_begin())
3434 return Jumpers;
3435 --I;
3436 }
3437 if (!isUnpredicatedTerminator(MI: *I))
3438 return Jumpers;
3439
3440 // Get the last instruction in the block.
3441 MachineInstr *LastInst = &*I;
3442 Jumpers.push_back(Elt: LastInst);
3443 MachineInstr *SecondLastInst = nullptr;
3444 // Find one more terminator if present.
3445 do {
3446 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(MI: *I)) {
3447 if (!SecondLastInst) {
3448 SecondLastInst = &*I;
3449 Jumpers.push_back(Elt: SecondLastInst);
3450 } else // This is a third branch.
3451 return Jumpers;
3452 }
3453 if (I == MBB.instr_begin())
3454 break;
3455 --I;
3456 } while (true);
3457 return Jumpers;
3458}
3459
3460// Returns Operand Index for the constant extended instruction.
3461unsigned HexagonInstrInfo::getCExtOpNum(const MachineInstr &MI) const {
3462 const uint64_t F = MI.getDesc().TSFlags;
3463 return (F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask;
3464}
3465
3466// See if instruction could potentially be a duplex candidate.
3467// If so, return its group. Zero otherwise.
3468HexagonII::CompoundGroup HexagonInstrInfo::getCompoundCandidateGroup(
3469 const MachineInstr &MI) const {
3470 Register DstReg, SrcReg, Src1Reg, Src2Reg;
3471
3472 switch (MI.getOpcode()) {
3473 default:
3474 return HexagonII::HCG_None;
3475 //
3476 // Compound pairs.
3477 // "p0=cmp.eq(Rs16,Rt16); if (p0.new) jump:nt #r9:2"
3478 // "Rd16=#U6 ; jump #r9:2"
3479 // "Rd16=Rs16 ; jump #r9:2"
3480 //
3481 case Hexagon::C2_cmpeq:
3482 case Hexagon::C2_cmpgt:
3483 case Hexagon::C2_cmpgtu:
3484 DstReg = MI.getOperand(i: 0).getReg();
3485 Src1Reg = MI.getOperand(i: 1).getReg();
3486 Src2Reg = MI.getOperand(i: 2).getReg();
3487 if (Hexagon::PredRegsRegClass.contains(Reg: DstReg) &&
3488 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3489 isIntRegForSubInst(Reg: Src1Reg) && isIntRegForSubInst(Reg: Src2Reg))
3490 return HexagonII::HCG_A;
3491 break;
3492 case Hexagon::C2_cmpeqi:
3493 case Hexagon::C2_cmpgti:
3494 case Hexagon::C2_cmpgtui:
3495 // P0 = cmp.eq(Rs,#u2)
3496 DstReg = MI.getOperand(i: 0).getReg();
3497 SrcReg = MI.getOperand(i: 1).getReg();
3498 if (Hexagon::PredRegsRegClass.contains(Reg: DstReg) &&
3499 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3500 isIntRegForSubInst(Reg: SrcReg) && MI.getOperand(i: 2).isImm() &&
3501 ((isUInt<5>(x: MI.getOperand(i: 2).getImm())) ||
3502 (MI.getOperand(i: 2).getImm() == -1)))
3503 return HexagonII::HCG_A;
3504 break;
3505 case Hexagon::A2_tfr:
3506 // Rd = Rs
3507 DstReg = MI.getOperand(i: 0).getReg();
3508 SrcReg = MI.getOperand(i: 1).getReg();
3509 if (isIntRegForSubInst(Reg: DstReg) && isIntRegForSubInst(Reg: SrcReg))
3510 return HexagonII::HCG_A;
3511 break;
3512 case Hexagon::A2_tfrsi:
3513 // Rd = #u6
3514 // Do not test for #u6 size since the const is getting extended
3515 // regardless and compound could be formed.
3516 DstReg = MI.getOperand(i: 0).getReg();
3517 if (isIntRegForSubInst(Reg: DstReg))
3518 return HexagonII::HCG_A;
3519 break;
3520 case Hexagon::S2_tstbit_i:
3521 DstReg = MI.getOperand(i: 0).getReg();
3522 Src1Reg = MI.getOperand(i: 1).getReg();
3523 if (Hexagon::PredRegsRegClass.contains(Reg: DstReg) &&
3524 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3525 MI.getOperand(i: 2).isImm() &&
3526 isIntRegForSubInst(Reg: Src1Reg) && (MI.getOperand(i: 2).getImm() == 0))
3527 return HexagonII::HCG_A;
3528 break;
3529 // The fact that .new form is used pretty much guarantees
3530 // that predicate register will match. Nevertheless,
3531 // there could be some false positives without additional
3532 // checking.
3533 case Hexagon::J2_jumptnew:
3534 case Hexagon::J2_jumpfnew:
3535 case Hexagon::J2_jumptnewpt:
3536 case Hexagon::J2_jumpfnewpt:
3537 Src1Reg = MI.getOperand(i: 0).getReg();
3538 if (Hexagon::PredRegsRegClass.contains(Reg: Src1Reg) &&
3539 (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3540 return HexagonII::HCG_B;
3541 break;
3542 // Transfer and jump:
3543 // Rd=#U6 ; jump #r9:2
3544 // Rd=Rs ; jump #r9:2
3545 // Do not test for jump range here.
3546 case Hexagon::J2_jump:
3547 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3548 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3549 return HexagonII::HCG_C;
3550 }
3551
3552 return HexagonII::HCG_None;
3553}
3554
3555// Returns -1 when there is no opcode found.
3556unsigned HexagonInstrInfo::getCompoundOpcode(const MachineInstr &GA,
3557 const MachineInstr &GB) const {
3558 assert(getCompoundCandidateGroup(GA) == HexagonII::HCG_A);
3559 assert(getCompoundCandidateGroup(GB) == HexagonII::HCG_B);
3560 if ((GA.getOpcode() != Hexagon::C2_cmpeqi) ||
3561 (GB.getOpcode() != Hexagon::J2_jumptnew))
3562 return -1u;
3563 Register DestReg = GA.getOperand(i: 0).getReg();
3564 if (!GB.readsRegister(Reg: DestReg, /*TRI=*/nullptr))
3565 return -1u;
3566 if (DestReg != Hexagon::P0 && DestReg != Hexagon::P1)
3567 return -1u;
3568 // The value compared against must be either u5 or -1.
3569 const MachineOperand &CmpOp = GA.getOperand(i: 2);
3570 if (!CmpOp.isImm())
3571 return -1u;
3572 int V = CmpOp.getImm();
3573 if (V == -1)
3574 return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqn1_tp0_jump_nt
3575 : Hexagon::J4_cmpeqn1_tp1_jump_nt;
3576 if (!isUInt<5>(x: V))
3577 return -1u;
3578 return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqi_tp0_jump_nt
3579 : Hexagon::J4_cmpeqi_tp1_jump_nt;
3580}
3581
3582// Returns -1 if there is no opcode found.
3583int HexagonInstrInfo::getDuplexOpcode(const MachineInstr &MI,
3584 bool ForBigCore) const {
3585 // Static table to switch the opcodes across Tiny Core and Big Core.
3586 // dup_ opcodes are Big core opcodes.
3587 // NOTE: There are special instructions that need to handled later.
3588 // L4_return* instructions, they will only occupy SLOT0 (on big core too).
3589 // PS_jmpret - This pseudo translates to J2_jumpr which occupies only SLOT2.
3590 // The compiler need to base the root instruction to L6_return_map_to_raw
3591 // which can go any slot.
3592 static const std::map<unsigned, unsigned> DupMap = {
3593 {Hexagon::A2_add, Hexagon::dup_A2_add},
3594 {Hexagon::A2_addi, Hexagon::dup_A2_addi},
3595 {Hexagon::A2_andir, Hexagon::dup_A2_andir},
3596 {Hexagon::A2_combineii, Hexagon::dup_A2_combineii},
3597 {Hexagon::A2_sxtb, Hexagon::dup_A2_sxtb},
3598 {Hexagon::A2_sxth, Hexagon::dup_A2_sxth},
3599 {Hexagon::A2_tfr, Hexagon::dup_A2_tfr},
3600 {Hexagon::A2_tfrsi, Hexagon::dup_A2_tfrsi},
3601 {Hexagon::A2_zxtb, Hexagon::dup_A2_zxtb},
3602 {Hexagon::A2_zxth, Hexagon::dup_A2_zxth},
3603 {Hexagon::A4_combineii, Hexagon::dup_A4_combineii},
3604 {Hexagon::A4_combineir, Hexagon::dup_A4_combineir},
3605 {Hexagon::A4_combineri, Hexagon::dup_A4_combineri},
3606 {Hexagon::C2_cmoveif, Hexagon::dup_C2_cmoveif},
3607 {Hexagon::C2_cmoveit, Hexagon::dup_C2_cmoveit},
3608 {Hexagon::C2_cmovenewif, Hexagon::dup_C2_cmovenewif},
3609 {Hexagon::C2_cmovenewit, Hexagon::dup_C2_cmovenewit},
3610 {Hexagon::C2_cmpeqi, Hexagon::dup_C2_cmpeqi},
3611 {Hexagon::L2_deallocframe, Hexagon::dup_L2_deallocframe},
3612 {Hexagon::L2_loadrb_io, Hexagon::dup_L2_loadrb_io},
3613 {Hexagon::L2_loadrd_io, Hexagon::dup_L2_loadrd_io},
3614 {Hexagon::L2_loadrh_io, Hexagon::dup_L2_loadrh_io},
3615 {Hexagon::L2_loadri_io, Hexagon::dup_L2_loadri_io},
3616 {Hexagon::L2_loadrub_io, Hexagon::dup_L2_loadrub_io},
3617 {Hexagon::L2_loadruh_io, Hexagon::dup_L2_loadruh_io},
3618 {Hexagon::S2_allocframe, Hexagon::dup_S2_allocframe},
3619 {Hexagon::S2_storerb_io, Hexagon::dup_S2_storerb_io},
3620 {Hexagon::S2_storerd_io, Hexagon::dup_S2_storerd_io},
3621 {Hexagon::S2_storerh_io, Hexagon::dup_S2_storerh_io},
3622 {Hexagon::S2_storeri_io, Hexagon::dup_S2_storeri_io},
3623 {Hexagon::S4_storeirb_io, Hexagon::dup_S4_storeirb_io},
3624 {Hexagon::S4_storeiri_io, Hexagon::dup_S4_storeiri_io},
3625 };
3626 unsigned OpNum = MI.getOpcode();
3627 // Conversion to Big core.
3628 if (ForBigCore) {
3629 auto Iter = DupMap.find(x: OpNum);
3630 if (Iter != DupMap.end())
3631 return Iter->second;
3632 } else { // Conversion to Tiny core.
3633 for (const auto &Iter : DupMap)
3634 if (Iter.second == OpNum)
3635 return Iter.first;
3636 }
3637 return -1;
3638}
3639
3640int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
3641 enum Hexagon::PredSense inPredSense;
3642 inPredSense = invertPredicate ? Hexagon::PredSense_false :
3643 Hexagon::PredSense_true;
3644 int CondOpcode = Hexagon::getPredOpcode(Opcode: Opc, inPredSense);
3645 if (CondOpcode >= 0) // Valid Conditional opcode/instruction
3646 return CondOpcode;
3647
3648 llvm_unreachable("Unexpected predicable instruction");
3649}
3650
3651// Return the cur value instruction for a given store.
3652int HexagonInstrInfo::getDotCurOp(const MachineInstr &MI) const {
3653 switch (MI.getOpcode()) {
3654 default: llvm_unreachable("Unknown .cur type");
3655 case Hexagon::V6_vL32b_pi:
3656 return Hexagon::V6_vL32b_cur_pi;
3657 case Hexagon::V6_vL32b_ai:
3658 return Hexagon::V6_vL32b_cur_ai;
3659 case Hexagon::V6_vL32b_nt_pi:
3660 return Hexagon::V6_vL32b_nt_cur_pi;
3661 case Hexagon::V6_vL32b_nt_ai:
3662 return Hexagon::V6_vL32b_nt_cur_ai;
3663 case Hexagon::V6_vL32b_ppu:
3664 return Hexagon::V6_vL32b_cur_ppu;
3665 case Hexagon::V6_vL32b_nt_ppu:
3666 return Hexagon::V6_vL32b_nt_cur_ppu;
3667 }
3668 return 0;
3669}
3670
3671// Return the regular version of the .cur instruction.
3672int HexagonInstrInfo::getNonDotCurOp(const MachineInstr &MI) const {
3673 switch (MI.getOpcode()) {
3674 default: llvm_unreachable("Unknown .cur type");
3675 case Hexagon::V6_vL32b_cur_pi:
3676 return Hexagon::V6_vL32b_pi;
3677 case Hexagon::V6_vL32b_cur_ai:
3678 return Hexagon::V6_vL32b_ai;
3679 case Hexagon::V6_vL32b_nt_cur_pi:
3680 return Hexagon::V6_vL32b_nt_pi;
3681 case Hexagon::V6_vL32b_nt_cur_ai:
3682 return Hexagon::V6_vL32b_nt_ai;
3683 case Hexagon::V6_vL32b_cur_ppu:
3684 return Hexagon::V6_vL32b_ppu;
3685 case Hexagon::V6_vL32b_nt_cur_ppu:
3686 return Hexagon::V6_vL32b_nt_ppu;
3687 }
3688 return 0;
3689}
3690
3691// The diagram below shows the steps involved in the conversion of a predicated
3692// store instruction to its .new predicated new-value form.
3693//
3694// Note: It doesn't include conditional new-value stores as they can't be
3695// converted to .new predicate.
3696//
3697// p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
3698// ^ ^
3699// / \ (not OK. it will cause new-value store to be
3700// / X conditional on p0.new while R2 producer is
3701// / \ on p0)
3702// / \.
3703// p.new store p.old NV store
3704// [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
3705// ^ ^
3706// \ /
3707// \ /
3708// \ /
3709// p.old store
3710// [if (p0)memw(R0+#0)=R2]
3711//
3712// The following set of instructions further explains the scenario where
3713// conditional new-value store becomes invalid when promoted to .new predicate
3714// form.
3715//
3716// { 1) if (p0) r0 = add(r1, r2)
3717// 2) p0 = cmp.eq(r3, #0) }
3718//
3719// 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
3720// the first two instructions because in instr 1, r0 is conditional on old value
3721// of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
3722// is not valid for new-value stores.
3723// Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
3724// from the "Conditional Store" list. Because a predicated new value store
3725// would NOT be promoted to a double dot new store. See diagram below:
3726// This function returns yes for those stores that are predicated but not
3727// yet promoted to predicate dot new instructions.
3728//
3729// +---------------------+
3730// /-----| if (p0) memw(..)=r0 |---------\~
3731// || +---------------------+ ||
3732// promote || /\ /\ || promote
3733// || /||\ /||\ ||
3734// \||/ demote || \||/
3735// \/ || || \/
3736// +-------------------------+ || +-------------------------+
3737// | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
3738// +-------------------------+ || +-------------------------+
3739// || || ||
3740// || demote \||/
3741// promote || \/ NOT possible
3742// || || /\~
3743// \||/ || /||\~
3744// \/ || ||
3745// +-----------------------------+
3746// | if (p0.new) memw(..)=r0.new |
3747// +-----------------------------+
3748// Double Dot New Store
3749//
3750// Returns the most basic instruction for the .new predicated instructions and
3751// new-value stores.
3752// For example, all of the following instructions will be converted back to the
3753// same instruction:
3754// 1) if (p0.new) memw(R0+#0) = R1.new --->
3755// 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
3756// 3) if (p0.new) memw(R0+#0) = R1 --->
3757//
3758// To understand the translation of instruction 1 to its original form, consider
3759// a packet with 3 instructions.
3760// { p0 = cmp.eq(R0,R1)
3761// if (p0.new) R2 = add(R3, R4)
3762// R5 = add (R3, R1)
3763// }
3764// if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
3765//
3766// This instruction can be part of the previous packet only if both p0 and R2
3767// are promoted to .new values. This promotion happens in steps, first
3768// predicate register is promoted to .new and in the next iteration R2 is
3769// promoted. Therefore, in case of dependence check failure (due to R5) during
3770// next iteration, it should be converted back to its most basic form.
3771
3772// Return the new value instruction for a given store.
3773int HexagonInstrInfo::getDotNewOp(const MachineInstr &MI) const {
3774 int NVOpcode = Hexagon::getNewValueOpcode(Opcode: MI.getOpcode());
3775 if (NVOpcode >= 0) // Valid new-value store instruction.
3776 return NVOpcode;
3777
3778 switch (MI.getOpcode()) {
3779 default:
3780 report_fatal_error(reason: Twine("Unknown .new type: ") +
3781 std::to_string(val: MI.getOpcode()));
3782 case Hexagon::S4_storerb_ur:
3783 return Hexagon::S4_storerbnew_ur;
3784
3785 case Hexagon::S2_storerb_pci:
3786 return Hexagon::S2_storerb_pci;
3787
3788 case Hexagon::S2_storeri_pci:
3789 return Hexagon::S2_storeri_pci;
3790
3791 case Hexagon::S2_storerh_pci:
3792 return Hexagon::S2_storerh_pci;
3793
3794 case Hexagon::S2_storerd_pci:
3795 return Hexagon::S2_storerd_pci;
3796
3797 case Hexagon::S2_storerf_pci:
3798 return Hexagon::S2_storerf_pci;
3799
3800 case Hexagon::V6_vS32b_ai:
3801 return Hexagon::V6_vS32b_new_ai;
3802
3803 case Hexagon::V6_vS32b_pi:
3804 return Hexagon::V6_vS32b_new_pi;
3805 }
3806 return 0;
3807}
3808
3809// Returns the opcode to use when converting MI, which is a conditional jump,
3810// into a conditional instruction which uses the .new value of the predicate.
3811// We also use branch probabilities to add a hint to the jump.
3812// If MBPI is null, all edges will be treated as equally likely for the
3813// purposes of establishing a predication hint.
3814int HexagonInstrInfo::getDotNewPredJumpOp(const MachineInstr &MI,
3815 const MachineBranchProbabilityInfo *MBPI) const {
3816 // We assume that block can have at most two successors.
3817 const MachineBasicBlock *Src = MI.getParent();
3818 const MachineOperand &BrTarget = MI.getOperand(i: 1);
3819 bool Taken = false;
3820 const BranchProbability OneHalf(1, 2);
3821
3822 auto getEdgeProbability = [MBPI] (const MachineBasicBlock *Src,
3823 const MachineBasicBlock *Dst) {
3824 if (MBPI)
3825 return MBPI->getEdgeProbability(Src, Dst);
3826 return BranchProbability(1, Src->succ_size());
3827 };
3828
3829 if (BrTarget.isMBB()) {
3830 const MachineBasicBlock *Dst = BrTarget.getMBB();
3831 Taken = getEdgeProbability(Src, Dst) >= OneHalf;
3832 } else {
3833 // The branch target is not a basic block (most likely a function).
3834 // Since BPI only gives probabilities for targets that are basic blocks,
3835 // try to identify another target of this branch (potentially a fall-
3836 // -through) and check the probability of that target.
3837 //
3838 // The only handled branch combinations are:
3839 // - one conditional branch,
3840 // - one conditional branch followed by one unconditional branch.
3841 // Otherwise, assume not-taken.
3842 assert(MI.isConditionalBranch());
3843 const MachineBasicBlock &B = *MI.getParent();
3844 bool SawCond = false, Bad = false;
3845 for (const MachineInstr &I : B) {
3846 if (!I.isBranch())
3847 continue;
3848 if (I.isConditionalBranch()) {
3849 SawCond = true;
3850 if (&I != &MI) {
3851 Bad = true;
3852 break;
3853 }
3854 }
3855 if (I.isUnconditionalBranch() && !SawCond) {
3856 Bad = true;
3857 break;
3858 }
3859 }
3860 if (!Bad) {
3861 MachineBasicBlock::const_instr_iterator It(MI);
3862 MachineBasicBlock::const_instr_iterator NextIt = std::next(x: It);
3863 if (NextIt == B.instr_end()) {
3864 // If this branch is the last, look for the fall-through block.
3865 for (const MachineBasicBlock *SB : B.successors()) {
3866 if (!B.isLayoutSuccessor(MBB: SB))
3867 continue;
3868 Taken = getEdgeProbability(Src, SB) < OneHalf;
3869 break;
3870 }
3871 } else {
3872 assert(NextIt->isUnconditionalBranch());
3873 // Find the first MBB operand and assume it's the target.
3874 const MachineBasicBlock *BT = nullptr;
3875 for (const MachineOperand &Op : NextIt->operands()) {
3876 if (!Op.isMBB())
3877 continue;
3878 BT = Op.getMBB();
3879 break;
3880 }
3881 Taken = BT && getEdgeProbability(Src, BT) < OneHalf;
3882 }
3883 } // if (!Bad)
3884 }
3885
3886 // The Taken flag should be set to something reasonable by this point.
3887
3888 switch (MI.getOpcode()) {
3889 case Hexagon::J2_jumpt:
3890 return Taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
3891 case Hexagon::J2_jumpf:
3892 return Taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
3893
3894 default:
3895 llvm_unreachable("Unexpected jump instruction.");
3896 }
3897}
3898
3899// Return .new predicate version for an instruction.
3900int HexagonInstrInfo::getDotNewPredOp(const MachineInstr &MI,
3901 const MachineBranchProbabilityInfo *MBPI) const {
3902 switch (MI.getOpcode()) {
3903 // Conditional Jumps
3904 case Hexagon::J2_jumpt:
3905 case Hexagon::J2_jumpf:
3906 return getDotNewPredJumpOp(MI, MBPI);
3907 }
3908
3909 int NewOpcode = Hexagon::getPredNewOpcode(Opcode: MI.getOpcode());
3910 if (NewOpcode >= 0)
3911 return NewOpcode;
3912 return 0;
3913}
3914
3915int HexagonInstrInfo::getDotOldOp(const MachineInstr &MI) const {
3916 int NewOp = MI.getOpcode();
3917 if (isPredicated(Opcode: NewOp) && isPredicatedNew(Opcode: NewOp)) { // Get predicate old form
3918 NewOp = Hexagon::getPredOldOpcode(Opcode: NewOp);
3919 // All Hexagon architectures have prediction bits on dot-new branches,
3920 // but only Hexagon V60+ has prediction bits on dot-old ones. Make sure
3921 // to pick the right opcode when converting back to dot-old.
3922 if (!Subtarget.hasFeature(Feature: Hexagon::ArchV60)) {
3923 switch (NewOp) {
3924 case Hexagon::J2_jumptpt:
3925 NewOp = Hexagon::J2_jumpt;
3926 break;
3927 case Hexagon::J2_jumpfpt:
3928 NewOp = Hexagon::J2_jumpf;
3929 break;
3930 case Hexagon::J2_jumprtpt:
3931 NewOp = Hexagon::J2_jumprt;
3932 break;
3933 case Hexagon::J2_jumprfpt:
3934 NewOp = Hexagon::J2_jumprf;
3935 break;
3936 }
3937 }
3938 assert(NewOp >= 0 &&
3939 "Couldn't change predicate new instruction to its old form.");
3940 }
3941
3942 if (isNewValueStore(Opcode: NewOp)) { // Convert into non-new-value format
3943 NewOp = Hexagon::getNonNVStore(Opcode: NewOp);
3944 assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
3945 }
3946
3947 if (Subtarget.hasV60Ops())
3948 return NewOp;
3949
3950 // Subtargets prior to V60 didn't support 'taken' forms of predicated jumps.
3951 switch (NewOp) {
3952 case Hexagon::J2_jumpfpt:
3953 return Hexagon::J2_jumpf;
3954 case Hexagon::J2_jumptpt:
3955 return Hexagon::J2_jumpt;
3956 case Hexagon::J2_jumprfpt:
3957 return Hexagon::J2_jumprf;
3958 case Hexagon::J2_jumprtpt:
3959 return Hexagon::J2_jumprt;
3960 }
3961 return NewOp;
3962}
3963
3964// See if instruction could potentially be a duplex candidate.
3965// If so, return its group. Zero otherwise.
3966HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup(
3967 const MachineInstr &MI) const {
3968 Register DstReg, SrcReg, Src1Reg, Src2Reg;
3969 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
3970
3971 switch (MI.getOpcode()) {
3972 default:
3973 return HexagonII::HSIG_None;
3974 //
3975 // Group L1:
3976 //
3977 // Rd = memw(Rs+#u4:2)
3978 // Rd = memub(Rs+#u4:0)
3979 case Hexagon::L2_loadri_io:
3980 case Hexagon::dup_L2_loadri_io:
3981 DstReg = MI.getOperand(i: 0).getReg();
3982 SrcReg = MI.getOperand(i: 1).getReg();
3983 // Special case this one from Group L2.
3984 // Rd = memw(r29+#u5:2)
3985 if (isIntRegForSubInst(Reg: DstReg)) {
3986 if (Hexagon::IntRegsRegClass.contains(Reg: SrcReg) &&
3987 HRI.getStackRegister() == SrcReg &&
3988 MI.getOperand(i: 2).isImm() &&
3989 isShiftedUInt<5,2>(x: MI.getOperand(i: 2).getImm()))
3990 return HexagonII::HSIG_L2;
3991 // Rd = memw(Rs+#u4:2)
3992 if (isIntRegForSubInst(Reg: SrcReg) &&
3993 (MI.getOperand(i: 2).isImm() &&
3994 isShiftedUInt<4,2>(x: MI.getOperand(i: 2).getImm())))
3995 return HexagonII::HSIG_L1;
3996 }
3997 break;
3998 case Hexagon::L2_loadrub_io:
3999 case Hexagon::dup_L2_loadrub_io:
4000 // Rd = memub(Rs+#u4:0)
4001 DstReg = MI.getOperand(i: 0).getReg();
4002 SrcReg = MI.getOperand(i: 1).getReg();
4003 if (isIntRegForSubInst(Reg: DstReg) && isIntRegForSubInst(Reg: SrcReg) &&
4004 MI.getOperand(i: 2).isImm() && isUInt<4>(x: MI.getOperand(i: 2).getImm()))
4005 return HexagonII::HSIG_L1;
4006 break;
4007 //
4008 // Group L2:
4009 //
4010 // Rd = memh/memuh(Rs+#u3:1)
4011 // Rd = memb(Rs+#u3:0)
4012 // Rd = memw(r29+#u5:2) - Handled above.
4013 // Rdd = memd(r29+#u5:3)
4014 // deallocframe
4015 // [if ([!]p0[.new])] dealloc_return
4016 // [if ([!]p0[.new])] jumpr r31
4017 case Hexagon::L2_loadrh_io:
4018 case Hexagon::L2_loadruh_io:
4019 case Hexagon::dup_L2_loadrh_io:
4020 case Hexagon::dup_L2_loadruh_io:
4021 // Rd = memh/memuh(Rs+#u3:1)
4022 DstReg = MI.getOperand(i: 0).getReg();
4023 SrcReg = MI.getOperand(i: 1).getReg();
4024 if (isIntRegForSubInst(Reg: DstReg) && isIntRegForSubInst(Reg: SrcReg) &&
4025 MI.getOperand(i: 2).isImm() &&
4026 isShiftedUInt<3,1>(x: MI.getOperand(i: 2).getImm()))
4027 return HexagonII::HSIG_L2;
4028 break;
4029 case Hexagon::L2_loadrb_io:
4030 case Hexagon::dup_L2_loadrb_io:
4031 // Rd = memb(Rs+#u3:0)
4032 DstReg = MI.getOperand(i: 0).getReg();
4033 SrcReg = MI.getOperand(i: 1).getReg();
4034 if (isIntRegForSubInst(Reg: DstReg) && isIntRegForSubInst(Reg: SrcReg) &&
4035 MI.getOperand(i: 2).isImm() &&
4036 isUInt<3>(x: MI.getOperand(i: 2).getImm()))
4037 return HexagonII::HSIG_L2;
4038 break;
4039 case Hexagon::L2_loadrd_io:
4040 case Hexagon::dup_L2_loadrd_io:
4041 // Rdd = memd(r29+#u5:3)
4042 DstReg = MI.getOperand(i: 0).getReg();
4043 SrcReg = MI.getOperand(i: 1).getReg();
4044 if (isDblRegForSubInst(Reg: DstReg, HRI) &&
4045 Hexagon::IntRegsRegClass.contains(Reg: SrcReg) &&
4046 HRI.getStackRegister() == SrcReg &&
4047 MI.getOperand(i: 2).isImm() &&
4048 isShiftedUInt<5,3>(x: MI.getOperand(i: 2).getImm()))
4049 return HexagonII::HSIG_L2;
4050 break;
4051 // dealloc_return is not documented in Hexagon Manual, but marked
4052 // with A_SUBINSN attribute in iset_v4classic.py.
4053 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
4054 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
4055 case Hexagon::L4_return:
4056 case Hexagon::L2_deallocframe:
4057 case Hexagon::dup_L2_deallocframe:
4058 return HexagonII::HSIG_L2;
4059 case Hexagon::EH_RETURN_JMPR:
4060 case Hexagon::PS_jmpret:
4061 case Hexagon::SL2_jumpr31:
4062 // jumpr r31
4063 // Actual form JMPR implicit-def %pc, implicit %r31, implicit internal %r0
4064 DstReg = MI.getOperand(i: 0).getReg();
4065 if (Hexagon::IntRegsRegClass.contains(Reg: DstReg) && (Hexagon::R31 == DstReg))
4066 return HexagonII::HSIG_L2;
4067 break;
4068 case Hexagon::PS_jmprett:
4069 case Hexagon::PS_jmpretf:
4070 case Hexagon::PS_jmprettnewpt:
4071 case Hexagon::PS_jmpretfnewpt:
4072 case Hexagon::PS_jmprettnew:
4073 case Hexagon::PS_jmpretfnew:
4074 case Hexagon::SL2_jumpr31_t:
4075 case Hexagon::SL2_jumpr31_f:
4076 case Hexagon::SL2_jumpr31_tnew:
4077 case Hexagon::SL2_jumpr31_fnew:
4078 DstReg = MI.getOperand(i: 1).getReg();
4079 SrcReg = MI.getOperand(i: 0).getReg();
4080 // [if ([!]p0[.new])] jumpr r31
4081 if ((Hexagon::PredRegsRegClass.contains(Reg: SrcReg) &&
4082 (Hexagon::P0 == SrcReg)) &&
4083 (Hexagon::IntRegsRegClass.contains(Reg: DstReg) && (Hexagon::R31 == DstReg)))
4084 return HexagonII::HSIG_L2;
4085 break;
4086 case Hexagon::L4_return_t:
4087 case Hexagon::L4_return_f:
4088 case Hexagon::L4_return_tnew_pnt:
4089 case Hexagon::L4_return_fnew_pnt:
4090 case Hexagon::L4_return_tnew_pt:
4091 case Hexagon::L4_return_fnew_pt:
4092 // [if ([!]p0[.new])] dealloc_return
4093 SrcReg = MI.getOperand(i: 0).getReg();
4094 if (Hexagon::PredRegsRegClass.contains(Reg: SrcReg) && (Hexagon::P0 == SrcReg))
4095 return HexagonII::HSIG_L2;
4096 break;
4097 //
4098 // Group S1:
4099 //
4100 // memw(Rs+#u4:2) = Rt
4101 // memb(Rs+#u4:0) = Rt
4102 case Hexagon::S2_storeri_io:
4103 case Hexagon::dup_S2_storeri_io:
4104 // Special case this one from Group S2.
4105 // memw(r29+#u5:2) = Rt
4106 Src1Reg = MI.getOperand(i: 0).getReg();
4107 Src2Reg = MI.getOperand(i: 2).getReg();
4108 if (Hexagon::IntRegsRegClass.contains(Reg: Src1Reg) &&
4109 isIntRegForSubInst(Reg: Src2Reg) &&
4110 HRI.getStackRegister() == Src1Reg && MI.getOperand(i: 1).isImm() &&
4111 isShiftedUInt<5,2>(x: MI.getOperand(i: 1).getImm()))
4112 return HexagonII::HSIG_S2;
4113 // memw(Rs+#u4:2) = Rt
4114 if (isIntRegForSubInst(Reg: Src1Reg) && isIntRegForSubInst(Reg: Src2Reg) &&
4115 MI.getOperand(i: 1).isImm() &&
4116 isShiftedUInt<4,2>(x: MI.getOperand(i: 1).getImm()))
4117 return HexagonII::HSIG_S1;
4118 break;
4119 case Hexagon::S2_storerb_io:
4120 case Hexagon::dup_S2_storerb_io:
4121 // memb(Rs+#u4:0) = Rt
4122 Src1Reg = MI.getOperand(i: 0).getReg();
4123 Src2Reg = MI.getOperand(i: 2).getReg();
4124 if (isIntRegForSubInst(Reg: Src1Reg) && isIntRegForSubInst(Reg: Src2Reg) &&
4125 MI.getOperand(i: 1).isImm() && isUInt<4>(x: MI.getOperand(i: 1).getImm()))
4126 return HexagonII::HSIG_S1;
4127 break;
4128 //
4129 // Group S2:
4130 //
4131 // memh(Rs+#u3:1) = Rt
4132 // memw(r29+#u5:2) = Rt
4133 // memd(r29+#s6:3) = Rtt
4134 // memw(Rs+#u4:2) = #U1
4135 // memb(Rs+#u4) = #U1
4136 // allocframe(#u5:3)
4137 case Hexagon::S2_storerh_io:
4138 case Hexagon::dup_S2_storerh_io:
4139 // memh(Rs+#u3:1) = Rt
4140 Src1Reg = MI.getOperand(i: 0).getReg();
4141 Src2Reg = MI.getOperand(i: 2).getReg();
4142 if (isIntRegForSubInst(Reg: Src1Reg) && isIntRegForSubInst(Reg: Src2Reg) &&
4143 MI.getOperand(i: 1).isImm() &&
4144 isShiftedUInt<3,1>(x: MI.getOperand(i: 1).getImm()))
4145 return HexagonII::HSIG_S1;
4146 break;
4147 case Hexagon::S2_storerd_io:
4148 case Hexagon::dup_S2_storerd_io:
4149 // memd(r29+#s6:3) = Rtt
4150 Src1Reg = MI.getOperand(i: 0).getReg();
4151 Src2Reg = MI.getOperand(i: 2).getReg();
4152 if (isDblRegForSubInst(Reg: Src2Reg, HRI) &&
4153 Hexagon::IntRegsRegClass.contains(Reg: Src1Reg) &&
4154 HRI.getStackRegister() == Src1Reg && MI.getOperand(i: 1).isImm() &&
4155 isShiftedInt<6,3>(x: MI.getOperand(i: 1).getImm()))
4156 return HexagonII::HSIG_S2;
4157 break;
4158 case Hexagon::S4_storeiri_io:
4159 case Hexagon::dup_S4_storeiri_io:
4160 // memw(Rs+#u4:2) = #U1
4161 Src1Reg = MI.getOperand(i: 0).getReg();
4162 if (isIntRegForSubInst(Reg: Src1Reg) && MI.getOperand(i: 1).isImm() &&
4163 isShiftedUInt<4,2>(x: MI.getOperand(i: 1).getImm()) &&
4164 MI.getOperand(i: 2).isImm() && isUInt<1>(x: MI.getOperand(i: 2).getImm()))
4165 return HexagonII::HSIG_S2;
4166 break;
4167 case Hexagon::S4_storeirb_io:
4168 case Hexagon::dup_S4_storeirb_io:
4169 // memb(Rs+#u4) = #U1
4170 Src1Reg = MI.getOperand(i: 0).getReg();
4171 if (isIntRegForSubInst(Reg: Src1Reg) &&
4172 MI.getOperand(i: 1).isImm() && isUInt<4>(x: MI.getOperand(i: 1).getImm()) &&
4173 MI.getOperand(i: 2).isImm() && isUInt<1>(x: MI.getOperand(i: 2).getImm()))
4174 return HexagonII::HSIG_S2;
4175 break;
4176 case Hexagon::S2_allocframe:
4177 case Hexagon::dup_S2_allocframe:
4178 if (MI.getOperand(i: 2).isImm() &&
4179 isShiftedUInt<5,3>(x: MI.getOperand(i: 2).getImm()))
4180 return HexagonII::HSIG_S1;
4181 break;
4182 //
4183 // Group A:
4184 //
4185 // Rx = add(Rx,#s7)
4186 // Rd = Rs
4187 // Rd = #u6
4188 // Rd = #-1
4189 // if ([!]P0[.new]) Rd = #0
4190 // Rd = add(r29,#u6:2)
4191 // Rx = add(Rx,Rs)
4192 // P0 = cmp.eq(Rs,#u2)
4193 // Rdd = combine(#0,Rs)
4194 // Rdd = combine(Rs,#0)
4195 // Rdd = combine(#u2,#U2)
4196 // Rd = add(Rs,#1)
4197 // Rd = add(Rs,#-1)
4198 // Rd = sxth/sxtb/zxtb/zxth(Rs)
4199 // Rd = and(Rs,#1)
4200 case Hexagon::A2_addi:
4201 case Hexagon::dup_A2_addi:
4202 DstReg = MI.getOperand(i: 0).getReg();
4203 SrcReg = MI.getOperand(i: 1).getReg();
4204 if (isIntRegForSubInst(Reg: DstReg)) {
4205 // Rd = add(r29,#u6:2)
4206 if (Hexagon::IntRegsRegClass.contains(Reg: SrcReg) &&
4207 HRI.getStackRegister() == SrcReg && MI.getOperand(i: 2).isImm() &&
4208 isShiftedUInt<6,2>(x: MI.getOperand(i: 2).getImm()))
4209 return HexagonII::HSIG_A;
4210 // Rx = add(Rx,#s7)
4211 if ((DstReg == SrcReg) && MI.getOperand(i: 2).isImm() &&
4212 isInt<7>(x: MI.getOperand(i: 2).getImm()))
4213 return HexagonII::HSIG_A;
4214 // Rd = add(Rs,#1)
4215 // Rd = add(Rs,#-1)
4216 if (isIntRegForSubInst(Reg: SrcReg) && MI.getOperand(i: 2).isImm() &&
4217 ((MI.getOperand(i: 2).getImm() == 1) ||
4218 (MI.getOperand(i: 2).getImm() == -1)))
4219 return HexagonII::HSIG_A;
4220 }
4221 break;
4222 case Hexagon::A2_add:
4223 case Hexagon::dup_A2_add:
4224 // Rx = add(Rx,Rs)
4225 DstReg = MI.getOperand(i: 0).getReg();
4226 Src1Reg = MI.getOperand(i: 1).getReg();
4227 Src2Reg = MI.getOperand(i: 2).getReg();
4228 if (isIntRegForSubInst(Reg: DstReg) && (DstReg == Src1Reg) &&
4229 isIntRegForSubInst(Reg: Src2Reg))
4230 return HexagonII::HSIG_A;
4231 break;
4232 case Hexagon::A2_andir:
4233 case Hexagon::dup_A2_andir:
4234 // Same as zxtb.
4235 // Rd16=and(Rs16,#255)
4236 // Rd16=and(Rs16,#1)
4237 DstReg = MI.getOperand(i: 0).getReg();
4238 SrcReg = MI.getOperand(i: 1).getReg();
4239 if (isIntRegForSubInst(Reg: DstReg) && isIntRegForSubInst(Reg: SrcReg) &&
4240 MI.getOperand(i: 2).isImm() &&
4241 ((MI.getOperand(i: 2).getImm() == 1) ||
4242 (MI.getOperand(i: 2).getImm() == 255)))
4243 return HexagonII::HSIG_A;
4244 break;
4245 case Hexagon::A2_tfr:
4246 case Hexagon::dup_A2_tfr:
4247 // Rd = Rs
4248 DstReg = MI.getOperand(i: 0).getReg();
4249 SrcReg = MI.getOperand(i: 1).getReg();
4250 if (isIntRegForSubInst(Reg: DstReg) && isIntRegForSubInst(Reg: SrcReg))
4251 return HexagonII::HSIG_A;
4252 break;
4253 case Hexagon::A2_tfrsi:
4254 case Hexagon::dup_A2_tfrsi:
4255 // Rd = #u6
4256 // Do not test for #u6 size since the const is getting extended
4257 // regardless and compound could be formed.
4258 // Rd = #-1
4259 DstReg = MI.getOperand(i: 0).getReg();
4260 if (isIntRegForSubInst(Reg: DstReg))
4261 return HexagonII::HSIG_A;
4262 break;
4263 case Hexagon::C2_cmoveit:
4264 case Hexagon::C2_cmovenewit:
4265 case Hexagon::C2_cmoveif:
4266 case Hexagon::C2_cmovenewif:
4267 case Hexagon::dup_C2_cmoveit:
4268 case Hexagon::dup_C2_cmovenewit:
4269 case Hexagon::dup_C2_cmoveif:
4270 case Hexagon::dup_C2_cmovenewif:
4271 // if ([!]P0[.new]) Rd = #0
4272 // Actual form:
4273 // %r16 = C2_cmovenewit internal %p0, 0, implicit undef %r16;
4274 DstReg = MI.getOperand(i: 0).getReg();
4275 SrcReg = MI.getOperand(i: 1).getReg();
4276 if (isIntRegForSubInst(Reg: DstReg) &&
4277 Hexagon::PredRegsRegClass.contains(Reg: SrcReg) && Hexagon::P0 == SrcReg &&
4278 MI.getOperand(i: 2).isImm() && MI.getOperand(i: 2).getImm() == 0)
4279 return HexagonII::HSIG_A;
4280 break;
4281 case Hexagon::C2_cmpeqi:
4282 case Hexagon::dup_C2_cmpeqi:
4283 // P0 = cmp.eq(Rs,#u2)
4284 DstReg = MI.getOperand(i: 0).getReg();
4285 SrcReg = MI.getOperand(i: 1).getReg();
4286 if (Hexagon::PredRegsRegClass.contains(Reg: DstReg) &&
4287 Hexagon::P0 == DstReg && isIntRegForSubInst(Reg: SrcReg) &&
4288 MI.getOperand(i: 2).isImm() && isUInt<2>(x: MI.getOperand(i: 2).getImm()))
4289 return HexagonII::HSIG_A;
4290 break;
4291 case Hexagon::A2_combineii:
4292 case Hexagon::A4_combineii:
4293 case Hexagon::dup_A2_combineii:
4294 case Hexagon::dup_A4_combineii:
4295 // Rdd = combine(#u2,#U2)
4296 DstReg = MI.getOperand(i: 0).getReg();
4297 if (isDblRegForSubInst(Reg: DstReg, HRI) &&
4298 ((MI.getOperand(i: 1).isImm() && isUInt<2>(x: MI.getOperand(i: 1).getImm())) ||
4299 (MI.getOperand(i: 1).isGlobal() &&
4300 isUInt<2>(x: MI.getOperand(i: 1).getOffset()))) &&
4301 ((MI.getOperand(i: 2).isImm() && isUInt<2>(x: MI.getOperand(i: 2).getImm())) ||
4302 (MI.getOperand(i: 2).isGlobal() &&
4303 isUInt<2>(x: MI.getOperand(i: 2).getOffset()))))
4304 return HexagonII::HSIG_A;
4305 break;
4306 case Hexagon::A4_combineri:
4307 case Hexagon::dup_A4_combineri:
4308 // Rdd = combine(Rs,#0)
4309 // Rdd = combine(Rs,#0)
4310 DstReg = MI.getOperand(i: 0).getReg();
4311 SrcReg = MI.getOperand(i: 1).getReg();
4312 if (isDblRegForSubInst(Reg: DstReg, HRI) && isIntRegForSubInst(Reg: SrcReg) &&
4313 ((MI.getOperand(i: 2).isImm() && MI.getOperand(i: 2).getImm() == 0) ||
4314 (MI.getOperand(i: 2).isGlobal() && MI.getOperand(i: 2).getOffset() == 0)))
4315 return HexagonII::HSIG_A;
4316 break;
4317 case Hexagon::A4_combineir:
4318 case Hexagon::dup_A4_combineir:
4319 // Rdd = combine(#0,Rs)
4320 DstReg = MI.getOperand(i: 0).getReg();
4321 SrcReg = MI.getOperand(i: 2).getReg();
4322 if (isDblRegForSubInst(Reg: DstReg, HRI) && isIntRegForSubInst(Reg: SrcReg) &&
4323 ((MI.getOperand(i: 1).isImm() && MI.getOperand(i: 1).getImm() == 0) ||
4324 (MI.getOperand(i: 1).isGlobal() && MI.getOperand(i: 1).getOffset() == 0)))
4325 return HexagonII::HSIG_A;
4326 break;
4327 case Hexagon::A2_sxtb:
4328 case Hexagon::A2_sxth:
4329 case Hexagon::A2_zxtb:
4330 case Hexagon::A2_zxth:
4331 case Hexagon::dup_A2_sxtb:
4332 case Hexagon::dup_A2_sxth:
4333 case Hexagon::dup_A2_zxtb:
4334 case Hexagon::dup_A2_zxth:
4335 // Rd = sxth/sxtb/zxtb/zxth(Rs)
4336 DstReg = MI.getOperand(i: 0).getReg();
4337 SrcReg = MI.getOperand(i: 1).getReg();
4338 if (isIntRegForSubInst(Reg: DstReg) && isIntRegForSubInst(Reg: SrcReg))
4339 return HexagonII::HSIG_A;
4340 break;
4341 }
4342
4343 return HexagonII::HSIG_None;
4344}
4345
4346short HexagonInstrInfo::getEquivalentHWInstr(const MachineInstr &MI) const {
4347 return Hexagon::getRealHWInstr(Opcode: MI.getOpcode(), inInstrType: Hexagon::InstrType_Real);
4348}
4349
4350unsigned HexagonInstrInfo::getInstrTimingClassLatency(
4351 const InstrItineraryData *ItinData, const MachineInstr &MI) const {
4352 // Default to one cycle for no itinerary. However, an "empty" itinerary may
4353 // still have a MinLatency property, which getStageLatency checks.
4354 if (!ItinData)
4355 return getInstrLatency(ItinData, MI);
4356
4357 if (MI.isTransient())
4358 return 0;
4359 return ItinData->getStageLatency(ItinClassIndx: MI.getDesc().getSchedClass());
4360}
4361
4362/// getOperandLatency - Compute and return the use operand latency of a given
4363/// pair of def and use.
4364/// In most cases, the static scheduling itinerary was enough to determine the
4365/// operand latency. But it may not be possible for instructions with variable
4366/// number of defs / uses.
4367///
4368/// This is a raw interface to the itinerary that may be directly overridden by
4369/// a target. Use computeOperandLatency to get the best estimate of latency.
4370std::optional<unsigned> HexagonInstrInfo::getOperandLatency(
4371 const InstrItineraryData *ItinData, const MachineInstr &DefMI,
4372 unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const {
4373 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4374
4375 // Get DefIdx and UseIdx for super registers.
4376 const MachineOperand &DefMO = DefMI.getOperand(i: DefIdx);
4377
4378 if (DefMO.isReg() && DefMO.getReg().isPhysical()) {
4379 if (DefMO.isImplicit()) {
4380 for (MCPhysReg SR : HRI.superregs(Reg: DefMO.getReg())) {
4381 int Idx = DefMI.findRegisterDefOperandIdx(Reg: SR, TRI: &HRI, isDead: false, Overlap: false);
4382 if (Idx != -1) {
4383 DefIdx = Idx;
4384 break;
4385 }
4386 }
4387 }
4388
4389 const MachineOperand &UseMO = UseMI.getOperand(i: UseIdx);
4390 if (UseMO.isImplicit()) {
4391 for (MCPhysReg SR : HRI.superregs(Reg: UseMO.getReg())) {
4392 int Idx = UseMI.findRegisterUseOperandIdx(Reg: SR, TRI: &HRI, isKill: false);
4393 if (Idx != -1) {
4394 UseIdx = Idx;
4395 break;
4396 }
4397 }
4398 }
4399 }
4400
4401 std::optional<unsigned> Latency = TargetInstrInfo::getOperandLatency(
4402 ItinData, DefMI, DefIdx, UseMI, UseIdx);
4403 if (Latency == 0)
4404 // We should never have 0 cycle latency between two instructions unless
4405 // they can be packetized together. However, this decision can't be made
4406 // here.
4407 Latency = 1;
4408 return Latency;
4409}
4410
4411// inverts the predication logic.
4412// p -> NotP
4413// NotP -> P
4414bool HexagonInstrInfo::getInvertedPredSense(
4415 SmallVectorImpl<MachineOperand> &Cond) const {
4416 if (Cond.empty())
4417 return false;
4418 unsigned Opc = getInvertedPredicatedOpcode(Opc: Cond[0].getImm());
4419 Cond[0].setImm(Opc);
4420 return true;
4421}
4422
4423unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
4424 int InvPredOpcode;
4425 InvPredOpcode = isPredicatedTrue(Opcode: Opc) ? Hexagon::getFalsePredOpcode(Opcode: Opc)
4426 : Hexagon::getTruePredOpcode(Opcode: Opc);
4427 if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
4428 return InvPredOpcode;
4429
4430 llvm_unreachable("Unexpected predicated instruction");
4431}
4432
4433// Returns the max value that doesn't need to be extended.
4434int HexagonInstrInfo::getMaxValue(const MachineInstr &MI) const {
4435 const uint64_t F = MI.getDesc().TSFlags;
4436 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4437 & HexagonII::ExtentSignedMask;
4438 unsigned bits = (F >> HexagonII::ExtentBitsPos)
4439 & HexagonII::ExtentBitsMask;
4440
4441 if (isSigned) // if value is signed
4442 return ~(-1U << (bits - 1));
4443 else
4444 return ~(-1U << bits);
4445}
4446
4447
4448bool HexagonInstrInfo::isAddrModeWithOffset(const MachineInstr &MI) const {
4449 switch (MI.getOpcode()) {
4450 case Hexagon::L2_loadrbgp:
4451 case Hexagon::L2_loadrdgp:
4452 case Hexagon::L2_loadrhgp:
4453 case Hexagon::L2_loadrigp:
4454 case Hexagon::L2_loadrubgp:
4455 case Hexagon::L2_loadruhgp:
4456 case Hexagon::S2_storerbgp:
4457 case Hexagon::S2_storerbnewgp:
4458 case Hexagon::S2_storerhgp:
4459 case Hexagon::S2_storerhnewgp:
4460 case Hexagon::S2_storerigp:
4461 case Hexagon::S2_storerinewgp:
4462 case Hexagon::S2_storerdgp:
4463 case Hexagon::S2_storerfgp:
4464 return true;
4465 }
4466 const uint64_t F = MI.getDesc().TSFlags;
4467 unsigned addrMode =
4468 ((F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask);
4469 // Disallow any base+offset instruction. The assembler does not yet reorder
4470 // based up any zero offset instruction.
4471 return (addrMode == HexagonII::BaseRegOffset ||
4472 addrMode == HexagonII::BaseImmOffset ||
4473 addrMode == HexagonII::BaseLongOffset);
4474}
4475
4476bool HexagonInstrInfo::isPureSlot0(const MachineInstr &MI) const {
4477 // Workaround for the Global Scheduler. Sometimes, it creates
4478 // A4_ext as a Pseudo instruction and calls this function to see if
4479 // it can be added to an existing bundle. Since the instruction doesn't
4480 // belong to any BB yet, we can't use getUnits API.
4481 if (MI.getOpcode() == Hexagon::A4_ext)
4482 return false;
4483
4484 unsigned FuncUnits = getUnits(MI);
4485 return HexagonFUnits::isSlot0Only(units: FuncUnits);
4486}
4487
4488bool HexagonInstrInfo::isRestrictNoSlot1Store(const MachineInstr &MI) const {
4489 const uint64_t F = MI.getDesc().TSFlags;
4490 return ((F >> HexagonII::RestrictNoSlot1StorePos) &
4491 HexagonII::RestrictNoSlot1StoreMask);
4492}
4493
4494void HexagonInstrInfo::changeDuplexOpcode(MachineBasicBlock::instr_iterator MII,
4495 bool ToBigInstrs) const {
4496 int Opcode = -1;
4497 if (ToBigInstrs) { // To BigCore Instr.
4498 // Check if the instruction can form a Duplex.
4499 if (getDuplexCandidateGroup(MI: *MII))
4500 // Get the opcode marked "dup_*" tag.
4501 Opcode = getDuplexOpcode(MI: *MII, ForBigCore: ToBigInstrs);
4502 } else // To TinyCore Instr.
4503 Opcode = getDuplexOpcode(MI: *MII, ForBigCore: ToBigInstrs);
4504
4505 // Change the opcode of the instruction.
4506 if (Opcode >= 0)
4507 MII->setDesc(get(Opcode));
4508}
4509
4510// This function is used to translate instructions to facilitate generating
4511// Duplexes on TinyCore.
4512void HexagonInstrInfo::translateInstrsForDup(MachineFunction &MF,
4513 bool ToBigInstrs) const {
4514 for (auto &MB : MF)
4515 for (MachineBasicBlock::instr_iterator Instr = MB.instr_begin(),
4516 End = MB.instr_end();
4517 Instr != End; ++Instr)
4518 changeDuplexOpcode(MII: Instr, ToBigInstrs);
4519}
4520
4521// This is a specialized form of above function.
4522void HexagonInstrInfo::translateInstrsForDup(
4523 MachineBasicBlock::instr_iterator MII, bool ToBigInstrs) const {
4524 MachineBasicBlock *MBB = MII->getParent();
4525 while ((MII != MBB->instr_end()) && MII->isInsideBundle()) {
4526 changeDuplexOpcode(MII, ToBigInstrs);
4527 ++MII;
4528 }
4529}
4530
4531unsigned HexagonInstrInfo::getMemAccessSize(const MachineInstr &MI) const {
4532 using namespace HexagonII;
4533
4534 const uint64_t F = MI.getDesc().TSFlags;
4535 unsigned S = (F >> MemAccessSizePos) & MemAccesSizeMask;
4536 unsigned Size = getMemAccessSizeInBytes(S: MemAccessSize(S));
4537 if (Size != 0)
4538 return Size;
4539 // Y2_dcfetchbo is special
4540 if (MI.getOpcode() == Hexagon::Y2_dcfetchbo)
4541 return HexagonII::DoubleWordAccess;
4542
4543 // Handle vector access sizes.
4544 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4545 switch (S) {
4546 case HexagonII::HVXVectorAccess:
4547 return HRI.getSpillSize(RC: Hexagon::HvxVRRegClass);
4548 default:
4549 llvm_unreachable("Unexpected instruction");
4550 }
4551}
4552
4553// Returns the min value that doesn't need to be extended.
4554int HexagonInstrInfo::getMinValue(const MachineInstr &MI) const {
4555 const uint64_t F = MI.getDesc().TSFlags;
4556 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4557 & HexagonII::ExtentSignedMask;
4558 unsigned bits = (F >> HexagonII::ExtentBitsPos)
4559 & HexagonII::ExtentBitsMask;
4560
4561 if (isSigned) // if value is signed
4562 return -1U << (bits - 1);
4563 else
4564 return 0;
4565}
4566
4567// Returns opcode of the non-extended equivalent instruction.
4568short HexagonInstrInfo::getNonExtOpcode(const MachineInstr &MI) const {
4569 // Check if the instruction has a register form that uses register in place
4570 // of the extended operand, if so return that as the non-extended form.
4571 short NonExtOpcode = Hexagon::getRegForm(Opcode: MI.getOpcode());
4572 if (NonExtOpcode >= 0)
4573 return NonExtOpcode;
4574
4575 if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
4576 // Check addressing mode and retrieve non-ext equivalent instruction.
4577 switch (getAddrMode(MI)) {
4578 case HexagonII::Absolute:
4579 return Hexagon::changeAddrMode_abs_io(Opcode: MI.getOpcode());
4580 case HexagonII::BaseImmOffset:
4581 return Hexagon::changeAddrMode_io_rr(Opcode: MI.getOpcode());
4582 case HexagonII::BaseLongOffset:
4583 return Hexagon::changeAddrMode_ur_rr(Opcode: MI.getOpcode());
4584
4585 default:
4586 return -1;
4587 }
4588 }
4589 return -1;
4590}
4591
4592bool HexagonInstrInfo::getPredReg(ArrayRef<MachineOperand> Cond,
4593 Register &PredReg, unsigned &PredRegPos,
4594 RegState &PredRegFlags) const {
4595 if (Cond.empty())
4596 return false;
4597 assert(Cond.size() == 2);
4598 if (isNewValueJump(Opcode: Cond[0].getImm()) || Cond[1].isMBB()) {
4599 LLVM_DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
4600 return false;
4601 }
4602 PredReg = Cond[1].getReg();
4603 PredRegPos = 1;
4604 // See IfConversion.cpp why we add RegState::Implicit | RegState::Undef
4605 PredRegFlags = {};
4606 if (Cond[1].isImplicit())
4607 PredRegFlags = RegState::Implicit;
4608 if (Cond[1].isUndef())
4609 PredRegFlags |= RegState::Undef;
4610 return true;
4611}
4612
4613short HexagonInstrInfo::getPseudoInstrPair(const MachineInstr &MI) const {
4614 return Hexagon::getRealHWInstr(Opcode: MI.getOpcode(), inInstrType: Hexagon::InstrType_Pseudo);
4615}
4616
4617short HexagonInstrInfo::getRegForm(const MachineInstr &MI) const {
4618 return Hexagon::getRegForm(Opcode: MI.getOpcode());
4619}
4620
4621// Return the number of bytes required to encode the instruction.
4622// Hexagon instructions are fixed length, 4 bytes, unless they
4623// use a constant extender, which requires another 4 bytes.
4624// For debug instructions and prolog labels, return 0.
4625unsigned HexagonInstrInfo::getSize(const MachineInstr &MI) const {
4626 if (MI.isDebugInstr() || MI.isPosition())
4627 return 0;
4628
4629 unsigned Size = MI.getDesc().getSize();
4630 if (!Size)
4631 // Assume the default insn size in case it cannot be determined
4632 // for whatever reason.
4633 Size = HEXAGON_INSTR_SIZE;
4634
4635 if (isConstExtended(MI) || isExtended(MI))
4636 Size += HEXAGON_INSTR_SIZE;
4637
4638 // Try and compute number of instructions in asm.
4639 if (BranchRelaxAsmLarge && MI.getOpcode() == Hexagon::INLINEASM) {
4640 const MachineBasicBlock &MBB = *MI.getParent();
4641 const MachineFunction *MF = MBB.getParent();
4642 const MCAsmInfo &MAI = MF->getTarget().getMCAsmInfo();
4643
4644 // Count the number of register definitions to find the asm string.
4645 unsigned NumDefs = 0;
4646 for (; MI.getOperand(i: NumDefs).isReg() && MI.getOperand(i: NumDefs).isDef();
4647 ++NumDefs)
4648 assert(NumDefs != MI.getNumOperands()-2 && "No asm string?");
4649
4650 assert(MI.getOperand(NumDefs).isSymbol() && "No asm string?");
4651 // Disassemble the AsmStr and approximate number of instructions.
4652 const char *AsmStr = MI.getOperand(i: NumDefs).getSymbolName();
4653 Size = getInlineAsmLength(Str: AsmStr, MAI);
4654 }
4655
4656 return Size;
4657}
4658
4659uint64_t HexagonInstrInfo::getType(const MachineInstr &MI) const {
4660 const uint64_t F = MI.getDesc().TSFlags;
4661 return (F >> HexagonII::TypePos) & HexagonII::TypeMask;
4662}
4663
4664InstrStage::FuncUnits HexagonInstrInfo::getUnits(const MachineInstr &MI) const {
4665 const InstrItineraryData &II = *Subtarget.getInstrItineraryData();
4666 const InstrStage &IS = *II.beginStage(ItinClassIndx: MI.getDesc().getSchedClass());
4667
4668 return IS.getUnits();
4669}
4670
4671// Calculate size of the basic block without debug instructions.
4672unsigned HexagonInstrInfo::nonDbgBBSize(const MachineBasicBlock *BB) const {
4673 return nonDbgMICount(MIB: BB->instr_begin(), MIE: BB->instr_end());
4674}
4675
4676unsigned HexagonInstrInfo::nonDbgBundleSize(
4677 MachineBasicBlock::const_iterator BundleHead) const {
4678 assert(BundleHead->isBundle() && "Not a bundle header");
4679 auto MII = BundleHead.getInstrIterator();
4680 // Skip the bundle header.
4681 return nonDbgMICount(MIB: ++MII, MIE: getBundleEnd(I: BundleHead.getInstrIterator()));
4682}
4683
4684/// immediateExtend - Changes the instruction in place to one using an immediate
4685/// extender.
4686void HexagonInstrInfo::immediateExtend(MachineInstr &MI) const {
4687 assert((isExtendable(MI)||isConstExtended(MI)) &&
4688 "Instruction must be extendable");
4689 // Find which operand is extendable.
4690 short ExtOpNum = getCExtOpNum(MI);
4691 MachineOperand &MO = MI.getOperand(i: ExtOpNum);
4692 // This needs to be something we understand.
4693 assert((MO.isMBB() || MO.isImm()) &&
4694 "Branch with unknown extendable field type");
4695 // Mark given operand as extended.
4696 MO.addTargetFlag(F: HexagonII::HMOTF_ConstExtended);
4697}
4698
4699bool HexagonInstrInfo::invertAndChangeJumpTarget(
4700 MachineInstr &MI, MachineBasicBlock *NewTarget) const {
4701 LLVM_DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to "
4702 << printMBBReference(*NewTarget);
4703 MI.dump(););
4704 assert(MI.isBranch());
4705 unsigned NewOpcode = getInvertedPredicatedOpcode(Opc: MI.getOpcode());
4706 int TargetPos = MI.getNumOperands() - 1;
4707 // In general branch target is the last operand,
4708 // but some implicit defs added at the end might change it.
4709 while ((TargetPos > -1) && !MI.getOperand(i: TargetPos).isMBB())
4710 --TargetPos;
4711 assert((TargetPos >= 0) && MI.getOperand(TargetPos).isMBB());
4712 MI.getOperand(i: TargetPos).setMBB(NewTarget);
4713 if (EnableBranchPrediction && isPredicatedNew(MI)) {
4714 NewOpcode = reversePrediction(Opcode: NewOpcode);
4715 }
4716 MI.setDesc(get(Opcode: NewOpcode));
4717 return true;
4718}
4719
4720void HexagonInstrInfo::genAllInsnTimingClasses(MachineFunction &MF) const {
4721 /* +++ The code below is used to generate complete set of Hexagon Insn +++ */
4722 MachineFunction::iterator A = MF.begin();
4723 MachineBasicBlock &B = *A;
4724 MachineBasicBlock::iterator I = B.begin();
4725 DebugLoc DL = I->getDebugLoc();
4726 MachineInstr *NewMI;
4727
4728 for (unsigned insn = TargetOpcode::GENERIC_OP_END+1;
4729 insn < Hexagon::INSTRUCTION_LIST_END; ++insn) {
4730 NewMI = BuildMI(BB&: B, I, MIMD: DL, MCID: get(Opcode: insn));
4731 LLVM_DEBUG(dbgs() << "\n"
4732 << getName(NewMI->getOpcode())
4733 << " Class: " << NewMI->getDesc().getSchedClass());
4734 NewMI->eraseFromParent();
4735 }
4736 /* --- The code above is used to generate complete set of Hexagon Insn --- */
4737}
4738
4739// inverts the predication logic.
4740// p -> NotP
4741// NotP -> P
4742bool HexagonInstrInfo::reversePredSense(MachineInstr &MI) const {
4743 LLVM_DEBUG(dbgs() << "\nTrying to reverse pred. sense of:"; MI.dump());
4744 MI.setDesc(get(Opcode: getInvertedPredicatedOpcode(Opc: MI.getOpcode())));
4745 return true;
4746}
4747
4748// Reverse the branch prediction.
4749unsigned HexagonInstrInfo::reversePrediction(unsigned Opcode) const {
4750 int PredRevOpcode = -1;
4751 if (isPredictedTaken(Opcode))
4752 PredRevOpcode = Hexagon::notTakenBranchPrediction(Opcode);
4753 else
4754 PredRevOpcode = Hexagon::takenBranchPrediction(Opcode);
4755 assert(PredRevOpcode > 0);
4756 return PredRevOpcode;
4757}
4758
4759// TODO: Add more rigorous validation.
4760bool HexagonInstrInfo::validateBranchCond(const ArrayRef<MachineOperand> &Cond)
4761 const {
4762 return Cond.empty() || (Cond[0].isImm() && (Cond.size() != 1));
4763}
4764
4765void HexagonInstrInfo::
4766setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const {
4767 assert(MIB->isBundle());
4768 MachineOperand &Operand = MIB->getOperand(i: 0);
4769 if (Operand.isImm())
4770 Operand.setImm(Operand.getImm() | memShufDisabledMask);
4771 else
4772 MIB->addOperand(Op: MachineOperand::CreateImm(Val: memShufDisabledMask));
4773}
4774
4775bool HexagonInstrInfo::getBundleNoShuf(const MachineInstr &MIB) const {
4776 assert(MIB.isBundle());
4777 const MachineOperand &Operand = MIB.getOperand(i: 0);
4778 return (Operand.isImm() && (Operand.getImm() & memShufDisabledMask) != 0);
4779}
4780
4781bool HexagonInstrInfo::isQFPMul(const MachineInstr *MI) const {
4782 return (MI->getOpcode() == Hexagon::V6_vmpy_qf16_hf ||
4783 MI->getOpcode() == Hexagon::V6_vmpy_qf16_mix_hf ||
4784 MI->getOpcode() == Hexagon::V6_vmpy_qf32_hf ||
4785 MI->getOpcode() == Hexagon::V6_vmpy_qf32_mix_hf ||
4786 MI->getOpcode() == Hexagon::V6_vmpy_qf32_sf ||
4787 MI->getOpcode() == Hexagon::V6_vmpy_qf16_mix_hf ||
4788 MI->getOpcode() == Hexagon::V6_vmpy_qf16 ||
4789 MI->getOpcode() == Hexagon::V6_vmpy_qf32_mix_hf ||
4790 MI->getOpcode() == Hexagon::V6_vmpy_qf32_qf16 ||
4791 MI->getOpcode() == Hexagon::V6_vmpy_qf32);
4792}
4793
4794namespace llvm::HexagonII {
4795
4796static constexpr RegTypeInfo make(RegType Out, RegType In1 = RegType::Unknown,
4797 RegType In2 = RegType::Unknown,
4798 RegType In3 = RegType::Unknown) {
4799 RegTypeInfo I;
4800 I.Output = Out;
4801 I.Input1 = In1;
4802 I.Input2 = In2;
4803 I.Input3 = In3;
4804 return I;
4805}
4806
4807RegTypeInfo getRegTypeInfo(unsigned Opcode) {
4808 switch (Opcode) {
4809 default:
4810 return {};
4811
4812 case Hexagon::V6_vabs_qf16_hf:
4813 return make(Out: RegType::QF16);
4814 case Hexagon::V6_vabs_qf16_qf16:
4815 return make(Out: RegType::QF16, In1: RegType::QF16);
4816 case Hexagon::V6_vabs_qf32_qf32:
4817 return make(Out: RegType::QF32, In1: RegType::QF32);
4818 case Hexagon::V6_vabs_qf32_sf:
4819 return make(Out: RegType::QF32);
4820 case Hexagon::V6_vadd_hf:
4821 return make(Out: RegType::QF16);
4822 case Hexagon::V6_vadd_qf16:
4823 return make(Out: RegType::QF16, In1: RegType::QF16, In2: RegType::QF16);
4824 case Hexagon::V6_vadd_qf16_mix:
4825 return make(Out: RegType::QF16, In1: RegType::QF16);
4826 case Hexagon::V6_vadd_qf32:
4827 return make(Out: RegType::QF32, In1: RegType::QF32, In2: RegType::QF32);
4828 case Hexagon::V6_vadd_qf32_mix:
4829 return make(Out: RegType::QF32, In1: RegType::QF32);
4830 case Hexagon::V6_vadd_sf:
4831 return make(Out: RegType::QF32);
4832 case Hexagon::V6_vconv_bf_qf32:
4833 return make(Out: RegType::Unknown, In1: RegType::QF32);
4834 case Hexagon::V6_vconv_f8_qf16:
4835 return make(Out: RegType::Unknown, In1: RegType::QF16);
4836 case Hexagon::V6_vconv_hf_qf16:
4837 return make(Out: RegType::Unknown, In1: RegType::QF16);
4838 case Hexagon::V6_vconv_hf_qf32:
4839 return make(Out: RegType::Unknown, In1: RegType::QF32);
4840 case Hexagon::V6_vconv_qf16_f8:
4841 return make(Out: RegType::QF16);
4842 case Hexagon::V6_vconv_qf16_hf:
4843 return make(Out: RegType::QF16);
4844 case Hexagon::V6_vconv_qf16_qf16:
4845 return make(Out: RegType::QF16, In1: RegType::QF16);
4846 case Hexagon::V6_vconv_qf32_qf32:
4847 return make(Out: RegType::QF32, In1: RegType::QF32);
4848 case Hexagon::V6_vconv_qf32_sf:
4849 return make(Out: RegType::QF32);
4850 case Hexagon::V6_vconv_sf_qf32:
4851 return make(Out: RegType::Unknown, In1: RegType::QF32);
4852 case Hexagon::V6_vilog2_qf16:
4853 return make(Out: RegType::Unknown, In1: RegType::QF16);
4854 case Hexagon::V6_vilog2_qf32:
4855 return make(Out: RegType::Unknown, In1: RegType::QF32);
4856 case Hexagon::V6_vmpy_qf16:
4857 return make(Out: RegType::QF16, In1: RegType::QF16, In2: RegType::QF16);
4858 case Hexagon::V6_vmpy_qf16_hf:
4859 return make(Out: RegType::QF16);
4860 case Hexagon::V6_vmpy_qf16_mix_hf:
4861 return make(Out: RegType::QF16, In1: RegType::QF16);
4862 case Hexagon::V6_vmpy_qf32:
4863 return make(Out: RegType::QF32, In1: RegType::QF32, In2: RegType::QF32);
4864 case Hexagon::V6_vmpy_qf32_hf:
4865 return make(Out: RegType::QF32);
4866 case Hexagon::V6_vmpy_qf32_mix_hf:
4867 return make(Out: RegType::QF32, In1: RegType::QF16);
4868 case Hexagon::V6_vmpy_qf32_qf16:
4869 return make(Out: RegType::QF32, In1: RegType::QF16, In2: RegType::QF16);
4870 case Hexagon::V6_vmpy_qf32_sf:
4871 return make(Out: RegType::QF32);
4872 case Hexagon::V6_vmpy_rt_hf:
4873 return make(Out: RegType::QF16);
4874 case Hexagon::V6_vmpy_rt_qf16:
4875 return make(Out: RegType::QF16, In1: RegType::QF16);
4876 case Hexagon::V6_vmpy_rt_sf:
4877 return make(Out: RegType::QF32);
4878 case Hexagon::V6_vneg_qf16_hf:
4879 return make(Out: RegType::QF16);
4880 case Hexagon::V6_vneg_qf16_qf16:
4881 return make(Out: RegType::QF16, In1: RegType::QF16);
4882 case Hexagon::V6_vneg_qf32_qf32:
4883 return make(Out: RegType::QF32, In1: RegType::QF32);
4884 case Hexagon::V6_vneg_qf32_sf:
4885 return make(Out: RegType::QF32);
4886 case Hexagon::V6_vsub_hf:
4887 return make(Out: RegType::QF16);
4888 case Hexagon::V6_vsub_qf16:
4889 return make(Out: RegType::QF16, In1: RegType::QF16, In2: RegType::QF16);
4890 case Hexagon::V6_vsub_qf16_mix:
4891 return make(Out: RegType::QF16, In1: RegType::QF16);
4892 case Hexagon::V6_vsub_qf32:
4893 return make(Out: RegType::QF32, In1: RegType::QF32, In2: RegType::QF32);
4894 case Hexagon::V6_vsub_qf32_mix:
4895 return make(Out: RegType::QF32, In1: RegType::QF32);
4896 case Hexagon::V6_vsub_sf:
4897 return make(Out: RegType::QF32);
4898 case Hexagon::V6_vsub_sf_mix:
4899 return make(Out: RegType::QF32, In1: RegType::Unknown, In2: RegType::QF32);
4900 case Hexagon::V6_vsub_hf_mix:
4901 return make(Out: RegType::QF16, In1: RegType::Unknown, In2: RegType::QF16);
4902 }
4903}
4904
4905} // namespace llvm::HexagonII
4906
4907bool HexagonInstrInfo::usesQF32Operand(MachineInstr *MI, unsigned Index) const {
4908 auto Info = HexagonII::getRegTypeInfo(Opcode: MI->getOpcode());
4909 switch (Index) {
4910 case 1:
4911 return Info.Input1 == HexagonII::RegType::QF32;
4912 case 2:
4913 return Info.Input2 == HexagonII::RegType::QF32;
4914 case 3:
4915 return Info.Input3 == HexagonII::RegType::QF32;
4916 case 0:
4917 return Info.Input1 == HexagonII::RegType::QF32 ||
4918 Info.Input2 == HexagonII::RegType::QF32 ||
4919 Info.Input3 == HexagonII::RegType::QF32;
4920 default: // No instruction with more than 3 operands uses QF32.
4921 return false;
4922 }
4923 return false;
4924}
4925
4926bool HexagonInstrInfo::usesQF16Operand(MachineInstr *MI, unsigned Index) const {
4927 auto Info = HexagonII::getRegTypeInfo(Opcode: MI->getOpcode());
4928 switch (Index) {
4929 case 1:
4930 return Info.Input1 == HexagonII::RegType::QF16;
4931 case 2:
4932 return Info.Input2 == HexagonII::RegType::QF16;
4933 case 3:
4934 return Info.Input3 == HexagonII::RegType::QF16;
4935 case 0:
4936 return Info.Input1 == HexagonII::RegType::QF16 ||
4937 Info.Input2 == HexagonII::RegType::QF16 ||
4938 Info.Input3 == HexagonII::RegType::QF16;
4939 default: // No instruction with more than 3 operands uses QF16.
4940 return false;
4941 }
4942 return false;
4943}
4944
4945bool HexagonInstrInfo::usesQFOperand(MachineInstr *MI, unsigned Index) const {
4946 return usesQF32Operand(MI, Index) || usesQF16Operand(MI, Index);
4947}
4948
4949bool HexagonInstrInfo::isQFP32Instr(MachineInstr *MI) const {
4950 return HexagonII::getOpRegType(Opcode: MI->getOpcode()) == HexagonII::RegType::QF32;
4951}
4952
4953bool HexagonInstrInfo::isQFP16Instr(MachineInstr *MI) const {
4954 return HexagonII::getOpRegType(Opcode: MI->getOpcode()) == HexagonII::RegType::QF16;
4955}
4956
4957bool HexagonInstrInfo::isQFPInstr(MachineInstr *MI) const {
4958 return isQFP32Instr(MI) || isQFP16Instr(MI);
4959}
4960
4961// Return true if the function contains any qf-generating instructions.
4962bool HexagonInstrInfo::hasQFPInstrs(const MachineFunction &MF) const {
4963 for (const MachineBasicBlock &MBB : MF)
4964 for (const MachineInstr &MI : MBB)
4965 if (isQFPInstr(MI: const_cast<MachineInstr *>(&MI)))
4966 return true;
4967 return false;
4968}
4969
4970// Returns true if A appears before B within the same basic block.
4971bool HexagonInstrInfo::isMIBefore(const MachineInstr *A,
4972 const MachineInstr *B) const {
4973 if (!A || !B || A->getParent() != B->getParent())
4974 return false;
4975
4976 for (const MachineInstr &MI : *A->getParent()) {
4977 if (&MI == A)
4978 return true;
4979 if (&MI == B)
4980 return false;
4981 }
4982 return false;
4983}
4984
4985// Addressing mode relations.
4986short HexagonInstrInfo::changeAddrMode_abs_io(short Opc) const {
4987 return Opc >= 0 ? Hexagon::changeAddrMode_abs_io(Opcode: Opc) : Opc;
4988}
4989
4990short HexagonInstrInfo::changeAddrMode_io_abs(short Opc) const {
4991 return Opc >= 0 ? Hexagon::changeAddrMode_io_abs(Opcode: Opc) : Opc;
4992}
4993
4994short HexagonInstrInfo::changeAddrMode_io_pi(short Opc) const {
4995 return Opc >= 0 ? Hexagon::changeAddrMode_io_pi(Opcode: Opc) : Opc;
4996}
4997
4998short HexagonInstrInfo::changeAddrMode_io_rr(short Opc) const {
4999 return Opc >= 0 ? Hexagon::changeAddrMode_io_rr(Opcode: Opc) : Opc;
5000}
5001
5002short HexagonInstrInfo::changeAddrMode_pi_io(short Opc) const {
5003 return Opc >= 0 ? Hexagon::changeAddrMode_pi_io(Opcode: Opc) : Opc;
5004}
5005
5006short HexagonInstrInfo::changeAddrMode_rr_io(short Opc) const {
5007 return Opc >= 0 ? Hexagon::changeAddrMode_rr_io(Opcode: Opc) : Opc;
5008}
5009
5010short HexagonInstrInfo::changeAddrMode_rr_ur(short Opc) const {
5011 return Opc >= 0 ? Hexagon::changeAddrMode_rr_ur(Opcode: Opc) : Opc;
5012}
5013
5014short HexagonInstrInfo::changeAddrMode_ur_rr(short Opc) const {
5015 return Opc >= 0 ? Hexagon::changeAddrMode_ur_rr(Opcode: Opc) : Opc;
5016}
5017
5018MCInst HexagonInstrInfo::getNop() const {
5019 static const MCInst Nop = MCInstBuilder(Hexagon::A2_nop);
5020
5021 return MCInstBuilder(Hexagon::BUNDLE)
5022 .addImm(Val: 0)
5023 .addInst(Val: &Nop);
5024}
5025