1//===- HexagonInstrInfo.cpp - Hexagon Instruction Information -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Hexagon implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "HexagonInstrInfo.h"
14#include "HexagonFrameLowering.h"
15#include "HexagonHazardRecognizer.h"
16#include "HexagonRegisterInfo.h"
17#include "HexagonSubtarget.h"
18#include "llvm/ADT/ArrayRef.h"
19#include "llvm/ADT/SmallPtrSet.h"
20#include "llvm/ADT/SmallVector.h"
21#include "llvm/ADT/StringExtras.h"
22#include "llvm/ADT/StringRef.h"
23#include "llvm/CodeGen/DFAPacketizer.h"
24#include "llvm/CodeGen/LiveIntervals.h"
25#include "llvm/CodeGen/LivePhysRegs.h"
26#include "llvm/CodeGen/MachineBasicBlock.h"
27#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineInstr.h"
31#include "llvm/CodeGen/MachineInstrBuilder.h"
32#include "llvm/CodeGen/MachineInstrBundle.h"
33#include "llvm/CodeGen/MachineMemOperand.h"
34#include "llvm/CodeGen/MachineOperand.h"
35#include "llvm/CodeGen/MachineRegisterInfo.h"
36#include "llvm/CodeGen/ScheduleDAG.h"
37#include "llvm/CodeGen/TargetInstrInfo.h"
38#include "llvm/CodeGen/TargetOpcodes.h"
39#include "llvm/CodeGen/TargetRegisterInfo.h"
40#include "llvm/CodeGen/TargetSubtargetInfo.h"
41#include "llvm/CodeGenTypes/MachineValueType.h"
42#include "llvm/IR/DebugLoc.h"
43#include "llvm/IR/GlobalVariable.h"
44#include "llvm/MC/MCAsmInfo.h"
45#include "llvm/MC/MCInstBuilder.h"
46#include "llvm/MC/MCInstrDesc.h"
47#include "llvm/MC/MCInstrItineraries.h"
48#include "llvm/Support/BranchProbability.h"
49#include "llvm/Support/CommandLine.h"
50#include "llvm/Support/Debug.h"
51#include "llvm/Support/ErrorHandling.h"
52#include "llvm/Support/MathExtras.h"
53#include "llvm/Support/raw_ostream.h"
54#include "llvm/Target/TargetMachine.h"
55#include <cassert>
56#include <cstdint>
57#include <cstring>
58#include <iterator>
59#include <optional>
60#include <string>
61#include <utility>
62
63using namespace llvm;
64
65#define DEBUG_TYPE "hexagon-instrinfo"
66
67#define GET_INSTRINFO_CTOR_DTOR
68#define GET_INSTRMAP_INFO
69#include "HexagonDepTimingClasses.h"
70#include "HexagonGenDFAPacketizer.inc"
71#include "HexagonGenInstrInfo.inc"
72
73cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
74 cl::init(Val: false), cl::desc("Do not consider inline-asm a scheduling/"
75 "packetization boundary."));
76
77static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction",
78 cl::Hidden, cl::init(Val: true), cl::desc("Enable branch prediction"));
79
80static cl::opt<bool> DisableNVSchedule(
81 "disable-hexagon-nv-schedule", cl::Hidden,
82 cl::desc("Disable schedule adjustment for new value stores."));
83
84static cl::opt<bool> EnableTimingClassLatency(
85 "enable-timing-class-latency", cl::Hidden, cl::init(Val: false),
86 cl::desc("Enable timing class latency"));
87
88static cl::opt<bool> EnableALUForwarding(
89 "enable-alu-forwarding", cl::Hidden, cl::init(Val: true),
90 cl::desc("Enable vec alu forwarding"));
91
92static cl::opt<bool> EnableACCForwarding(
93 "enable-acc-forwarding", cl::Hidden, cl::init(Val: true),
94 cl::desc("Enable vec acc forwarding"));
95
96static cl::opt<bool> BranchRelaxAsmLarge("branch-relax-asm-large",
97 cl::init(Val: true), cl::Hidden,
98 cl::desc("branch relax asm"));
99
100static cl::opt<bool>
101 UseDFAHazardRec("dfa-hazard-rec", cl::init(Val: true), cl::Hidden,
102 cl::desc("Use the DFA based hazard recognizer."));
103
104/// Constants for Hexagon instructions.
105const int Hexagon_MEMW_OFFSET_MAX = 4095;
106const int Hexagon_MEMW_OFFSET_MIN = -4096;
107const int Hexagon_MEMD_OFFSET_MAX = 8191;
108const int Hexagon_MEMD_OFFSET_MIN = -8192;
109const int Hexagon_MEMH_OFFSET_MAX = 2047;
110const int Hexagon_MEMH_OFFSET_MIN = -2048;
111const int Hexagon_MEMB_OFFSET_MAX = 1023;
112const int Hexagon_MEMB_OFFSET_MIN = -1024;
113const int Hexagon_ADDI_OFFSET_MAX = 32767;
114const int Hexagon_ADDI_OFFSET_MIN = -32768;
115
116// Pin the vtable to this file.
117void HexagonInstrInfo::anchor() {}
118
119HexagonInstrInfo::HexagonInstrInfo(const HexagonSubtarget &ST)
120 : HexagonGenInstrInfo(ST, RegInfo, Hexagon::ADJCALLSTACKDOWN,
121 Hexagon::ADJCALLSTACKUP),
122 RegInfo(ST.getHwMode()), Subtarget(ST) {}
123
124namespace llvm {
125namespace HexagonFUnits {
126 bool isSlot0Only(unsigned units);
127}
128}
129
130static bool isIntRegForSubInst(Register Reg) {
131 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
132 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
133}
134
135static bool isDblRegForSubInst(Register Reg, const HexagonRegisterInfo &HRI) {
136 return isIntRegForSubInst(Reg: HRI.getSubReg(Reg, Idx: Hexagon::isub_lo)) &&
137 isIntRegForSubInst(Reg: HRI.getSubReg(Reg, Idx: Hexagon::isub_hi));
138}
139
140/// Calculate number of instructions excluding the debug instructions.
141static unsigned nonDbgMICount(MachineBasicBlock::const_instr_iterator MIB,
142 MachineBasicBlock::const_instr_iterator MIE) {
143 unsigned Count = 0;
144 for (; MIB != MIE; ++MIB) {
145 if (!MIB->isDebugInstr())
146 ++Count;
147 }
148 return Count;
149}
150
151// Check if the A2_tfrsi instruction is cheap or not. If the operand has
152// to be constant-extendend it is not cheap since it occupies two slots
153// in a packet.
154bool HexagonInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
155 // Enable the following steps only at Os/Oz
156 if (!(MI.getMF()->getFunction().hasOptSize()))
157 return MI.isAsCheapAsAMove();
158
159 if (MI.getOpcode() == Hexagon::A2_tfrsi) {
160 auto Op = MI.getOperand(i: 1);
161 // If the instruction has a global address as operand, it is not cheap
162 // since the operand will be constant extended.
163 if (Op.isGlobal())
164 return false;
165 // If the instruction has an operand of size > 16bits, its will be
166 // const-extended and hence, it is not cheap.
167 if (Op.isImm()) {
168 int64_t Imm = Op.getImm();
169 if (!isInt<16>(x: Imm))
170 return false;
171 }
172 }
173 return MI.isAsCheapAsAMove();
174}
175
176// Do not sink floating point instructions that updates USR register.
177// Example:
178// feclearexcept
179// F2_conv_w2sf
180// fetestexcept
181// MachineSink sinks F2_conv_w2sf and we are not able to catch exceptions.
182// TODO: On some of these floating point instructions, USR is marked as Use.
183// In reality, these instructions also Def the USR. If USR is marked as Def,
184// some of the assumptions in assembler packetization are broken.
185bool HexagonInstrInfo::shouldSink(const MachineInstr &MI) const {
186 // Assumption: A floating point instruction that reads the USR will write
187 // the USR as well.
188 if (isFloat(MI) && MI.hasRegisterImplicitUseOperand(Reg: Hexagon::USR))
189 return false;
190 return true;
191}
192
193/// Find the hardware loop instruction used to set-up the specified loop.
194/// On Hexagon, we have two instructions used to set-up the hardware loop
195/// (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
196/// to indicate the end of a loop.
197MachineInstr *HexagonInstrInfo::findLoopInstr(MachineBasicBlock *BB,
198 unsigned EndLoopOp, MachineBasicBlock *TargetBB,
199 SmallPtrSet<MachineBasicBlock *, 8> &Visited) const {
200 unsigned LOOPi;
201 unsigned LOOPr;
202 if (EndLoopOp == Hexagon::ENDLOOP0) {
203 LOOPi = Hexagon::J2_loop0i;
204 LOOPr = Hexagon::J2_loop0r;
205 } else { // EndLoopOp == Hexagon::EndLOOP1
206 LOOPi = Hexagon::J2_loop1i;
207 LOOPr = Hexagon::J2_loop1r;
208 }
209
210 // The loop set-up instruction will be in a predecessor block
211 for (MachineBasicBlock *PB : BB->predecessors()) {
212 // If this has been visited, already skip it.
213 if (!Visited.insert(Ptr: PB).second)
214 continue;
215 if (PB == BB)
216 continue;
217 for (MachineInstr &I : llvm::reverse(C: PB->instrs())) {
218 unsigned Opc = I.getOpcode();
219 if (Opc == LOOPi || Opc == LOOPr)
220 return &I;
221 // We've reached a different loop, which means the loop01 has been
222 // removed.
223 if (Opc == EndLoopOp && I.getOperand(i: 0).getMBB() != TargetBB)
224 return nullptr;
225 }
226 // Check the predecessors for the LOOP instruction.
227 if (MachineInstr *Loop = findLoopInstr(BB: PB, EndLoopOp, TargetBB, Visited))
228 return Loop;
229 }
230 return nullptr;
231}
232
233/// Gather register def/uses from MI.
234/// This treats possible (predicated) defs as actually happening ones
235/// (conservatively).
236static inline void parseOperands(const MachineInstr &MI,
237 SmallVectorImpl<Register> &Defs, SmallVectorImpl<Register> &Uses) {
238 Defs.clear();
239 Uses.clear();
240
241 for (const MachineOperand &MO : MI.operands()) {
242 if (!MO.isReg())
243 continue;
244
245 Register Reg = MO.getReg();
246 if (!Reg)
247 continue;
248
249 if (MO.isUse())
250 Uses.push_back(Elt: MO.getReg());
251
252 if (MO.isDef())
253 Defs.push_back(Elt: MO.getReg());
254 }
255}
256
257// Position dependent, so check twice for swap.
258static bool isDuplexPairMatch(unsigned Ga, unsigned Gb) {
259 switch (Ga) {
260 case HexagonII::HSIG_None:
261 default:
262 return false;
263 case HexagonII::HSIG_L1:
264 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
265 case HexagonII::HSIG_L2:
266 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
267 Gb == HexagonII::HSIG_A);
268 case HexagonII::HSIG_S1:
269 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
270 Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_A);
271 case HexagonII::HSIG_S2:
272 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
273 Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_S2 ||
274 Gb == HexagonII::HSIG_A);
275 case HexagonII::HSIG_A:
276 return (Gb == HexagonII::HSIG_A);
277 case HexagonII::HSIG_Compound:
278 return (Gb == HexagonII::HSIG_Compound);
279 }
280 return false;
281}
282
283/// isLoadFromStackSlot - If the specified machine instruction is a direct
284/// load from a stack slot, return the virtual or physical register number of
285/// the destination along with the FrameIndex of the loaded stack slot. If
286/// not, return 0. This predicate must return 0 if the instruction has
287/// any side effects other than loading from the stack slot.
288Register HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
289 int &FrameIndex) const {
290 switch (MI.getOpcode()) {
291 default:
292 break;
293 case Hexagon::L2_loadri_io:
294 case Hexagon::L2_loadrd_io:
295 case Hexagon::V6_vL32b_ai:
296 case Hexagon::V6_vL32b_nt_ai:
297 case Hexagon::V6_vL32Ub_ai:
298 case Hexagon::LDriw_pred:
299 case Hexagon::LDriw_ctr:
300 case Hexagon::PS_vloadrq_ai:
301 case Hexagon::PS_vloadrw_ai:
302 case Hexagon::PS_vloadrw_nt_ai: {
303 const MachineOperand OpFI = MI.getOperand(i: 1);
304 if (!OpFI.isFI())
305 return 0;
306 const MachineOperand OpOff = MI.getOperand(i: 2);
307 if (!OpOff.isImm() || OpOff.getImm() != 0)
308 return 0;
309 FrameIndex = OpFI.getIndex();
310 return MI.getOperand(i: 0).getReg();
311 }
312
313 case Hexagon::L2_ploadrit_io:
314 case Hexagon::L2_ploadrif_io:
315 case Hexagon::L2_ploadrdt_io:
316 case Hexagon::L2_ploadrdf_io: {
317 const MachineOperand OpFI = MI.getOperand(i: 2);
318 if (!OpFI.isFI())
319 return 0;
320 const MachineOperand OpOff = MI.getOperand(i: 3);
321 if (!OpOff.isImm() || OpOff.getImm() != 0)
322 return 0;
323 FrameIndex = OpFI.getIndex();
324 return MI.getOperand(i: 0).getReg();
325 }
326 }
327
328 return 0;
329}
330
331/// isStoreToStackSlot - If the specified machine instruction is a direct
332/// store to a stack slot, return the virtual or physical register number of
333/// the source reg along with the FrameIndex of the loaded stack slot. If
334/// not, return 0. This predicate must return 0 if the instruction has
335/// any side effects other than storing to the stack slot.
336Register HexagonInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
337 int &FrameIndex) const {
338 switch (MI.getOpcode()) {
339 default:
340 break;
341 case Hexagon::S2_storerb_io:
342 case Hexagon::S2_storerh_io:
343 case Hexagon::S2_storeri_io:
344 case Hexagon::S2_storerd_io:
345 case Hexagon::V6_vS32b_ai:
346 case Hexagon::V6_vS32Ub_ai:
347 case Hexagon::STriw_pred:
348 case Hexagon::STriw_ctr:
349 case Hexagon::PS_vstorerq_ai:
350 case Hexagon::PS_vstorerw_ai: {
351 const MachineOperand &OpFI = MI.getOperand(i: 0);
352 if (!OpFI.isFI())
353 return 0;
354 const MachineOperand &OpOff = MI.getOperand(i: 1);
355 if (!OpOff.isImm() || OpOff.getImm() != 0)
356 return 0;
357 FrameIndex = OpFI.getIndex();
358 return MI.getOperand(i: 2).getReg();
359 }
360
361 case Hexagon::S2_pstorerbt_io:
362 case Hexagon::S2_pstorerbf_io:
363 case Hexagon::S2_pstorerht_io:
364 case Hexagon::S2_pstorerhf_io:
365 case Hexagon::S2_pstorerit_io:
366 case Hexagon::S2_pstorerif_io:
367 case Hexagon::S2_pstorerdt_io:
368 case Hexagon::S2_pstorerdf_io: {
369 const MachineOperand &OpFI = MI.getOperand(i: 1);
370 if (!OpFI.isFI())
371 return 0;
372 const MachineOperand &OpOff = MI.getOperand(i: 2);
373 if (!OpOff.isImm() || OpOff.getImm() != 0)
374 return 0;
375 FrameIndex = OpFI.getIndex();
376 return MI.getOperand(i: 3).getReg();
377 }
378 }
379
380 return 0;
381}
382
383/// This function checks if the instruction or bundle of instructions
384/// has load from stack slot and returns frameindex and machine memory
385/// operand of that instruction if true.
386bool HexagonInstrInfo::hasLoadFromStackSlot(
387 const MachineInstr &MI,
388 SmallVectorImpl<const MachineMemOperand *> &Accesses) const {
389 if (MI.isBundle()) {
390 const MachineBasicBlock *MBB = MI.getParent();
391 MachineBasicBlock::const_instr_iterator MII = MI.getIterator();
392 for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
393 if (TargetInstrInfo::hasLoadFromStackSlot(MI: *MII, Accesses))
394 return true;
395 return false;
396 }
397
398 return TargetInstrInfo::hasLoadFromStackSlot(MI, Accesses);
399}
400
401/// This function checks if the instruction or bundle of instructions
402/// has store to stack slot and returns frameindex and machine memory
403/// operand of that instruction if true.
404bool HexagonInstrInfo::hasStoreToStackSlot(
405 const MachineInstr &MI,
406 SmallVectorImpl<const MachineMemOperand *> &Accesses) const {
407 if (MI.isBundle()) {
408 const MachineBasicBlock *MBB = MI.getParent();
409 MachineBasicBlock::const_instr_iterator MII = MI.getIterator();
410 for (++MII; MII != MBB->instr_end() && MII->isInsideBundle(); ++MII)
411 if (TargetInstrInfo::hasStoreToStackSlot(MI: *MII, Accesses))
412 return true;
413 return false;
414 }
415
416 return TargetInstrInfo::hasStoreToStackSlot(MI, Accesses);
417}
418
419/// This function can analyze one/two way branching only and should (mostly) be
420/// called by target independent side.
421/// First entry is always the opcode of the branching instruction, except when
422/// the Cond vector is supposed to be empty, e.g., when analyzeBranch fails, a
423/// BB with only unconditional jump. Subsequent entries depend upon the opcode,
424/// e.g. Jump_c p will have
425/// Cond[0] = Jump_c
426/// Cond[1] = p
427/// HW-loop ENDLOOP:
428/// Cond[0] = ENDLOOP
429/// Cond[1] = MBB
430/// New value jump:
431/// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
432/// Cond[1] = R
433/// Cond[2] = Imm
434bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
435 MachineBasicBlock *&TBB,
436 MachineBasicBlock *&FBB,
437 SmallVectorImpl<MachineOperand> &Cond,
438 bool AllowModify) const {
439 TBB = nullptr;
440 FBB = nullptr;
441 Cond.clear();
442
443 // If the block has no terminators, it just falls into the block after it.
444 MachineBasicBlock::instr_iterator I = MBB.instr_end();
445 if (I == MBB.instr_begin())
446 return false;
447
448 // A basic block may looks like this:
449 //
450 // [ insn
451 // EH_LABEL
452 // insn
453 // insn
454 // insn
455 // EH_LABEL
456 // insn ]
457 //
458 // It has two succs but does not have a terminator
459 // Don't know how to handle it.
460 do {
461 --I;
462 if (I->isEHLabel())
463 // Don't analyze EH branches.
464 return true;
465 } while (I != MBB.instr_begin());
466
467 I = MBB.instr_end();
468 --I;
469
470 while (I->isDebugInstr()) {
471 if (I == MBB.instr_begin())
472 return false;
473 --I;
474 }
475
476 bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
477 I->getOperand(i: 0).isMBB();
478 // Delete the J2_jump if it's equivalent to a fall-through.
479 if (AllowModify && JumpToBlock &&
480 MBB.isLayoutSuccessor(MBB: I->getOperand(i: 0).getMBB())) {
481 LLVM_DEBUG(dbgs() << "\nErasing the jump to successor block\n";);
482 I->eraseFromParent();
483 I = MBB.instr_end();
484 if (I == MBB.instr_begin())
485 return false;
486 --I;
487 }
488 if (!isUnpredicatedTerminator(MI: *I))
489 return false;
490
491 // Get the last instruction in the block.
492 MachineInstr *LastInst = &*I;
493 MachineInstr *SecondLastInst = nullptr;
494 // Find one more terminator if present.
495 while (true) {
496 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(MI: *I)) {
497 if (!SecondLastInst)
498 SecondLastInst = &*I;
499 else
500 // This is a third branch.
501 return true;
502 }
503 if (I == MBB.instr_begin())
504 break;
505 --I;
506 }
507
508 int LastOpcode = LastInst->getOpcode();
509 int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
510 // If the branch target is not a basic block, it could be a tail call.
511 // (It is, if the target is a function.)
512 if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(i: 0).isMBB())
513 return true;
514 if (SecLastOpcode == Hexagon::J2_jump &&
515 !SecondLastInst->getOperand(i: 0).isMBB())
516 return true;
517
518 bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(Opcode: LastOpcode);
519 bool LastOpcodeHasNVJump = isNewValueJump(MI: *LastInst);
520
521 if (LastOpcodeHasJMP_c && !LastInst->getOperand(i: 1).isMBB())
522 return true;
523
524 // If there is only one terminator instruction, process it.
525 if (LastInst && !SecondLastInst) {
526 if (LastOpcode == Hexagon::J2_jump) {
527 TBB = LastInst->getOperand(i: 0).getMBB();
528 return false;
529 }
530 if (isEndLoopN(Opcode: LastOpcode)) {
531 TBB = LastInst->getOperand(i: 0).getMBB();
532 Cond.push_back(Elt: MachineOperand::CreateImm(Val: LastInst->getOpcode()));
533 Cond.push_back(Elt: LastInst->getOperand(i: 0));
534 return false;
535 }
536 if (LastOpcodeHasJMP_c) {
537 TBB = LastInst->getOperand(i: 1).getMBB();
538 Cond.push_back(Elt: MachineOperand::CreateImm(Val: LastInst->getOpcode()));
539 Cond.push_back(Elt: LastInst->getOperand(i: 0));
540 return false;
541 }
542 // Only supporting rr/ri versions of new-value jumps.
543 if (LastOpcodeHasNVJump && (LastInst->getNumExplicitOperands() == 3)) {
544 TBB = LastInst->getOperand(i: 2).getMBB();
545 Cond.push_back(Elt: MachineOperand::CreateImm(Val: LastInst->getOpcode()));
546 Cond.push_back(Elt: LastInst->getOperand(i: 0));
547 Cond.push_back(Elt: LastInst->getOperand(i: 1));
548 return false;
549 }
550 LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
551 << " with one jump\n";);
552 // Otherwise, don't know what this is.
553 return true;
554 }
555
556 bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(Opcode: SecLastOpcode);
557 bool SecLastOpcodeHasNVJump = isNewValueJump(MI: *SecondLastInst);
558 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
559 if (!SecondLastInst->getOperand(i: 1).isMBB())
560 return true;
561 TBB = SecondLastInst->getOperand(i: 1).getMBB();
562 Cond.push_back(Elt: MachineOperand::CreateImm(Val: SecondLastInst->getOpcode()));
563 Cond.push_back(Elt: SecondLastInst->getOperand(i: 0));
564 FBB = LastInst->getOperand(i: 0).getMBB();
565 return false;
566 }
567
568 // Only supporting rr/ri versions of new-value jumps.
569 if (SecLastOpcodeHasNVJump &&
570 (SecondLastInst->getNumExplicitOperands() == 3) &&
571 (LastOpcode == Hexagon::J2_jump)) {
572 TBB = SecondLastInst->getOperand(i: 2).getMBB();
573 Cond.push_back(Elt: MachineOperand::CreateImm(Val: SecondLastInst->getOpcode()));
574 Cond.push_back(Elt: SecondLastInst->getOperand(i: 0));
575 Cond.push_back(Elt: SecondLastInst->getOperand(i: 1));
576 FBB = LastInst->getOperand(i: 0).getMBB();
577 return false;
578 }
579
580 // If the block ends with two Hexagon:JMPs, handle it. The second one is not
581 // executed, so remove it.
582 if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
583 TBB = SecondLastInst->getOperand(i: 0).getMBB();
584 I = LastInst->getIterator();
585 if (AllowModify)
586 I->eraseFromParent();
587 return false;
588 }
589
590 // If the block ends with an ENDLOOP, and J2_jump, handle it.
591 if (isEndLoopN(Opcode: SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
592 TBB = SecondLastInst->getOperand(i: 0).getMBB();
593 Cond.push_back(Elt: MachineOperand::CreateImm(Val: SecondLastInst->getOpcode()));
594 Cond.push_back(Elt: SecondLastInst->getOperand(i: 0));
595 FBB = LastInst->getOperand(i: 0).getMBB();
596 return false;
597 }
598 LLVM_DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
599 << " with two jumps";);
600 // Otherwise, can't handle this.
601 return true;
602}
603
604unsigned HexagonInstrInfo::removeBranch(MachineBasicBlock &MBB,
605 int *BytesRemoved) const {
606 assert(!BytesRemoved && "code size not handled");
607
608 LLVM_DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB));
609 MachineBasicBlock::iterator I = MBB.end();
610 unsigned Count = 0;
611 while (I != MBB.begin()) {
612 --I;
613 if (I->isDebugInstr())
614 continue;
615 // Only removing branches from end of MBB.
616 if (!I->isBranch())
617 return Count;
618 if (Count && (I->getOpcode() == Hexagon::J2_jump))
619 llvm_unreachable("Malformed basic block: unconditional branch not last");
620 MBB.erase(I: &MBB.back());
621 I = MBB.end();
622 ++Count;
623 }
624 return Count;
625}
626
627unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB,
628 MachineBasicBlock *TBB,
629 MachineBasicBlock *FBB,
630 ArrayRef<MachineOperand> Cond,
631 const DebugLoc &DL,
632 int *BytesAdded) const {
633 unsigned BOpc = Hexagon::J2_jump;
634 unsigned BccOpc = Hexagon::J2_jumpt;
635 assert(validateBranchCond(Cond) && "Invalid branching condition");
636 assert(TBB && "insertBranch must not be told to insert a fallthrough");
637 assert(!BytesAdded && "code size not handled");
638
639 // Check if reverseBranchCondition has asked to reverse this branch
640 // If we want to reverse the branch an odd number of times, we want
641 // J2_jumpf.
642 if (!Cond.empty() && Cond[0].isImm())
643 BccOpc = Cond[0].getImm();
644
645 if (!FBB) {
646 if (Cond.empty()) {
647 // Due to a bug in TailMerging/CFG Optimization, we need to add a
648 // special case handling of a predicated jump followed by an
649 // unconditional jump. If not, Tail Merging and CFG Optimization go
650 // into an infinite loop.
651 MachineBasicBlock *NewTBB, *NewFBB;
652 SmallVector<MachineOperand, 4> Cond;
653 auto Term = MBB.getFirstTerminator();
654 if (Term != MBB.end() && isPredicated(MI: *Term) &&
655 !analyzeBranch(MBB, TBB&: NewTBB, FBB&: NewFBB, Cond, AllowModify: false) &&
656 MachineFunction::iterator(NewTBB) == ++MBB.getIterator()) {
657 reverseBranchCondition(Cond);
658 removeBranch(MBB);
659 return insertBranch(MBB, TBB, FBB: nullptr, Cond, DL);
660 }
661 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: BOpc)).addMBB(MBB: TBB);
662 } else if (isEndLoopN(Opcode: Cond[0].getImm())) {
663 int EndLoopOp = Cond[0].getImm();
664 assert(Cond[1].isMBB());
665 // Since we're adding an ENDLOOP, there better be a LOOP instruction.
666 // Check for it, and change the BB target if needed.
667 SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
668 MachineInstr *Loop = findLoopInstr(BB: TBB, EndLoopOp, TargetBB: Cond[1].getMBB(),
669 Visited&: VisitedBBs);
670 assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
671 Loop->getOperand(i: 0).setMBB(TBB);
672 // Add the ENDLOOP after the finding the LOOP0.
673 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: EndLoopOp)).addMBB(MBB: TBB);
674 } else if (isNewValueJump(Opcode: Cond[0].getImm())) {
675 assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump");
676 // New value jump
677 // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
678 // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
679 RegState Flags1 = getUndefRegState(B: Cond[1].isUndef());
680 LLVM_DEBUG(dbgs() << "\nInserting NVJump for "
681 << printMBBReference(MBB););
682 if (Cond[2].isReg()) {
683 RegState Flags2 = getUndefRegState(B: Cond[2].isUndef());
684 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: BccOpc)).addReg(RegNo: Cond[1].getReg(), Flags: Flags1).
685 addReg(RegNo: Cond[2].getReg(), Flags: Flags2).addMBB(MBB: TBB);
686 } else if(Cond[2].isImm()) {
687 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: BccOpc)).addReg(RegNo: Cond[1].getReg(), Flags: Flags1).
688 addImm(Val: Cond[2].getImm()).addMBB(MBB: TBB);
689 } else
690 llvm_unreachable("Invalid condition for branching");
691 } else {
692 assert((Cond.size() == 2) && "Malformed cond vector");
693 const MachineOperand &RO = Cond[1];
694 RegState Flags = getUndefRegState(B: RO.isUndef());
695 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: BccOpc)).addReg(RegNo: RO.getReg(), Flags).addMBB(MBB: TBB);
696 }
697 return 1;
698 }
699 assert((!Cond.empty()) &&
700 "Cond. cannot be empty when multiple branchings are required");
701 assert((!isNewValueJump(Cond[0].getImm())) &&
702 "NV-jump cannot be inserted with another branch");
703 // Special case for hardware loops. The condition is a basic block.
704 if (isEndLoopN(Opcode: Cond[0].getImm())) {
705 int EndLoopOp = Cond[0].getImm();
706 assert(Cond[1].isMBB());
707 // Since we're adding an ENDLOOP, there better be a LOOP instruction.
708 // Check for it, and change the BB target if needed.
709 SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
710 MachineInstr *Loop = findLoopInstr(BB: TBB, EndLoopOp, TargetBB: Cond[1].getMBB(),
711 Visited&: VisitedBBs);
712 assert(Loop != nullptr && "Inserting an ENDLOOP without a LOOP");
713 Loop->getOperand(i: 0).setMBB(TBB);
714 // Add the ENDLOOP after the finding the LOOP0.
715 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: EndLoopOp)).addMBB(MBB: TBB);
716 } else {
717 const MachineOperand &RO = Cond[1];
718 RegState Flags = getUndefRegState(B: RO.isUndef());
719 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: BccOpc)).addReg(RegNo: RO.getReg(), Flags).addMBB(MBB: TBB);
720 }
721 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: BOpc)).addMBB(MBB: FBB);
722
723 return 2;
724}
725
726namespace {
727class HexagonPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
728 MachineInstr *Loop, *EndLoop;
729 MachineFunction *MF;
730 const HexagonInstrInfo *TII;
731 int64_t TripCount;
732 Register LoopCount;
733 DebugLoc DL;
734
735public:
736 HexagonPipelinerLoopInfo(MachineInstr *Loop, MachineInstr *EndLoop)
737 : Loop(Loop), EndLoop(EndLoop), MF(Loop->getParent()->getParent()),
738 TII(MF->getSubtarget<HexagonSubtarget>().getInstrInfo()),
739 DL(Loop->getDebugLoc()) {
740 // Inspect the Loop instruction up-front, as it may be deleted when we call
741 // createTripCountGreaterCondition.
742 TripCount = Loop->getOpcode() == Hexagon::J2_loop0r
743 ? -1
744 : Loop->getOperand(i: 1).getImm();
745 if (TripCount == -1)
746 LoopCount = Loop->getOperand(i: 1).getReg();
747 }
748
749 bool shouldIgnoreForPipelining(const MachineInstr *MI) const override {
750 // Only ignore the terminator.
751 return MI == EndLoop;
752 }
753
754 std::optional<bool> createTripCountGreaterCondition(
755 int TC, MachineBasicBlock &MBB,
756 SmallVectorImpl<MachineOperand> &Cond) override {
757 if (TripCount == -1) {
758 // Check if we're done with the loop.
759 Register Done = TII->createVR(MF, VT: MVT::i1);
760 MachineInstr *NewCmp = BuildMI(BB: &MBB, MIMD: DL,
761 MCID: TII->get(Opcode: Hexagon::C2_cmpgtui), DestReg: Done)
762 .addReg(RegNo: LoopCount)
763 .addImm(Val: TC);
764 Cond.push_back(Elt: MachineOperand::CreateImm(Val: Hexagon::J2_jumpf));
765 Cond.push_back(Elt: NewCmp->getOperand(i: 0));
766 return {};
767 }
768
769 return TripCount > TC;
770 }
771
772 void setPreheader(MachineBasicBlock *NewPreheader) override {
773 NewPreheader->splice(Where: NewPreheader->getFirstTerminator(), Other: Loop->getParent(),
774 From: Loop);
775 }
776
777 void adjustTripCount(int TripCountAdjust) override {
778 // If the loop trip count is a compile-time value, then just change the
779 // value.
780 if (Loop->getOpcode() == Hexagon::J2_loop0i ||
781 Loop->getOpcode() == Hexagon::J2_loop1i) {
782 int64_t TripCount = Loop->getOperand(i: 1).getImm() + TripCountAdjust;
783 assert(TripCount > 0 && "Can't create an empty or negative loop!");
784 Loop->getOperand(i: 1).setImm(TripCount);
785 return;
786 }
787
788 // The loop trip count is a run-time value. We generate code to subtract
789 // one from the trip count, and update the loop instruction.
790 Register LoopCount = Loop->getOperand(i: 1).getReg();
791 Register NewLoopCount = TII->createVR(MF, VT: MVT::i32);
792 BuildMI(BB&: *Loop->getParent(), I: Loop, MIMD: Loop->getDebugLoc(),
793 MCID: TII->get(Opcode: Hexagon::A2_addi), DestReg: NewLoopCount)
794 .addReg(RegNo: LoopCount)
795 .addImm(Val: TripCountAdjust);
796 Loop->getOperand(i: 1).setReg(NewLoopCount);
797 }
798
799 void disposed(LiveIntervals *LIS) override {
800 if (LIS)
801 LIS->RemoveMachineInstrFromMaps(MI&: *Loop);
802 Loop->eraseFromParent();
803 }
804};
805} // namespace
806
807std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
808HexagonInstrInfo::analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const {
809 // We really "analyze" only hardware loops right now.
810 MachineBasicBlock::iterator I = LoopBB->getFirstTerminator();
811
812 if (I != LoopBB->end() && isEndLoopN(Opcode: I->getOpcode())) {
813 SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
814 MachineInstr *LoopInst = findLoopInstr(
815 BB: LoopBB, EndLoopOp: I->getOpcode(), TargetBB: I->getOperand(i: 0).getMBB(), Visited&: VisitedBBs);
816 if (LoopInst)
817 return std::make_unique<HexagonPipelinerLoopInfo>(args&: LoopInst, args: &*I);
818 }
819 return nullptr;
820}
821
822bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
823 unsigned NumCycles, unsigned ExtraPredCycles,
824 BranchProbability Probability) const {
825 return nonDbgBBSize(BB: &MBB) <= 3;
826}
827
828bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
829 unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB,
830 unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability)
831 const {
832 return nonDbgBBSize(BB: &TMBB) <= 3 && nonDbgBBSize(BB: &FMBB) <= 3;
833}
834
835bool HexagonInstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
836 unsigned NumInstrs, BranchProbability Probability) const {
837 return NumInstrs <= 4;
838}
839
840static void getLiveInRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
841 SmallVector<std::pair<MCPhysReg, const MachineOperand*>,2> Clobbers;
842 const MachineBasicBlock &B = *MI.getParent();
843 Regs.addLiveIns(MBB: B);
844 auto E = MachineBasicBlock::const_iterator(MI.getIterator());
845 for (auto I = B.begin(); I != E; ++I) {
846 Clobbers.clear();
847 Regs.stepForward(MI: *I, Clobbers);
848 }
849}
850
851static void getLiveOutRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) {
852 const MachineBasicBlock &B = *MI.getParent();
853 Regs.addLiveOuts(MBB: B);
854 auto E = ++MachineBasicBlock::const_iterator(MI.getIterator()).getReverse();
855 for (auto I = B.rbegin(); I != E; ++I)
856 Regs.stepBackward(MI: *I);
857}
858
859void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
860 MachineBasicBlock::iterator I,
861 const DebugLoc &DL, Register DestReg,
862 Register SrcReg, bool KillSrc,
863 bool RenamableDest,
864 bool RenamableSrc) const {
865 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
866 RegState KillFlag = getKillRegState(B: KillSrc);
867
868 if (Hexagon::IntRegsRegClass.contains(Reg1: SrcReg, Reg2: DestReg)) {
869 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::A2_tfr), DestReg)
870 .addReg(RegNo: SrcReg, Flags: KillFlag);
871 return;
872 }
873 if (Hexagon::DoubleRegsRegClass.contains(Reg1: SrcReg, Reg2: DestReg)) {
874 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::A2_tfrp), DestReg)
875 .addReg(RegNo: SrcReg, Flags: KillFlag);
876 return;
877 }
878 if (Hexagon::PredRegsRegClass.contains(Reg1: SrcReg, Reg2: DestReg)) {
879 // Map Pd = Ps to Pd = or(Ps, Ps).
880 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::C2_or), DestReg)
881 .addReg(RegNo: SrcReg).addReg(RegNo: SrcReg, Flags: KillFlag);
882 return;
883 }
884 if (Hexagon::CtrRegsRegClass.contains(Reg: DestReg) &&
885 Hexagon::IntRegsRegClass.contains(Reg: SrcReg)) {
886 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::A2_tfrrcr), DestReg)
887 .addReg(RegNo: SrcReg, Flags: KillFlag);
888 return;
889 }
890 if (Hexagon::IntRegsRegClass.contains(Reg: DestReg) &&
891 Hexagon::CtrRegsRegClass.contains(Reg: SrcReg)) {
892 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::A2_tfrcrr), DestReg)
893 .addReg(RegNo: SrcReg, Flags: KillFlag);
894 return;
895 }
896 if (Hexagon::ModRegsRegClass.contains(Reg: DestReg) &&
897 Hexagon::IntRegsRegClass.contains(Reg: SrcReg)) {
898 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::A2_tfrrcr), DestReg)
899 .addReg(RegNo: SrcReg, Flags: KillFlag);
900 return;
901 }
902 if (Hexagon::PredRegsRegClass.contains(Reg: SrcReg) &&
903 Hexagon::IntRegsRegClass.contains(Reg: DestReg)) {
904 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::C2_tfrpr), DestReg)
905 .addReg(RegNo: SrcReg, Flags: KillFlag);
906 return;
907 }
908 if (Hexagon::IntRegsRegClass.contains(Reg: SrcReg) &&
909 Hexagon::PredRegsRegClass.contains(Reg: DestReg)) {
910 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::C2_tfrrp), DestReg)
911 .addReg(RegNo: SrcReg, Flags: KillFlag);
912 return;
913 }
914 if (Hexagon::PredRegsRegClass.contains(Reg: SrcReg) &&
915 Hexagon::IntRegsRegClass.contains(Reg: DestReg)) {
916 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::C2_tfrpr), DestReg)
917 .addReg(RegNo: SrcReg, Flags: KillFlag);
918 return;
919 }
920 if (Hexagon::HvxVRRegClass.contains(Reg1: SrcReg, Reg2: DestReg)) {
921 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vassign), DestReg).
922 addReg(RegNo: SrcReg, Flags: KillFlag);
923 return;
924 }
925 if (Hexagon::HvxWRRegClass.contains(Reg1: SrcReg, Reg2: DestReg)) {
926 LivePhysRegs LiveAtMI(HRI);
927 getLiveInRegsAt(Regs&: LiveAtMI, MI: *I);
928 Register SrcLo = HRI.getSubReg(Reg: SrcReg, Idx: Hexagon::vsub_lo);
929 Register SrcHi = HRI.getSubReg(Reg: SrcReg, Idx: Hexagon::vsub_hi);
930 RegState UndefLo = getUndefRegState(B: !LiveAtMI.contains(Reg: SrcLo));
931 RegState UndefHi = getUndefRegState(B: !LiveAtMI.contains(Reg: SrcHi));
932 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vcombine), DestReg)
933 .addReg(RegNo: SrcHi, Flags: KillFlag | UndefHi)
934 .addReg(RegNo: SrcLo, Flags: KillFlag | UndefLo);
935 return;
936 }
937 if (Hexagon::HvxQRRegClass.contains(Reg1: SrcReg, Reg2: DestReg)) {
938 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::V6_pred_and), DestReg)
939 .addReg(RegNo: SrcReg)
940 .addReg(RegNo: SrcReg, Flags: KillFlag);
941 return;
942 }
943 if (Hexagon::HvxQRRegClass.contains(Reg: SrcReg) &&
944 Hexagon::HvxVRRegClass.contains(Reg: DestReg)) {
945 llvm_unreachable("Unimplemented pred to vec");
946 return;
947 }
948 if (Hexagon::HvxQRRegClass.contains(Reg: DestReg) &&
949 Hexagon::HvxVRRegClass.contains(Reg: SrcReg)) {
950 llvm_unreachable("Unimplemented vec to pred");
951 return;
952 }
953
954#ifndef NDEBUG
955 // Show the invalid registers to ease debugging.
956 dbgs() << "Invalid registers for copy in " << printMBBReference(MBB) << ": "
957 << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n';
958#endif
959 llvm_unreachable("Unimplemented");
960}
961
962void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
963 MachineBasicBlock::iterator I,
964 Register SrcReg, bool isKill, int FI,
965 const TargetRegisterClass *RC,
966 Register VReg,
967 MachineInstr::MIFlag Flags) const {
968 DebugLoc DL = MBB.findDebugLoc(MBBI: I);
969 MachineFunction &MF = *MBB.getParent();
970 MachineFrameInfo &MFI = MF.getFrameInfo();
971 RegState KillFlag = getKillRegState(B: isKill);
972
973 MachineMemOperand *MMO = MF.getMachineMemOperand(
974 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI), F: MachineMemOperand::MOStore,
975 Size: MFI.getObjectSize(ObjectIdx: FI), BaseAlignment: MFI.getObjectAlign(ObjectIdx: FI));
976
977 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
978 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::S2_storeri_io))
979 .addFrameIndex(Idx: FI).addImm(Val: 0)
980 .addReg(RegNo: SrcReg, Flags: KillFlag).addMemOperand(MMO);
981 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
982 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::S2_storerd_io))
983 .addFrameIndex(Idx: FI).addImm(Val: 0)
984 .addReg(RegNo: SrcReg, Flags: KillFlag).addMemOperand(MMO);
985 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
986 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::STriw_pred))
987 .addFrameIndex(Idx: FI).addImm(Val: 0)
988 .addReg(RegNo: SrcReg, Flags: KillFlag).addMemOperand(MMO);
989 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
990 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::STriw_ctr))
991 .addFrameIndex(Idx: FI).addImm(Val: 0)
992 .addReg(RegNo: SrcReg, Flags: KillFlag).addMemOperand(MMO);
993 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
994 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::PS_vstorerq_ai))
995 .addFrameIndex(Idx: FI).addImm(Val: 0)
996 .addReg(RegNo: SrcReg, Flags: KillFlag).addMemOperand(MMO);
997 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
998 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::PS_vstorerv_ai))
999 .addFrameIndex(Idx: FI).addImm(Val: 0)
1000 .addReg(RegNo: SrcReg, Flags: KillFlag).addMemOperand(MMO);
1001 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
1002 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::PS_vstorerw_ai))
1003 .addFrameIndex(Idx: FI).addImm(Val: 0)
1004 .addReg(RegNo: SrcReg, Flags: KillFlag).addMemOperand(MMO);
1005 } else {
1006 llvm_unreachable("Unimplemented");
1007 }
1008}
1009
1010void HexagonInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1011 MachineBasicBlock::iterator I,
1012 Register DestReg, int FI,
1013 const TargetRegisterClass *RC,
1014 Register VReg, unsigned SubReg,
1015 MachineInstr::MIFlag Flags) const {
1016 DebugLoc DL = MBB.findDebugLoc(MBBI: I);
1017 MachineFunction &MF = *MBB.getParent();
1018 MachineFrameInfo &MFI = MF.getFrameInfo();
1019
1020 MachineMemOperand *MMO = MF.getMachineMemOperand(
1021 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI), F: MachineMemOperand::MOLoad,
1022 Size: MFI.getObjectSize(ObjectIdx: FI), BaseAlignment: MFI.getObjectAlign(ObjectIdx: FI));
1023
1024 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
1025 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::L2_loadri_io), DestReg)
1026 .addFrameIndex(Idx: FI).addImm(Val: 0).addMemOperand(MMO);
1027 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
1028 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::L2_loadrd_io), DestReg)
1029 .addFrameIndex(Idx: FI).addImm(Val: 0).addMemOperand(MMO);
1030 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
1031 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::LDriw_pred), DestReg)
1032 .addFrameIndex(Idx: FI).addImm(Val: 0).addMemOperand(MMO);
1033 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
1034 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::LDriw_ctr), DestReg)
1035 .addFrameIndex(Idx: FI).addImm(Val: 0).addMemOperand(MMO);
1036 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) {
1037 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::PS_vloadrq_ai), DestReg)
1038 .addFrameIndex(Idx: FI).addImm(Val: 0).addMemOperand(MMO);
1039 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) {
1040 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::PS_vloadrv_ai), DestReg)
1041 .addFrameIndex(Idx: FI).addImm(Val: 0).addMemOperand(MMO);
1042 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) {
1043 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: Hexagon::PS_vloadrw_ai), DestReg)
1044 .addFrameIndex(Idx: FI).addImm(Val: 0).addMemOperand(MMO);
1045 } else {
1046 llvm_unreachable("Can't store this register to stack slot");
1047 }
1048}
1049
1050/// expandPostRAPseudo - This function is called for all pseudo instructions
1051/// that remain after register allocation. Many pseudo instructions are
1052/// created to help register allocation. This is the place to convert them
1053/// into real instructions. The target can edit MI in place, or it can insert
1054/// new instructions and erase MI. The function should return true if
1055/// anything was changed.
1056bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1057 MachineBasicBlock &MBB = *MI.getParent();
1058 MachineFunction &MF = *MBB.getParent();
1059 MachineRegisterInfo &MRI = MF.getRegInfo();
1060 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1061 LivePhysRegs LiveIn(HRI), LiveOut(HRI);
1062 DebugLoc DL = MI.getDebugLoc();
1063 unsigned Opc = MI.getOpcode();
1064
1065 auto RealCirc = [&](unsigned Opc, bool HasImm, unsigned MxOp) {
1066 Register Mx = MI.getOperand(i: MxOp).getReg();
1067 Register CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1);
1068 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::A2_tfrrcr), DestReg: CSx)
1069 .add(MO: MI.getOperand(i: (HasImm ? 5 : 4)));
1070 auto MIB = BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Opc)).add(MO: MI.getOperand(i: 0))
1071 .add(MO: MI.getOperand(i: 1)).add(MO: MI.getOperand(i: 2)).add(MO: MI.getOperand(i: 3));
1072 if (HasImm)
1073 MIB.add(MO: MI.getOperand(i: 4));
1074 MIB.addReg(RegNo: CSx, Flags: RegState::Implicit);
1075 MBB.erase(I: MI);
1076 return true;
1077 };
1078
1079 auto UseAligned = [&](const MachineInstr &MI, Align NeedAlign) {
1080 if (MI.memoperands().empty())
1081 return false;
1082 return all_of(Range: MI.memoperands(), P: [NeedAlign](const MachineMemOperand *MMO) {
1083 return MMO->getAlign() >= NeedAlign;
1084 });
1085 };
1086
1087 switch (Opc) {
1088 case Hexagon::PS_call_instrprof_custom: {
1089 auto Op0 = MI.getOperand(i: 0);
1090 assert(Op0.isGlobal() &&
1091 "First operand must be a global containing handler name.");
1092 const GlobalValue *NameVar = Op0.getGlobal();
1093 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Val: NameVar);
1094 auto *Arr = cast<ConstantDataArray>(Val: GV->getInitializer());
1095 StringRef NameStr = Arr->isCString() ? Arr->getAsCString() : Arr->getAsString();
1096
1097 MachineOperand &Op1 = MI.getOperand(i: 1);
1098 // Set R0 with the imm value to be passed to the custom profiling handler.
1099 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::A2_tfrsi), DestReg: Hexagon::R0)
1100 .addImm(Val: Op1.getImm());
1101 // The call to the custom handler is being treated as a special one as the
1102 // callee is responsible for saving and restoring all the registers
1103 // (including caller saved registers) it needs to modify. This is
1104 // done to reduce the impact of instrumentation on the code being
1105 // instrumented/profiled.
1106 // NOTE: R14, R15 and R28 are reserved for PLT handling. These registers
1107 // are in the Def list of the Hexagon::PS_call_instrprof_custom and
1108 // therefore will be handled appropriately duing register allocation.
1109
1110 // TODO: It may be a good idea to add a separate pseudo instruction for
1111 // static relocation which doesn't need to reserve r14, r15 and r28.
1112
1113 auto MIB = BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::J2_call))
1114 .addUse(RegNo: Hexagon::R0, Flags: RegState::Implicit|RegState::InternalRead)
1115 .addDef(RegNo: Hexagon::R29, Flags: RegState::ImplicitDefine)
1116 .addDef(RegNo: Hexagon::R30, Flags: RegState::ImplicitDefine)
1117 .addDef(RegNo: Hexagon::R14, Flags: RegState::ImplicitDefine)
1118 .addDef(RegNo: Hexagon::R15, Flags: RegState::ImplicitDefine)
1119 .addDef(RegNo: Hexagon::R28, Flags: RegState::ImplicitDefine);
1120 const char *cstr = MF.createExternalSymbolName(Name: NameStr);
1121 MIB.addExternalSymbol(FnName: cstr);
1122 MBB.erase(I: MI);
1123 return true;
1124 }
1125 case TargetOpcode::COPY: {
1126 MachineOperand &MD = MI.getOperand(i: 0);
1127 MachineOperand &MS = MI.getOperand(i: 1);
1128 MachineBasicBlock::iterator MBBI = MI.getIterator();
1129 if (MD.getReg() != MS.getReg() && !MS.isUndef()) {
1130 copyPhysReg(MBB, I: MI, DL, DestReg: MD.getReg(), SrcReg: MS.getReg(), KillSrc: MS.isKill());
1131 std::prev(x: MBBI)->copyImplicitOps(MF&: *MBB.getParent(), MI);
1132 }
1133 MBB.erase(I: MBBI);
1134 return true;
1135 }
1136 case Hexagon::PS_aligna:
1137 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::A2_andir), DestReg: MI.getOperand(i: 0).getReg())
1138 .addReg(RegNo: HRI.getFrameRegister())
1139 .addImm(Val: -MI.getOperand(i: 1).getImm());
1140 MBB.erase(I: MI);
1141 return true;
1142 case Hexagon::V6_vassignp: {
1143 Register SrcReg = MI.getOperand(i: 1).getReg();
1144 Register DstReg = MI.getOperand(i: 0).getReg();
1145 Register SrcLo = HRI.getSubReg(Reg: SrcReg, Idx: Hexagon::vsub_lo);
1146 Register SrcHi = HRI.getSubReg(Reg: SrcReg, Idx: Hexagon::vsub_hi);
1147 getLiveInRegsAt(Regs&: LiveIn, MI);
1148 RegState UndefLo = getUndefRegState(B: !LiveIn.contains(Reg: SrcLo));
1149 RegState UndefHi = getUndefRegState(B: !LiveIn.contains(Reg: SrcHi));
1150 RegState Kill = getKillRegState(B: MI.getOperand(i: 1).isKill());
1151 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vcombine), DestReg: DstReg)
1152 .addReg(RegNo: SrcHi, Flags: UndefHi)
1153 .addReg(RegNo: SrcLo, Flags: Kill | UndefLo);
1154 MBB.erase(I: MI);
1155 return true;
1156 }
1157 case Hexagon::V6_lo: {
1158 Register SrcReg = MI.getOperand(i: 1).getReg();
1159 Register DstReg = MI.getOperand(i: 0).getReg();
1160 Register SrcSubLo = HRI.getSubReg(Reg: SrcReg, Idx: Hexagon::vsub_lo);
1161 copyPhysReg(MBB, I: MI, DL, DestReg: DstReg, SrcReg: SrcSubLo, KillSrc: MI.getOperand(i: 1).isKill());
1162 MBB.erase(I: MI);
1163 MRI.clearKillFlags(Reg: SrcSubLo);
1164 return true;
1165 }
1166 case Hexagon::V6_hi: {
1167 Register SrcReg = MI.getOperand(i: 1).getReg();
1168 Register DstReg = MI.getOperand(i: 0).getReg();
1169 Register SrcSubHi = HRI.getSubReg(Reg: SrcReg, Idx: Hexagon::vsub_hi);
1170 copyPhysReg(MBB, I: MI, DL, DestReg: DstReg, SrcReg: SrcSubHi, KillSrc: MI.getOperand(i: 1).isKill());
1171 MBB.erase(I: MI);
1172 MRI.clearKillFlags(Reg: SrcSubHi);
1173 return true;
1174 }
1175 case Hexagon::PS_vloadrv_ai: {
1176 Register DstReg = MI.getOperand(i: 0).getReg();
1177 const MachineOperand &BaseOp = MI.getOperand(i: 1);
1178 assert(BaseOp.getSubReg() == 0);
1179 int Offset = MI.getOperand(i: 2).getImm();
1180 Align NeedAlign = HRI.getSpillAlign(RC: Hexagon::HvxVRRegClass);
1181 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai
1182 : Hexagon::V6_vL32Ub_ai;
1183 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: NewOpc), DestReg: DstReg)
1184 .addReg(RegNo: BaseOp.getReg(), Flags: getRegState(RegOp: BaseOp))
1185 .addImm(Val: Offset)
1186 .cloneMemRefs(OtherMI: MI);
1187 MBB.erase(I: MI);
1188 return true;
1189 }
1190 case Hexagon::PS_vloadrw_ai: {
1191 Register DstReg = MI.getOperand(i: 0).getReg();
1192 const MachineOperand &BaseOp = MI.getOperand(i: 1);
1193 assert(BaseOp.getSubReg() == 0);
1194 int Offset = MI.getOperand(i: 2).getImm();
1195 unsigned VecOffset = HRI.getSpillSize(RC: Hexagon::HvxVRRegClass);
1196 Align NeedAlign = HRI.getSpillAlign(RC: Hexagon::HvxVRRegClass);
1197 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai
1198 : Hexagon::V6_vL32Ub_ai;
1199 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: NewOpc),
1200 DestReg: HRI.getSubReg(Reg: DstReg, Idx: Hexagon::vsub_lo))
1201 .addReg(RegNo: BaseOp.getReg(), Flags: getRegState(RegOp: BaseOp) & ~RegState::Kill)
1202 .addImm(Val: Offset)
1203 .cloneMemRefs(OtherMI: MI);
1204 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: NewOpc),
1205 DestReg: HRI.getSubReg(Reg: DstReg, Idx: Hexagon::vsub_hi))
1206 .addReg(RegNo: BaseOp.getReg(), Flags: getRegState(RegOp: BaseOp))
1207 .addImm(Val: Offset + VecOffset)
1208 .cloneMemRefs(OtherMI: MI);
1209 MBB.erase(I: MI);
1210 return true;
1211 }
1212 case Hexagon::PS_vstorerv_ai: {
1213 const MachineOperand &SrcOp = MI.getOperand(i: 2);
1214 assert(SrcOp.getSubReg() == 0);
1215 const MachineOperand &BaseOp = MI.getOperand(i: 0);
1216 assert(BaseOp.getSubReg() == 0);
1217 int Offset = MI.getOperand(i: 1).getImm();
1218 Align NeedAlign = HRI.getSpillAlign(RC: Hexagon::HvxVRRegClass);
1219 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai
1220 : Hexagon::V6_vS32Ub_ai;
1221 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: NewOpc))
1222 .addReg(RegNo: BaseOp.getReg(), Flags: getRegState(RegOp: BaseOp))
1223 .addImm(Val: Offset)
1224 .addReg(RegNo: SrcOp.getReg(), Flags: getRegState(RegOp: SrcOp))
1225 .cloneMemRefs(OtherMI: MI);
1226 MBB.erase(I: MI);
1227 return true;
1228 }
1229 case Hexagon::PS_vstorerw_ai: {
1230 Register SrcReg = MI.getOperand(i: 2).getReg();
1231 const MachineOperand &BaseOp = MI.getOperand(i: 0);
1232 assert(BaseOp.getSubReg() == 0);
1233 int Offset = MI.getOperand(i: 1).getImm();
1234 unsigned VecOffset = HRI.getSpillSize(RC: Hexagon::HvxVRRegClass);
1235 Align NeedAlign = HRI.getSpillAlign(RC: Hexagon::HvxVRRegClass);
1236 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai
1237 : Hexagon::V6_vS32Ub_ai;
1238 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: NewOpc))
1239 .addReg(RegNo: BaseOp.getReg(), Flags: getRegState(RegOp: BaseOp) & ~RegState::Kill)
1240 .addImm(Val: Offset)
1241 .addReg(RegNo: HRI.getSubReg(Reg: SrcReg, Idx: Hexagon::vsub_lo))
1242 .cloneMemRefs(OtherMI: MI);
1243 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: NewOpc))
1244 .addReg(RegNo: BaseOp.getReg(), Flags: getRegState(RegOp: BaseOp))
1245 .addImm(Val: Offset + VecOffset)
1246 .addReg(RegNo: HRI.getSubReg(Reg: SrcReg, Idx: Hexagon::vsub_hi))
1247 .cloneMemRefs(OtherMI: MI);
1248 MBB.erase(I: MI);
1249 return true;
1250 }
1251 case Hexagon::PS_true: {
1252 Register Reg = MI.getOperand(i: 0).getReg();
1253 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::C2_orn), DestReg: Reg)
1254 .addReg(RegNo: Reg, Flags: RegState::Undef)
1255 .addReg(RegNo: Reg, Flags: RegState::Undef);
1256 MBB.erase(I: MI);
1257 return true;
1258 }
1259 case Hexagon::PS_false: {
1260 Register Reg = MI.getOperand(i: 0).getReg();
1261 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::C2_andn), DestReg: Reg)
1262 .addReg(RegNo: Reg, Flags: RegState::Undef)
1263 .addReg(RegNo: Reg, Flags: RegState::Undef);
1264 MBB.erase(I: MI);
1265 return true;
1266 }
1267 case Hexagon::PS_qtrue: {
1268 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_veqw), DestReg: MI.getOperand(i: 0).getReg())
1269 .addReg(RegNo: Hexagon::V0, Flags: RegState::Undef)
1270 .addReg(RegNo: Hexagon::V0, Flags: RegState::Undef);
1271 MBB.erase(I: MI);
1272 return true;
1273 }
1274 case Hexagon::PS_qfalse: {
1275 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vgtw), DestReg: MI.getOperand(i: 0).getReg())
1276 .addReg(RegNo: Hexagon::V0, Flags: RegState::Undef)
1277 .addReg(RegNo: Hexagon::V0, Flags: RegState::Undef);
1278 MBB.erase(I: MI);
1279 return true;
1280 }
1281 case Hexagon::PS_vdd0: {
1282 Register Vd = MI.getOperand(i: 0).getReg();
1283 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vsubw_dv), DestReg: Vd)
1284 .addReg(RegNo: Vd, Flags: RegState::Undef)
1285 .addReg(RegNo: Vd, Flags: RegState::Undef);
1286 MBB.erase(I: MI);
1287 return true;
1288 }
1289 case Hexagon::PS_vmulw: {
1290 // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
1291 Register DstReg = MI.getOperand(i: 0).getReg();
1292 Register Src1Reg = MI.getOperand(i: 1).getReg();
1293 Register Src2Reg = MI.getOperand(i: 2).getReg();
1294 Register Src1SubHi = HRI.getSubReg(Reg: Src1Reg, Idx: Hexagon::isub_hi);
1295 Register Src1SubLo = HRI.getSubReg(Reg: Src1Reg, Idx: Hexagon::isub_lo);
1296 Register Src2SubHi = HRI.getSubReg(Reg: Src2Reg, Idx: Hexagon::isub_hi);
1297 Register Src2SubLo = HRI.getSubReg(Reg: Src2Reg, Idx: Hexagon::isub_lo);
1298 BuildMI(BB&: MBB, I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Hexagon::M2_mpyi),
1299 DestReg: HRI.getSubReg(Reg: DstReg, Idx: Hexagon::isub_hi))
1300 .addReg(RegNo: Src1SubHi)
1301 .addReg(RegNo: Src2SubHi);
1302 BuildMI(BB&: MBB, I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Hexagon::M2_mpyi),
1303 DestReg: HRI.getSubReg(Reg: DstReg, Idx: Hexagon::isub_lo))
1304 .addReg(RegNo: Src1SubLo)
1305 .addReg(RegNo: Src2SubLo);
1306 MBB.erase(I: MI);
1307 MRI.clearKillFlags(Reg: Src1SubHi);
1308 MRI.clearKillFlags(Reg: Src1SubLo);
1309 MRI.clearKillFlags(Reg: Src2SubHi);
1310 MRI.clearKillFlags(Reg: Src2SubLo);
1311 return true;
1312 }
1313 case Hexagon::PS_vmulw_acc: {
1314 // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
1315 Register DstReg = MI.getOperand(i: 0).getReg();
1316 Register Src1Reg = MI.getOperand(i: 1).getReg();
1317 Register Src2Reg = MI.getOperand(i: 2).getReg();
1318 Register Src3Reg = MI.getOperand(i: 3).getReg();
1319 Register Src1SubHi = HRI.getSubReg(Reg: Src1Reg, Idx: Hexagon::isub_hi);
1320 Register Src1SubLo = HRI.getSubReg(Reg: Src1Reg, Idx: Hexagon::isub_lo);
1321 Register Src2SubHi = HRI.getSubReg(Reg: Src2Reg, Idx: Hexagon::isub_hi);
1322 Register Src2SubLo = HRI.getSubReg(Reg: Src2Reg, Idx: Hexagon::isub_lo);
1323 Register Src3SubHi = HRI.getSubReg(Reg: Src3Reg, Idx: Hexagon::isub_hi);
1324 Register Src3SubLo = HRI.getSubReg(Reg: Src3Reg, Idx: Hexagon::isub_lo);
1325 BuildMI(BB&: MBB, I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Hexagon::M2_maci),
1326 DestReg: HRI.getSubReg(Reg: DstReg, Idx: Hexagon::isub_hi))
1327 .addReg(RegNo: Src1SubHi)
1328 .addReg(RegNo: Src2SubHi)
1329 .addReg(RegNo: Src3SubHi);
1330 BuildMI(BB&: MBB, I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: Hexagon::M2_maci),
1331 DestReg: HRI.getSubReg(Reg: DstReg, Idx: Hexagon::isub_lo))
1332 .addReg(RegNo: Src1SubLo)
1333 .addReg(RegNo: Src2SubLo)
1334 .addReg(RegNo: Src3SubLo);
1335 MBB.erase(I: MI);
1336 MRI.clearKillFlags(Reg: Src1SubHi);
1337 MRI.clearKillFlags(Reg: Src1SubLo);
1338 MRI.clearKillFlags(Reg: Src2SubHi);
1339 MRI.clearKillFlags(Reg: Src2SubLo);
1340 MRI.clearKillFlags(Reg: Src3SubHi);
1341 MRI.clearKillFlags(Reg: Src3SubLo);
1342 return true;
1343 }
1344 case Hexagon::PS_pselect: {
1345 const MachineOperand &Op0 = MI.getOperand(i: 0);
1346 const MachineOperand &Op1 = MI.getOperand(i: 1);
1347 const MachineOperand &Op2 = MI.getOperand(i: 2);
1348 const MachineOperand &Op3 = MI.getOperand(i: 3);
1349 Register Rd = Op0.getReg();
1350 Register Pu = Op1.getReg();
1351 Register Rs = Op2.getReg();
1352 Register Rt = Op3.getReg();
1353 DebugLoc DL = MI.getDebugLoc();
1354 RegState K1 = getKillRegState(B: Op1.isKill());
1355 RegState K2 = getKillRegState(B: Op2.isKill());
1356 RegState K3 = getKillRegState(B: Op3.isKill());
1357 if (Rd != Rs)
1358 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::A2_tfrpt), DestReg: Rd)
1359 .addReg(RegNo: Pu, Flags: (Rd == Rt) ? K1 : RegState::NoFlags)
1360 .addReg(RegNo: Rs, Flags: K2);
1361 if (Rd != Rt)
1362 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::A2_tfrpf), DestReg: Rd)
1363 .addReg(RegNo: Pu, Flags: K1)
1364 .addReg(RegNo: Rt, Flags: K3);
1365 MBB.erase(I: MI);
1366 return true;
1367 }
1368 case Hexagon::PS_vselect: {
1369 const MachineOperand &Op0 = MI.getOperand(i: 0);
1370 const MachineOperand &Op1 = MI.getOperand(i: 1);
1371 const MachineOperand &Op2 = MI.getOperand(i: 2);
1372 const MachineOperand &Op3 = MI.getOperand(i: 3);
1373 getLiveOutRegsAt(Regs&: LiveOut, MI);
1374 bool IsDestLive = !LiveOut.available(MRI, Reg: Op0.getReg());
1375 Register PReg = Op1.getReg();
1376 assert(Op1.getSubReg() == 0);
1377 RegState PState = getRegState(RegOp: Op1);
1378
1379 if (Op0.getReg() != Op2.getReg()) {
1380 RegState S =
1381 Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill : PState;
1382 auto T = BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vcmov))
1383 .add(MO: Op0)
1384 .addReg(RegNo: PReg, Flags: S)
1385 .add(MO: Op2);
1386 if (IsDestLive)
1387 T.addReg(RegNo: Op0.getReg(), Flags: RegState::Implicit);
1388 IsDestLive = true;
1389 }
1390 if (Op0.getReg() != Op3.getReg()) {
1391 auto T = BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vncmov))
1392 .add(MO: Op0)
1393 .addReg(RegNo: PReg, Flags: PState)
1394 .add(MO: Op3);
1395 if (IsDestLive)
1396 T.addReg(RegNo: Op0.getReg(), Flags: RegState::Implicit);
1397 }
1398 MBB.erase(I: MI);
1399 return true;
1400 }
1401 case Hexagon::PS_wselect: {
1402 MachineOperand &Op0 = MI.getOperand(i: 0);
1403 MachineOperand &Op1 = MI.getOperand(i: 1);
1404 MachineOperand &Op2 = MI.getOperand(i: 2);
1405 MachineOperand &Op3 = MI.getOperand(i: 3);
1406 getLiveOutRegsAt(Regs&: LiveOut, MI);
1407 bool IsDestLive = !LiveOut.available(MRI, Reg: Op0.getReg());
1408 Register PReg = Op1.getReg();
1409 assert(Op1.getSubReg() == 0);
1410 RegState PState = getRegState(RegOp: Op1);
1411
1412 if (Op0.getReg() != Op2.getReg()) {
1413 RegState S =
1414 Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill : PState;
1415 Register SrcLo = HRI.getSubReg(Reg: Op2.getReg(), Idx: Hexagon::vsub_lo);
1416 Register SrcHi = HRI.getSubReg(Reg: Op2.getReg(), Idx: Hexagon::vsub_hi);
1417 auto T = BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vccombine))
1418 .add(MO: Op0)
1419 .addReg(RegNo: PReg, Flags: S)
1420 .addReg(RegNo: SrcHi)
1421 .addReg(RegNo: SrcLo);
1422 if (IsDestLive)
1423 T.addReg(RegNo: Op0.getReg(), Flags: RegState::Implicit);
1424 IsDestLive = true;
1425 }
1426 if (Op0.getReg() != Op3.getReg()) {
1427 Register SrcLo = HRI.getSubReg(Reg: Op3.getReg(), Idx: Hexagon::vsub_lo);
1428 Register SrcHi = HRI.getSubReg(Reg: Op3.getReg(), Idx: Hexagon::vsub_hi);
1429 auto T = BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vnccombine))
1430 .add(MO: Op0)
1431 .addReg(RegNo: PReg, Flags: PState)
1432 .addReg(RegNo: SrcHi)
1433 .addReg(RegNo: SrcLo);
1434 if (IsDestLive)
1435 T.addReg(RegNo: Op0.getReg(), Flags: RegState::Implicit);
1436 }
1437 MBB.erase(I: MI);
1438 return true;
1439 }
1440
1441 case Hexagon::PS_crash: {
1442 // Generate a misaligned load that is guaranteed to cause a crash.
1443 class CrashPseudoSourceValue : public PseudoSourceValue {
1444 public:
1445 CrashPseudoSourceValue(const TargetMachine &TM)
1446 : PseudoSourceValue(TargetCustom, TM) {}
1447
1448 bool isConstant(const MachineFrameInfo *) const override {
1449 return false;
1450 }
1451 bool isAliased(const MachineFrameInfo *) const override {
1452 return false;
1453 }
1454 bool mayAlias(const MachineFrameInfo *) const override {
1455 return false;
1456 }
1457 void printCustom(raw_ostream &OS) const override {
1458 OS << "MisalignedCrash";
1459 }
1460 };
1461
1462 static const CrashPseudoSourceValue CrashPSV(MF.getTarget());
1463 MachineMemOperand *MMO = MF.getMachineMemOperand(
1464 PtrInfo: MachinePointerInfo(&CrashPSV),
1465 F: MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile, Size: 8,
1466 BaseAlignment: Align(1));
1467 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::PS_loadrdabs), DestReg: Hexagon::D13)
1468 .addImm(Val: 0xBADC0FEE) // Misaligned load.
1469 .addMemOperand(MMO);
1470 MBB.erase(I: MI);
1471 return true;
1472 }
1473
1474 case Hexagon::PS_tailcall_i:
1475 MI.setDesc(get(Opcode: Hexagon::J2_jump));
1476 return true;
1477 case Hexagon::PS_tailcall_r:
1478 case Hexagon::PS_jmpret:
1479 MI.setDesc(get(Opcode: Hexagon::J2_jumpr));
1480 return true;
1481 case Hexagon::PS_jmprett:
1482 MI.setDesc(get(Opcode: Hexagon::J2_jumprt));
1483 return true;
1484 case Hexagon::PS_jmpretf:
1485 MI.setDesc(get(Opcode: Hexagon::J2_jumprf));
1486 return true;
1487 case Hexagon::PS_jmprettnewpt:
1488 MI.setDesc(get(Opcode: Hexagon::J2_jumprtnewpt));
1489 return true;
1490 case Hexagon::PS_jmpretfnewpt:
1491 MI.setDesc(get(Opcode: Hexagon::J2_jumprfnewpt));
1492 return true;
1493 case Hexagon::PS_jmprettnew:
1494 MI.setDesc(get(Opcode: Hexagon::J2_jumprtnew));
1495 return true;
1496 case Hexagon::PS_jmpretfnew:
1497 MI.setDesc(get(Opcode: Hexagon::J2_jumprfnew));
1498 return true;
1499
1500 case Hexagon::PS_loadrub_pci:
1501 return RealCirc(Hexagon::L2_loadrub_pci, /*HasImm*/true, /*MxOp*/4);
1502 case Hexagon::PS_loadrb_pci:
1503 return RealCirc(Hexagon::L2_loadrb_pci, /*HasImm*/true, /*MxOp*/4);
1504 case Hexagon::PS_loadruh_pci:
1505 return RealCirc(Hexagon::L2_loadruh_pci, /*HasImm*/true, /*MxOp*/4);
1506 case Hexagon::PS_loadrh_pci:
1507 return RealCirc(Hexagon::L2_loadrh_pci, /*HasImm*/true, /*MxOp*/4);
1508 case Hexagon::PS_loadri_pci:
1509 return RealCirc(Hexagon::L2_loadri_pci, /*HasImm*/true, /*MxOp*/4);
1510 case Hexagon::PS_loadrd_pci:
1511 return RealCirc(Hexagon::L2_loadrd_pci, /*HasImm*/true, /*MxOp*/4);
1512 case Hexagon::PS_loadrub_pcr:
1513 return RealCirc(Hexagon::L2_loadrub_pcr, /*HasImm*/false, /*MxOp*/3);
1514 case Hexagon::PS_loadrb_pcr:
1515 return RealCirc(Hexagon::L2_loadrb_pcr, /*HasImm*/false, /*MxOp*/3);
1516 case Hexagon::PS_loadruh_pcr:
1517 return RealCirc(Hexagon::L2_loadruh_pcr, /*HasImm*/false, /*MxOp*/3);
1518 case Hexagon::PS_loadrh_pcr:
1519 return RealCirc(Hexagon::L2_loadrh_pcr, /*HasImm*/false, /*MxOp*/3);
1520 case Hexagon::PS_loadri_pcr:
1521 return RealCirc(Hexagon::L2_loadri_pcr, /*HasImm*/false, /*MxOp*/3);
1522 case Hexagon::PS_loadrd_pcr:
1523 return RealCirc(Hexagon::L2_loadrd_pcr, /*HasImm*/false, /*MxOp*/3);
1524 case Hexagon::PS_storerb_pci:
1525 return RealCirc(Hexagon::S2_storerb_pci, /*HasImm*/true, /*MxOp*/3);
1526 case Hexagon::PS_storerh_pci:
1527 return RealCirc(Hexagon::S2_storerh_pci, /*HasImm*/true, /*MxOp*/3);
1528 case Hexagon::PS_storerf_pci:
1529 return RealCirc(Hexagon::S2_storerf_pci, /*HasImm*/true, /*MxOp*/3);
1530 case Hexagon::PS_storeri_pci:
1531 return RealCirc(Hexagon::S2_storeri_pci, /*HasImm*/true, /*MxOp*/3);
1532 case Hexagon::PS_storerd_pci:
1533 return RealCirc(Hexagon::S2_storerd_pci, /*HasImm*/true, /*MxOp*/3);
1534 case Hexagon::PS_storerb_pcr:
1535 return RealCirc(Hexagon::S2_storerb_pcr, /*HasImm*/false, /*MxOp*/2);
1536 case Hexagon::PS_storerh_pcr:
1537 return RealCirc(Hexagon::S2_storerh_pcr, /*HasImm*/false, /*MxOp*/2);
1538 case Hexagon::PS_storerf_pcr:
1539 return RealCirc(Hexagon::S2_storerf_pcr, /*HasImm*/false, /*MxOp*/2);
1540 case Hexagon::PS_storeri_pcr:
1541 return RealCirc(Hexagon::S2_storeri_pcr, /*HasImm*/false, /*MxOp*/2);
1542 case Hexagon::PS_storerd_pcr:
1543 return RealCirc(Hexagon::S2_storerd_pcr, /*HasImm*/false, /*MxOp*/2);
1544 }
1545
1546 return false;
1547}
1548
1549MachineBasicBlock::instr_iterator
1550HexagonInstrInfo::expandVGatherPseudo(MachineInstr &MI) const {
1551 MachineBasicBlock &MBB = *MI.getParent();
1552 const DebugLoc &DL = MI.getDebugLoc();
1553 unsigned Opc = MI.getOpcode();
1554 MachineBasicBlock::iterator First;
1555
1556 switch (Opc) {
1557 case Hexagon::V6_vgather_vscatter_mh_pseudo:
1558 // This is mainly a place holder. It will be extended.
1559 First = BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vgathermh))
1560 .add(MO: MI.getOperand(i: 2))
1561 .add(MO: MI.getOperand(i: 3))
1562 .add(MO: MI.getOperand(i: 4));
1563 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vscattermh))
1564 .add(MO: MI.getOperand(i: 2))
1565 .add(MO: MI.getOperand(i: 3))
1566 .add(MO: MI.getOperand(i: 4))
1567 .addReg(RegNo: Hexagon::VTMP);
1568 MBB.erase(I: MI);
1569 return First.getInstrIterator();
1570 case Hexagon::V6_vgathermh_pseudo:
1571 First = BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vgathermh))
1572 .add(MO: MI.getOperand(i: 2))
1573 .add(MO: MI.getOperand(i: 3))
1574 .add(MO: MI.getOperand(i: 4));
1575 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vS32b_new_ai))
1576 .add(MO: MI.getOperand(i: 0))
1577 .addImm(Val: MI.getOperand(i: 1).getImm())
1578 .addReg(RegNo: Hexagon::VTMP);
1579 MBB.erase(I: MI);
1580 return First.getInstrIterator();
1581
1582 case Hexagon::V6_vgathermw_pseudo:
1583 First = BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vgathermw))
1584 .add(MO: MI.getOperand(i: 2))
1585 .add(MO: MI.getOperand(i: 3))
1586 .add(MO: MI.getOperand(i: 4));
1587 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vS32b_new_ai))
1588 .add(MO: MI.getOperand(i: 0))
1589 .addImm(Val: MI.getOperand(i: 1).getImm())
1590 .addReg(RegNo: Hexagon::VTMP);
1591 MBB.erase(I: MI);
1592 return First.getInstrIterator();
1593
1594 case Hexagon::V6_vgathermhw_pseudo:
1595 First = BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vgathermhw))
1596 .add(MO: MI.getOperand(i: 2))
1597 .add(MO: MI.getOperand(i: 3))
1598 .add(MO: MI.getOperand(i: 4));
1599 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vS32b_new_ai))
1600 .add(MO: MI.getOperand(i: 0))
1601 .addImm(Val: MI.getOperand(i: 1).getImm())
1602 .addReg(RegNo: Hexagon::VTMP);
1603 MBB.erase(I: MI);
1604 return First.getInstrIterator();
1605
1606 case Hexagon::V6_vgathermhq_pseudo:
1607 First = BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vgathermhq))
1608 .add(MO: MI.getOperand(i: 2))
1609 .add(MO: MI.getOperand(i: 3))
1610 .add(MO: MI.getOperand(i: 4))
1611 .add(MO: MI.getOperand(i: 5));
1612 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vS32b_new_ai))
1613 .add(MO: MI.getOperand(i: 0))
1614 .addImm(Val: MI.getOperand(i: 1).getImm())
1615 .addReg(RegNo: Hexagon::VTMP);
1616 MBB.erase(I: MI);
1617 return First.getInstrIterator();
1618
1619 case Hexagon::V6_vgathermwq_pseudo:
1620 First = BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vgathermwq))
1621 .add(MO: MI.getOperand(i: 2))
1622 .add(MO: MI.getOperand(i: 3))
1623 .add(MO: MI.getOperand(i: 4))
1624 .add(MO: MI.getOperand(i: 5));
1625 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vS32b_new_ai))
1626 .add(MO: MI.getOperand(i: 0))
1627 .addImm(Val: MI.getOperand(i: 1).getImm())
1628 .addReg(RegNo: Hexagon::VTMP);
1629 MBB.erase(I: MI);
1630 return First.getInstrIterator();
1631
1632 case Hexagon::V6_vgathermhwq_pseudo:
1633 First = BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vgathermhwq))
1634 .add(MO: MI.getOperand(i: 2))
1635 .add(MO: MI.getOperand(i: 3))
1636 .add(MO: MI.getOperand(i: 4))
1637 .add(MO: MI.getOperand(i: 5));
1638 BuildMI(BB&: MBB, I&: MI, MIMD: DL, MCID: get(Opcode: Hexagon::V6_vS32b_new_ai))
1639 .add(MO: MI.getOperand(i: 0))
1640 .addImm(Val: MI.getOperand(i: 1).getImm())
1641 .addReg(RegNo: Hexagon::VTMP);
1642 MBB.erase(I: MI);
1643 return First.getInstrIterator();
1644 }
1645
1646 return MI.getIterator();
1647}
1648
1649// We indicate that we want to reverse the branch by
1650// inserting the reversed branching opcode.
1651bool HexagonInstrInfo::reverseBranchCondition(
1652 SmallVectorImpl<MachineOperand> &Cond) const {
1653 if (Cond.empty())
1654 return true;
1655 assert(Cond[0].isImm() && "First entry in the cond vector not imm-val");
1656 unsigned opcode = Cond[0].getImm();
1657 //unsigned temp;
1658 assert(get(opcode).isBranch() && "Should be a branching condition.");
1659 if (isEndLoopN(Opcode: opcode))
1660 return true;
1661 unsigned NewOpcode = getInvertedPredicatedOpcode(Opc: opcode);
1662 Cond[0].setImm(NewOpcode);
1663 return false;
1664}
1665
1666void HexagonInstrInfo::insertNoop(MachineBasicBlock &MBB,
1667 MachineBasicBlock::iterator MI) const {
1668 DebugLoc DL;
1669 BuildMI(BB&: MBB, I: MI, MIMD: DL, MCID: get(Opcode: Hexagon::A2_nop));
1670}
1671
1672bool HexagonInstrInfo::isPostIncrement(const MachineInstr &MI) const {
1673 return getAddrMode(MI) == HexagonII::PostInc;
1674}
1675
1676// Returns true if an instruction is predicated irrespective of the predicate
1677// sense. For example, all of the following will return true.
1678// if (p0) R1 = add(R2, R3)
1679// if (!p0) R1 = add(R2, R3)
1680// if (p0.new) R1 = add(R2, R3)
1681// if (!p0.new) R1 = add(R2, R3)
1682// Note: New-value stores are not included here as in the current
1683// implementation, we don't need to check their predicate sense.
1684bool HexagonInstrInfo::isPredicated(const MachineInstr &MI) const {
1685 const uint64_t F = MI.getDesc().TSFlags;
1686 return (F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask;
1687}
1688
1689bool HexagonInstrInfo::PredicateInstruction(
1690 MachineInstr &MI, ArrayRef<MachineOperand> Cond) const {
1691 if (Cond.empty() || isNewValueJump(Opcode: Cond[0].getImm()) ||
1692 isEndLoopN(Opcode: Cond[0].getImm())) {
1693 LLVM_DEBUG(dbgs() << "\nCannot predicate:"; MI.dump(););
1694 return false;
1695 }
1696 int Opc = MI.getOpcode();
1697 assert (isPredicable(MI) && "Expected predicable instruction");
1698 bool invertJump = predOpcodeHasNot(Cond);
1699
1700 // We have to predicate MI "in place", i.e. after this function returns,
1701 // MI will need to be transformed into a predicated form. To avoid com-
1702 // plicated manipulations with the operands (handling tied operands,
1703 // etc.), build a new temporary instruction, then overwrite MI with it.
1704
1705 MachineBasicBlock &B = *MI.getParent();
1706 DebugLoc DL = MI.getDebugLoc();
1707 unsigned PredOpc = getCondOpcode(Opc, sense: invertJump);
1708 MachineInstrBuilder T = BuildMI(BB&: B, I&: MI, MIMD: DL, MCID: get(Opcode: PredOpc));
1709 unsigned NOp = 0, NumOps = MI.getNumOperands();
1710 while (NOp < NumOps) {
1711 MachineOperand &Op = MI.getOperand(i: NOp);
1712 if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1713 break;
1714 T.add(MO: Op);
1715 NOp++;
1716 }
1717
1718 Register PredReg;
1719 unsigned PredRegPos;
1720 RegState PredRegFlags = {};
1721 bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1722 (void)GotPredReg;
1723 assert(GotPredReg);
1724 T.addReg(RegNo: PredReg, Flags: PredRegFlags);
1725 while (NOp < NumOps)
1726 T.add(MO: MI.getOperand(i: NOp++));
1727
1728 MI.setDesc(get(Opcode: PredOpc));
1729 while (unsigned n = MI.getNumOperands())
1730 MI.removeOperand(OpNo: n-1);
1731 for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1732 MI.addOperand(Op: T->getOperand(i));
1733
1734 MachineBasicBlock::instr_iterator TI = T->getIterator();
1735 B.erase(I: TI);
1736
1737 MachineRegisterInfo &MRI = B.getParent()->getRegInfo();
1738 MRI.clearKillFlags(Reg: PredReg);
1739 return true;
1740}
1741
1742bool HexagonInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1743 ArrayRef<MachineOperand> Pred2) const {
1744 // TODO: Fix this
1745 return false;
1746}
1747
1748bool HexagonInstrInfo::ClobbersPredicate(MachineInstr &MI,
1749 std::vector<MachineOperand> &Pred,
1750 bool SkipDead) const {
1751 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1752
1753 for (const MachineOperand &MO : MI.operands()) {
1754 if (MO.isReg()) {
1755 if (!MO.isDef())
1756 continue;
1757 const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(Reg: MO.getReg());
1758 if (RC == &Hexagon::PredRegsRegClass) {
1759 Pred.push_back(x: MO);
1760 return true;
1761 }
1762 continue;
1763 } else if (MO.isRegMask()) {
1764 for (Register PR : Hexagon::PredRegsRegClass) {
1765 if (!MI.modifiesRegister(Reg: PR, TRI: &HRI))
1766 continue;
1767 Pred.push_back(x: MO);
1768 return true;
1769 }
1770 }
1771 }
1772 return false;
1773}
1774
1775bool HexagonInstrInfo::isPredicable(const MachineInstr &MI) const {
1776 if (!MI.getDesc().isPredicable())
1777 return false;
1778
1779 if (MI.isCall() || isTailCall(MI)) {
1780 if (!Subtarget.usePredicatedCalls())
1781 return false;
1782 }
1783
1784 // HVX loads are not predicable on v60, but are on v62.
1785 if (!Subtarget.hasV62Ops()) {
1786 switch (MI.getOpcode()) {
1787 case Hexagon::V6_vL32b_ai:
1788 case Hexagon::V6_vL32b_pi:
1789 case Hexagon::V6_vL32b_ppu:
1790 case Hexagon::V6_vL32b_cur_ai:
1791 case Hexagon::V6_vL32b_cur_pi:
1792 case Hexagon::V6_vL32b_cur_ppu:
1793 case Hexagon::V6_vL32b_nt_ai:
1794 case Hexagon::V6_vL32b_nt_pi:
1795 case Hexagon::V6_vL32b_nt_ppu:
1796 case Hexagon::V6_vL32b_tmp_ai:
1797 case Hexagon::V6_vL32b_tmp_pi:
1798 case Hexagon::V6_vL32b_tmp_ppu:
1799 case Hexagon::V6_vL32b_nt_cur_ai:
1800 case Hexagon::V6_vL32b_nt_cur_pi:
1801 case Hexagon::V6_vL32b_nt_cur_ppu:
1802 case Hexagon::V6_vL32b_nt_tmp_ai:
1803 case Hexagon::V6_vL32b_nt_tmp_pi:
1804 case Hexagon::V6_vL32b_nt_tmp_ppu:
1805 return false;
1806 }
1807 }
1808 return true;
1809}
1810
1811bool HexagonInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst,
1812 bool Invert) const {
1813 if (Invert)
1814 return false;
1815
1816 switch (Inst.getOpcode()) {
1817 // TODO: Add more instructions to be handled by MachineCombiner.
1818 case Hexagon::F2_sfadd:
1819 return Inst.getFlag(Flag: MachineInstr::MIFlag::FmReassoc);
1820 default:
1821 return false;
1822 }
1823}
1824
1825bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
1826 const MachineBasicBlock *MBB,
1827 const MachineFunction &MF) const {
1828 // Debug info is never a scheduling boundary. It's necessary to be explicit
1829 // due to the special treatment of IT instructions below, otherwise a
1830 // dbg_value followed by an IT will result in the IT instruction being
1831 // considered a scheduling hazard, which is wrong. It should be the actual
1832 // instruction preceding the dbg_value instruction(s), just like it is
1833 // when debug info is not present.
1834 if (MI.isDebugInstr())
1835 return false;
1836
1837 // Throwing call is a boundary.
1838 if (MI.isCall()) {
1839 // Don't mess around with no return calls.
1840 if (doesNotReturn(CallMI: MI))
1841 return true;
1842 // If any of the block's successors is a landing pad, this could be a
1843 // throwing call.
1844 for (auto *I : MBB->successors())
1845 if (I->isEHPad())
1846 return true;
1847 }
1848
1849 // Terminators and labels can't be scheduled around.
1850 if (MI.getDesc().isTerminator() || MI.isPosition())
1851 return true;
1852
1853 // INLINEASM_BR can jump to another block
1854 if (MI.getOpcode() == TargetOpcode::INLINEASM_BR)
1855 return true;
1856
1857 if (MI.isInlineAsm() && !ScheduleInlineAsm)
1858 return true;
1859
1860 return false;
1861}
1862
1863/// Measure the specified inline asm to determine an approximation of its
1864/// length.
1865/// Comments (which run till the next SeparatorString or newline) do not
1866/// count as an instruction.
1867/// Any other non-whitespace text is considered an instruction, with
1868/// multiple instructions separated by SeparatorString or newlines.
1869/// Variable-length instructions are not handled here; this function
1870/// may be overloaded in the target code to do that.
1871/// Hexagon counts the number of ##'s and adjust for that many
1872/// constant exenders.
1873unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str,
1874 const MCAsmInfo &MAI,
1875 const TargetSubtargetInfo *STI) const {
1876 StringRef AStr(Str);
1877 // Count the number of instructions in the asm.
1878 bool atInsnStart = true;
1879 unsigned Length = 0;
1880 const unsigned MaxInstLength = MAI.getMaxInstLength(STI);
1881 for (; *Str; ++Str) {
1882 if (*Str == '\n' || strncmp(s1: Str, s2: MAI.getSeparatorString(),
1883 n: strlen(s: MAI.getSeparatorString())) == 0)
1884 atInsnStart = true;
1885 if (atInsnStart && !isSpace(C: static_cast<unsigned char>(*Str))) {
1886 Length += MaxInstLength;
1887 atInsnStart = false;
1888 }
1889 if (atInsnStart && strncmp(s1: Str, s2: MAI.getCommentString().data(),
1890 n: MAI.getCommentString().size()) == 0)
1891 atInsnStart = false;
1892 }
1893
1894 // Add to size number of constant extenders seen * 4.
1895 StringRef Occ("##");
1896 Length += AStr.count(Str: Occ)*4;
1897 return Length;
1898}
1899
1900ScheduleHazardRecognizer*
1901HexagonInstrInfo::CreateTargetPostRAHazardRecognizer(
1902 const InstrItineraryData *II, const ScheduleDAG *DAG) const {
1903 if (UseDFAHazardRec)
1904 return new HexagonHazardRecognizer(II, this, Subtarget);
1905 return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
1906}
1907
1908/// For a comparison instruction, return the source registers in
1909/// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
1910/// compares against in CmpValue. Return true if the comparison instruction
1911/// can be analyzed.
1912bool HexagonInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
1913 Register &SrcReg2, int64_t &Mask,
1914 int64_t &Value) const {
1915 unsigned Opc = MI.getOpcode();
1916
1917 // Set mask and the first source register.
1918 switch (Opc) {
1919 case Hexagon::C2_cmpeq:
1920 case Hexagon::C2_cmpeqp:
1921 case Hexagon::C2_cmpgt:
1922 case Hexagon::C2_cmpgtp:
1923 case Hexagon::C2_cmpgtu:
1924 case Hexagon::C2_cmpgtup:
1925 case Hexagon::C4_cmpneq:
1926 case Hexagon::C4_cmplte:
1927 case Hexagon::C4_cmplteu:
1928 case Hexagon::C2_cmpeqi:
1929 case Hexagon::C2_cmpgti:
1930 case Hexagon::C2_cmpgtui:
1931 case Hexagon::C4_cmpneqi:
1932 case Hexagon::C4_cmplteui:
1933 case Hexagon::C4_cmpltei:
1934 SrcReg = MI.getOperand(i: 1).getReg();
1935 Mask = ~0;
1936 break;
1937 case Hexagon::A4_cmpbeq:
1938 case Hexagon::A4_cmpbgt:
1939 case Hexagon::A4_cmpbgtu:
1940 case Hexagon::A4_cmpbeqi:
1941 case Hexagon::A4_cmpbgti:
1942 case Hexagon::A4_cmpbgtui:
1943 SrcReg = MI.getOperand(i: 1).getReg();
1944 Mask = 0xFF;
1945 break;
1946 case Hexagon::A4_cmpheq:
1947 case Hexagon::A4_cmphgt:
1948 case Hexagon::A4_cmphgtu:
1949 case Hexagon::A4_cmpheqi:
1950 case Hexagon::A4_cmphgti:
1951 case Hexagon::A4_cmphgtui:
1952 SrcReg = MI.getOperand(i: 1).getReg();
1953 Mask = 0xFFFF;
1954 break;
1955 }
1956
1957 // Set the value/second source register.
1958 switch (Opc) {
1959 case Hexagon::C2_cmpeq:
1960 case Hexagon::C2_cmpeqp:
1961 case Hexagon::C2_cmpgt:
1962 case Hexagon::C2_cmpgtp:
1963 case Hexagon::C2_cmpgtu:
1964 case Hexagon::C2_cmpgtup:
1965 case Hexagon::A4_cmpbeq:
1966 case Hexagon::A4_cmpbgt:
1967 case Hexagon::A4_cmpbgtu:
1968 case Hexagon::A4_cmpheq:
1969 case Hexagon::A4_cmphgt:
1970 case Hexagon::A4_cmphgtu:
1971 case Hexagon::C4_cmpneq:
1972 case Hexagon::C4_cmplte:
1973 case Hexagon::C4_cmplteu:
1974 SrcReg2 = MI.getOperand(i: 2).getReg();
1975 Value = 0;
1976 return true;
1977
1978 case Hexagon::C2_cmpeqi:
1979 case Hexagon::C2_cmpgtui:
1980 case Hexagon::C2_cmpgti:
1981 case Hexagon::C4_cmpneqi:
1982 case Hexagon::C4_cmplteui:
1983 case Hexagon::C4_cmpltei:
1984 case Hexagon::A4_cmpbeqi:
1985 case Hexagon::A4_cmpbgti:
1986 case Hexagon::A4_cmpbgtui:
1987 case Hexagon::A4_cmpheqi:
1988 case Hexagon::A4_cmphgti:
1989 case Hexagon::A4_cmphgtui: {
1990 SrcReg2 = 0;
1991 const MachineOperand &Op2 = MI.getOperand(i: 2);
1992 if (!Op2.isImm())
1993 return false;
1994 Value = MI.getOperand(i: 2).getImm();
1995 return true;
1996 }
1997 }
1998
1999 return false;
2000}
2001
2002unsigned HexagonInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
2003 const MachineInstr &MI,
2004 unsigned *PredCost) const {
2005 return getInstrTimingClassLatency(ItinData, MI);
2006}
2007
2008DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(
2009 const TargetSubtargetInfo &STI) const {
2010 const InstrItineraryData *II = STI.getInstrItineraryData();
2011 return static_cast<const HexagonSubtarget&>(STI).createDFAPacketizer(IID: II);
2012}
2013
2014// Inspired by this pair:
2015// %r13 = L2_loadri_io %r29, 136; mem:LD4[FixedStack0]
2016// S2_storeri_io %r29, 132, killed %r1; flags: mem:ST4[FixedStack1]
2017// Currently AA considers the addresses in these instructions to be aliasing.
2018bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(
2019 const MachineInstr &MIa, const MachineInstr &MIb) const {
2020 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
2021 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
2022 return false;
2023
2024 // Instructions that are pure loads, not loads and stores like memops are not
2025 // dependent.
2026 if (MIa.mayLoad() && !isMemOp(MI: MIa) && MIb.mayLoad() && !isMemOp(MI: MIb))
2027 return true;
2028
2029 // Get the base register in MIa.
2030 unsigned BasePosA, OffsetPosA;
2031 if (!getBaseAndOffsetPosition(MI: MIa, BasePos&: BasePosA, OffsetPos&: OffsetPosA))
2032 return false;
2033 const MachineOperand &BaseA = MIa.getOperand(i: BasePosA);
2034 Register BaseRegA = BaseA.getReg();
2035 unsigned BaseSubA = BaseA.getSubReg();
2036
2037 // Get the base register in MIb.
2038 unsigned BasePosB, OffsetPosB;
2039 if (!getBaseAndOffsetPosition(MI: MIb, BasePos&: BasePosB, OffsetPos&: OffsetPosB))
2040 return false;
2041 const MachineOperand &BaseB = MIb.getOperand(i: BasePosB);
2042 Register BaseRegB = BaseB.getReg();
2043 unsigned BaseSubB = BaseB.getSubReg();
2044
2045 if (BaseRegA != BaseRegB || BaseSubA != BaseSubB)
2046 return false;
2047
2048 // Get the access sizes.
2049 unsigned SizeA = getMemAccessSize(MI: MIa);
2050 unsigned SizeB = getMemAccessSize(MI: MIb);
2051
2052 // Get the offsets. Handle immediates only for now.
2053 const MachineOperand &OffA = MIa.getOperand(i: OffsetPosA);
2054 const MachineOperand &OffB = MIb.getOperand(i: OffsetPosB);
2055 if (!MIa.getOperand(i: OffsetPosA).isImm() ||
2056 !MIb.getOperand(i: OffsetPosB).isImm())
2057 return false;
2058 int OffsetA = isPostIncrement(MI: MIa) ? 0 : OffA.getImm();
2059 int OffsetB = isPostIncrement(MI: MIb) ? 0 : OffB.getImm();
2060
2061 // This is a mem access with the same base register and known offsets from it.
2062 // Reason about it.
2063 if (OffsetA > OffsetB) {
2064 uint64_t OffDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
2065 return SizeB <= OffDiff;
2066 }
2067 if (OffsetA < OffsetB) {
2068 uint64_t OffDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
2069 return SizeA <= OffDiff;
2070 }
2071
2072 return false;
2073}
2074
2075/// If the instruction is an increment of a constant value, return the amount.
2076bool HexagonInstrInfo::getIncrementValue(const MachineInstr &MI,
2077 int &Value) const {
2078 if (isPostIncrement(MI)) {
2079 unsigned BasePos = 0, OffsetPos = 0;
2080 if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
2081 return false;
2082 const MachineOperand &OffsetOp = MI.getOperand(i: OffsetPos);
2083 if (OffsetOp.isImm()) {
2084 Value = OffsetOp.getImm();
2085 return true;
2086 }
2087 } else if (MI.getOpcode() == Hexagon::A2_addi) {
2088 const MachineOperand &AddOp = MI.getOperand(i: 2);
2089 if (AddOp.isImm()) {
2090 Value = AddOp.getImm();
2091 return true;
2092 }
2093 }
2094
2095 return false;
2096}
2097
2098std::pair<unsigned, unsigned>
2099HexagonInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
2100 return std::make_pair(x: TF & ~HexagonII::MO_Bitmasks,
2101 y: TF & HexagonII::MO_Bitmasks);
2102}
2103
2104ArrayRef<std::pair<unsigned, const char*>>
2105HexagonInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
2106 using namespace HexagonII;
2107
2108 static const std::pair<unsigned, const char*> Flags[] = {
2109 {MO_PCREL, "hexagon-pcrel"},
2110 {MO_GOT, "hexagon-got"},
2111 {MO_LO16, "hexagon-lo16"},
2112 {MO_HI16, "hexagon-hi16"},
2113 {MO_GPREL, "hexagon-gprel"},
2114 {MO_GDGOT, "hexagon-gdgot"},
2115 {MO_GDPLT, "hexagon-gdplt"},
2116 {MO_IE, "hexagon-ie"},
2117 {MO_IEGOT, "hexagon-iegot"},
2118 {MO_TPREL, "hexagon-tprel"}
2119 };
2120 return ArrayRef(Flags);
2121}
2122
2123ArrayRef<std::pair<unsigned, const char*>>
2124HexagonInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
2125 using namespace HexagonII;
2126
2127 static const std::pair<unsigned, const char*> Flags[] = {
2128 {HMOTF_ConstExtended, "hexagon-ext"}
2129 };
2130 return ArrayRef(Flags);
2131}
2132
2133Register HexagonInstrInfo::createVR(MachineFunction *MF, MVT VT) const {
2134 MachineRegisterInfo &MRI = MF->getRegInfo();
2135 const TargetRegisterClass *TRC;
2136 if (VT == MVT::i1) {
2137 TRC = &Hexagon::PredRegsRegClass;
2138 } else if (VT == MVT::i32 || VT == MVT::f32) {
2139 TRC = &Hexagon::IntRegsRegClass;
2140 } else if (VT == MVT::i64 || VT == MVT::f64) {
2141 TRC = &Hexagon::DoubleRegsRegClass;
2142 } else {
2143 llvm_unreachable("Cannot handle this register class");
2144 }
2145
2146 Register NewReg = MRI.createVirtualRegister(RegClass: TRC);
2147 return NewReg;
2148}
2149
2150bool HexagonInstrInfo::isAbsoluteSet(const MachineInstr &MI) const {
2151 return (getAddrMode(MI) == HexagonII::AbsoluteSet);
2152}
2153
2154bool HexagonInstrInfo::isAccumulator(const MachineInstr &MI) const {
2155 const uint64_t F = MI.getDesc().TSFlags;
2156 return((F >> HexagonII::AccumulatorPos) & HexagonII::AccumulatorMask);
2157}
2158
2159bool HexagonInstrInfo::isBaseImmOffset(const MachineInstr &MI) const {
2160 return getAddrMode(MI) == HexagonII::BaseImmOffset;
2161}
2162
2163bool HexagonInstrInfo::isComplex(const MachineInstr &MI) const {
2164 return !isTC1(MI) && !isTC2Early(MI) && !MI.getDesc().mayLoad() &&
2165 !MI.getDesc().mayStore() &&
2166 MI.getDesc().getOpcode() != Hexagon::S2_allocframe &&
2167 MI.getDesc().getOpcode() != Hexagon::L2_deallocframe &&
2168 !isMemOp(MI) && !MI.isBranch() && !MI.isReturn() && !MI.isCall();
2169}
2170
2171// Return true if the instruction is a compound branch instruction.
2172bool HexagonInstrInfo::isCompoundBranchInstr(const MachineInstr &MI) const {
2173 return getType(MI) == HexagonII::TypeCJ && MI.isBranch();
2174}
2175
2176// TODO: In order to have isExtendable for fpimm/f32Ext, we need to handle
2177// isFPImm and later getFPImm as well.
2178bool HexagonInstrInfo::isConstExtended(const MachineInstr &MI) const {
2179 const uint64_t F = MI.getDesc().TSFlags;
2180 unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
2181 if (isExtended) // Instruction must be extended.
2182 return true;
2183
2184 unsigned isExtendable =
2185 (F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
2186 if (!isExtendable)
2187 return false;
2188
2189 if (MI.isCall())
2190 return false;
2191
2192 short ExtOpNum = getCExtOpNum(MI);
2193 const MachineOperand &MO = MI.getOperand(i: ExtOpNum);
2194 // Use MO operand flags to determine if MO
2195 // has the HMOTF_ConstExtended flag set.
2196 if (MO.getTargetFlags() & HexagonII::HMOTF_ConstExtended)
2197 return true;
2198 // If this is a Machine BB address we are talking about, and it is
2199 // not marked as extended, say so.
2200 if (MO.isMBB())
2201 return false;
2202
2203 // We could be using an instruction with an extendable immediate and shoehorn
2204 // a global address into it. If it is a global address it will be constant
2205 // extended. We do this for COMBINE.
2206 if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
2207 MO.isJTI() || MO.isCPI() || MO.isFPImm())
2208 return true;
2209
2210 // If the extendable operand is not 'Immediate' type, the instruction should
2211 // have 'isExtended' flag set.
2212 assert(MO.isImm() && "Extendable operand must be Immediate type");
2213
2214 int64_t Value = MO.getImm();
2215 if ((F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask) {
2216 int32_t SValue = Value;
2217 int32_t MinValue = getMinValue(MI);
2218 int32_t MaxValue = getMaxValue(MI);
2219 return SValue < MinValue || SValue > MaxValue;
2220 }
2221 uint32_t UValue = Value;
2222 uint32_t MinValue = getMinValue(MI);
2223 uint32_t MaxValue = getMaxValue(MI);
2224 return UValue < MinValue || UValue > MaxValue;
2225}
2226
2227bool HexagonInstrInfo::isDeallocRet(const MachineInstr &MI) const {
2228 switch (MI.getOpcode()) {
2229 case Hexagon::L4_return:
2230 case Hexagon::L4_return_t:
2231 case Hexagon::L4_return_f:
2232 case Hexagon::L4_return_tnew_pnt:
2233 case Hexagon::L4_return_fnew_pnt:
2234 case Hexagon::L4_return_tnew_pt:
2235 case Hexagon::L4_return_fnew_pt:
2236 return true;
2237 }
2238 return false;
2239}
2240
2241// Return true when ConsMI uses a register defined by ProdMI.
2242bool HexagonInstrInfo::isDependent(const MachineInstr &ProdMI,
2243 const MachineInstr &ConsMI) const {
2244 if (!ProdMI.getDesc().getNumDefs())
2245 return false;
2246 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
2247
2248 SmallVector<Register, 4> DefsA;
2249 SmallVector<Register, 4> DefsB;
2250 SmallVector<Register, 8> UsesA;
2251 SmallVector<Register, 8> UsesB;
2252
2253 parseOperands(MI: ProdMI, Defs&: DefsA, Uses&: UsesA);
2254 parseOperands(MI: ConsMI, Defs&: DefsB, Uses&: UsesB);
2255
2256 for (auto &RegA : DefsA)
2257 for (auto &RegB : UsesB) {
2258 // True data dependency.
2259 if (RegA == RegB)
2260 return true;
2261
2262 if (RegA.isPhysical() && llvm::is_contained(Range: HRI.subregs(Reg: RegA), Element: RegB))
2263 return true;
2264
2265 if (RegB.isPhysical() && llvm::is_contained(Range: HRI.subregs(Reg: RegB), Element: RegA))
2266 return true;
2267 }
2268
2269 return false;
2270}
2271
2272// Returns true if the instruction is already a .cur.
2273bool HexagonInstrInfo::isDotCurInst(const MachineInstr &MI) const {
2274 switch (MI.getOpcode()) {
2275 case Hexagon::V6_vL32b_cur_pi:
2276 case Hexagon::V6_vL32b_cur_ai:
2277 return true;
2278 }
2279 return false;
2280}
2281
2282// Returns true, if any one of the operands is a dot new
2283// insn, whether it is predicated dot new or register dot new.
2284bool HexagonInstrInfo::isDotNewInst(const MachineInstr &MI) const {
2285 if (isNewValueInst(MI) || (isPredicated(MI) && isPredicatedNew(MI)))
2286 return true;
2287
2288 return false;
2289}
2290
2291/// Symmetrical. See if these two instructions are fit for duplex pair.
2292bool HexagonInstrInfo::isDuplexPair(const MachineInstr &MIa,
2293 const MachineInstr &MIb) const {
2294 HexagonII::SubInstructionGroup MIaG = getDuplexCandidateGroup(MI: MIa);
2295 HexagonII::SubInstructionGroup MIbG = getDuplexCandidateGroup(MI: MIb);
2296 return (isDuplexPairMatch(Ga: MIaG, Gb: MIbG) || isDuplexPairMatch(Ga: MIbG, Gb: MIaG));
2297}
2298
2299bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {
2300 return (Opcode == Hexagon::ENDLOOP0 ||
2301 Opcode == Hexagon::ENDLOOP1);
2302}
2303
2304bool HexagonInstrInfo::isExpr(unsigned OpType) const {
2305 switch(OpType) {
2306 case MachineOperand::MO_MachineBasicBlock:
2307 case MachineOperand::MO_GlobalAddress:
2308 case MachineOperand::MO_ExternalSymbol:
2309 case MachineOperand::MO_JumpTableIndex:
2310 case MachineOperand::MO_ConstantPoolIndex:
2311 case MachineOperand::MO_BlockAddress:
2312 return true;
2313 default:
2314 return false;
2315 }
2316}
2317
2318bool HexagonInstrInfo::isExtendable(const MachineInstr &MI) const {
2319 const MCInstrDesc &MID = MI.getDesc();
2320 const uint64_t F = MID.TSFlags;
2321 if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
2322 return true;
2323
2324 // TODO: This is largely obsolete now. Will need to be removed
2325 // in consecutive patches.
2326 switch (MI.getOpcode()) {
2327 // PS_fi and PS_fia remain special cases.
2328 case Hexagon::PS_fi:
2329 case Hexagon::PS_fia:
2330 return true;
2331 default:
2332 return false;
2333 }
2334 return false;
2335}
2336
2337// This returns true in two cases:
2338// - The OP code itself indicates that this is an extended instruction.
2339// - One of MOs has been marked with HMOTF_ConstExtended flag.
2340bool HexagonInstrInfo::isExtended(const MachineInstr &MI) const {
2341 // First check if this is permanently extended op code.
2342 const uint64_t F = MI.getDesc().TSFlags;
2343 if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
2344 return true;
2345 // Use MO operand flags to determine if one of MI's operands
2346 // has HMOTF_ConstExtended flag set.
2347 for (const MachineOperand &MO : MI.operands())
2348 if (MO.getTargetFlags() & HexagonII::HMOTF_ConstExtended)
2349 return true;
2350 return false;
2351}
2352
2353bool HexagonInstrInfo::isFloat(const MachineInstr &MI) const {
2354 unsigned Opcode = MI.getOpcode();
2355 const uint64_t F = get(Opcode).TSFlags;
2356 return (F >> HexagonII::FPPos) & HexagonII::FPMask;
2357}
2358
2359// No V60 HVX VMEM with A_INDIRECT.
2360bool HexagonInstrInfo::isHVXMemWithAIndirect(const MachineInstr &I,
2361 const MachineInstr &J) const {
2362 if (!isHVXVec(MI: I))
2363 return false;
2364 if (!I.mayLoad() && !I.mayStore())
2365 return false;
2366 return J.isIndirectBranch() || isIndirectCall(MI: J) || isIndirectL4Return(MI: J);
2367}
2368
2369bool HexagonInstrInfo::isIndirectCall(const MachineInstr &MI) const {
2370 switch (MI.getOpcode()) {
2371 case Hexagon::J2_callr:
2372 case Hexagon::J2_callrf:
2373 case Hexagon::J2_callrt:
2374 case Hexagon::PS_call_nr:
2375 return true;
2376 }
2377 return false;
2378}
2379
2380bool HexagonInstrInfo::isIndirectL4Return(const MachineInstr &MI) const {
2381 switch (MI.getOpcode()) {
2382 case Hexagon::L4_return:
2383 case Hexagon::L4_return_t:
2384 case Hexagon::L4_return_f:
2385 case Hexagon::L4_return_fnew_pnt:
2386 case Hexagon::L4_return_fnew_pt:
2387 case Hexagon::L4_return_tnew_pnt:
2388 case Hexagon::L4_return_tnew_pt:
2389 return true;
2390 }
2391 return false;
2392}
2393
2394bool HexagonInstrInfo::isJumpR(const MachineInstr &MI) const {
2395 switch (MI.getOpcode()) {
2396 case Hexagon::J2_jumpr:
2397 case Hexagon::J2_jumprt:
2398 case Hexagon::J2_jumprf:
2399 case Hexagon::J2_jumprtnewpt:
2400 case Hexagon::J2_jumprfnewpt:
2401 case Hexagon::J2_jumprtnew:
2402 case Hexagon::J2_jumprfnew:
2403 return true;
2404 }
2405 return false;
2406}
2407
2408// Return true if a given MI can accommodate given offset.
2409// Use abs estimate as oppose to the exact number.
2410// TODO: This will need to be changed to use MC level
2411// definition of instruction extendable field size.
2412bool HexagonInstrInfo::isJumpWithinBranchRange(const MachineInstr &MI,
2413 unsigned offset) const {
2414 // This selection of jump instructions matches to that what
2415 // analyzeBranch can parse, plus NVJ.
2416 if (isNewValueJump(MI)) // r9:2
2417 return isInt<11>(x: offset);
2418
2419 switch (MI.getOpcode()) {
2420 // Still missing Jump to address condition on register value.
2421 default:
2422 return false;
2423 case Hexagon::J2_jump: // bits<24> dst; // r22:2
2424 case Hexagon::J2_call:
2425 case Hexagon::PS_call_nr:
2426 return isInt<24>(x: offset);
2427 case Hexagon::J2_jumpt: //bits<17> dst; // r15:2
2428 case Hexagon::J2_jumpf:
2429 case Hexagon::J2_jumptnew:
2430 case Hexagon::J2_jumptnewpt:
2431 case Hexagon::J2_jumpfnew:
2432 case Hexagon::J2_jumpfnewpt:
2433 case Hexagon::J2_callt:
2434 case Hexagon::J2_callf:
2435 return isInt<17>(x: offset);
2436 case Hexagon::J2_loop0i:
2437 case Hexagon::J2_loop0iext:
2438 case Hexagon::J2_loop0r:
2439 case Hexagon::J2_loop0rext:
2440 case Hexagon::J2_loop1i:
2441 case Hexagon::J2_loop1iext:
2442 case Hexagon::J2_loop1r:
2443 case Hexagon::J2_loop1rext:
2444 return isInt<9>(x: offset);
2445 // TODO: Add all the compound branches here. Can we do this in Relation model?
2446 case Hexagon::J4_cmpeqi_tp0_jump_nt:
2447 case Hexagon::J4_cmpeqi_tp1_jump_nt:
2448 case Hexagon::J4_cmpeqn1_tp0_jump_nt:
2449 case Hexagon::J4_cmpeqn1_tp1_jump_nt:
2450 return isInt<11>(x: offset);
2451 }
2452}
2453
2454bool HexagonInstrInfo::isLateSourceInstr(const MachineInstr &MI) const {
2455 // Instructions with iclass A_CVI_VX and attribute A_CVI_LATE uses a multiply
2456 // resource, but all operands can be received late like an ALU instruction.
2457 return getType(MI) == HexagonII::TypeCVI_VX_LATE;
2458}
2459
2460bool HexagonInstrInfo::isLoopN(const MachineInstr &MI) const {
2461 unsigned Opcode = MI.getOpcode();
2462 return Opcode == Hexagon::J2_loop0i ||
2463 Opcode == Hexagon::J2_loop0r ||
2464 Opcode == Hexagon::J2_loop0iext ||
2465 Opcode == Hexagon::J2_loop0rext ||
2466 Opcode == Hexagon::J2_loop1i ||
2467 Opcode == Hexagon::J2_loop1r ||
2468 Opcode == Hexagon::J2_loop1iext ||
2469 Opcode == Hexagon::J2_loop1rext;
2470}
2471
2472bool HexagonInstrInfo::isMemOp(const MachineInstr &MI) const {
2473 switch (MI.getOpcode()) {
2474 default: return false;
2475 case Hexagon::L4_iadd_memopw_io:
2476 case Hexagon::L4_isub_memopw_io:
2477 case Hexagon::L4_add_memopw_io:
2478 case Hexagon::L4_sub_memopw_io:
2479 case Hexagon::L4_and_memopw_io:
2480 case Hexagon::L4_or_memopw_io:
2481 case Hexagon::L4_iadd_memoph_io:
2482 case Hexagon::L4_isub_memoph_io:
2483 case Hexagon::L4_add_memoph_io:
2484 case Hexagon::L4_sub_memoph_io:
2485 case Hexagon::L4_and_memoph_io:
2486 case Hexagon::L4_or_memoph_io:
2487 case Hexagon::L4_iadd_memopb_io:
2488 case Hexagon::L4_isub_memopb_io:
2489 case Hexagon::L4_add_memopb_io:
2490 case Hexagon::L4_sub_memopb_io:
2491 case Hexagon::L4_and_memopb_io:
2492 case Hexagon::L4_or_memopb_io:
2493 case Hexagon::L4_ior_memopb_io:
2494 case Hexagon::L4_ior_memoph_io:
2495 case Hexagon::L4_ior_memopw_io:
2496 case Hexagon::L4_iand_memopb_io:
2497 case Hexagon::L4_iand_memoph_io:
2498 case Hexagon::L4_iand_memopw_io:
2499 return true;
2500 }
2501 return false;
2502}
2503
2504bool HexagonInstrInfo::isNewValue(const MachineInstr &MI) const {
2505 const uint64_t F = MI.getDesc().TSFlags;
2506 return (F >> HexagonII::NewValuePos) & HexagonII::NewValueMask;
2507}
2508
2509bool HexagonInstrInfo::isNewValue(unsigned Opcode) const {
2510 const uint64_t F = get(Opcode).TSFlags;
2511 return (F >> HexagonII::NewValuePos) & HexagonII::NewValueMask;
2512}
2513
2514bool HexagonInstrInfo::isNewValueInst(const MachineInstr &MI) const {
2515 return isNewValueJump(MI) || isNewValueStore(MI);
2516}
2517
2518bool HexagonInstrInfo::isNewValueJump(const MachineInstr &MI) const {
2519 return isNewValue(MI) && MI.isBranch();
2520}
2521
2522bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const {
2523 return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
2524}
2525
2526bool HexagonInstrInfo::isNewValueStore(const MachineInstr &MI) const {
2527 const uint64_t F = MI.getDesc().TSFlags;
2528 return (F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask;
2529}
2530
2531bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
2532 const uint64_t F = get(Opcode).TSFlags;
2533 return (F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask;
2534}
2535
2536// Returns true if a particular operand is extendable for an instruction.
2537bool HexagonInstrInfo::isOperandExtended(const MachineInstr &MI,
2538 unsigned OperandNum) const {
2539 const uint64_t F = MI.getDesc().TSFlags;
2540 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
2541 == OperandNum;
2542}
2543
2544bool HexagonInstrInfo::isPredicatedNew(const MachineInstr &MI) const {
2545 const uint64_t F = MI.getDesc().TSFlags;
2546 assert(isPredicated(MI));
2547 return (F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask;
2548}
2549
2550bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
2551 const uint64_t F = get(Opcode).TSFlags;
2552 assert(isPredicated(Opcode));
2553 return (F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask;
2554}
2555
2556bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr &MI) const {
2557 const uint64_t F = MI.getDesc().TSFlags;
2558 return !((F >> HexagonII::PredicatedFalsePos) &
2559 HexagonII::PredicatedFalseMask);
2560}
2561
2562bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
2563 const uint64_t F = get(Opcode).TSFlags;
2564 // Make sure that the instruction is predicated.
2565 assert((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
2566 return !((F >> HexagonII::PredicatedFalsePos) &
2567 HexagonII::PredicatedFalseMask);
2568}
2569
2570bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
2571 const uint64_t F = get(Opcode).TSFlags;
2572 return (F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask;
2573}
2574
2575bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const {
2576 const uint64_t F = get(Opcode).TSFlags;
2577 return (F >> HexagonII::PredicateLatePos) & HexagonII::PredicateLateMask;
2578}
2579
2580bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {
2581 const uint64_t F = get(Opcode).TSFlags;
2582 assert(get(Opcode).isBranch() &&
2583 (isPredicatedNew(Opcode) || isNewValue(Opcode)));
2584 return (F >> HexagonII::TakenPos) & HexagonII::TakenMask;
2585}
2586
2587bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr &MI) const {
2588 return MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
2589 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
2590 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
2591 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
2592}
2593
2594bool HexagonInstrInfo::isSignExtendingLoad(const MachineInstr &MI) const {
2595 switch (MI.getOpcode()) {
2596 // Byte
2597 case Hexagon::L2_loadrb_io:
2598 case Hexagon::L4_loadrb_ur:
2599 case Hexagon::L4_loadrb_ap:
2600 case Hexagon::L2_loadrb_pr:
2601 case Hexagon::L2_loadrb_pbr:
2602 case Hexagon::L2_loadrb_pi:
2603 case Hexagon::L2_loadrb_pci:
2604 case Hexagon::L2_loadrb_pcr:
2605 case Hexagon::L2_loadbsw2_io:
2606 case Hexagon::L4_loadbsw2_ur:
2607 case Hexagon::L4_loadbsw2_ap:
2608 case Hexagon::L2_loadbsw2_pr:
2609 case Hexagon::L2_loadbsw2_pbr:
2610 case Hexagon::L2_loadbsw2_pi:
2611 case Hexagon::L2_loadbsw2_pci:
2612 case Hexagon::L2_loadbsw2_pcr:
2613 case Hexagon::L2_loadbsw4_io:
2614 case Hexagon::L4_loadbsw4_ur:
2615 case Hexagon::L4_loadbsw4_ap:
2616 case Hexagon::L2_loadbsw4_pr:
2617 case Hexagon::L2_loadbsw4_pbr:
2618 case Hexagon::L2_loadbsw4_pi:
2619 case Hexagon::L2_loadbsw4_pci:
2620 case Hexagon::L2_loadbsw4_pcr:
2621 case Hexagon::L4_loadrb_rr:
2622 case Hexagon::L2_ploadrbt_io:
2623 case Hexagon::L2_ploadrbt_pi:
2624 case Hexagon::L2_ploadrbf_io:
2625 case Hexagon::L2_ploadrbf_pi:
2626 case Hexagon::L2_ploadrbtnew_io:
2627 case Hexagon::L2_ploadrbfnew_io:
2628 case Hexagon::L4_ploadrbt_rr:
2629 case Hexagon::L4_ploadrbf_rr:
2630 case Hexagon::L4_ploadrbtnew_rr:
2631 case Hexagon::L4_ploadrbfnew_rr:
2632 case Hexagon::L2_ploadrbtnew_pi:
2633 case Hexagon::L2_ploadrbfnew_pi:
2634 case Hexagon::L4_ploadrbt_abs:
2635 case Hexagon::L4_ploadrbf_abs:
2636 case Hexagon::L4_ploadrbtnew_abs:
2637 case Hexagon::L4_ploadrbfnew_abs:
2638 case Hexagon::L2_loadrbgp:
2639 // Half
2640 case Hexagon::L2_loadrh_io:
2641 case Hexagon::L4_loadrh_ur:
2642 case Hexagon::L4_loadrh_ap:
2643 case Hexagon::L2_loadrh_pr:
2644 case Hexagon::L2_loadrh_pbr:
2645 case Hexagon::L2_loadrh_pi:
2646 case Hexagon::L2_loadrh_pci:
2647 case Hexagon::L2_loadrh_pcr:
2648 case Hexagon::L4_loadrh_rr:
2649 case Hexagon::L2_ploadrht_io:
2650 case Hexagon::L2_ploadrht_pi:
2651 case Hexagon::L2_ploadrhf_io:
2652 case Hexagon::L2_ploadrhf_pi:
2653 case Hexagon::L2_ploadrhtnew_io:
2654 case Hexagon::L2_ploadrhfnew_io:
2655 case Hexagon::L4_ploadrht_rr:
2656 case Hexagon::L4_ploadrhf_rr:
2657 case Hexagon::L4_ploadrhtnew_rr:
2658 case Hexagon::L4_ploadrhfnew_rr:
2659 case Hexagon::L2_ploadrhtnew_pi:
2660 case Hexagon::L2_ploadrhfnew_pi:
2661 case Hexagon::L4_ploadrht_abs:
2662 case Hexagon::L4_ploadrhf_abs:
2663 case Hexagon::L4_ploadrhtnew_abs:
2664 case Hexagon::L4_ploadrhfnew_abs:
2665 case Hexagon::L2_loadrhgp:
2666 return true;
2667 default:
2668 return false;
2669 }
2670}
2671
2672bool HexagonInstrInfo::isSolo(const MachineInstr &MI) const {
2673 const uint64_t F = MI.getDesc().TSFlags;
2674 return (F >> HexagonII::SoloPos) & HexagonII::SoloMask;
2675}
2676
2677bool HexagonInstrInfo::isSpillPredRegOp(const MachineInstr &MI) const {
2678 switch (MI.getOpcode()) {
2679 case Hexagon::STriw_pred:
2680 case Hexagon::LDriw_pred:
2681 return true;
2682 default:
2683 return false;
2684 }
2685}
2686
2687bool HexagonInstrInfo::isTailCall(const MachineInstr &MI) const {
2688 if (!MI.isBranch())
2689 return false;
2690
2691 for (auto &Op : MI.operands())
2692 if (Op.isGlobal() || Op.isSymbol())
2693 return true;
2694 return false;
2695}
2696
2697// Returns true when SU has a timing class TC1.
2698bool HexagonInstrInfo::isTC1(const MachineInstr &MI) const {
2699 unsigned SchedClass = MI.getDesc().getSchedClass();
2700 return is_TC1(SchedClass);
2701}
2702
2703bool HexagonInstrInfo::isTC2(const MachineInstr &MI) const {
2704 unsigned SchedClass = MI.getDesc().getSchedClass();
2705 return is_TC2(SchedClass);
2706}
2707
2708bool HexagonInstrInfo::isTC2Early(const MachineInstr &MI) const {
2709 unsigned SchedClass = MI.getDesc().getSchedClass();
2710 return is_TC2early(SchedClass);
2711}
2712
2713bool HexagonInstrInfo::isTC4x(const MachineInstr &MI) const {
2714 unsigned SchedClass = MI.getDesc().getSchedClass();
2715 return is_TC4x(SchedClass);
2716}
2717
2718// Schedule this ASAP.
2719bool HexagonInstrInfo::isToBeScheduledASAP(const MachineInstr &MI1,
2720 const MachineInstr &MI2) const {
2721 if (mayBeCurLoad(MI: MI1)) {
2722 // if (result of SU is used in Next) return true;
2723 Register DstReg = MI1.getOperand(i: 0).getReg();
2724 int N = MI2.getNumOperands();
2725 for (int I = 0; I < N; I++)
2726 if (MI2.getOperand(i: I).isReg() && DstReg == MI2.getOperand(i: I).getReg())
2727 return true;
2728 }
2729 if (mayBeNewStore(MI: MI2))
2730 if (MI2.getOpcode() == Hexagon::V6_vS32b_pi)
2731 if (MI1.getOperand(i: 0).isReg() && MI2.getOperand(i: 3).isReg() &&
2732 MI1.getOperand(i: 0).getReg() == MI2.getOperand(i: 3).getReg())
2733 return true;
2734 return false;
2735}
2736
2737bool HexagonInstrInfo::isHVXVec(const MachineInstr &MI) const {
2738 const uint64_t V = getType(MI);
2739 return HexagonII::TypeCVI_FIRST <= V && V <= HexagonII::TypeCVI_LAST;
2740}
2741
2742// Check if the Offset is a valid auto-inc imm by Load/Store Type.
2743bool HexagonInstrInfo::isValidAutoIncImm(const EVT VT, int Offset) const {
2744 int Size = VT.getSizeInBits() / 8;
2745 if (Offset % Size != 0)
2746 return false;
2747 int Count = Offset / Size;
2748
2749 switch (VT.getSimpleVT().SimpleTy) {
2750 // For scalars the auto-inc is s4
2751 case MVT::i8:
2752 case MVT::i16:
2753 case MVT::i32:
2754 case MVT::i64:
2755 case MVT::f32:
2756 case MVT::f64:
2757 case MVT::v2i16:
2758 case MVT::v2i32:
2759 case MVT::v4i8:
2760 case MVT::v4i16:
2761 case MVT::v8i8:
2762 return isInt<4>(x: Count);
2763 // For HVX vectors the auto-inc is s3
2764 case MVT::v64i8:
2765 case MVT::v32i16:
2766 case MVT::v16i32:
2767 case MVT::v8i64:
2768 case MVT::v128i8:
2769 case MVT::v64i16:
2770 case MVT::v32i32:
2771 case MVT::v16i64:
2772 return isInt<3>(x: Count);
2773 default:
2774 break;
2775 }
2776
2777 llvm_unreachable("Not an valid type!");
2778}
2779
2780bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
2781 const TargetRegisterInfo *TRI, bool Extend) const {
2782 // This function is to check whether the "Offset" is in the correct range of
2783 // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
2784 // inserted to calculate the final address. Due to this reason, the function
2785 // assumes that the "Offset" has correct alignment.
2786 // We used to assert if the offset was not properly aligned, however,
2787 // there are cases where a misaligned pointer recast can cause this
2788 // problem, and we need to allow for it. The front end warns of such
2789 // misaligns with respect to load size.
2790 switch (Opcode) {
2791 case Hexagon::PS_vstorerq_ai:
2792 case Hexagon::PS_vstorerv_ai:
2793 case Hexagon::PS_vstorerw_ai:
2794 case Hexagon::PS_vstorerw_nt_ai:
2795 case Hexagon::PS_vloadrq_ai:
2796 case Hexagon::PS_vloadrv_ai:
2797 case Hexagon::PS_vloadrw_ai:
2798 case Hexagon::PS_vloadrw_nt_ai:
2799 case Hexagon::V6_vL32b_ai:
2800 case Hexagon::V6_vS32b_ai:
2801 case Hexagon::V6_vS32b_pred_ai:
2802 case Hexagon::V6_vS32b_npred_ai:
2803 case Hexagon::V6_vS32b_qpred_ai:
2804 case Hexagon::V6_vS32b_nqpred_ai:
2805 case Hexagon::V6_vS32b_new_ai:
2806 case Hexagon::V6_vS32b_new_pred_ai:
2807 case Hexagon::V6_vS32b_new_npred_ai:
2808 case Hexagon::V6_vS32b_nt_pred_ai:
2809 case Hexagon::V6_vS32b_nt_npred_ai:
2810 case Hexagon::V6_vS32b_nt_new_ai:
2811 case Hexagon::V6_vS32b_nt_new_pred_ai:
2812 case Hexagon::V6_vS32b_nt_new_npred_ai:
2813 case Hexagon::V6_vS32b_nt_qpred_ai:
2814 case Hexagon::V6_vS32b_nt_nqpred_ai:
2815 case Hexagon::V6_vL32b_nt_ai:
2816 case Hexagon::V6_vS32b_nt_ai:
2817 case Hexagon::V6_vL32Ub_ai:
2818 case Hexagon::V6_vS32Ub_ai:
2819 case Hexagon::V6_vL32b_cur_ai:
2820 case Hexagon::V6_vL32b_tmp_ai:
2821 case Hexagon::V6_vL32b_pred_ai:
2822 case Hexagon::V6_vL32b_npred_ai:
2823 case Hexagon::V6_vL32b_cur_pred_ai:
2824 case Hexagon::V6_vL32b_cur_npred_ai:
2825 case Hexagon::V6_vL32b_tmp_pred_ai:
2826 case Hexagon::V6_vL32b_tmp_npred_ai:
2827 case Hexagon::V6_vL32b_nt_cur_ai:
2828 case Hexagon::V6_vL32b_nt_tmp_ai:
2829 case Hexagon::V6_vL32b_nt_pred_ai:
2830 case Hexagon::V6_vL32b_nt_npred_ai:
2831 case Hexagon::V6_vL32b_nt_cur_pred_ai:
2832 case Hexagon::V6_vL32b_nt_cur_npred_ai:
2833 case Hexagon::V6_vL32b_nt_tmp_pred_ai:
2834 case Hexagon::V6_vL32b_nt_tmp_npred_ai:
2835 case Hexagon::V6_vS32Ub_pred_ai:
2836 case Hexagon::V6_vS32Ub_npred_ai:
2837 case Hexagon::V6_vgathermh_pseudo:
2838 case Hexagon::V6_vgather_vscatter_mh_pseudo:
2839 case Hexagon::V6_vgathermw_pseudo:
2840 case Hexagon::V6_vgathermhw_pseudo:
2841 case Hexagon::V6_vgathermhq_pseudo:
2842 case Hexagon::V6_vgathermwq_pseudo:
2843 case Hexagon::V6_vgathermhwq_pseudo: {
2844 unsigned VectorSize = TRI->getSpillSize(RC: Hexagon::HvxVRRegClass);
2845 assert(isPowerOf2_32(VectorSize));
2846 if (Offset & (VectorSize-1))
2847 return false;
2848 return isInt<4>(x: Offset >> Log2_32(Value: VectorSize));
2849 }
2850
2851 case Hexagon::J2_loop0i:
2852 case Hexagon::J2_loop1i:
2853 return isUInt<10>(x: Offset);
2854
2855 case Hexagon::S4_storeirb_io:
2856 case Hexagon::S4_storeirbt_io:
2857 case Hexagon::S4_storeirbf_io:
2858 return isUInt<6>(x: Offset);
2859
2860 case Hexagon::S4_storeirh_io:
2861 case Hexagon::S4_storeirht_io:
2862 case Hexagon::S4_storeirhf_io:
2863 return isShiftedUInt<6,1>(x: Offset);
2864
2865 case Hexagon::S4_storeiri_io:
2866 case Hexagon::S4_storeirit_io:
2867 case Hexagon::S4_storeirif_io:
2868 return isShiftedUInt<6,2>(x: Offset);
2869 // Handle these two compare instructions that are not extendable.
2870 case Hexagon::A4_cmpbeqi:
2871 return isUInt<8>(x: Offset);
2872 case Hexagon::A4_cmpbgti:
2873 return isInt<8>(x: Offset);
2874 }
2875
2876 if (Extend)
2877 return true;
2878
2879 switch (Opcode) {
2880 case Hexagon::L2_loadri_io:
2881 case Hexagon::S2_storeri_io:
2882 return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
2883 (Offset <= Hexagon_MEMW_OFFSET_MAX);
2884
2885 case Hexagon::L2_loadrd_io:
2886 case Hexagon::S2_storerd_io:
2887 return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
2888 (Offset <= Hexagon_MEMD_OFFSET_MAX);
2889
2890 case Hexagon::L2_loadrh_io:
2891 case Hexagon::L2_loadruh_io:
2892 case Hexagon::S2_storerh_io:
2893 case Hexagon::S2_storerf_io:
2894 return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2895 (Offset <= Hexagon_MEMH_OFFSET_MAX);
2896
2897 case Hexagon::L2_loadrb_io:
2898 case Hexagon::L2_loadrub_io:
2899 case Hexagon::S2_storerb_io:
2900 return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2901 (Offset <= Hexagon_MEMB_OFFSET_MAX);
2902
2903 case Hexagon::A2_addi:
2904 return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2905 (Offset <= Hexagon_ADDI_OFFSET_MAX);
2906
2907 case Hexagon::L4_iadd_memopw_io:
2908 case Hexagon::L4_isub_memopw_io:
2909 case Hexagon::L4_add_memopw_io:
2910 case Hexagon::L4_sub_memopw_io:
2911 case Hexagon::L4_iand_memopw_io:
2912 case Hexagon::L4_ior_memopw_io:
2913 case Hexagon::L4_and_memopw_io:
2914 case Hexagon::L4_or_memopw_io:
2915 return (0 <= Offset && Offset <= 255);
2916
2917 case Hexagon::L4_iadd_memoph_io:
2918 case Hexagon::L4_isub_memoph_io:
2919 case Hexagon::L4_add_memoph_io:
2920 case Hexagon::L4_sub_memoph_io:
2921 case Hexagon::L4_iand_memoph_io:
2922 case Hexagon::L4_ior_memoph_io:
2923 case Hexagon::L4_and_memoph_io:
2924 case Hexagon::L4_or_memoph_io:
2925 return (0 <= Offset && Offset <= 127);
2926
2927 case Hexagon::L4_iadd_memopb_io:
2928 case Hexagon::L4_isub_memopb_io:
2929 case Hexagon::L4_add_memopb_io:
2930 case Hexagon::L4_sub_memopb_io:
2931 case Hexagon::L4_iand_memopb_io:
2932 case Hexagon::L4_ior_memopb_io:
2933 case Hexagon::L4_and_memopb_io:
2934 case Hexagon::L4_or_memopb_io:
2935 return (0 <= Offset && Offset <= 63);
2936
2937 // LDriw_xxx and STriw_xxx are pseudo operations, so it has to take offset of
2938 // any size. Later pass knows how to handle it.
2939 case Hexagon::STriw_pred:
2940 case Hexagon::LDriw_pred:
2941 case Hexagon::STriw_ctr:
2942 case Hexagon::LDriw_ctr:
2943 return true;
2944
2945 case Hexagon::PS_fi:
2946 case Hexagon::PS_fia:
2947 case Hexagon::INLINEASM:
2948 return true;
2949
2950 case Hexagon::L2_ploadrbt_io:
2951 case Hexagon::L2_ploadrbf_io:
2952 case Hexagon::L2_ploadrubt_io:
2953 case Hexagon::L2_ploadrubf_io:
2954 case Hexagon::S2_pstorerbt_io:
2955 case Hexagon::S2_pstorerbf_io:
2956 return isUInt<6>(x: Offset);
2957
2958 case Hexagon::L2_ploadrht_io:
2959 case Hexagon::L2_ploadrhf_io:
2960 case Hexagon::L2_ploadruht_io:
2961 case Hexagon::L2_ploadruhf_io:
2962 case Hexagon::S2_pstorerht_io:
2963 case Hexagon::S2_pstorerhf_io:
2964 case Hexagon::S2_pstorerft_io:
2965 case Hexagon::S2_pstorerff_io:
2966 return isShiftedUInt<6,1>(x: Offset);
2967
2968 case Hexagon::L2_ploadrit_io:
2969 case Hexagon::L2_ploadrif_io:
2970 case Hexagon::S2_pstorerit_io:
2971 case Hexagon::S2_pstorerif_io:
2972 return isShiftedUInt<6,2>(x: Offset);
2973
2974 case Hexagon::L2_ploadrdt_io:
2975 case Hexagon::L2_ploadrdf_io:
2976 case Hexagon::S2_pstorerdt_io:
2977 case Hexagon::S2_pstorerdf_io:
2978 return isShiftedUInt<6,3>(x: Offset);
2979
2980 case Hexagon::L2_loadbsw2_io:
2981 case Hexagon::L2_loadbzw2_io:
2982 return isShiftedInt<11,1>(x: Offset);
2983
2984 case Hexagon::L2_loadbsw4_io:
2985 case Hexagon::L2_loadbzw4_io:
2986 return isShiftedInt<11,2>(x: Offset);
2987 } // switch
2988
2989 dbgs() << "Failed Opcode is : " << Opcode << " (" << getName(Opcode)
2990 << ")\n";
2991 llvm_unreachable("No offset range is defined for this opcode. "
2992 "Please define it in the above switch statement!");
2993}
2994
2995bool HexagonInstrInfo::isVecAcc(const MachineInstr &MI) const {
2996 return isHVXVec(MI) && isAccumulator(MI);
2997}
2998
2999bool HexagonInstrInfo::isVecALU(const MachineInstr &MI) const {
3000 const uint64_t F = get(Opcode: MI.getOpcode()).TSFlags;
3001 const uint64_t V = ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
3002 return
3003 V == HexagonII::TypeCVI_VA ||
3004 V == HexagonII::TypeCVI_VA_DV;
3005}
3006
3007bool HexagonInstrInfo::isVecUsableNextPacket(const MachineInstr &ProdMI,
3008 const MachineInstr &ConsMI) const {
3009 if (EnableACCForwarding && isVecAcc(MI: ProdMI) && isVecAcc(MI: ConsMI))
3010 return true;
3011
3012 if (EnableALUForwarding && (isVecALU(MI: ConsMI) || isLateSourceInstr(MI: ConsMI)))
3013 return true;
3014
3015 if (mayBeNewStore(MI: ConsMI))
3016 return true;
3017
3018 return false;
3019}
3020
3021bool HexagonInstrInfo::isZeroExtendingLoad(const MachineInstr &MI) const {
3022 switch (MI.getOpcode()) {
3023 // Byte
3024 case Hexagon::L2_loadrub_io:
3025 case Hexagon::L4_loadrub_ur:
3026 case Hexagon::L4_loadrub_ap:
3027 case Hexagon::L2_loadrub_pr:
3028 case Hexagon::L2_loadrub_pbr:
3029 case Hexagon::L2_loadrub_pi:
3030 case Hexagon::L2_loadrub_pci:
3031 case Hexagon::L2_loadrub_pcr:
3032 case Hexagon::L2_loadbzw2_io:
3033 case Hexagon::L4_loadbzw2_ur:
3034 case Hexagon::L4_loadbzw2_ap:
3035 case Hexagon::L2_loadbzw2_pr:
3036 case Hexagon::L2_loadbzw2_pbr:
3037 case Hexagon::L2_loadbzw2_pi:
3038 case Hexagon::L2_loadbzw2_pci:
3039 case Hexagon::L2_loadbzw2_pcr:
3040 case Hexagon::L2_loadbzw4_io:
3041 case Hexagon::L4_loadbzw4_ur:
3042 case Hexagon::L4_loadbzw4_ap:
3043 case Hexagon::L2_loadbzw4_pr:
3044 case Hexagon::L2_loadbzw4_pbr:
3045 case Hexagon::L2_loadbzw4_pi:
3046 case Hexagon::L2_loadbzw4_pci:
3047 case Hexagon::L2_loadbzw4_pcr:
3048 case Hexagon::L4_loadrub_rr:
3049 case Hexagon::L2_ploadrubt_io:
3050 case Hexagon::L2_ploadrubt_pi:
3051 case Hexagon::L2_ploadrubf_io:
3052 case Hexagon::L2_ploadrubf_pi:
3053 case Hexagon::L2_ploadrubtnew_io:
3054 case Hexagon::L2_ploadrubfnew_io:
3055 case Hexagon::L4_ploadrubt_rr:
3056 case Hexagon::L4_ploadrubf_rr:
3057 case Hexagon::L4_ploadrubtnew_rr:
3058 case Hexagon::L4_ploadrubfnew_rr:
3059 case Hexagon::L2_ploadrubtnew_pi:
3060 case Hexagon::L2_ploadrubfnew_pi:
3061 case Hexagon::L4_ploadrubt_abs:
3062 case Hexagon::L4_ploadrubf_abs:
3063 case Hexagon::L4_ploadrubtnew_abs:
3064 case Hexagon::L4_ploadrubfnew_abs:
3065 case Hexagon::L2_loadrubgp:
3066 // Half
3067 case Hexagon::L2_loadruh_io:
3068 case Hexagon::L4_loadruh_ur:
3069 case Hexagon::L4_loadruh_ap:
3070 case Hexagon::L2_loadruh_pr:
3071 case Hexagon::L2_loadruh_pbr:
3072 case Hexagon::L2_loadruh_pi:
3073 case Hexagon::L2_loadruh_pci:
3074 case Hexagon::L2_loadruh_pcr:
3075 case Hexagon::L4_loadruh_rr:
3076 case Hexagon::L2_ploadruht_io:
3077 case Hexagon::L2_ploadruht_pi:
3078 case Hexagon::L2_ploadruhf_io:
3079 case Hexagon::L2_ploadruhf_pi:
3080 case Hexagon::L2_ploadruhtnew_io:
3081 case Hexagon::L2_ploadruhfnew_io:
3082 case Hexagon::L4_ploadruht_rr:
3083 case Hexagon::L4_ploadruhf_rr:
3084 case Hexagon::L4_ploadruhtnew_rr:
3085 case Hexagon::L4_ploadruhfnew_rr:
3086 case Hexagon::L2_ploadruhtnew_pi:
3087 case Hexagon::L2_ploadruhfnew_pi:
3088 case Hexagon::L4_ploadruht_abs:
3089 case Hexagon::L4_ploadruhf_abs:
3090 case Hexagon::L4_ploadruhtnew_abs:
3091 case Hexagon::L4_ploadruhfnew_abs:
3092 case Hexagon::L2_loadruhgp:
3093 return true;
3094 default:
3095 return false;
3096 }
3097}
3098
3099// Add latency to instruction.
3100bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr &MI1,
3101 const MachineInstr &MI2) const {
3102 if (isHVXVec(MI: MI1) && isHVXVec(MI: MI2))
3103 if (!isVecUsableNextPacket(ProdMI: MI1, ConsMI: MI2))
3104 return true;
3105 return false;
3106}
3107
3108/// Get the base register and byte offset of a load/store instr.
3109bool HexagonInstrInfo::getMemOperandsWithOffsetWidth(
3110 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps,
3111 int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
3112 const TargetRegisterInfo *TRI) const {
3113 OffsetIsScalable = false;
3114 const MachineOperand *BaseOp = getBaseAndOffset(MI: LdSt, Offset, AccessSize&: Width);
3115 if (!BaseOp || !BaseOp->isReg())
3116 return false;
3117 BaseOps.push_back(Elt: BaseOp);
3118 return true;
3119}
3120
3121/// Can these instructions execute at the same time in a bundle.
3122bool HexagonInstrInfo::canExecuteInBundle(const MachineInstr &First,
3123 const MachineInstr &Second) const {
3124 if (Second.mayStore() && First.getOpcode() == Hexagon::S2_allocframe) {
3125 const MachineOperand &Op = Second.getOperand(i: 0);
3126 if (Op.isReg() && Op.isUse() && Op.getReg() == Hexagon::R29)
3127 return true;
3128 }
3129 if (DisableNVSchedule)
3130 return false;
3131 if (mayBeNewStore(MI: Second)) {
3132 // Make sure the definition of the first instruction is the value being
3133 // stored.
3134 const MachineOperand &Stored =
3135 Second.getOperand(i: Second.getNumOperands() - 1);
3136 if (!Stored.isReg())
3137 return false;
3138 for (unsigned i = 0, e = First.getNumOperands(); i < e; ++i) {
3139 const MachineOperand &Op = First.getOperand(i);
3140 if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
3141 return true;
3142 }
3143 }
3144 return false;
3145}
3146
3147bool HexagonInstrInfo::doesNotReturn(const MachineInstr &CallMI) const {
3148 unsigned Opc = CallMI.getOpcode();
3149 return Opc == Hexagon::PS_call_nr || Opc == Hexagon::PS_callr_nr;
3150}
3151
3152bool HexagonInstrInfo::hasEHLabel(const MachineBasicBlock *B) const {
3153 for (auto &I : *B)
3154 if (I.isEHLabel())
3155 return true;
3156 return false;
3157}
3158
3159// Returns true if an instruction can be converted into a non-extended
3160// equivalent instruction.
3161bool HexagonInstrInfo::hasNonExtEquivalent(const MachineInstr &MI) const {
3162 short NonExtOpcode;
3163 // Check if the instruction has a register form that uses register in place
3164 // of the extended operand, if so return that as the non-extended form.
3165 if (Hexagon::getRegForm(Opcode: MI.getOpcode()) >= 0)
3166 return true;
3167
3168 if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
3169 // Check addressing mode and retrieve non-ext equivalent instruction.
3170
3171 switch (getAddrMode(MI)) {
3172 case HexagonII::Absolute:
3173 // Load/store with absolute addressing mode can be converted into
3174 // base+offset mode.
3175 NonExtOpcode = Hexagon::changeAddrMode_abs_io(Opcode: MI.getOpcode());
3176 break;
3177 case HexagonII::BaseImmOffset:
3178 // Load/store with base+offset addressing mode can be converted into
3179 // base+register offset addressing mode. However left shift operand should
3180 // be set to 0.
3181 NonExtOpcode = Hexagon::changeAddrMode_io_rr(Opcode: MI.getOpcode());
3182 break;
3183 case HexagonII::BaseLongOffset:
3184 NonExtOpcode = Hexagon::changeAddrMode_ur_rr(Opcode: MI.getOpcode());
3185 break;
3186 default:
3187 return false;
3188 }
3189 if (NonExtOpcode < 0)
3190 return false;
3191 return true;
3192 }
3193 return false;
3194}
3195
3196bool HexagonInstrInfo::hasPseudoInstrPair(const MachineInstr &MI) const {
3197 return Hexagon::getRealHWInstr(Opcode: MI.getOpcode(),
3198 inInstrType: Hexagon::InstrType_Pseudo) >= 0;
3199}
3200
3201bool HexagonInstrInfo::hasUncondBranch(const MachineBasicBlock *B)
3202 const {
3203 MachineBasicBlock::const_iterator I = B->getFirstTerminator(), E = B->end();
3204 while (I != E) {
3205 if (I->isBarrier())
3206 return true;
3207 ++I;
3208 }
3209 return false;
3210}
3211
3212// Returns true, if a LD insn can be promoted to a cur load.
3213bool HexagonInstrInfo::mayBeCurLoad(const MachineInstr &MI) const {
3214 const uint64_t F = MI.getDesc().TSFlags;
3215 return ((F >> HexagonII::mayCVLoadPos) & HexagonII::mayCVLoadMask) &&
3216 Subtarget.hasV60Ops();
3217}
3218
3219// Returns true, if a ST insn can be promoted to a new-value store.
3220bool HexagonInstrInfo::mayBeNewStore(const MachineInstr &MI) const {
3221 if (MI.mayStore() && !Subtarget.useNewValueStores())
3222 return false;
3223
3224 const uint64_t F = MI.getDesc().TSFlags;
3225 return (F >> HexagonII::mayNVStorePos) & HexagonII::mayNVStoreMask;
3226}
3227
3228bool HexagonInstrInfo::producesStall(const MachineInstr &ProdMI,
3229 const MachineInstr &ConsMI) const {
3230 // There is no stall when ProdMI is not a V60 vector.
3231 if (!isHVXVec(MI: ProdMI))
3232 return false;
3233
3234 // There is no stall when ProdMI and ConsMI are not dependent.
3235 if (!isDependent(ProdMI, ConsMI))
3236 return false;
3237
3238 // When Forward Scheduling is enabled, there is no stall if ProdMI and ConsMI
3239 // are scheduled in consecutive packets.
3240 if (isVecUsableNextPacket(ProdMI, ConsMI))
3241 return false;
3242
3243 return true;
3244}
3245
3246bool HexagonInstrInfo::producesStall(const MachineInstr &MI,
3247 MachineBasicBlock::const_instr_iterator BII) const {
3248 // There is no stall when I is not a V60 vector.
3249 if (!isHVXVec(MI))
3250 return false;
3251
3252 MachineBasicBlock::const_instr_iterator MII = BII;
3253 MachineBasicBlock::const_instr_iterator MIE = MII->getParent()->instr_end();
3254
3255 if (!MII->isBundle())
3256 return producesStall(ProdMI: *MII, ConsMI: MI);
3257
3258 for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
3259 const MachineInstr &J = *MII;
3260 if (producesStall(ProdMI: J, ConsMI: MI))
3261 return true;
3262 }
3263 return false;
3264}
3265
3266bool HexagonInstrInfo::predCanBeUsedAsDotNew(const MachineInstr &MI,
3267 Register PredReg) const {
3268 for (const MachineOperand &MO : MI.operands()) {
3269 // Predicate register must be explicitly defined.
3270 if (MO.isRegMask() && MO.clobbersPhysReg(PhysReg: PredReg))
3271 return false;
3272 if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
3273 return false;
3274 }
3275
3276 // Instruction that produce late predicate cannot be used as sources of
3277 // dot-new.
3278 switch (MI.getOpcode()) {
3279 case Hexagon::A4_addp_c:
3280 case Hexagon::A4_subp_c:
3281 case Hexagon::A4_tlbmatch:
3282 case Hexagon::A5_ACS:
3283 case Hexagon::F2_sfinvsqrta:
3284 case Hexagon::F2_sfrecipa:
3285 case Hexagon::J2_endloop0:
3286 case Hexagon::J2_endloop01:
3287 case Hexagon::J2_ploop1si:
3288 case Hexagon::J2_ploop1sr:
3289 case Hexagon::J2_ploop2si:
3290 case Hexagon::J2_ploop2sr:
3291 case Hexagon::J2_ploop3si:
3292 case Hexagon::J2_ploop3sr:
3293 case Hexagon::S2_cabacdecbin:
3294 case Hexagon::S2_storew_locked:
3295 case Hexagon::S4_stored_locked:
3296 return false;
3297 }
3298 return true;
3299}
3300
3301bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {
3302 return Opcode == Hexagon::J2_jumpt ||
3303 Opcode == Hexagon::J2_jumptpt ||
3304 Opcode == Hexagon::J2_jumpf ||
3305 Opcode == Hexagon::J2_jumpfpt ||
3306 Opcode == Hexagon::J2_jumptnew ||
3307 Opcode == Hexagon::J2_jumpfnew ||
3308 Opcode == Hexagon::J2_jumptnewpt ||
3309 Opcode == Hexagon::J2_jumpfnewpt;
3310}
3311
3312bool HexagonInstrInfo::predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const {
3313 if (Cond.empty() || !isPredicated(Opcode: Cond[0].getImm()))
3314 return false;
3315 return !isPredicatedTrue(Opcode: Cond[0].getImm());
3316}
3317
3318unsigned HexagonInstrInfo::getAddrMode(const MachineInstr &MI) const {
3319 const uint64_t F = MI.getDesc().TSFlags;
3320 return (F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask;
3321}
3322
3323// Returns the base register in a memory access (load/store). The offset is
3324// returned in Offset and the access size is returned in AccessSize.
3325// If the base operand has a subregister or the offset field does not contain
3326// an immediate value, return nullptr.
3327MachineOperand *
3328HexagonInstrInfo::getBaseAndOffset(const MachineInstr &MI, int64_t &Offset,
3329 LocationSize &AccessSize) const {
3330 // Return if it is not a base+offset type instruction or a MemOp.
3331 if (getAddrMode(MI) != HexagonII::BaseImmOffset &&
3332 getAddrMode(MI) != HexagonII::BaseLongOffset && !isMemOp(MI) &&
3333 !isPostIncrement(MI))
3334 return nullptr;
3335
3336 AccessSize = LocationSize::precise(Value: getMemAccessSize(MI));
3337
3338 unsigned BasePos = 0, OffsetPos = 0;
3339 if (!getBaseAndOffsetPosition(MI, BasePos, OffsetPos))
3340 return nullptr;
3341
3342 // Post increment updates its EA after the mem access,
3343 // so we need to treat its offset as zero.
3344 if (isPostIncrement(MI)) {
3345 Offset = 0;
3346 } else {
3347 const MachineOperand &OffsetOp = MI.getOperand(i: OffsetPos);
3348 if (!OffsetOp.isImm())
3349 return nullptr;
3350 Offset = OffsetOp.getImm();
3351 }
3352
3353 const MachineOperand &BaseOp = MI.getOperand(i: BasePos);
3354 if (BaseOp.getSubReg() != 0)
3355 return nullptr;
3356 return &const_cast<MachineOperand&>(BaseOp);
3357}
3358
3359/// Return the position of the base and offset operands for this instruction.
3360bool HexagonInstrInfo::getBaseAndOffsetPosition(const MachineInstr &MI,
3361 unsigned &BasePos, unsigned &OffsetPos) const {
3362 if (!isAddrModeWithOffset(MI) && !isPostIncrement(MI))
3363 return false;
3364
3365 // Deal with memops first.
3366 if (isMemOp(MI)) {
3367 BasePos = 0;
3368 OffsetPos = 1;
3369 } else if (MI.mayStore()) {
3370 BasePos = 0;
3371 OffsetPos = 1;
3372 } else if (MI.mayLoad()) {
3373 BasePos = 1;
3374 OffsetPos = 2;
3375 } else
3376 return false;
3377
3378 if (isPredicated(MI)) {
3379 BasePos++;
3380 OffsetPos++;
3381 }
3382 if (isPostIncrement(MI)) {
3383 BasePos++;
3384 OffsetPos++;
3385 }
3386
3387 if (!MI.getOperand(i: BasePos).isReg() || !MI.getOperand(i: OffsetPos).isImm())
3388 return false;
3389
3390 return true;
3391}
3392
3393// Inserts branching instructions in reverse order of their occurrence.
3394// e.g. jump_t t1 (i1)
3395// jump t2 (i2)
3396// Jumpers = {i2, i1}
3397SmallVector<MachineInstr*, 2> HexagonInstrInfo::getBranchingInstrs(
3398 MachineBasicBlock& MBB) const {
3399 SmallVector<MachineInstr*, 2> Jumpers;
3400 // If the block has no terminators, it just falls into the block after it.
3401 MachineBasicBlock::instr_iterator I = MBB.instr_end();
3402 if (I == MBB.instr_begin())
3403 return Jumpers;
3404
3405 // A basic block may looks like this:
3406 //
3407 // [ insn
3408 // EH_LABEL
3409 // insn
3410 // insn
3411 // insn
3412 // EH_LABEL
3413 // insn ]
3414 //
3415 // It has two succs but does not have a terminator
3416 // Don't know how to handle it.
3417 do {
3418 --I;
3419 if (I->isEHLabel())
3420 return Jumpers;
3421 } while (I != MBB.instr_begin());
3422
3423 I = MBB.instr_end();
3424 --I;
3425
3426 while (I->isDebugInstr()) {
3427 if (I == MBB.instr_begin())
3428 return Jumpers;
3429 --I;
3430 }
3431 if (!isUnpredicatedTerminator(MI: *I))
3432 return Jumpers;
3433
3434 // Get the last instruction in the block.
3435 MachineInstr *LastInst = &*I;
3436 Jumpers.push_back(Elt: LastInst);
3437 MachineInstr *SecondLastInst = nullptr;
3438 // Find one more terminator if present.
3439 do {
3440 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(MI: *I)) {
3441 if (!SecondLastInst) {
3442 SecondLastInst = &*I;
3443 Jumpers.push_back(Elt: SecondLastInst);
3444 } else // This is a third branch.
3445 return Jumpers;
3446 }
3447 if (I == MBB.instr_begin())
3448 break;
3449 --I;
3450 } while (true);
3451 return Jumpers;
3452}
3453
3454// Returns Operand Index for the constant extended instruction.
3455unsigned HexagonInstrInfo::getCExtOpNum(const MachineInstr &MI) const {
3456 const uint64_t F = MI.getDesc().TSFlags;
3457 return (F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask;
3458}
3459
3460// See if instruction could potentially be a duplex candidate.
3461// If so, return its group. Zero otherwise.
3462HexagonII::CompoundGroup HexagonInstrInfo::getCompoundCandidateGroup(
3463 const MachineInstr &MI) const {
3464 Register DstReg, SrcReg, Src1Reg, Src2Reg;
3465
3466 switch (MI.getOpcode()) {
3467 default:
3468 return HexagonII::HCG_None;
3469 //
3470 // Compound pairs.
3471 // "p0=cmp.eq(Rs16,Rt16); if (p0.new) jump:nt #r9:2"
3472 // "Rd16=#U6 ; jump #r9:2"
3473 // "Rd16=Rs16 ; jump #r9:2"
3474 //
3475 case Hexagon::C2_cmpeq:
3476 case Hexagon::C2_cmpgt:
3477 case Hexagon::C2_cmpgtu:
3478 DstReg = MI.getOperand(i: 0).getReg();
3479 Src1Reg = MI.getOperand(i: 1).getReg();
3480 Src2Reg = MI.getOperand(i: 2).getReg();
3481 if (Hexagon::PredRegsRegClass.contains(Reg: DstReg) &&
3482 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3483 isIntRegForSubInst(Reg: Src1Reg) && isIntRegForSubInst(Reg: Src2Reg))
3484 return HexagonII::HCG_A;
3485 break;
3486 case Hexagon::C2_cmpeqi:
3487 case Hexagon::C2_cmpgti:
3488 case Hexagon::C2_cmpgtui:
3489 // P0 = cmp.eq(Rs,#u2)
3490 DstReg = MI.getOperand(i: 0).getReg();
3491 SrcReg = MI.getOperand(i: 1).getReg();
3492 if (Hexagon::PredRegsRegClass.contains(Reg: DstReg) &&
3493 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3494 isIntRegForSubInst(Reg: SrcReg) && MI.getOperand(i: 2).isImm() &&
3495 ((isUInt<5>(x: MI.getOperand(i: 2).getImm())) ||
3496 (MI.getOperand(i: 2).getImm() == -1)))
3497 return HexagonII::HCG_A;
3498 break;
3499 case Hexagon::A2_tfr:
3500 // Rd = Rs
3501 DstReg = MI.getOperand(i: 0).getReg();
3502 SrcReg = MI.getOperand(i: 1).getReg();
3503 if (isIntRegForSubInst(Reg: DstReg) && isIntRegForSubInst(Reg: SrcReg))
3504 return HexagonII::HCG_A;
3505 break;
3506 case Hexagon::A2_tfrsi:
3507 // Rd = #u6
3508 // Do not test for #u6 size since the const is getting extended
3509 // regardless and compound could be formed.
3510 DstReg = MI.getOperand(i: 0).getReg();
3511 if (isIntRegForSubInst(Reg: DstReg))
3512 return HexagonII::HCG_A;
3513 break;
3514 case Hexagon::S2_tstbit_i:
3515 DstReg = MI.getOperand(i: 0).getReg();
3516 Src1Reg = MI.getOperand(i: 1).getReg();
3517 if (Hexagon::PredRegsRegClass.contains(Reg: DstReg) &&
3518 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3519 MI.getOperand(i: 2).isImm() &&
3520 isIntRegForSubInst(Reg: Src1Reg) && (MI.getOperand(i: 2).getImm() == 0))
3521 return HexagonII::HCG_A;
3522 break;
3523 // The fact that .new form is used pretty much guarantees
3524 // that predicate register will match. Nevertheless,
3525 // there could be some false positives without additional
3526 // checking.
3527 case Hexagon::J2_jumptnew:
3528 case Hexagon::J2_jumpfnew:
3529 case Hexagon::J2_jumptnewpt:
3530 case Hexagon::J2_jumpfnewpt:
3531 Src1Reg = MI.getOperand(i: 0).getReg();
3532 if (Hexagon::PredRegsRegClass.contains(Reg: Src1Reg) &&
3533 (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3534 return HexagonII::HCG_B;
3535 break;
3536 // Transfer and jump:
3537 // Rd=#U6 ; jump #r9:2
3538 // Rd=Rs ; jump #r9:2
3539 // Do not test for jump range here.
3540 case Hexagon::J2_jump:
3541 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3542 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
3543 return HexagonII::HCG_C;
3544 }
3545
3546 return HexagonII::HCG_None;
3547}
3548
3549// Returns -1 when there is no opcode found.
3550unsigned HexagonInstrInfo::getCompoundOpcode(const MachineInstr &GA,
3551 const MachineInstr &GB) const {
3552 assert(getCompoundCandidateGroup(GA) == HexagonII::HCG_A);
3553 assert(getCompoundCandidateGroup(GB) == HexagonII::HCG_B);
3554 if ((GA.getOpcode() != Hexagon::C2_cmpeqi) ||
3555 (GB.getOpcode() != Hexagon::J2_jumptnew))
3556 return -1u;
3557 Register DestReg = GA.getOperand(i: 0).getReg();
3558 if (!GB.readsRegister(Reg: DestReg, /*TRI=*/nullptr))
3559 return -1u;
3560 if (DestReg != Hexagon::P0 && DestReg != Hexagon::P1)
3561 return -1u;
3562 // The value compared against must be either u5 or -1.
3563 const MachineOperand &CmpOp = GA.getOperand(i: 2);
3564 if (!CmpOp.isImm())
3565 return -1u;
3566 int V = CmpOp.getImm();
3567 if (V == -1)
3568 return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqn1_tp0_jump_nt
3569 : Hexagon::J4_cmpeqn1_tp1_jump_nt;
3570 if (!isUInt<5>(x: V))
3571 return -1u;
3572 return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqi_tp0_jump_nt
3573 : Hexagon::J4_cmpeqi_tp1_jump_nt;
3574}
3575
3576// Returns -1 if there is no opcode found.
3577int HexagonInstrInfo::getDuplexOpcode(const MachineInstr &MI,
3578 bool ForBigCore) const {
3579 // Static table to switch the opcodes across Tiny Core and Big Core.
3580 // dup_ opcodes are Big core opcodes.
3581 // NOTE: There are special instructions that need to handled later.
3582 // L4_return* instructions, they will only occupy SLOT0 (on big core too).
3583 // PS_jmpret - This pseudo translates to J2_jumpr which occupies only SLOT2.
3584 // The compiler need to base the root instruction to L6_return_map_to_raw
3585 // which can go any slot.
3586 static const std::map<unsigned, unsigned> DupMap = {
3587 {Hexagon::A2_add, Hexagon::dup_A2_add},
3588 {Hexagon::A2_addi, Hexagon::dup_A2_addi},
3589 {Hexagon::A2_andir, Hexagon::dup_A2_andir},
3590 {Hexagon::A2_combineii, Hexagon::dup_A2_combineii},
3591 {Hexagon::A2_sxtb, Hexagon::dup_A2_sxtb},
3592 {Hexagon::A2_sxth, Hexagon::dup_A2_sxth},
3593 {Hexagon::A2_tfr, Hexagon::dup_A2_tfr},
3594 {Hexagon::A2_tfrsi, Hexagon::dup_A2_tfrsi},
3595 {Hexagon::A2_zxtb, Hexagon::dup_A2_zxtb},
3596 {Hexagon::A2_zxth, Hexagon::dup_A2_zxth},
3597 {Hexagon::A4_combineii, Hexagon::dup_A4_combineii},
3598 {Hexagon::A4_combineir, Hexagon::dup_A4_combineir},
3599 {Hexagon::A4_combineri, Hexagon::dup_A4_combineri},
3600 {Hexagon::C2_cmoveif, Hexagon::dup_C2_cmoveif},
3601 {Hexagon::C2_cmoveit, Hexagon::dup_C2_cmoveit},
3602 {Hexagon::C2_cmovenewif, Hexagon::dup_C2_cmovenewif},
3603 {Hexagon::C2_cmovenewit, Hexagon::dup_C2_cmovenewit},
3604 {Hexagon::C2_cmpeqi, Hexagon::dup_C2_cmpeqi},
3605 {Hexagon::L2_deallocframe, Hexagon::dup_L2_deallocframe},
3606 {Hexagon::L2_loadrb_io, Hexagon::dup_L2_loadrb_io},
3607 {Hexagon::L2_loadrd_io, Hexagon::dup_L2_loadrd_io},
3608 {Hexagon::L2_loadrh_io, Hexagon::dup_L2_loadrh_io},
3609 {Hexagon::L2_loadri_io, Hexagon::dup_L2_loadri_io},
3610 {Hexagon::L2_loadrub_io, Hexagon::dup_L2_loadrub_io},
3611 {Hexagon::L2_loadruh_io, Hexagon::dup_L2_loadruh_io},
3612 {Hexagon::S2_allocframe, Hexagon::dup_S2_allocframe},
3613 {Hexagon::S2_storerb_io, Hexagon::dup_S2_storerb_io},
3614 {Hexagon::S2_storerd_io, Hexagon::dup_S2_storerd_io},
3615 {Hexagon::S2_storerh_io, Hexagon::dup_S2_storerh_io},
3616 {Hexagon::S2_storeri_io, Hexagon::dup_S2_storeri_io},
3617 {Hexagon::S4_storeirb_io, Hexagon::dup_S4_storeirb_io},
3618 {Hexagon::S4_storeiri_io, Hexagon::dup_S4_storeiri_io},
3619 };
3620 unsigned OpNum = MI.getOpcode();
3621 // Conversion to Big core.
3622 if (ForBigCore) {
3623 auto Iter = DupMap.find(x: OpNum);
3624 if (Iter != DupMap.end())
3625 return Iter->second;
3626 } else { // Conversion to Tiny core.
3627 for (const auto &Iter : DupMap)
3628 if (Iter.second == OpNum)
3629 return Iter.first;
3630 }
3631 return -1;
3632}
3633
3634int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
3635 enum Hexagon::PredSense inPredSense;
3636 inPredSense = invertPredicate ? Hexagon::PredSense_false :
3637 Hexagon::PredSense_true;
3638 int CondOpcode = Hexagon::getPredOpcode(Opcode: Opc, inPredSense);
3639 if (CondOpcode >= 0) // Valid Conditional opcode/instruction
3640 return CondOpcode;
3641
3642 llvm_unreachable("Unexpected predicable instruction");
3643}
3644
3645// Return the cur value instruction for a given store.
3646int HexagonInstrInfo::getDotCurOp(const MachineInstr &MI) const {
3647 switch (MI.getOpcode()) {
3648 default: llvm_unreachable("Unknown .cur type");
3649 case Hexagon::V6_vL32b_pi:
3650 return Hexagon::V6_vL32b_cur_pi;
3651 case Hexagon::V6_vL32b_ai:
3652 return Hexagon::V6_vL32b_cur_ai;
3653 case Hexagon::V6_vL32b_nt_pi:
3654 return Hexagon::V6_vL32b_nt_cur_pi;
3655 case Hexagon::V6_vL32b_nt_ai:
3656 return Hexagon::V6_vL32b_nt_cur_ai;
3657 case Hexagon::V6_vL32b_ppu:
3658 return Hexagon::V6_vL32b_cur_ppu;
3659 case Hexagon::V6_vL32b_nt_ppu:
3660 return Hexagon::V6_vL32b_nt_cur_ppu;
3661 }
3662 return 0;
3663}
3664
3665// Return the regular version of the .cur instruction.
3666int HexagonInstrInfo::getNonDotCurOp(const MachineInstr &MI) const {
3667 switch (MI.getOpcode()) {
3668 default: llvm_unreachable("Unknown .cur type");
3669 case Hexagon::V6_vL32b_cur_pi:
3670 return Hexagon::V6_vL32b_pi;
3671 case Hexagon::V6_vL32b_cur_ai:
3672 return Hexagon::V6_vL32b_ai;
3673 case Hexagon::V6_vL32b_nt_cur_pi:
3674 return Hexagon::V6_vL32b_nt_pi;
3675 case Hexagon::V6_vL32b_nt_cur_ai:
3676 return Hexagon::V6_vL32b_nt_ai;
3677 case Hexagon::V6_vL32b_cur_ppu:
3678 return Hexagon::V6_vL32b_ppu;
3679 case Hexagon::V6_vL32b_nt_cur_ppu:
3680 return Hexagon::V6_vL32b_nt_ppu;
3681 }
3682 return 0;
3683}
3684
3685// The diagram below shows the steps involved in the conversion of a predicated
3686// store instruction to its .new predicated new-value form.
3687//
3688// Note: It doesn't include conditional new-value stores as they can't be
3689// converted to .new predicate.
3690//
3691// p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
3692// ^ ^
3693// / \ (not OK. it will cause new-value store to be
3694// / X conditional on p0.new while R2 producer is
3695// / \ on p0)
3696// / \.
3697// p.new store p.old NV store
3698// [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
3699// ^ ^
3700// \ /
3701// \ /
3702// \ /
3703// p.old store
3704// [if (p0)memw(R0+#0)=R2]
3705//
3706// The following set of instructions further explains the scenario where
3707// conditional new-value store becomes invalid when promoted to .new predicate
3708// form.
3709//
3710// { 1) if (p0) r0 = add(r1, r2)
3711// 2) p0 = cmp.eq(r3, #0) }
3712//
3713// 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
3714// the first two instructions because in instr 1, r0 is conditional on old value
3715// of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
3716// is not valid for new-value stores.
3717// Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
3718// from the "Conditional Store" list. Because a predicated new value store
3719// would NOT be promoted to a double dot new store. See diagram below:
3720// This function returns yes for those stores that are predicated but not
3721// yet promoted to predicate dot new instructions.
3722//
3723// +---------------------+
3724// /-----| if (p0) memw(..)=r0 |---------\~
3725// || +---------------------+ ||
3726// promote || /\ /\ || promote
3727// || /||\ /||\ ||
3728// \||/ demote || \||/
3729// \/ || || \/
3730// +-------------------------+ || +-------------------------+
3731// | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
3732// +-------------------------+ || +-------------------------+
3733// || || ||
3734// || demote \||/
3735// promote || \/ NOT possible
3736// || || /\~
3737// \||/ || /||\~
3738// \/ || ||
3739// +-----------------------------+
3740// | if (p0.new) memw(..)=r0.new |
3741// +-----------------------------+
3742// Double Dot New Store
3743//
3744// Returns the most basic instruction for the .new predicated instructions and
3745// new-value stores.
3746// For example, all of the following instructions will be converted back to the
3747// same instruction:
3748// 1) if (p0.new) memw(R0+#0) = R1.new --->
3749// 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
3750// 3) if (p0.new) memw(R0+#0) = R1 --->
3751//
3752// To understand the translation of instruction 1 to its original form, consider
3753// a packet with 3 instructions.
3754// { p0 = cmp.eq(R0,R1)
3755// if (p0.new) R2 = add(R3, R4)
3756// R5 = add (R3, R1)
3757// }
3758// if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
3759//
3760// This instruction can be part of the previous packet only if both p0 and R2
3761// are promoted to .new values. This promotion happens in steps, first
3762// predicate register is promoted to .new and in the next iteration R2 is
3763// promoted. Therefore, in case of dependence check failure (due to R5) during
3764// next iteration, it should be converted back to its most basic form.
3765
3766// Return the new value instruction for a given store.
3767int HexagonInstrInfo::getDotNewOp(const MachineInstr &MI) const {
3768 int NVOpcode = Hexagon::getNewValueOpcode(Opcode: MI.getOpcode());
3769 if (NVOpcode >= 0) // Valid new-value store instruction.
3770 return NVOpcode;
3771
3772 switch (MI.getOpcode()) {
3773 default:
3774 report_fatal_error(reason: Twine("Unknown .new type: ") +
3775 std::to_string(val: MI.getOpcode()));
3776 case Hexagon::S4_storerb_ur:
3777 return Hexagon::S4_storerbnew_ur;
3778
3779 case Hexagon::S2_storerb_pci:
3780 return Hexagon::S2_storerb_pci;
3781
3782 case Hexagon::S2_storeri_pci:
3783 return Hexagon::S2_storeri_pci;
3784
3785 case Hexagon::S2_storerh_pci:
3786 return Hexagon::S2_storerh_pci;
3787
3788 case Hexagon::S2_storerd_pci:
3789 return Hexagon::S2_storerd_pci;
3790
3791 case Hexagon::S2_storerf_pci:
3792 return Hexagon::S2_storerf_pci;
3793
3794 case Hexagon::V6_vS32b_ai:
3795 return Hexagon::V6_vS32b_new_ai;
3796
3797 case Hexagon::V6_vS32b_pi:
3798 return Hexagon::V6_vS32b_new_pi;
3799 }
3800 return 0;
3801}
3802
3803// Returns the opcode to use when converting MI, which is a conditional jump,
3804// into a conditional instruction which uses the .new value of the predicate.
3805// We also use branch probabilities to add a hint to the jump.
3806// If MBPI is null, all edges will be treated as equally likely for the
3807// purposes of establishing a predication hint.
3808int HexagonInstrInfo::getDotNewPredJumpOp(const MachineInstr &MI,
3809 const MachineBranchProbabilityInfo *MBPI) const {
3810 // We assume that block can have at most two successors.
3811 const MachineBasicBlock *Src = MI.getParent();
3812 const MachineOperand &BrTarget = MI.getOperand(i: 1);
3813 bool Taken = false;
3814 const BranchProbability OneHalf(1, 2);
3815
3816 auto getEdgeProbability = [MBPI] (const MachineBasicBlock *Src,
3817 const MachineBasicBlock *Dst) {
3818 if (MBPI)
3819 return MBPI->getEdgeProbability(Src, Dst);
3820 return BranchProbability(1, Src->succ_size());
3821 };
3822
3823 if (BrTarget.isMBB()) {
3824 const MachineBasicBlock *Dst = BrTarget.getMBB();
3825 Taken = getEdgeProbability(Src, Dst) >= OneHalf;
3826 } else {
3827 // The branch target is not a basic block (most likely a function).
3828 // Since BPI only gives probabilities for targets that are basic blocks,
3829 // try to identify another target of this branch (potentially a fall-
3830 // -through) and check the probability of that target.
3831 //
3832 // The only handled branch combinations are:
3833 // - one conditional branch,
3834 // - one conditional branch followed by one unconditional branch.
3835 // Otherwise, assume not-taken.
3836 assert(MI.isConditionalBranch());
3837 const MachineBasicBlock &B = *MI.getParent();
3838 bool SawCond = false, Bad = false;
3839 for (const MachineInstr &I : B) {
3840 if (!I.isBranch())
3841 continue;
3842 if (I.isConditionalBranch()) {
3843 SawCond = true;
3844 if (&I != &MI) {
3845 Bad = true;
3846 break;
3847 }
3848 }
3849 if (I.isUnconditionalBranch() && !SawCond) {
3850 Bad = true;
3851 break;
3852 }
3853 }
3854 if (!Bad) {
3855 MachineBasicBlock::const_instr_iterator It(MI);
3856 MachineBasicBlock::const_instr_iterator NextIt = std::next(x: It);
3857 if (NextIt == B.instr_end()) {
3858 // If this branch is the last, look for the fall-through block.
3859 for (const MachineBasicBlock *SB : B.successors()) {
3860 if (!B.isLayoutSuccessor(MBB: SB))
3861 continue;
3862 Taken = getEdgeProbability(Src, SB) < OneHalf;
3863 break;
3864 }
3865 } else {
3866 assert(NextIt->isUnconditionalBranch());
3867 // Find the first MBB operand and assume it's the target.
3868 const MachineBasicBlock *BT = nullptr;
3869 for (const MachineOperand &Op : NextIt->operands()) {
3870 if (!Op.isMBB())
3871 continue;
3872 BT = Op.getMBB();
3873 break;
3874 }
3875 Taken = BT && getEdgeProbability(Src, BT) < OneHalf;
3876 }
3877 } // if (!Bad)
3878 }
3879
3880 // The Taken flag should be set to something reasonable by this point.
3881
3882 switch (MI.getOpcode()) {
3883 case Hexagon::J2_jumpt:
3884 return Taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
3885 case Hexagon::J2_jumpf:
3886 return Taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
3887
3888 default:
3889 llvm_unreachable("Unexpected jump instruction.");
3890 }
3891}
3892
3893// Return .new predicate version for an instruction.
3894int HexagonInstrInfo::getDotNewPredOp(const MachineInstr &MI,
3895 const MachineBranchProbabilityInfo *MBPI) const {
3896 switch (MI.getOpcode()) {
3897 // Conditional Jumps
3898 case Hexagon::J2_jumpt:
3899 case Hexagon::J2_jumpf:
3900 return getDotNewPredJumpOp(MI, MBPI);
3901 }
3902
3903 int NewOpcode = Hexagon::getPredNewOpcode(Opcode: MI.getOpcode());
3904 if (NewOpcode >= 0)
3905 return NewOpcode;
3906 return 0;
3907}
3908
3909int HexagonInstrInfo::getDotOldOp(const MachineInstr &MI) const {
3910 int NewOp = MI.getOpcode();
3911 if (isPredicated(Opcode: NewOp) && isPredicatedNew(Opcode: NewOp)) { // Get predicate old form
3912 NewOp = Hexagon::getPredOldOpcode(Opcode: NewOp);
3913 // All Hexagon architectures have prediction bits on dot-new branches,
3914 // but only Hexagon V60+ has prediction bits on dot-old ones. Make sure
3915 // to pick the right opcode when converting back to dot-old.
3916 if (!Subtarget.hasFeature(Feature: Hexagon::ArchV60)) {
3917 switch (NewOp) {
3918 case Hexagon::J2_jumptpt:
3919 NewOp = Hexagon::J2_jumpt;
3920 break;
3921 case Hexagon::J2_jumpfpt:
3922 NewOp = Hexagon::J2_jumpf;
3923 break;
3924 case Hexagon::J2_jumprtpt:
3925 NewOp = Hexagon::J2_jumprt;
3926 break;
3927 case Hexagon::J2_jumprfpt:
3928 NewOp = Hexagon::J2_jumprf;
3929 break;
3930 }
3931 }
3932 assert(NewOp >= 0 &&
3933 "Couldn't change predicate new instruction to its old form.");
3934 }
3935
3936 if (isNewValueStore(Opcode: NewOp)) { // Convert into non-new-value format
3937 NewOp = Hexagon::getNonNVStore(Opcode: NewOp);
3938 assert(NewOp >= 0 && "Couldn't change new-value store to its old form.");
3939 }
3940
3941 if (Subtarget.hasV60Ops())
3942 return NewOp;
3943
3944 // Subtargets prior to V60 didn't support 'taken' forms of predicated jumps.
3945 switch (NewOp) {
3946 case Hexagon::J2_jumpfpt:
3947 return Hexagon::J2_jumpf;
3948 case Hexagon::J2_jumptpt:
3949 return Hexagon::J2_jumpt;
3950 case Hexagon::J2_jumprfpt:
3951 return Hexagon::J2_jumprf;
3952 case Hexagon::J2_jumprtpt:
3953 return Hexagon::J2_jumprt;
3954 }
3955 return NewOp;
3956}
3957
3958// See if instruction could potentially be a duplex candidate.
3959// If so, return its group. Zero otherwise.
3960HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup(
3961 const MachineInstr &MI) const {
3962 Register DstReg, SrcReg, Src1Reg, Src2Reg;
3963 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
3964
3965 switch (MI.getOpcode()) {
3966 default:
3967 return HexagonII::HSIG_None;
3968 //
3969 // Group L1:
3970 //
3971 // Rd = memw(Rs+#u4:2)
3972 // Rd = memub(Rs+#u4:0)
3973 case Hexagon::L2_loadri_io:
3974 case Hexagon::dup_L2_loadri_io:
3975 DstReg = MI.getOperand(i: 0).getReg();
3976 SrcReg = MI.getOperand(i: 1).getReg();
3977 // Special case this one from Group L2.
3978 // Rd = memw(r29+#u5:2)
3979 if (isIntRegForSubInst(Reg: DstReg)) {
3980 if (Hexagon::IntRegsRegClass.contains(Reg: SrcReg) &&
3981 HRI.getStackRegister() == SrcReg &&
3982 MI.getOperand(i: 2).isImm() &&
3983 isShiftedUInt<5,2>(x: MI.getOperand(i: 2).getImm()))
3984 return HexagonII::HSIG_L2;
3985 // Rd = memw(Rs+#u4:2)
3986 if (isIntRegForSubInst(Reg: SrcReg) &&
3987 (MI.getOperand(i: 2).isImm() &&
3988 isShiftedUInt<4,2>(x: MI.getOperand(i: 2).getImm())))
3989 return HexagonII::HSIG_L1;
3990 }
3991 break;
3992 case Hexagon::L2_loadrub_io:
3993 case Hexagon::dup_L2_loadrub_io:
3994 // Rd = memub(Rs+#u4:0)
3995 DstReg = MI.getOperand(i: 0).getReg();
3996 SrcReg = MI.getOperand(i: 1).getReg();
3997 if (isIntRegForSubInst(Reg: DstReg) && isIntRegForSubInst(Reg: SrcReg) &&
3998 MI.getOperand(i: 2).isImm() && isUInt<4>(x: MI.getOperand(i: 2).getImm()))
3999 return HexagonII::HSIG_L1;
4000 break;
4001 //
4002 // Group L2:
4003 //
4004 // Rd = memh/memuh(Rs+#u3:1)
4005 // Rd = memb(Rs+#u3:0)
4006 // Rd = memw(r29+#u5:2) - Handled above.
4007 // Rdd = memd(r29+#u5:3)
4008 // deallocframe
4009 // [if ([!]p0[.new])] dealloc_return
4010 // [if ([!]p0[.new])] jumpr r31
4011 case Hexagon::L2_loadrh_io:
4012 case Hexagon::L2_loadruh_io:
4013 case Hexagon::dup_L2_loadrh_io:
4014 case Hexagon::dup_L2_loadruh_io:
4015 // Rd = memh/memuh(Rs+#u3:1)
4016 DstReg = MI.getOperand(i: 0).getReg();
4017 SrcReg = MI.getOperand(i: 1).getReg();
4018 if (isIntRegForSubInst(Reg: DstReg) && isIntRegForSubInst(Reg: SrcReg) &&
4019 MI.getOperand(i: 2).isImm() &&
4020 isShiftedUInt<3,1>(x: MI.getOperand(i: 2).getImm()))
4021 return HexagonII::HSIG_L2;
4022 break;
4023 case Hexagon::L2_loadrb_io:
4024 case Hexagon::dup_L2_loadrb_io:
4025 // Rd = memb(Rs+#u3:0)
4026 DstReg = MI.getOperand(i: 0).getReg();
4027 SrcReg = MI.getOperand(i: 1).getReg();
4028 if (isIntRegForSubInst(Reg: DstReg) && isIntRegForSubInst(Reg: SrcReg) &&
4029 MI.getOperand(i: 2).isImm() &&
4030 isUInt<3>(x: MI.getOperand(i: 2).getImm()))
4031 return HexagonII::HSIG_L2;
4032 break;
4033 case Hexagon::L2_loadrd_io:
4034 case Hexagon::dup_L2_loadrd_io:
4035 // Rdd = memd(r29+#u5:3)
4036 DstReg = MI.getOperand(i: 0).getReg();
4037 SrcReg = MI.getOperand(i: 1).getReg();
4038 if (isDblRegForSubInst(Reg: DstReg, HRI) &&
4039 Hexagon::IntRegsRegClass.contains(Reg: SrcReg) &&
4040 HRI.getStackRegister() == SrcReg &&
4041 MI.getOperand(i: 2).isImm() &&
4042 isShiftedUInt<5,3>(x: MI.getOperand(i: 2).getImm()))
4043 return HexagonII::HSIG_L2;
4044 break;
4045 // dealloc_return is not documented in Hexagon Manual, but marked
4046 // with A_SUBINSN attribute in iset_v4classic.py.
4047 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
4048 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC:
4049 case Hexagon::L4_return:
4050 case Hexagon::L2_deallocframe:
4051 case Hexagon::dup_L2_deallocframe:
4052 return HexagonII::HSIG_L2;
4053 case Hexagon::EH_RETURN_JMPR:
4054 case Hexagon::PS_jmpret:
4055 case Hexagon::SL2_jumpr31:
4056 // jumpr r31
4057 // Actual form JMPR implicit-def %pc, implicit %r31, implicit internal %r0
4058 DstReg = MI.getOperand(i: 0).getReg();
4059 if (Hexagon::IntRegsRegClass.contains(Reg: DstReg) && (Hexagon::R31 == DstReg))
4060 return HexagonII::HSIG_L2;
4061 break;
4062 case Hexagon::PS_jmprett:
4063 case Hexagon::PS_jmpretf:
4064 case Hexagon::PS_jmprettnewpt:
4065 case Hexagon::PS_jmpretfnewpt:
4066 case Hexagon::PS_jmprettnew:
4067 case Hexagon::PS_jmpretfnew:
4068 case Hexagon::SL2_jumpr31_t:
4069 case Hexagon::SL2_jumpr31_f:
4070 case Hexagon::SL2_jumpr31_tnew:
4071 case Hexagon::SL2_jumpr31_fnew:
4072 DstReg = MI.getOperand(i: 1).getReg();
4073 SrcReg = MI.getOperand(i: 0).getReg();
4074 // [if ([!]p0[.new])] jumpr r31
4075 if ((Hexagon::PredRegsRegClass.contains(Reg: SrcReg) &&
4076 (Hexagon::P0 == SrcReg)) &&
4077 (Hexagon::IntRegsRegClass.contains(Reg: DstReg) && (Hexagon::R31 == DstReg)))
4078 return HexagonII::HSIG_L2;
4079 break;
4080 case Hexagon::L4_return_t:
4081 case Hexagon::L4_return_f:
4082 case Hexagon::L4_return_tnew_pnt:
4083 case Hexagon::L4_return_fnew_pnt:
4084 case Hexagon::L4_return_tnew_pt:
4085 case Hexagon::L4_return_fnew_pt:
4086 // [if ([!]p0[.new])] dealloc_return
4087 SrcReg = MI.getOperand(i: 0).getReg();
4088 if (Hexagon::PredRegsRegClass.contains(Reg: SrcReg) && (Hexagon::P0 == SrcReg))
4089 return HexagonII::HSIG_L2;
4090 break;
4091 //
4092 // Group S1:
4093 //
4094 // memw(Rs+#u4:2) = Rt
4095 // memb(Rs+#u4:0) = Rt
4096 case Hexagon::S2_storeri_io:
4097 case Hexagon::dup_S2_storeri_io:
4098 // Special case this one from Group S2.
4099 // memw(r29+#u5:2) = Rt
4100 Src1Reg = MI.getOperand(i: 0).getReg();
4101 Src2Reg = MI.getOperand(i: 2).getReg();
4102 if (Hexagon::IntRegsRegClass.contains(Reg: Src1Reg) &&
4103 isIntRegForSubInst(Reg: Src2Reg) &&
4104 HRI.getStackRegister() == Src1Reg && MI.getOperand(i: 1).isImm() &&
4105 isShiftedUInt<5,2>(x: MI.getOperand(i: 1).getImm()))
4106 return HexagonII::HSIG_S2;
4107 // memw(Rs+#u4:2) = Rt
4108 if (isIntRegForSubInst(Reg: Src1Reg) && isIntRegForSubInst(Reg: Src2Reg) &&
4109 MI.getOperand(i: 1).isImm() &&
4110 isShiftedUInt<4,2>(x: MI.getOperand(i: 1).getImm()))
4111 return HexagonII::HSIG_S1;
4112 break;
4113 case Hexagon::S2_storerb_io:
4114 case Hexagon::dup_S2_storerb_io:
4115 // memb(Rs+#u4:0) = Rt
4116 Src1Reg = MI.getOperand(i: 0).getReg();
4117 Src2Reg = MI.getOperand(i: 2).getReg();
4118 if (isIntRegForSubInst(Reg: Src1Reg) && isIntRegForSubInst(Reg: Src2Reg) &&
4119 MI.getOperand(i: 1).isImm() && isUInt<4>(x: MI.getOperand(i: 1).getImm()))
4120 return HexagonII::HSIG_S1;
4121 break;
4122 //
4123 // Group S2:
4124 //
4125 // memh(Rs+#u3:1) = Rt
4126 // memw(r29+#u5:2) = Rt
4127 // memd(r29+#s6:3) = Rtt
4128 // memw(Rs+#u4:2) = #U1
4129 // memb(Rs+#u4) = #U1
4130 // allocframe(#u5:3)
4131 case Hexagon::S2_storerh_io:
4132 case Hexagon::dup_S2_storerh_io:
4133 // memh(Rs+#u3:1) = Rt
4134 Src1Reg = MI.getOperand(i: 0).getReg();
4135 Src2Reg = MI.getOperand(i: 2).getReg();
4136 if (isIntRegForSubInst(Reg: Src1Reg) && isIntRegForSubInst(Reg: Src2Reg) &&
4137 MI.getOperand(i: 1).isImm() &&
4138 isShiftedUInt<3,1>(x: MI.getOperand(i: 1).getImm()))
4139 return HexagonII::HSIG_S1;
4140 break;
4141 case Hexagon::S2_storerd_io:
4142 case Hexagon::dup_S2_storerd_io:
4143 // memd(r29+#s6:3) = Rtt
4144 Src1Reg = MI.getOperand(i: 0).getReg();
4145 Src2Reg = MI.getOperand(i: 2).getReg();
4146 if (isDblRegForSubInst(Reg: Src2Reg, HRI) &&
4147 Hexagon::IntRegsRegClass.contains(Reg: Src1Reg) &&
4148 HRI.getStackRegister() == Src1Reg && MI.getOperand(i: 1).isImm() &&
4149 isShiftedInt<6,3>(x: MI.getOperand(i: 1).getImm()))
4150 return HexagonII::HSIG_S2;
4151 break;
4152 case Hexagon::S4_storeiri_io:
4153 case Hexagon::dup_S4_storeiri_io:
4154 // memw(Rs+#u4:2) = #U1
4155 Src1Reg = MI.getOperand(i: 0).getReg();
4156 if (isIntRegForSubInst(Reg: Src1Reg) && MI.getOperand(i: 1).isImm() &&
4157 isShiftedUInt<4,2>(x: MI.getOperand(i: 1).getImm()) &&
4158 MI.getOperand(i: 2).isImm() && isUInt<1>(x: MI.getOperand(i: 2).getImm()))
4159 return HexagonII::HSIG_S2;
4160 break;
4161 case Hexagon::S4_storeirb_io:
4162 case Hexagon::dup_S4_storeirb_io:
4163 // memb(Rs+#u4) = #U1
4164 Src1Reg = MI.getOperand(i: 0).getReg();
4165 if (isIntRegForSubInst(Reg: Src1Reg) &&
4166 MI.getOperand(i: 1).isImm() && isUInt<4>(x: MI.getOperand(i: 1).getImm()) &&
4167 MI.getOperand(i: 2).isImm() && isUInt<1>(x: MI.getOperand(i: 2).getImm()))
4168 return HexagonII::HSIG_S2;
4169 break;
4170 case Hexagon::S2_allocframe:
4171 case Hexagon::dup_S2_allocframe:
4172 if (MI.getOperand(i: 2).isImm() &&
4173 isShiftedUInt<5,3>(x: MI.getOperand(i: 2).getImm()))
4174 return HexagonII::HSIG_S1;
4175 break;
4176 //
4177 // Group A:
4178 //
4179 // Rx = add(Rx,#s7)
4180 // Rd = Rs
4181 // Rd = #u6
4182 // Rd = #-1
4183 // if ([!]P0[.new]) Rd = #0
4184 // Rd = add(r29,#u6:2)
4185 // Rx = add(Rx,Rs)
4186 // P0 = cmp.eq(Rs,#u2)
4187 // Rdd = combine(#0,Rs)
4188 // Rdd = combine(Rs,#0)
4189 // Rdd = combine(#u2,#U2)
4190 // Rd = add(Rs,#1)
4191 // Rd = add(Rs,#-1)
4192 // Rd = sxth/sxtb/zxtb/zxth(Rs)
4193 // Rd = and(Rs,#1)
4194 case Hexagon::A2_addi:
4195 case Hexagon::dup_A2_addi:
4196 DstReg = MI.getOperand(i: 0).getReg();
4197 SrcReg = MI.getOperand(i: 1).getReg();
4198 if (isIntRegForSubInst(Reg: DstReg)) {
4199 // Rd = add(r29,#u6:2)
4200 if (Hexagon::IntRegsRegClass.contains(Reg: SrcReg) &&
4201 HRI.getStackRegister() == SrcReg && MI.getOperand(i: 2).isImm() &&
4202 isShiftedUInt<6,2>(x: MI.getOperand(i: 2).getImm()))
4203 return HexagonII::HSIG_A;
4204 // Rx = add(Rx,#s7)
4205 if ((DstReg == SrcReg) && MI.getOperand(i: 2).isImm() &&
4206 isInt<7>(x: MI.getOperand(i: 2).getImm()))
4207 return HexagonII::HSIG_A;
4208 // Rd = add(Rs,#1)
4209 // Rd = add(Rs,#-1)
4210 if (isIntRegForSubInst(Reg: SrcReg) && MI.getOperand(i: 2).isImm() &&
4211 ((MI.getOperand(i: 2).getImm() == 1) ||
4212 (MI.getOperand(i: 2).getImm() == -1)))
4213 return HexagonII::HSIG_A;
4214 }
4215 break;
4216 case Hexagon::A2_add:
4217 case Hexagon::dup_A2_add:
4218 // Rx = add(Rx,Rs)
4219 DstReg = MI.getOperand(i: 0).getReg();
4220 Src1Reg = MI.getOperand(i: 1).getReg();
4221 Src2Reg = MI.getOperand(i: 2).getReg();
4222 if (isIntRegForSubInst(Reg: DstReg) && (DstReg == Src1Reg) &&
4223 isIntRegForSubInst(Reg: Src2Reg))
4224 return HexagonII::HSIG_A;
4225 break;
4226 case Hexagon::A2_andir:
4227 case Hexagon::dup_A2_andir:
4228 // Same as zxtb.
4229 // Rd16=and(Rs16,#255)
4230 // Rd16=and(Rs16,#1)
4231 DstReg = MI.getOperand(i: 0).getReg();
4232 SrcReg = MI.getOperand(i: 1).getReg();
4233 if (isIntRegForSubInst(Reg: DstReg) && isIntRegForSubInst(Reg: SrcReg) &&
4234 MI.getOperand(i: 2).isImm() &&
4235 ((MI.getOperand(i: 2).getImm() == 1) ||
4236 (MI.getOperand(i: 2).getImm() == 255)))
4237 return HexagonII::HSIG_A;
4238 break;
4239 case Hexagon::A2_tfr:
4240 case Hexagon::dup_A2_tfr:
4241 // Rd = Rs
4242 DstReg = MI.getOperand(i: 0).getReg();
4243 SrcReg = MI.getOperand(i: 1).getReg();
4244 if (isIntRegForSubInst(Reg: DstReg) && isIntRegForSubInst(Reg: SrcReg))
4245 return HexagonII::HSIG_A;
4246 break;
4247 case Hexagon::A2_tfrsi:
4248 case Hexagon::dup_A2_tfrsi:
4249 // Rd = #u6
4250 // Do not test for #u6 size since the const is getting extended
4251 // regardless and compound could be formed.
4252 // Rd = #-1
4253 DstReg = MI.getOperand(i: 0).getReg();
4254 if (isIntRegForSubInst(Reg: DstReg))
4255 return HexagonII::HSIG_A;
4256 break;
4257 case Hexagon::C2_cmoveit:
4258 case Hexagon::C2_cmovenewit:
4259 case Hexagon::C2_cmoveif:
4260 case Hexagon::C2_cmovenewif:
4261 case Hexagon::dup_C2_cmoveit:
4262 case Hexagon::dup_C2_cmovenewit:
4263 case Hexagon::dup_C2_cmoveif:
4264 case Hexagon::dup_C2_cmovenewif:
4265 // if ([!]P0[.new]) Rd = #0
4266 // Actual form:
4267 // %r16 = C2_cmovenewit internal %p0, 0, implicit undef %r16;
4268 DstReg = MI.getOperand(i: 0).getReg();
4269 SrcReg = MI.getOperand(i: 1).getReg();
4270 if (isIntRegForSubInst(Reg: DstReg) &&
4271 Hexagon::PredRegsRegClass.contains(Reg: SrcReg) && Hexagon::P0 == SrcReg &&
4272 MI.getOperand(i: 2).isImm() && MI.getOperand(i: 2).getImm() == 0)
4273 return HexagonII::HSIG_A;
4274 break;
4275 case Hexagon::C2_cmpeqi:
4276 case Hexagon::dup_C2_cmpeqi:
4277 // P0 = cmp.eq(Rs,#u2)
4278 DstReg = MI.getOperand(i: 0).getReg();
4279 SrcReg = MI.getOperand(i: 1).getReg();
4280 if (Hexagon::PredRegsRegClass.contains(Reg: DstReg) &&
4281 Hexagon::P0 == DstReg && isIntRegForSubInst(Reg: SrcReg) &&
4282 MI.getOperand(i: 2).isImm() && isUInt<2>(x: MI.getOperand(i: 2).getImm()))
4283 return HexagonII::HSIG_A;
4284 break;
4285 case Hexagon::A2_combineii:
4286 case Hexagon::A4_combineii:
4287 case Hexagon::dup_A2_combineii:
4288 case Hexagon::dup_A4_combineii:
4289 // Rdd = combine(#u2,#U2)
4290 DstReg = MI.getOperand(i: 0).getReg();
4291 if (isDblRegForSubInst(Reg: DstReg, HRI) &&
4292 ((MI.getOperand(i: 1).isImm() && isUInt<2>(x: MI.getOperand(i: 1).getImm())) ||
4293 (MI.getOperand(i: 1).isGlobal() &&
4294 isUInt<2>(x: MI.getOperand(i: 1).getOffset()))) &&
4295 ((MI.getOperand(i: 2).isImm() && isUInt<2>(x: MI.getOperand(i: 2).getImm())) ||
4296 (MI.getOperand(i: 2).isGlobal() &&
4297 isUInt<2>(x: MI.getOperand(i: 2).getOffset()))))
4298 return HexagonII::HSIG_A;
4299 break;
4300 case Hexagon::A4_combineri:
4301 case Hexagon::dup_A4_combineri:
4302 // Rdd = combine(Rs,#0)
4303 // Rdd = combine(Rs,#0)
4304 DstReg = MI.getOperand(i: 0).getReg();
4305 SrcReg = MI.getOperand(i: 1).getReg();
4306 if (isDblRegForSubInst(Reg: DstReg, HRI) && isIntRegForSubInst(Reg: SrcReg) &&
4307 ((MI.getOperand(i: 2).isImm() && MI.getOperand(i: 2).getImm() == 0) ||
4308 (MI.getOperand(i: 2).isGlobal() && MI.getOperand(i: 2).getOffset() == 0)))
4309 return HexagonII::HSIG_A;
4310 break;
4311 case Hexagon::A4_combineir:
4312 case Hexagon::dup_A4_combineir:
4313 // Rdd = combine(#0,Rs)
4314 DstReg = MI.getOperand(i: 0).getReg();
4315 SrcReg = MI.getOperand(i: 2).getReg();
4316 if (isDblRegForSubInst(Reg: DstReg, HRI) && isIntRegForSubInst(Reg: SrcReg) &&
4317 ((MI.getOperand(i: 1).isImm() && MI.getOperand(i: 1).getImm() == 0) ||
4318 (MI.getOperand(i: 1).isGlobal() && MI.getOperand(i: 1).getOffset() == 0)))
4319 return HexagonII::HSIG_A;
4320 break;
4321 case Hexagon::A2_sxtb:
4322 case Hexagon::A2_sxth:
4323 case Hexagon::A2_zxtb:
4324 case Hexagon::A2_zxth:
4325 case Hexagon::dup_A2_sxtb:
4326 case Hexagon::dup_A2_sxth:
4327 case Hexagon::dup_A2_zxtb:
4328 case Hexagon::dup_A2_zxth:
4329 // Rd = sxth/sxtb/zxtb/zxth(Rs)
4330 DstReg = MI.getOperand(i: 0).getReg();
4331 SrcReg = MI.getOperand(i: 1).getReg();
4332 if (isIntRegForSubInst(Reg: DstReg) && isIntRegForSubInst(Reg: SrcReg))
4333 return HexagonII::HSIG_A;
4334 break;
4335 }
4336
4337 return HexagonII::HSIG_None;
4338}
4339
4340short HexagonInstrInfo::getEquivalentHWInstr(const MachineInstr &MI) const {
4341 return Hexagon::getRealHWInstr(Opcode: MI.getOpcode(), inInstrType: Hexagon::InstrType_Real);
4342}
4343
4344unsigned HexagonInstrInfo::getInstrTimingClassLatency(
4345 const InstrItineraryData *ItinData, const MachineInstr &MI) const {
4346 // Default to one cycle for no itinerary. However, an "empty" itinerary may
4347 // still have a MinLatency property, which getStageLatency checks.
4348 if (!ItinData)
4349 return getInstrLatency(ItinData, MI);
4350
4351 if (MI.isTransient())
4352 return 0;
4353 return ItinData->getStageLatency(ItinClassIndx: MI.getDesc().getSchedClass());
4354}
4355
4356/// getOperandLatency - Compute and return the use operand latency of a given
4357/// pair of def and use.
4358/// In most cases, the static scheduling itinerary was enough to determine the
4359/// operand latency. But it may not be possible for instructions with variable
4360/// number of defs / uses.
4361///
4362/// This is a raw interface to the itinerary that may be directly overridden by
4363/// a target. Use computeOperandLatency to get the best estimate of latency.
4364std::optional<unsigned> HexagonInstrInfo::getOperandLatency(
4365 const InstrItineraryData *ItinData, const MachineInstr &DefMI,
4366 unsigned DefIdx, const MachineInstr &UseMI, unsigned UseIdx) const {
4367 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4368
4369 // Get DefIdx and UseIdx for super registers.
4370 const MachineOperand &DefMO = DefMI.getOperand(i: DefIdx);
4371
4372 if (DefMO.isReg() && DefMO.getReg().isPhysical()) {
4373 if (DefMO.isImplicit()) {
4374 for (MCPhysReg SR : HRI.superregs(Reg: DefMO.getReg())) {
4375 int Idx = DefMI.findRegisterDefOperandIdx(Reg: SR, TRI: &HRI, isDead: false, Overlap: false);
4376 if (Idx != -1) {
4377 DefIdx = Idx;
4378 break;
4379 }
4380 }
4381 }
4382
4383 const MachineOperand &UseMO = UseMI.getOperand(i: UseIdx);
4384 if (UseMO.isImplicit()) {
4385 for (MCPhysReg SR : HRI.superregs(Reg: UseMO.getReg())) {
4386 int Idx = UseMI.findRegisterUseOperandIdx(Reg: SR, TRI: &HRI, isKill: false);
4387 if (Idx != -1) {
4388 UseIdx = Idx;
4389 break;
4390 }
4391 }
4392 }
4393 }
4394
4395 std::optional<unsigned> Latency = TargetInstrInfo::getOperandLatency(
4396 ItinData, DefMI, DefIdx, UseMI, UseIdx);
4397 if (Latency == 0)
4398 // We should never have 0 cycle latency between two instructions unless
4399 // they can be packetized together. However, this decision can't be made
4400 // here.
4401 Latency = 1;
4402 return Latency;
4403}
4404
4405// inverts the predication logic.
4406// p -> NotP
4407// NotP -> P
4408bool HexagonInstrInfo::getInvertedPredSense(
4409 SmallVectorImpl<MachineOperand> &Cond) const {
4410 if (Cond.empty())
4411 return false;
4412 unsigned Opc = getInvertedPredicatedOpcode(Opc: Cond[0].getImm());
4413 Cond[0].setImm(Opc);
4414 return true;
4415}
4416
4417unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
4418 int InvPredOpcode;
4419 InvPredOpcode = isPredicatedTrue(Opcode: Opc) ? Hexagon::getFalsePredOpcode(Opcode: Opc)
4420 : Hexagon::getTruePredOpcode(Opcode: Opc);
4421 if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
4422 return InvPredOpcode;
4423
4424 llvm_unreachable("Unexpected predicated instruction");
4425}
4426
4427// Returns the max value that doesn't need to be extended.
4428int HexagonInstrInfo::getMaxValue(const MachineInstr &MI) const {
4429 const uint64_t F = MI.getDesc().TSFlags;
4430 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4431 & HexagonII::ExtentSignedMask;
4432 unsigned bits = (F >> HexagonII::ExtentBitsPos)
4433 & HexagonII::ExtentBitsMask;
4434
4435 if (isSigned) // if value is signed
4436 return ~(-1U << (bits - 1));
4437 else
4438 return ~(-1U << bits);
4439}
4440
4441
4442bool HexagonInstrInfo::isAddrModeWithOffset(const MachineInstr &MI) const {
4443 switch (MI.getOpcode()) {
4444 case Hexagon::L2_loadrbgp:
4445 case Hexagon::L2_loadrdgp:
4446 case Hexagon::L2_loadrhgp:
4447 case Hexagon::L2_loadrigp:
4448 case Hexagon::L2_loadrubgp:
4449 case Hexagon::L2_loadruhgp:
4450 case Hexagon::S2_storerbgp:
4451 case Hexagon::S2_storerbnewgp:
4452 case Hexagon::S2_storerhgp:
4453 case Hexagon::S2_storerhnewgp:
4454 case Hexagon::S2_storerigp:
4455 case Hexagon::S2_storerinewgp:
4456 case Hexagon::S2_storerdgp:
4457 case Hexagon::S2_storerfgp:
4458 return true;
4459 }
4460 const uint64_t F = MI.getDesc().TSFlags;
4461 unsigned addrMode =
4462 ((F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask);
4463 // Disallow any base+offset instruction. The assembler does not yet reorder
4464 // based up any zero offset instruction.
4465 return (addrMode == HexagonII::BaseRegOffset ||
4466 addrMode == HexagonII::BaseImmOffset ||
4467 addrMode == HexagonII::BaseLongOffset);
4468}
4469
4470bool HexagonInstrInfo::isPureSlot0(const MachineInstr &MI) const {
4471 // Workaround for the Global Scheduler. Sometimes, it creates
4472 // A4_ext as a Pseudo instruction and calls this function to see if
4473 // it can be added to an existing bundle. Since the instruction doesn't
4474 // belong to any BB yet, we can't use getUnits API.
4475 if (MI.getOpcode() == Hexagon::A4_ext)
4476 return false;
4477
4478 unsigned FuncUnits = getUnits(MI);
4479 return HexagonFUnits::isSlot0Only(units: FuncUnits);
4480}
4481
4482bool HexagonInstrInfo::isRestrictNoSlot1Store(const MachineInstr &MI) const {
4483 const uint64_t F = MI.getDesc().TSFlags;
4484 return ((F >> HexagonII::RestrictNoSlot1StorePos) &
4485 HexagonII::RestrictNoSlot1StoreMask);
4486}
4487
4488void HexagonInstrInfo::changeDuplexOpcode(MachineBasicBlock::instr_iterator MII,
4489 bool ToBigInstrs) const {
4490 int Opcode = -1;
4491 if (ToBigInstrs) { // To BigCore Instr.
4492 // Check if the instruction can form a Duplex.
4493 if (getDuplexCandidateGroup(MI: *MII))
4494 // Get the opcode marked "dup_*" tag.
4495 Opcode = getDuplexOpcode(MI: *MII, ForBigCore: ToBigInstrs);
4496 } else // To TinyCore Instr.
4497 Opcode = getDuplexOpcode(MI: *MII, ForBigCore: ToBigInstrs);
4498
4499 // Change the opcode of the instruction.
4500 if (Opcode >= 0)
4501 MII->setDesc(get(Opcode));
4502}
4503
4504// This function is used to translate instructions to facilitate generating
4505// Duplexes on TinyCore.
4506void HexagonInstrInfo::translateInstrsForDup(MachineFunction &MF,
4507 bool ToBigInstrs) const {
4508 for (auto &MB : MF)
4509 for (MachineBasicBlock::instr_iterator Instr = MB.instr_begin(),
4510 End = MB.instr_end();
4511 Instr != End; ++Instr)
4512 changeDuplexOpcode(MII: Instr, ToBigInstrs);
4513}
4514
4515// This is a specialized form of above function.
4516void HexagonInstrInfo::translateInstrsForDup(
4517 MachineBasicBlock::instr_iterator MII, bool ToBigInstrs) const {
4518 MachineBasicBlock *MBB = MII->getParent();
4519 while ((MII != MBB->instr_end()) && MII->isInsideBundle()) {
4520 changeDuplexOpcode(MII, ToBigInstrs);
4521 ++MII;
4522 }
4523}
4524
4525unsigned HexagonInstrInfo::getMemAccessSize(const MachineInstr &MI) const {
4526 using namespace HexagonII;
4527
4528 const uint64_t F = MI.getDesc().TSFlags;
4529 unsigned S = (F >> MemAccessSizePos) & MemAccesSizeMask;
4530 unsigned Size = getMemAccessSizeInBytes(S: MemAccessSize(S));
4531 if (Size != 0)
4532 return Size;
4533 // Y2_dcfetchbo is special
4534 if (MI.getOpcode() == Hexagon::Y2_dcfetchbo)
4535 return HexagonII::DoubleWordAccess;
4536
4537 // Handle vector access sizes.
4538 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
4539 switch (S) {
4540 case HexagonII::HVXVectorAccess:
4541 return HRI.getSpillSize(RC: Hexagon::HvxVRRegClass);
4542 default:
4543 llvm_unreachable("Unexpected instruction");
4544 }
4545}
4546
4547// Returns the min value that doesn't need to be extended.
4548int HexagonInstrInfo::getMinValue(const MachineInstr &MI) const {
4549 const uint64_t F = MI.getDesc().TSFlags;
4550 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
4551 & HexagonII::ExtentSignedMask;
4552 unsigned bits = (F >> HexagonII::ExtentBitsPos)
4553 & HexagonII::ExtentBitsMask;
4554
4555 if (isSigned) // if value is signed
4556 return -1U << (bits - 1);
4557 else
4558 return 0;
4559}
4560
4561// Returns opcode of the non-extended equivalent instruction.
4562short HexagonInstrInfo::getNonExtOpcode(const MachineInstr &MI) const {
4563 // Check if the instruction has a register form that uses register in place
4564 // of the extended operand, if so return that as the non-extended form.
4565 short NonExtOpcode = Hexagon::getRegForm(Opcode: MI.getOpcode());
4566 if (NonExtOpcode >= 0)
4567 return NonExtOpcode;
4568
4569 if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) {
4570 // Check addressing mode and retrieve non-ext equivalent instruction.
4571 switch (getAddrMode(MI)) {
4572 case HexagonII::Absolute:
4573 return Hexagon::changeAddrMode_abs_io(Opcode: MI.getOpcode());
4574 case HexagonII::BaseImmOffset:
4575 return Hexagon::changeAddrMode_io_rr(Opcode: MI.getOpcode());
4576 case HexagonII::BaseLongOffset:
4577 return Hexagon::changeAddrMode_ur_rr(Opcode: MI.getOpcode());
4578
4579 default:
4580 return -1;
4581 }
4582 }
4583 return -1;
4584}
4585
4586bool HexagonInstrInfo::getPredReg(ArrayRef<MachineOperand> Cond,
4587 Register &PredReg, unsigned &PredRegPos,
4588 RegState &PredRegFlags) const {
4589 if (Cond.empty())
4590 return false;
4591 assert(Cond.size() == 2);
4592 if (isNewValueJump(Opcode: Cond[0].getImm()) || Cond[1].isMBB()) {
4593 LLVM_DEBUG(dbgs() << "No predregs for new-value jumps/endloop");
4594 return false;
4595 }
4596 PredReg = Cond[1].getReg();
4597 PredRegPos = 1;
4598 // See IfConversion.cpp why we add RegState::Implicit | RegState::Undef
4599 PredRegFlags = {};
4600 if (Cond[1].isImplicit())
4601 PredRegFlags = RegState::Implicit;
4602 if (Cond[1].isUndef())
4603 PredRegFlags |= RegState::Undef;
4604 return true;
4605}
4606
4607short HexagonInstrInfo::getPseudoInstrPair(const MachineInstr &MI) const {
4608 return Hexagon::getRealHWInstr(Opcode: MI.getOpcode(), inInstrType: Hexagon::InstrType_Pseudo);
4609}
4610
4611short HexagonInstrInfo::getRegForm(const MachineInstr &MI) const {
4612 return Hexagon::getRegForm(Opcode: MI.getOpcode());
4613}
4614
4615// Return the number of bytes required to encode the instruction.
4616// Hexagon instructions are fixed length, 4 bytes, unless they
4617// use a constant extender, which requires another 4 bytes.
4618// For debug instructions and prolog labels, return 0.
4619unsigned HexagonInstrInfo::getSize(const MachineInstr &MI) const {
4620 if (MI.isDebugInstr() || MI.isPosition())
4621 return 0;
4622
4623 unsigned Size = MI.getDesc().getSize();
4624 if (!Size)
4625 // Assume the default insn size in case it cannot be determined
4626 // for whatever reason.
4627 Size = HEXAGON_INSTR_SIZE;
4628
4629 if (isConstExtended(MI) || isExtended(MI))
4630 Size += HEXAGON_INSTR_SIZE;
4631
4632 // Try and compute number of instructions in asm.
4633 if (BranchRelaxAsmLarge && MI.getOpcode() == Hexagon::INLINEASM) {
4634 const MachineBasicBlock &MBB = *MI.getParent();
4635 const MachineFunction *MF = MBB.getParent();
4636 const MCAsmInfo &MAI = MF->getTarget().getMCAsmInfo();
4637
4638 // Count the number of register definitions to find the asm string.
4639 unsigned NumDefs = 0;
4640 for (; MI.getOperand(i: NumDefs).isReg() && MI.getOperand(i: NumDefs).isDef();
4641 ++NumDefs)
4642 assert(NumDefs != MI.getNumOperands()-2 && "No asm string?");
4643
4644 assert(MI.getOperand(NumDefs).isSymbol() && "No asm string?");
4645 // Disassemble the AsmStr and approximate number of instructions.
4646 const char *AsmStr = MI.getOperand(i: NumDefs).getSymbolName();
4647 Size = getInlineAsmLength(Str: AsmStr, MAI);
4648 }
4649
4650 return Size;
4651}
4652
4653uint64_t HexagonInstrInfo::getType(const MachineInstr &MI) const {
4654 const uint64_t F = MI.getDesc().TSFlags;
4655 return (F >> HexagonII::TypePos) & HexagonII::TypeMask;
4656}
4657
4658InstrStage::FuncUnits HexagonInstrInfo::getUnits(const MachineInstr &MI) const {
4659 const InstrItineraryData &II = *Subtarget.getInstrItineraryData();
4660 const InstrStage &IS = *II.beginStage(ItinClassIndx: MI.getDesc().getSchedClass());
4661
4662 return IS.getUnits();
4663}
4664
4665// Calculate size of the basic block without debug instructions.
4666unsigned HexagonInstrInfo::nonDbgBBSize(const MachineBasicBlock *BB) const {
4667 return nonDbgMICount(MIB: BB->instr_begin(), MIE: BB->instr_end());
4668}
4669
4670unsigned HexagonInstrInfo::nonDbgBundleSize(
4671 MachineBasicBlock::const_iterator BundleHead) const {
4672 assert(BundleHead->isBundle() && "Not a bundle header");
4673 auto MII = BundleHead.getInstrIterator();
4674 // Skip the bundle header.
4675 return nonDbgMICount(MIB: ++MII, MIE: getBundleEnd(I: BundleHead.getInstrIterator()));
4676}
4677
4678/// immediateExtend - Changes the instruction in place to one using an immediate
4679/// extender.
4680void HexagonInstrInfo::immediateExtend(MachineInstr &MI) const {
4681 assert((isExtendable(MI)||isConstExtended(MI)) &&
4682 "Instruction must be extendable");
4683 // Find which operand is extendable.
4684 short ExtOpNum = getCExtOpNum(MI);
4685 MachineOperand &MO = MI.getOperand(i: ExtOpNum);
4686 // This needs to be something we understand.
4687 assert((MO.isMBB() || MO.isImm()) &&
4688 "Branch with unknown extendable field type");
4689 // Mark given operand as extended.
4690 MO.addTargetFlag(F: HexagonII::HMOTF_ConstExtended);
4691}
4692
4693bool HexagonInstrInfo::invertAndChangeJumpTarget(
4694 MachineInstr &MI, MachineBasicBlock *NewTarget) const {
4695 LLVM_DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to "
4696 << printMBBReference(*NewTarget);
4697 MI.dump(););
4698 assert(MI.isBranch());
4699 unsigned NewOpcode = getInvertedPredicatedOpcode(Opc: MI.getOpcode());
4700 int TargetPos = MI.getNumOperands() - 1;
4701 // In general branch target is the last operand,
4702 // but some implicit defs added at the end might change it.
4703 while ((TargetPos > -1) && !MI.getOperand(i: TargetPos).isMBB())
4704 --TargetPos;
4705 assert((TargetPos >= 0) && MI.getOperand(TargetPos).isMBB());
4706 MI.getOperand(i: TargetPos).setMBB(NewTarget);
4707 if (EnableBranchPrediction && isPredicatedNew(MI)) {
4708 NewOpcode = reversePrediction(Opcode: NewOpcode);
4709 }
4710 MI.setDesc(get(Opcode: NewOpcode));
4711 return true;
4712}
4713
4714void HexagonInstrInfo::genAllInsnTimingClasses(MachineFunction &MF) const {
4715 /* +++ The code below is used to generate complete set of Hexagon Insn +++ */
4716 MachineFunction::iterator A = MF.begin();
4717 MachineBasicBlock &B = *A;
4718 MachineBasicBlock::iterator I = B.begin();
4719 DebugLoc DL = I->getDebugLoc();
4720 MachineInstr *NewMI;
4721
4722 for (unsigned insn = TargetOpcode::GENERIC_OP_END+1;
4723 insn < Hexagon::INSTRUCTION_LIST_END; ++insn) {
4724 NewMI = BuildMI(BB&: B, I, MIMD: DL, MCID: get(Opcode: insn));
4725 LLVM_DEBUG(dbgs() << "\n"
4726 << getName(NewMI->getOpcode())
4727 << " Class: " << NewMI->getDesc().getSchedClass());
4728 NewMI->eraseFromParent();
4729 }
4730 /* --- The code above is used to generate complete set of Hexagon Insn --- */
4731}
4732
4733// inverts the predication logic.
4734// p -> NotP
4735// NotP -> P
4736bool HexagonInstrInfo::reversePredSense(MachineInstr &MI) const {
4737 LLVM_DEBUG(dbgs() << "\nTrying to reverse pred. sense of:"; MI.dump());
4738 MI.setDesc(get(Opcode: getInvertedPredicatedOpcode(Opc: MI.getOpcode())));
4739 return true;
4740}
4741
4742// Reverse the branch prediction.
4743unsigned HexagonInstrInfo::reversePrediction(unsigned Opcode) const {
4744 int PredRevOpcode = -1;
4745 if (isPredictedTaken(Opcode))
4746 PredRevOpcode = Hexagon::notTakenBranchPrediction(Opcode);
4747 else
4748 PredRevOpcode = Hexagon::takenBranchPrediction(Opcode);
4749 assert(PredRevOpcode > 0);
4750 return PredRevOpcode;
4751}
4752
4753// TODO: Add more rigorous validation.
4754bool HexagonInstrInfo::validateBranchCond(const ArrayRef<MachineOperand> &Cond)
4755 const {
4756 return Cond.empty() || (Cond[0].isImm() && (Cond.size() != 1));
4757}
4758
4759void HexagonInstrInfo::
4760setBundleNoShuf(MachineBasicBlock::instr_iterator MIB) const {
4761 assert(MIB->isBundle());
4762 MachineOperand &Operand = MIB->getOperand(i: 0);
4763 if (Operand.isImm())
4764 Operand.setImm(Operand.getImm() | memShufDisabledMask);
4765 else
4766 MIB->addOperand(Op: MachineOperand::CreateImm(Val: memShufDisabledMask));
4767}
4768
4769bool HexagonInstrInfo::getBundleNoShuf(const MachineInstr &MIB) const {
4770 assert(MIB.isBundle());
4771 const MachineOperand &Operand = MIB.getOperand(i: 0);
4772 return (Operand.isImm() && (Operand.getImm() & memShufDisabledMask) != 0);
4773}
4774
4775bool HexagonInstrInfo::isQFPMul(const MachineInstr *MI) const {
4776 return (MI->getOpcode() == Hexagon::V6_vmpy_qf16_hf ||
4777 MI->getOpcode() == Hexagon::V6_vmpy_qf16_mix_hf ||
4778 MI->getOpcode() == Hexagon::V6_vmpy_qf32_hf ||
4779 MI->getOpcode() == Hexagon::V6_vmpy_qf32_mix_hf ||
4780 MI->getOpcode() == Hexagon::V6_vmpy_qf32_sf ||
4781 MI->getOpcode() == Hexagon::V6_vmpy_qf16_mix_hf ||
4782 MI->getOpcode() == Hexagon::V6_vmpy_qf16 ||
4783 MI->getOpcode() == Hexagon::V6_vmpy_qf32_mix_hf ||
4784 MI->getOpcode() == Hexagon::V6_vmpy_qf32_qf16 ||
4785 MI->getOpcode() == Hexagon::V6_vmpy_qf32);
4786}
4787
4788namespace llvm::HexagonII {
4789
4790static constexpr RegTypeInfo make(RegType Out, RegType In1 = RegType::Unknown,
4791 RegType In2 = RegType::Unknown,
4792 RegType In3 = RegType::Unknown) {
4793 RegTypeInfo I;
4794 I.Output = Out;
4795 I.Input1 = In1;
4796 I.Input2 = In2;
4797 I.Input3 = In3;
4798 return I;
4799}
4800
4801RegTypeInfo getRegTypeInfo(unsigned Opcode) {
4802 switch (Opcode) {
4803 default:
4804 return {};
4805
4806 case Hexagon::V6_vabs_qf16_hf:
4807 return make(Out: RegType::QF16);
4808 case Hexagon::V6_vabs_qf16_qf16:
4809 return make(Out: RegType::QF16, In1: RegType::QF16);
4810 case Hexagon::V6_vabs_qf32_qf32:
4811 return make(Out: RegType::QF32, In1: RegType::QF32);
4812 case Hexagon::V6_vabs_qf32_sf:
4813 return make(Out: RegType::QF32);
4814 case Hexagon::V6_vadd_hf:
4815 return make(Out: RegType::QF16);
4816 case Hexagon::V6_vadd_qf16:
4817 return make(Out: RegType::QF16, In1: RegType::QF16, In2: RegType::QF16);
4818 case Hexagon::V6_vadd_qf16_mix:
4819 return make(Out: RegType::QF16, In1: RegType::QF16);
4820 case Hexagon::V6_vadd_qf32:
4821 return make(Out: RegType::QF32, In1: RegType::QF32, In2: RegType::QF32);
4822 case Hexagon::V6_vadd_qf32_mix:
4823 return make(Out: RegType::QF32, In1: RegType::QF32);
4824 case Hexagon::V6_vadd_sf:
4825 return make(Out: RegType::QF32);
4826 case Hexagon::V6_vconv_bf_qf32:
4827 return make(Out: RegType::Unknown, In1: RegType::QF32);
4828 case Hexagon::V6_vconv_f8_qf16:
4829 return make(Out: RegType::Unknown, In1: RegType::QF16);
4830 case Hexagon::V6_vconv_hf_qf16:
4831 return make(Out: RegType::Unknown, In1: RegType::QF16);
4832 case Hexagon::V6_vconv_hf_qf32:
4833 return make(Out: RegType::Unknown, In1: RegType::QF32);
4834 case Hexagon::V6_vconv_qf16_f8:
4835 return make(Out: RegType::QF16);
4836 case Hexagon::V6_vconv_qf16_hf:
4837 return make(Out: RegType::QF16);
4838 case Hexagon::V6_vconv_qf16_qf16:
4839 return make(Out: RegType::QF16, In1: RegType::QF16);
4840 case Hexagon::V6_vconv_qf32_qf32:
4841 return make(Out: RegType::QF32, In1: RegType::QF32);
4842 case Hexagon::V6_vconv_qf32_sf:
4843 return make(Out: RegType::QF32);
4844 case Hexagon::V6_vconv_sf_qf32:
4845 return make(Out: RegType::Unknown, In1: RegType::QF32);
4846 case Hexagon::V6_vilog2_qf16:
4847 return make(Out: RegType::Unknown, In1: RegType::QF16);
4848 case Hexagon::V6_vilog2_qf32:
4849 return make(Out: RegType::Unknown, In1: RegType::QF32);
4850 case Hexagon::V6_vmpy_qf16:
4851 return make(Out: RegType::QF16, In1: RegType::QF16, In2: RegType::QF16);
4852 case Hexagon::V6_vmpy_qf16_hf:
4853 return make(Out: RegType::QF16);
4854 case Hexagon::V6_vmpy_qf16_mix_hf:
4855 return make(Out: RegType::QF16, In1: RegType::QF16);
4856 case Hexagon::V6_vmpy_qf32:
4857 return make(Out: RegType::QF32, In1: RegType::QF32, In2: RegType::QF32);
4858 case Hexagon::V6_vmpy_qf32_hf:
4859 return make(Out: RegType::QF32);
4860 case Hexagon::V6_vmpy_qf32_mix_hf:
4861 return make(Out: RegType::QF32, In1: RegType::QF16);
4862 case Hexagon::V6_vmpy_qf32_qf16:
4863 return make(Out: RegType::QF32, In1: RegType::QF16, In2: RegType::QF16);
4864 case Hexagon::V6_vmpy_qf32_sf:
4865 return make(Out: RegType::QF32);
4866 case Hexagon::V6_vmpy_rt_hf:
4867 return make(Out: RegType::QF16);
4868 case Hexagon::V6_vmpy_rt_qf16:
4869 return make(Out: RegType::QF16, In1: RegType::QF16);
4870 case Hexagon::V6_vmpy_rt_sf:
4871 return make(Out: RegType::QF32);
4872 case Hexagon::V6_vneg_qf16_hf:
4873 return make(Out: RegType::QF16);
4874 case Hexagon::V6_vneg_qf16_qf16:
4875 return make(Out: RegType::QF16, In1: RegType::QF16);
4876 case Hexagon::V6_vneg_qf32_qf32:
4877 return make(Out: RegType::QF32, In1: RegType::QF32);
4878 case Hexagon::V6_vneg_qf32_sf:
4879 return make(Out: RegType::QF32);
4880 case Hexagon::V6_vsub_hf:
4881 return make(Out: RegType::QF16);
4882 case Hexagon::V6_vsub_qf16:
4883 return make(Out: RegType::QF16, In1: RegType::QF16, In2: RegType::QF16);
4884 case Hexagon::V6_vsub_qf16_mix:
4885 return make(Out: RegType::QF16, In1: RegType::QF16);
4886 case Hexagon::V6_vsub_qf32:
4887 return make(Out: RegType::QF32, In1: RegType::QF32, In2: RegType::QF32);
4888 case Hexagon::V6_vsub_qf32_mix:
4889 return make(Out: RegType::QF32, In1: RegType::QF32);
4890 case Hexagon::V6_vsub_sf:
4891 return make(Out: RegType::QF32);
4892 case Hexagon::V6_vsub_sf_mix:
4893 return make(Out: RegType::QF32, In1: RegType::Unknown, In2: RegType::QF32);
4894 case Hexagon::V6_vsub_hf_mix:
4895 return make(Out: RegType::QF16, In1: RegType::Unknown, In2: RegType::QF16);
4896 }
4897}
4898
4899} // namespace llvm::HexagonII
4900
4901bool HexagonInstrInfo::usesQF32Operand(MachineInstr *MI, unsigned Index) const {
4902 auto Info = HexagonII::getRegTypeInfo(Opcode: MI->getOpcode());
4903 switch (Index) {
4904 case 1:
4905 return Info.Input1 == HexagonII::RegType::QF32;
4906 case 2:
4907 return Info.Input2 == HexagonII::RegType::QF32;
4908 case 3:
4909 return Info.Input3 == HexagonII::RegType::QF32;
4910 case 0:
4911 return Info.Input1 == HexagonII::RegType::QF32 ||
4912 Info.Input2 == HexagonII::RegType::QF32 ||
4913 Info.Input3 == HexagonII::RegType::QF32;
4914 default: // No instruction with more than 3 operands uses QF32.
4915 return false;
4916 }
4917 return false;
4918}
4919
4920bool HexagonInstrInfo::usesQF16Operand(MachineInstr *MI, unsigned Index) const {
4921 auto Info = HexagonII::getRegTypeInfo(Opcode: MI->getOpcode());
4922 switch (Index) {
4923 case 1:
4924 return Info.Input1 == HexagonII::RegType::QF16;
4925 case 2:
4926 return Info.Input2 == HexagonII::RegType::QF16;
4927 case 3:
4928 return Info.Input3 == HexagonII::RegType::QF16;
4929 case 0:
4930 return Info.Input1 == HexagonII::RegType::QF16 ||
4931 Info.Input2 == HexagonII::RegType::QF16 ||
4932 Info.Input3 == HexagonII::RegType::QF16;
4933 default: // No instruction with more than 3 operands uses QF16.
4934 return false;
4935 }
4936 return false;
4937}
4938
4939bool HexagonInstrInfo::usesQFOperand(MachineInstr *MI, unsigned Index) const {
4940 return usesQF32Operand(MI, Index) || usesQF16Operand(MI, Index);
4941}
4942
4943bool HexagonInstrInfo::isQFP32Instr(MachineInstr *MI) const {
4944 return HexagonII::getOpRegType(Opcode: MI->getOpcode()) == HexagonII::RegType::QF32;
4945}
4946
4947bool HexagonInstrInfo::isQFP16Instr(MachineInstr *MI) const {
4948 return HexagonII::getOpRegType(Opcode: MI->getOpcode()) == HexagonII::RegType::QF16;
4949}
4950
4951bool HexagonInstrInfo::isQFPInstr(MachineInstr *MI) const {
4952 return isQFP32Instr(MI) || isQFP16Instr(MI);
4953}
4954
4955// Return true if the function contains any qf-generating instructions.
4956bool HexagonInstrInfo::hasQFPInstrs(const MachineFunction &MF) const {
4957 for (const MachineBasicBlock &MBB : MF)
4958 for (const MachineInstr &MI : MBB)
4959 if (isQFPInstr(MI: const_cast<MachineInstr *>(&MI)))
4960 return true;
4961 return false;
4962}
4963
4964// Returns true if A appears before B within the same basic block.
4965bool HexagonInstrInfo::isMIBefore(const MachineInstr *A,
4966 const MachineInstr *B) const {
4967 if (!A || !B || A->getParent() != B->getParent())
4968 return false;
4969
4970 for (const MachineInstr &MI : *A->getParent()) {
4971 if (&MI == A)
4972 return true;
4973 if (&MI == B)
4974 return false;
4975 }
4976 return false;
4977}
4978
4979// Addressing mode relations.
4980short HexagonInstrInfo::changeAddrMode_abs_io(short Opc) const {
4981 return Opc >= 0 ? Hexagon::changeAddrMode_abs_io(Opcode: Opc) : Opc;
4982}
4983
4984short HexagonInstrInfo::changeAddrMode_io_abs(short Opc) const {
4985 return Opc >= 0 ? Hexagon::changeAddrMode_io_abs(Opcode: Opc) : Opc;
4986}
4987
4988short HexagonInstrInfo::changeAddrMode_io_pi(short Opc) const {
4989 return Opc >= 0 ? Hexagon::changeAddrMode_io_pi(Opcode: Opc) : Opc;
4990}
4991
4992short HexagonInstrInfo::changeAddrMode_io_rr(short Opc) const {
4993 return Opc >= 0 ? Hexagon::changeAddrMode_io_rr(Opcode: Opc) : Opc;
4994}
4995
4996short HexagonInstrInfo::changeAddrMode_pi_io(short Opc) const {
4997 return Opc >= 0 ? Hexagon::changeAddrMode_pi_io(Opcode: Opc) : Opc;
4998}
4999
5000short HexagonInstrInfo::changeAddrMode_rr_io(short Opc) const {
5001 return Opc >= 0 ? Hexagon::changeAddrMode_rr_io(Opcode: Opc) : Opc;
5002}
5003
5004short HexagonInstrInfo::changeAddrMode_rr_ur(short Opc) const {
5005 return Opc >= 0 ? Hexagon::changeAddrMode_rr_ur(Opcode: Opc) : Opc;
5006}
5007
5008short HexagonInstrInfo::changeAddrMode_ur_rr(short Opc) const {
5009 return Opc >= 0 ? Hexagon::changeAddrMode_ur_rr(Opcode: Opc) : Opc;
5010}
5011
5012MCInst HexagonInstrInfo::getNop() const {
5013 static const MCInst Nop = MCInstBuilder(Hexagon::A2_nop);
5014
5015 return MCInstBuilder(Hexagon::BUNDLE)
5016 .addImm(Val: 0)
5017 .addInst(Val: &Nop);
5018}
5019