1//===- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a printer that converts from our internal representation
10// of machine-dependent LLVM code to GAS-format MIPS assembly language.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MipsAsmPrinter.h"
15#include "MCTargetDesc/MipsABIInfo.h"
16#include "MCTargetDesc/MipsBaseInfo.h"
17#include "MCTargetDesc/MipsInstPrinter.h"
18#include "MCTargetDesc/MipsMCAsmInfo.h"
19#include "MCTargetDesc/MipsMCTargetDesc.h"
20#include "MCTargetDesc/MipsTargetStreamer.h"
21#include "Mips.h"
22#include "MipsMCInstLower.h"
23#include "MipsMachineFunction.h"
24#include "MipsSubtarget.h"
25#include "MipsTargetMachine.h"
26#include "TargetInfo/MipsTargetInfo.h"
27#include "llvm/ADT/SmallString.h"
28#include "llvm/ADT/StringRef.h"
29#include "llvm/ADT/Twine.h"
30#include "llvm/BinaryFormat/ELF.h"
31#include "llvm/CodeGen/MachineBasicBlock.h"
32#include "llvm/CodeGen/MachineConstantPool.h"
33#include "llvm/CodeGen/MachineFrameInfo.h"
34#include "llvm/CodeGen/MachineFunction.h"
35#include "llvm/CodeGen/MachineInstr.h"
36#include "llvm/CodeGen/MachineJumpTableInfo.h"
37#include "llvm/CodeGen/MachineOperand.h"
38#include "llvm/CodeGen/TargetRegisterInfo.h"
39#include "llvm/CodeGen/TargetSubtargetInfo.h"
40#include "llvm/IR/Attributes.h"
41#include "llvm/IR/BasicBlock.h"
42#include "llvm/IR/DataLayout.h"
43#include "llvm/IR/Function.h"
44#include "llvm/IR/InlineAsm.h"
45#include "llvm/IR/Instructions.h"
46#include "llvm/IR/Module.h"
47#include "llvm/MC/MCContext.h"
48#include "llvm/MC/MCExpr.h"
49#include "llvm/MC/MCInst.h"
50#include "llvm/MC/MCInstBuilder.h"
51#include "llvm/MC/MCObjectFileInfo.h"
52#include "llvm/MC/MCSectionELF.h"
53#include "llvm/MC/MCSymbol.h"
54#include "llvm/MC/TargetRegistry.h"
55#include "llvm/Support/Casting.h"
56#include "llvm/Support/Compiler.h"
57#include "llvm/Support/ErrorHandling.h"
58#include "llvm/Support/raw_ostream.h"
59#include "llvm/Target/TargetLoweringObjectFile.h"
60#include "llvm/Target/TargetMachine.h"
61#include "llvm/TargetParser/Triple.h"
62#include <cassert>
63#include <cstdint>
64#include <map>
65#include <memory>
66#include <string>
67#include <vector>
68
69using namespace llvm;
70
71#define DEBUG_TYPE "mips-asm-printer"
72
73extern cl::opt<bool> EmitJalrReloc;
74
75MipsTargetStreamer &MipsAsmPrinter::getTargetStreamer() const {
76 return static_cast<MipsTargetStreamer &>(*OutStreamer->getTargetStreamer());
77}
78
79bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
80 Subtarget = &MF.getSubtarget<MipsSubtarget>();
81
82 MipsFI = MF.getInfo<MipsFunctionInfo>();
83 if (Subtarget->inMips16Mode())
84 for (const auto &I : MipsFI->StubsNeeded)
85 StubsNeeded.insert(x: I);
86 MCP = MF.getConstantPool();
87
88 AsmPrinter::runOnMachineFunction(MF);
89
90 emitXRayTable();
91
92 return true;
93}
94
95bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {
96 MCOp = MCInstLowering.LowerOperand(MO);
97 return MCOp.isValid();
98}
99
100#include "MipsGenMCPseudoLowering.inc"
101
102// Lower PseudoReturn/PseudoIndirectBranch/PseudoIndirectBranch64 to JR, JR_MM,
103// JALR, or JALR64 as appropriate for the target.
104void MipsAsmPrinter::emitPseudoIndirectBranch(MCStreamer &OutStreamer,
105 const MachineInstr *MI) {
106 bool HasLinkReg = false;
107 bool InMicroMipsMode = Subtarget->inMicroMipsMode();
108 MCInst TmpInst0;
109
110 if (Subtarget->hasMips64r6()) {
111 // MIPS64r6 should use (JALR64 ZERO_64, $rs)
112 TmpInst0.setOpcode(Mips::JALR64);
113 HasLinkReg = true;
114 } else if (Subtarget->hasMips32r6()) {
115 // MIPS32r6 should use (JALR ZERO, $rs)
116 if (InMicroMipsMode)
117 TmpInst0.setOpcode(Mips::JRC16_MMR6);
118 else {
119 TmpInst0.setOpcode(Mips::JALR);
120 HasLinkReg = true;
121 }
122 } else if (Subtarget->inMicroMipsMode())
123 // microMIPS should use (JR_MM $rs)
124 TmpInst0.setOpcode(Mips::JR_MM);
125 else {
126 // Everything else should use (JR $rs)
127 TmpInst0.setOpcode(Mips::JR);
128 }
129
130 MCOperand MCOp;
131
132 if (HasLinkReg) {
133 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
134 TmpInst0.addOperand(Op: MCOperand::createReg(Reg: ZeroReg));
135 }
136
137 lowerOperand(MO: MI->getOperand(i: 0), MCOp);
138 TmpInst0.addOperand(Op: MCOp);
139
140 EmitToStreamer(S&: OutStreamer, Inst: TmpInst0);
141}
142
143// If there is an MO_JALR operand, insert:
144//
145// .reloc tmplabel, R_{MICRO}MIPS_JALR, symbol
146// tmplabel:
147//
148// This is an optimization hint for the linker which may then replace
149// an indirect call with a direct branch.
150static void emitDirectiveRelocJalr(const MachineInstr &MI,
151 MCContext &OutContext,
152 TargetMachine &TM,
153 MCStreamer &OutStreamer,
154 const MipsSubtarget &Subtarget) {
155 for (const MachineOperand &MO :
156 llvm::drop_begin(RangeOrContainer: MI.operands(), N: MI.getDesc().getNumOperands())) {
157 if (MO.isMCSymbol() && (MO.getTargetFlags() & MipsII::MO_JALR)) {
158 MCSymbol *Callee = MO.getMCSymbol();
159 if (Callee && !Callee->getName().empty()) {
160 MCSymbol *OffsetLabel = OutContext.createTempSymbol();
161 const MCExpr *OffsetExpr =
162 MCSymbolRefExpr::create(Symbol: OffsetLabel, Ctx&: OutContext);
163 const MCExpr *CaleeExpr =
164 MCSymbolRefExpr::create(Symbol: Callee, Ctx&: OutContext);
165 OutStreamer.emitRelocDirective(
166 Offset: *OffsetExpr,
167 Name: Subtarget.inMicroMipsMode() ? "R_MICROMIPS_JALR" : "R_MIPS_JALR",
168 Expr: CaleeExpr);
169 OutStreamer.emitLabel(Symbol: OffsetLabel);
170 return;
171 }
172 }
173 }
174}
175
176void MipsAsmPrinter::emitInstruction(const MachineInstr *MI) {
177 // FIXME: Enable feature predicate checks once all the test pass.
178 // Mips_MC::verifyInstructionPredicates(MI->getOpcode(),
179 // getSubtargetInfo().getFeatureBits());
180
181 MipsTargetStreamer &TS = getTargetStreamer();
182 unsigned Opc = MI->getOpcode();
183 TS.forbidModuleDirective();
184
185 if (MI->isDebugValue()) {
186 SmallString<128> Str;
187 raw_svector_ostream OS(Str);
188
189 PrintDebugValueComment(MI, OS);
190 return;
191 }
192 if (MI->isDebugLabel())
193 return;
194
195 // If we just ended a constant pool, mark it as such.
196 if (InConstantPool && Opc != Mips::CONSTPOOL_ENTRY) {
197 OutStreamer->emitDataRegion(Kind: MCDR_DataRegionEnd);
198 InConstantPool = false;
199 }
200 if (Opc == Mips::CONSTPOOL_ENTRY) {
201 // CONSTPOOL_ENTRY - This instruction represents a floating
202 // constant pool in the function. The first operand is the ID#
203 // for this instruction, the second is the index into the
204 // MachineConstantPool that this is, the third is the size in
205 // bytes of this constant pool entry.
206 // The required alignment is specified on the basic block holding this MI.
207 //
208 unsigned LabelId = (unsigned)MI->getOperand(i: 0).getImm();
209 unsigned CPIdx = (unsigned)MI->getOperand(i: 1).getIndex();
210
211 // If this is the first entry of the pool, mark it.
212 if (!InConstantPool) {
213 OutStreamer->emitDataRegion(Kind: MCDR_DataRegion);
214 InConstantPool = true;
215 }
216
217 OutStreamer->emitLabel(Symbol: GetCPISymbol(CPID: LabelId));
218
219 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
220 if (MCPE.isMachineConstantPoolEntry())
221 emitMachineConstantPoolValue(MCPV: MCPE.Val.MachineCPVal);
222 else
223 emitGlobalConstant(DL: MF->getDataLayout(), CV: MCPE.Val.ConstVal);
224 return;
225 }
226
227 switch (Opc) {
228 case Mips::PATCHABLE_FUNCTION_ENTER:
229 LowerPATCHABLE_FUNCTION_ENTER(MI: *MI);
230 return;
231 case Mips::PATCHABLE_FUNCTION_EXIT:
232 LowerPATCHABLE_FUNCTION_EXIT(MI: *MI);
233 return;
234 case Mips::PATCHABLE_TAIL_CALL:
235 LowerPATCHABLE_TAIL_CALL(MI: *MI);
236 return;
237 }
238
239 if (EmitJalrReloc &&
240 (MI->isReturn() || MI->isCall() || MI->isIndirectBranch())) {
241 emitDirectiveRelocJalr(MI: *MI, OutContext, TM, OutStreamer&: *OutStreamer, Subtarget: *Subtarget);
242 }
243
244 MachineBasicBlock::const_instr_iterator I = MI->getIterator();
245 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
246
247 do {
248 // Do any auto-generated pseudo lowerings.
249 if (MCInst OutInst; lowerPseudoInstExpansion(MI: &*I, Inst&: OutInst)) {
250 EmitToStreamer(S&: *OutStreamer, Inst: OutInst);
251 continue;
252 }
253
254 // Skip the BUNDLE pseudo instruction and lower the contents
255 if (I->isBundle())
256 continue;
257
258 if (I->getOpcode() == Mips::PseudoReturn ||
259 I->getOpcode() == Mips::PseudoReturn64 ||
260 I->getOpcode() == Mips::PseudoIndirectBranch ||
261 I->getOpcode() == Mips::PseudoIndirectBranch64 ||
262 I->getOpcode() == Mips::TAILCALLREG ||
263 I->getOpcode() == Mips::TAILCALLREG64) {
264 emitPseudoIndirectBranch(OutStreamer&: *OutStreamer, MI: &*I);
265 continue;
266 }
267
268 // The inMips16Mode() test is not permanent.
269 // Some instructions are marked as pseudo right now which
270 // would make the test fail for the wrong reason but
271 // that will be fixed soon. We need this here because we are
272 // removing another test for this situation downstream in the
273 // callchain.
274 //
275 if (I->isPseudo() && !Subtarget->inMips16Mode()
276 && !isLongBranchPseudo(Opcode: I->getOpcode()))
277 llvm_unreachable("Pseudo opcode found in emitInstruction()");
278
279 MCInst TmpInst0;
280 MCInstLowering.Lower(MI: &*I, OutMI&: TmpInst0);
281 EmitToStreamer(S&: *OutStreamer, Inst: TmpInst0);
282 } while ((++I != E) && I->isInsideBundle()); // Delay slot check
283}
284
285//===----------------------------------------------------------------------===//
286//
287// Mips Asm Directives
288//
289// -- Frame directive "frame Stackpointer, Stacksize, RARegister"
290// Describe the stack frame.
291//
292// -- Mask directives "(f)mask bitmask, offset"
293// Tells the assembler which registers are saved and where.
294// bitmask - contain a little endian bitset indicating which registers are
295// saved on function prologue (e.g. with a 0x80000000 mask, the
296// assembler knows the register 31 (RA) is saved at prologue.
297// offset - the position before stack pointer subtraction indicating where
298// the first saved register on prologue is located. (e.g. with a
299//
300// Consider the following function prologue:
301//
302// .frame $fp,48,$ra
303// .mask 0xc0000000,-8
304// addiu $sp, $sp, -48
305// sw $ra, 40($sp)
306// sw $fp, 36($sp)
307//
308// With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
309// 30 (FP) are saved at prologue. As the save order on prologue is from
310// left to right, RA is saved first. A -8 offset means that after the
311// stack pointer subtration, the first register in the mask (RA) will be
312// saved at address 48-8=40.
313//
314//===----------------------------------------------------------------------===//
315
316//===----------------------------------------------------------------------===//
317// Mask directives
318//===----------------------------------------------------------------------===//
319
320// Create a bitmask with all callee saved registers for CPU or Floating Point
321// registers. For CPU registers consider RA, GP and FP for saving if necessary.
322void MipsAsmPrinter::printSavedRegsBitmask() {
323 // CPU and FPU Saved Registers Bitmasks
324 unsigned CPUBitmask = 0, FPUBitmask = 0;
325 int CPUTopSavedRegOff, FPUTopSavedRegOff;
326
327 // Set the CPU and FPU Bitmasks
328 const MachineFrameInfo &MFI = MF->getFrameInfo();
329 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
330 const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
331 // size of stack area to which FP callee-saved regs are saved.
332 unsigned CPURegSize = TRI->getRegSizeInBits(RC: Mips::GPR32RegClass) / 8;
333 unsigned FGR32RegSize = TRI->getRegSizeInBits(RC: Mips::FGR32RegClass) / 8;
334 unsigned AFGR64RegSize = TRI->getRegSizeInBits(RC: Mips::AFGR64RegClass) / 8;
335 bool HasAFGR64Reg = false;
336 unsigned CSFPRegsSize = 0;
337
338 for (const auto &I : CSI) {
339 Register Reg = I.getReg();
340 unsigned RegNum = TRI->getEncodingValue(Reg);
341
342 // If it's a floating point register, set the FPU Bitmask.
343 // If it's a general purpose register, set the CPU Bitmask.
344 if (Mips::FGR32RegClass.contains(Reg)) {
345 FPUBitmask |= (1 << RegNum);
346 CSFPRegsSize += FGR32RegSize;
347 } else if (Mips::AFGR64RegClass.contains(Reg)) {
348 FPUBitmask |= (3 << RegNum);
349 CSFPRegsSize += AFGR64RegSize;
350 HasAFGR64Reg = true;
351 } else if (Mips::GPR32RegClass.contains(Reg))
352 CPUBitmask |= (1 << RegNum);
353 }
354
355 // FP Regs are saved right below where the virtual frame pointer points to.
356 FPUTopSavedRegOff = FPUBitmask ?
357 (HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
358
359 // CPU Regs are saved below FP Regs.
360 CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
361
362 MipsTargetStreamer &TS = getTargetStreamer();
363 // Print CPUBitmask
364 TS.emitMask(CPUBitmask, CPUTopSavedRegOff);
365
366 // Print FPUBitmask
367 TS.emitFMask(FPUBitmask, FPUTopSavedRegOff);
368}
369
370//===----------------------------------------------------------------------===//
371// Frame and Set directives
372//===----------------------------------------------------------------------===//
373
374/// Frame Directive
375void MipsAsmPrinter::emitFrameDirective() {
376 const TargetRegisterInfo &RI = *MF->getSubtarget().getRegisterInfo();
377
378 Register stackReg = RI.getFrameRegister(MF: *MF);
379 MCRegister returnReg = RI.getRARegister();
380 unsigned stackSize = MF->getFrameInfo().getStackSize();
381
382 getTargetStreamer().emitFrame(StackReg: stackReg, StackSize: stackSize, ReturnReg: returnReg);
383}
384
385/// Emit Set directives.
386const char *MipsAsmPrinter::getCurrentABIString() const {
387 switch (static_cast<MipsTargetMachine &>(TM).getABI().GetEnumValue()) {
388 case MipsABIInfo::ABI::O32: return "abi32";
389 case MipsABIInfo::ABI::N32: return "abiN32";
390 case MipsABIInfo::ABI::N64: return "abi64";
391 default: llvm_unreachable("Unknown Mips ABI");
392 }
393}
394
395void MipsAsmPrinter::emitFunctionEntryLabel() {
396 MipsTargetStreamer &TS = getTargetStreamer();
397
398 if (Subtarget->inMicroMipsMode()) {
399 TS.emitDirectiveSetMicroMips();
400 TS.setUsesMicroMips();
401 TS.updateABIInfo(P: *Subtarget);
402 } else
403 TS.emitDirectiveSetNoMicroMips();
404
405 if (Subtarget->inMips16Mode())
406 TS.emitDirectiveSetMips16();
407 else
408 TS.emitDirectiveSetNoMips16();
409
410 TS.emitDirectiveEnt(Symbol: *CurrentFnSym);
411 OutStreamer->emitLabel(Symbol: CurrentFnSym);
412}
413
414/// EmitFunctionBodyStart - Targets can override this to emit stuff before
415/// the first basic block in the function.
416void MipsAsmPrinter::emitFunctionBodyStart() {
417 MipsTargetStreamer &TS = getTargetStreamer();
418
419 MCInstLowering.Initialize(C: &MF->getContext());
420
421 bool IsNakedFunction = MF->getFunction().hasFnAttribute(Kind: Attribute::Naked);
422 if (!IsNakedFunction)
423 emitFrameDirective();
424
425 if (!IsNakedFunction)
426 printSavedRegsBitmask();
427
428 if (!Subtarget->inMips16Mode()) {
429 TS.emitDirectiveSetNoReorder();
430 TS.emitDirectiveSetNoMacro();
431 TS.emitDirectiveSetNoAt();
432 }
433}
434
435/// EmitFunctionBodyEnd - Targets can override this to emit stuff after
436/// the last basic block in the function.
437void MipsAsmPrinter::emitFunctionBodyEnd() {
438 MipsTargetStreamer &TS = getTargetStreamer();
439
440 // There are instruction for this macros, but they must
441 // always be at the function end, and we can't emit and
442 // break with BB logic.
443 if (!Subtarget->inMips16Mode()) {
444 TS.emitDirectiveSetAt();
445 TS.emitDirectiveSetMacro();
446 TS.emitDirectiveSetReorder();
447 }
448 TS.emitDirectiveEnd(Name: CurrentFnSym->getName());
449 // Make sure to terminate any constant pools that were at the end
450 // of the function.
451 if (!InConstantPool)
452 return;
453 InConstantPool = false;
454 OutStreamer->emitDataRegion(Kind: MCDR_DataRegionEnd);
455}
456
457void MipsAsmPrinter::emitBasicBlockEnd(const MachineBasicBlock &MBB) {
458 AsmPrinter::emitBasicBlockEnd(MBB);
459 MipsTargetStreamer &TS = getTargetStreamer();
460 if (MBB.empty())
461 TS.emitDirectiveInsn();
462}
463
464// Print out an operand for an inline asm expression.
465bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
466 const char *ExtraCode, raw_ostream &O) {
467 // Does this asm operand have a single letter operand modifier?
468 if (ExtraCode && ExtraCode[0]) {
469 if (ExtraCode[1] != 0) return true; // Unknown modifier.
470
471 const MachineOperand &MO = MI->getOperand(i: OpNum);
472 switch (ExtraCode[0]) {
473 default:
474 // See if this is a generic print operand
475 return AsmPrinter::PrintAsmOperand(MI, OpNo: OpNum, ExtraCode, OS&: O);
476 case 'X': // hex const int
477 if (!MO.isImm())
478 return true;
479 O << "0x" << Twine::utohexstr(Val: MO.getImm());
480 return false;
481 case 'x': // hex const int (low 16 bits)
482 if (!MO.isImm())
483 return true;
484 O << "0x" << Twine::utohexstr(Val: MO.getImm() & 0xffff);
485 return false;
486 case 'd': // decimal const int
487 if (!MO.isImm())
488 return true;
489 O << MO.getImm();
490 return false;
491 case 'm': // decimal const int minus 1
492 if (!MO.isImm())
493 return true;
494 O << MO.getImm() - 1;
495 return false;
496 case 'y': // exact log2
497 if (!MO.isImm())
498 return true;
499 if (!isPowerOf2_64(Value: MO.getImm()))
500 return true;
501 O << Log2_64(Value: MO.getImm());
502 return false;
503 case 'z':
504 // $0 if zero, regular printing otherwise
505 if (MO.isImm() && MO.getImm() == 0) {
506 O << "$0";
507 return false;
508 }
509 // If not, call printOperand as normal.
510 break;
511 case 'D': // Second part of a double word register operand
512 case 'L': // Low order register of a double word register operand
513 case 'M': // High order register of a double word register operand
514 {
515 if (OpNum == 0)
516 return true;
517 const MachineOperand &FlagsOP = MI->getOperand(i: OpNum - 1);
518 if (!FlagsOP.isImm())
519 return true;
520 const InlineAsm::Flag Flags(FlagsOP.getImm());
521 const unsigned NumVals = Flags.getNumOperandRegisters();
522 // Number of registers represented by this operand. We are looking
523 // for 2 for 32 bit mode and 1 for 64 bit mode.
524 if (NumVals != 2) {
525 if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
526 Register Reg = MO.getReg();
527 O << '$' << MipsInstPrinter::getRegisterName(Reg);
528 return false;
529 }
530 return true;
531 }
532
533 unsigned RegOp = OpNum;
534 if (!Subtarget->isGP64bit()){
535 // Endianness reverses which register holds the high or low value
536 // between M and L.
537 switch(ExtraCode[0]) {
538 case 'M':
539 RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
540 break;
541 case 'L':
542 RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
543 break;
544 case 'D': // Always the second part
545 RegOp = OpNum + 1;
546 }
547 if (RegOp >= MI->getNumOperands())
548 return true;
549 const MachineOperand &MO = MI->getOperand(i: RegOp);
550 if (!MO.isReg())
551 return true;
552 Register Reg = MO.getReg();
553 O << '$' << MipsInstPrinter::getRegisterName(Reg);
554 return false;
555 }
556 break;
557 }
558 case 'w': {
559 MCRegister w = getMSARegFromFReg(Reg: MO.getReg());
560 if (w != Mips::NoRegister) {
561 O << '$' << MipsInstPrinter::getRegisterName(Reg: w);
562 return false;
563 }
564 break;
565 }
566 }
567 }
568
569 printOperand(MI, opNum: OpNum, O);
570 return false;
571}
572
573bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
574 unsigned OpNum,
575 const char *ExtraCode,
576 raw_ostream &O) {
577 assert(OpNum + 1 < MI->getNumOperands() && "Insufficient operands");
578 const MachineOperand &BaseMO = MI->getOperand(i: OpNum);
579 const MachineOperand &OffsetMO = MI->getOperand(i: OpNum + 1);
580 assert(BaseMO.isReg() &&
581 "Unexpected base pointer for inline asm memory operand.");
582 assert(OffsetMO.isImm() &&
583 "Unexpected offset for inline asm memory operand.");
584 int Offset = OffsetMO.getImm();
585
586 // Currently we are expecting either no ExtraCode or 'D','M','L'.
587 if (ExtraCode) {
588 switch (ExtraCode[0]) {
589 case 'D':
590 Offset += 4;
591 break;
592 case 'M':
593 if (Subtarget->isLittle())
594 Offset += 4;
595 break;
596 case 'L':
597 if (!Subtarget->isLittle())
598 Offset += 4;
599 break;
600 default:
601 return true; // Unknown modifier.
602 }
603 }
604
605 O << Offset << "($" << MipsInstPrinter::getRegisterName(Reg: BaseMO.getReg())
606 << ")";
607
608 return false;
609}
610
611void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
612 raw_ostream &O) {
613 const MachineOperand &MO = MI->getOperand(i: opNum);
614 bool closeP = false;
615
616 if (MO.getTargetFlags())
617 closeP = true;
618
619 switch(MO.getTargetFlags()) {
620 case MipsII::MO_GPREL: O << "%gp_rel("; break;
621 case MipsII::MO_GOT_CALL: O << "%call16("; break;
622 case MipsII::MO_GOT: O << "%got("; break;
623 case MipsII::MO_ABS_HI: O << "%hi("; break;
624 case MipsII::MO_ABS_LO: O << "%lo("; break;
625 case MipsII::MO_HIGHER: O << "%higher("; break;
626 case MipsII::MO_HIGHEST: O << "%highest(("; break;
627 case MipsII::MO_TLSGD: O << "%tlsgd("; break;
628 case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
629 case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
630 case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
631 case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
632 case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
633 case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
634 case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
635 case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
636 }
637
638 switch (MO.getType()) {
639 case MachineOperand::MO_Register:
640 O << '$'
641 << StringRef(MipsInstPrinter::getRegisterName(Reg: MO.getReg())).lower();
642 break;
643
644 case MachineOperand::MO_Immediate:
645 O << MO.getImm();
646 break;
647
648 case MachineOperand::MO_MachineBasicBlock:
649 MO.getMBB()->getSymbol()->print(OS&: O, MAI);
650 return;
651
652 case MachineOperand::MO_GlobalAddress:
653 PrintSymbolOperand(MO, OS&: O);
654 break;
655
656 case MachineOperand::MO_BlockAddress: {
657 MCSymbol *BA = GetBlockAddressSymbol(BA: MO.getBlockAddress());
658 O << BA->getName();
659 break;
660 }
661
662 case MachineOperand::MO_ConstantPoolIndex:
663 O << getDataLayout().getPrivateGlobalPrefix() << "CPI"
664 << getFunctionNumber() << "_" << MO.getIndex();
665 if (MO.getOffset())
666 O << "+" << MO.getOffset();
667 break;
668
669 default:
670 llvm_unreachable("<unknown operand type>");
671 }
672
673 if (closeP) O << ")";
674}
675
676void MipsAsmPrinter::
677printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
678 // Load/Store memory operands -- imm($reg)
679 // If PIC target the target is loaded as the
680 // pattern lw $25,%call16($28)
681
682 // opNum can be invalid if instruction has reglist as operand.
683 // MemOperand is always last operand of instruction (base + offset).
684 switch (MI->getOpcode()) {
685 default:
686 break;
687 case Mips::SWM32_MM:
688 case Mips::LWM32_MM:
689 opNum = MI->getNumOperands() - 2;
690 break;
691 }
692
693 printOperand(MI, opNum: opNum+1, O);
694 O << "(";
695 printOperand(MI, opNum, O);
696 O << ")";
697}
698
699void MipsAsmPrinter::
700printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
701 // when using stack locations for not load/store instructions
702 // print the same way as all normal 3 operand instructions.
703 printOperand(MI, opNum, O);
704 O << ", ";
705 printOperand(MI, opNum: opNum+1, O);
706}
707
708void MipsAsmPrinter::printFCCOperand(const MachineInstr *MI, int opNum,
709 raw_ostream &O) {
710 const MachineOperand &MO = MI->getOperand(i: opNum);
711 O << Mips::MipsFCCToString(CC: (Mips::CondCode)MO.getImm());
712}
713
714void MipsAsmPrinter::
715printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O) {
716 for (int i = opNum, e = MI->getNumOperands(); i != e; ++i) {
717 if (i != opNum) O << ", ";
718 printOperand(MI, opNum: i, O);
719 }
720}
721
722void MipsAsmPrinter::emitStartOfAsmFile(Module &M) {
723 const Triple &TT = TM.getTargetTriple();
724
725 if (TT.isOSBinFormatELF()) {
726 MipsTargetStreamer &TS = getTargetStreamer();
727
728 // MipsTargetStreamer has an initialization order problem when emitting an
729 // object file directly (see MipsTargetELFStreamer for full details). Work
730 // around it by re-initializing the PIC state here.
731 TS.setPic(OutContext.getObjectFileInfo()->isPositionIndependent());
732
733 // Try to get target-features from the first function.
734 StringRef FS = TM.getTargetFeatureString();
735 Module::iterator F = M.begin();
736 if (FS.empty() && M.size() && F->hasFnAttribute(Kind: "target-features"))
737 FS = F->getFnAttribute(Kind: "target-features").getValueAsString();
738
739 std::string strFS = FS.str();
740 if (M.size() && F->getFnAttribute(Kind: "use-soft-float").getValueAsBool())
741 strFS += strFS.empty() ? "+soft-float" : ",+soft-float";
742
743 // Compute MIPS architecture attributes based on the default subtarget
744 // that we'd have constructed.
745 // FIXME: For ifunc related functions we could iterate over and look
746 // for a feature string that doesn't match the default one.
747 StringRef CPU = MIPS_MC::selectMipsCPU(TT, CPU: TM.getTargetCPU());
748 const MipsTargetMachine &MTM = static_cast<const MipsTargetMachine &>(TM);
749 const MipsSubtarget STI(TT, CPU, StringRef(strFS), MTM.isLittleEndian(),
750 MTM, std::nullopt);
751
752 bool IsABICalls = STI.isABICalls();
753 const MipsABIInfo &ABI = MTM.getABI();
754 if (IsABICalls) {
755 TS.emitDirectiveAbiCalls();
756 // FIXME: This condition should be a lot more complicated that it is here.
757 // Ideally it should test for properties of the ABI and not the ABI
758 // itself.
759 // For the moment, I'm only correcting enough to make MIPS-IV work.
760 if (!isPositionIndependent() && STI.hasSym32())
761 TS.emitDirectiveOptionPic0();
762 }
763
764 // Tell the assembler which ABI we are using
765 std::string SectionName = std::string(".mdebug.") + getCurrentABIString();
766 OutStreamer->switchSection(
767 Section: OutContext.getELFSection(Section: SectionName, Type: ELF::SHT_PROGBITS, Flags: 0));
768
769 // NaN: At the moment we only support:
770 // 1. .nan legacy (default)
771 // 2. .nan 2008
772 STI.isNaN2008() ? TS.emitDirectiveNaN2008() : TS.emitDirectiveNaNLegacy();
773
774 // TODO: handle O64 ABI
775
776 TS.updateABIInfo(P: STI);
777
778 // We should always emit a '.module fp=...' but binutils 2.24 does not
779 // accept it. We therefore emit it when it contradicts the ABI defaults
780 // (-mfpxx or -mfp64) and omit it otherwise.
781 if ((ABI.IsO32() && (STI.isABI_FPXX() || STI.isFP64bit())) ||
782 STI.useSoftFloat())
783 TS.emitDirectiveModuleFP();
784
785 // We should always emit a '.module [no]oddspreg' but binutils 2.24 does not
786 // accept it. We therefore emit it when it contradicts the default or an
787 // option has changed the default (i.e. FPXX) and omit it otherwise.
788 if (ABI.IsO32() && (!STI.useOddSPReg() || STI.isABI_FPXX()))
789 TS.emitDirectiveModuleOddSPReg();
790
791 // Switch to the .text section.
792 OutStreamer->switchSection(Section: getObjFileLowering().getTextSection());
793 }
794}
795
796void MipsAsmPrinter::emitInlineAsmStart() const {
797 MipsTargetStreamer &TS = getTargetStreamer();
798
799 // GCC's choice of assembler options for inline assembly code ('at', 'macro'
800 // and 'reorder') is different from LLVM's choice for generated code ('noat',
801 // 'nomacro' and 'noreorder').
802 // In order to maintain compatibility with inline assembly code which depends
803 // on GCC's assembler options being used, we have to switch to those options
804 // for the duration of the inline assembly block and then switch back.
805 TS.emitDirectiveSetPush();
806 TS.emitDirectiveSetAt();
807 TS.emitDirectiveSetMacro();
808 TS.emitDirectiveSetReorder();
809 OutStreamer->addBlankLine();
810}
811
812void MipsAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
813 const MCSubtargetInfo *EndInfo,
814 const MachineInstr *MI) {
815 OutStreamer->addBlankLine();
816 getTargetStreamer().emitDirectiveSetPop();
817}
818
819void MipsAsmPrinter::emitJumpTableEntry(const MachineJumpTableInfo &MJTI,
820 const MachineBasicBlock *MBB,
821 unsigned uid) const {
822 MCSymbol *MBBSym = MBB->getSymbol();
823 switch (MJTI.getEntryKind()) {
824 case MachineJumpTableInfo::EK_BlockAddress:
825 OutStreamer->emitValue(Value: MCSymbolRefExpr::create(Symbol: MBBSym, Ctx&: OutContext),
826 Size: getDataLayout().getPointerSize());
827 break;
828 case MachineJumpTableInfo::EK_GPRel32BlockAddress:
829 // Each entry is a GP-relative value targeting the block symbol.
830 getTargetStreamer().emitGPRel32Value(
831 MCSymbolRefExpr::create(Symbol: MBBSym, Ctx&: OutContext));
832 break;
833 case MachineJumpTableInfo::EK_GPRel64BlockAddress:
834 getTargetStreamer().emitGPRel64Value(
835 MCSymbolRefExpr::create(Symbol: MBBSym, Ctx&: OutContext));
836 break;
837 default:
838 llvm_unreachable("");
839 }
840}
841
842void MipsAsmPrinter::EmitJal(const MCSubtargetInfo &STI, MCSymbol *Symbol) {
843 MCInst I;
844 I.setOpcode(Mips::JAL);
845 I.addOperand(
846 Op: MCOperand::createExpr(Val: MCSymbolRefExpr::create(Symbol, Ctx&: OutContext)));
847 OutStreamer->emitInstruction(Inst: I, STI);
848}
849
850void MipsAsmPrinter::EmitInstrReg(const MCSubtargetInfo &STI, unsigned Opcode,
851 unsigned Reg) {
852 MCInst I;
853 I.setOpcode(Opcode);
854 I.addOperand(Op: MCOperand::createReg(Reg));
855 OutStreamer->emitInstruction(Inst: I, STI);
856}
857
858void MipsAsmPrinter::EmitInstrRegReg(const MCSubtargetInfo &STI,
859 unsigned Opcode, unsigned Reg1,
860 unsigned Reg2) {
861 MCInst I;
862 //
863 // Because of the current td files for Mips32, the operands for MTC1
864 // appear backwards from their normal assembly order. It's not a trivial
865 // change to fix this in the td file so we adjust for it here.
866 //
867 if (Opcode == Mips::MTC1) {
868 unsigned Temp = Reg1;
869 Reg1 = Reg2;
870 Reg2 = Temp;
871 }
872 I.setOpcode(Opcode);
873 I.addOperand(Op: MCOperand::createReg(Reg: Reg1));
874 I.addOperand(Op: MCOperand::createReg(Reg: Reg2));
875 OutStreamer->emitInstruction(Inst: I, STI);
876}
877
878void MipsAsmPrinter::EmitInstrRegRegReg(const MCSubtargetInfo &STI,
879 unsigned Opcode, unsigned Reg1,
880 unsigned Reg2, unsigned Reg3) {
881 MCInst I;
882 I.setOpcode(Opcode);
883 I.addOperand(Op: MCOperand::createReg(Reg: Reg1));
884 I.addOperand(Op: MCOperand::createReg(Reg: Reg2));
885 I.addOperand(Op: MCOperand::createReg(Reg: Reg3));
886 OutStreamer->emitInstruction(Inst: I, STI);
887}
888
889void MipsAsmPrinter::EmitMovFPIntPair(const MCSubtargetInfo &STI,
890 unsigned MovOpc, unsigned Reg1,
891 unsigned Reg2, unsigned FPReg1,
892 unsigned FPReg2, bool LE) {
893 if (!LE) {
894 unsigned temp = Reg1;
895 Reg1 = Reg2;
896 Reg2 = temp;
897 }
898 EmitInstrRegReg(STI, Opcode: MovOpc, Reg1, Reg2: FPReg1);
899 EmitInstrRegReg(STI, Opcode: MovOpc, Reg1: Reg2, Reg2: FPReg2);
900}
901
902void MipsAsmPrinter::EmitSwapFPIntParams(const MCSubtargetInfo &STI,
903 Mips16HardFloatInfo::FPParamVariant PV,
904 bool LE, bool ToFP) {
905 using namespace Mips16HardFloatInfo;
906
907 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1;
908 switch (PV) {
909 case FSig:
910 EmitInstrRegReg(STI, Opcode: MovOpc, Reg1: Mips::A0, Reg2: Mips::F12);
911 break;
912 case FFSig:
913 EmitMovFPIntPair(STI, MovOpc, Reg1: Mips::A0, Reg2: Mips::A1, FPReg1: Mips::F12, FPReg2: Mips::F14, LE);
914 break;
915 case FDSig:
916 EmitInstrRegReg(STI, Opcode: MovOpc, Reg1: Mips::A0, Reg2: Mips::F12);
917 EmitMovFPIntPair(STI, MovOpc, Reg1: Mips::A2, Reg2: Mips::A3, FPReg1: Mips::F14, FPReg2: Mips::F15, LE);
918 break;
919 case DSig:
920 EmitMovFPIntPair(STI, MovOpc, Reg1: Mips::A0, Reg2: Mips::A1, FPReg1: Mips::F12, FPReg2: Mips::F13, LE);
921 break;
922 case DDSig:
923 EmitMovFPIntPair(STI, MovOpc, Reg1: Mips::A0, Reg2: Mips::A1, FPReg1: Mips::F12, FPReg2: Mips::F13, LE);
924 EmitMovFPIntPair(STI, MovOpc, Reg1: Mips::A2, Reg2: Mips::A3, FPReg1: Mips::F14, FPReg2: Mips::F15, LE);
925 break;
926 case DFSig:
927 EmitMovFPIntPair(STI, MovOpc, Reg1: Mips::A0, Reg2: Mips::A1, FPReg1: Mips::F12, FPReg2: Mips::F13, LE);
928 EmitInstrRegReg(STI, Opcode: MovOpc, Reg1: Mips::A2, Reg2: Mips::F14);
929 break;
930 case NoSig:
931 return;
932 }
933}
934
935void MipsAsmPrinter::EmitSwapFPIntRetval(
936 const MCSubtargetInfo &STI, Mips16HardFloatInfo::FPReturnVariant RV,
937 bool LE) {
938 using namespace Mips16HardFloatInfo;
939
940 unsigned MovOpc = Mips::MFC1;
941 switch (RV) {
942 case FRet:
943 EmitInstrRegReg(STI, Opcode: MovOpc, Reg1: Mips::V0, Reg2: Mips::F0);
944 break;
945 case DRet:
946 EmitMovFPIntPair(STI, MovOpc, Reg1: Mips::V0, Reg2: Mips::V1, FPReg1: Mips::F0, FPReg2: Mips::F1, LE);
947 break;
948 case CFRet:
949 EmitMovFPIntPair(STI, MovOpc, Reg1: Mips::V0, Reg2: Mips::V1, FPReg1: Mips::F0, FPReg2: Mips::F1, LE);
950 break;
951 case CDRet:
952 EmitMovFPIntPair(STI, MovOpc, Reg1: Mips::V0, Reg2: Mips::V1, FPReg1: Mips::F0, FPReg2: Mips::F1, LE);
953 EmitMovFPIntPair(STI, MovOpc, Reg1: Mips::A0, Reg2: Mips::A1, FPReg1: Mips::F2, FPReg2: Mips::F3, LE);
954 break;
955 case NoFPRet:
956 break;
957 }
958}
959
960void MipsAsmPrinter::EmitFPCallStub(
961 const char *Symbol, const Mips16HardFloatInfo::FuncSignature *Signature) {
962 using namespace Mips16HardFloatInfo;
963
964 MCSymbol *MSymbol = OutContext.getOrCreateSymbol(Name: StringRef(Symbol));
965 bool LE = getDataLayout().isLittleEndian();
966 // Construct a local MCSubtargetInfo here.
967 // This is because the MachineFunction won't exist (but have not yet been
968 // freed) and since we're at the global level we can use the default
969 // constructed subtarget.
970 std::unique_ptr<MCSubtargetInfo> STI(TM.getTarget().createMCSubtargetInfo(
971 TheTriple: TM.getTargetTriple(), CPU: TM.getTargetCPU(), Features: TM.getTargetFeatureString()));
972
973 //
974 // .global xxxx
975 //
976 OutStreamer->emitSymbolAttribute(Symbol: MSymbol, Attribute: MCSA_Global);
977 const char *RetType;
978 //
979 // make the comment field identifying the return and parameter
980 // types of the floating point stub
981 // # Stub function to call rettype xxxx (params)
982 //
983 switch (Signature->RetSig) {
984 case FRet:
985 RetType = "float";
986 break;
987 case DRet:
988 RetType = "double";
989 break;
990 case CFRet:
991 RetType = "complex";
992 break;
993 case CDRet:
994 RetType = "double complex";
995 break;
996 case NoFPRet:
997 RetType = "";
998 break;
999 }
1000 const char *Parms;
1001 switch (Signature->ParamSig) {
1002 case FSig:
1003 Parms = "float";
1004 break;
1005 case FFSig:
1006 Parms = "float, float";
1007 break;
1008 case FDSig:
1009 Parms = "float, double";
1010 break;
1011 case DSig:
1012 Parms = "double";
1013 break;
1014 case DDSig:
1015 Parms = "double, double";
1016 break;
1017 case DFSig:
1018 Parms = "double, float";
1019 break;
1020 case NoSig:
1021 Parms = "";
1022 break;
1023 }
1024 OutStreamer->AddComment(T: "\t# Stub function to call " + Twine(RetType) + " " +
1025 Twine(Symbol) + " (" + Twine(Parms) + ")");
1026 //
1027 // probably not necessary but we save and restore the current section state
1028 //
1029 OutStreamer->pushSection();
1030 //
1031 // .section mips16.call.fpxxxx,"ax",@progbits
1032 //
1033 MCSectionELF *M = OutContext.getELFSection(
1034 Section: ".mips16.call.fp." + std::string(Symbol), Type: ELF::SHT_PROGBITS,
1035 Flags: ELF::SHF_ALLOC | ELF::SHF_EXECINSTR);
1036 OutStreamer->switchSection(Section: M);
1037 //
1038 // .align 2
1039 //
1040 OutStreamer->emitValueToAlignment(Alignment: Align(4));
1041 MipsTargetStreamer &TS = getTargetStreamer();
1042 //
1043 // .set nomips16
1044 // .set nomicromips
1045 //
1046 TS.emitDirectiveSetNoMips16();
1047 TS.emitDirectiveSetNoMicroMips();
1048 //
1049 // .ent __call_stub_fp_xxxx
1050 // .type __call_stub_fp_xxxx,@function
1051 // __call_stub_fp_xxxx:
1052 //
1053 std::string x = "__call_stub_fp_" + std::string(Symbol);
1054 MCSymbol *Stub = OutContext.getOrCreateSymbol(Name: StringRef(x));
1055 TS.emitDirectiveEnt(Symbol: *Stub);
1056 MCSymbol *MType =
1057 OutContext.getOrCreateSymbol(Name: "__call_stub_fp_" + Twine(Symbol));
1058 OutStreamer->emitSymbolAttribute(Symbol: MType, Attribute: MCSA_ELF_TypeFunction);
1059 OutStreamer->emitLabel(Symbol: Stub);
1060
1061 // Only handle non-pic for now.
1062 assert(!isPositionIndependent() &&
1063 "should not be here if we are compiling pic");
1064 TS.emitDirectiveSetReorder();
1065 //
1066 // We need to add a MipsMCExpr class to MCTargetDesc to fully implement
1067 // stubs without raw text but this current patch is for compiler generated
1068 // functions and they all return some value.
1069 // The calling sequence for non pic is different in that case and we need
1070 // to implement %lo and %hi in order to handle the case of no return value
1071 // See the corresponding method in Mips16HardFloat for details.
1072 //
1073 // mov the return address to S2.
1074 // we have no stack space to store it and we are about to make another call.
1075 // We need to make sure that the enclosing function knows to save S2
1076 // This should have already been handled.
1077 //
1078 // Mov $18, $31
1079
1080 EmitInstrRegRegReg(STI: *STI, Opcode: Mips::OR, Reg1: Mips::S2, Reg2: Mips::RA, Reg3: Mips::ZERO);
1081
1082 EmitSwapFPIntParams(STI: *STI, PV: Signature->ParamSig, LE, ToFP: true);
1083
1084 // Jal xxxx
1085 //
1086 EmitJal(STI: *STI, Symbol: MSymbol);
1087
1088 // fix return values
1089 EmitSwapFPIntRetval(STI: *STI, RV: Signature->RetSig, LE);
1090 //
1091 // do the return
1092 // if (Signature->RetSig == NoFPRet)
1093 // llvm_unreachable("should not be any stubs here with no return value");
1094 // else
1095 EmitInstrReg(STI: *STI, Opcode: Mips::JR, Reg: Mips::S2);
1096
1097 MCSymbol *Tmp = OutContext.createTempSymbol();
1098 OutStreamer->emitLabel(Symbol: Tmp);
1099 const MCSymbolRefExpr *E = MCSymbolRefExpr::create(Symbol: Stub, Ctx&: OutContext);
1100 const MCSymbolRefExpr *T = MCSymbolRefExpr::create(Symbol: Tmp, Ctx&: OutContext);
1101 const MCExpr *T_min_E = MCBinaryExpr::createSub(LHS: T, RHS: E, Ctx&: OutContext);
1102 OutStreamer->emitELFSize(Symbol: Stub, Value: T_min_E);
1103 TS.emitDirectiveEnd(Name: x);
1104 OutStreamer->popSection();
1105}
1106
1107void MipsAsmPrinter::emitEndOfAsmFile(Module &M) {
1108 // Emit needed stubs
1109 //
1110 for (std::map<
1111 const char *,
1112 const Mips16HardFloatInfo::FuncSignature *>::const_iterator
1113 it = StubsNeeded.begin();
1114 it != StubsNeeded.end(); ++it) {
1115 const char *Symbol = it->first;
1116 const Mips16HardFloatInfo::FuncSignature *Signature = it->second;
1117 EmitFPCallStub(Symbol, Signature);
1118 }
1119 // return to the text section
1120 OutStreamer->switchSection(Section: OutContext.getObjectFileInfo()->getTextSection());
1121}
1122
1123void MipsAsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind) {
1124 const uint8_t NoopsInSledCount = Subtarget->isGP64bit() ? 15 : 11;
1125 // For mips32 we want to emit the following pattern:
1126 //
1127 // .Lxray_sled_N:
1128 // ALIGN
1129 // B .tmpN
1130 // 11 NOP instructions (44 bytes)
1131 // ADDIU T9, T9, 52
1132 // .tmpN
1133 //
1134 // We need the 44 bytes (11 instructions) because at runtime, we'd
1135 // be patching over the full 48 bytes (12 instructions) with the following
1136 // pattern:
1137 //
1138 // ADDIU SP, SP, -8
1139 // NOP
1140 // SW RA, 4(SP)
1141 // SW T9, 0(SP)
1142 // LUI T9, %hi(__xray_FunctionEntry/Exit)
1143 // ORI T9, T9, %lo(__xray_FunctionEntry/Exit)
1144 // LUI T0, %hi(function_id)
1145 // JALR T9
1146 // ORI T0, T0, %lo(function_id)
1147 // LW T9, 0(SP)
1148 // LW RA, 4(SP)
1149 // ADDIU SP, SP, 8
1150 //
1151 // We add 52 bytes to t9 because we want to adjust the function pointer to
1152 // the actual start of function i.e. the address just after the noop sled.
1153 // We do this because gp displacement relocation is emitted at the start of
1154 // of the function i.e after the nop sled and to correctly calculate the
1155 // global offset table address, t9 must hold the address of the instruction
1156 // containing the gp displacement relocation.
1157 // FIXME: Is this correct for the static relocation model?
1158 //
1159 // For mips64 we want to emit the following pattern:
1160 //
1161 // .Lxray_sled_N:
1162 // ALIGN
1163 // B .tmpN
1164 // 15 NOP instructions (60 bytes)
1165 // .tmpN
1166 //
1167 // We need the 60 bytes (15 instructions) because at runtime, we'd
1168 // be patching over the full 64 bytes (16 instructions) with the following
1169 // pattern:
1170 //
1171 // DADDIU SP, SP, -16
1172 // NOP
1173 // SD RA, 8(SP)
1174 // SD T9, 0(SP)
1175 // LUI T9, %highest(__xray_FunctionEntry/Exit)
1176 // ORI T9, T9, %higher(__xray_FunctionEntry/Exit)
1177 // DSLL T9, T9, 16
1178 // ORI T9, T9, %hi(__xray_FunctionEntry/Exit)
1179 // DSLL T9, T9, 16
1180 // ORI T9, T9, %lo(__xray_FunctionEntry/Exit)
1181 // LUI T0, %hi(function_id)
1182 // JALR T9
1183 // ADDIU T0, T0, %lo(function_id)
1184 // LD T9, 0(SP)
1185 // LD RA, 8(SP)
1186 // DADDIU SP, SP, 16
1187 //
1188 OutStreamer->emitCodeAlignment(Alignment: Align(4), STI: &getSubtargetInfo());
1189 auto CurSled = OutContext.createTempSymbol(Name: "xray_sled_", AlwaysAddSuffix: true);
1190 OutStreamer->emitLabel(Symbol: CurSled);
1191 auto Target = OutContext.createTempSymbol();
1192
1193 // Emit "B .tmpN" instruction, which jumps over the nop sled to the actual
1194 // start of function
1195 const MCExpr *TargetExpr = MCSymbolRefExpr::create(Symbol: Target, Ctx&: OutContext);
1196 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(Mips::BEQ)
1197 .addReg(Reg: Mips::ZERO)
1198 .addReg(Reg: Mips::ZERO)
1199 .addExpr(Val: TargetExpr));
1200
1201 for (int8_t I = 0; I < NoopsInSledCount; I++)
1202 EmitToStreamer(S&: *OutStreamer, Inst: MCInstBuilder(Mips::SLL)
1203 .addReg(Reg: Mips::ZERO)
1204 .addReg(Reg: Mips::ZERO)
1205 .addImm(Val: 0));
1206
1207 OutStreamer->emitLabel(Symbol: Target);
1208
1209 if (!Subtarget->isGP64bit()) {
1210 EmitToStreamer(S&: *OutStreamer,
1211 Inst: MCInstBuilder(Mips::ADDiu)
1212 .addReg(Reg: Mips::T9)
1213 .addReg(Reg: Mips::T9)
1214 .addImm(Val: 0x34));
1215 }
1216
1217 recordSled(Sled: CurSled, MI, Kind, Version: 2);
1218}
1219
1220void MipsAsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI) {
1221 EmitSled(MI, Kind: SledKind::FUNCTION_ENTER);
1222}
1223
1224void MipsAsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI) {
1225 EmitSled(MI, Kind: SledKind::FUNCTION_EXIT);
1226}
1227
1228void MipsAsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI) {
1229 EmitSled(MI, Kind: SledKind::TAIL_CALL);
1230}
1231
1232void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
1233 raw_ostream &OS) {
1234 // TODO: implement
1235}
1236
1237// Emit .dtprelword or .dtpreldword directive
1238// and value for debug thread local expression.
1239void MipsAsmPrinter::emitDebugValue(const MCExpr *Value, unsigned Size) const {
1240 if (auto *MipsExpr = dyn_cast<MCSpecifierExpr>(Val: Value)) {
1241 if (MipsExpr && MipsExpr->getSpecifier() == Mips::S_DTPREL) {
1242 switch (Size) {
1243 case 4:
1244 getTargetStreamer().emitDTPRel32Value(MipsExpr->getSubExpr());
1245 break;
1246 case 8:
1247 getTargetStreamer().emitDTPRel64Value(MipsExpr->getSubExpr());
1248 break;
1249 default:
1250 llvm_unreachable("Unexpected size of expression value.");
1251 }
1252 return;
1253 }
1254 }
1255 AsmPrinter::emitDebugValue(Value, Size);
1256}
1257
1258bool MipsAsmPrinter::isLongBranchPseudo(int Opcode) const {
1259 return (Opcode == Mips::LONG_BRANCH_LUi
1260 || Opcode == Mips::LONG_BRANCH_LUi2Op
1261 || Opcode == Mips::LONG_BRANCH_LUi2Op_64
1262 || Opcode == Mips::LONG_BRANCH_ADDiu
1263 || Opcode == Mips::LONG_BRANCH_ADDiu2Op
1264 || Opcode == Mips::LONG_BRANCH_DADDiu
1265 || Opcode == Mips::LONG_BRANCH_DADDiu2Op);
1266}
1267
1268char MipsAsmPrinter::ID = 0;
1269
1270INITIALIZE_PASS(MipsAsmPrinter, "mips-asm-printer", "Mips Assembly Printer",
1271 false, false)
1272
1273// Force static initialization.
1274extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
1275LLVMInitializeMipsAsmPrinter() {
1276 RegisterAsmPrinter<MipsAsmPrinter> X(getTheMipsTarget());
1277 RegisterAsmPrinter<MipsAsmPrinter> Y(getTheMipselTarget());
1278 RegisterAsmPrinter<MipsAsmPrinter> A(getTheMips64Target());
1279 RegisterAsmPrinter<MipsAsmPrinter> B(getTheMips64elTarget());
1280}
1281