1//===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the Mips specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MipsSubtarget.h"
14#include "Mips.h"
15#include "MipsCallLowering.h"
16#include "MipsLegalizerInfo.h"
17#include "MipsRegisterBankInfo.h"
18#include "MipsRegisterInfo.h"
19#include "MipsSelectionDAGInfo.h"
20#include "MipsTargetMachine.h"
21#include "llvm/IR/Attributes.h"
22#include "llvm/IR/Function.h"
23#include "llvm/MC/TargetRegistry.h"
24#include "llvm/Support/CommandLine.h"
25#include "llvm/Support/Debug.h"
26#include "llvm/Support/raw_ostream.h"
27
28using namespace llvm;
29
30cl::opt<CompactBranchPolicy> MipsCompactBranchPolicy(
31 "mips-compact-branches", cl::Optional, cl::init(Val: CB_Optimal),
32 cl::desc("MIPS Specific: Compact branch policy."),
33 cl::values(clEnumValN(CB_Never, "never",
34 "Do not use compact branches if possible."),
35 clEnumValN(CB_Optimal, "optimal",
36 "Use compact branches where appropriate (default)."),
37 clEnumValN(CB_Always, "always",
38 "Always use compact branches if possible.")));
39
40#define DEBUG_TYPE "mips-subtarget"
41
42#define GET_SUBTARGETINFO_TARGET_DESC
43#define GET_SUBTARGETINFO_CTOR
44#include "MipsGenSubtargetInfo.inc"
45
46// FIXME: Maybe this should be on by default when Mips16 is specified
47//
48static cl::opt<bool>
49 Mixed16_32("mips-mixed-16-32", cl::init(Val: false),
50 cl::desc("Allow for a mixture of Mips16 "
51 "and Mips32 code in a single output file"),
52 cl::Hidden);
53
54static cl::opt<bool> Mips_Os16("mips-os16", cl::init(Val: false),
55 cl::desc("Compile all functions that don't use "
56 "floating point as Mips 16"),
57 cl::Hidden);
58
59static cl::opt<bool> Mips16HardFloat("mips16-hard-float", cl::NotHidden,
60 cl::desc("Enable mips16 hard float."),
61 cl::init(Val: false));
62
63static cl::opt<bool>
64 Mips16ConstantIslands("mips16-constant-islands", cl::NotHidden,
65 cl::desc("Enable mips16 constant islands."),
66 cl::init(Val: true));
67
68static cl::opt<bool>
69 GPOpt("mgpopt", cl::Hidden,
70 cl::desc("Enable gp-relative addressing of mips small data items"));
71
72bool MipsSubtarget::DspWarningPrinted = false;
73bool MipsSubtarget::MSAWarningPrinted = false;
74bool MipsSubtarget::VirtWarningPrinted = false;
75bool MipsSubtarget::CRCWarningPrinted = false;
76bool MipsSubtarget::GINVWarningPrinted = false;
77
78void MipsSubtarget::anchor() {}
79
80MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
81 bool little, const MipsTargetMachine &TM,
82 MaybeAlign StackAlignOverride)
83 : MipsGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
84 MipsArchVersion(MipsDefault), IsLittle(little), IsSoftFloat(false),
85 IsSingleFloat(false), IsFPXX(false), NoABICalls(false), Abs2008(false),
86 IsFP64bit(false), UseOddSPReg(true), IsNaN2008bit(false),
87 IsGP64bit(false), HasVFPU(false), HasCnMips(false), HasCnMipsP(false),
88 IsR5900(false), FixR5900(false), HasMips3_32(false), HasMips3_32r2(false),
89 HasMips4_32(false), HasMips4_32r2(false), HasMips5_32r2(false),
90 InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
91 InMicroMipsMode(false), HasDSP(false), HasDSPR2(false), HasDSPR3(false),
92 AllowMixed16_32(Mixed16_32 || Mips_Os16), Os16(Mips_Os16), HasMSA(false),
93 UseTCCInDIV(false), HasSym32(false), HasEVA(false), DisableMadd4(false),
94 HasMT(false), HasCRC(false), HasVirt(false), HasGINV(false),
95 UseIndirectJumpsHazard(false), StrictAlign(false),
96 UseCompactBranches(MipsCompactBranchPolicy != CB_Never),
97 StackAlignOverride(StackAlignOverride), TM(TM), TargetTriple(TT),
98 InstrInfo(
99 MipsInstrInfo::create(STI&: initializeSubtargetDependencies(CPU, FS, TM))),
100 FrameLowering(MipsFrameLowering::create(ST: *this)),
101 TLInfo(MipsTargetLowering::create(TM, STI: *this)) {
102
103 if (MipsArchVersion == MipsDefault)
104 MipsArchVersion = Mips32;
105
106 // Don't even attempt to generate code for MIPS-V. It has not
107 // been tested and currently exists for the integrated assembler only.
108 if (MipsArchVersion == Mips5)
109 report_fatal_error(reason: "Code generation for MIPS-V is not implemented", gen_crash_diag: false);
110
111 // Check if Architecture and ABI are compatible.
112 assert(((!isGP64bit() && isABI_O32()) || isGP64bit()) &&
113 "Invalid Arch & ABI pair.");
114
115 if (hasMSA() && !isFP64bit())
116 report_fatal_error(reason: "MSA requires a 64-bit FPU register file (FR=1 mode). "
117 "See -mattr=+fp64.",
118 gen_crash_diag: false);
119
120 if (isFP64bit() && !hasMips64() && hasMips32() && !hasMips32r2())
121 report_fatal_error(
122 reason: "FPU with 64-bit registers is not available on MIPS32 pre revision 2. "
123 "Use -mcpu=mips32r2 or greater.", gen_crash_diag: false);
124
125 if (!isABI_O32() && !useOddSPReg())
126 report_fatal_error(reason: "-mattr=+nooddspreg requires the O32 ABI.", gen_crash_diag: false);
127
128 if (IsFPXX && (isABI_N32() || isABI_N64()))
129 report_fatal_error(reason: "FPXX is not permitted for the N32/N64 ABI's.", gen_crash_diag: false);
130
131 if (hasMips64r6() && InMicroMipsMode)
132 report_fatal_error(reason: "microMIPS64R6 is not supported", gen_crash_diag: false);
133
134 if (!isABI_O32() && InMicroMipsMode)
135 report_fatal_error(reason: "microMIPS64 is not supported.", gen_crash_diag: false);
136
137 if (UseIndirectJumpsHazard) {
138 if (InMicroMipsMode)
139 report_fatal_error(
140 reason: "cannot combine indirect jumps with hazard barriers and microMIPS");
141 if (!hasMips32r2())
142 report_fatal_error(
143 reason: "indirect jumps with hazard barriers requires MIPS32R2 or later");
144 }
145 if (inAbs2008Mode() && hasMips32() && !hasMips32r2()) {
146 report_fatal_error(reason: "IEEE 754-2008 abs.fmt is not supported for the given "
147 "architecture.",
148 gen_crash_diag: false);
149 }
150
151 if (hasMips32r6()) {
152 StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
153
154 assert(isFP64bit());
155 assert(isNaN2008());
156 assert(inAbs2008Mode());
157 if (hasDSP())
158 report_fatal_error(reason: ISA + " is not compatible with the DSP ASE", gen_crash_diag: false);
159 }
160
161 if (NoABICalls && TM.isPositionIndependent())
162 report_fatal_error(reason: "position-independent code requires '-mabicalls'");
163
164 if (isABI_N64() && !TM.isPositionIndependent() && !hasSym32())
165 NoABICalls = true;
166
167 // Set UseSmallSection.
168 UseSmallSection = GPOpt;
169 if (!NoABICalls && GPOpt) {
170 errs() << "warning: cannot use small-data accesses for '-mabicalls'"
171 << "\n";
172 UseSmallSection = false;
173 }
174
175 if (hasDSPR2() && !DspWarningPrinted) {
176 if (hasMips64() && !hasMips64r2()) {
177 errs() << "warning: the 'dspr2' ASE requires MIPS64 revision 2 or "
178 << "greater\n";
179 DspWarningPrinted = true;
180 } else if (hasMips32() && !hasMips32r2()) {
181 errs() << "warning: the 'dspr2' ASE requires MIPS32 revision 2 or "
182 << "greater\n";
183 DspWarningPrinted = true;
184 }
185 } else if (hasDSP() && !DspWarningPrinted) {
186 if (hasMips64() && !hasMips64r2()) {
187 errs() << "warning: the 'dsp' ASE requires MIPS64 revision 2 or "
188 << "greater\n";
189 DspWarningPrinted = true;
190 } else if (hasMips32() && !hasMips32r2()) {
191 errs() << "warning: the 'dsp' ASE requires MIPS32 revision 2 or "
192 << "greater\n";
193 DspWarningPrinted = true;
194 }
195 }
196
197 StringRef ArchName = hasMips64() ? "MIPS64" : "MIPS32";
198
199 if (!hasMips32r5() && hasMSA() && !MSAWarningPrinted) {
200 errs() << "warning: the 'msa' ASE requires " << ArchName
201 << " revision 5 or greater\n";
202 MSAWarningPrinted = true;
203 }
204 if (!hasMips32r5() && hasVirt() && !VirtWarningPrinted) {
205 errs() << "warning: the 'virt' ASE requires " << ArchName
206 << " revision 5 or greater\n";
207 VirtWarningPrinted = true;
208 }
209 if (!hasMips32r6() && hasCRC() && !CRCWarningPrinted) {
210 errs() << "warning: the 'crc' ASE requires " << ArchName
211 << " revision 6 or greater\n";
212 CRCWarningPrinted = true;
213 }
214 if (!hasMips32r6() && hasGINV() && !GINVWarningPrinted) {
215 errs() << "warning: the 'ginv' ASE requires " << ArchName
216 << " revision 6 or greater\n";
217 GINVWarningPrinted = true;
218 }
219
220 TSInfo = std::make_unique<MipsSelectionDAGInfo>();
221
222 CallLoweringInfo.reset(p: new MipsCallLowering(*getTargetLowering()));
223 Legalizer.reset(p: new MipsLegalizerInfo(*this));
224
225 auto *RBI = new MipsRegisterBankInfo(*getRegisterInfo());
226 RegBankInfo.reset(p: RBI);
227 InstSelector.reset(p: createMipsInstructionSelector(TM, *this, *RBI));
228}
229
230MipsSubtarget::~MipsSubtarget() = default;
231
232bool MipsSubtarget::isPositionIndependent() const {
233 return TM.isPositionIndependent();
234}
235
236/// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
237bool MipsSubtarget::enablePostRAScheduler() const { return true; }
238
239void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
240 CriticalPathRCs.clear();
241 CriticalPathRCs.push_back(Elt: isGP64bit() ? &Mips::GPR64RegClass
242 : &Mips::GPR32RegClass);
243}
244
245CodeGenOptLevel MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
246 return CodeGenOptLevel::Aggressive;
247}
248
249MipsSubtarget &
250MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
251 const TargetMachine &TM) {
252 StringRef CPUName = MIPS_MC::selectMipsCPU(TT: TM.getTargetTriple(), CPU);
253
254 // Parse features string.
255 ParseSubtargetFeatures(CPU: CPUName, /*TuneCPU*/ CPUName, FS);
256 if (InMips16Mode && !IsSoftFloat)
257 InMips16HardFloat = true;
258
259 if (StackAlignOverride)
260 stackAlignment = *StackAlignOverride;
261 else if (isABI_N32() || isABI_N64())
262 stackAlignment = Align(16);
263 else {
264 assert(isABI_O32() && "Unknown ABI for stack alignment!");
265 stackAlignment = Align(8);
266 }
267
268 if ((isABI_N32() || isABI_N64()) && !isGP64bit())
269 reportFatalUsageError(reason: "64-bit code requested on a subtarget that doesn't "
270 "support it!");
271
272 return *this;
273}
274
275bool MipsSubtarget::useConstantIslands() {
276 LLVM_DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands
277 << "\n");
278 return Mips16ConstantIslands;
279}
280
281Reloc::Model MipsSubtarget::getRelocationModel() const {
282 return TM.getRelocationModel();
283}
284
285bool MipsSubtarget::isABI_N64() const { return getABI().IsN64(); }
286bool MipsSubtarget::isABI_N32() const { return getABI().IsN32(); }
287bool MipsSubtarget::isABI_O32() const { return getABI().IsO32(); }
288const MipsABIInfo &MipsSubtarget::getABI() const { return TM.getABI(); }
289
290const SelectionDAGTargetInfo *MipsSubtarget::getSelectionDAGInfo() const {
291 return TSInfo.get();
292}
293
294const CallLowering *MipsSubtarget::getCallLowering() const {
295 return CallLoweringInfo.get();
296}
297
298const LegalizerInfo *MipsSubtarget::getLegalizerInfo() const {
299 return Legalizer.get();
300}
301
302const RegisterBankInfo *MipsSubtarget::getRegBankInfo() const {
303 return RegBankInfo.get();
304}
305
306InstructionSelector *MipsSubtarget::getInstructionSelector() const {
307 return InstSelector.get();
308}
309
310// Libcalls for which no helper is generated. Sorted by name for binary search.
311const RTLIB::LibcallImpl MipsSubtarget::HardFloatLibCalls[34] = {
312 RTLIB::impl___mips16_adddf3, RTLIB::impl___mips16_addsf3,
313 RTLIB::impl___mips16_divdf3, RTLIB::impl___mips16_divsf3,
314 RTLIB::impl___mips16_eqdf2, RTLIB::impl___mips16_eqsf2,
315 RTLIB::impl___mips16_extendsfdf2, RTLIB::impl___mips16_fix_truncdfsi,
316 RTLIB::impl___mips16_fix_truncsfsi, RTLIB::impl___mips16_floatsidf,
317 RTLIB::impl___mips16_floatsisf, RTLIB::impl___mips16_floatunsidf,
318 RTLIB::impl___mips16_floatunsisf, RTLIB::impl___mips16_gedf2,
319 RTLIB::impl___mips16_gesf2, RTLIB::impl___mips16_gtdf2,
320 RTLIB::impl___mips16_gtsf2, RTLIB::impl___mips16_ledf2,
321 RTLIB::impl___mips16_lesf2, RTLIB::impl___mips16_ltdf2,
322 RTLIB::impl___mips16_ltsf2, RTLIB::impl___mips16_muldf3,
323 RTLIB::impl___mips16_mulsf3, RTLIB::impl___mips16_nedf2,
324 RTLIB::impl___mips16_nesf2, RTLIB::impl___mips16_ret_dc,
325 RTLIB::impl___mips16_ret_df, RTLIB::impl___mips16_ret_sc,
326 RTLIB::impl___mips16_ret_sf, RTLIB::impl___mips16_subdf3,
327 RTLIB::impl___mips16_subsf3, RTLIB::impl___mips16_truncdfsf2,
328 RTLIB::impl___mips16_unorddf2, RTLIB::impl___mips16_unordsf2};
329
330void MipsSubtarget::initLibcallLoweringInfo(LibcallLoweringInfo &Info) const {
331 if (inMips16Mode() && !useSoftFloat()) {
332 for (unsigned I = 0; I != std::size(HardFloatLibCalls); ++I) {
333 assert((I == 0 || HardFloatLibCalls[I - 1] < HardFloatLibCalls[I]) &&
334 "Array not sorted!");
335 RTLIB::Libcall LC =
336 RTLIB::RuntimeLibcallsInfo::getLibcallFromImpl(Impl: HardFloatLibCalls[I]);
337 Info.setLibcallImpl(Call: LC, Impl: HardFloatLibCalls[I]);
338 }
339 }
340}
341