1//===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the Mips specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#include "MipsSubtarget.h"
14#include "Mips.h"
15#include "MipsCallLowering.h"
16#include "MipsLegalizerInfo.h"
17#include "MipsRegisterBankInfo.h"
18#include "MipsRegisterInfo.h"
19#include "MipsSelectionDAGInfo.h"
20#include "MipsTargetMachine.h"
21#include "llvm/IR/Attributes.h"
22#include "llvm/IR/Function.h"
23#include "llvm/MC/TargetRegistry.h"
24#include "llvm/Support/CommandLine.h"
25#include "llvm/Support/Debug.h"
26#include "llvm/Support/raw_ostream.h"
27
28using namespace llvm;
29
30cl::opt<CompactBranchPolicy> MipsCompactBranchPolicy(
31 "mips-compact-branches", cl::Optional, cl::init(Val: CB_Optimal),
32 cl::desc("MIPS Specific: Compact branch policy."),
33 cl::values(clEnumValN(CB_Never, "never",
34 "Do not use compact branches if possible."),
35 clEnumValN(CB_Optimal, "optimal",
36 "Use compact branches where appropriate (default)."),
37 clEnumValN(CB_Always, "always",
38 "Always use compact branches if possible.")));
39
40#define DEBUG_TYPE "mips-subtarget"
41
42#define GET_SUBTARGETINFO_TARGET_DESC
43#define GET_SUBTARGETINFO_CTOR
44#include "MipsGenSubtargetInfo.inc"
45
46// FIXME: Maybe this should be on by default when Mips16 is specified
47//
48static cl::opt<bool>
49 Mixed16_32("mips-mixed-16-32", cl::init(Val: false),
50 cl::desc("Allow for a mixture of Mips16 "
51 "and Mips32 code in a single output file"),
52 cl::Hidden);
53
54static cl::opt<bool> Mips_Os16("mips-os16", cl::init(Val: false),
55 cl::desc("Compile all functions that don't use "
56 "floating point as Mips 16"),
57 cl::Hidden);
58
59static cl::opt<bool> Mips16HardFloat("mips16-hard-float", cl::NotHidden,
60 cl::desc("Enable mips16 hard float."),
61 cl::init(Val: false));
62
63static cl::opt<bool>
64 Mips16ConstantIslands("mips16-constant-islands", cl::NotHidden,
65 cl::desc("Enable mips16 constant islands."),
66 cl::init(Val: true));
67
68static cl::opt<bool>
69 GPOpt("mgpopt", cl::Hidden,
70 cl::desc("Enable gp-relative addressing of mips small data items"));
71
72bool MipsSubtarget::DspWarningPrinted = false;
73bool MipsSubtarget::MSAWarningPrinted = false;
74bool MipsSubtarget::VirtWarningPrinted = false;
75bool MipsSubtarget::CRCWarningPrinted = false;
76bool MipsSubtarget::GINVWarningPrinted = false;
77bool MipsSubtarget::MIPS1WarningPrinted = false;
78
79void MipsSubtarget::anchor() {}
80
81MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
82 bool little, const MipsTargetMachine &TM,
83 MaybeAlign StackAlignOverride)
84 : MipsGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
85 MipsArchVersion(MipsDefault), IsLittle(little), IsSoftFloat(false),
86 IsSingleFloat(false), IsFPXX(false), NoABICalls(false), Abs2008(false),
87 IsFP64bit(false), UseOddSPReg(true), IsNaN2008bit(false),
88 IsGP64bit(false), HasVFPU(false), HasCnMips(false), HasCnMipsP(false),
89 IsR5900(false), FixR5900(false), HasMips3_32(false), HasMips3_32r2(false),
90 HasMips4_32(false), HasMips4_32r2(false), HasMips5_32r2(false),
91 InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
92 InMicroMipsMode(false), HasDSP(false), HasDSPR2(false), HasDSPR3(false),
93 AllowMixed16_32(Mixed16_32 || Mips_Os16), Os16(Mips_Os16), HasMSA(false),
94 UseTCCInDIV(false), HasSym32(false), HasEVA(false), DisableMadd4(false),
95 HasMT(false), HasCRC(false), HasVirt(false), HasGINV(false),
96 UseIndirectJumpsHazard(false), StrictAlign(false),
97 UseCompactBranches(MipsCompactBranchPolicy != CB_Never),
98 StackAlignOverride(StackAlignOverride), TM(TM), TargetTriple(TT),
99 InstrInfo(
100 MipsInstrInfo::create(STI&: initializeSubtargetDependencies(CPU, FS, TM))),
101 FrameLowering(MipsFrameLowering::create(ST: *this)),
102 TLInfo(MipsTargetLowering::create(TM, STI: *this)) {
103
104 if (MipsArchVersion == MipsDefault)
105 MipsArchVersion = Mips32;
106
107 // MIPS-I has not been tested.
108 if (MipsArchVersion == Mips1 && !MIPS1WarningPrinted) {
109 errs() << "warning: MIPS-I support is experimental\n";
110 MIPS1WarningPrinted = true;
111 }
112
113 // Don't even attempt to generate code for MIPS-V. It has not
114 // been tested and currently exists for the integrated assembler only.
115 if (MipsArchVersion == Mips5)
116 report_fatal_error(reason: "Code generation for MIPS-V is not implemented", gen_crash_diag: false);
117
118 // Check if Architecture and ABI are compatible.
119 assert(((!isGP64bit() && isABI_O32()) || isGP64bit()) &&
120 "Invalid Arch & ABI pair.");
121
122 if (hasMSA() && !isFP64bit())
123 report_fatal_error(reason: "MSA requires a 64-bit FPU register file (FR=1 mode). "
124 "See -mattr=+fp64.",
125 gen_crash_diag: false);
126
127 if (isFP64bit() && !hasMips64() && hasMips32() && !hasMips32r2())
128 report_fatal_error(
129 reason: "FPU with 64-bit registers is not available on MIPS32 pre revision 2. "
130 "Use -mcpu=mips32r2 or greater.", gen_crash_diag: false);
131
132 if (!isABI_O32() && !useOddSPReg())
133 report_fatal_error(reason: "-mattr=+nooddspreg requires the O32 ABI.", gen_crash_diag: false);
134
135 if (IsFPXX && (isABI_N32() || isABI_N64()))
136 report_fatal_error(reason: "FPXX is not permitted for the N32/N64 ABI's.", gen_crash_diag: false);
137
138 if (hasMips64r6() && InMicroMipsMode)
139 report_fatal_error(reason: "microMIPS64R6 is not supported", gen_crash_diag: false);
140
141 if (!isABI_O32() && InMicroMipsMode)
142 report_fatal_error(reason: "microMIPS64 is not supported.", gen_crash_diag: false);
143
144 if (UseIndirectJumpsHazard) {
145 if (InMicroMipsMode)
146 report_fatal_error(
147 reason: "cannot combine indirect jumps with hazard barriers and microMIPS");
148 if (!hasMips32r2())
149 report_fatal_error(
150 reason: "indirect jumps with hazard barriers requires MIPS32R2 or later");
151 }
152 if (inAbs2008Mode() && hasMips32() && !hasMips32r2()) {
153 report_fatal_error(reason: "IEEE 754-2008 abs.fmt is not supported for the given "
154 "architecture.",
155 gen_crash_diag: false);
156 }
157
158 if (hasMips32r6()) {
159 StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
160
161 assert(isFP64bit());
162 assert(isNaN2008());
163 assert(inAbs2008Mode());
164 if (hasDSP())
165 report_fatal_error(reason: ISA + " is not compatible with the DSP ASE", gen_crash_diag: false);
166 }
167
168 if (NoABICalls && TM.isPositionIndependent())
169 report_fatal_error(reason: "position-independent code requires '-mabicalls'");
170
171 if (isABI_N64() && !TM.isPositionIndependent() && !hasSym32())
172 NoABICalls = true;
173
174 // Set UseSmallSection.
175 UseSmallSection = GPOpt;
176 if (!NoABICalls && GPOpt) {
177 errs() << "warning: cannot use small-data accesses for '-mabicalls'"
178 << "\n";
179 UseSmallSection = false;
180 }
181
182 if (hasDSPR2() && !DspWarningPrinted) {
183 if (hasMips64() && !hasMips64r2()) {
184 errs() << "warning: the 'dspr2' ASE requires MIPS64 revision 2 or "
185 << "greater\n";
186 DspWarningPrinted = true;
187 } else if (hasMips32() && !hasMips32r2()) {
188 errs() << "warning: the 'dspr2' ASE requires MIPS32 revision 2 or "
189 << "greater\n";
190 DspWarningPrinted = true;
191 }
192 } else if (hasDSP() && !DspWarningPrinted) {
193 if (hasMips64() && !hasMips64r2()) {
194 errs() << "warning: the 'dsp' ASE requires MIPS64 revision 2 or "
195 << "greater\n";
196 DspWarningPrinted = true;
197 } else if (hasMips32() && !hasMips32r2()) {
198 errs() << "warning: the 'dsp' ASE requires MIPS32 revision 2 or "
199 << "greater\n";
200 DspWarningPrinted = true;
201 }
202 }
203
204 StringRef ArchName = hasMips64() ? "MIPS64" : "MIPS32";
205
206 if (!hasMips32r5() && hasMSA() && !MSAWarningPrinted) {
207 errs() << "warning: the 'msa' ASE requires " << ArchName
208 << " revision 5 or greater\n";
209 MSAWarningPrinted = true;
210 }
211 if (!hasMips32r5() && hasVirt() && !VirtWarningPrinted) {
212 errs() << "warning: the 'virt' ASE requires " << ArchName
213 << " revision 5 or greater\n";
214 VirtWarningPrinted = true;
215 }
216 if (!hasMips32r6() && hasCRC() && !CRCWarningPrinted) {
217 errs() << "warning: the 'crc' ASE requires " << ArchName
218 << " revision 6 or greater\n";
219 CRCWarningPrinted = true;
220 }
221 if (!hasMips32r6() && hasGINV() && !GINVWarningPrinted) {
222 errs() << "warning: the 'ginv' ASE requires " << ArchName
223 << " revision 6 or greater\n";
224 GINVWarningPrinted = true;
225 }
226
227 TSInfo = std::make_unique<MipsSelectionDAGInfo>();
228
229 CallLoweringInfo.reset(p: new MipsCallLowering(*getTargetLowering()));
230 Legalizer.reset(p: new MipsLegalizerInfo(*this));
231
232 auto *RBI = new MipsRegisterBankInfo(*getRegisterInfo());
233 RegBankInfo.reset(p: RBI);
234 InstSelector.reset(p: createMipsInstructionSelector(TM, *this, *RBI));
235}
236
237MipsSubtarget::~MipsSubtarget() = default;
238
239bool MipsSubtarget::isPositionIndependent() const {
240 return TM.isPositionIndependent();
241}
242
243/// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
244bool MipsSubtarget::enablePostRAScheduler() const { return true; }
245
246void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
247 CriticalPathRCs.clear();
248 CriticalPathRCs.push_back(Elt: isGP64bit() ? &Mips::GPR64RegClass
249 : &Mips::GPR32RegClass);
250}
251
252CodeGenOptLevel MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
253 return CodeGenOptLevel::Aggressive;
254}
255
256MipsSubtarget &
257MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
258 const TargetMachine &TM) {
259 StringRef CPUName = MIPS_MC::selectMipsCPU(TT: TM.getTargetTriple(), CPU);
260
261 // Parse features string.
262 ParseSubtargetFeatures(CPU: CPUName, /*TuneCPU*/ CPUName, FS);
263 // Initialize scheduling itinerary for the specified CPU.
264 InstrItins = getInstrItineraryForCPU(CPU: CPUName);
265
266 if (InMips16Mode && !IsSoftFloat)
267 InMips16HardFloat = true;
268
269 if (StackAlignOverride)
270 stackAlignment = *StackAlignOverride;
271 else if (isABI_N32() || isABI_N64())
272 stackAlignment = Align(16);
273 else {
274 assert(isABI_O32() && "Unknown ABI for stack alignment!");
275 stackAlignment = Align(8);
276 }
277
278 if ((isABI_N32() || isABI_N64()) && !isGP64bit())
279 reportFatalUsageError(reason: "64-bit code requested on a subtarget that doesn't "
280 "support it!");
281
282 return *this;
283}
284
285bool MipsSubtarget::useConstantIslands() {
286 LLVM_DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands
287 << "\n");
288 return Mips16ConstantIslands;
289}
290
291Reloc::Model MipsSubtarget::getRelocationModel() const {
292 return TM.getRelocationModel();
293}
294
295bool MipsSubtarget::isABI_N64() const { return getABI().IsN64(); }
296bool MipsSubtarget::isABI_N32() const { return getABI().IsN32(); }
297bool MipsSubtarget::isABI_O32() const { return getABI().IsO32(); }
298const MipsABIInfo &MipsSubtarget::getABI() const { return TM.getABI(); }
299
300const SelectionDAGTargetInfo *MipsSubtarget::getSelectionDAGInfo() const {
301 return TSInfo.get();
302}
303
304const CallLowering *MipsSubtarget::getCallLowering() const {
305 return CallLoweringInfo.get();
306}
307
308const LegalizerInfo *MipsSubtarget::getLegalizerInfo() const {
309 return Legalizer.get();
310}
311
312const RegisterBankInfo *MipsSubtarget::getRegBankInfo() const {
313 return RegBankInfo.get();
314}
315
316InstructionSelector *MipsSubtarget::getInstructionSelector() const {
317 return InstSelector.get();
318}
319
320// Libcalls for which no helper is generated. Sorted by name for binary search.
321const RTLIB::LibcallImpl MipsSubtarget::HardFloatLibCalls[34] = {
322 RTLIB::impl___mips16_adddf3, RTLIB::impl___mips16_addsf3,
323 RTLIB::impl___mips16_divdf3, RTLIB::impl___mips16_divsf3,
324 RTLIB::impl___mips16_eqdf2, RTLIB::impl___mips16_eqsf2,
325 RTLIB::impl___mips16_extendsfdf2, RTLIB::impl___mips16_fix_truncdfsi,
326 RTLIB::impl___mips16_fix_truncsfsi, RTLIB::impl___mips16_floatsidf,
327 RTLIB::impl___mips16_floatsisf, RTLIB::impl___mips16_floatunsidf,
328 RTLIB::impl___mips16_floatunsisf, RTLIB::impl___mips16_gedf2,
329 RTLIB::impl___mips16_gesf2, RTLIB::impl___mips16_gtdf2,
330 RTLIB::impl___mips16_gtsf2, RTLIB::impl___mips16_ledf2,
331 RTLIB::impl___mips16_lesf2, RTLIB::impl___mips16_ltdf2,
332 RTLIB::impl___mips16_ltsf2, RTLIB::impl___mips16_muldf3,
333 RTLIB::impl___mips16_mulsf3, RTLIB::impl___mips16_nedf2,
334 RTLIB::impl___mips16_nesf2, RTLIB::impl___mips16_ret_dc,
335 RTLIB::impl___mips16_ret_df, RTLIB::impl___mips16_ret_sc,
336 RTLIB::impl___mips16_ret_sf, RTLIB::impl___mips16_subdf3,
337 RTLIB::impl___mips16_subsf3, RTLIB::impl___mips16_truncdfsf2,
338 RTLIB::impl___mips16_unorddf2, RTLIB::impl___mips16_unordsf2};
339
340void MipsSubtarget::initLibcallLoweringInfo(LibcallLoweringInfo &Info) const {
341 if (inMips16Mode() && !useSoftFloat()) {
342 for (unsigned I = 0; I != std::size(HardFloatLibCalls); ++I) {
343 assert((I == 0 || HardFloatLibCalls[I - 1] < HardFloatLibCalls[I]) &&
344 "Array not sorted!");
345 RTLIB::Libcall LC =
346 RTLIB::RuntimeLibcallsInfo::getLibcallFromImpl(Impl: HardFloatLibCalls[I]);
347 Info.setLibcallImpl(Call: LC, Impl: HardFloatLibCalls[I]);
348 }
349 }
350}
351