1//===-- RISCVInstrInfo.cpp - RISC-V Instruction Information -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the RISC-V implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVInstrInfo.h"
14#include "MCTargetDesc/RISCVBaseInfo.h"
15#include "MCTargetDesc/RISCVMatInt.h"
16#include "RISCV.h"
17#include "RISCVMachineFunctionInfo.h"
18#include "RISCVSubtarget.h"
19#include "llvm/ADT/STLExtras.h"
20#include "llvm/ADT/SmallVector.h"
21#include "llvm/ADT/Statistic.h"
22#include "llvm/Analysis/MemoryLocation.h"
23#include "llvm/Analysis/ValueTracking.h"
24#include "llvm/CodeGen/LiveIntervals.h"
25#include "llvm/CodeGen/LiveVariables.h"
26#include "llvm/CodeGen/MachineCombinerPattern.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/MachineRegisterInfo.h"
29#include "llvm/CodeGen/MachineTraceMetrics.h"
30#include "llvm/CodeGen/RegisterScavenging.h"
31#include "llvm/CodeGen/StackMaps.h"
32#include "llvm/IR/DebugInfoMetadata.h"
33#include "llvm/IR/Module.h"
34#include "llvm/MC/MCDwarf.h"
35#include "llvm/MC/MCInstBuilder.h"
36#include "llvm/MC/TargetRegistry.h"
37#include "llvm/Support/ErrorHandling.h"
38
39using namespace llvm;
40
41#define GEN_CHECK_COMPRESS_INSTR
42#include "RISCVGenCompressInstEmitter.inc"
43
44#define GET_INSTRINFO_CTOR_DTOR
45#include "RISCVGenInstrInfo.inc"
46
47#define DEBUG_TYPE "riscv-instr-info"
48STATISTIC(NumVRegSpilled,
49 "Number of registers within vector register groups spilled");
50STATISTIC(NumVRegReloaded,
51 "Number of registers within vector register groups reloaded");
52
53static cl::opt<bool> PreferWholeRegisterMove(
54 "riscv-prefer-whole-register-move", cl::init(Val: false), cl::Hidden,
55 cl::desc("Prefer whole register move for vector registers."));
56
57static cl::opt<MachineTraceStrategy> ForceMachineCombinerStrategy(
58 "riscv-force-machine-combiner-strategy", cl::Hidden,
59 cl::desc("Force machine combiner to use a specific strategy for machine "
60 "trace metrics evaluation."),
61 cl::init(Val: MachineTraceStrategy::TS_NumStrategies),
62 cl::values(clEnumValN(MachineTraceStrategy::TS_Local, "local",
63 "Local strategy."),
64 clEnumValN(MachineTraceStrategy::TS_MinInstrCount, "min-instr",
65 "MinInstrCount strategy.")));
66
67static cl::opt<bool> OutlinerEnableRegSave(
68 "riscv-outliner-regsave", cl::init(Val: true), cl::Hidden,
69 cl::desc("Enable RegSave strategy in machine outliner (save X5 to a "
70 "temporary register when X5 is live across outlined calls)."));
71
72namespace llvm::RISCVVPseudosTable {
73
74using namespace RISCV;
75
76#define GET_RISCVVPseudosTable_IMPL
77#include "RISCVGenSearchableTables.inc"
78
79} // namespace llvm::RISCVVPseudosTable
80
81namespace llvm::RISCV {
82
83#define GET_RISCVMaskedPseudosTable_IMPL
84#include "RISCVGenSearchableTables.inc"
85
86} // end namespace llvm::RISCV
87
88RISCVInstrInfo::RISCVInstrInfo(const RISCVSubtarget &STI)
89 : RISCVGenInstrInfo(STI, RegInfo, RISCV::ADJCALLSTACKDOWN,
90 RISCV::ADJCALLSTACKUP),
91 RegInfo(STI.getHwMode()), STI(STI) {}
92
93#define GET_INSTRINFO_HELPERS
94#include "RISCVGenInstrInfo.inc"
95
96MCInst RISCVInstrInfo::getNop() const {
97 if (STI.hasStdExtZca())
98 return MCInstBuilder(RISCV::C_NOP);
99 return MCInstBuilder(RISCV::ADDI)
100 .addReg(Reg: RISCV::X0)
101 .addReg(Reg: RISCV::X0)
102 .addImm(Val: 0);
103}
104
105Register RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
106 int &FrameIndex) const {
107 TypeSize Dummy = TypeSize::getZero();
108 return isLoadFromStackSlot(MI, FrameIndex, MemBytes&: Dummy);
109}
110
111static std::optional<unsigned> getLMULForRVVWholeLoadStore(unsigned Opcode) {
112 switch (Opcode) {
113 default:
114 return std::nullopt;
115 case RISCV::VS1R_V:
116 case RISCV::VL1RE8_V:
117 case RISCV::VL1RE16_V:
118 case RISCV::VL1RE32_V:
119 case RISCV::VL1RE64_V:
120 return 1;
121 case RISCV::VS2R_V:
122 case RISCV::VL2RE8_V:
123 case RISCV::VL2RE16_V:
124 case RISCV::VL2RE32_V:
125 case RISCV::VL2RE64_V:
126 return 2;
127 case RISCV::VS4R_V:
128 case RISCV::VL4RE8_V:
129 case RISCV::VL4RE16_V:
130 case RISCV::VL4RE32_V:
131 case RISCV::VL4RE64_V:
132 return 4;
133 case RISCV::VS8R_V:
134 case RISCV::VL8RE8_V:
135 case RISCV::VL8RE16_V:
136 case RISCV::VL8RE32_V:
137 case RISCV::VL8RE64_V:
138 return 8;
139 }
140}
141
142Register RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
143 int &FrameIndex,
144 TypeSize &MemBytes) const {
145 switch (MI.getOpcode()) {
146 default:
147 return 0;
148 case RISCV::LB:
149 case RISCV::LBU:
150 MemBytes = TypeSize::getFixed(ExactSize: 1);
151 break;
152 case RISCV::LH:
153 case RISCV::LH_INX:
154 case RISCV::LHU:
155 case RISCV::FLH:
156 MemBytes = TypeSize::getFixed(ExactSize: 2);
157 break;
158 case RISCV::LW:
159 case RISCV::LW_INX:
160 case RISCV::FLW:
161 case RISCV::LWU:
162 MemBytes = TypeSize::getFixed(ExactSize: 4);
163 break;
164 case RISCV::LD:
165 case RISCV::LD_RV32:
166 case RISCV::FLD:
167 MemBytes = TypeSize::getFixed(ExactSize: 8);
168 break;
169 case RISCV::VL1RE8_V:
170 case RISCV::VL2RE8_V:
171 case RISCV::VL4RE8_V:
172 case RISCV::VL8RE8_V:
173 if (!MI.getOperand(i: 1).isFI())
174 return Register();
175 FrameIndex = MI.getOperand(i: 1).getIndex();
176 unsigned LMUL = *getLMULForRVVWholeLoadStore(Opcode: MI.getOpcode());
177 MemBytes = TypeSize::getScalable(MinimumSize: RISCV::RVVBytesPerBlock * LMUL);
178 return MI.getOperand(i: 0).getReg();
179 }
180
181 if (MI.getOperand(i: 1).isFI() && MI.getOperand(i: 2).isImm() &&
182 MI.getOperand(i: 2).getImm() == 0) {
183 FrameIndex = MI.getOperand(i: 1).getIndex();
184 return MI.getOperand(i: 0).getReg();
185 }
186
187 return 0;
188}
189
190Register RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
191 int &FrameIndex) const {
192 TypeSize Dummy = TypeSize::getZero();
193 return isStoreToStackSlot(MI, FrameIndex, MemBytes&: Dummy);
194}
195
196Register RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
197 int &FrameIndex,
198 TypeSize &MemBytes) const {
199 switch (MI.getOpcode()) {
200 default:
201 return 0;
202 case RISCV::SB:
203 MemBytes = TypeSize::getFixed(ExactSize: 1);
204 break;
205 case RISCV::SH:
206 case RISCV::SH_INX:
207 case RISCV::FSH:
208 MemBytes = TypeSize::getFixed(ExactSize: 2);
209 break;
210 case RISCV::SW:
211 case RISCV::SW_INX:
212 case RISCV::FSW:
213 MemBytes = TypeSize::getFixed(ExactSize: 4);
214 break;
215 case RISCV::SD:
216 case RISCV::SD_RV32:
217 case RISCV::FSD:
218 MemBytes = TypeSize::getFixed(ExactSize: 8);
219 break;
220 case RISCV::VS1R_V:
221 case RISCV::VS2R_V:
222 case RISCV::VS4R_V:
223 case RISCV::VS8R_V:
224 if (!MI.getOperand(i: 1).isFI())
225 return Register();
226 FrameIndex = MI.getOperand(i: 1).getIndex();
227 unsigned LMUL = *getLMULForRVVWholeLoadStore(Opcode: MI.getOpcode());
228 MemBytes = TypeSize::getScalable(MinimumSize: RISCV::RVVBytesPerBlock * LMUL);
229 return MI.getOperand(i: 0).getReg();
230 }
231
232 if (MI.getOperand(i: 1).isFI() && MI.getOperand(i: 2).isImm() &&
233 MI.getOperand(i: 2).getImm() == 0) {
234 FrameIndex = MI.getOperand(i: 1).getIndex();
235 return MI.getOperand(i: 0).getReg();
236 }
237
238 return 0;
239}
240
241bool RISCVInstrInfo::isReMaterializableImpl(
242 const MachineInstr &MI) const {
243 switch (RISCV::getRVVMCOpcode(RVVPseudoOpcode: MI.getOpcode())) {
244 case RISCV::VMV_V_X:
245 case RISCV::VFMV_V_F:
246 case RISCV::VMV_V_I:
247 case RISCV::VMV_S_X:
248 case RISCV::VFMV_S_F:
249 case RISCV::VID_V:
250 return MI.getOperand(i: 1).isUndef();
251 default:
252 return TargetInstrInfo::isReMaterializableImpl(MI);
253 }
254}
255
256static bool forwardCopyWillClobberTuple(unsigned DstReg, unsigned SrcReg,
257 unsigned NumRegs) {
258 return DstReg > SrcReg && (DstReg - SrcReg) < NumRegs;
259}
260
261static bool isConvertibleToVMV_V_V(const RISCVSubtarget &STI,
262 const MachineBasicBlock &MBB,
263 MachineBasicBlock::const_iterator MBBI,
264 MachineBasicBlock::const_iterator &DefMBBI,
265 RISCVVType::VLMUL LMul) {
266 if (PreferWholeRegisterMove)
267 return false;
268
269 assert(MBBI->getOpcode() == TargetOpcode::COPY &&
270 "Unexpected COPY instruction.");
271 Register SrcReg = MBBI->getOperand(i: 1).getReg();
272 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
273
274 bool FoundDef = false;
275 bool FirstVSetVLI = false;
276 unsigned FirstSEW = 0;
277 while (MBBI != MBB.begin()) {
278 --MBBI;
279 if (MBBI->isMetaInstruction())
280 continue;
281
282 if (RISCVInstrInfo::isVectorConfigInstr(MI: *MBBI)) {
283 // There is a vsetvli between COPY and source define instruction.
284 // vy = def_vop ... (producing instruction)
285 // ...
286 // vsetvli
287 // ...
288 // vx = COPY vy
289 if (!FoundDef) {
290 if (!FirstVSetVLI) {
291 FirstVSetVLI = true;
292 unsigned FirstVType = MBBI->getOperand(i: 2).getImm();
293 RISCVVType::VLMUL FirstLMul = RISCVVType::getVLMUL(VType: FirstVType);
294 FirstSEW = RISCVVType::getSEW(VType: FirstVType);
295 // The first encountered vsetvli must have the same lmul as the
296 // register class of COPY.
297 if (FirstLMul != LMul)
298 return false;
299 }
300 // Only permit `vsetvli x0, x0, vtype` between COPY and the source
301 // define instruction.
302 if (!RISCVInstrInfo::isVLPreservingConfig(MI: *MBBI))
303 return false;
304 continue;
305 }
306
307 // MBBI is the first vsetvli before the producing instruction.
308 unsigned VType = MBBI->getOperand(i: 2).getImm();
309 // If there is a vsetvli between COPY and the producing instruction.
310 if (FirstVSetVLI) {
311 // If SEW is different, return false.
312 if (RISCVVType::getSEW(VType) != FirstSEW)
313 return false;
314 }
315
316 // If the vsetvli is tail undisturbed, keep the whole register move.
317 if (!RISCVVType::isTailAgnostic(VType))
318 return false;
319
320 // The checking is conservative. We only have register classes for
321 // LMUL = 1/2/4/8. We should be able to convert vmv1r.v to vmv.v.v
322 // for fractional LMUL operations. However, we could not use the vsetvli
323 // lmul for widening operations. The result of widening operation is
324 // 2 x LMUL.
325 return LMul == RISCVVType::getVLMUL(VType);
326 } else if (MBBI->isInlineAsm() || MBBI->isCall()) {
327 return false;
328 } else if (MBBI->getNumDefs()) {
329 // Check all the instructions which will change VL.
330 // For example, vleff has implicit def VL.
331 if (MBBI->modifiesRegister(Reg: RISCV::VL, /*TRI=*/nullptr))
332 return false;
333
334 // Only converting whole register copies to vmv.v.v when the defining
335 // value appears in the explicit operands.
336 for (const MachineOperand &MO : MBBI->explicit_operands()) {
337 if (!MO.isReg() || !MO.isDef())
338 continue;
339 if (!FoundDef && TRI->regsOverlap(RegA: MO.getReg(), RegB: SrcReg)) {
340 // We only permit the source of COPY has the same LMUL as the defined
341 // operand.
342 // There are cases we need to keep the whole register copy if the LMUL
343 // is different.
344 // For example,
345 // $x0 = PseudoVSETIVLI 4, 73 // vsetivli zero, 4, e16,m2,ta,m
346 // $v28m4 = PseudoVWADD_VV_M2 $v26m2, $v8m2
347 // # The COPY may be created by vlmul_trunc intrinsic.
348 // $v26m2 = COPY renamable $v28m2, implicit killed $v28m4
349 //
350 // After widening, the valid value will be 4 x e32 elements. If we
351 // convert the COPY to vmv.v.v, it will only copy 4 x e16 elements.
352 // FIXME: The COPY of subregister of Zvlsseg register will not be able
353 // to convert to vmv.v.[v|i] under the constraint.
354 if (MO.getReg() != SrcReg)
355 return false;
356
357 // In widening reduction instructions with LMUL_1 input vector case,
358 // only checking the LMUL is insufficient due to reduction result is
359 // always LMUL_1.
360 // For example,
361 // $x11 = PseudoVSETIVLI 1, 64 // vsetivli a1, 1, e8, m1, ta, mu
362 // $v8m1 = PseudoVWREDSUM_VS_M1 $v26, $v27
363 // $v26 = COPY killed renamable $v8
364 // After widening, The valid value will be 1 x e16 elements. If we
365 // convert the COPY to vmv.v.v, it will only copy 1 x e8 elements.
366 uint64_t TSFlags = MBBI->getDesc().TSFlags;
367 if (RISCVII::isRVVWideningReduction(TSFlags))
368 return false;
369
370 // If the producing instruction does not depend on vsetvli, do not
371 // convert COPY to vmv.v.v. For example, VL1R_V or PseudoVRELOAD.
372 if (!RISCVII::hasSEWOp(TSFlags) || !RISCVII::hasVLOp(TSFlags))
373 return false;
374
375 // Found the definition.
376 FoundDef = true;
377 DefMBBI = MBBI;
378 break;
379 }
380 }
381 }
382 }
383
384 return false;
385}
386
387void RISCVInstrInfo::copyPhysRegVector(
388 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
389 const DebugLoc &DL, MCRegister DstReg, MCRegister SrcReg, bool KillSrc,
390 const TargetRegisterClass *RegClass) const {
391 const RISCVRegisterInfo *TRI = STI.getRegisterInfo();
392 RISCVVType::VLMUL LMul = RISCVRI::getLMul(TSFlags: RegClass->TSFlags);
393 unsigned NF = RISCVRI::getNF(TSFlags: RegClass->TSFlags);
394
395 uint16_t SrcEncoding = TRI->getEncodingValue(Reg: SrcReg);
396 uint16_t DstEncoding = TRI->getEncodingValue(Reg: DstReg);
397 auto [LMulVal, Fractional] = RISCVVType::decodeVLMUL(VLMul: LMul);
398 assert(!Fractional && "It is impossible be fractional lmul here.");
399 unsigned NumRegs = NF * LMulVal;
400 bool ReversedCopy =
401 forwardCopyWillClobberTuple(DstReg: DstEncoding, SrcReg: SrcEncoding, NumRegs);
402 if (ReversedCopy) {
403 // If the src and dest overlap when copying a tuple, we need to copy the
404 // registers in reverse.
405 SrcEncoding += NumRegs - 1;
406 DstEncoding += NumRegs - 1;
407 }
408
409 unsigned I = 0;
410 auto GetCopyInfo = [&](uint16_t SrcEncoding, uint16_t DstEncoding)
411 -> std::tuple<RISCVVType::VLMUL, const TargetRegisterClass &, unsigned,
412 unsigned, unsigned> {
413 if (ReversedCopy) {
414 // For reversed copying, if there are enough aligned registers(8/4/2), we
415 // can do a larger copy(LMUL8/4/2).
416 // Besides, we have already known that DstEncoding is larger than
417 // SrcEncoding in forwardCopyWillClobberTuple, so the difference between
418 // DstEncoding and SrcEncoding should be >= LMUL value we try to use to
419 // avoid clobbering.
420 uint16_t Diff = DstEncoding - SrcEncoding;
421 if (I + 8 <= NumRegs && Diff >= 8 && SrcEncoding % 8 == 7 &&
422 DstEncoding % 8 == 7)
423 return {RISCVVType::LMUL_8, RISCV::VRM8RegClass, RISCV::VMV8R_V,
424 RISCV::PseudoVMV_V_V_M8, RISCV::PseudoVMV_V_I_M8};
425 if (I + 4 <= NumRegs && Diff >= 4 && SrcEncoding % 4 == 3 &&
426 DstEncoding % 4 == 3)
427 return {RISCVVType::LMUL_4, RISCV::VRM4RegClass, RISCV::VMV4R_V,
428 RISCV::PseudoVMV_V_V_M4, RISCV::PseudoVMV_V_I_M4};
429 if (I + 2 <= NumRegs && Diff >= 2 && SrcEncoding % 2 == 1 &&
430 DstEncoding % 2 == 1)
431 return {RISCVVType::LMUL_2, RISCV::VRM2RegClass, RISCV::VMV2R_V,
432 RISCV::PseudoVMV_V_V_M2, RISCV::PseudoVMV_V_I_M2};
433 // Or we should do LMUL1 copying.
434 return {RISCVVType::LMUL_1, RISCV::VRRegClass, RISCV::VMV1R_V,
435 RISCV::PseudoVMV_V_V_M1, RISCV::PseudoVMV_V_I_M1};
436 }
437
438 // For forward copying, if source register encoding and destination register
439 // encoding are aligned to 8/4/2, we can do a LMUL8/4/2 copying.
440 if (I + 8 <= NumRegs && SrcEncoding % 8 == 0 && DstEncoding % 8 == 0)
441 return {RISCVVType::LMUL_8, RISCV::VRM8RegClass, RISCV::VMV8R_V,
442 RISCV::PseudoVMV_V_V_M8, RISCV::PseudoVMV_V_I_M8};
443 if (I + 4 <= NumRegs && SrcEncoding % 4 == 0 && DstEncoding % 4 == 0)
444 return {RISCVVType::LMUL_4, RISCV::VRM4RegClass, RISCV::VMV4R_V,
445 RISCV::PseudoVMV_V_V_M4, RISCV::PseudoVMV_V_I_M4};
446 if (I + 2 <= NumRegs && SrcEncoding % 2 == 0 && DstEncoding % 2 == 0)
447 return {RISCVVType::LMUL_2, RISCV::VRM2RegClass, RISCV::VMV2R_V,
448 RISCV::PseudoVMV_V_V_M2, RISCV::PseudoVMV_V_I_M2};
449 // Or we should do LMUL1 copying.
450 return {RISCVVType::LMUL_1, RISCV::VRRegClass, RISCV::VMV1R_V,
451 RISCV::PseudoVMV_V_V_M1, RISCV::PseudoVMV_V_I_M1};
452 };
453
454 while (I != NumRegs) {
455 // For non-segment copying, we only do this once as the registers are always
456 // aligned.
457 // For segment copying, we may do this several times. If the registers are
458 // aligned to larger LMUL, we can eliminate some copyings.
459 auto [LMulCopied, RegClass, Opc, VVOpc, VIOpc] =
460 GetCopyInfo(SrcEncoding, DstEncoding);
461 auto [NumCopied, _] = RISCVVType::decodeVLMUL(VLMul: LMulCopied);
462
463 MachineBasicBlock::const_iterator DefMBBI;
464 if (LMul == LMulCopied &&
465 isConvertibleToVMV_V_V(STI, MBB, MBBI, DefMBBI, LMul)) {
466 Opc = VVOpc;
467 if (DefMBBI->getOpcode() == VIOpc)
468 Opc = VIOpc;
469 }
470
471 // Emit actual copying.
472 // For reversed copying, the encoding should be decreased.
473 MCRegister ActualSrcReg = TRI->findVRegWithEncoding(
474 RegClass, Encoding: ReversedCopy ? (SrcEncoding - NumCopied + 1) : SrcEncoding);
475 MCRegister ActualDstReg = TRI->findVRegWithEncoding(
476 RegClass, Encoding: ReversedCopy ? (DstEncoding - NumCopied + 1) : DstEncoding);
477
478 auto MIB = BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: Opc), DestReg: ActualDstReg);
479 bool UseVMV_V_I = RISCV::getRVVMCOpcode(RVVPseudoOpcode: Opc) == RISCV::VMV_V_I;
480 bool UseVMV = UseVMV_V_I || RISCV::getRVVMCOpcode(RVVPseudoOpcode: Opc) == RISCV::VMV_V_V;
481 if (UseVMV)
482 MIB.addReg(RegNo: ActualDstReg, Flags: RegState::Undef);
483 if (UseVMV_V_I)
484 MIB = MIB.add(MO: DefMBBI->getOperand(i: 2));
485 else
486 MIB = MIB.addReg(RegNo: ActualSrcReg, Flags: getKillRegState(B: KillSrc));
487 if (UseVMV) {
488 const MCInstrDesc &Desc = DefMBBI->getDesc();
489 MIB.add(MO: DefMBBI->getOperand(i: RISCVII::getVLOpNum(Desc))); // AVL
490 unsigned Log2SEW =
491 DefMBBI->getOperand(i: RISCVII::getSEWOpNum(Desc)).getImm();
492 MIB.addImm(Val: Log2SEW ? Log2SEW : 3); // SEW
493 MIB.addImm(Val: 0); // tu, mu
494 MIB.addReg(RegNo: RISCV::VL, Flags: RegState::Implicit);
495 MIB.addReg(RegNo: RISCV::VTYPE, Flags: RegState::Implicit);
496 }
497 // Add an implicit read of the original source to silence the verifier
498 // in the cases where some of the smaller VRs we're copying from might be
499 // undef, caused by the fact that the original, larger source VR might not
500 // be fully initialized at the time this COPY happens.
501 MIB.addReg(RegNo: SrcReg, Flags: RegState::Implicit);
502
503 // If we are copying reversely, we should decrease the encoding.
504 SrcEncoding += (ReversedCopy ? -NumCopied : NumCopied);
505 DstEncoding += (ReversedCopy ? -NumCopied : NumCopied);
506 I += NumCopied;
507 }
508}
509
510void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
511 MachineBasicBlock::iterator MBBI,
512 const DebugLoc &DL, Register DstReg,
513 Register SrcReg, bool KillSrc,
514 bool RenamableDest, bool RenamableSrc) const {
515 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
516 RegState KillFlag = getKillRegState(B: KillSrc);
517
518 if (RISCV::GPRRegClass.contains(Reg1: DstReg, Reg2: SrcReg)) {
519 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: RISCV::ADDI), DestReg: DstReg)
520 .addReg(RegNo: SrcReg, Flags: KillFlag | getRenamableRegState(B: RenamableSrc))
521 .addImm(Val: 0);
522 return;
523 }
524
525 // Extracting from X0_Pair may create copies from DUMMY_REG_PAIR_WITH_X0.
526 if (SrcReg == RISCV::DUMMY_REG_PAIR_WITH_X0 &&
527 RISCV::GPRRegClass.contains(Reg: DstReg)) {
528 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: RISCV::ADDI), DestReg: DstReg)
529 .addReg(RegNo: RISCV::X0)
530 .addImm(Val: 0);
531 return;
532 }
533
534 if (RISCV::GPRF16RegClass.contains(Reg1: DstReg, Reg2: SrcReg)) {
535 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: RISCV::PseudoMV_FPR16INX), DestReg: DstReg)
536 .addReg(RegNo: SrcReg, Flags: KillFlag | getRenamableRegState(B: RenamableSrc));
537 return;
538 }
539
540 if (RISCV::GPRF32RegClass.contains(Reg1: DstReg, Reg2: SrcReg)) {
541 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: RISCV::PseudoMV_FPR32INX), DestReg: DstReg)
542 .addReg(RegNo: SrcReg, Flags: KillFlag | getRenamableRegState(B: RenamableSrc));
543 return;
544 }
545
546 if (RISCV::GPRPairRegClass.contains(Reg1: DstReg, Reg2: SrcReg)) {
547 if (STI.isRV32()) {
548 if (STI.hasStdExtZdinx()) {
549 // On RV32_Zdinx, FMV.D will move a pair of registers to another pair of
550 // registers, in one instruction.
551 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: RISCV::FSGNJ_D_IN32X), DestReg: DstReg)
552 .addReg(RegNo: SrcReg, Flags: getRenamableRegState(B: RenamableSrc))
553 .addReg(RegNo: SrcReg, Flags: KillFlag | getRenamableRegState(B: RenamableSrc));
554 return;
555 }
556
557 if (STI.hasStdExtP()) {
558 // On RV32P, `padd.dw` is a GPR Pair Add
559 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: RISCV::PADD_DW), DestReg: DstReg)
560 .addReg(RegNo: RISCV::X0_Pair)
561 .addReg(RegNo: SrcReg, Flags: KillFlag | getRenamableRegState(B: RenamableSrc));
562 return;
563 }
564 }
565
566 MCRegister EvenReg = TRI->getSubReg(Reg: SrcReg, Idx: RISCV::sub_gpr_even);
567 MCRegister OddReg = TRI->getSubReg(Reg: SrcReg, Idx: RISCV::sub_gpr_odd);
568 // We need to correct the odd register of X0_Pair.
569 if (OddReg == RISCV::DUMMY_REG_PAIR_WITH_X0)
570 OddReg = RISCV::X0;
571 assert(DstReg != RISCV::X0_Pair && "Cannot write to X0_Pair");
572
573 // Emit an ADDI for both parts of GPRPair.
574 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: RISCV::ADDI),
575 DestReg: TRI->getSubReg(Reg: DstReg, Idx: RISCV::sub_gpr_even))
576 .addReg(RegNo: EvenReg, Flags: KillFlag)
577 .addImm(Val: 0);
578 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: RISCV::ADDI),
579 DestReg: TRI->getSubReg(Reg: DstReg, Idx: RISCV::sub_gpr_odd))
580 .addReg(RegNo: OddReg, Flags: KillFlag)
581 .addImm(Val: 0);
582 return;
583 }
584
585 // Handle copy from csr
586 if (RISCV::VCSRRegClass.contains(Reg: SrcReg) &&
587 RISCV::GPRRegClass.contains(Reg: DstReg)) {
588 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: RISCV::CSRRS), DestReg: DstReg)
589 .addImm(Val: RISCVSysReg::lookupSysRegByName(Name: TRI->getName(RegNo: SrcReg))->Encoding)
590 .addReg(RegNo: RISCV::X0);
591 return;
592 }
593
594 if (RISCV::FPR16RegClass.contains(Reg1: DstReg, Reg2: SrcReg)) {
595 unsigned Opc;
596 if (STI.hasStdExtZfh()) {
597 Opc = RISCV::FSGNJ_H;
598 } else {
599 assert(STI.hasStdExtF() &&
600 (STI.hasStdExtZfhmin() || STI.hasStdExtZfbfmin()) &&
601 "Unexpected extensions");
602 // Zfhmin/Zfbfmin doesn't have FSGNJ_H, replace FSGNJ_H with FSGNJ_S.
603 DstReg = TRI->getMatchingSuperReg(Reg: DstReg, SubIdx: RISCV::sub_16,
604 RC: &RISCV::FPR32RegClass);
605 SrcReg = TRI->getMatchingSuperReg(Reg: SrcReg, SubIdx: RISCV::sub_16,
606 RC: &RISCV::FPR32RegClass);
607 Opc = RISCV::FSGNJ_S;
608 }
609 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: Opc), DestReg: DstReg)
610 .addReg(RegNo: SrcReg, Flags: KillFlag)
611 .addReg(RegNo: SrcReg, Flags: KillFlag);
612 return;
613 }
614
615 if (RISCV::FPR32RegClass.contains(Reg1: DstReg, Reg2: SrcReg)) {
616 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: RISCV::FSGNJ_S), DestReg: DstReg)
617 .addReg(RegNo: SrcReg, Flags: KillFlag)
618 .addReg(RegNo: SrcReg, Flags: KillFlag);
619 return;
620 }
621
622 if (RISCV::FPR64RegClass.contains(Reg1: DstReg, Reg2: SrcReg)) {
623 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: RISCV::FSGNJ_D), DestReg: DstReg)
624 .addReg(RegNo: SrcReg, Flags: KillFlag)
625 .addReg(RegNo: SrcReg, Flags: KillFlag);
626 return;
627 }
628
629 if (RISCV::FPR32RegClass.contains(Reg: DstReg) &&
630 RISCV::GPRRegClass.contains(Reg: SrcReg)) {
631 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: RISCV::FMV_W_X), DestReg: DstReg)
632 .addReg(RegNo: SrcReg, Flags: KillFlag);
633 return;
634 }
635
636 if (RISCV::GPRRegClass.contains(Reg: DstReg) &&
637 RISCV::FPR32RegClass.contains(Reg: SrcReg)) {
638 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: RISCV::FMV_X_W), DestReg: DstReg)
639 .addReg(RegNo: SrcReg, Flags: KillFlag);
640 return;
641 }
642
643 if (RISCV::FPR64RegClass.contains(Reg: DstReg) &&
644 RISCV::GPRRegClass.contains(Reg: SrcReg)) {
645 assert(STI.getXLen() == 64 && "Unexpected GPR size");
646 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: RISCV::FMV_D_X), DestReg: DstReg)
647 .addReg(RegNo: SrcReg, Flags: KillFlag);
648 return;
649 }
650
651 if (RISCV::GPRRegClass.contains(Reg: DstReg) &&
652 RISCV::FPR64RegClass.contains(Reg: SrcReg)) {
653 assert(STI.getXLen() == 64 && "Unexpected GPR size");
654 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: RISCV::FMV_X_D), DestReg: DstReg)
655 .addReg(RegNo: SrcReg, Flags: KillFlag);
656 return;
657 }
658
659 // VR->VR copies.
660 const TargetRegisterClass *RegClass =
661 TRI->getCommonMinimalPhysRegClass(Reg1: SrcReg, Reg2: DstReg);
662 if (RISCVRegisterInfo::isRVVRegClass(RC: RegClass)) {
663 copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RegClass);
664 return;
665 }
666
667 llvm_unreachable("Impossible reg-to-reg copy");
668}
669
670void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
671 MachineBasicBlock::iterator I,
672 Register SrcReg, bool IsKill, int FI,
673 const TargetRegisterClass *RC,
674 Register VReg,
675 MachineInstr::MIFlag Flags) const {
676 MachineFunction *MF = MBB.getParent();
677 MachineFrameInfo &MFI = MF->getFrameInfo();
678 Align Alignment = MFI.getObjectAlign(ObjectIdx: FI);
679
680 unsigned Opcode;
681 if (RISCV::GPRRegClass.hasSubClassEq(RC)) {
682 Opcode = RegInfo.getRegSizeInBits(RC: RISCV::GPRRegClass) == 32 ? RISCV::SW
683 : RISCV::SD;
684 } else if (RISCV::GPRF16RegClass.hasSubClassEq(RC)) {
685 Opcode = RISCV::SH_INX;
686 } else if (RISCV::GPRF32RegClass.hasSubClassEq(RC)) {
687 Opcode = RISCV::SW_INX;
688 } else if (RISCV::GPRPairRegClass.hasSubClassEq(RC)) {
689 if (!STI.is64Bit() && STI.hasStdExtZilsd() &&
690 Alignment >= STI.getZilsdAlign()) {
691 Opcode = RISCV::SD_RV32;
692 } else {
693 Opcode = RISCV::PseudoRV32ZdinxSD;
694 }
695 } else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) {
696 Opcode = RISCV::FSH;
697 } else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) {
698 Opcode = RISCV::FSW;
699 } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) {
700 Opcode = RISCV::FSD;
701 } else if (RISCV::VRRegClass.hasSubClassEq(RC)) {
702 Opcode = RISCV::VS1R_V;
703 } else if (RISCV::VRM2RegClass.hasSubClassEq(RC)) {
704 Opcode = RISCV::VS2R_V;
705 } else if (RISCV::VRM4RegClass.hasSubClassEq(RC)) {
706 Opcode = RISCV::VS4R_V;
707 } else if (RISCV::VRM8RegClass.hasSubClassEq(RC)) {
708 Opcode = RISCV::VS8R_V;
709 } else if (RISCV::VRN2M1RegClass.hasSubClassEq(RC))
710 Opcode = RISCV::PseudoVSPILL2_M1;
711 else if (RISCV::VRN2M2RegClass.hasSubClassEq(RC))
712 Opcode = RISCV::PseudoVSPILL2_M2;
713 else if (RISCV::VRN2M4RegClass.hasSubClassEq(RC))
714 Opcode = RISCV::PseudoVSPILL2_M4;
715 else if (RISCV::VRN3M1RegClass.hasSubClassEq(RC))
716 Opcode = RISCV::PseudoVSPILL3_M1;
717 else if (RISCV::VRN3M2RegClass.hasSubClassEq(RC))
718 Opcode = RISCV::PseudoVSPILL3_M2;
719 else if (RISCV::VRN4M1RegClass.hasSubClassEq(RC))
720 Opcode = RISCV::PseudoVSPILL4_M1;
721 else if (RISCV::VRN4M2RegClass.hasSubClassEq(RC))
722 Opcode = RISCV::PseudoVSPILL4_M2;
723 else if (RISCV::VRN5M1RegClass.hasSubClassEq(RC))
724 Opcode = RISCV::PseudoVSPILL5_M1;
725 else if (RISCV::VRN6M1RegClass.hasSubClassEq(RC))
726 Opcode = RISCV::PseudoVSPILL6_M1;
727 else if (RISCV::VRN7M1RegClass.hasSubClassEq(RC))
728 Opcode = RISCV::PseudoVSPILL7_M1;
729 else if (RISCV::VRN8M1RegClass.hasSubClassEq(RC))
730 Opcode = RISCV::PseudoVSPILL8_M1;
731 else
732 llvm_unreachable("Can't store this register to stack slot");
733
734 if (RISCVRegisterInfo::isRVVRegClass(RC)) {
735 MachineMemOperand *MMO = MF->getMachineMemOperand(
736 PtrInfo: MachinePointerInfo::getFixedStack(MF&: *MF, FI), F: MachineMemOperand::MOStore,
737 Size: TypeSize::getScalable(MinimumSize: MFI.getObjectSize(ObjectIdx: FI)), BaseAlignment: Alignment);
738
739 MFI.setStackID(ObjectIdx: FI, ID: TargetStackID::ScalableVector);
740 BuildMI(BB&: MBB, I, MIMD: DebugLoc(), MCID: get(Opcode))
741 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: IsKill))
742 .addFrameIndex(Idx: FI)
743 .addMemOperand(MMO)
744 .setMIFlag(Flags);
745 NumVRegSpilled += RegInfo.getRegSizeInBits(RC: *RC) / RISCV::RVVBitsPerBlock;
746 } else {
747 MachineMemOperand *MMO = MF->getMachineMemOperand(
748 PtrInfo: MachinePointerInfo::getFixedStack(MF&: *MF, FI), F: MachineMemOperand::MOStore,
749 Size: MFI.getObjectSize(ObjectIdx: FI), BaseAlignment: Alignment);
750
751 BuildMI(BB&: MBB, I, MIMD: DebugLoc(), MCID: get(Opcode))
752 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: IsKill))
753 .addFrameIndex(Idx: FI)
754 .addImm(Val: 0)
755 .addMemOperand(MMO)
756 .setMIFlag(Flags);
757 }
758}
759
760void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
761 MachineBasicBlock::iterator I,
762 Register DstReg, int FI,
763 const TargetRegisterClass *RC,
764 Register VReg, unsigned SubReg,
765 MachineInstr::MIFlag Flags) const {
766 MachineFunction *MF = MBB.getParent();
767 MachineFrameInfo &MFI = MF->getFrameInfo();
768 Align Alignment = MFI.getObjectAlign(ObjectIdx: FI);
769 DebugLoc DL =
770 Flags & MachineInstr::FrameDestroy ? MBB.findDebugLoc(MBBI: I) : DebugLoc();
771
772 unsigned Opcode;
773 if (RISCV::GPRRegClass.hasSubClassEq(RC)) {
774 Opcode = RegInfo.getRegSizeInBits(RC: RISCV::GPRRegClass) == 32 ? RISCV::LW
775 : RISCV::LD;
776 } else if (RISCV::GPRF16RegClass.hasSubClassEq(RC)) {
777 Opcode = RISCV::LH_INX;
778 } else if (RISCV::GPRF32RegClass.hasSubClassEq(RC)) {
779 Opcode = RISCV::LW_INX;
780 } else if (RISCV::GPRPairRegClass.hasSubClassEq(RC)) {
781 if (!STI.is64Bit() && STI.hasStdExtZilsd() &&
782 Alignment >= STI.getZilsdAlign()) {
783 Opcode = RISCV::LD_RV32;
784 } else {
785 Opcode = RISCV::PseudoRV32ZdinxLD;
786 }
787 } else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) {
788 Opcode = RISCV::FLH;
789 } else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) {
790 Opcode = RISCV::FLW;
791 } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) {
792 Opcode = RISCV::FLD;
793 } else if (RISCV::VRRegClass.hasSubClassEq(RC)) {
794 Opcode = RISCV::VL1RE8_V;
795 } else if (RISCV::VRM2RegClass.hasSubClassEq(RC)) {
796 Opcode = RISCV::VL2RE8_V;
797 } else if (RISCV::VRM4RegClass.hasSubClassEq(RC)) {
798 Opcode = RISCV::VL4RE8_V;
799 } else if (RISCV::VRM8RegClass.hasSubClassEq(RC)) {
800 Opcode = RISCV::VL8RE8_V;
801 } else if (RISCV::VRN2M1RegClass.hasSubClassEq(RC))
802 Opcode = RISCV::PseudoVRELOAD2_M1;
803 else if (RISCV::VRN2M2RegClass.hasSubClassEq(RC))
804 Opcode = RISCV::PseudoVRELOAD2_M2;
805 else if (RISCV::VRN2M4RegClass.hasSubClassEq(RC))
806 Opcode = RISCV::PseudoVRELOAD2_M4;
807 else if (RISCV::VRN3M1RegClass.hasSubClassEq(RC))
808 Opcode = RISCV::PseudoVRELOAD3_M1;
809 else if (RISCV::VRN3M2RegClass.hasSubClassEq(RC))
810 Opcode = RISCV::PseudoVRELOAD3_M2;
811 else if (RISCV::VRN4M1RegClass.hasSubClassEq(RC))
812 Opcode = RISCV::PseudoVRELOAD4_M1;
813 else if (RISCV::VRN4M2RegClass.hasSubClassEq(RC))
814 Opcode = RISCV::PseudoVRELOAD4_M2;
815 else if (RISCV::VRN5M1RegClass.hasSubClassEq(RC))
816 Opcode = RISCV::PseudoVRELOAD5_M1;
817 else if (RISCV::VRN6M1RegClass.hasSubClassEq(RC))
818 Opcode = RISCV::PseudoVRELOAD6_M1;
819 else if (RISCV::VRN7M1RegClass.hasSubClassEq(RC))
820 Opcode = RISCV::PseudoVRELOAD7_M1;
821 else if (RISCV::VRN8M1RegClass.hasSubClassEq(RC))
822 Opcode = RISCV::PseudoVRELOAD8_M1;
823 else
824 llvm_unreachable("Can't load this register from stack slot");
825
826 if (RISCVRegisterInfo::isRVVRegClass(RC)) {
827 MachineMemOperand *MMO = MF->getMachineMemOperand(
828 PtrInfo: MachinePointerInfo::getFixedStack(MF&: *MF, FI), F: MachineMemOperand::MOLoad,
829 Size: TypeSize::getScalable(MinimumSize: MFI.getObjectSize(ObjectIdx: FI)), BaseAlignment: Alignment);
830
831 MFI.setStackID(ObjectIdx: FI, ID: TargetStackID::ScalableVector);
832 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode), DestReg: DstReg)
833 .addFrameIndex(Idx: FI)
834 .addMemOperand(MMO)
835 .setMIFlag(Flags);
836 NumVRegReloaded += RegInfo.getRegSizeInBits(RC: *RC) / RISCV::RVVBitsPerBlock;
837 } else {
838 MachineMemOperand *MMO = MF->getMachineMemOperand(
839 PtrInfo: MachinePointerInfo::getFixedStack(MF&: *MF, FI), F: MachineMemOperand::MOLoad,
840 Size: MFI.getObjectSize(ObjectIdx: FI), BaseAlignment: Alignment);
841
842 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode), DestReg: DstReg)
843 .addFrameIndex(Idx: FI)
844 .addImm(Val: 0)
845 .addMemOperand(MMO)
846 .setMIFlag(Flags);
847 }
848}
849std::optional<unsigned> getFoldedOpcode(MachineFunction &MF, MachineInstr &MI,
850 ArrayRef<unsigned> Ops,
851 const RISCVSubtarget &ST) {
852
853 // The below optimizations narrow the load so they are only valid for little
854 // endian.
855 // TODO: Support big endian by adding an offset into the frame object?
856 if (MF.getDataLayout().isBigEndian())
857 return std::nullopt;
858
859 // Fold load from stack followed by sext.b/sext.h/sext.w/zext.b/zext.h/zext.w.
860 if (Ops.size() != 1 || Ops[0] != 1)
861 return std::nullopt;
862
863 switch (MI.getOpcode()) {
864 default:
865 if (RISCVInstrInfo::isSEXT_W(MI))
866 return RISCV::LW;
867 if (RISCVInstrInfo::isZEXT_W(MI))
868 return RISCV::LWU;
869 if (RISCVInstrInfo::isZEXT_B(MI))
870 return RISCV::LBU;
871 break;
872 case RISCV::SEXT_H:
873 return RISCV::LH;
874 case RISCV::SEXT_B:
875 return RISCV::LB;
876 case RISCV::ZEXT_H_RV32:
877 case RISCV::ZEXT_H_RV64:
878 return RISCV::LHU;
879 }
880
881 switch (RISCV::getRVVMCOpcode(RVVPseudoOpcode: MI.getOpcode())) {
882 default:
883 return std::nullopt;
884 case RISCV::VMV_X_S: {
885 unsigned Log2SEW =
886 MI.getOperand(i: RISCVII::getSEWOpNum(Desc: MI.getDesc())).getImm();
887 if (ST.getXLen() < (1U << Log2SEW))
888 return std::nullopt;
889 switch (Log2SEW) {
890 case 3:
891 return RISCV::LB;
892 case 4:
893 return RISCV::LH;
894 case 5:
895 return RISCV::LW;
896 case 6:
897 return RISCV::LD;
898 default:
899 llvm_unreachable("Unexpected SEW");
900 }
901 }
902 case RISCV::VFMV_F_S: {
903 unsigned Log2SEW =
904 MI.getOperand(i: RISCVII::getSEWOpNum(Desc: MI.getDesc())).getImm();
905 switch (Log2SEW) {
906 case 4:
907 return RISCV::FLH;
908 case 5:
909 return RISCV::FLW;
910 case 6:
911 return RISCV::FLD;
912 default:
913 llvm_unreachable("Unexpected SEW");
914 }
915 }
916 }
917}
918
919// This is the version used during InlineSpiller::spillAroundUses
920MachineInstr *
921RISCVInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
922 ArrayRef<unsigned> Ops, int FrameIndex,
923 MachineInstr *&CopyMI, LiveIntervals *LIS,
924 VirtRegMap *VRM) const {
925 MachineBasicBlock::iterator InsertPt = MI;
926 std::optional<unsigned> LoadOpc = getFoldedOpcode(MF, MI, Ops, ST: STI);
927 if (!LoadOpc)
928 return nullptr;
929 Register DstReg = MI.getOperand(i: 0).getReg();
930 return BuildMI(BB&: *MI.getParent(), I: InsertPt, MIMD: MI.getDebugLoc(), MCID: get(Opcode: *LoadOpc),
931 DestReg: DstReg)
932 .addFrameIndex(Idx: FrameIndex)
933 .addImm(Val: 0);
934}
935
936static unsigned getLoadPredicatedOpcode(unsigned Opcode) {
937 switch (Opcode) {
938 case RISCV::LB:
939 return RISCV::PseudoCCLB;
940 case RISCV::LBU:
941 return RISCV::PseudoCCLBU;
942 case RISCV::LH:
943 return RISCV::PseudoCCLH;
944 case RISCV::LHU:
945 return RISCV::PseudoCCLHU;
946 case RISCV::LW:
947 return RISCV::PseudoCCLW;
948 case RISCV::LWU:
949 return RISCV::PseudoCCLWU;
950 case RISCV::LD:
951 return RISCV::PseudoCCLD;
952 case RISCV::QC_E_LB:
953 return RISCV::PseudoCCQC_E_LB;
954 case RISCV::QC_E_LBU:
955 return RISCV::PseudoCCQC_E_LBU;
956 case RISCV::QC_E_LH:
957 return RISCV::PseudoCCQC_E_LH;
958 case RISCV::QC_E_LHU:
959 return RISCV::PseudoCCQC_E_LHU;
960 case RISCV::QC_E_LW:
961 return RISCV::PseudoCCQC_E_LW;
962 default:
963 return 0;
964 }
965}
966
967MachineInstr *RISCVInstrInfo::foldMemoryOperandImpl(
968 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
969 MachineInstr &LoadMI, MachineInstr *&CopyMI, LiveIntervals *LIS,
970 VirtRegMap *VRM) const {
971 MachineBasicBlock::iterator InsertPt = MI;
972 // For now, only handle RISCV::PseudoCCMOVGPR.
973 if (MI.getOpcode() != RISCV::PseudoCCMOVGPR)
974 return nullptr;
975
976 unsigned PredOpc = getLoadPredicatedOpcode(Opcode: LoadMI.getOpcode());
977
978 if (!STI.hasShortForwardBranchILoad() || !PredOpc)
979 return nullptr;
980
981 MachineRegisterInfo &MRI = MF.getRegInfo();
982 if (Ops.size() != 1 || (Ops[0] != 1 && Ops[0] != 2))
983 return nullptr;
984
985 bool Invert = Ops[0] == 2;
986 const MachineOperand &FalseReg = MI.getOperand(i: !Invert ? 2 : 1);
987 Register DestReg = MI.getOperand(i: 0).getReg();
988 const TargetRegisterClass *PreviousClass = MRI.getRegClass(Reg: FalseReg.getReg());
989 if (!MRI.constrainRegClass(Reg: DestReg, RC: PreviousClass))
990 return nullptr;
991
992 // Create a new predicated version of DefMI.
993 MachineInstrBuilder NewMI = BuildMI(BB&: *MI.getParent(), I: InsertPt,
994 MIMD: MI.getDebugLoc(), MCID: get(Opcode: PredOpc), DestReg);
995
996 // Copy the false register.
997 NewMI.add(MO: FalseReg);
998
999 // Copy all the DefMI operands.
1000 const MCInstrDesc &DefDesc = LoadMI.getDesc();
1001 for (unsigned i = 1, e = DefDesc.getNumOperands(); i != e; ++i)
1002 NewMI.add(MO: LoadMI.getOperand(i));
1003
1004 // Add branch opcode, inverting if necessary.
1005 unsigned BCC = MI.getOperand(i: MI.getNumExplicitOperands() - 3).getImm();
1006 if (!Invert)
1007 BCC = RISCVCC::getInverseBranchOpcode(BCC);
1008 NewMI.addImm(Val: BCC);
1009
1010 // Copy condition portion
1011 NewMI.add(MOs: {MI.getOperand(i: MI.getNumExplicitOperands() - 2),
1012 MI.getOperand(i: MI.getNumExplicitOperands() - 1)});
1013 NewMI.cloneMemRefs(OtherMI: LoadMI);
1014 return NewMI;
1015}
1016
1017void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
1018 MachineBasicBlock::iterator MBBI,
1019 const DebugLoc &DL, Register DstReg, uint64_t Val,
1020 MachineInstr::MIFlag Flag, bool DstRenamable,
1021 bool DstIsDead) const {
1022 Register SrcReg = RISCV::X0;
1023
1024 // For RV32, allow a sign or unsigned 32 bit value.
1025 if (!STI.is64Bit() && !isInt<32>(x: Val)) {
1026 // If have a uimm32 it will still fit in a register so we can allow it.
1027 if (!isUInt<32>(x: Val))
1028 report_fatal_error(reason: "Should only materialize 32-bit constants for RV32");
1029
1030 // Sign extend for generateInstSeq.
1031 Val = SignExtend64<32>(x: Val);
1032 }
1033
1034 RISCVMatInt::InstSeq Seq = RISCVMatInt::generateInstSeq(Val, STI);
1035 assert(!Seq.empty());
1036
1037 bool SrcRenamable = false;
1038 unsigned Num = 0;
1039
1040 for (const RISCVMatInt::Inst &Inst : Seq) {
1041 bool LastItem = ++Num == Seq.size();
1042 RegState DstRegState = getDeadRegState(B: DstIsDead && LastItem) |
1043 getRenamableRegState(B: DstRenamable);
1044 RegState SrcRegState = getKillRegState(B: SrcReg != RISCV::X0) |
1045 getRenamableRegState(B: SrcRenamable);
1046 switch (Inst.getOpndKind()) {
1047 case RISCVMatInt::Imm:
1048 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: Inst.getOpcode()))
1049 .addReg(RegNo: DstReg, Flags: RegState::Define | DstRegState)
1050 .addImm(Val: Inst.getImm())
1051 .setMIFlag(Flag);
1052 break;
1053 case RISCVMatInt::RegX0:
1054 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: Inst.getOpcode()))
1055 .addReg(RegNo: DstReg, Flags: RegState::Define | DstRegState)
1056 .addReg(RegNo: SrcReg, Flags: SrcRegState)
1057 .addReg(RegNo: RISCV::X0)
1058 .setMIFlag(Flag);
1059 break;
1060 case RISCVMatInt::RegReg:
1061 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: Inst.getOpcode()))
1062 .addReg(RegNo: DstReg, Flags: RegState::Define | DstRegState)
1063 .addReg(RegNo: SrcReg, Flags: SrcRegState)
1064 .addReg(RegNo: SrcReg, Flags: SrcRegState)
1065 .setMIFlag(Flag);
1066 break;
1067 case RISCVMatInt::RegImm:
1068 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: get(Opcode: Inst.getOpcode()))
1069 .addReg(RegNo: DstReg, Flags: RegState::Define | DstRegState)
1070 .addReg(RegNo: SrcReg, Flags: SrcRegState)
1071 .addImm(Val: Inst.getImm())
1072 .setMIFlag(Flag);
1073 break;
1074 }
1075
1076 // Only the first instruction has X0 as its source.
1077 SrcReg = DstReg;
1078 SrcRenamable = DstRenamable;
1079 }
1080}
1081
1082RISCVCC::CondCode RISCVInstrInfo::getCondFromBranchOpc(unsigned Opc) {
1083 switch (Opc) {
1084 default:
1085 return RISCVCC::COND_INVALID;
1086 case RISCV::BEQ:
1087 case RISCV::BEQI:
1088 case RISCV::CV_BEQIMM:
1089 case RISCV::QC_BEQI:
1090 case RISCV::QC_E_BEQI:
1091 case RISCV::NDS_BBC:
1092 case RISCV::NDS_BEQC:
1093 return RISCVCC::COND_EQ;
1094 case RISCV::BNE:
1095 case RISCV::BNEI:
1096 case RISCV::QC_BNEI:
1097 case RISCV::QC_E_BNEI:
1098 case RISCV::CV_BNEIMM:
1099 case RISCV::NDS_BBS:
1100 case RISCV::NDS_BNEC:
1101 return RISCVCC::COND_NE;
1102 case RISCV::BLT:
1103 case RISCV::QC_BLTI:
1104 case RISCV::QC_E_BLTI:
1105 return RISCVCC::COND_LT;
1106 case RISCV::BGE:
1107 case RISCV::QC_BGEI:
1108 case RISCV::QC_E_BGEI:
1109 return RISCVCC::COND_GE;
1110 case RISCV::BLTU:
1111 case RISCV::QC_BLTUI:
1112 case RISCV::QC_E_BLTUI:
1113 return RISCVCC::COND_LTU;
1114 case RISCV::BGEU:
1115 case RISCV::QC_BGEUI:
1116 case RISCV::QC_E_BGEUI:
1117 return RISCVCC::COND_GEU;
1118 }
1119}
1120
1121bool RISCVInstrInfo::evaluateCondBranch(RISCVCC::CondCode CC, int64_t C0,
1122 int64_t C1) {
1123 switch (CC) {
1124 default:
1125 llvm_unreachable("Unexpected CC");
1126 case RISCVCC::COND_EQ:
1127 return C0 == C1;
1128 case RISCVCC::COND_NE:
1129 return C0 != C1;
1130 case RISCVCC::COND_LT:
1131 return C0 < C1;
1132 case RISCVCC::COND_GE:
1133 return C0 >= C1;
1134 case RISCVCC::COND_LTU:
1135 return (uint64_t)C0 < (uint64_t)C1;
1136 case RISCVCC::COND_GEU:
1137 return (uint64_t)C0 >= (uint64_t)C1;
1138 }
1139}
1140
1141// The contents of values added to Cond are not examined outside of
1142// RISCVInstrInfo, giving us flexibility in what to push to it. For RISCV, we
1143// push BranchOpcode, Reg1, Reg2.
1144static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
1145 SmallVectorImpl<MachineOperand> &Cond) {
1146 // Block ends with fall-through condbranch.
1147 assert(LastInst.getDesc().isConditionalBranch() &&
1148 "Unknown conditional branch");
1149 Target = LastInst.getOperand(i: 2).getMBB();
1150 Cond.push_back(Elt: MachineOperand::CreateImm(Val: LastInst.getOpcode()));
1151 Cond.push_back(Elt: LastInst.getOperand(i: 0));
1152 Cond.push_back(Elt: LastInst.getOperand(i: 1));
1153}
1154
1155static unsigned getInverseXqcicmOpcode(unsigned Opcode) {
1156 switch (Opcode) {
1157 default:
1158 llvm_unreachable("Unexpected Opcode");
1159 case RISCV::QC_MVEQ:
1160 return RISCV::QC_MVNE;
1161 case RISCV::QC_MVNE:
1162 return RISCV::QC_MVEQ;
1163 case RISCV::QC_MVLT:
1164 return RISCV::QC_MVGE;
1165 case RISCV::QC_MVGE:
1166 return RISCV::QC_MVLT;
1167 case RISCV::QC_MVLTU:
1168 return RISCV::QC_MVGEU;
1169 case RISCV::QC_MVGEU:
1170 return RISCV::QC_MVLTU;
1171 case RISCV::QC_MVEQI:
1172 return RISCV::QC_MVNEI;
1173 case RISCV::QC_MVNEI:
1174 return RISCV::QC_MVEQI;
1175 case RISCV::QC_MVLTI:
1176 return RISCV::QC_MVGEI;
1177 case RISCV::QC_MVGEI:
1178 return RISCV::QC_MVLTI;
1179 case RISCV::QC_MVLTUI:
1180 return RISCV::QC_MVGEUI;
1181 case RISCV::QC_MVGEUI:
1182 return RISCV::QC_MVLTUI;
1183 }
1184}
1185
1186unsigned RISCVCC::getBrCond(RISCVCC::CondCode CC, unsigned SelectOpc) {
1187 switch (SelectOpc) {
1188 default:
1189 switch (CC) {
1190 default:
1191 llvm_unreachable("Unexpected condition code!");
1192 case RISCVCC::COND_EQ:
1193 return RISCV::BEQ;
1194 case RISCVCC::COND_NE:
1195 return RISCV::BNE;
1196 case RISCVCC::COND_LT:
1197 return RISCV::BLT;
1198 case RISCVCC::COND_GE:
1199 return RISCV::BGE;
1200 case RISCVCC::COND_LTU:
1201 return RISCV::BLTU;
1202 case RISCVCC::COND_GEU:
1203 return RISCV::BGEU;
1204 }
1205 break;
1206 case RISCV::Select_GPR_Using_CC_Imm5_Zibi:
1207 switch (CC) {
1208 default:
1209 llvm_unreachable("Unexpected condition code!");
1210 case RISCVCC::COND_EQ:
1211 return RISCV::BEQI;
1212 case RISCVCC::COND_NE:
1213 return RISCV::BNEI;
1214 }
1215 break;
1216 case RISCV::Select_GPR_Using_CC_SImm5_CV:
1217 switch (CC) {
1218 default:
1219 llvm_unreachable("Unexpected condition code!");
1220 case RISCVCC::COND_EQ:
1221 return RISCV::CV_BEQIMM;
1222 case RISCVCC::COND_NE:
1223 return RISCV::CV_BNEIMM;
1224 }
1225 break;
1226 case RISCV::Select_GPRNoX0_Using_CC_SImm5NonZero_QC:
1227 switch (CC) {
1228 default:
1229 llvm_unreachable("Unexpected condition code!");
1230 case RISCVCC::COND_EQ:
1231 return RISCV::QC_BEQI;
1232 case RISCVCC::COND_NE:
1233 return RISCV::QC_BNEI;
1234 case RISCVCC::COND_LT:
1235 return RISCV::QC_BLTI;
1236 case RISCVCC::COND_GE:
1237 return RISCV::QC_BGEI;
1238 }
1239 break;
1240 case RISCV::Select_GPRNoX0_Using_CC_UImm5NonZero_QC:
1241 switch (CC) {
1242 default:
1243 llvm_unreachable("Unexpected condition code!");
1244 case RISCVCC::COND_LTU:
1245 return RISCV::QC_BLTUI;
1246 case RISCVCC::COND_GEU:
1247 return RISCV::QC_BGEUI;
1248 }
1249 break;
1250 case RISCV::Select_GPRNoX0_Using_CC_SImm16NonZero_QC:
1251 switch (CC) {
1252 default:
1253 llvm_unreachable("Unexpected condition code!");
1254 case RISCVCC::COND_EQ:
1255 return RISCV::QC_E_BEQI;
1256 case RISCVCC::COND_NE:
1257 return RISCV::QC_E_BNEI;
1258 case RISCVCC::COND_LT:
1259 return RISCV::QC_E_BLTI;
1260 case RISCVCC::COND_GE:
1261 return RISCV::QC_E_BGEI;
1262 }
1263 break;
1264 case RISCV::Select_GPRNoX0_Using_CC_UImm16NonZero_QC:
1265 switch (CC) {
1266 default:
1267 llvm_unreachable("Unexpected condition code!");
1268 case RISCVCC::COND_LTU:
1269 return RISCV::QC_E_BLTUI;
1270 case RISCVCC::COND_GEU:
1271 return RISCV::QC_E_BGEUI;
1272 }
1273 break;
1274 case RISCV::Select_GPR_Using_CC_UImmLog2XLen_NDS:
1275 switch (CC) {
1276 default:
1277 llvm_unreachable("Unexpected condition code!");
1278 case RISCVCC::COND_EQ:
1279 return RISCV::NDS_BBC;
1280 case RISCVCC::COND_NE:
1281 return RISCV::NDS_BBS;
1282 }
1283 break;
1284 case RISCV::Select_GPR_Using_CC_UImm7_NDS:
1285 switch (CC) {
1286 default:
1287 llvm_unreachable("Unexpected condition code!");
1288 case RISCVCC::COND_EQ:
1289 return RISCV::NDS_BEQC;
1290 case RISCVCC::COND_NE:
1291 return RISCV::NDS_BNEC;
1292 }
1293 break;
1294 }
1295}
1296
1297RISCVCC::CondCode RISCVCC::getInverseBranchCondition(RISCVCC::CondCode CC) {
1298 switch (CC) {
1299 default:
1300 llvm_unreachable("Unrecognized conditional branch");
1301 case RISCVCC::COND_EQ:
1302 return RISCVCC::COND_NE;
1303 case RISCVCC::COND_NE:
1304 return RISCVCC::COND_EQ;
1305 case RISCVCC::COND_LT:
1306 return RISCVCC::COND_GE;
1307 case RISCVCC::COND_GE:
1308 return RISCVCC::COND_LT;
1309 case RISCVCC::COND_LTU:
1310 return RISCVCC::COND_GEU;
1311 case RISCVCC::COND_GEU:
1312 return RISCVCC::COND_LTU;
1313 }
1314}
1315
1316// Return inverse branch
1317unsigned RISCVCC::getInverseBranchOpcode(unsigned BCC) {
1318 switch (BCC) {
1319 default:
1320 llvm_unreachable("Unexpected branch opcode!");
1321 case RISCV::BEQ:
1322 return RISCV::BNE;
1323 case RISCV::BEQI:
1324 return RISCV::BNEI;
1325 case RISCV::BNE:
1326 return RISCV::BEQ;
1327 case RISCV::BNEI:
1328 return RISCV::BEQI;
1329 case RISCV::BLT:
1330 return RISCV::BGE;
1331 case RISCV::BGE:
1332 return RISCV::BLT;
1333 case RISCV::BLTU:
1334 return RISCV::BGEU;
1335 case RISCV::BGEU:
1336 return RISCV::BLTU;
1337 case RISCV::CV_BEQIMM:
1338 return RISCV::CV_BNEIMM;
1339 case RISCV::CV_BNEIMM:
1340 return RISCV::CV_BEQIMM;
1341 case RISCV::QC_BEQI:
1342 return RISCV::QC_BNEI;
1343 case RISCV::QC_BNEI:
1344 return RISCV::QC_BEQI;
1345 case RISCV::QC_BLTI:
1346 return RISCV::QC_BGEI;
1347 case RISCV::QC_BGEI:
1348 return RISCV::QC_BLTI;
1349 case RISCV::QC_BLTUI:
1350 return RISCV::QC_BGEUI;
1351 case RISCV::QC_BGEUI:
1352 return RISCV::QC_BLTUI;
1353 case RISCV::QC_E_BEQI:
1354 return RISCV::QC_E_BNEI;
1355 case RISCV::QC_E_BNEI:
1356 return RISCV::QC_E_BEQI;
1357 case RISCV::QC_E_BLTI:
1358 return RISCV::QC_E_BGEI;
1359 case RISCV::QC_E_BGEI:
1360 return RISCV::QC_E_BLTI;
1361 case RISCV::QC_E_BLTUI:
1362 return RISCV::QC_E_BGEUI;
1363 case RISCV::QC_E_BGEUI:
1364 return RISCV::QC_E_BLTUI;
1365 case RISCV::NDS_BBC:
1366 return RISCV::NDS_BBS;
1367 case RISCV::NDS_BBS:
1368 return RISCV::NDS_BBC;
1369 case RISCV::NDS_BEQC:
1370 return RISCV::NDS_BNEC;
1371 case RISCV::NDS_BNEC:
1372 return RISCV::NDS_BEQC;
1373 }
1374}
1375
1376bool RISCVInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
1377 MachineBasicBlock *&TBB,
1378 MachineBasicBlock *&FBB,
1379 SmallVectorImpl<MachineOperand> &Cond,
1380 bool AllowModify) const {
1381 TBB = FBB = nullptr;
1382 Cond.clear();
1383
1384 // If the block has no terminators, it just falls into the block after it.
1385 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
1386 if (I == MBB.end() || !isUnpredicatedTerminator(MI: *I))
1387 return false;
1388
1389 // Count the number of terminators and find the first unconditional or
1390 // indirect branch.
1391 MachineBasicBlock::iterator FirstUncondOrIndirectBr = MBB.end();
1392 int NumTerminators = 0;
1393 for (auto J = I.getReverse(); J != MBB.rend() && isUnpredicatedTerminator(MI: *J);
1394 J++) {
1395 NumTerminators++;
1396 if (J->getDesc().isUnconditionalBranch() ||
1397 J->getDesc().isIndirectBranch()) {
1398 FirstUncondOrIndirectBr = J.getReverse();
1399 }
1400 }
1401
1402 // If AllowModify is true, we can erase any terminators after
1403 // FirstUncondOrIndirectBR.
1404 if (AllowModify && FirstUncondOrIndirectBr != MBB.end()) {
1405 while (std::next(x: FirstUncondOrIndirectBr) != MBB.end()) {
1406 std::next(x: FirstUncondOrIndirectBr)->eraseFromParent();
1407 NumTerminators--;
1408 }
1409 I = FirstUncondOrIndirectBr;
1410 }
1411
1412 // We can't handle blocks that end in an indirect branch.
1413 if (I->getDesc().isIndirectBranch())
1414 return true;
1415
1416 // We can't handle Generic branch opcodes from Global ISel.
1417 if (I->isPreISelOpcode())
1418 return true;
1419
1420 // We can't handle blocks with more than 2 terminators.
1421 if (NumTerminators > 2)
1422 return true;
1423
1424 // Handle a single unconditional branch.
1425 if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) {
1426 TBB = getBranchDestBlock(MI: *I);
1427 return false;
1428 }
1429
1430 // Handle a single conditional branch.
1431 if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) {
1432 parseCondBranch(LastInst&: *I, Target&: TBB, Cond);
1433 return false;
1434 }
1435
1436 // Handle a conditional branch followed by an unconditional branch.
1437 if (NumTerminators == 2 && std::prev(x: I)->getDesc().isConditionalBranch() &&
1438 I->getDesc().isUnconditionalBranch()) {
1439 parseCondBranch(LastInst&: *std::prev(x: I), Target&: TBB, Cond);
1440 FBB = getBranchDestBlock(MI: *I);
1441 return false;
1442 }
1443
1444 // Otherwise, we can't handle this.
1445 return true;
1446}
1447
1448unsigned RISCVInstrInfo::removeBranch(MachineBasicBlock &MBB,
1449 int *BytesRemoved) const {
1450 if (BytesRemoved)
1451 *BytesRemoved = 0;
1452 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
1453 if (I == MBB.end())
1454 return 0;
1455
1456 if (!I->getDesc().isUnconditionalBranch() &&
1457 !I->getDesc().isConditionalBranch())
1458 return 0;
1459
1460 // Remove the branch.
1461 if (BytesRemoved)
1462 *BytesRemoved += getInstSizeInBytes(MI: *I);
1463 I->eraseFromParent();
1464
1465 I = MBB.end();
1466
1467 if (I == MBB.begin())
1468 return 1;
1469 --I;
1470 if (!I->getDesc().isConditionalBranch())
1471 return 1;
1472
1473 // Remove the branch.
1474 if (BytesRemoved)
1475 *BytesRemoved += getInstSizeInBytes(MI: *I);
1476 I->eraseFromParent();
1477 return 2;
1478}
1479
1480// Inserts a branch into the end of the specific MachineBasicBlock, returning
1481// the number of instructions inserted.
1482unsigned RISCVInstrInfo::insertBranch(
1483 MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
1484 ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
1485 if (BytesAdded)
1486 *BytesAdded = 0;
1487
1488 // Shouldn't be a fall through.
1489 assert(TBB && "insertBranch must not be told to insert a fallthrough");
1490 assert((Cond.size() == 3 || Cond.size() == 0) &&
1491 "RISC-V branch conditions have two components!");
1492
1493 // Unconditional branch.
1494 if (Cond.empty()) {
1495 MachineInstr &MI = *BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: RISCV::PseudoBR)).addMBB(MBB: TBB);
1496 if (BytesAdded)
1497 *BytesAdded += getInstSizeInBytes(MI);
1498 return 1;
1499 }
1500
1501 // Either a one or two-way conditional branch.
1502 MachineInstr &CondMI = *BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: Cond[0].getImm()))
1503 .add(MO: Cond[1])
1504 .add(MO: Cond[2])
1505 .addMBB(MBB: TBB);
1506 if (BytesAdded)
1507 *BytesAdded += getInstSizeInBytes(MI: CondMI);
1508
1509 // One-way conditional branch.
1510 if (!FBB)
1511 return 1;
1512
1513 // Two-way conditional branch.
1514 MachineInstr &MI = *BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: RISCV::PseudoBR)).addMBB(MBB: FBB);
1515 if (BytesAdded)
1516 *BytesAdded += getInstSizeInBytes(MI);
1517 return 2;
1518}
1519
1520void RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
1521 MachineBasicBlock &DestBB,
1522 MachineBasicBlock &RestoreBB,
1523 const DebugLoc &DL, int64_t BrOffset,
1524 RegScavenger *RS) const {
1525 assert(RS && "RegScavenger required for long branching");
1526 assert(MBB.empty() &&
1527 "new block should be inserted for expanding unconditional branch");
1528 assert(MBB.pred_size() == 1);
1529 assert(RestoreBB.empty() &&
1530 "restore block should be inserted for restoring clobbered registers");
1531
1532 MachineFunction *MF = MBB.getParent();
1533 MachineRegisterInfo &MRI = MF->getRegInfo();
1534 RISCVMachineFunctionInfo *RVFI = MF->getInfo<RISCVMachineFunctionInfo>();
1535 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
1536
1537 if (!isInt<32>(x: BrOffset))
1538 report_fatal_error(
1539 reason: "Branch offsets outside of the signed 32-bit range not supported");
1540
1541 // FIXME: A virtual register must be used initially, as the register
1542 // scavenger won't work with empty blocks (SIInstrInfo::insertIndirectBranch
1543 // uses the same workaround).
1544 Register ScratchReg = MRI.createVirtualRegister(RegClass: &RISCV::GPRJALRRegClass);
1545 auto II = MBB.end();
1546 // We may also update the jump target to RestoreBB later.
1547 MachineInstr &MI = *BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: get(Opcode: RISCV::PseudoJump))
1548 .addReg(RegNo: ScratchReg, Flags: RegState::Define | RegState::Dead)
1549 .addMBB(MBB: &DestBB, TargetFlags: RISCVII::MO_CALL);
1550
1551 RS->enterBasicBlockEnd(MBB);
1552 // When cf-protection-branch is enabled, we must use t2 (x7) for software
1553 // guarded branches to hold the landing pad label.
1554 bool HasCFBranch =
1555 MF->getInfo<RISCVMachineFunctionInfo>()->hasCFProtectionBranch();
1556 const TargetRegisterClass *RC = &RISCV::GPRRegClass;
1557 if (HasCFBranch)
1558 RC = &RISCV::GPRX7RegClass;
1559 Register TmpGPR =
1560 RS->scavengeRegisterBackwards(RC: *RC, To: MI.getIterator(),
1561 /*RestoreAfter=*/false, /*SpAdj=*/SPAdj: 0,
1562 /*AllowSpill=*/false);
1563 if (TmpGPR.isValid())
1564 RS->setRegUsed(Reg: TmpGPR);
1565 else {
1566 // The case when there is no scavenged register needs special handling.
1567
1568 // Pick s11(or s1 for rve) because it doesn't make a difference.
1569 TmpGPR = STI.hasStdExtE() ? RISCV::X9 : RISCV::X27;
1570 // Force t2 if cf-protection-branch is enabled
1571 if (HasCFBranch)
1572 TmpGPR = RISCV::X7;
1573
1574 int FrameIndex = RVFI->getBranchRelaxationScratchFrameIndex();
1575 if (FrameIndex == -1)
1576 report_fatal_error(reason: "underestimated function size");
1577
1578 storeRegToStackSlot(MBB, I: MI, SrcReg: TmpGPR, /*IsKill=*/true, FI: FrameIndex,
1579 RC: &RISCV::GPRRegClass, VReg: Register());
1580 TRI->eliminateFrameIndex(MI: std::prev(x: MI.getIterator()),
1581 /*SpAdj=*/SPAdj: 0, /*FIOperandNum=*/1);
1582
1583 MI.getOperand(i: 1).setMBB(&RestoreBB);
1584
1585 loadRegFromStackSlot(MBB&: RestoreBB, I: RestoreBB.end(), DstReg: TmpGPR, FI: FrameIndex,
1586 RC: &RISCV::GPRRegClass, VReg: Register());
1587 TRI->eliminateFrameIndex(MI: RestoreBB.back(),
1588 /*SpAdj=*/SPAdj: 0, /*FIOperandNum=*/1);
1589 }
1590
1591 MRI.replaceRegWith(FromReg: ScratchReg, ToReg: TmpGPR);
1592 MRI.clearVirtRegs();
1593}
1594
1595bool RISCVInstrInfo::reverseBranchCondition(
1596 SmallVectorImpl<MachineOperand> &Cond) const {
1597 assert((Cond.size() == 3) && "Invalid branch condition!");
1598
1599 Cond[0].setImm(RISCVCC::getInverseBranchOpcode(BCC: Cond[0].getImm()));
1600
1601 return false;
1602}
1603
1604// Return true if the instruction is a load immediate instruction (i.e.
1605// (ADDI x0, imm) or (BSETI x0, imm)).
1606static bool isLoadImm(const MachineInstr *MI, int64_t &Imm) {
1607 if (MI->getOpcode() == RISCV::ADDI && MI->getOperand(i: 1).isReg() &&
1608 MI->getOperand(i: 1).getReg() == RISCV::X0) {
1609 Imm = MI->getOperand(i: 2).getImm();
1610 return true;
1611 }
1612 // BSETI can be used to create power of 2 constants. Only 2048 is currently
1613 // interesting because it is 1 more than the maximum ADDI constant.
1614 if (MI->getOpcode() == RISCV::BSETI && MI->getOperand(i: 1).isReg() &&
1615 MI->getOperand(i: 1).getReg() == RISCV::X0 &&
1616 MI->getOperand(i: 2).getImm() == 11) {
1617 Imm = 2048;
1618 return true;
1619 }
1620 return false;
1621}
1622
1623bool RISCVInstrInfo::isFromLoadImm(const MachineRegisterInfo &MRI,
1624 const MachineOperand &Op, int64_t &Imm) {
1625 // Either a load from immediate instruction or X0.
1626 if (!Op.isReg())
1627 return false;
1628
1629 Register Reg = Op.getReg();
1630 if (Reg == RISCV::X0) {
1631 Imm = 0;
1632 return true;
1633 }
1634 return Reg.isVirtual() && isLoadImm(MI: MRI.getVRegDef(Reg), Imm);
1635}
1636
1637bool RISCVInstrInfo::optimizeCondBranch(MachineInstr &MI) const {
1638 bool IsSigned = false;
1639 bool IsEquality = false;
1640 switch (MI.getOpcode()) {
1641 default:
1642 return false;
1643 case RISCV::BEQ:
1644 case RISCV::BNE:
1645 IsEquality = true;
1646 break;
1647 case RISCV::BGE:
1648 case RISCV::BLT:
1649 IsSigned = true;
1650 break;
1651 case RISCV::BGEU:
1652 case RISCV::BLTU:
1653 break;
1654 }
1655
1656 MachineBasicBlock *MBB = MI.getParent();
1657 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
1658
1659 const MachineOperand &LHS = MI.getOperand(i: 0);
1660 const MachineOperand &RHS = MI.getOperand(i: 1);
1661 MachineBasicBlock *TBB = MI.getOperand(i: 2).getMBB();
1662
1663 RISCVCC::CondCode CC = getCondFromBranchOpc(Opc: MI.getOpcode());
1664 assert(CC != RISCVCC::COND_INVALID);
1665
1666 // Canonicalize conditional branches which can be constant folded into
1667 // beqz or bnez. We can't modify the CFG here.
1668 int64_t C0, C1;
1669 if (isFromLoadImm(MRI, Op: LHS, Imm&: C0) && isFromLoadImm(MRI, Op: RHS, Imm&: C1)) {
1670 unsigned NewOpc = evaluateCondBranch(CC, C0, C1) ? RISCV::BEQ : RISCV::BNE;
1671 // Build the new branch and remove the old one.
1672 BuildMI(BB&: *MBB, I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: NewOpc))
1673 .addReg(RegNo: RISCV::X0)
1674 .addReg(RegNo: RISCV::X0)
1675 .addMBB(MBB: TBB);
1676 MI.eraseFromParent();
1677 return true;
1678 }
1679
1680 if (IsEquality)
1681 return false;
1682
1683 // For two constants C0 and C1 from
1684 // ```
1685 // li Y, C0
1686 // li Z, C1
1687 // ```
1688 // 1. if C1 = C0 + 1
1689 // we can turn:
1690 // (a) blt Y, X -> bge X, Z
1691 // (b) bge Y, X -> blt X, Z
1692 //
1693 // 2. if C1 = C0 - 1
1694 // we can turn:
1695 // (a) blt X, Y -> bge Z, X
1696 // (b) bge X, Y -> blt Z, X
1697 //
1698 // To make sure this optimization is really beneficial, we only
1699 // optimize for cases where Y had only one use (i.e. only used by the branch).
1700 // Try to find the register for constant Z; return
1701 // invalid register otherwise.
1702 auto searchConst = [&](int64_t C1) -> Register {
1703 MachineBasicBlock::reverse_iterator II(&MI), E = MBB->rend();
1704 auto DefC1 = std::find_if(first: ++II, last: E, pred: [&](const MachineInstr &I) -> bool {
1705 int64_t Imm;
1706 return isLoadImm(MI: &I, Imm) && Imm == C1 &&
1707 I.getOperand(i: 0).getReg().isVirtual();
1708 });
1709 if (DefC1 != E)
1710 return DefC1->getOperand(i: 0).getReg();
1711
1712 return Register();
1713 };
1714
1715 unsigned NewOpc = RISCVCC::getBrCond(CC: getInverseBranchCondition(CC));
1716
1717 // Might be case 1.
1718 // Don't change 0 to 1 since we can use x0.
1719 // For unsigned cases changing -1U to 0 would be incorrect.
1720 // The incorrect case for signed would be INT_MAX, but isFromLoadImm can't
1721 // return that.
1722 if (isFromLoadImm(MRI, Op: LHS, Imm&: C0) && C0 != 0 && LHS.getReg().isVirtual() &&
1723 MRI.hasOneUse(RegNo: LHS.getReg()) && (IsSigned || C0 != -1)) {
1724 assert((isInt<12>(C0) || C0 == 2048) && "Unexpected immediate");
1725 if (Register RegZ = searchConst(C0 + 1)) {
1726 BuildMI(BB&: *MBB, I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: NewOpc))
1727 .add(MO: RHS)
1728 .addReg(RegNo: RegZ)
1729 .addMBB(MBB: TBB);
1730 // We might extend the live range of Z, clear its kill flag to
1731 // account for this.
1732 MRI.clearKillFlags(Reg: RegZ);
1733 MI.eraseFromParent();
1734 return true;
1735 }
1736 }
1737
1738 // Might be case 2.
1739 // For signed cases we don't want to change 0 since we can use x0.
1740 // For unsigned cases changing 0 to -1U would be incorrect.
1741 // The incorrect case for signed would be INT_MIN, but isFromLoadImm can't
1742 // return that.
1743 if (isFromLoadImm(MRI, Op: RHS, Imm&: C0) && C0 != 0 && RHS.getReg().isVirtual() &&
1744 MRI.hasOneUse(RegNo: RHS.getReg())) {
1745 assert((isInt<12>(C0) || C0 == 2048) && "Unexpected immediate");
1746 if (Register RegZ = searchConst(C0 - 1)) {
1747 BuildMI(BB&: *MBB, I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: NewOpc))
1748 .addReg(RegNo: RegZ)
1749 .add(MO: LHS)
1750 .addMBB(MBB: TBB);
1751 // We might extend the live range of Z, clear its kill flag to
1752 // account for this.
1753 MRI.clearKillFlags(Reg: RegZ);
1754 MI.eraseFromParent();
1755 return true;
1756 }
1757 }
1758
1759 return false;
1760}
1761
1762MachineBasicBlock *
1763RISCVInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
1764 assert(MI.getDesc().isBranch() && "Unexpected opcode!");
1765 // The branch target is always the last operand.
1766 int NumOp = MI.getNumExplicitOperands();
1767 return MI.getOperand(i: NumOp - 1).getMBB();
1768}
1769
1770bool RISCVInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
1771 int64_t BrOffset) const {
1772 unsigned XLen = STI.getXLen();
1773 // Ideally we could determine the supported branch offset from the
1774 // RISCVII::FormMask, but this can't be used for Pseudo instructions like
1775 // PseudoBR.
1776 switch (BranchOp) {
1777 default:
1778 llvm_unreachable("Unexpected opcode!");
1779 case RISCV::NDS_BBC:
1780 case RISCV::NDS_BBS:
1781 case RISCV::NDS_BEQC:
1782 case RISCV::NDS_BNEC:
1783 return isInt<11>(x: BrOffset);
1784 case RISCV::BEQ:
1785 case RISCV::BNE:
1786 case RISCV::BLT:
1787 case RISCV::BGE:
1788 case RISCV::BLTU:
1789 case RISCV::BGEU:
1790 case RISCV::BEQI:
1791 case RISCV::BNEI:
1792 case RISCV::CV_BEQIMM:
1793 case RISCV::CV_BNEIMM:
1794 case RISCV::QC_BEQI:
1795 case RISCV::QC_BNEI:
1796 case RISCV::QC_BGEI:
1797 case RISCV::QC_BLTI:
1798 case RISCV::QC_BLTUI:
1799 case RISCV::QC_BGEUI:
1800 case RISCV::QC_E_BEQI:
1801 case RISCV::QC_E_BNEI:
1802 case RISCV::QC_E_BGEI:
1803 case RISCV::QC_E_BLTI:
1804 case RISCV::QC_E_BLTUI:
1805 case RISCV::QC_E_BGEUI:
1806 return isInt<13>(x: BrOffset);
1807 case RISCV::JAL:
1808 case RISCV::PseudoBR:
1809 return isInt<21>(x: BrOffset);
1810 case RISCV::PseudoJump:
1811 return isInt<32>(x: SignExtend64(X: BrOffset + 0x800, B: XLen));
1812 }
1813}
1814
1815// If the operation has a predicated pseudo instruction, return the pseudo
1816// instruction opcode. Otherwise, return RISCV::INSTRUCTION_LIST_END.
1817// TODO: Support more operations.
1818unsigned getPredicatedOpcode(unsigned Opcode) {
1819 // clang-format off
1820 switch (Opcode) {
1821 case RISCV::ADD: return RISCV::PseudoCCADD;
1822 case RISCV::SUB: return RISCV::PseudoCCSUB;
1823 case RISCV::SLL: return RISCV::PseudoCCSLL;
1824 case RISCV::SRL: return RISCV::PseudoCCSRL;
1825 case RISCV::SRA: return RISCV::PseudoCCSRA;
1826 case RISCV::AND: return RISCV::PseudoCCAND;
1827 case RISCV::OR: return RISCV::PseudoCCOR;
1828 case RISCV::XOR: return RISCV::PseudoCCXOR;
1829 case RISCV::MAX: return RISCV::PseudoCCMAX;
1830 case RISCV::MAXU: return RISCV::PseudoCCMAXU;
1831 case RISCV::MIN: return RISCV::PseudoCCMIN;
1832 case RISCV::MINU: return RISCV::PseudoCCMINU;
1833 case RISCV::MUL: return RISCV::PseudoCCMUL;
1834 case RISCV::LUI: return RISCV::PseudoCCLUI;
1835 case RISCV::QC_LI: return RISCV::PseudoCCQC_LI;
1836 case RISCV::QC_E_LI: return RISCV::PseudoCCQC_E_LI;
1837
1838 case RISCV::ADDI: return RISCV::PseudoCCADDI;
1839 case RISCV::SLLI: return RISCV::PseudoCCSLLI;
1840 case RISCV::SRLI: return RISCV::PseudoCCSRLI;
1841 case RISCV::SRAI: return RISCV::PseudoCCSRAI;
1842 case RISCV::ANDI: return RISCV::PseudoCCANDI;
1843 case RISCV::ORI: return RISCV::PseudoCCORI;
1844 case RISCV::XORI: return RISCV::PseudoCCXORI;
1845
1846 case RISCV::ADDW: return RISCV::PseudoCCADDW;
1847 case RISCV::SUBW: return RISCV::PseudoCCSUBW;
1848 case RISCV::SLLW: return RISCV::PseudoCCSLLW;
1849 case RISCV::SRLW: return RISCV::PseudoCCSRLW;
1850 case RISCV::SRAW: return RISCV::PseudoCCSRAW;
1851
1852 case RISCV::ADDIW: return RISCV::PseudoCCADDIW;
1853 case RISCV::SLLIW: return RISCV::PseudoCCSLLIW;
1854 case RISCV::SRLIW: return RISCV::PseudoCCSRLIW;
1855 case RISCV::SRAIW: return RISCV::PseudoCCSRAIW;
1856
1857 case RISCV::ANDN: return RISCV::PseudoCCANDN;
1858 case RISCV::ORN: return RISCV::PseudoCCORN;
1859 case RISCV::XNOR: return RISCV::PseudoCCXNOR;
1860
1861 case RISCV::NDS_BFOS: return RISCV::PseudoCCNDS_BFOS;
1862 case RISCV::NDS_BFOZ: return RISCV::PseudoCCNDS_BFOZ;
1863 }
1864 // clang-format on
1865
1866 return RISCV::INSTRUCTION_LIST_END;
1867}
1868
1869/// Identify instructions that can be folded into a CCMOV instruction, and
1870/// return the defining instruction.
1871static MachineInstr *canFoldAsPredicatedOp(Register Reg,
1872 const MachineRegisterInfo &MRI,
1873 const TargetInstrInfo *TII,
1874 const RISCVSubtarget &STI) {
1875 if (!Reg.isVirtual())
1876 return nullptr;
1877 if (!MRI.hasOneNonDBGUse(RegNo: Reg))
1878 return nullptr;
1879 MachineInstr *MI = MRI.getVRegDef(Reg);
1880 if (!MI)
1881 return nullptr;
1882
1883 if (!STI.hasShortForwardBranchIMinMax() &&
1884 (MI->getOpcode() == RISCV::MAX || MI->getOpcode() == RISCV::MIN ||
1885 MI->getOpcode() == RISCV::MINU || MI->getOpcode() == RISCV::MAXU))
1886 return nullptr;
1887
1888 if (!STI.hasShortForwardBranchIMul() && MI->getOpcode() == RISCV::MUL)
1889 return nullptr;
1890
1891 // Check if MI can be predicated and folded into the CCMOV.
1892 if (getPredicatedOpcode(Opcode: MI->getOpcode()) == RISCV::INSTRUCTION_LIST_END)
1893 return nullptr;
1894 // Don't predicate li idiom.
1895 if (MI->getOpcode() == RISCV::ADDI && MI->getOperand(i: 1).isReg() &&
1896 MI->getOperand(i: 1).getReg() == RISCV::X0)
1897 return nullptr;
1898 // Check if MI has any other defs or physreg uses.
1899 for (const MachineOperand &MO : llvm::drop_begin(RangeOrContainer: MI->operands())) {
1900 // Reject frame index operands, PEI can't handle the predicated pseudos.
1901 if (MO.isFI() || MO.isCPI() || MO.isJTI())
1902 return nullptr;
1903 if (!MO.isReg())
1904 continue;
1905 // MI can't have any tied operands, that would conflict with predication.
1906 if (MO.isTied())
1907 return nullptr;
1908 if (MO.isDef())
1909 return nullptr;
1910 // Allow constant physregs.
1911 if (MO.getReg().isPhysical() && !MRI.isConstantPhysReg(PhysReg: MO.getReg()))
1912 return nullptr;
1913 }
1914 bool DontMoveAcrossStores = true;
1915 if (!MI->isSafeToMove(SawStore&: DontMoveAcrossStores))
1916 return nullptr;
1917 return MI;
1918}
1919
1920MachineInstr *
1921RISCVInstrInfo::optimizeSelect(MachineInstr &MI,
1922 SmallPtrSetImpl<MachineInstr *> &SeenMIs,
1923 bool PreferFalse) const {
1924 assert(MI.getOpcode() == RISCV::PseudoCCMOVGPR &&
1925 "Unknown select instruction");
1926 if (!STI.hasShortForwardBranchIALU())
1927 return nullptr;
1928
1929 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
1930 MachineInstr *DefMI =
1931 canFoldAsPredicatedOp(Reg: MI.getOperand(i: 2).getReg(), MRI, TII: this, STI);
1932 bool Invert = !DefMI;
1933 if (!DefMI)
1934 DefMI = canFoldAsPredicatedOp(Reg: MI.getOperand(i: 1).getReg(), MRI, TII: this, STI);
1935 if (!DefMI)
1936 return nullptr;
1937
1938 // Find new register class to use.
1939 MachineOperand FalseReg = MI.getOperand(i: Invert ? 2 : 1);
1940 Register DestReg = MI.getOperand(i: 0).getReg();
1941 const TargetRegisterClass *PreviousClass = MRI.getRegClass(Reg: FalseReg.getReg());
1942 if (!MRI.constrainRegClass(Reg: DestReg, RC: PreviousClass))
1943 return nullptr;
1944
1945 unsigned PredOpc = getPredicatedOpcode(Opcode: DefMI->getOpcode());
1946 assert(PredOpc != RISCV::INSTRUCTION_LIST_END && "Unexpected opcode!");
1947
1948 // Create a new predicated version of DefMI.
1949 MachineInstrBuilder NewMI =
1950 BuildMI(BB&: *MI.getParent(), I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: PredOpc), DestReg);
1951
1952 // Copy the false register.
1953 NewMI.add(MO: FalseReg);
1954
1955 // Copy all the DefMI operands.
1956 const MCInstrDesc &DefDesc = DefMI->getDesc();
1957 for (unsigned i = 1, e = DefDesc.getNumOperands(); i != e; ++i)
1958 NewMI.add(MO: DefMI->getOperand(i));
1959
1960 // Add branch opcode, inverting if necessary.
1961 unsigned BCCOpcode = MI.getOperand(i: MI.getNumExplicitOperands() - 3).getImm();
1962 if (Invert)
1963 BCCOpcode = RISCVCC::getInverseBranchOpcode(BCC: BCCOpcode);
1964 NewMI.addImm(Val: BCCOpcode);
1965
1966 // Copy the condition portion.
1967 NewMI.add(MO: MI.getOperand(i: MI.getNumExplicitOperands() - 2));
1968 NewMI.add(MO: MI.getOperand(i: MI.getNumExplicitOperands() - 1));
1969
1970 // Update SeenMIs set: register newly created MI and erase removed DefMI.
1971 SeenMIs.insert(Ptr: NewMI);
1972 SeenMIs.erase(Ptr: DefMI);
1973
1974 // If MI is inside a loop, and DefMI is outside the loop, then kill flags on
1975 // DefMI would be invalid when transferred inside the loop. Checking for a
1976 // loop is expensive, but at least remove kill flags if they are in different
1977 // BBs.
1978 if (DefMI->getParent() != MI.getParent())
1979 NewMI->clearKillInfo();
1980
1981 // The caller will erase MI, but not DefMI.
1982 DefMI->eraseFromParent();
1983 return NewMI;
1984}
1985
1986unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
1987 if (MI.isMetaInstruction())
1988 return 0;
1989
1990 unsigned Opcode = MI.getOpcode();
1991
1992 if (Opcode == TargetOpcode::INLINEASM ||
1993 Opcode == TargetOpcode::INLINEASM_BR) {
1994 const MachineFunction &MF = *MI.getParent()->getParent();
1995 return getInlineAsmLength(Str: MI.getOperand(i: 0).getSymbolName(),
1996 MAI: MF.getTarget().getMCAsmInfo());
1997 }
1998
1999 if (requiresNTLHint(MI)) {
2000 if (STI.hasStdExtZca()) {
2001 if (isCompressibleInst(MI, STI))
2002 return 4; // c.ntl.all + c.load/c.store
2003 return 6; // c.ntl.all + load/store
2004 }
2005 return 8; // ntl.all + load/store
2006 }
2007
2008 if (Opcode == TargetOpcode::BUNDLE)
2009 return getInstBundleSize(MI);
2010
2011 if (MI.getParent() && MI.getParent()->getParent()) {
2012 if (isCompressibleInst(MI, STI))
2013 return 2;
2014 }
2015
2016 switch (Opcode) {
2017 case RISCV::PseudoMV_FPR16INX:
2018 case RISCV::PseudoMV_FPR32INX:
2019 case RISCV::PseudoClearGPR:
2020 // MV is always compressible to either c.mv or c.li rd, 0.
2021 return STI.hasStdExtZca() ? 2 : 4;
2022 // Below cases are for short forward branch pseudos
2023 case RISCV::PseudoCCMOVGPRNoX0:
2024 return get(Opcode: MI.getOperand(i: MI.getNumExplicitOperands() - 3).getImm())
2025 .getSize() +
2026 2;
2027 case RISCV::PseudoCCMOVGPR:
2028 case RISCV::PseudoCCADD:
2029 case RISCV::PseudoCCSUB:
2030 case RISCV::PseudoCCSLL:
2031 case RISCV::PseudoCCSRL:
2032 case RISCV::PseudoCCSRA:
2033 case RISCV::PseudoCCAND:
2034 case RISCV::PseudoCCOR:
2035 case RISCV::PseudoCCXOR:
2036 case RISCV::PseudoCCADDI:
2037 case RISCV::PseudoCCANDI:
2038 case RISCV::PseudoCCORI:
2039 case RISCV::PseudoCCXORI:
2040 case RISCV::PseudoCCLUI:
2041 case RISCV::PseudoCCSLLI:
2042 case RISCV::PseudoCCSRLI:
2043 case RISCV::PseudoCCSRAI:
2044 case RISCV::PseudoCCADDW:
2045 case RISCV::PseudoCCSUBW:
2046 case RISCV::PseudoCCSLLW:
2047 case RISCV::PseudoCCSRLW:
2048 case RISCV::PseudoCCSRAW:
2049 case RISCV::PseudoCCADDIW:
2050 case RISCV::PseudoCCSLLIW:
2051 case RISCV::PseudoCCSRLIW:
2052 case RISCV::PseudoCCSRAIW:
2053 case RISCV::PseudoCCANDN:
2054 case RISCV::PseudoCCORN:
2055 case RISCV::PseudoCCXNOR:
2056 case RISCV::PseudoCCMAX:
2057 case RISCV::PseudoCCMIN:
2058 case RISCV::PseudoCCMAXU:
2059 case RISCV::PseudoCCMINU:
2060 case RISCV::PseudoCCMUL:
2061 case RISCV::PseudoCCLB:
2062 case RISCV::PseudoCCLH:
2063 case RISCV::PseudoCCLW:
2064 case RISCV::PseudoCCLHU:
2065 case RISCV::PseudoCCLBU:
2066 case RISCV::PseudoCCLWU:
2067 case RISCV::PseudoCCLD:
2068 case RISCV::PseudoCCQC_LI:
2069 return get(Opcode: MI.getOperand(i: MI.getNumExplicitOperands() - 3).getImm())
2070 .getSize() +
2071 4;
2072 case RISCV::PseudoCCQC_E_LI:
2073 case RISCV::PseudoCCQC_E_LB:
2074 case RISCV::PseudoCCQC_E_LH:
2075 case RISCV::PseudoCCQC_E_LW:
2076 case RISCV::PseudoCCQC_E_LHU:
2077 case RISCV::PseudoCCQC_E_LBU:
2078 return get(Opcode: MI.getOperand(i: MI.getNumExplicitOperands() - 3).getImm())
2079 .getSize() +
2080 6;
2081 case TargetOpcode::STACKMAP:
2082 // The upper bound for a stackmap intrinsic is the full length of its shadow
2083 return StackMapOpers(&MI).getNumPatchBytes();
2084 case TargetOpcode::PATCHPOINT:
2085 // The size of the patchpoint intrinsic is the number of bytes requested
2086 return PatchPointOpers(&MI).getNumPatchBytes();
2087 case TargetOpcode::STATEPOINT: {
2088 // The size of the statepoint intrinsic is the number of bytes requested
2089 unsigned NumBytes = StatepointOpers(&MI).getNumPatchBytes();
2090 // No patch bytes means at most a PseudoCall is emitted
2091 return std::max(a: NumBytes, b: 8U);
2092 }
2093 case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
2094 case TargetOpcode::PATCHABLE_FUNCTION_EXIT:
2095 case TargetOpcode::PATCHABLE_TAIL_CALL: {
2096 const MachineFunction &MF = *MI.getParent()->getParent();
2097 const Function &F = MF.getFunction();
2098 if (Opcode == TargetOpcode::PATCHABLE_FUNCTION_ENTER &&
2099 F.hasFnAttribute(Kind: "patchable-function-entry")) {
2100 unsigned Num =
2101 F.getFnAttributeAsParsedInteger(Kind: "patchable-function-entry");
2102 // Number of C.NOP or NOP
2103 return (STI.hasStdExtZca() ? 2 : 4) * Num;
2104 }
2105 // XRay uses C.JAL + 21 or 33 C.NOP for each sled in RV32 and RV64,
2106 // respectively.
2107 return STI.is64Bit() ? 68 : 44;
2108 }
2109 default:
2110 return get(Opcode).getSize();
2111 }
2112}
2113
2114bool RISCVInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
2115 const unsigned Opcode = MI.getOpcode();
2116 switch (Opcode) {
2117 default:
2118 break;
2119 case RISCV::FSGNJ_D:
2120 case RISCV::FSGNJ_S:
2121 case RISCV::FSGNJ_H:
2122 case RISCV::FSGNJ_D_INX:
2123 case RISCV::FSGNJ_D_IN32X:
2124 case RISCV::FSGNJ_S_INX:
2125 case RISCV::FSGNJ_H_INX:
2126 // The canonical floating-point move is fsgnj rd, rs, rs.
2127 return MI.getOperand(i: 1).isReg() && MI.getOperand(i: 2).isReg() &&
2128 MI.getOperand(i: 1).getReg() == MI.getOperand(i: 2).getReg();
2129 case RISCV::ADDI:
2130 case RISCV::ORI:
2131 case RISCV::XORI:
2132 return (MI.getOperand(i: 1).isReg() &&
2133 MI.getOperand(i: 1).getReg() == RISCV::X0) ||
2134 (MI.getOperand(i: 2).isImm() && MI.getOperand(i: 2).getImm() == 0);
2135 }
2136 return MI.isAsCheapAsAMove();
2137}
2138
2139std::optional<DestSourcePair>
2140RISCVInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
2141 if (MI.isMoveReg())
2142 return DestSourcePair{MI.getOperand(i: 0), MI.getOperand(i: 1)};
2143 switch (MI.getOpcode()) {
2144 default:
2145 break;
2146 case RISCV::ADD:
2147 case RISCV::OR:
2148 case RISCV::XOR:
2149 if (MI.getOperand(i: 1).isReg() && MI.getOperand(i: 1).getReg() == RISCV::X0 &&
2150 MI.getOperand(i: 2).isReg())
2151 return DestSourcePair{MI.getOperand(i: 0), MI.getOperand(i: 2)};
2152 if (MI.getOperand(i: 2).isReg() && MI.getOperand(i: 2).getReg() == RISCV::X0 &&
2153 MI.getOperand(i: 1).isReg())
2154 return DestSourcePair{MI.getOperand(i: 0), MI.getOperand(i: 1)};
2155 break;
2156 case RISCV::ADDI:
2157 // Operand 1 can be a frameindex but callers expect registers
2158 if (MI.getOperand(i: 1).isReg() && MI.getOperand(i: 2).isImm() &&
2159 MI.getOperand(i: 2).getImm() == 0)
2160 return DestSourcePair{MI.getOperand(i: 0), MI.getOperand(i: 1)};
2161 break;
2162 case RISCV::SUB:
2163 if (MI.getOperand(i: 2).isReg() && MI.getOperand(i: 2).getReg() == RISCV::X0 &&
2164 MI.getOperand(i: 1).isReg())
2165 return DestSourcePair{MI.getOperand(i: 0), MI.getOperand(i: 1)};
2166 break;
2167 case RISCV::SH1ADD:
2168 case RISCV::SH1ADD_UW:
2169 case RISCV::SH2ADD:
2170 case RISCV::SH2ADD_UW:
2171 case RISCV::SH3ADD:
2172 case RISCV::SH3ADD_UW:
2173 if (MI.getOperand(i: 1).isReg() && MI.getOperand(i: 1).getReg() == RISCV::X0 &&
2174 MI.getOperand(i: 2).isReg())
2175 return DestSourcePair{MI.getOperand(i: 0), MI.getOperand(i: 2)};
2176 break;
2177 case RISCV::FSGNJ_D:
2178 case RISCV::FSGNJ_S:
2179 case RISCV::FSGNJ_H:
2180 case RISCV::FSGNJ_D_INX:
2181 case RISCV::FSGNJ_D_IN32X:
2182 case RISCV::FSGNJ_S_INX:
2183 case RISCV::FSGNJ_H_INX:
2184 // The canonical floating-point move is fsgnj rd, rs, rs.
2185 if (MI.getOperand(i: 1).isReg() && MI.getOperand(i: 2).isReg() &&
2186 MI.getOperand(i: 1).getReg() == MI.getOperand(i: 2).getReg())
2187 return DestSourcePair{MI.getOperand(i: 0), MI.getOperand(i: 1)};
2188 break;
2189 }
2190 return std::nullopt;
2191}
2192
2193MachineTraceStrategy RISCVInstrInfo::getMachineCombinerTraceStrategy() const {
2194 if (ForceMachineCombinerStrategy.getNumOccurrences() == 0) {
2195 // The option is unused. Choose Local strategy only for in-order cores. When
2196 // scheduling model is unspecified, use MinInstrCount strategy as more
2197 // generic one.
2198 const auto &SchedModel = STI.getSchedModel();
2199 return (!SchedModel.hasInstrSchedModel() || SchedModel.isOutOfOrder())
2200 ? MachineTraceStrategy::TS_MinInstrCount
2201 : MachineTraceStrategy::TS_Local;
2202 }
2203 // The strategy was forced by the option.
2204 return ForceMachineCombinerStrategy;
2205}
2206
2207void RISCVInstrInfo::finalizeInsInstrs(
2208 MachineInstr &Root, unsigned &Pattern,
2209 SmallVectorImpl<MachineInstr *> &InsInstrs) const {
2210 int16_t FrmOpIdx =
2211 RISCV::getNamedOperandIdx(Opcode: Root.getOpcode(), Name: RISCV::OpName::frm);
2212 if (FrmOpIdx < 0) {
2213 assert(all_of(InsInstrs,
2214 [](MachineInstr *MI) {
2215 return RISCV::getNamedOperandIdx(MI->getOpcode(),
2216 RISCV::OpName::frm) < 0;
2217 }) &&
2218 "New instructions require FRM whereas the old one does not have it");
2219 return;
2220 }
2221
2222 const MachineOperand &FRM = Root.getOperand(i: FrmOpIdx);
2223 MachineFunction &MF = *Root.getMF();
2224
2225 for (auto *NewMI : InsInstrs) {
2226 // We'd already added the FRM operand.
2227 if (static_cast<unsigned>(RISCV::getNamedOperandIdx(
2228 Opcode: NewMI->getOpcode(), Name: RISCV::OpName::frm)) != NewMI->getNumOperands())
2229 continue;
2230 MachineInstrBuilder MIB(MF, NewMI);
2231 MIB.add(MO: FRM);
2232 if (FRM.getImm() == RISCVFPRndMode::DYN)
2233 MIB.addUse(RegNo: RISCV::FRM, Flags: RegState::Implicit);
2234 }
2235}
2236
2237static bool isFADD(unsigned Opc) {
2238 switch (Opc) {
2239 default:
2240 return false;
2241 case RISCV::FADD_H:
2242 case RISCV::FADD_S:
2243 case RISCV::FADD_D:
2244 return true;
2245 }
2246}
2247
2248static bool isFSUB(unsigned Opc) {
2249 switch (Opc) {
2250 default:
2251 return false;
2252 case RISCV::FSUB_H:
2253 case RISCV::FSUB_S:
2254 case RISCV::FSUB_D:
2255 return true;
2256 }
2257}
2258
2259static bool isFMUL(unsigned Opc) {
2260 switch (Opc) {
2261 default:
2262 return false;
2263 case RISCV::FMUL_H:
2264 case RISCV::FMUL_S:
2265 case RISCV::FMUL_D:
2266 return true;
2267 }
2268}
2269
2270bool RISCVInstrInfo::isVectorAssociativeAndCommutative(const MachineInstr &Inst,
2271 bool Invert) const {
2272#define OPCODE_LMUL_CASE(OPC) \
2273 case RISCV::OPC##_M1: \
2274 case RISCV::OPC##_M2: \
2275 case RISCV::OPC##_M4: \
2276 case RISCV::OPC##_M8: \
2277 case RISCV::OPC##_MF2: \
2278 case RISCV::OPC##_MF4: \
2279 case RISCV::OPC##_MF8
2280
2281#define OPCODE_LMUL_MASK_CASE(OPC) \
2282 case RISCV::OPC##_M1_MASK: \
2283 case RISCV::OPC##_M2_MASK: \
2284 case RISCV::OPC##_M4_MASK: \
2285 case RISCV::OPC##_M8_MASK: \
2286 case RISCV::OPC##_MF2_MASK: \
2287 case RISCV::OPC##_MF4_MASK: \
2288 case RISCV::OPC##_MF8_MASK
2289
2290 unsigned Opcode = Inst.getOpcode();
2291 if (Invert) {
2292 if (auto InvOpcode = getInverseOpcode(Opcode))
2293 Opcode = *InvOpcode;
2294 else
2295 return false;
2296 }
2297
2298 // clang-format off
2299 switch (Opcode) {
2300 default:
2301 return false;
2302 OPCODE_LMUL_CASE(PseudoVADD_VV):
2303 OPCODE_LMUL_MASK_CASE(PseudoVADD_VV):
2304 OPCODE_LMUL_CASE(PseudoVMUL_VV):
2305 OPCODE_LMUL_MASK_CASE(PseudoVMUL_VV):
2306 return true;
2307 }
2308 // clang-format on
2309
2310#undef OPCODE_LMUL_MASK_CASE
2311#undef OPCODE_LMUL_CASE
2312}
2313
2314bool RISCVInstrInfo::areRVVInstsReassociable(const MachineInstr &Root,
2315 const MachineInstr &Prev) const {
2316 if (!areOpcodesEqualOrInverse(Opcode1: Root.getOpcode(), Opcode2: Prev.getOpcode()))
2317 return false;
2318
2319 assert(Root.getMF() == Prev.getMF());
2320 const MachineRegisterInfo *MRI = &Root.getMF()->getRegInfo();
2321 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
2322
2323 // Make sure vtype operands are also the same.
2324 const MCInstrDesc &Desc = get(Opcode: Root.getOpcode());
2325 const uint64_t TSFlags = Desc.TSFlags;
2326
2327 auto checkImmOperand = [&](unsigned OpIdx) {
2328 return Root.getOperand(i: OpIdx).getImm() == Prev.getOperand(i: OpIdx).getImm();
2329 };
2330
2331 auto checkRegOperand = [&](unsigned OpIdx) {
2332 return Root.getOperand(i: OpIdx).getReg() == Prev.getOperand(i: OpIdx).getReg();
2333 };
2334
2335 // PassThru
2336 // TODO: Potentially we can loosen the condition to consider Root to be
2337 // associable with Prev if Root has NoReg as passthru. In which case we
2338 // also need to loosen the condition on vector policies between these.
2339 if (!checkRegOperand(1))
2340 return false;
2341
2342 // SEW
2343 if (RISCVII::hasSEWOp(TSFlags) &&
2344 !checkImmOperand(RISCVII::getSEWOpNum(Desc)))
2345 return false;
2346
2347 // Mask
2348 if (RISCVII::usesMaskPolicy(TSFlags)) {
2349 const MachineBasicBlock *MBB = Root.getParent();
2350 const MachineBasicBlock::const_reverse_iterator It1(&Root);
2351 const MachineBasicBlock::const_reverse_iterator It2(&Prev);
2352 Register MI1VReg;
2353
2354 bool SeenMI2 = false;
2355 for (auto End = MBB->rend(), It = It1; It != End; ++It) {
2356 if (It == It2) {
2357 SeenMI2 = true;
2358 if (!MI1VReg.isValid())
2359 // There is no V0 def between Root and Prev; they're sharing the
2360 // same V0.
2361 break;
2362 }
2363
2364 if (It->modifiesRegister(Reg: RISCV::V0, TRI)) {
2365 Register SrcReg = It->getOperand(i: 1).getReg();
2366 // If it's not VReg it'll be more difficult to track its defs, so
2367 // bailing out here just to be safe.
2368 if (!SrcReg.isVirtual())
2369 return false;
2370
2371 if (!MI1VReg.isValid()) {
2372 // This is the V0 def for Root.
2373 MI1VReg = SrcReg;
2374 continue;
2375 }
2376
2377 // Some random mask updates.
2378 if (!SeenMI2)
2379 continue;
2380
2381 // This is the V0 def for Prev; check if it's the same as that of
2382 // Root.
2383 if (MI1VReg != SrcReg)
2384 return false;
2385 else
2386 break;
2387 }
2388 }
2389
2390 // If we haven't encountered Prev, it's likely that this function was
2391 // called in a wrong way (e.g. Root is before Prev).
2392 assert(SeenMI2 && "Prev is expected to appear before Root");
2393 }
2394
2395 // Tail / Mask policies
2396 if (RISCVII::hasVecPolicyOp(TSFlags) &&
2397 !checkImmOperand(RISCVII::getVecPolicyOpNum(Desc)))
2398 return false;
2399
2400 // VL
2401 if (RISCVII::hasVLOp(TSFlags)) {
2402 unsigned OpIdx = RISCVII::getVLOpNum(Desc);
2403 const MachineOperand &Op1 = Root.getOperand(i: OpIdx);
2404 const MachineOperand &Op2 = Prev.getOperand(i: OpIdx);
2405 if (Op1.getType() != Op2.getType())
2406 return false;
2407 switch (Op1.getType()) {
2408 case MachineOperand::MO_Register:
2409 if (Op1.getReg() != Op2.getReg())
2410 return false;
2411 break;
2412 case MachineOperand::MO_Immediate:
2413 if (Op1.getImm() != Op2.getImm())
2414 return false;
2415 break;
2416 default:
2417 llvm_unreachable("Unrecognized VL operand type");
2418 }
2419 }
2420
2421 // Rounding modes
2422 if (int Idx = RISCVII::getFRMOpNum(Desc); Idx >= 0 && !checkImmOperand(Idx))
2423 return false;
2424 if (int Idx = RISCVII::getVXRMOpNum(Desc); Idx >= 0 && !checkImmOperand(Idx))
2425 return false;
2426
2427 return true;
2428}
2429
2430// Most of our RVV pseudos have passthru operand, so the real operands
2431// start from index = 2.
2432bool RISCVInstrInfo::hasReassociableVectorSibling(const MachineInstr &Inst,
2433 bool &Commuted) const {
2434 const MachineBasicBlock *MBB = Inst.getParent();
2435 const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
2436 assert(RISCVII::isFirstDefTiedToFirstUse(get(Inst.getOpcode())) &&
2437 "Expect the present of passthrough operand.");
2438 MachineInstr *MI1 = MRI.getUniqueVRegDef(Reg: Inst.getOperand(i: 2).getReg());
2439 MachineInstr *MI2 = MRI.getUniqueVRegDef(Reg: Inst.getOperand(i: 3).getReg());
2440
2441 // If only one operand has the same or inverse opcode and it's the second
2442 // source operand, the operands must be commuted.
2443 Commuted = !areRVVInstsReassociable(Root: Inst, Prev: *MI1) &&
2444 areRVVInstsReassociable(Root: Inst, Prev: *MI2);
2445 if (Commuted)
2446 std::swap(a&: MI1, b&: MI2);
2447
2448 return areRVVInstsReassociable(Root: Inst, Prev: *MI1) &&
2449 (isVectorAssociativeAndCommutative(Inst: *MI1) ||
2450 isVectorAssociativeAndCommutative(Inst: *MI1, /* Invert */ true)) &&
2451 hasReassociableOperands(Inst: *MI1, MBB) &&
2452 MRI.hasOneNonDBGUse(RegNo: MI1->getOperand(i: 0).getReg());
2453}
2454
2455bool RISCVInstrInfo::hasReassociableOperands(
2456 const MachineInstr &Inst, const MachineBasicBlock *MBB) const {
2457 if (!isVectorAssociativeAndCommutative(Inst) &&
2458 !isVectorAssociativeAndCommutative(Inst, /*Invert=*/true))
2459 return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
2460
2461 const MachineOperand &Op1 = Inst.getOperand(i: 2);
2462 const MachineOperand &Op2 = Inst.getOperand(i: 3);
2463 const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
2464
2465 // We need virtual register definitions for the operands that we will
2466 // reassociate.
2467 MachineInstr *MI1 = nullptr;
2468 MachineInstr *MI2 = nullptr;
2469 if (Op1.isReg() && Op1.getReg().isVirtual())
2470 MI1 = MRI.getUniqueVRegDef(Reg: Op1.getReg());
2471 if (Op2.isReg() && Op2.getReg().isVirtual())
2472 MI2 = MRI.getUniqueVRegDef(Reg: Op2.getReg());
2473
2474 // And at least one operand must be defined in MBB.
2475 return MI1 && MI2 && (MI1->getParent() == MBB || MI2->getParent() == MBB);
2476}
2477
2478void RISCVInstrInfo::getReassociateOperandIndices(
2479 const MachineInstr &Root, unsigned Pattern,
2480 std::array<unsigned, 5> &OperandIndices) const {
2481 TargetInstrInfo::getReassociateOperandIndices(Root, Pattern, OperandIndices);
2482 if (RISCV::getRVVMCOpcode(RVVPseudoOpcode: Root.getOpcode())) {
2483 // Skip the passthrough operand, so increment all indices by one.
2484 for (unsigned I = 0; I < 5; ++I)
2485 ++OperandIndices[I];
2486 }
2487}
2488
2489bool RISCVInstrInfo::hasReassociableSibling(const MachineInstr &Inst,
2490 bool &Commuted) const {
2491 if (isVectorAssociativeAndCommutative(Inst) ||
2492 isVectorAssociativeAndCommutative(Inst, /*Invert=*/true))
2493 return hasReassociableVectorSibling(Inst, Commuted);
2494
2495 if (!TargetInstrInfo::hasReassociableSibling(Inst, Commuted))
2496 return false;
2497
2498 const MachineRegisterInfo &MRI = Inst.getMF()->getRegInfo();
2499 unsigned OperandIdx = Commuted ? 2 : 1;
2500 const MachineInstr &Sibling =
2501 *MRI.getVRegDef(Reg: Inst.getOperand(i: OperandIdx).getReg());
2502
2503 int16_t InstFrmOpIdx =
2504 RISCV::getNamedOperandIdx(Opcode: Inst.getOpcode(), Name: RISCV::OpName::frm);
2505 int16_t SiblingFrmOpIdx =
2506 RISCV::getNamedOperandIdx(Opcode: Sibling.getOpcode(), Name: RISCV::OpName::frm);
2507
2508 return (InstFrmOpIdx < 0 && SiblingFrmOpIdx < 0) ||
2509 RISCV::hasEqualFRM(MI1: Inst, MI2: Sibling);
2510}
2511
2512bool RISCVInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst,
2513 bool Invert) const {
2514 if (isVectorAssociativeAndCommutative(Inst, Invert))
2515 return true;
2516
2517 unsigned Opc = Inst.getOpcode();
2518 if (Invert) {
2519 auto InverseOpcode = getInverseOpcode(Opcode: Opc);
2520 if (!InverseOpcode)
2521 return false;
2522 Opc = *InverseOpcode;
2523 }
2524
2525 if (isFADD(Opc) || isFMUL(Opc))
2526 return Inst.getFlag(Flag: MachineInstr::MIFlag::FmReassoc) &&
2527 Inst.getFlag(Flag: MachineInstr::MIFlag::FmNsz);
2528
2529 switch (Opc) {
2530 default:
2531 return false;
2532 case RISCV::ADD:
2533 case RISCV::ADDW:
2534 case RISCV::AND:
2535 case RISCV::OR:
2536 case RISCV::XOR:
2537 // From RISC-V ISA spec, if both the high and low bits of the same product
2538 // are required, then the recommended code sequence is:
2539 //
2540 // MULH[[S]U] rdh, rs1, rs2
2541 // MUL rdl, rs1, rs2
2542 // (source register specifiers must be in same order and rdh cannot be the
2543 // same as rs1 or rs2)
2544 //
2545 // Microarchitectures can then fuse these into a single multiply operation
2546 // instead of performing two separate multiplies.
2547 // MachineCombiner may reassociate MUL operands and lose the fusion
2548 // opportunity.
2549 case RISCV::MUL:
2550 case RISCV::MULW:
2551 case RISCV::MIN:
2552 case RISCV::MINU:
2553 case RISCV::MAX:
2554 case RISCV::MAXU:
2555 case RISCV::FMIN_H:
2556 case RISCV::FMIN_S:
2557 case RISCV::FMIN_D:
2558 case RISCV::FMAX_H:
2559 case RISCV::FMAX_S:
2560 case RISCV::FMAX_D:
2561 return true;
2562 }
2563
2564 return false;
2565}
2566
2567std::optional<unsigned>
2568RISCVInstrInfo::getInverseOpcode(unsigned Opcode) const {
2569#define RVV_OPC_LMUL_CASE(OPC, INV) \
2570 case RISCV::OPC##_M1: \
2571 return RISCV::INV##_M1; \
2572 case RISCV::OPC##_M2: \
2573 return RISCV::INV##_M2; \
2574 case RISCV::OPC##_M4: \
2575 return RISCV::INV##_M4; \
2576 case RISCV::OPC##_M8: \
2577 return RISCV::INV##_M8; \
2578 case RISCV::OPC##_MF2: \
2579 return RISCV::INV##_MF2; \
2580 case RISCV::OPC##_MF4: \
2581 return RISCV::INV##_MF4; \
2582 case RISCV::OPC##_MF8: \
2583 return RISCV::INV##_MF8
2584
2585#define RVV_OPC_LMUL_MASK_CASE(OPC, INV) \
2586 case RISCV::OPC##_M1_MASK: \
2587 return RISCV::INV##_M1_MASK; \
2588 case RISCV::OPC##_M2_MASK: \
2589 return RISCV::INV##_M2_MASK; \
2590 case RISCV::OPC##_M4_MASK: \
2591 return RISCV::INV##_M4_MASK; \
2592 case RISCV::OPC##_M8_MASK: \
2593 return RISCV::INV##_M8_MASK; \
2594 case RISCV::OPC##_MF2_MASK: \
2595 return RISCV::INV##_MF2_MASK; \
2596 case RISCV::OPC##_MF4_MASK: \
2597 return RISCV::INV##_MF4_MASK; \
2598 case RISCV::OPC##_MF8_MASK: \
2599 return RISCV::INV##_MF8_MASK
2600
2601 switch (Opcode) {
2602 default:
2603 return std::nullopt;
2604 case RISCV::FADD_H:
2605 return RISCV::FSUB_H;
2606 case RISCV::FADD_S:
2607 return RISCV::FSUB_S;
2608 case RISCV::FADD_D:
2609 return RISCV::FSUB_D;
2610 case RISCV::FSUB_H:
2611 return RISCV::FADD_H;
2612 case RISCV::FSUB_S:
2613 return RISCV::FADD_S;
2614 case RISCV::FSUB_D:
2615 return RISCV::FADD_D;
2616 case RISCV::ADD:
2617 return RISCV::SUB;
2618 case RISCV::SUB:
2619 return RISCV::ADD;
2620 case RISCV::ADDW:
2621 return RISCV::SUBW;
2622 case RISCV::SUBW:
2623 return RISCV::ADDW;
2624 // clang-format off
2625 RVV_OPC_LMUL_CASE(PseudoVADD_VV, PseudoVSUB_VV);
2626 RVV_OPC_LMUL_MASK_CASE(PseudoVADD_VV, PseudoVSUB_VV);
2627 RVV_OPC_LMUL_CASE(PseudoVSUB_VV, PseudoVADD_VV);
2628 RVV_OPC_LMUL_MASK_CASE(PseudoVSUB_VV, PseudoVADD_VV);
2629 // clang-format on
2630 }
2631
2632#undef RVV_OPC_LMUL_MASK_CASE
2633#undef RVV_OPC_LMUL_CASE
2634}
2635
2636static bool canCombineFPFusedMultiply(const MachineInstr &Root,
2637 const MachineOperand &MO,
2638 bool DoRegPressureReduce) {
2639 if (!MO.isReg() || !MO.getReg().isVirtual())
2640 return false;
2641 const MachineRegisterInfo &MRI = Root.getMF()->getRegInfo();
2642 MachineInstr *MI = MRI.getVRegDef(Reg: MO.getReg());
2643 if (!MI || !isFMUL(Opc: MI->getOpcode()))
2644 return false;
2645
2646 if (!Root.getFlag(Flag: MachineInstr::MIFlag::FmContract) ||
2647 !MI->getFlag(Flag: MachineInstr::MIFlag::FmContract))
2648 return false;
2649
2650 // Try combining even if fmul has more than one use as it eliminates
2651 // dependency between fadd(fsub) and fmul. However, it can extend liveranges
2652 // for fmul operands, so reject the transformation in register pressure
2653 // reduction mode.
2654 if (DoRegPressureReduce && !MRI.hasOneNonDBGUse(RegNo: MI->getOperand(i: 0).getReg()))
2655 return false;
2656
2657 // Do not combine instructions from different basic blocks.
2658 if (Root.getParent() != MI->getParent())
2659 return false;
2660 return RISCV::hasEqualFRM(MI1: Root, MI2: *MI);
2661}
2662
2663static bool getFPFusedMultiplyPatterns(MachineInstr &Root,
2664 SmallVectorImpl<unsigned> &Patterns,
2665 bool DoRegPressureReduce) {
2666 unsigned Opc = Root.getOpcode();
2667 bool IsFAdd = isFADD(Opc);
2668 if (!IsFAdd && !isFSUB(Opc))
2669 return false;
2670 bool Added = false;
2671 if (canCombineFPFusedMultiply(Root, MO: Root.getOperand(i: 1),
2672 DoRegPressureReduce)) {
2673 Patterns.push_back(Elt: IsFAdd ? RISCVMachineCombinerPattern::FMADD_AX
2674 : RISCVMachineCombinerPattern::FMSUB);
2675 Added = true;
2676 }
2677 if (canCombineFPFusedMultiply(Root, MO: Root.getOperand(i: 2),
2678 DoRegPressureReduce)) {
2679 Patterns.push_back(Elt: IsFAdd ? RISCVMachineCombinerPattern::FMADD_XA
2680 : RISCVMachineCombinerPattern::FNMSUB);
2681 Added = true;
2682 }
2683 return Added;
2684}
2685
2686static bool getFPPatterns(MachineInstr &Root,
2687 SmallVectorImpl<unsigned> &Patterns,
2688 bool DoRegPressureReduce) {
2689 return getFPFusedMultiplyPatterns(Root, Patterns, DoRegPressureReduce);
2690}
2691
2692/// Utility routine that checks if \param MO is defined by an
2693/// \param CombineOpc instruction in the basic block \param MBB
2694static const MachineInstr *canCombine(const MachineBasicBlock &MBB,
2695 const MachineOperand &MO,
2696 unsigned CombineOpc) {
2697 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2698 const MachineInstr *MI = nullptr;
2699
2700 if (MO.isReg() && MO.getReg().isVirtual())
2701 MI = MRI.getUniqueVRegDef(Reg: MO.getReg());
2702 // And it needs to be in the trace (otherwise, it won't have a depth).
2703 if (!MI || MI->getParent() != &MBB || MI->getOpcode() != CombineOpc)
2704 return nullptr;
2705 // Must only used by the user we combine with.
2706 if (!MRI.hasOneNonDBGUse(RegNo: MI->getOperand(i: 0).getReg()))
2707 return nullptr;
2708
2709 return MI;
2710}
2711
2712/// Utility routine that checks if \param MO is defined by a SLLI in \param
2713/// MBB that can be combined by splitting across 2 SHXADD instructions. The
2714/// first SHXADD shift amount is given by \param OuterShiftAmt.
2715static bool canCombineShiftIntoShXAdd(const MachineBasicBlock &MBB,
2716 const MachineOperand &MO,
2717 unsigned OuterShiftAmt) {
2718 const MachineInstr *ShiftMI = canCombine(MBB, MO, CombineOpc: RISCV::SLLI);
2719 if (!ShiftMI)
2720 return false;
2721
2722 unsigned InnerShiftAmt = ShiftMI->getOperand(i: 2).getImm();
2723 if (InnerShiftAmt < OuterShiftAmt || (InnerShiftAmt - OuterShiftAmt) > 3)
2724 return false;
2725
2726 return true;
2727}
2728
2729// Returns the shift amount from a SHXADD instruction. Returns 0 if the
2730// instruction is not a SHXADD.
2731static unsigned getSHXADDShiftAmount(unsigned Opc) {
2732 switch (Opc) {
2733 default:
2734 return 0;
2735 case RISCV::SH1ADD:
2736 return 1;
2737 case RISCV::SH2ADD:
2738 return 2;
2739 case RISCV::SH3ADD:
2740 return 3;
2741 }
2742}
2743
2744// Returns the shift amount from a SHXADD.UW instruction. Returns 0 if the
2745// instruction is not a SHXADD.UW.
2746static unsigned getSHXADDUWShiftAmount(unsigned Opc) {
2747 switch (Opc) {
2748 default:
2749 return 0;
2750 case RISCV::SH1ADD_UW:
2751 return 1;
2752 case RISCV::SH2ADD_UW:
2753 return 2;
2754 case RISCV::SH3ADD_UW:
2755 return 3;
2756 }
2757}
2758
2759// Look for opportunities to combine (sh3add Z, (add X, (slli Y, 5))) into
2760// (sh3add (sh2add Y, Z), X).
2761static bool getSHXADDPatterns(const MachineInstr &Root,
2762 SmallVectorImpl<unsigned> &Patterns) {
2763 unsigned ShiftAmt = getSHXADDShiftAmount(Opc: Root.getOpcode());
2764 if (!ShiftAmt)
2765 return false;
2766
2767 const MachineBasicBlock &MBB = *Root.getParent();
2768
2769 const MachineInstr *AddMI = canCombine(MBB, MO: Root.getOperand(i: 2), CombineOpc: RISCV::ADD);
2770 if (!AddMI)
2771 return false;
2772
2773 bool Found = false;
2774 if (canCombineShiftIntoShXAdd(MBB, MO: AddMI->getOperand(i: 1), OuterShiftAmt: ShiftAmt)) {
2775 Patterns.push_back(Elt: RISCVMachineCombinerPattern::SHXADD_ADD_SLLI_OP1);
2776 Found = true;
2777 }
2778 if (canCombineShiftIntoShXAdd(MBB, MO: AddMI->getOperand(i: 2), OuterShiftAmt: ShiftAmt)) {
2779 Patterns.push_back(Elt: RISCVMachineCombinerPattern::SHXADD_ADD_SLLI_OP2);
2780 Found = true;
2781 }
2782
2783 return Found;
2784}
2785
2786CombinerObjective RISCVInstrInfo::getCombinerObjective(unsigned Pattern) const {
2787 switch (Pattern) {
2788 case RISCVMachineCombinerPattern::FMADD_AX:
2789 case RISCVMachineCombinerPattern::FMADD_XA:
2790 case RISCVMachineCombinerPattern::FMSUB:
2791 case RISCVMachineCombinerPattern::FNMSUB:
2792 return CombinerObjective::MustReduceDepth;
2793 default:
2794 return TargetInstrInfo::getCombinerObjective(Pattern);
2795 }
2796}
2797
2798bool RISCVInstrInfo::getMachineCombinerPatterns(
2799 MachineInstr &Root, SmallVectorImpl<unsigned> &Patterns,
2800 bool DoRegPressureReduce) const {
2801
2802 if (getFPPatterns(Root, Patterns, DoRegPressureReduce))
2803 return true;
2804
2805 if (getSHXADDPatterns(Root, Patterns))
2806 return true;
2807
2808 return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns,
2809 DoRegPressureReduce);
2810}
2811
2812static unsigned getFPFusedMultiplyOpcode(unsigned RootOpc, unsigned Pattern) {
2813 switch (RootOpc) {
2814 default:
2815 llvm_unreachable("Unexpected opcode");
2816 case RISCV::FADD_H:
2817 return RISCV::FMADD_H;
2818 case RISCV::FADD_S:
2819 return RISCV::FMADD_S;
2820 case RISCV::FADD_D:
2821 return RISCV::FMADD_D;
2822 case RISCV::FSUB_H:
2823 return Pattern == RISCVMachineCombinerPattern::FMSUB ? RISCV::FMSUB_H
2824 : RISCV::FNMSUB_H;
2825 case RISCV::FSUB_S:
2826 return Pattern == RISCVMachineCombinerPattern::FMSUB ? RISCV::FMSUB_S
2827 : RISCV::FNMSUB_S;
2828 case RISCV::FSUB_D:
2829 return Pattern == RISCVMachineCombinerPattern::FMSUB ? RISCV::FMSUB_D
2830 : RISCV::FNMSUB_D;
2831 }
2832}
2833
2834static unsigned getAddendOperandIdx(unsigned Pattern) {
2835 switch (Pattern) {
2836 default:
2837 llvm_unreachable("Unexpected pattern");
2838 case RISCVMachineCombinerPattern::FMADD_AX:
2839 case RISCVMachineCombinerPattern::FMSUB:
2840 return 2;
2841 case RISCVMachineCombinerPattern::FMADD_XA:
2842 case RISCVMachineCombinerPattern::FNMSUB:
2843 return 1;
2844 }
2845}
2846
2847static void combineFPFusedMultiply(MachineInstr &Root, MachineInstr &Prev,
2848 unsigned Pattern,
2849 SmallVectorImpl<MachineInstr *> &InsInstrs,
2850 SmallVectorImpl<MachineInstr *> &DelInstrs) {
2851 MachineFunction *MF = Root.getMF();
2852 MachineRegisterInfo &MRI = MF->getRegInfo();
2853 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
2854
2855 MachineOperand &Mul1 = Prev.getOperand(i: 1);
2856 MachineOperand &Mul2 = Prev.getOperand(i: 2);
2857 MachineOperand &Dst = Root.getOperand(i: 0);
2858 MachineOperand &Addend = Root.getOperand(i: getAddendOperandIdx(Pattern));
2859
2860 Register DstReg = Dst.getReg();
2861 unsigned FusedOpc = getFPFusedMultiplyOpcode(RootOpc: Root.getOpcode(), Pattern);
2862 uint32_t IntersectedFlags = Root.getFlags() & Prev.getFlags();
2863 DebugLoc MergedLoc =
2864 DILocation::getMergedLocation(LocA: Root.getDebugLoc(), LocB: Prev.getDebugLoc());
2865
2866 bool Mul1IsKill = Mul1.isKill();
2867 bool Mul2IsKill = Mul2.isKill();
2868 bool AddendIsKill = Addend.isKill();
2869
2870 // We need to clear kill flags since we may be extending the live range past
2871 // a kill. If the mul had kill flags, we can preserve those since we know
2872 // where the previous range stopped.
2873 MRI.clearKillFlags(Reg: Mul1.getReg());
2874 MRI.clearKillFlags(Reg: Mul2.getReg());
2875
2876 MachineInstrBuilder MIB =
2877 BuildMI(MF&: *MF, MIMD: MergedLoc, MCID: TII->get(Opcode: FusedOpc), DestReg: DstReg)
2878 .addReg(RegNo: Mul1.getReg(), Flags: getKillRegState(B: Mul1IsKill))
2879 .addReg(RegNo: Mul2.getReg(), Flags: getKillRegState(B: Mul2IsKill))
2880 .addReg(RegNo: Addend.getReg(), Flags: getKillRegState(B: AddendIsKill))
2881 .setMIFlags(IntersectedFlags);
2882
2883 InsInstrs.push_back(Elt: MIB);
2884 if (MRI.hasOneNonDBGUse(RegNo: Prev.getOperand(i: 0).getReg()))
2885 DelInstrs.push_back(Elt: &Prev);
2886 DelInstrs.push_back(Elt: &Root);
2887}
2888
2889// Combine patterns like (sh3add Z, (add X, (slli Y, 5))) to
2890// (sh3add (sh2add Y, Z), X) if the shift amount can be split across two
2891// shXadd instructions. The outer shXadd keeps its original opcode.
2892static void
2893genShXAddAddShift(MachineInstr &Root, unsigned AddOpIdx,
2894 SmallVectorImpl<MachineInstr *> &InsInstrs,
2895 SmallVectorImpl<MachineInstr *> &DelInstrs,
2896 DenseMap<Register, unsigned> &InstrIdxForVirtReg) {
2897 MachineFunction *MF = Root.getMF();
2898 MachineRegisterInfo &MRI = MF->getRegInfo();
2899 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
2900
2901 unsigned OuterShiftAmt = getSHXADDShiftAmount(Opc: Root.getOpcode());
2902 assert(OuterShiftAmt != 0 && "Unexpected opcode");
2903
2904 MachineInstr *AddMI = MRI.getUniqueVRegDef(Reg: Root.getOperand(i: 2).getReg());
2905 MachineInstr *ShiftMI =
2906 MRI.getUniqueVRegDef(Reg: AddMI->getOperand(i: AddOpIdx).getReg());
2907
2908 unsigned InnerShiftAmt = ShiftMI->getOperand(i: 2).getImm();
2909 assert(InnerShiftAmt >= OuterShiftAmt && "Unexpected shift amount");
2910
2911 unsigned InnerOpc;
2912 switch (InnerShiftAmt - OuterShiftAmt) {
2913 default:
2914 llvm_unreachable("Unexpected shift amount");
2915 case 0:
2916 InnerOpc = RISCV::ADD;
2917 break;
2918 case 1:
2919 InnerOpc = RISCV::SH1ADD;
2920 break;
2921 case 2:
2922 InnerOpc = RISCV::SH2ADD;
2923 break;
2924 case 3:
2925 InnerOpc = RISCV::SH3ADD;
2926 break;
2927 }
2928
2929 const MachineOperand &X = AddMI->getOperand(i: 3 - AddOpIdx);
2930 const MachineOperand &Y = ShiftMI->getOperand(i: 1);
2931 const MachineOperand &Z = Root.getOperand(i: 1);
2932
2933 Register NewVR = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
2934
2935 auto MIB1 = BuildMI(MF&: *MF, MIMD: MIMetadata(Root), MCID: TII->get(Opcode: InnerOpc), DestReg: NewVR)
2936 .addReg(RegNo: Y.getReg(), Flags: getKillRegState(B: Y.isKill()))
2937 .addReg(RegNo: Z.getReg(), Flags: getKillRegState(B: Z.isKill()));
2938 auto MIB2 = BuildMI(MF&: *MF, MIMD: MIMetadata(Root), MCID: TII->get(Opcode: Root.getOpcode()),
2939 DestReg: Root.getOperand(i: 0).getReg())
2940 .addReg(RegNo: NewVR, Flags: RegState::Kill)
2941 .addReg(RegNo: X.getReg(), Flags: getKillRegState(B: X.isKill()));
2942
2943 InstrIdxForVirtReg.insert(KV: std::make_pair(x&: NewVR, y: 0));
2944 InsInstrs.push_back(Elt: MIB1);
2945 InsInstrs.push_back(Elt: MIB2);
2946 DelInstrs.push_back(Elt: ShiftMI);
2947 DelInstrs.push_back(Elt: AddMI);
2948 DelInstrs.push_back(Elt: &Root);
2949}
2950
2951void RISCVInstrInfo::genAlternativeCodeSequence(
2952 MachineInstr &Root, unsigned Pattern,
2953 SmallVectorImpl<MachineInstr *> &InsInstrs,
2954 SmallVectorImpl<MachineInstr *> &DelInstrs,
2955 DenseMap<Register, unsigned> &InstrIdxForVirtReg) const {
2956 MachineRegisterInfo &MRI = Root.getMF()->getRegInfo();
2957 switch (Pattern) {
2958 default:
2959 TargetInstrInfo::genAlternativeCodeSequence(Root, Pattern, InsInstrs,
2960 DelInstrs, InstIdxForVirtReg&: InstrIdxForVirtReg);
2961 return;
2962 case RISCVMachineCombinerPattern::FMADD_AX:
2963 case RISCVMachineCombinerPattern::FMSUB: {
2964 MachineInstr &Prev = *MRI.getVRegDef(Reg: Root.getOperand(i: 1).getReg());
2965 combineFPFusedMultiply(Root, Prev, Pattern, InsInstrs, DelInstrs);
2966 return;
2967 }
2968 case RISCVMachineCombinerPattern::FMADD_XA:
2969 case RISCVMachineCombinerPattern::FNMSUB: {
2970 MachineInstr &Prev = *MRI.getVRegDef(Reg: Root.getOperand(i: 2).getReg());
2971 combineFPFusedMultiply(Root, Prev, Pattern, InsInstrs, DelInstrs);
2972 return;
2973 }
2974 case RISCVMachineCombinerPattern::SHXADD_ADD_SLLI_OP1:
2975 genShXAddAddShift(Root, AddOpIdx: 1, InsInstrs, DelInstrs, InstrIdxForVirtReg);
2976 return;
2977 case RISCVMachineCombinerPattern::SHXADD_ADD_SLLI_OP2:
2978 genShXAddAddShift(Root, AddOpIdx: 2, InsInstrs, DelInstrs, InstrIdxForVirtReg);
2979 return;
2980 }
2981}
2982
2983bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
2984 StringRef &ErrInfo) const {
2985 MCInstrDesc const &Desc = MI.getDesc();
2986
2987 for (const auto &[Index, Operand] : enumerate(First: Desc.operands())) {
2988 const MachineOperand &MO = MI.getOperand(i: Index);
2989 unsigned OpType = Operand.OperandType;
2990 switch (OpType) {
2991 default:
2992 if (OpType >= RISCVOp::OPERAND_FIRST_RISCV_IMM &&
2993 OpType <= RISCVOp::OPERAND_LAST_RISCV_IMM) {
2994 if (!MO.isImm()) {
2995 ErrInfo = "Expected an immediate operand.";
2996 return false;
2997 }
2998 int64_t Imm = MO.getImm();
2999 bool Ok;
3000 switch (OpType) {
3001 default:
3002 llvm_unreachable("Unexpected operand type");
3003
3004#define CASE_OPERAND_UIMM(NUM) \
3005 case RISCVOp::OPERAND_UIMM##NUM: \
3006 Ok = isUInt<NUM>(Imm); \
3007 break;
3008#define CASE_OPERAND_UIMM_LSB_ZEROS(BITS, SUFFIX) \
3009 case RISCVOp::OPERAND_UIMM##BITS##_LSB##SUFFIX: { \
3010 constexpr size_t NumZeros = sizeof(#SUFFIX) - 1; \
3011 Ok = isShiftedUInt<BITS - NumZeros, NumZeros>(Imm); \
3012 break; \
3013 }
3014#define CASE_OPERAND_SIMM(NUM) \
3015 case RISCVOp::OPERAND_SIMM##NUM: \
3016 Ok = isInt<NUM>(Imm); \
3017 break;
3018 // clang-format off
3019 CASE_OPERAND_UIMM(1)
3020 CASE_OPERAND_UIMM(2)
3021 CASE_OPERAND_UIMM(3)
3022 CASE_OPERAND_UIMM(4)
3023 CASE_OPERAND_UIMM(5)
3024 CASE_OPERAND_UIMM(6)
3025 CASE_OPERAND_UIMM(7)
3026 CASE_OPERAND_UIMM(8)
3027 CASE_OPERAND_UIMM(9)
3028 CASE_OPERAND_UIMM(10)
3029 CASE_OPERAND_UIMM(12)
3030 CASE_OPERAND_UIMM(16)
3031 CASE_OPERAND_UIMM(32)
3032 CASE_OPERAND_UIMM(48)
3033 CASE_OPERAND_UIMM(64)
3034 CASE_OPERAND_UIMM_LSB_ZEROS(2, 0)
3035 CASE_OPERAND_UIMM_LSB_ZEROS(5, 0)
3036 CASE_OPERAND_UIMM_LSB_ZEROS(6, 0)
3037 CASE_OPERAND_UIMM_LSB_ZEROS(7, 00)
3038 CASE_OPERAND_UIMM_LSB_ZEROS(7, 000)
3039 CASE_OPERAND_UIMM_LSB_ZEROS(8, 00)
3040 CASE_OPERAND_UIMM_LSB_ZEROS(8, 000)
3041 CASE_OPERAND_UIMM_LSB_ZEROS(9, 000)
3042 // clang-format on
3043 case RISCVOp::OPERAND_UIMM5_NONZERO:
3044 Ok = isUInt<5>(x: Imm) && (Imm != 0);
3045 break;
3046 case RISCVOp::OPERAND_UIMM5_GT3:
3047 Ok = isUInt<5>(x: Imm) && (Imm > 3);
3048 break;
3049 case RISCVOp::OPERAND_UIMM5_PLUS1:
3050 Ok = Imm >= 1 && Imm <= 32;
3051 break;
3052 case RISCVOp::OPERAND_UIMM6_PLUS1:
3053 Ok = Imm >= 1 && Imm <= 64;
3054 break;
3055 case RISCVOp::OPERAND_UIMM7_EQ_XLEN:
3056 Ok = Imm == STI.getXLen();
3057 break;
3058 case RISCVOp::OPERAND_UIMM8_GE32:
3059 Ok = isUInt<8>(x: Imm) && Imm >= 32;
3060 break;
3061 case RISCVOp::OPERAND_UIMM9_YBNDSWI:
3062 Ok = RISCV::isValidYBNDSWImm(Imm);
3063 break;
3064 case RISCVOp::OPERAND_SIMM10_LSB0000_NONZERO:
3065 Ok = isShiftedInt<6, 4>(x: Imm) && (Imm != 0);
3066 break;
3067 case RISCVOp::OPERAND_UIMM10_LSB00_NONZERO:
3068 Ok = isShiftedUInt<8, 2>(x: Imm) && (Imm != 0);
3069 break;
3070 case RISCVOp::OPERAND_UIMM16_NONZERO:
3071 Ok = isUInt<16>(x: Imm) && (Imm != 0);
3072 break;
3073 case RISCVOp::OPERAND_THREE:
3074 Ok = Imm == 3;
3075 break;
3076 case RISCVOp::OPERAND_FOUR:
3077 Ok = Imm == 4;
3078 break;
3079 case RISCVOp::OPERAND_IMM5_ZIBI:
3080 Ok = (isUInt<5>(x: Imm) && Imm != 0) || Imm == -1;
3081 break;
3082 // clang-format off
3083 CASE_OPERAND_SIMM(5)
3084 CASE_OPERAND_SIMM(6)
3085 CASE_OPERAND_SIMM(8)
3086 CASE_OPERAND_SIMM(10)
3087 CASE_OPERAND_SIMM(11)
3088 CASE_OPERAND_SIMM(12)
3089 CASE_OPERAND_SIMM(26)
3090 // clang-format on
3091 case RISCVOp::OPERAND_SIMM5_PLUS1:
3092 Ok = Imm >= -15 && Imm <= 16;
3093 break;
3094 case RISCVOp::OPERAND_SIMM5_NONZERO:
3095 Ok = isInt<5>(x: Imm) && (Imm != 0);
3096 break;
3097 case RISCVOp::OPERAND_SIMM6_NONZERO:
3098 Ok = Imm != 0 && isInt<6>(x: Imm);
3099 break;
3100 case RISCVOp::OPERAND_VTYPEI10:
3101 Ok = isUInt<10>(x: Imm) && RISCVVType::isValidVType(VType: Imm);
3102 break;
3103 case RISCVOp::OPERAND_VTYPEI11:
3104 Ok = isUInt<11>(x: Imm) && RISCVVType::isValidVType(VType: Imm);
3105 break;
3106 case RISCVOp::OPERAND_SIMM12_LSB00000:
3107 Ok = isShiftedInt<7, 5>(x: Imm);
3108 break;
3109 case RISCVOp::OPERAND_SIMM16_NONZERO:
3110 Ok = isInt<16>(x: Imm) && (Imm != 0);
3111 break;
3112 case RISCVOp::OPERAND_SIMM20_LI:
3113 Ok = isInt<20>(x: Imm);
3114 break;
3115 case RISCVOp::OPERAND_UIMMLOG2XLEN:
3116 Ok = STI.is64Bit() ? isUInt<6>(x: Imm) : isUInt<5>(x: Imm);
3117 break;
3118 case RISCVOp::OPERAND_UIMMLOG2XLEN_NONZERO:
3119 Ok = STI.is64Bit() ? isUInt<6>(x: Imm) : isUInt<5>(x: Imm);
3120 Ok = Ok && Imm != 0;
3121 break;
3122 case RISCVOp::OPERAND_CLUI_IMM:
3123 Ok = (isUInt<5>(x: Imm) && Imm != 0) || (Imm >= 0xfffe0 && Imm <= 0xfffff);
3124 break;
3125 case RISCVOp::OPERAND_RVKRNUM:
3126 Ok = Imm >= 0 && Imm <= 10;
3127 break;
3128 case RISCVOp::OPERAND_RVKRNUM_0_7:
3129 Ok = Imm >= 0 && Imm <= 7;
3130 break;
3131 case RISCVOp::OPERAND_RVKRNUM_1_10:
3132 Ok = Imm >= 1 && Imm <= 10;
3133 break;
3134 case RISCVOp::OPERAND_RVKRNUM_2_14:
3135 Ok = Imm >= 2 && Imm <= 14;
3136 break;
3137 case RISCVOp::OPERAND_RLIST:
3138 Ok = Imm >= RISCVZC::RA && Imm <= RISCVZC::RA_S0_S11;
3139 break;
3140 case RISCVOp::OPERAND_RLIST_S0:
3141 Ok = Imm >= RISCVZC::RA_S0 && Imm <= RISCVZC::RA_S0_S11;
3142 break;
3143 case RISCVOp::OPERAND_STACKADJ:
3144 Ok = Imm >= 0 && Imm <= 48 && Imm % 16 == 0;
3145 break;
3146 case RISCVOp::OPERAND_FRMARG:
3147 Ok = RISCVFPRndMode::isValidRoundingMode(Mode: Imm);
3148 break;
3149 case RISCVOp::OPERAND_RTZARG:
3150 Ok = Imm == RISCVFPRndMode::RTZ;
3151 break;
3152 case RISCVOp::OPERAND_SMTVType:
3153 Ok = XSMTVTypeMode::isValidSMTVTypeMode(Mode: Imm);
3154 break;
3155 case RISCVOp::OPERAND_SMTI8:
3156 Ok = Imm == XSMTVTypeMode::SMT_I8;
3157 break;
3158 case RISCVOp::OPERAND_COND_CODE:
3159 Ok = Imm >= 0 && Imm < RISCVCC::COND_INVALID;
3160 break;
3161 case RISCVOp::OPERAND_ATOMIC_ORDERING:
3162 Ok = isValidAtomicOrdering(I: Imm);
3163 break;
3164 case RISCVOp::OPERAND_VEC_POLICY:
3165 Ok = (Imm & (RISCVVType::TAIL_AGNOSTIC | RISCVVType::MASK_AGNOSTIC)) ==
3166 Imm;
3167 break;
3168 case RISCVOp::OPERAND_SEW:
3169 Ok = (isUInt<5>(x: Imm) && RISCVVType::isValidSEW(SEW: 1 << Imm));
3170 break;
3171 case RISCVOp::OPERAND_SEW_MASK:
3172 Ok = Imm == 0;
3173 break;
3174 case RISCVOp::OPERAND_VEC_RM:
3175 assert(RISCVII::hasRoundModeOp(Desc.TSFlags));
3176 if (RISCVII::usesVXRM(TSFlags: Desc.TSFlags))
3177 Ok = isUInt<2>(x: Imm);
3178 else
3179 Ok = RISCVFPRndMode::isValidRoundingMode(Mode: Imm);
3180 break;
3181 case RISCVOp::OPERAND_XSFMM_VTYPE:
3182 Ok = RISCVVType::isValidXSfmmVType(VTypeI: Imm);
3183 break;
3184 case RISCVOp::OPERAND_XSFMM_TWIDEN:
3185 Ok = Imm == 1 || Imm == 2 || Imm == 4;
3186 break;
3187 }
3188 if (!Ok) {
3189 ErrInfo = "Invalid immediate";
3190 return false;
3191 }
3192 }
3193 break;
3194 case RISCVOp::OPERAND_SIMM12_LO:
3195 // TODO: We could be stricter about what non-register operands are
3196 // allowed.
3197 if (MO.isReg()) {
3198 ErrInfo = "Expected a non-register operand.";
3199 return false;
3200 }
3201 if (MO.isImm() && !isInt<12>(x: MO.getImm())) {
3202 ErrInfo = "Invalid immediate";
3203 return false;
3204 }
3205 break;
3206 case RISCVOp::OPERAND_UIMM20_LUI:
3207 case RISCVOp::OPERAND_UIMM20_AUIPC:
3208 // TODO: We could be stricter about what non-register operands are
3209 // allowed.
3210 if (MO.isReg()) {
3211 ErrInfo = "Expected a non-register operand.";
3212 return false;
3213 }
3214 if (MO.isImm() && !isUInt<20>(x: MO.getImm())) {
3215 ErrInfo = "Invalid immediate";
3216 return false;
3217 }
3218 break;
3219 case RISCVOp::OPERAND_BARE_SIMM32:
3220 // TODO: We could be stricter about what non-register operands are
3221 // allowed.
3222 if (MO.isReg()) {
3223 ErrInfo = "Expected a non-register operand.";
3224 return false;
3225 }
3226 if (MO.isImm() && !isInt<32>(x: MO.getImm())) {
3227 ErrInfo = "Invalid immediate";
3228 return false;
3229 }
3230 break;
3231 case RISCVOp::OPERAND_AVL:
3232 if (MO.isImm()) {
3233 int64_t Imm = MO.getImm();
3234 // VLMAX is represented as -1.
3235 if (!isUInt<5>(x: Imm) && Imm != -1) {
3236 ErrInfo = "Invalid immediate";
3237 return false;
3238 }
3239 } else if (!MO.isReg()) {
3240 ErrInfo = "Expected a register or immediate operand.";
3241 return false;
3242 }
3243 break;
3244 case RISCVOp::OPERAND_SFB_RHS:
3245 if (!MO.isReg() && !MO.isImm()) {
3246 ErrInfo = "Expected a register or immediate operand.";
3247 return false;
3248 }
3249 break;
3250 }
3251 }
3252
3253 const uint64_t TSFlags = Desc.TSFlags;
3254 if (RISCVII::hasVLOp(TSFlags)) {
3255 const MachineOperand &Op = MI.getOperand(i: RISCVII::getVLOpNum(Desc));
3256 if (!Op.isImm() && !Op.isReg()) {
3257 ErrInfo = "Invalid operand type for VL operand";
3258 return false;
3259 }
3260 if (Op.isReg() && Op.getReg().isValid()) {
3261 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
3262 auto *RC = MRI.getRegClass(Reg: Op.getReg());
3263 if (!RISCV::GPRNoX0RegClass.hasSubClassEq(RC)) {
3264 ErrInfo = "Invalid register class for VL operand";
3265 return false;
3266 }
3267 }
3268 if (!RISCVII::hasSEWOp(TSFlags)) {
3269 ErrInfo = "VL operand w/o SEW operand?";
3270 return false;
3271 }
3272 }
3273 if (RISCVII::hasSEWOp(TSFlags)) {
3274 unsigned OpIdx = RISCVII::getSEWOpNum(Desc);
3275 if (!MI.getOperand(i: OpIdx).isImm()) {
3276 ErrInfo = "SEW value expected to be an immediate";
3277 return false;
3278 }
3279 uint64_t Log2SEW = MI.getOperand(i: OpIdx).getImm();
3280 if (Log2SEW > 31) {
3281 ErrInfo = "Unexpected SEW value";
3282 return false;
3283 }
3284 unsigned SEW = Log2SEW ? 1 << Log2SEW : 8;
3285 if (!RISCVVType::isValidSEW(SEW)) {
3286 ErrInfo = "Unexpected SEW value";
3287 return false;
3288 }
3289 }
3290 if (RISCVII::hasVecPolicyOp(TSFlags)) {
3291 unsigned OpIdx = RISCVII::getVecPolicyOpNum(Desc);
3292 if (!MI.getOperand(i: OpIdx).isImm()) {
3293 ErrInfo = "Policy operand expected to be an immediate";
3294 return false;
3295 }
3296 uint64_t Policy = MI.getOperand(i: OpIdx).getImm();
3297 if (Policy > (RISCVVType::TAIL_AGNOSTIC | RISCVVType::MASK_AGNOSTIC)) {
3298 ErrInfo = "Invalid Policy Value";
3299 return false;
3300 }
3301 if (!RISCVII::hasVLOp(TSFlags)) {
3302 ErrInfo = "policy operand w/o VL operand?";
3303 return false;
3304 }
3305
3306 // VecPolicy operands can only exist on instructions with passthru/merge
3307 // arguments. Note that not all arguments with passthru have vec policy
3308 // operands- some instructions have implicit policies.
3309 unsigned UseOpIdx;
3310 if (!MI.isRegTiedToUseOperand(DefOpIdx: 0, UseOpIdx: &UseOpIdx)) {
3311 ErrInfo = "policy operand w/o tied operand?";
3312 return false;
3313 }
3314 }
3315
3316 if (int Idx = RISCVII::getFRMOpNum(Desc);
3317 Idx >= 0 && MI.getOperand(i: Idx).getImm() == RISCVFPRndMode::DYN &&
3318 !MI.readsRegister(Reg: RISCV::FRM, /*TRI=*/nullptr)) {
3319 ErrInfo = "dynamic rounding mode should read FRM";
3320 return false;
3321 }
3322
3323 return true;
3324}
3325
3326bool RISCVInstrInfo::canFoldIntoAddrMode(const MachineInstr &MemI, Register Reg,
3327 const MachineInstr &AddrI,
3328 ExtAddrMode &AM) const {
3329 switch (MemI.getOpcode()) {
3330 default:
3331 return false;
3332 case RISCV::LB:
3333 case RISCV::LBU:
3334 case RISCV::LH:
3335 case RISCV::LH_INX:
3336 case RISCV::LHU:
3337 case RISCV::LW:
3338 case RISCV::LW_INX:
3339 case RISCV::LWU:
3340 case RISCV::LD:
3341 case RISCV::LD_RV32:
3342 case RISCV::FLH:
3343 case RISCV::FLW:
3344 case RISCV::FLD:
3345 case RISCV::SB:
3346 case RISCV::SH:
3347 case RISCV::SH_INX:
3348 case RISCV::SW:
3349 case RISCV::SW_INX:
3350 case RISCV::SD:
3351 case RISCV::SD_RV32:
3352 case RISCV::FSH:
3353 case RISCV::FSW:
3354 case RISCV::FSD:
3355 break;
3356 }
3357
3358 if (MemI.getOperand(i: 0).getReg() == Reg)
3359 return false;
3360
3361 if (AddrI.getOpcode() != RISCV::ADDI || !AddrI.getOperand(i: 1).isReg() ||
3362 !AddrI.getOperand(i: 2).isImm())
3363 return false;
3364
3365 int64_t OldOffset = MemI.getOperand(i: 2).getImm();
3366 int64_t Disp = AddrI.getOperand(i: 2).getImm();
3367 int64_t NewOffset = OldOffset + Disp;
3368 if (!STI.is64Bit())
3369 NewOffset = SignExtend64<32>(x: NewOffset);
3370
3371 if (!isInt<12>(x: NewOffset))
3372 return false;
3373
3374 AM.BaseReg = AddrI.getOperand(i: 1).getReg();
3375 AM.ScaledReg = 0;
3376 AM.Scale = 0;
3377 AM.Displacement = NewOffset;
3378 AM.Form = ExtAddrMode::Formula::Basic;
3379 return true;
3380}
3381
3382MachineInstr *RISCVInstrInfo::emitLdStWithAddr(MachineInstr &MemI,
3383 const ExtAddrMode &AM) const {
3384
3385 const DebugLoc &DL = MemI.getDebugLoc();
3386 MachineBasicBlock &MBB = *MemI.getParent();
3387
3388 assert(AM.ScaledReg == 0 && AM.Scale == 0 &&
3389 "Addressing mode not supported for folding");
3390
3391 return BuildMI(BB&: MBB, I&: MemI, MIMD: DL, MCID: get(Opcode: MemI.getOpcode()))
3392 .addReg(RegNo: MemI.getOperand(i: 0).getReg(), Flags: getDefRegState(B: MemI.mayLoad()))
3393 .addReg(RegNo: AM.BaseReg)
3394 .addImm(Val: AM.Displacement)
3395 .setMemRefs(MemI.memoperands())
3396 .setMIFlags(MemI.getFlags());
3397}
3398
3399// TODO: At the moment, MIPS introduced paring of instructions operating with
3400// word or double word. This should be extended with more instructions when more
3401// vendors support load/store pairing.
3402bool RISCVInstrInfo::isPairableLdStInstOpc(unsigned Opc) {
3403 switch (Opc) {
3404 default:
3405 return false;
3406 case RISCV::SW:
3407 case RISCV::SD:
3408 case RISCV::LD:
3409 case RISCV::LW:
3410 return true;
3411 }
3412}
3413
3414bool RISCVInstrInfo::isLdStSafeToPair(const MachineInstr &LdSt,
3415 const TargetRegisterInfo *TRI) {
3416 // If this is a volatile load/store, don't mess with it.
3417 if (LdSt.hasOrderedMemoryRef() || LdSt.getNumExplicitOperands() != 3)
3418 return false;
3419
3420 if (LdSt.getOperand(i: 1).isFI())
3421 return true;
3422
3423 assert(LdSt.getOperand(1).isReg() && "Expected a reg operand.");
3424 // Can't cluster if the instruction modifies the base register
3425 // or it is update form. e.g. ld x5,8(x5)
3426 if (LdSt.modifiesRegister(Reg: LdSt.getOperand(i: 1).getReg(), TRI))
3427 return false;
3428
3429 if (!LdSt.getOperand(i: 2).isImm())
3430 return false;
3431
3432 return true;
3433}
3434
3435bool RISCVInstrInfo::getMemOperandsWithOffsetWidth(
3436 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps,
3437 int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
3438 const TargetRegisterInfo *TRI) const {
3439 if (!LdSt.mayLoadOrStore())
3440 return false;
3441
3442 // Conservatively, only handle scalar loads/stores for now.
3443 switch (LdSt.getOpcode()) {
3444 case RISCV::LB:
3445 case RISCV::LBU:
3446 case RISCV::SB:
3447 case RISCV::LH:
3448 case RISCV::LH_INX:
3449 case RISCV::LHU:
3450 case RISCV::FLH:
3451 case RISCV::SH:
3452 case RISCV::SH_INX:
3453 case RISCV::FSH:
3454 case RISCV::LW:
3455 case RISCV::LW_INX:
3456 case RISCV::LWU:
3457 case RISCV::FLW:
3458 case RISCV::SW:
3459 case RISCV::SW_INX:
3460 case RISCV::FSW:
3461 case RISCV::LD:
3462 case RISCV::LD_RV32:
3463 case RISCV::FLD:
3464 case RISCV::SD:
3465 case RISCV::SD_RV32:
3466 case RISCV::FSD:
3467 break;
3468 default:
3469 return false;
3470 }
3471 const MachineOperand *BaseOp;
3472 OffsetIsScalable = false;
3473 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI))
3474 return false;
3475 BaseOps.push_back(Elt: BaseOp);
3476 return true;
3477}
3478
3479// TODO: This was copied from SIInstrInfo. Could it be lifted to a common
3480// helper?
3481static bool memOpsHaveSameBasePtr(const MachineInstr &MI1,
3482 ArrayRef<const MachineOperand *> BaseOps1,
3483 const MachineInstr &MI2,
3484 ArrayRef<const MachineOperand *> BaseOps2) {
3485 // Only examine the first "base" operand of each instruction, on the
3486 // assumption that it represents the real base address of the memory access.
3487 // Other operands are typically offsets or indices from this base address.
3488 if (BaseOps1.front()->isIdenticalTo(Other: *BaseOps2.front()))
3489 return true;
3490
3491 if (!MI1.hasOneMemOperand() || !MI2.hasOneMemOperand())
3492 return false;
3493
3494 auto MO1 = *MI1.memoperands_begin();
3495 auto MO2 = *MI2.memoperands_begin();
3496 if (MO1->getAddrSpace() != MO2->getAddrSpace())
3497 return false;
3498
3499 auto Base1 = MO1->getValue();
3500 auto Base2 = MO2->getValue();
3501 if (!Base1 || !Base2)
3502 return false;
3503 Base1 = getUnderlyingObject(V: Base1);
3504 Base2 = getUnderlyingObject(V: Base2);
3505
3506 if (isa<UndefValue>(Val: Base1) || isa<UndefValue>(Val: Base2))
3507 return false;
3508
3509 return Base1 == Base2;
3510}
3511
3512bool RISCVInstrInfo::shouldClusterMemOps(
3513 ArrayRef<const MachineOperand *> BaseOps1, int64_t Offset1,
3514 bool OffsetIsScalable1, ArrayRef<const MachineOperand *> BaseOps2,
3515 int64_t Offset2, bool OffsetIsScalable2, unsigned ClusterSize,
3516 unsigned NumBytes) const {
3517 // If the mem ops (to be clustered) do not have the same base ptr, then they
3518 // should not be clustered
3519 if (!BaseOps1.empty() && !BaseOps2.empty()) {
3520 const MachineInstr &FirstLdSt = *BaseOps1.front()->getParent();
3521 const MachineInstr &SecondLdSt = *BaseOps2.front()->getParent();
3522 if (!memOpsHaveSameBasePtr(MI1: FirstLdSt, BaseOps1, MI2: SecondLdSt, BaseOps2))
3523 return false;
3524 } else if (!BaseOps1.empty() || !BaseOps2.empty()) {
3525 // If only one base op is empty, they do not have the same base ptr
3526 return false;
3527 }
3528
3529 unsigned CacheLineSize =
3530 BaseOps1.front()->getParent()->getMF()->getSubtarget().getCacheLineSize();
3531 // Assume a cache line size of 64 bytes if no size is set in RISCVSubtarget.
3532 CacheLineSize = CacheLineSize ? CacheLineSize : 64;
3533 // Cluster if the memory operations are on the same or a neighbouring cache
3534 // line, but limit the maximum ClusterSize to avoid creating too much
3535 // additional register pressure.
3536 return ClusterSize <= 4 && std::abs(i: Offset1 - Offset2) < CacheLineSize;
3537}
3538
3539// Set BaseReg (the base register operand), Offset (the byte offset being
3540// accessed) and the access Width of the passed instruction that reads/writes
3541// memory. Returns false if the instruction does not read/write memory or the
3542// BaseReg/Offset/Width can't be determined. Is not guaranteed to always
3543// recognise base operands and offsets in all cases.
3544// TODO: Add an IsScalable bool ref argument (like the equivalent AArch64
3545// function) and set it as appropriate.
3546bool RISCVInstrInfo::getMemOperandWithOffsetWidth(
3547 const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset,
3548 LocationSize &Width, const TargetRegisterInfo *TRI) const {
3549 if (!LdSt.mayLoadOrStore())
3550 return false;
3551
3552 // Here we assume the standard RISC-V ISA, which uses a base+offset
3553 // addressing mode. You'll need to relax these conditions to support custom
3554 // load/store instructions.
3555 if (LdSt.getNumExplicitOperands() != 3)
3556 return false;
3557 if ((!LdSt.getOperand(i: 1).isReg() && !LdSt.getOperand(i: 1).isFI()) ||
3558 !LdSt.getOperand(i: 2).isImm())
3559 return false;
3560
3561 if (!LdSt.hasOneMemOperand())
3562 return false;
3563
3564 Width = (*LdSt.memoperands_begin())->getSize();
3565 BaseReg = &LdSt.getOperand(i: 1);
3566 Offset = LdSt.getOperand(i: 2).getImm();
3567 return true;
3568}
3569
3570bool RISCVInstrInfo::areMemAccessesTriviallyDisjoint(
3571 const MachineInstr &MIa, const MachineInstr &MIb) const {
3572 assert(MIa.mayLoadOrStore() && "MIa must be a load or store.");
3573 assert(MIb.mayLoadOrStore() && "MIb must be a load or store.");
3574
3575 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() ||
3576 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef())
3577 return false;
3578
3579 // Retrieve the base register, offset from the base register and width. Width
3580 // is the size of memory that is being loaded/stored (e.g. 1, 2, 4). If
3581 // base registers are identical, and the offset of a lower memory access +
3582 // the width doesn't overlap the offset of a higher memory access,
3583 // then the memory accesses are different.
3584 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
3585 const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr;
3586 int64_t OffsetA = 0, OffsetB = 0;
3587 LocationSize WidthA = LocationSize::precise(Value: 0),
3588 WidthB = LocationSize::precise(Value: 0);
3589 if (getMemOperandWithOffsetWidth(LdSt: MIa, BaseReg&: BaseOpA, Offset&: OffsetA, Width&: WidthA, TRI) &&
3590 getMemOperandWithOffsetWidth(LdSt: MIb, BaseReg&: BaseOpB, Offset&: OffsetB, Width&: WidthB, TRI)) {
3591 if (BaseOpA->isIdenticalTo(Other: *BaseOpB)) {
3592 int LowOffset = std::min(a: OffsetA, b: OffsetB);
3593 int HighOffset = std::max(a: OffsetA, b: OffsetB);
3594 LocationSize LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
3595 if (LowWidth.hasValue() &&
3596 LowOffset + (int)LowWidth.getValue() <= HighOffset)
3597 return true;
3598 }
3599 }
3600 return false;
3601}
3602
3603std::pair<unsigned, unsigned>
3604RISCVInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
3605 const unsigned Mask = RISCVII::MO_DIRECT_FLAG_MASK;
3606 return std::make_pair(x: TF & Mask, y: TF & ~Mask);
3607}
3608
3609ArrayRef<std::pair<unsigned, const char *>>
3610RISCVInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
3611 using namespace RISCVII;
3612 static const std::pair<unsigned, const char *> TargetFlags[] = {
3613 {MO_CALL, "riscv-call"},
3614 {MO_LO, "riscv-lo"},
3615 {MO_HI, "riscv-hi"},
3616 {MO_PCREL_LO, "riscv-pcrel-lo"},
3617 {MO_PCREL_HI, "riscv-pcrel-hi"},
3618 {MO_GOT_HI, "riscv-got-hi"},
3619 {MO_TPREL_LO, "riscv-tprel-lo"},
3620 {MO_TPREL_HI, "riscv-tprel-hi"},
3621 {MO_TPREL_ADD, "riscv-tprel-add"},
3622 {MO_TLS_GOT_HI, "riscv-tls-got-hi"},
3623 {MO_TLS_GD_HI, "riscv-tls-gd-hi"},
3624 {MO_TLSDESC_HI, "riscv-tlsdesc-hi"},
3625 {MO_TLSDESC_LOAD_LO, "riscv-tlsdesc-load-lo"},
3626 {MO_TLSDESC_ADD_LO, "riscv-tlsdesc-add-lo"},
3627 {MO_TLSDESC_CALL, "riscv-tlsdesc-call"},
3628 {MO_QC_ACCESS, "riscv-qc-access"},
3629 };
3630 return ArrayRef(TargetFlags);
3631}
3632bool RISCVInstrInfo::isFunctionSafeToOutlineFrom(
3633 MachineFunction &MF, bool OutlineFromLinkOnceODRs) const {
3634 const Function &F = MF.getFunction();
3635
3636 // Can F be deduplicated by the linker? If it can, don't outline from it.
3637 if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage())
3638 return false;
3639
3640 // Don't outline from functions with section markings; the program could
3641 // expect that all the code is in the named section.
3642 if (F.hasSection())
3643 return false;
3644
3645 // It's safe to outline from MF.
3646 return true;
3647}
3648
3649bool RISCVInstrInfo::isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
3650 unsigned &Flags) const {
3651 // More accurate safety checking is done in getOutliningCandidateInfo.
3652 return TargetInstrInfo::isMBBSafeToOutlineFrom(MBB, Flags);
3653}
3654
3655// Enum values indicating how an outlined call should be constructed.
3656enum MachineOutlinerConstructionID {
3657 MachineOutlinerTailCall,
3658 MachineOutlinerDefault,
3659 MachineOutlinerRegSave
3660};
3661
3662bool RISCVInstrInfo::shouldOutlineFromFunctionByDefault(
3663 MachineFunction &MF) const {
3664 return MF.getFunction().hasMinSize();
3665}
3666
3667static bool isCandidatePatchable(const MachineBasicBlock &MBB) {
3668 const MachineFunction *MF = MBB.getParent();
3669 const Function &F = MF->getFunction();
3670 return F.getFnAttribute(Kind: "fentry-call").getValueAsBool() ||
3671 F.hasFnAttribute(Kind: "patchable-function-entry");
3672}
3673
3674static bool isMIReadsReg(const MachineInstr &MI, const TargetRegisterInfo *TRI,
3675 MCRegister RegNo) {
3676 return MI.readsRegister(Reg: RegNo, TRI) ||
3677 MI.getDesc().hasImplicitUseOfPhysReg(Reg: RegNo);
3678}
3679
3680static bool isMIModifiesReg(const MachineInstr &MI,
3681 const TargetRegisterInfo *TRI, MCRegister RegNo) {
3682 return MI.modifiesRegister(Reg: RegNo, TRI) ||
3683 MI.getDesc().hasImplicitDefOfPhysReg(Reg: RegNo);
3684}
3685
3686static bool cannotInsertTailCall(const MachineBasicBlock &MBB) {
3687 if (!MBB.back().isReturn())
3688 return true;
3689 if (isCandidatePatchable(MBB))
3690 return true;
3691
3692 // If the candidate reads the pre-set register
3693 // that can be used for expanding PseudoTAIL instruction,
3694 // then we cannot insert tail call.
3695 const TargetSubtargetInfo &STI = MBB.getParent()->getSubtarget();
3696 MCRegister TailExpandUseRegNo =
3697 RISCVII::getTailExpandUseRegNo(FeatureBits: STI.getFeatureBits());
3698 for (const MachineInstr &MI : MBB) {
3699 if (isMIReadsReg(MI, TRI: STI.getRegisterInfo(), RegNo: TailExpandUseRegNo))
3700 return true;
3701 if (isMIModifiesReg(MI, TRI: STI.getRegisterInfo(), RegNo: TailExpandUseRegNo))
3702 break;
3703 }
3704 return false;
3705}
3706
3707static Register findRegisterToSaveX5To(outliner::Candidate &C,
3708 const TargetRegisterInfo &TRI) {
3709 // Candidate registers for saving X5: t1-t6
3710 static const MCPhysReg TempRegs[] = {
3711 RISCV::X6, // t1
3712 RISCV::X7, // t2
3713 RISCV::X28, // t3
3714 RISCV::X29, // t4
3715 RISCV::X30, // t5
3716 RISCV::X31 // t6
3717 };
3718
3719 const MachineFunction *MF = C.getMF();
3720 const MachineRegisterInfo &MRI = MF->getRegInfo();
3721
3722 for (MCPhysReg Reg : TempRegs) {
3723 if (MRI.isReserved(PhysReg: Reg))
3724 continue;
3725
3726 if (C.isAvailableAcrossAndOutOfSeq(Reg, TRI) &&
3727 C.isAvailableInsideSeq(Reg, TRI)) {
3728 return Reg;
3729 }
3730 }
3731
3732 return Register();
3733}
3734
3735bool RISCVInstrInfo::analyzeCandidate(outliner::Candidate &C) const {
3736 // If the expansion register for tail calls is live across the candidate
3737 // outlined call site, we cannot outline that candidate as the expansion
3738 // would clobber the register.
3739 MCRegister TailExpandUseReg =
3740 RISCVII::getTailExpandUseRegNo(FeatureBits: STI.getFeatureBits());
3741 if (C.back().isReturn() &&
3742 !C.isAvailableAcrossAndOutOfSeq(Reg: TailExpandUseReg, TRI: RegInfo)) {
3743 LLVM_DEBUG(dbgs() << "MBB:\n" << *C.getMBB());
3744 LLVM_DEBUG(dbgs() << "Cannot be outlined between: " << C.front() << "and "
3745 << C.back());
3746 LLVM_DEBUG(dbgs() << "Because the tail-call register is live across "
3747 "the proposed outlined function call\n");
3748 return true;
3749 }
3750
3751 // If last instruction is return then we can rely on
3752 // the verification already performed in the getOutliningTypeImpl.
3753 if (C.back().isReturn()) {
3754 assert(!cannotInsertTailCall(*C.getMBB()) &&
3755 "The candidate who uses return instruction must be outlined "
3756 "using tail call");
3757 return false;
3758 }
3759
3760 // Filter out candidates where the X5 register (t0) can't be used to setup
3761 // the function call.
3762 if (!C.isAvailableInsideSeq(Reg: RISCV::X5, TRI: RegInfo))
3763 return true;
3764
3765 // If X5 is available in the region, use X5 directly (MachineOutlinerDefault).
3766 if (C.isAvailableAcrossAndOutOfSeq(Reg: RISCV::X5, TRI: RegInfo))
3767 return false;
3768
3769 // Otherwise, try to save X5 into t1-t6 (MachineOutlinerRegSave).
3770 if (OutlinerEnableRegSave && findRegisterToSaveX5To(C, TRI: RegInfo))
3771 return false;
3772
3773 return true;
3774}
3775
3776std::optional<std::unique_ptr<outliner::OutlinedFunction>>
3777RISCVInstrInfo::getOutliningCandidateInfo(
3778 const MachineModuleInfo &MMI,
3779 std::vector<outliner::Candidate> &RepeatedSequenceLocs,
3780 unsigned MinRepeats) const {
3781
3782 // Analyze each candidate and erase the ones that are not viable.
3783 llvm::erase_if(C&: RepeatedSequenceLocs, P: [this](auto Candidate) {
3784 return analyzeCandidate(C&: Candidate);
3785 });
3786
3787 // If the sequence doesn't have enough candidates left, then we're done.
3788 if (RepeatedSequenceLocs.size() < MinRepeats)
3789 return std::nullopt;
3790
3791 // Each RepeatedSequenceLoc is identical.
3792 outliner::Candidate &Candidate = RepeatedSequenceLocs[0];
3793 unsigned InstrSizeCExt =
3794 Candidate.getMF()->getSubtarget<RISCVSubtarget>().hasStdExtZca() ? 2 : 4;
3795 unsigned CallOverhead = 0, FrameOverhead = 0;
3796
3797 // Count the number of CFI instructions in the candidate, if present.
3798 unsigned CFICount = 0;
3799 for (auto &I : Candidate) {
3800 if (I.isCFIInstruction())
3801 CFICount++;
3802 }
3803
3804 // Ensure CFI coverage matches: comparing the number of CFIs in the candidate
3805 // with the total number of CFIs in the parent function for each candidate.
3806 // Outlining only a subset of a function’s CFIs would split the unwind state
3807 // across two code regions and lead to incorrect address offsets between the
3808 // outlined body and the remaining code. To preserve correct unwind info, we
3809 // only outline when all CFIs in the function can be outlined together.
3810 for (outliner::Candidate &C : RepeatedSequenceLocs) {
3811 std::vector<MCCFIInstruction> CFIInstructions =
3812 C.getMF()->getFrameInstructions();
3813
3814 if (CFICount > 0 && CFICount != CFIInstructions.size())
3815 return std::nullopt;
3816 }
3817
3818 MachineOutlinerConstructionID MOCI = MachineOutlinerDefault;
3819 if (Candidate.back().isReturn()) {
3820 MOCI = MachineOutlinerTailCall;
3821 // tail call = auipc + jalr in the worst case without linker relaxation.
3822 // FIXME: This code suggests the JALR can be compressed - how?
3823 CallOverhead = 4 + InstrSizeCExt;
3824 // Using tail call we move ret instruction from caller to callee.
3825 FrameOverhead = 0;
3826 } else {
3827 // call t0, function = 8 bytes.
3828 CallOverhead = 8;
3829 // jr t0 = 4 bytes, 2 bytes if compressed instructions are enabled.
3830 FrameOverhead = InstrSizeCExt;
3831 }
3832
3833 // If we have CFI instructions, we can only outline if the outlined section
3834 // can be a tail call.
3835 if (MOCI != MachineOutlinerTailCall && CFICount > 0)
3836 return std::nullopt;
3837
3838 if (OutlinerEnableRegSave && MOCI == MachineOutlinerDefault) {
3839 // Set per-candidate overhead based on X5 availability
3840 for (auto &C : RepeatedSequenceLocs) {
3841
3842 if (C.isAvailableAcrossAndOutOfSeq(Reg: RISCV::X5, TRI: RegInfo)) {
3843 // X5 is available, just need the call
3844 unsigned CandCallOverhead = 8;
3845 C.setCallInfo(CID: MachineOutlinerDefault, CO: CandCallOverhead);
3846 } else {
3847 // X5 unavailable, need save + call + restore
3848 // Save (2-4) + Call (8) + Restore (2-4)
3849 unsigned CandCallOverhead = InstrSizeCExt + 8 + InstrSizeCExt;
3850 C.setCallInfo(CID: MachineOutlinerRegSave, CO: CandCallOverhead);
3851 }
3852 }
3853 } else {
3854 for (auto &C : RepeatedSequenceLocs)
3855 C.setCallInfo(CID: MOCI, CO: CallOverhead);
3856 }
3857
3858 unsigned SequenceSize = 0;
3859 for (auto &MI : Candidate)
3860 SequenceSize += getInstSizeInBytes(MI);
3861
3862 return std::make_unique<outliner::OutlinedFunction>(
3863 args&: RepeatedSequenceLocs, args&: SequenceSize, args&: FrameOverhead, args&: MOCI);
3864}
3865
3866outliner::InstrType
3867RISCVInstrInfo::getOutliningTypeImpl(const MachineModuleInfo &MMI,
3868 MachineBasicBlock::iterator &MBBI,
3869 unsigned Flags) const {
3870 MachineInstr &MI = *MBBI;
3871 MachineBasicBlock *MBB = MI.getParent();
3872 const TargetRegisterInfo *TRI =
3873 MBB->getParent()->getSubtarget().getRegisterInfo();
3874 const auto &F = MI.getMF()->getFunction();
3875
3876 // We can only outline CFI instructions if we will tail call the outlined
3877 // function, or fix up the CFI offsets. Currently, CFI instructions are
3878 // outlined only if in a tail call.
3879 if (MI.isCFIInstruction())
3880 return outliner::InstrType::Legal;
3881
3882 if (cannotInsertTailCall(MBB: *MBB) &&
3883 (MI.isReturn() || isMIModifiesReg(MI, TRI, RegNo: RISCV::X5)))
3884 return outliner::InstrType::Illegal;
3885
3886 // Make sure the operands don't reference something unsafe.
3887 for (const auto &MO : MI.operands()) {
3888
3889 // pcrel-hi and pcrel-lo can't put in separate sections, filter that out
3890 // if any possible.
3891 if (MO.getTargetFlags() == RISCVII::MO_PCREL_LO &&
3892 (MI.getMF()->getTarget().getFunctionSections() || F.hasComdat() ||
3893 F.hasSection() || F.getSectionPrefix()))
3894 return outliner::InstrType::Illegal;
3895 }
3896
3897 if (isLPAD(MI))
3898 return outliner::InstrType::Illegal;
3899
3900 return outliner::InstrType::Legal;
3901}
3902
3903void RISCVInstrInfo::buildOutlinedFrame(
3904 MachineBasicBlock &MBB, MachineFunction &MF,
3905 const outliner::OutlinedFunction &OF) const {
3906
3907 if (OF.FrameConstructionID == MachineOutlinerTailCall)
3908 return;
3909
3910 MBB.addLiveIn(PhysReg: RISCV::X5);
3911
3912 // Add in a return instruction to the end of the outlined frame.
3913 MBB.insert(I: MBB.end(), MI: BuildMI(MF, MIMD: DebugLoc(), MCID: get(Opcode: RISCV::JALR))
3914 .addReg(RegNo: RISCV::X0, Flags: RegState::Define)
3915 .addReg(RegNo: RISCV::X5)
3916 .addImm(Val: 0));
3917}
3918
3919MachineBasicBlock::iterator RISCVInstrInfo::insertOutlinedCall(
3920 Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It,
3921 MachineFunction &MF, outliner::Candidate &C) const {
3922
3923 if (C.CallConstructionID == MachineOutlinerTailCall) {
3924 It = MBB.insert(I: It, MI: BuildMI(MF, MIMD: DebugLoc(), MCID: get(Opcode: RISCV::PseudoTAIL))
3925 .addGlobalAddress(GV: M.getNamedValue(Name: MF.getName()),
3926 /*Offset=*/0, TargetFlags: RISCVII::MO_CALL));
3927 return It;
3928 }
3929
3930 if (C.CallConstructionID == MachineOutlinerRegSave) {
3931 Register SaveReg = findRegisterToSaveX5To(C, TRI: RegInfo);
3932 assert(SaveReg && "Cannot find an available register to save/restore X5.");
3933
3934 // Save: ADDI SaveReg, X5, 0 (equivalent to MV SaveReg, X5)
3935 It = MBB.insert(I: It, MI: BuildMI(MF, MIMD: DebugLoc(), MCID: get(Opcode: RISCV::ADDI), DestReg: SaveReg)
3936 .addReg(RegNo: RISCV::X5)
3937 .addImm(Val: 0));
3938 It++;
3939
3940 // Call: PseudoCALLReg X5
3941 It = MBB.insert(
3942 I: It, MI: BuildMI(MF, MIMD: DebugLoc(), MCID: get(Opcode: RISCV::PseudoCALLReg), DestReg: RISCV::X5)
3943 .addGlobalAddress(GV: M.getNamedValue(Name: MF.getName()), Offset: 0,
3944 TargetFlags: RISCVII::MO_CALL));
3945 MachineBasicBlock::iterator CallPt = It;
3946 It++;
3947
3948 // Restore: ADDI X5, SaveReg, 0 (equivalent to MV X5, SaveReg)
3949 It = MBB.insert(I: It, MI: BuildMI(MF, MIMD: DebugLoc(), MCID: get(Opcode: RISCV::ADDI), DestReg: RISCV::X5)
3950 .addReg(RegNo: SaveReg)
3951 .addImm(Val: 0));
3952
3953 return CallPt;
3954 }
3955
3956 // Add in a call instruction to the outlined function at the given location.
3957 It = MBB.insert(I: It,
3958 MI: BuildMI(MF, MIMD: DebugLoc(), MCID: get(Opcode: RISCV::PseudoCALLReg), DestReg: RISCV::X5)
3959 .addGlobalAddress(GV: M.getNamedValue(Name: MF.getName()), Offset: 0,
3960 TargetFlags: RISCVII::MO_CALL));
3961 return It;
3962}
3963
3964void RISCVInstrInfo::buildClearRegister(Register Reg, MachineBasicBlock &MBB,
3965 MachineBasicBlock::iterator Iter,
3966 DebugLoc &DL,
3967 bool AllowSideEffects) const {
3968
3969 const MachineFunction &MF = *MBB.getParent();
3970 const RISCVRegisterInfo &TRI = *STI.getRegisterInfo();
3971
3972 if (TRI.isGeneralPurposeRegister(MF, Reg)) {
3973 BuildMI(BB&: MBB, I: Iter, MIMD: DL, MCID: get(Opcode: RISCV::PseudoClearGPR), DestReg: Reg);
3974 } else if (RISCV::FPR32RegClass.contains(Reg)) {
3975 BuildMI(BB&: MBB, I: Iter, MIMD: DL, MCID: get(Opcode: RISCV::PseudoClearFPR32), DestReg: Reg);
3976 } else if (RISCV::FPR64RegClass.contains(Reg)) {
3977 BuildMI(BB&: MBB, I: Iter, MIMD: DL, MCID: get(Opcode: RISCV::PseudoClearFPR64), DestReg: Reg);
3978 } else if (RISCV::FPR128RegClass.contains(Reg)) {
3979 BuildMI(BB&: MBB, I: Iter, MIMD: DL, MCID: get(Opcode: RISCV::PseudoClearFPR128), DestReg: Reg);
3980 } else {
3981 llvm::reportFatalInternalError(
3982 reason: "buildClearRegister is not implemented for vector registers");
3983 }
3984}
3985
3986std::optional<RegImmPair> RISCVInstrInfo::isAddImmediate(const MachineInstr &MI,
3987 Register Reg) const {
3988 // TODO: Handle cases where Reg is a super- or sub-register of the
3989 // destination register.
3990 const MachineOperand &Op0 = MI.getOperand(i: 0);
3991 if (!Op0.isReg() || Reg != Op0.getReg())
3992 return std::nullopt;
3993
3994 // Don't consider ADDIW as a candidate because the caller may not be aware
3995 // of its sign extension behaviour.
3996 if (MI.getOpcode() == RISCV::ADDI && MI.getOperand(i: 1).isReg() &&
3997 MI.getOperand(i: 2).isImm())
3998 return RegImmPair{MI.getOperand(i: 1).getReg(), MI.getOperand(i: 2).getImm()};
3999
4000 return std::nullopt;
4001}
4002
4003// MIR printer helper function to annotate Operands with a comment.
4004std::string RISCVInstrInfo::createMIROperandComment(
4005 const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx,
4006 const TargetRegisterInfo *TRI) const {
4007 // Print a generic comment for this operand if there is one.
4008 std::string GenericComment =
4009 TargetInstrInfo::createMIROperandComment(MI, Op, OpIdx, TRI);
4010 if (!GenericComment.empty())
4011 return GenericComment;
4012
4013 const MCInstrDesc &Desc = MI.getDesc();
4014 if (OpIdx >= Desc.getNumOperands())
4015 return std::string();
4016
4017 std::string Comment;
4018 raw_string_ostream OS(Comment);
4019
4020 const MCOperandInfo &OpInfo = Desc.operands()[OpIdx];
4021
4022 // Print the full VType operand of vsetvli/vsetivli instructions, and the SEW
4023 // operand of vector codegen pseudos.
4024 switch (OpInfo.OperandType) {
4025 case RISCVOp::OPERAND_VTYPEI10:
4026 case RISCVOp::OPERAND_VTYPEI11: {
4027 unsigned Imm = Op.getImm();
4028 RISCVVType::printVType(VType: Imm, OS);
4029 break;
4030 }
4031 case RISCVOp::OPERAND_XSFMM_VTYPE: {
4032 unsigned Imm = Op.getImm();
4033 RISCVVType::printXSfmmVType(VType: Imm, OS);
4034 break;
4035 }
4036 case RISCVOp::OPERAND_XSFMM_TWIDEN: {
4037 unsigned Imm = Op.getImm();
4038 OS << "w" << Imm;
4039 break;
4040 }
4041 case RISCVOp::OPERAND_SEW:
4042 case RISCVOp::OPERAND_SEW_MASK: {
4043 unsigned Log2SEW = Op.getImm();
4044 unsigned SEW = Log2SEW ? 1 << Log2SEW : 8;
4045 assert(RISCVVType::isValidSEW(SEW) && "Unexpected SEW");
4046 OS << "e" << SEW;
4047 break;
4048 }
4049 case RISCVOp::OPERAND_VEC_POLICY: {
4050 unsigned Policy = Op.getImm();
4051 assert(Policy <= (RISCVVType::TAIL_AGNOSTIC | RISCVVType::MASK_AGNOSTIC) &&
4052 "Invalid Policy Value");
4053 OS << (Policy & RISCVVType::TAIL_AGNOSTIC ? "ta" : "tu") << ", "
4054 << (Policy & RISCVVType::MASK_AGNOSTIC ? "ma" : "mu");
4055 break;
4056 }
4057 case RISCVOp::OPERAND_AVL:
4058 if (Op.isImm() && Op.getImm() == -1)
4059 OS << "vl=VLMAX";
4060 else
4061 OS << "vl";
4062 break;
4063 case RISCVOp::OPERAND_VEC_RM:
4064 if (RISCVII::usesVXRM(TSFlags: Desc.TSFlags)) {
4065 assert(RISCVVXRndMode::isValidRoundingMode(Op.getImm()));
4066 auto VXRM = static_cast<RISCVVXRndMode::RoundingMode>(Op.getImm());
4067 OS << "vxrm=" << RISCVVXRndMode::roundingModeToString(RndMode: VXRM);
4068 } else {
4069 assert(RISCVFPRndMode::isValidRoundingMode(Op.getImm()));
4070 auto FRM = static_cast<RISCVFPRndMode::RoundingMode>(Op.getImm());
4071 OS << "frm=" << RISCVFPRndMode::roundingModeToString(RndMode: FRM);
4072 }
4073 break;
4074 }
4075
4076 return Comment;
4077}
4078
4079// clang-format off
4080#define CASE_RVV_OPCODE_UNMASK_LMUL(OP, LMUL) \
4081 RISCV::Pseudo##OP##_##LMUL
4082
4083#define CASE_RVV_OPCODE_MASK_LMUL(OP, LMUL) \
4084 RISCV::Pseudo##OP##_##LMUL##_MASK
4085
4086#define CASE_RVV_OPCODE_LMUL(OP, LMUL) \
4087 CASE_RVV_OPCODE_UNMASK_LMUL(OP, LMUL): \
4088 case CASE_RVV_OPCODE_MASK_LMUL(OP, LMUL)
4089
4090#define CASE_RVV_OPCODE_UNMASK_WIDEN(OP) \
4091 CASE_RVV_OPCODE_UNMASK_LMUL(OP, MF8): \
4092 case CASE_RVV_OPCODE_UNMASK_LMUL(OP, MF4): \
4093 case CASE_RVV_OPCODE_UNMASK_LMUL(OP, MF2): \
4094 case CASE_RVV_OPCODE_UNMASK_LMUL(OP, M1): \
4095 case CASE_RVV_OPCODE_UNMASK_LMUL(OP, M2): \
4096 case CASE_RVV_OPCODE_UNMASK_LMUL(OP, M4)
4097
4098#define CASE_RVV_OPCODE_UNMASK(OP) \
4099 CASE_RVV_OPCODE_UNMASK_WIDEN(OP): \
4100 case CASE_RVV_OPCODE_UNMASK_LMUL(OP, M8)
4101
4102#define CASE_RVV_OPCODE_MASK_WIDEN(OP) \
4103 CASE_RVV_OPCODE_MASK_LMUL(OP, MF8): \
4104 case CASE_RVV_OPCODE_MASK_LMUL(OP, MF4): \
4105 case CASE_RVV_OPCODE_MASK_LMUL(OP, MF2): \
4106 case CASE_RVV_OPCODE_MASK_LMUL(OP, M1): \
4107 case CASE_RVV_OPCODE_MASK_LMUL(OP, M2): \
4108 case CASE_RVV_OPCODE_MASK_LMUL(OP, M4)
4109
4110#define CASE_RVV_OPCODE_MASK(OP) \
4111 CASE_RVV_OPCODE_MASK_WIDEN(OP): \
4112 case CASE_RVV_OPCODE_MASK_LMUL(OP, M8)
4113
4114#define CASE_RVV_OPCODE_WIDEN(OP) \
4115 CASE_RVV_OPCODE_UNMASK_WIDEN(OP): \
4116 case CASE_RVV_OPCODE_MASK_WIDEN(OP)
4117
4118#define CASE_RVV_OPCODE(OP) \
4119 CASE_RVV_OPCODE_UNMASK(OP): \
4120 case CASE_RVV_OPCODE_MASK(OP)
4121// clang-format on
4122
4123// clang-format off
4124#define CASE_VMA_OPCODE_COMMON(OP, TYPE, LMUL) \
4125 RISCV::PseudoV##OP##_##TYPE##_##LMUL
4126
4127#define CASE_VMA_OPCODE_LMULS(OP, TYPE) \
4128 CASE_VMA_OPCODE_COMMON(OP, TYPE, MF8): \
4129 case CASE_VMA_OPCODE_COMMON(OP, TYPE, MF4): \
4130 case CASE_VMA_OPCODE_COMMON(OP, TYPE, MF2): \
4131 case CASE_VMA_OPCODE_COMMON(OP, TYPE, M1): \
4132 case CASE_VMA_OPCODE_COMMON(OP, TYPE, M2): \
4133 case CASE_VMA_OPCODE_COMMON(OP, TYPE, M4): \
4134 case CASE_VMA_OPCODE_COMMON(OP, TYPE, M8)
4135
4136// VFMA instructions are SEW specific.
4137#define CASE_VFMA_OPCODE_COMMON(OP, TYPE, LMUL, SEW) \
4138 RISCV::PseudoV##OP##_##TYPE##_##LMUL##_##SEW
4139
4140#define CASE_VFMA_OPCODE_LMULS_M1(OP, TYPE, SEW) \
4141 CASE_VFMA_OPCODE_COMMON(OP, TYPE, M1, SEW): \
4142 case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M2, SEW): \
4143 case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M4, SEW): \
4144 case CASE_VFMA_OPCODE_COMMON(OP, TYPE, M8, SEW)
4145
4146#define CASE_VFMA_OPCODE_LMULS_MF2(OP, TYPE, SEW) \
4147 CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF2, SEW): \
4148 case CASE_VFMA_OPCODE_LMULS_M1(OP, TYPE, SEW)
4149
4150#define CASE_VFMA_OPCODE_LMULS_MF4(OP, TYPE, SEW) \
4151 CASE_VFMA_OPCODE_COMMON(OP, TYPE, MF4, SEW): \
4152 case CASE_VFMA_OPCODE_LMULS_MF2(OP, TYPE, SEW)
4153
4154#define CASE_VFMA_OPCODE_VV(OP) \
4155 CASE_VFMA_OPCODE_LMULS_MF4(OP, VV, E16): \
4156 case CASE_VFMA_OPCODE_LMULS_MF4(OP##_ALT, VV, E16): \
4157 case CASE_VFMA_OPCODE_LMULS_MF2(OP, VV, E32): \
4158 case CASE_VFMA_OPCODE_LMULS_M1(OP, VV, E64)
4159
4160#define CASE_VFMA_SPLATS(OP) \
4161 CASE_VFMA_OPCODE_LMULS_MF4(OP, VFPR16, E16): \
4162 case CASE_VFMA_OPCODE_LMULS_MF4(OP##_ALT, VFPR16, E16): \
4163 case CASE_VFMA_OPCODE_LMULS_MF2(OP, VFPR32, E32): \
4164 case CASE_VFMA_OPCODE_LMULS_M1(OP, VFPR64, E64)
4165// clang-format on
4166
4167bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI,
4168 unsigned &SrcOpIdx1,
4169 unsigned &SrcOpIdx2) const {
4170 const MCInstrDesc &Desc = MI.getDesc();
4171 if (!Desc.isCommutable())
4172 return false;
4173
4174 switch (MI.getOpcode()) {
4175 case RISCV::TH_MVEQZ:
4176 case RISCV::TH_MVNEZ:
4177 // We can't commute operands if operand 2 (i.e., rs1 in
4178 // mveqz/mvnez rd,rs1,rs2) is the zero-register (as it is
4179 // not valid as the in/out-operand 1).
4180 if (MI.getOperand(i: 2).getReg() == RISCV::X0)
4181 return false;
4182 // Operands 1 and 2 are commutable, if we switch the opcode.
4183 return fixCommutedOpIndices(ResultIdx1&: SrcOpIdx1, ResultIdx2&: SrcOpIdx2, CommutableOpIdx1: 1, CommutableOpIdx2: 2);
4184 case RISCV::QC_SELECTIEQ:
4185 case RISCV::QC_SELECTINE:
4186 case RISCV::QC_SELECTIIEQ:
4187 case RISCV::QC_SELECTIINE:
4188 return fixCommutedOpIndices(ResultIdx1&: SrcOpIdx1, ResultIdx2&: SrcOpIdx2, CommutableOpIdx1: 1, CommutableOpIdx2: 2);
4189 case RISCV::QC_MVEQ:
4190 case RISCV::QC_MVNE:
4191 case RISCV::QC_MVLT:
4192 case RISCV::QC_MVGE:
4193 case RISCV::QC_MVLTU:
4194 case RISCV::QC_MVGEU:
4195 case RISCV::QC_MVEQI:
4196 case RISCV::QC_MVNEI:
4197 case RISCV::QC_MVLTI:
4198 case RISCV::QC_MVGEI:
4199 case RISCV::QC_MVLTUI:
4200 case RISCV::QC_MVGEUI:
4201 return fixCommutedOpIndices(ResultIdx1&: SrcOpIdx1, ResultIdx2&: SrcOpIdx2, CommutableOpIdx1: 1, CommutableOpIdx2: 4);
4202 case RISCV::TH_MULA:
4203 case RISCV::TH_MULAW:
4204 case RISCV::TH_MULAH:
4205 case RISCV::TH_MULS:
4206 case RISCV::TH_MULSW:
4207 case RISCV::TH_MULSH:
4208 // Operands 2 and 3 are commutable.
4209 return fixCommutedOpIndices(ResultIdx1&: SrcOpIdx1, ResultIdx2&: SrcOpIdx2, CommutableOpIdx1: 2, CommutableOpIdx2: 3);
4210 case RISCV::PseudoCCMOVGPRNoX0:
4211 case RISCV::PseudoCCMOVGPR:
4212 // Operands 1 and 2 are commutable.
4213 return fixCommutedOpIndices(ResultIdx1&: SrcOpIdx1, ResultIdx2&: SrcOpIdx2, CommutableOpIdx1: 1, CommutableOpIdx2: 2);
4214 case CASE_RVV_OPCODE(VADD_VV):
4215 case CASE_RVV_OPCODE(VAND_VV):
4216 case CASE_RVV_OPCODE(VOR_VV):
4217 case CASE_RVV_OPCODE(VXOR_VV):
4218 case CASE_RVV_OPCODE_MASK(VMSEQ_VV):
4219 case CASE_RVV_OPCODE_MASK(VMSNE_VV):
4220 case CASE_RVV_OPCODE(VMIN_VV):
4221 case CASE_RVV_OPCODE(VMINU_VV):
4222 case CASE_RVV_OPCODE(VMAX_VV):
4223 case CASE_RVV_OPCODE(VMAXU_VV):
4224 case CASE_RVV_OPCODE(VMUL_VV):
4225 case CASE_RVV_OPCODE(VMULH_VV):
4226 case CASE_RVV_OPCODE(VMULHU_VV):
4227 case CASE_RVV_OPCODE_WIDEN(VWADD_VV):
4228 case CASE_RVV_OPCODE_WIDEN(VWADDU_VV):
4229 case CASE_RVV_OPCODE_WIDEN(VWMUL_VV):
4230 case CASE_RVV_OPCODE_WIDEN(VWMULU_VV):
4231 case CASE_RVV_OPCODE_WIDEN(VWMACC_VV):
4232 case CASE_RVV_OPCODE_WIDEN(VWMACCU_VV):
4233 case CASE_RVV_OPCODE(VABD_VV):
4234 case CASE_RVV_OPCODE(VABDU_VV):
4235 case CASE_RVV_OPCODE_WIDEN(VWABDA_VV):
4236 case CASE_RVV_OPCODE_WIDEN(VWABDAU_VV):
4237 case CASE_RVV_OPCODE_UNMASK(VADC_VVM):
4238 case CASE_RVV_OPCODE(VSADD_VV):
4239 case CASE_RVV_OPCODE(VSADDU_VV):
4240 case CASE_RVV_OPCODE(VAADD_VV):
4241 case CASE_RVV_OPCODE(VAADDU_VV):
4242 case CASE_RVV_OPCODE(VSMUL_VV):
4243 case CASE_RVV_OPCODE_LMUL(VDOT4A_VV, MF2):
4244 case CASE_RVV_OPCODE_LMUL(VDOT4A_VV, M1):
4245 case CASE_RVV_OPCODE_LMUL(VDOT4A_VV, M2):
4246 case CASE_RVV_OPCODE_LMUL(VDOT4A_VV, M4):
4247 case CASE_RVV_OPCODE_LMUL(VDOT4A_VV, M8):
4248 case CASE_RVV_OPCODE_LMUL(VDOT4AU_VV, MF2):
4249 case CASE_RVV_OPCODE_LMUL(VDOT4AU_VV, M1):
4250 case CASE_RVV_OPCODE_LMUL(VDOT4AU_VV, M2):
4251 case CASE_RVV_OPCODE_LMUL(VDOT4AU_VV, M4):
4252 case CASE_RVV_OPCODE_LMUL(VDOT4AU_VV, M8):
4253 // Operands 2 and 3 are commutable.
4254 return fixCommutedOpIndices(ResultIdx1&: SrcOpIdx1, ResultIdx2&: SrcOpIdx2, CommutableOpIdx1: 2, CommutableOpIdx2: 3);
4255 case CASE_VFMA_SPLATS(FMADD):
4256 case CASE_VFMA_SPLATS(FMSUB):
4257 case CASE_VFMA_SPLATS(FMACC):
4258 case CASE_VFMA_SPLATS(FMSAC):
4259 case CASE_VFMA_SPLATS(FNMADD):
4260 case CASE_VFMA_SPLATS(FNMSUB):
4261 case CASE_VFMA_SPLATS(FNMACC):
4262 case CASE_VFMA_SPLATS(FNMSAC):
4263 case CASE_VFMA_OPCODE_VV(FMACC):
4264 case CASE_VFMA_OPCODE_VV(FMSAC):
4265 case CASE_VFMA_OPCODE_VV(FNMACC):
4266 case CASE_VFMA_OPCODE_VV(FNMSAC):
4267 case CASE_VMA_OPCODE_LMULS(MADD, VX):
4268 case CASE_VMA_OPCODE_LMULS(NMSUB, VX):
4269 case CASE_VMA_OPCODE_LMULS(MACC, VX):
4270 case CASE_VMA_OPCODE_LMULS(NMSAC, VX):
4271 case CASE_VMA_OPCODE_LMULS(MACC, VV):
4272 case CASE_VMA_OPCODE_LMULS(NMSAC, VV): {
4273 // If the tail policy is undisturbed we can't commute.
4274 assert(RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags));
4275 if ((MI.getOperand(i: RISCVII::getVecPolicyOpNum(Desc: MI.getDesc())).getImm() &
4276 1) == 0)
4277 return false;
4278
4279 // For these instructions we can only swap operand 1 and operand 3 by
4280 // changing the opcode.
4281 unsigned CommutableOpIdx1 = 1;
4282 unsigned CommutableOpIdx2 = 3;
4283 if (!fixCommutedOpIndices(ResultIdx1&: SrcOpIdx1, ResultIdx2&: SrcOpIdx2, CommutableOpIdx1,
4284 CommutableOpIdx2))
4285 return false;
4286 return true;
4287 }
4288 case CASE_VFMA_OPCODE_VV(FMADD):
4289 case CASE_VFMA_OPCODE_VV(FMSUB):
4290 case CASE_VFMA_OPCODE_VV(FNMADD):
4291 case CASE_VFMA_OPCODE_VV(FNMSUB):
4292 case CASE_VMA_OPCODE_LMULS(MADD, VV):
4293 case CASE_VMA_OPCODE_LMULS(NMSUB, VV): {
4294 // If the tail policy is undisturbed we can't commute.
4295 assert(RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags));
4296 if ((MI.getOperand(i: RISCVII::getVecPolicyOpNum(Desc: MI.getDesc())).getImm() &
4297 1) == 0)
4298 return false;
4299
4300 // For these instructions we have more freedom. We can commute with the
4301 // other multiplicand or with the addend/subtrahend/minuend.
4302
4303 // Any fixed operand must be from source 1, 2 or 3.
4304 if (SrcOpIdx1 != CommuteAnyOperandIndex && SrcOpIdx1 > 3)
4305 return false;
4306 if (SrcOpIdx2 != CommuteAnyOperandIndex && SrcOpIdx2 > 3)
4307 return false;
4308
4309 // It both ops are fixed one must be the tied source.
4310 if (SrcOpIdx1 != CommuteAnyOperandIndex &&
4311 SrcOpIdx2 != CommuteAnyOperandIndex && SrcOpIdx1 != 1 && SrcOpIdx2 != 1)
4312 return false;
4313
4314 // Look for two different register operands assumed to be commutable
4315 // regardless of the FMA opcode. The FMA opcode is adjusted later if
4316 // needed.
4317 if (SrcOpIdx1 == CommuteAnyOperandIndex ||
4318 SrcOpIdx2 == CommuteAnyOperandIndex) {
4319 // At least one of operands to be commuted is not specified and
4320 // this method is free to choose appropriate commutable operands.
4321 unsigned CommutableOpIdx1 = SrcOpIdx1;
4322 if (SrcOpIdx1 == SrcOpIdx2) {
4323 // Both of operands are not fixed. Set one of commutable
4324 // operands to the tied source.
4325 CommutableOpIdx1 = 1;
4326 } else if (SrcOpIdx1 == CommuteAnyOperandIndex) {
4327 // Only one of the operands is not fixed.
4328 CommutableOpIdx1 = SrcOpIdx2;
4329 }
4330
4331 // CommutableOpIdx1 is well defined now. Let's choose another commutable
4332 // operand and assign its index to CommutableOpIdx2.
4333 unsigned CommutableOpIdx2;
4334 if (CommutableOpIdx1 != 1) {
4335 // If we haven't already used the tied source, we must use it now.
4336 CommutableOpIdx2 = 1;
4337 } else {
4338 Register Op1Reg = MI.getOperand(i: CommutableOpIdx1).getReg();
4339
4340 // The commuted operands should have different registers.
4341 // Otherwise, the commute transformation does not change anything and
4342 // is useless. We use this as a hint to make our decision.
4343 if (Op1Reg != MI.getOperand(i: 2).getReg())
4344 CommutableOpIdx2 = 2;
4345 else
4346 CommutableOpIdx2 = 3;
4347 }
4348
4349 // Assign the found pair of commutable indices to SrcOpIdx1 and
4350 // SrcOpIdx2 to return those values.
4351 if (!fixCommutedOpIndices(ResultIdx1&: SrcOpIdx1, ResultIdx2&: SrcOpIdx2, CommutableOpIdx1,
4352 CommutableOpIdx2))
4353 return false;
4354 }
4355
4356 return true;
4357 }
4358 }
4359
4360 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
4361}
4362
4363// clang-format off
4364#define CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, LMUL) \
4365 case RISCV::PseudoV##OLDOP##_##TYPE##_##LMUL: \
4366 Opc = RISCV::PseudoV##NEWOP##_##TYPE##_##LMUL; \
4367 break;
4368
4369#define CASE_VMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, TYPE) \
4370 CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF8) \
4371 CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF4) \
4372 CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF2) \
4373 CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M1) \
4374 CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M2) \
4375 CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M4) \
4376 CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M8)
4377
4378// VFMA depends on SEW.
4379#define CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, LMUL, SEW) \
4380 case RISCV::PseudoV##OLDOP##_##TYPE##_##LMUL##_##SEW: \
4381 Opc = RISCV::PseudoV##NEWOP##_##TYPE##_##LMUL##_##SEW; \
4382 break;
4383
4384#define CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, TYPE, SEW) \
4385 CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M1, SEW) \
4386 CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M2, SEW) \
4387 CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M4, SEW) \
4388 CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M8, SEW)
4389
4390#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, TYPE, SEW) \
4391 CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF2, SEW) \
4392 CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, TYPE, SEW)
4393
4394#define CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE, SEW) \
4395 CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF4, SEW) \
4396 CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, TYPE, SEW)
4397
4398#define CASE_VFMA_CHANGE_OPCODE_VV(OLDOP, NEWOP) \
4399 CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, VV, E16) \
4400 CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP##_ALT, NEWOP##_ALT, VV, E16) \
4401 CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, VV, E32) \
4402 CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, VV, E64)
4403
4404#define CASE_VFMA_CHANGE_OPCODE_SPLATS(OLDOP, NEWOP) \
4405 CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, VFPR16, E16) \
4406 CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP##_ALT, NEWOP##_ALT, VFPR16, E16) \
4407 CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, VFPR32, E32) \
4408 CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, VFPR64, E64)
4409// clang-format on
4410
4411MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
4412 bool NewMI,
4413 unsigned OpIdx1,
4414 unsigned OpIdx2) const {
4415 auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
4416 if (NewMI)
4417 return *MI.getParent()->getParent()->CloneMachineInstr(Orig: &MI);
4418 return MI;
4419 };
4420
4421 switch (MI.getOpcode()) {
4422 case RISCV::TH_MVEQZ:
4423 case RISCV::TH_MVNEZ: {
4424 auto &WorkingMI = cloneIfNew(MI);
4425 WorkingMI.setDesc(get(Opcode: MI.getOpcode() == RISCV::TH_MVEQZ ? RISCV::TH_MVNEZ
4426 : RISCV::TH_MVEQZ));
4427 return TargetInstrInfo::commuteInstructionImpl(MI&: WorkingMI, NewMI: false, OpIdx1,
4428 OpIdx2);
4429 }
4430 case RISCV::QC_SELECTIEQ:
4431 case RISCV::QC_SELECTINE:
4432 case RISCV::QC_SELECTIIEQ:
4433 case RISCV::QC_SELECTIINE:
4434 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
4435 case RISCV::QC_MVEQ:
4436 case RISCV::QC_MVNE:
4437 case RISCV::QC_MVLT:
4438 case RISCV::QC_MVGE:
4439 case RISCV::QC_MVLTU:
4440 case RISCV::QC_MVGEU:
4441 case RISCV::QC_MVEQI:
4442 case RISCV::QC_MVNEI:
4443 case RISCV::QC_MVLTI:
4444 case RISCV::QC_MVGEI:
4445 case RISCV::QC_MVLTUI:
4446 case RISCV::QC_MVGEUI: {
4447 auto &WorkingMI = cloneIfNew(MI);
4448 WorkingMI.setDesc(get(Opcode: getInverseXqcicmOpcode(Opcode: MI.getOpcode())));
4449 return TargetInstrInfo::commuteInstructionImpl(MI&: WorkingMI, NewMI: false, OpIdx1,
4450 OpIdx2);
4451 }
4452 case RISCV::PseudoCCMOVGPRNoX0:
4453 case RISCV::PseudoCCMOVGPR: {
4454 // CCMOV can be commuted by inverting the condition.
4455 unsigned BCC = MI.getOperand(i: MI.getNumExplicitOperands() - 3).getImm();
4456 BCC = RISCVCC::getInverseBranchOpcode(BCC);
4457 auto &WorkingMI = cloneIfNew(MI);
4458 WorkingMI.getOperand(i: MI.getNumExplicitOperands() - 3).setImm(BCC);
4459 return TargetInstrInfo::commuteInstructionImpl(MI&: WorkingMI, /*NewMI*/ false,
4460 OpIdx1, OpIdx2);
4461 }
4462 case CASE_VFMA_SPLATS(FMACC):
4463 case CASE_VFMA_SPLATS(FMADD):
4464 case CASE_VFMA_SPLATS(FMSAC):
4465 case CASE_VFMA_SPLATS(FMSUB):
4466 case CASE_VFMA_SPLATS(FNMACC):
4467 case CASE_VFMA_SPLATS(FNMADD):
4468 case CASE_VFMA_SPLATS(FNMSAC):
4469 case CASE_VFMA_SPLATS(FNMSUB):
4470 case CASE_VFMA_OPCODE_VV(FMACC):
4471 case CASE_VFMA_OPCODE_VV(FMSAC):
4472 case CASE_VFMA_OPCODE_VV(FNMACC):
4473 case CASE_VFMA_OPCODE_VV(FNMSAC):
4474 case CASE_VMA_OPCODE_LMULS(MADD, VX):
4475 case CASE_VMA_OPCODE_LMULS(NMSUB, VX):
4476 case CASE_VMA_OPCODE_LMULS(MACC, VX):
4477 case CASE_VMA_OPCODE_LMULS(NMSAC, VX):
4478 case CASE_VMA_OPCODE_LMULS(MACC, VV):
4479 case CASE_VMA_OPCODE_LMULS(NMSAC, VV): {
4480 // It only make sense to toggle these between clobbering the
4481 // addend/subtrahend/minuend one of the multiplicands.
4482 assert((OpIdx1 == 1 || OpIdx2 == 1) && "Unexpected opcode index");
4483 assert((OpIdx1 == 3 || OpIdx2 == 3) && "Unexpected opcode index");
4484 unsigned Opc;
4485 switch (MI.getOpcode()) {
4486 default:
4487 llvm_unreachable("Unexpected opcode");
4488 CASE_VFMA_CHANGE_OPCODE_SPLATS(FMACC, FMADD)
4489 CASE_VFMA_CHANGE_OPCODE_SPLATS(FMADD, FMACC)
4490 CASE_VFMA_CHANGE_OPCODE_SPLATS(FMSAC, FMSUB)
4491 CASE_VFMA_CHANGE_OPCODE_SPLATS(FMSUB, FMSAC)
4492 CASE_VFMA_CHANGE_OPCODE_SPLATS(FNMACC, FNMADD)
4493 CASE_VFMA_CHANGE_OPCODE_SPLATS(FNMADD, FNMACC)
4494 CASE_VFMA_CHANGE_OPCODE_SPLATS(FNMSAC, FNMSUB)
4495 CASE_VFMA_CHANGE_OPCODE_SPLATS(FNMSUB, FNMSAC)
4496 CASE_VFMA_CHANGE_OPCODE_VV(FMACC, FMADD)
4497 CASE_VFMA_CHANGE_OPCODE_VV(FMSAC, FMSUB)
4498 CASE_VFMA_CHANGE_OPCODE_VV(FNMACC, FNMADD)
4499 CASE_VFMA_CHANGE_OPCODE_VV(FNMSAC, FNMSUB)
4500 CASE_VMA_CHANGE_OPCODE_LMULS(MACC, MADD, VX)
4501 CASE_VMA_CHANGE_OPCODE_LMULS(MADD, MACC, VX)
4502 CASE_VMA_CHANGE_OPCODE_LMULS(NMSAC, NMSUB, VX)
4503 CASE_VMA_CHANGE_OPCODE_LMULS(NMSUB, NMSAC, VX)
4504 CASE_VMA_CHANGE_OPCODE_LMULS(MACC, MADD, VV)
4505 CASE_VMA_CHANGE_OPCODE_LMULS(NMSAC, NMSUB, VV)
4506 }
4507
4508 auto &WorkingMI = cloneIfNew(MI);
4509 WorkingMI.setDesc(get(Opcode: Opc));
4510 return TargetInstrInfo::commuteInstructionImpl(MI&: WorkingMI, /*NewMI=*/false,
4511 OpIdx1, OpIdx2);
4512 }
4513 case CASE_VFMA_OPCODE_VV(FMADD):
4514 case CASE_VFMA_OPCODE_VV(FMSUB):
4515 case CASE_VFMA_OPCODE_VV(FNMADD):
4516 case CASE_VFMA_OPCODE_VV(FNMSUB):
4517 case CASE_VMA_OPCODE_LMULS(MADD, VV):
4518 case CASE_VMA_OPCODE_LMULS(NMSUB, VV): {
4519 assert((OpIdx1 == 1 || OpIdx2 == 1) && "Unexpected opcode index");
4520 // If one of the operands, is the addend we need to change opcode.
4521 // Otherwise we're just swapping 2 of the multiplicands.
4522 if (OpIdx1 == 3 || OpIdx2 == 3) {
4523 unsigned Opc;
4524 switch (MI.getOpcode()) {
4525 default:
4526 llvm_unreachable("Unexpected opcode");
4527 CASE_VFMA_CHANGE_OPCODE_VV(FMADD, FMACC)
4528 CASE_VFMA_CHANGE_OPCODE_VV(FMSUB, FMSAC)
4529 CASE_VFMA_CHANGE_OPCODE_VV(FNMADD, FNMACC)
4530 CASE_VFMA_CHANGE_OPCODE_VV(FNMSUB, FNMSAC)
4531 CASE_VMA_CHANGE_OPCODE_LMULS(MADD, MACC, VV)
4532 CASE_VMA_CHANGE_OPCODE_LMULS(NMSUB, NMSAC, VV)
4533 }
4534
4535 auto &WorkingMI = cloneIfNew(MI);
4536 WorkingMI.setDesc(get(Opcode: Opc));
4537 return TargetInstrInfo::commuteInstructionImpl(MI&: WorkingMI, /*NewMI=*/false,
4538 OpIdx1, OpIdx2);
4539 }
4540 // Let the default code handle it.
4541 break;
4542 }
4543 }
4544
4545 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
4546}
4547
4548#undef CASE_VMA_CHANGE_OPCODE_COMMON
4549#undef CASE_VMA_CHANGE_OPCODE_LMULS
4550#undef CASE_VFMA_CHANGE_OPCODE_COMMON
4551#undef CASE_VFMA_CHANGE_OPCODE_LMULS_M1
4552#undef CASE_VFMA_CHANGE_OPCODE_LMULS_MF2
4553#undef CASE_VFMA_CHANGE_OPCODE_LMULS_MF4
4554#undef CASE_VFMA_CHANGE_OPCODE_VV
4555#undef CASE_VFMA_CHANGE_OPCODE_SPLATS
4556
4557#undef CASE_RVV_OPCODE_UNMASK_LMUL
4558#undef CASE_RVV_OPCODE_MASK_LMUL
4559#undef CASE_RVV_OPCODE_LMUL
4560#undef CASE_RVV_OPCODE_UNMASK_WIDEN
4561#undef CASE_RVV_OPCODE_UNMASK
4562#undef CASE_RVV_OPCODE_MASK_WIDEN
4563#undef CASE_RVV_OPCODE_MASK
4564#undef CASE_RVV_OPCODE_WIDEN
4565#undef CASE_RVV_OPCODE
4566
4567#undef CASE_VMA_OPCODE_COMMON
4568#undef CASE_VMA_OPCODE_LMULS
4569#undef CASE_VFMA_OPCODE_COMMON
4570#undef CASE_VFMA_OPCODE_LMULS_M1
4571#undef CASE_VFMA_OPCODE_LMULS_MF2
4572#undef CASE_VFMA_OPCODE_LMULS_MF4
4573#undef CASE_VFMA_OPCODE_VV
4574#undef CASE_VFMA_SPLATS
4575
4576bool RISCVInstrInfo::simplifyInstruction(MachineInstr &MI) const {
4577 switch (MI.getOpcode()) {
4578 default:
4579 break;
4580 case RISCV::ADD:
4581 case RISCV::OR:
4582 case RISCV::XOR:
4583 // Normalize (so we hit the next if clause).
4584 // add/[x]or rd, zero, rs => add/[x]or rd, rs, zero
4585 if (MI.getOperand(i: 1).getReg() == RISCV::X0)
4586 commuteInstruction(MI);
4587 // add/[x]or rd, rs, zero => addi rd, rs, 0
4588 if (MI.getOperand(i: 2).getReg() == RISCV::X0) {
4589 MI.getOperand(i: 2).ChangeToImmediate(ImmVal: 0);
4590 MI.setDesc(get(Opcode: RISCV::ADDI));
4591 return true;
4592 }
4593 // xor rd, rs, rs => addi rd, zero, 0
4594 if (MI.getOpcode() == RISCV::XOR &&
4595 MI.getOperand(i: 1).getReg() == MI.getOperand(i: 2).getReg()) {
4596 MI.getOperand(i: 1).setReg(RISCV::X0);
4597 MI.getOperand(i: 2).ChangeToImmediate(ImmVal: 0);
4598 MI.setDesc(get(Opcode: RISCV::ADDI));
4599 return true;
4600 }
4601 break;
4602 case RISCV::ORI:
4603 case RISCV::XORI:
4604 // [x]ori rd, zero, N => addi rd, zero, N
4605 if (MI.getOperand(i: 1).getReg() == RISCV::X0) {
4606 MI.setDesc(get(Opcode: RISCV::ADDI));
4607 return true;
4608 }
4609 break;
4610 case RISCV::SUB:
4611 // sub rd, rs, zero => addi rd, rs, 0
4612 if (MI.getOperand(i: 2).getReg() == RISCV::X0) {
4613 MI.getOperand(i: 2).ChangeToImmediate(ImmVal: 0);
4614 MI.setDesc(get(Opcode: RISCV::ADDI));
4615 return true;
4616 }
4617 break;
4618 case RISCV::SUBW:
4619 // subw rd, rs, zero => addiw rd, rs, 0
4620 if (MI.getOperand(i: 2).getReg() == RISCV::X0) {
4621 MI.getOperand(i: 2).ChangeToImmediate(ImmVal: 0);
4622 MI.setDesc(get(Opcode: RISCV::ADDIW));
4623 return true;
4624 }
4625 break;
4626 case RISCV::ADDW:
4627 // Normalize (so we hit the next if clause).
4628 // addw rd, zero, rs => addw rd, rs, zero
4629 if (MI.getOperand(i: 1).getReg() == RISCV::X0)
4630 commuteInstruction(MI);
4631 // addw rd, rs, zero => addiw rd, rs, 0
4632 if (MI.getOperand(i: 2).getReg() == RISCV::X0) {
4633 MI.getOperand(i: 2).ChangeToImmediate(ImmVal: 0);
4634 MI.setDesc(get(Opcode: RISCV::ADDIW));
4635 return true;
4636 }
4637 break;
4638 case RISCV::SH1ADD:
4639 case RISCV::SH1ADD_UW:
4640 case RISCV::SH2ADD:
4641 case RISCV::SH2ADD_UW:
4642 case RISCV::SH3ADD:
4643 case RISCV::SH3ADD_UW:
4644 // shNadd[.uw] rd, zero, rs => addi rd, rs, 0
4645 if (MI.getOperand(i: 1).getReg() == RISCV::X0) {
4646 MI.removeOperand(OpNo: 1);
4647 MI.addOperand(Op: MachineOperand::CreateImm(Val: 0));
4648 MI.setDesc(get(Opcode: RISCV::ADDI));
4649 return true;
4650 }
4651 // shNadd[.uw] rd, rs, zero => slli[.uw] rd, rs, N
4652 if (MI.getOperand(i: 2).getReg() == RISCV::X0) {
4653 MI.removeOperand(OpNo: 2);
4654 unsigned Opc = MI.getOpcode();
4655 if (Opc == RISCV::SH1ADD_UW || Opc == RISCV::SH2ADD_UW ||
4656 Opc == RISCV::SH3ADD_UW) {
4657 MI.addOperand(Op: MachineOperand::CreateImm(Val: getSHXADDUWShiftAmount(Opc)));
4658 MI.setDesc(get(Opcode: RISCV::SLLI_UW));
4659 return true;
4660 }
4661 MI.addOperand(Op: MachineOperand::CreateImm(Val: getSHXADDShiftAmount(Opc)));
4662 MI.setDesc(get(Opcode: RISCV::SLLI));
4663 return true;
4664 }
4665 break;
4666 case RISCV::AND:
4667 case RISCV::MUL:
4668 case RISCV::MULH:
4669 case RISCV::MULHSU:
4670 case RISCV::MULHU:
4671 case RISCV::MULW:
4672 // and rd, zero, rs => addi rd, zero, 0
4673 // mul* rd, zero, rs => addi rd, zero, 0
4674 // and rd, rs, zero => addi rd, zero, 0
4675 // mul* rd, rs, zero => addi rd, zero, 0
4676 if (MI.getOperand(i: 1).getReg() == RISCV::X0 ||
4677 MI.getOperand(i: 2).getReg() == RISCV::X0) {
4678 MI.getOperand(i: 1).setReg(RISCV::X0);
4679 MI.getOperand(i: 2).ChangeToImmediate(ImmVal: 0);
4680 MI.setDesc(get(Opcode: RISCV::ADDI));
4681 return true;
4682 }
4683 break;
4684 case RISCV::ANDI:
4685 // andi rd, zero, C => addi rd, zero, 0
4686 if (MI.getOperand(i: 1).getReg() == RISCV::X0) {
4687 MI.getOperand(i: 2).setImm(0);
4688 MI.setDesc(get(Opcode: RISCV::ADDI));
4689 return true;
4690 }
4691 break;
4692 case RISCV::SLL:
4693 case RISCV::SRL:
4694 case RISCV::SRA:
4695 // shift rd, zero, rs => addi rd, zero, 0
4696 if (MI.getOperand(i: 1).getReg() == RISCV::X0) {
4697 MI.getOperand(i: 2).ChangeToImmediate(ImmVal: 0);
4698 MI.setDesc(get(Opcode: RISCV::ADDI));
4699 return true;
4700 }
4701 // shift rd, rs, zero => addi rd, rs, 0
4702 if (MI.getOperand(i: 2).getReg() == RISCV::X0) {
4703 MI.getOperand(i: 2).ChangeToImmediate(ImmVal: 0);
4704 MI.setDesc(get(Opcode: RISCV::ADDI));
4705 return true;
4706 }
4707 break;
4708 case RISCV::SLLW:
4709 case RISCV::SRLW:
4710 case RISCV::SRAW:
4711 // shiftw rd, zero, rs => addi rd, zero, 0
4712 if (MI.getOperand(i: 1).getReg() == RISCV::X0) {
4713 MI.getOperand(i: 2).ChangeToImmediate(ImmVal: 0);
4714 MI.setDesc(get(Opcode: RISCV::ADDI));
4715 return true;
4716 }
4717 break;
4718 case RISCV::SLLI:
4719 case RISCV::SRLI:
4720 case RISCV::SRAI:
4721 case RISCV::SLLIW:
4722 case RISCV::SRLIW:
4723 case RISCV::SRAIW:
4724 case RISCV::SLLI_UW:
4725 // shiftimm rd, zero, N => addi rd, zero, 0
4726 if (MI.getOperand(i: 1).getReg() == RISCV::X0) {
4727 MI.getOperand(i: 2).setImm(0);
4728 MI.setDesc(get(Opcode: RISCV::ADDI));
4729 return true;
4730 }
4731 break;
4732 case RISCV::SLTU:
4733 case RISCV::ADD_UW:
4734 // sltu rd, zero, zero => addi rd, zero, 0
4735 // add.uw rd, zero, zero => addi rd, zero, 0
4736 if (MI.getOperand(i: 1).getReg() == RISCV::X0 &&
4737 MI.getOperand(i: 2).getReg() == RISCV::X0) {
4738 MI.getOperand(i: 2).ChangeToImmediate(ImmVal: 0);
4739 MI.setDesc(get(Opcode: RISCV::ADDI));
4740 return true;
4741 }
4742 // add.uw rd, zero, rs => addi rd, rs, 0
4743 if (MI.getOpcode() == RISCV::ADD_UW &&
4744 MI.getOperand(i: 1).getReg() == RISCV::X0) {
4745 MI.removeOperand(OpNo: 1);
4746 MI.addOperand(Op: MachineOperand::CreateImm(Val: 0));
4747 MI.setDesc(get(Opcode: RISCV::ADDI));
4748 }
4749 break;
4750 case RISCV::SLTIU:
4751 // sltiu rd, zero, NZC => addi rd, zero, 1
4752 // sltiu rd, zero, 0 => addi rd, zero, 0
4753 if (MI.getOperand(i: 1).getReg() == RISCV::X0) {
4754 MI.getOperand(i: 2).setImm(MI.getOperand(i: 2).getImm() != 0);
4755 MI.setDesc(get(Opcode: RISCV::ADDI));
4756 return true;
4757 }
4758 break;
4759 case RISCV::SEXT_H:
4760 case RISCV::SEXT_B:
4761 case RISCV::ZEXT_H_RV32:
4762 case RISCV::ZEXT_H_RV64:
4763 // sext.[hb] rd, zero => addi rd, zero, 0
4764 // zext.h rd, zero => addi rd, zero, 0
4765 if (MI.getOperand(i: 1).getReg() == RISCV::X0) {
4766 MI.addOperand(Op: MachineOperand::CreateImm(Val: 0));
4767 MI.setDesc(get(Opcode: RISCV::ADDI));
4768 return true;
4769 }
4770 break;
4771 case RISCV::MIN:
4772 case RISCV::MINU:
4773 case RISCV::MAX:
4774 case RISCV::MAXU:
4775 // min|max rd, rs, rs => addi rd, rs, 0
4776 if (MI.getOperand(i: 1).getReg() == MI.getOperand(i: 2).getReg()) {
4777 MI.getOperand(i: 2).ChangeToImmediate(ImmVal: 0);
4778 MI.setDesc(get(Opcode: RISCV::ADDI));
4779 return true;
4780 }
4781 break;
4782 case RISCV::BEQ:
4783 case RISCV::BNE:
4784 // b{eq,ne} zero, rs, imm => b{eq,ne} rs, zero, imm
4785 if (MI.getOperand(i: 0).getReg() == RISCV::X0) {
4786 MachineOperand MO0 = MI.getOperand(i: 0);
4787 MI.removeOperand(OpNo: 0);
4788 MI.insert(InsertBefore: MI.operands_begin() + 1, Ops: {MO0});
4789 }
4790 break;
4791 case RISCV::BLTU:
4792 // bltu zero, rs, imm => bne rs, zero, imm
4793 if (MI.getOperand(i: 0).getReg() == RISCV::X0) {
4794 MachineOperand MO0 = MI.getOperand(i: 0);
4795 MI.removeOperand(OpNo: 0);
4796 MI.insert(InsertBefore: MI.operands_begin() + 1, Ops: {MO0});
4797 MI.setDesc(get(Opcode: RISCV::BNE));
4798 }
4799 break;
4800 case RISCV::BGEU:
4801 // bgeu zero, rs, imm => beq rs, zero, imm
4802 if (MI.getOperand(i: 0).getReg() == RISCV::X0) {
4803 MachineOperand MO0 = MI.getOperand(i: 0);
4804 MI.removeOperand(OpNo: 0);
4805 MI.insert(InsertBefore: MI.operands_begin() + 1, Ops: {MO0});
4806 MI.setDesc(get(Opcode: RISCV::BEQ));
4807 }
4808 break;
4809 }
4810 return false;
4811}
4812
4813// clang-format off
4814#define CASE_WIDEOP_OPCODE_COMMON(OP, LMUL) \
4815 RISCV::PseudoV##OP##_##LMUL##_TIED
4816
4817#define CASE_WIDEOP_OPCODE_LMULS(OP) \
4818 CASE_WIDEOP_OPCODE_COMMON(OP, MF8): \
4819 case CASE_WIDEOP_OPCODE_COMMON(OP, MF4): \
4820 case CASE_WIDEOP_OPCODE_COMMON(OP, MF2): \
4821 case CASE_WIDEOP_OPCODE_COMMON(OP, M1): \
4822 case CASE_WIDEOP_OPCODE_COMMON(OP, M2): \
4823 case CASE_WIDEOP_OPCODE_COMMON(OP, M4)
4824
4825#define CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, LMUL) \
4826 case RISCV::PseudoV##OP##_##LMUL##_TIED: \
4827 NewOpc = RISCV::PseudoV##OP##_##LMUL; \
4828 break;
4829
4830#define CASE_WIDEOP_CHANGE_OPCODE_LMULS(OP) \
4831 CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF8) \
4832 CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF4) \
4833 CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF2) \
4834 CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M1) \
4835 CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M2) \
4836 CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, M4)
4837
4838// FP Widening Ops may by SEW aware. Create SEW aware cases for these cases.
4839#define CASE_FP_WIDEOP_OPCODE_COMMON(OP, LMUL, SEW) \
4840 RISCV::PseudoV##OP##_##LMUL##_##SEW##_TIED
4841
4842#define CASE_FP_WIDEOP_OPCODE_LMULS(OP) \
4843 CASE_FP_WIDEOP_OPCODE_COMMON(OP, MF4, E16): \
4844 case CASE_FP_WIDEOP_OPCODE_COMMON(OP, MF2, E16): \
4845 case CASE_FP_WIDEOP_OPCODE_COMMON(OP, MF2, E32): \
4846 case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M1, E16): \
4847 case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M1, E32): \
4848 case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M2, E16): \
4849 case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M2, E32): \
4850 case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M4, E16): \
4851 case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M4, E32) \
4852
4853#define CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, LMUL, SEW) \
4854 case RISCV::PseudoV##OP##_##LMUL##_##SEW##_TIED: \
4855 NewOpc = RISCV::PseudoV##OP##_##LMUL##_##SEW; \
4856 break;
4857
4858#define CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS(OP) \
4859 CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF4, E16) \
4860 CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF2, E16) \
4861 CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF2, E32) \
4862 CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M1, E16) \
4863 CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M1, E32) \
4864 CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M2, E16) \
4865 CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M2, E32) \
4866 CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M4, E16) \
4867 CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M4, E32) \
4868
4869#define CASE_FP_WIDEOP_OPCODE_LMULS_ALT(OP) \
4870 CASE_FP_WIDEOP_OPCODE_COMMON(OP, MF4, E16): \
4871 case CASE_FP_WIDEOP_OPCODE_COMMON(OP, MF2, E16): \
4872 case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M1, E16): \
4873 case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M2, E16): \
4874 case CASE_FP_WIDEOP_OPCODE_COMMON(OP, M4, E16)
4875
4876#define CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS_ALT(OP) \
4877 CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF4, E16) \
4878 CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF2, E16) \
4879 CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M1, E16) \
4880 CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M2, E16) \
4881 CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON(OP, M4, E16)
4882// clang-format on
4883
4884MachineInstr *RISCVInstrInfo::convertToThreeAddress(MachineInstr &MI,
4885 LiveVariables *LV,
4886 LiveIntervals *LIS) const {
4887 MachineInstrBuilder MIB;
4888 switch (MI.getOpcode()) {
4889 default:
4890 return nullptr;
4891 case CASE_FP_WIDEOP_OPCODE_LMULS_ALT(FWADD_ALT_WV):
4892 case CASE_FP_WIDEOP_OPCODE_LMULS_ALT(FWSUB_ALT_WV):
4893 case CASE_FP_WIDEOP_OPCODE_LMULS(FWADD_WV):
4894 case CASE_FP_WIDEOP_OPCODE_LMULS(FWSUB_WV): {
4895 assert(RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags) &&
4896 MI.getNumExplicitOperands() == 7 &&
4897 "Expect 7 explicit operands rd, rs2, rs1, rm, vl, sew, policy");
4898 // If the tail policy is undisturbed we can't convert.
4899 if ((MI.getOperand(i: RISCVII::getVecPolicyOpNum(Desc: MI.getDesc())).getImm() &
4900 1) == 0)
4901 return nullptr;
4902 // clang-format off
4903 unsigned NewOpc;
4904 switch (MI.getOpcode()) {
4905 default:
4906 llvm_unreachable("Unexpected opcode");
4907 CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS(FWADD_WV)
4908 CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS(FWSUB_WV)
4909 CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS_ALT(FWADD_ALT_WV)
4910 CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS_ALT(FWSUB_ALT_WV)
4911 }
4912 // clang-format on
4913
4914 MachineBasicBlock &MBB = *MI.getParent();
4915 MIB = BuildMI(BB&: MBB, I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: NewOpc))
4916 .add(MO: MI.getOperand(i: 0))
4917 .addReg(RegNo: MI.getOperand(i: 0).getReg(), Flags: RegState::Undef)
4918 .add(MO: MI.getOperand(i: 1))
4919 .add(MO: MI.getOperand(i: 2))
4920 .add(MO: MI.getOperand(i: 3))
4921 .add(MO: MI.getOperand(i: 4))
4922 .add(MO: MI.getOperand(i: 5))
4923 .add(MO: MI.getOperand(i: 6));
4924 break;
4925 }
4926 case CASE_WIDEOP_OPCODE_LMULS(WADD_WV):
4927 case CASE_WIDEOP_OPCODE_LMULS(WADDU_WV):
4928 case CASE_WIDEOP_OPCODE_LMULS(WSUB_WV):
4929 case CASE_WIDEOP_OPCODE_LMULS(WSUBU_WV): {
4930 // If the tail policy is undisturbed we can't convert.
4931 assert(RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags) &&
4932 MI.getNumExplicitOperands() == 6);
4933 if ((MI.getOperand(i: RISCVII::getVecPolicyOpNum(Desc: MI.getDesc())).getImm() &
4934 1) == 0)
4935 return nullptr;
4936
4937 // clang-format off
4938 unsigned NewOpc;
4939 switch (MI.getOpcode()) {
4940 default:
4941 llvm_unreachable("Unexpected opcode");
4942 CASE_WIDEOP_CHANGE_OPCODE_LMULS(WADD_WV)
4943 CASE_WIDEOP_CHANGE_OPCODE_LMULS(WADDU_WV)
4944 CASE_WIDEOP_CHANGE_OPCODE_LMULS(WSUB_WV)
4945 CASE_WIDEOP_CHANGE_OPCODE_LMULS(WSUBU_WV)
4946 }
4947 // clang-format on
4948
4949 MachineBasicBlock &MBB = *MI.getParent();
4950 MIB = BuildMI(BB&: MBB, I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: NewOpc))
4951 .add(MO: MI.getOperand(i: 0))
4952 .addReg(RegNo: MI.getOperand(i: 0).getReg(), Flags: RegState::Undef)
4953 .add(MO: MI.getOperand(i: 1))
4954 .add(MO: MI.getOperand(i: 2))
4955 .add(MO: MI.getOperand(i: 3))
4956 .add(MO: MI.getOperand(i: 4))
4957 .add(MO: MI.getOperand(i: 5));
4958 break;
4959 }
4960 }
4961 MIB.copyImplicitOps(OtherMI: MI);
4962
4963 if (LV) {
4964 unsigned NumOps = MI.getNumOperands();
4965 for (unsigned I = 1; I < NumOps; ++I) {
4966 MachineOperand &Op = MI.getOperand(i: I);
4967 if (Op.isReg() && Op.isKill())
4968 LV->replaceKillInstruction(Reg: Op.getReg(), OldMI&: MI, NewMI&: *MIB);
4969 }
4970 }
4971
4972 if (LIS) {
4973 SlotIndex Idx = LIS->ReplaceMachineInstrInMaps(MI, NewMI&: *MIB);
4974
4975 if (MI.getOperand(i: 0).isEarlyClobber()) {
4976 // Use operand 1 was tied to early-clobber def operand 0, so its live
4977 // interval could have ended at an early-clobber slot. Now they are not
4978 // tied we need to update it to the normal register slot.
4979 LiveInterval &LI = LIS->getInterval(Reg: MI.getOperand(i: 1).getReg());
4980 LiveRange::Segment *S = LI.getSegmentContaining(Idx);
4981 if (S->end == Idx.getRegSlot(EC: true))
4982 S->end = Idx.getRegSlot();
4983 }
4984 }
4985
4986 return MIB;
4987}
4988
4989#undef CASE_WIDEOP_OPCODE_COMMON
4990#undef CASE_WIDEOP_OPCODE_LMULS
4991#undef CASE_WIDEOP_CHANGE_OPCODE_COMMON
4992#undef CASE_WIDEOP_CHANGE_OPCODE_LMULS
4993#undef CASE_FP_WIDEOP_OPCODE_COMMON
4994#undef CASE_FP_WIDEOP_OPCODE_LMULS
4995#undef CASE_FP_WIDEOP_CHANGE_OPCODE_COMMON
4996#undef CASE_FP_WIDEOP_CHANGE_OPCODE_LMULS
4997
4998void RISCVInstrInfo::mulImm(MachineFunction &MF, MachineBasicBlock &MBB,
4999 MachineBasicBlock::iterator II, const DebugLoc &DL,
5000 Register DestReg, uint32_t Amount,
5001 MachineInstr::MIFlag Flag) const {
5002 MachineRegisterInfo &MRI = MF.getRegInfo();
5003 if (llvm::has_single_bit(Value: Amount)) {
5004 uint32_t ShiftAmount = Log2_32(Value: Amount);
5005 if (ShiftAmount == 0)
5006 return;
5007 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: get(Opcode: RISCV::SLLI), DestReg)
5008 .addReg(RegNo: DestReg, Flags: RegState::Kill)
5009 .addImm(Val: ShiftAmount)
5010 .setMIFlag(Flag);
5011 } else if (int ShXAmount, ShiftAmount;
5012 STI.hasShlAdd(ShAmt: 3) &&
5013 (ShXAmount = isShifted359(Value: Amount, Shift&: ShiftAmount)) != 0) {
5014 // We can use Zba SHXADD+SLLI instructions for multiply in some cases.
5015 unsigned Opc;
5016 switch (ShXAmount) {
5017 case 1:
5018 Opc = RISCV::SH1ADD;
5019 break;
5020 case 2:
5021 Opc = RISCV::SH2ADD;
5022 break;
5023 case 3:
5024 Opc = RISCV::SH3ADD;
5025 break;
5026 default:
5027 llvm_unreachable("unexpected result of isShifted359");
5028 }
5029 if (ShiftAmount)
5030 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: get(Opcode: RISCV::SLLI), DestReg)
5031 .addReg(RegNo: DestReg, Flags: RegState::Kill)
5032 .addImm(Val: ShiftAmount)
5033 .setMIFlag(Flag);
5034 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: get(Opcode: Opc), DestReg)
5035 .addReg(RegNo: DestReg, Flags: RegState::Kill)
5036 .addReg(RegNo: DestReg)
5037 .setMIFlag(Flag);
5038 } else if (llvm::has_single_bit(Value: Amount - 1)) {
5039 Register ScaledRegister = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
5040 uint32_t ShiftAmount = Log2_32(Value: Amount - 1);
5041 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: get(Opcode: RISCV::SLLI), DestReg: ScaledRegister)
5042 .addReg(RegNo: DestReg)
5043 .addImm(Val: ShiftAmount)
5044 .setMIFlag(Flag);
5045 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: get(Opcode: RISCV::ADD), DestReg)
5046 .addReg(RegNo: ScaledRegister, Flags: RegState::Kill)
5047 .addReg(RegNo: DestReg, Flags: RegState::Kill)
5048 .setMIFlag(Flag);
5049 } else if (llvm::has_single_bit(Value: Amount + 1)) {
5050 Register ScaledRegister = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
5051 uint32_t ShiftAmount = Log2_32(Value: Amount + 1);
5052 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: get(Opcode: RISCV::SLLI), DestReg: ScaledRegister)
5053 .addReg(RegNo: DestReg)
5054 .addImm(Val: ShiftAmount)
5055 .setMIFlag(Flag);
5056 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: get(Opcode: RISCV::SUB), DestReg)
5057 .addReg(RegNo: ScaledRegister, Flags: RegState::Kill)
5058 .addReg(RegNo: DestReg, Flags: RegState::Kill)
5059 .setMIFlag(Flag);
5060 } else if (STI.hasStdExtZmmul()) {
5061 Register N = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
5062 movImm(MBB, MBBI: II, DL, DstReg: N, Val: Amount, Flag);
5063 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: get(Opcode: RISCV::MUL), DestReg)
5064 .addReg(RegNo: DestReg, Flags: RegState::Kill)
5065 .addReg(RegNo: N, Flags: RegState::Kill)
5066 .setMIFlag(Flag);
5067 } else {
5068 Register Acc;
5069 uint32_t PrevShiftAmount = 0;
5070 for (uint32_t ShiftAmount = 0; Amount >> ShiftAmount; ShiftAmount++) {
5071 if (Amount & (1U << ShiftAmount)) {
5072 if (ShiftAmount)
5073 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: get(Opcode: RISCV::SLLI), DestReg)
5074 .addReg(RegNo: DestReg, Flags: RegState::Kill)
5075 .addImm(Val: ShiftAmount - PrevShiftAmount)
5076 .setMIFlag(Flag);
5077 if (Amount >> (ShiftAmount + 1)) {
5078 // If we don't have an accmulator yet, create it and copy DestReg.
5079 if (!Acc) {
5080 Acc = MRI.createVirtualRegister(RegClass: &RISCV::GPRRegClass);
5081 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: get(Opcode: TargetOpcode::COPY), DestReg: Acc)
5082 .addReg(RegNo: DestReg)
5083 .setMIFlag(Flag);
5084 } else {
5085 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: get(Opcode: RISCV::ADD), DestReg: Acc)
5086 .addReg(RegNo: Acc, Flags: RegState::Kill)
5087 .addReg(RegNo: DestReg)
5088 .setMIFlag(Flag);
5089 }
5090 }
5091 PrevShiftAmount = ShiftAmount;
5092 }
5093 }
5094 assert(Acc && "Expected valid accumulator");
5095 BuildMI(BB&: MBB, I: II, MIMD: DL, MCID: get(Opcode: RISCV::ADD), DestReg)
5096 .addReg(RegNo: DestReg, Flags: RegState::Kill)
5097 .addReg(RegNo: Acc, Flags: RegState::Kill)
5098 .setMIFlag(Flag);
5099 }
5100}
5101
5102ArrayRef<std::pair<MachineMemOperand::Flags, const char *>>
5103RISCVInstrInfo::getSerializableMachineMemOperandTargetFlags() const {
5104 static const std::pair<MachineMemOperand::Flags, const char *> TargetFlags[] =
5105 {{MONontemporalBit0, "riscv-nontemporal-domain-bit-0"},
5106 {MONontemporalBit1, "riscv-nontemporal-domain-bit-1"}};
5107 return ArrayRef(TargetFlags);
5108}
5109
5110unsigned RISCVInstrInfo::getTailDuplicateSize(CodeGenOptLevel OptLevel) const {
5111 return OptLevel >= CodeGenOptLevel::Aggressive
5112 ? STI.getTailDupAggressiveThreshold()
5113 : 2;
5114}
5115
5116bool RISCV::isRVVSpill(const MachineInstr &MI) {
5117 // RVV lacks any support for immediate addressing for stack addresses, so be
5118 // conservative.
5119 unsigned Opcode = MI.getOpcode();
5120 if (!RISCVVPseudosTable::getPseudoInfo(Pseudo: Opcode) &&
5121 !getLMULForRVVWholeLoadStore(Opcode) && !isRVVSpillForZvlsseg(Opcode))
5122 return false;
5123 return true;
5124}
5125
5126/// Return true if \p MI is a copy that will be lowered to one or more vmvNr.vs.
5127bool RISCV::isVectorCopy(const TargetRegisterInfo *TRI,
5128 const MachineInstr &MI) {
5129 return MI.isCopy() && MI.getOperand(i: 0).getReg().isPhysical() &&
5130 RISCVRegisterInfo::isRVVRegClass(
5131 RC: TRI->getMinimalPhysRegClass(Reg: MI.getOperand(i: 0).getReg()));
5132}
5133
5134std::optional<std::pair<unsigned, unsigned>>
5135RISCV::isRVVSpillForZvlsseg(unsigned Opcode) {
5136 switch (Opcode) {
5137 default:
5138 return std::nullopt;
5139 case RISCV::PseudoVSPILL2_M1:
5140 case RISCV::PseudoVRELOAD2_M1:
5141 return std::make_pair(x: 2u, y: 1u);
5142 case RISCV::PseudoVSPILL2_M2:
5143 case RISCV::PseudoVRELOAD2_M2:
5144 return std::make_pair(x: 2u, y: 2u);
5145 case RISCV::PseudoVSPILL2_M4:
5146 case RISCV::PseudoVRELOAD2_M4:
5147 return std::make_pair(x: 2u, y: 4u);
5148 case RISCV::PseudoVSPILL3_M1:
5149 case RISCV::PseudoVRELOAD3_M1:
5150 return std::make_pair(x: 3u, y: 1u);
5151 case RISCV::PseudoVSPILL3_M2:
5152 case RISCV::PseudoVRELOAD3_M2:
5153 return std::make_pair(x: 3u, y: 2u);
5154 case RISCV::PseudoVSPILL4_M1:
5155 case RISCV::PseudoVRELOAD4_M1:
5156 return std::make_pair(x: 4u, y: 1u);
5157 case RISCV::PseudoVSPILL4_M2:
5158 case RISCV::PseudoVRELOAD4_M2:
5159 return std::make_pair(x: 4u, y: 2u);
5160 case RISCV::PseudoVSPILL5_M1:
5161 case RISCV::PseudoVRELOAD5_M1:
5162 return std::make_pair(x: 5u, y: 1u);
5163 case RISCV::PseudoVSPILL6_M1:
5164 case RISCV::PseudoVRELOAD6_M1:
5165 return std::make_pair(x: 6u, y: 1u);
5166 case RISCV::PseudoVSPILL7_M1:
5167 case RISCV::PseudoVRELOAD7_M1:
5168 return std::make_pair(x: 7u, y: 1u);
5169 case RISCV::PseudoVSPILL8_M1:
5170 case RISCV::PseudoVRELOAD8_M1:
5171 return std::make_pair(x: 8u, y: 1u);
5172 }
5173}
5174
5175bool RISCV::hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2) {
5176 int16_t MI1FrmOpIdx =
5177 RISCV::getNamedOperandIdx(Opcode: MI1.getOpcode(), Name: RISCV::OpName::frm);
5178 int16_t MI2FrmOpIdx =
5179 RISCV::getNamedOperandIdx(Opcode: MI2.getOpcode(), Name: RISCV::OpName::frm);
5180 if (MI1FrmOpIdx < 0 || MI2FrmOpIdx < 0)
5181 return false;
5182 MachineOperand FrmOp1 = MI1.getOperand(i: MI1FrmOpIdx);
5183 MachineOperand FrmOp2 = MI2.getOperand(i: MI2FrmOpIdx);
5184 return FrmOp1.getImm() == FrmOp2.getImm();
5185}
5186
5187std::optional<unsigned>
5188RISCV::getVectorLowDemandedScalarBits(unsigned Opcode, unsigned Log2SEW) {
5189 switch (Opcode) {
5190 default:
5191 return std::nullopt;
5192
5193 // 11.6. Vector Single-Width Shift Instructions
5194 case RISCV::VSLL_VX:
5195 case RISCV::VSRL_VX:
5196 case RISCV::VSRA_VX:
5197 // 12.4. Vector Single-Width Scaling Shift Instructions
5198 case RISCV::VSSRL_VX:
5199 case RISCV::VSSRA_VX:
5200 // Zvbb
5201 case RISCV::VROL_VX:
5202 case RISCV::VROR_VX:
5203 // Only the low lg2(SEW) bits of the shift-amount value are used.
5204 return Log2SEW;
5205
5206 // 11.7 Vector Narrowing Integer Right Shift Instructions
5207 case RISCV::VNSRL_WX:
5208 case RISCV::VNSRA_WX:
5209 // 12.5. Vector Narrowing Fixed-Point Clip Instructions
5210 case RISCV::VNCLIPU_WX:
5211 case RISCV::VNCLIP_WX:
5212 // Zvbb
5213 case RISCV::VWSLL_VX:
5214 // Only the low lg2(2*SEW) bits of the shift-amount value are used.
5215 return Log2SEW + 1;
5216
5217 // 11.1. Vector Single-Width Integer Add and Subtract
5218 case RISCV::VADD_VX:
5219 case RISCV::VSUB_VX:
5220 case RISCV::VRSUB_VX:
5221 // 11.2. Vector Widening Integer Add/Subtract
5222 case RISCV::VWADDU_VX:
5223 case RISCV::VWSUBU_VX:
5224 case RISCV::VWADD_VX:
5225 case RISCV::VWSUB_VX:
5226 case RISCV::VWADDU_WX:
5227 case RISCV::VWSUBU_WX:
5228 case RISCV::VWADD_WX:
5229 case RISCV::VWSUB_WX:
5230 // 11.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
5231 case RISCV::VADC_VXM:
5232 case RISCV::VADC_VIM:
5233 case RISCV::VMADC_VXM:
5234 case RISCV::VMADC_VIM:
5235 case RISCV::VMADC_VX:
5236 case RISCV::VSBC_VXM:
5237 case RISCV::VMSBC_VXM:
5238 case RISCV::VMSBC_VX:
5239 // 11.5 Vector Bitwise Logical Instructions
5240 case RISCV::VAND_VX:
5241 case RISCV::VOR_VX:
5242 case RISCV::VXOR_VX:
5243 // 11.8. Vector Integer Compare Instructions
5244 case RISCV::VMSEQ_VX:
5245 case RISCV::VMSNE_VX:
5246 case RISCV::VMSLTU_VX:
5247 case RISCV::VMSLT_VX:
5248 case RISCV::VMSLEU_VX:
5249 case RISCV::VMSLE_VX:
5250 case RISCV::VMSGTU_VX:
5251 case RISCV::VMSGT_VX:
5252 // 11.9. Vector Integer Min/Max Instructions
5253 case RISCV::VMINU_VX:
5254 case RISCV::VMIN_VX:
5255 case RISCV::VMAXU_VX:
5256 case RISCV::VMAX_VX:
5257 // 11.10. Vector Single-Width Integer Multiply Instructions
5258 case RISCV::VMUL_VX:
5259 case RISCV::VMULH_VX:
5260 case RISCV::VMULHU_VX:
5261 case RISCV::VMULHSU_VX:
5262 // 11.11. Vector Integer Divide Instructions
5263 case RISCV::VDIVU_VX:
5264 case RISCV::VDIV_VX:
5265 case RISCV::VREMU_VX:
5266 case RISCV::VREM_VX:
5267 // 11.12. Vector Widening Integer Multiply Instructions
5268 case RISCV::VWMUL_VX:
5269 case RISCV::VWMULU_VX:
5270 case RISCV::VWMULSU_VX:
5271 // 11.13. Vector Single-Width Integer Multiply-Add Instructions
5272 case RISCV::VMACC_VX:
5273 case RISCV::VNMSAC_VX:
5274 case RISCV::VMADD_VX:
5275 case RISCV::VNMSUB_VX:
5276 // 11.14. Vector Widening Integer Multiply-Add Instructions
5277 case RISCV::VWMACCU_VX:
5278 case RISCV::VWMACC_VX:
5279 case RISCV::VWMACCSU_VX:
5280 case RISCV::VWMACCUS_VX:
5281 // 11.15. Vector Integer Merge Instructions
5282 case RISCV::VMERGE_VXM:
5283 // 11.16. Vector Integer Move Instructions
5284 case RISCV::VMV_V_X:
5285 // 12.1. Vector Single-Width Saturating Add and Subtract
5286 case RISCV::VSADDU_VX:
5287 case RISCV::VSADD_VX:
5288 case RISCV::VSSUBU_VX:
5289 case RISCV::VSSUB_VX:
5290 // 12.2. Vector Single-Width Averaging Add and Subtract
5291 case RISCV::VAADDU_VX:
5292 case RISCV::VAADD_VX:
5293 case RISCV::VASUBU_VX:
5294 case RISCV::VASUB_VX:
5295 // 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation
5296 case RISCV::VSMUL_VX:
5297 // 16.1. Integer Scalar Move Instructions
5298 case RISCV::VMV_S_X:
5299 // Zvbb
5300 case RISCV::VANDN_VX:
5301 return 1U << Log2SEW;
5302 }
5303}
5304
5305unsigned RISCV::getRVVMCOpcode(unsigned RVVPseudoOpcode) {
5306 const RISCVVPseudosTable::PseudoInfo *RVV =
5307 RISCVVPseudosTable::getPseudoInfo(Pseudo: RVVPseudoOpcode);
5308 if (!RVV)
5309 return 0;
5310 return RVV->BaseInstr;
5311}
5312
5313unsigned RISCV::getDestLog2EEW(const MCInstrDesc &Desc, unsigned Log2SEW) {
5314 unsigned DestEEW =
5315 (Desc.TSFlags & RISCVII::DestEEWMask) >> RISCVII::DestEEWShift;
5316 // EEW = 1
5317 if (DestEEW == 0)
5318 return 0;
5319 // EEW = SEW * n
5320 unsigned Scaled = Log2SEW + (DestEEW - 1);
5321 assert(Scaled >= 3 && Scaled <= 6);
5322 return Scaled;
5323}
5324
5325static std::optional<int64_t> getEffectiveImm(const MachineOperand &MO) {
5326 assert(MO.isImm() || MO.getReg().isVirtual());
5327 if (MO.isImm())
5328 return MO.getImm();
5329 const MachineInstr *Def =
5330 MO.getParent()->getMF()->getRegInfo().getVRegDef(Reg: MO.getReg());
5331 int64_t Imm;
5332 if (isLoadImm(MI: Def, Imm))
5333 return Imm;
5334 return std::nullopt;
5335}
5336
5337/// Given two VL operands, do we know that LHS <= RHS? Must be used in SSA form.
5338bool RISCV::isVLKnownLE(const MachineOperand &LHS, const MachineOperand &RHS) {
5339 assert((LHS.isImm() || LHS.getParent()->getMF()->getRegInfo().isSSA()) &&
5340 (RHS.isImm() || RHS.getParent()->getMF()->getRegInfo().isSSA()));
5341 if (LHS.isReg() && RHS.isReg() && LHS.getReg().isVirtual() &&
5342 LHS.getReg() == RHS.getReg())
5343 return true;
5344 if (RHS.isImm() && RHS.getImm() == RISCV::VLMaxSentinel)
5345 return true;
5346 if (LHS.isImm() && LHS.getImm() == 0)
5347 return true;
5348 if (LHS.isImm() && LHS.getImm() == RISCV::VLMaxSentinel)
5349 return false;
5350 std::optional<int64_t> LHSImm = getEffectiveImm(MO: LHS),
5351 RHSImm = getEffectiveImm(MO: RHS);
5352 if (!LHSImm || !RHSImm)
5353 return false;
5354 return LHSImm <= RHSImm;
5355}
5356
5357namespace {
5358class RISCVPipelinerLoopInfo : public TargetInstrInfo::PipelinerLoopInfo {
5359 const MachineInstr *LHS;
5360 const MachineInstr *RHS;
5361 SmallVector<MachineOperand, 3> Cond;
5362
5363public:
5364 RISCVPipelinerLoopInfo(const MachineInstr *LHS, const MachineInstr *RHS,
5365 const SmallVectorImpl<MachineOperand> &Cond)
5366 : LHS(LHS), RHS(RHS), Cond(Cond.begin(), Cond.end()) {}
5367
5368 bool shouldIgnoreForPipelining(const MachineInstr *MI) const override {
5369 // Make the instructions for loop control be placed in stage 0.
5370 // The predecessors of LHS/RHS are considered by the caller.
5371 if (LHS && MI == LHS)
5372 return true;
5373 if (RHS && MI == RHS)
5374 return true;
5375 return false;
5376 }
5377
5378 std::optional<bool> createTripCountGreaterCondition(
5379 int TC, MachineBasicBlock &MBB,
5380 SmallVectorImpl<MachineOperand> &CondParam) override {
5381 // A branch instruction will be inserted as "if (Cond) goto epilogue".
5382 // Cond is normalized for such use.
5383 // The predecessors of the branch are assumed to have already been inserted.
5384 CondParam = Cond;
5385 return {};
5386 }
5387
5388 void setPreheader(MachineBasicBlock *NewPreheader) override {}
5389
5390 void adjustTripCount(int TripCountAdjust) override {}
5391};
5392} // namespace
5393
5394std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo>
5395RISCVInstrInfo::analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const {
5396 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
5397 SmallVector<MachineOperand, 4> Cond;
5398 if (analyzeBranch(MBB&: *LoopBB, TBB, FBB, Cond, /*AllowModify=*/false))
5399 return nullptr;
5400
5401 // Infinite loops are not supported
5402 if (TBB == LoopBB && FBB == LoopBB)
5403 return nullptr;
5404
5405 // Must be conditional branch
5406 if (FBB == nullptr)
5407 return nullptr;
5408
5409 assert((TBB == LoopBB || FBB == LoopBB) &&
5410 "The Loop must be a single-basic-block loop");
5411
5412 // Normalization for createTripCountGreaterCondition()
5413 if (TBB == LoopBB)
5414 reverseBranchCondition(Cond);
5415
5416 const MachineRegisterInfo &MRI = LoopBB->getParent()->getRegInfo();
5417 auto FindRegDef = [&MRI](MachineOperand &Op) -> const MachineInstr * {
5418 if (!Op.isReg())
5419 return nullptr;
5420 Register Reg = Op.getReg();
5421 if (!Reg.isVirtual())
5422 return nullptr;
5423 return MRI.getVRegDef(Reg);
5424 };
5425
5426 const MachineInstr *LHS = FindRegDef(Cond[1]);
5427 const MachineInstr *RHS = FindRegDef(Cond[2]);
5428 if (LHS && LHS->isPHI())
5429 return nullptr;
5430 if (RHS && RHS->isPHI())
5431 return nullptr;
5432
5433 return std::make_unique<RISCVPipelinerLoopInfo>(args&: LHS, args&: RHS, args&: Cond);
5434}
5435
5436// FIXME: We should remove this if we have a default generic scheduling model.
5437bool RISCVInstrInfo::isHighLatencyDef(int Opc) const {
5438 unsigned RVVMCOpcode = RISCV::getRVVMCOpcode(RVVPseudoOpcode: Opc);
5439 Opc = RVVMCOpcode ? RVVMCOpcode : Opc;
5440 switch (Opc) {
5441 default:
5442 return false;
5443 // Integer div/rem.
5444 case RISCV::DIV:
5445 case RISCV::DIVW:
5446 case RISCV::DIVU:
5447 case RISCV::DIVUW:
5448 case RISCV::REM:
5449 case RISCV::REMW:
5450 case RISCV::REMU:
5451 case RISCV::REMUW:
5452 // Floating-point div/sqrt.
5453 case RISCV::FDIV_H:
5454 case RISCV::FDIV_S:
5455 case RISCV::FDIV_D:
5456 case RISCV::FDIV_H_INX:
5457 case RISCV::FDIV_S_INX:
5458 case RISCV::FDIV_D_INX:
5459 case RISCV::FDIV_D_IN32X:
5460 case RISCV::FSQRT_H:
5461 case RISCV::FSQRT_S:
5462 case RISCV::FSQRT_D:
5463 case RISCV::FSQRT_H_INX:
5464 case RISCV::FSQRT_S_INX:
5465 case RISCV::FSQRT_D_INX:
5466 case RISCV::FSQRT_D_IN32X:
5467 // Vector integer div/rem
5468 case RISCV::VDIV_VV:
5469 case RISCV::VDIV_VX:
5470 case RISCV::VDIVU_VV:
5471 case RISCV::VDIVU_VX:
5472 case RISCV::VREM_VV:
5473 case RISCV::VREM_VX:
5474 case RISCV::VREMU_VV:
5475 case RISCV::VREMU_VX:
5476 // Vector floating-point div/sqrt.
5477 case RISCV::VFDIV_VV:
5478 case RISCV::VFDIV_VF:
5479 case RISCV::VFRDIV_VF:
5480 case RISCV::VFSQRT_V:
5481 case RISCV::VFRSQRT7_V:
5482 return true;
5483 }
5484}
5485
5486bool RISCVInstrInfo::isVRegCopy(const MachineInstr *MI, unsigned LMul) const {
5487 if (MI->getOpcode() != TargetOpcode::COPY)
5488 return false;
5489 const MachineRegisterInfo &MRI = MI->getMF()->getRegInfo();
5490 const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
5491
5492 Register DstReg = MI->getOperand(i: 0).getReg();
5493 const TargetRegisterClass *RC = DstReg.isVirtual()
5494 ? MRI.getRegClass(Reg: DstReg)
5495 : TRI->getMinimalPhysRegClass(Reg: DstReg);
5496
5497 if (!RISCVRegisterInfo::isRVVRegClass(RC))
5498 return false;
5499
5500 if (!LMul)
5501 return true;
5502
5503 // TODO: Perhaps we could distinguish segment register classes (e.g. VRN3M2)
5504 // in the future.
5505 auto [RCLMul, RCFractional] =
5506 RISCVVType::decodeVLMUL(VLMul: RISCVRI::getLMul(TSFlags: RC->TSFlags));
5507 return (!RCFractional && LMul == RCLMul) || (RCFractional && LMul == 1);
5508}
5509
5510bool RISCVInstrInfo::requiresNTLHint(const MachineInstr &MI) const {
5511 if (MI.memoperands_empty())
5512 return false;
5513
5514 MachineMemOperand *MMO = *(MI.memoperands_begin());
5515 if (!MMO->isNonTemporal())
5516 return false;
5517
5518 return true;
5519}
5520
5521bool RISCVInstrInfo::isSafeToMove(const MachineInstr &From,
5522 const MachineBasicBlock::iterator &To) {
5523 assert(To == From.getParent()->end() || From.getParent() == To->getParent());
5524 SmallVector<Register> PhysUses, PhysDefs;
5525 for (const MachineOperand &MO : From.all_uses())
5526 if (MO.getReg().isPhysical())
5527 PhysUses.push_back(Elt: MO.getReg());
5528 for (const MachineOperand &MO : From.all_defs())
5529 if (MO.getReg().isPhysical())
5530 PhysDefs.push_back(Elt: MO.getReg());
5531 bool SawStore = false;
5532 for (auto II = std::next(x: From.getIterator()); II != To; II++) {
5533 for (Register PhysReg : PhysUses)
5534 if (II->definesRegister(Reg: PhysReg, TRI: nullptr))
5535 return false;
5536 for (Register PhysReg : PhysDefs)
5537 if (II->definesRegister(Reg: PhysReg, TRI: nullptr) ||
5538 II->readsRegister(Reg: PhysReg, TRI: nullptr))
5539 return false;
5540 if (II->mayStore()) {
5541 SawStore = true;
5542 break;
5543 }
5544 }
5545 return From.isSafeToMove(SawStore);
5546}
5547