1//===-- SparcInstrInfo.cpp - Sparc Instruction Information ----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Sparc implementation of the TargetInstrInfo class.
10//
11//===----------------------------------------------------------------------===//
12
13#include "SparcInstrInfo.h"
14#include "Sparc.h"
15#include "SparcMachineFunctionInfo.h"
16#include "SparcSubtarget.h"
17#include "llvm/ADT/SmallVector.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/CodeGen/MachineMemOperand.h"
21#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/Support/ErrorHandling.h"
23
24using namespace llvm;
25
26#define GET_INSTRINFO_CTOR_DTOR
27#include "SparcGenInstrInfo.inc"
28
29static cl::opt<unsigned> BPccDisplacementBits(
30 "sparc-bpcc-offset-bits", cl::Hidden, cl::init(Val: 19),
31 cl::desc("Restrict range of BPcc/FBPfcc instructions (DEBUG)"));
32
33static cl::opt<unsigned>
34 BPrDisplacementBits("sparc-bpr-offset-bits", cl::Hidden, cl::init(Val: 16),
35 cl::desc("Restrict range of BPr instructions (DEBUG)"));
36
37// Pin the vtable to this file.
38void SparcInstrInfo::anchor() {}
39
40SparcInstrInfo::SparcInstrInfo(const SparcSubtarget &ST)
41 : SparcGenInstrInfo(ST, RI, SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
42 RI(ST), Subtarget(ST) {}
43
44const TargetRegisterClass *SparcInstrInfo::getInlineAsmMemoryOperandRegClass(
45 InlineAsm::ConstraintCode C) const {
46 return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
47}
48
49/// isLoadFromStackSlot - If the specified machine instruction is a direct
50/// load from a stack slot, return the virtual or physical register number of
51/// the destination along with the FrameIndex of the loaded stack slot. If
52/// not, return 0. This predicate must return 0 if the instruction has
53/// any side effects other than loading from the stack slot.
54Register SparcInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
55 int &FrameIndex,
56 TypeSize &MemBytes) const {
57 switch (MI.getOpcode()) {
58 default:
59 return 0;
60 case SP::LDri:
61 MemBytes = TypeSize::getFixed(ExactSize: 4);
62 break;
63 case SP::LDXri:
64 MemBytes = TypeSize::getFixed(ExactSize: 8);
65 break;
66 case SP::LDFri:
67 MemBytes = TypeSize::getFixed(ExactSize: 4);
68 break;
69 case SP::LDDFri:
70 MemBytes = TypeSize::getFixed(ExactSize: 8);
71 break;
72 case SP::LDQFri:
73 MemBytes = TypeSize::getFixed(ExactSize: 16);
74 break;
75 }
76 if (MI.getOperand(i: 1).isFI() && MI.getOperand(i: 2).isImm() &&
77 MI.getOperand(i: 2).getImm() == 0) {
78 FrameIndex = MI.getOperand(i: 1).getIndex();
79 return MI.getOperand(i: 0).getReg();
80 }
81 return 0;
82}
83
84/// isStoreToStackSlot - If the specified machine instruction is a direct
85/// store to a stack slot, return the virtual or physical register number of
86/// the source reg along with the FrameIndex of the loaded stack slot. If
87/// not, return 0. This predicate must return 0 if the instruction has
88/// any side effects other than storing to the stack slot.
89Register SparcInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
90 int &FrameIndex,
91 TypeSize &MemBytes) const {
92 switch (MI.getOpcode()) {
93 default:
94 return 0;
95 case SP::STri:
96 MemBytes = TypeSize::getFixed(ExactSize: 4);
97 break;
98 case SP::STXri:
99 MemBytes = TypeSize::getFixed(ExactSize: 8);
100 break;
101 case SP::STFri:
102 MemBytes = TypeSize::getFixed(ExactSize: 4);
103 break;
104 case SP::STDFri:
105 MemBytes = TypeSize::getFixed(ExactSize: 8);
106 break;
107 case SP::STQFri:
108 MemBytes = TypeSize::getFixed(ExactSize: 16);
109 break;
110 }
111 if (MI.getOperand(i: 0).isFI() && MI.getOperand(i: 1).isImm() &&
112 MI.getOperand(i: 1).getImm() == 0) {
113 FrameIndex = MI.getOperand(i: 0).getIndex();
114 return MI.getOperand(i: 2).getReg();
115 }
116 return 0;
117}
118
119static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
120{
121 switch(CC) {
122 case SPCC::ICC_A: return SPCC::ICC_N;
123 case SPCC::ICC_N: return SPCC::ICC_A;
124 case SPCC::ICC_NE: return SPCC::ICC_E;
125 case SPCC::ICC_E: return SPCC::ICC_NE;
126 case SPCC::ICC_G: return SPCC::ICC_LE;
127 case SPCC::ICC_LE: return SPCC::ICC_G;
128 case SPCC::ICC_GE: return SPCC::ICC_L;
129 case SPCC::ICC_L: return SPCC::ICC_GE;
130 case SPCC::ICC_GU: return SPCC::ICC_LEU;
131 case SPCC::ICC_LEU: return SPCC::ICC_GU;
132 case SPCC::ICC_CC: return SPCC::ICC_CS;
133 case SPCC::ICC_CS: return SPCC::ICC_CC;
134 case SPCC::ICC_POS: return SPCC::ICC_NEG;
135 case SPCC::ICC_NEG: return SPCC::ICC_POS;
136 case SPCC::ICC_VC: return SPCC::ICC_VS;
137 case SPCC::ICC_VS: return SPCC::ICC_VC;
138
139 case SPCC::FCC_A: return SPCC::FCC_N;
140 case SPCC::FCC_N: return SPCC::FCC_A;
141 case SPCC::FCC_U: return SPCC::FCC_O;
142 case SPCC::FCC_O: return SPCC::FCC_U;
143 case SPCC::FCC_G: return SPCC::FCC_ULE;
144 case SPCC::FCC_LE: return SPCC::FCC_UG;
145 case SPCC::FCC_UG: return SPCC::FCC_LE;
146 case SPCC::FCC_ULE: return SPCC::FCC_G;
147 case SPCC::FCC_L: return SPCC::FCC_UGE;
148 case SPCC::FCC_GE: return SPCC::FCC_UL;
149 case SPCC::FCC_UL: return SPCC::FCC_GE;
150 case SPCC::FCC_UGE: return SPCC::FCC_L;
151 case SPCC::FCC_LG: return SPCC::FCC_UE;
152 case SPCC::FCC_UE: return SPCC::FCC_LG;
153 case SPCC::FCC_NE: return SPCC::FCC_E;
154 case SPCC::FCC_E: return SPCC::FCC_NE;
155
156 case SPCC::CPCC_A: return SPCC::CPCC_N;
157 case SPCC::CPCC_N: return SPCC::CPCC_A;
158 case SPCC::CPCC_3: [[fallthrough]];
159 case SPCC::CPCC_2: [[fallthrough]];
160 case SPCC::CPCC_23: [[fallthrough]];
161 case SPCC::CPCC_1: [[fallthrough]];
162 case SPCC::CPCC_13: [[fallthrough]];
163 case SPCC::CPCC_12: [[fallthrough]];
164 case SPCC::CPCC_123: [[fallthrough]];
165 case SPCC::CPCC_0: [[fallthrough]];
166 case SPCC::CPCC_03: [[fallthrough]];
167 case SPCC::CPCC_02: [[fallthrough]];
168 case SPCC::CPCC_023: [[fallthrough]];
169 case SPCC::CPCC_01: [[fallthrough]];
170 case SPCC::CPCC_013: [[fallthrough]];
171 case SPCC::CPCC_012:
172 // "Opposite" code is not meaningful, as we don't know
173 // what the CoProc condition means here. The cond-code will
174 // only be used in inline assembler, so this code should
175 // not be reached in a normal compilation pass.
176 llvm_unreachable("Meaningless inversion of co-processor cond code");
177
178 case SPCC::REG_BEGIN:
179 llvm_unreachable("Use of reserved cond code");
180 case SPCC::REG_Z:
181 return SPCC::REG_NZ;
182 case SPCC::REG_LEZ:
183 return SPCC::REG_GZ;
184 case SPCC::REG_LZ:
185 return SPCC::REG_GEZ;
186 case SPCC::REG_NZ:
187 return SPCC::REG_Z;
188 case SPCC::REG_GZ:
189 return SPCC::REG_LEZ;
190 case SPCC::REG_GEZ:
191 return SPCC::REG_LZ;
192 }
193 llvm_unreachable("Invalid cond code");
194}
195
196static bool isUncondBranchOpcode(int Opc) { return Opc == SP::BA; }
197
198static bool isI32CondBranchOpcode(int Opc) {
199 return Opc == SP::BCOND || Opc == SP::BPICC || Opc == SP::BPICCA ||
200 Opc == SP::BPICCNT || Opc == SP::BPICCANT;
201}
202
203static bool isI64CondBranchOpcode(int Opc) {
204 return Opc == SP::BPXCC || Opc == SP::BPXCCA || Opc == SP::BPXCCNT ||
205 Opc == SP::BPXCCANT;
206}
207
208static bool isRegCondBranchOpcode(int Opc) {
209 return Opc == SP::BPR || Opc == SP::BPRA || Opc == SP::BPRNT ||
210 Opc == SP::BPRANT;
211}
212
213static bool isFCondBranchOpcode(int Opc) {
214 return Opc == SP::FBCOND || Opc == SP::FBCONDA || Opc == SP::FBCOND_V9 ||
215 Opc == SP::FBCONDA_V9;
216}
217
218static bool isCondBranchOpcode(int Opc) {
219 return isI32CondBranchOpcode(Opc) || isI64CondBranchOpcode(Opc) ||
220 isRegCondBranchOpcode(Opc) || isFCondBranchOpcode(Opc);
221}
222
223static bool isIndirectBranchOpcode(int Opc) {
224 return Opc == SP::BINDrr || Opc == SP::BINDri;
225}
226
227static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target,
228 SmallVectorImpl<MachineOperand> &Cond) {
229 unsigned Opc = LastInst->getOpcode();
230 int64_t CC = LastInst->getOperand(i: 1).getImm();
231
232 // Push the branch opcode into Cond too so later in insertBranch
233 // it can use the information to emit the correct SPARC branch opcode.
234 Cond.push_back(Elt: MachineOperand::CreateImm(Val: Opc));
235 Cond.push_back(Elt: MachineOperand::CreateImm(Val: CC));
236
237 // Branch on register contents need another argument to indicate
238 // the register it branches on.
239 if (isRegCondBranchOpcode(Opc)) {
240 Register Reg = LastInst->getOperand(i: 2).getReg();
241 Cond.push_back(Elt: MachineOperand::CreateReg(Reg, isDef: false));
242 }
243
244 Target = LastInst->getOperand(i: 0).getMBB();
245}
246
247MachineBasicBlock *
248SparcInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
249 switch (MI.getOpcode()) {
250 default:
251 llvm_unreachable("unexpected opcode!");
252 case SP::BA:
253 case SP::BCOND:
254 case SP::BCONDA:
255 case SP::FBCOND:
256 case SP::FBCONDA:
257 case SP::BPICC:
258 case SP::BPICCA:
259 case SP::BPICCNT:
260 case SP::BPICCANT:
261 case SP::BPXCC:
262 case SP::BPXCCA:
263 case SP::BPXCCNT:
264 case SP::BPXCCANT:
265 case SP::BPFCC:
266 case SP::BPFCCA:
267 case SP::BPFCCNT:
268 case SP::BPFCCANT:
269 case SP::FBCOND_V9:
270 case SP::FBCONDA_V9:
271 case SP::BPR:
272 case SP::BPRA:
273 case SP::BPRNT:
274 case SP::BPRANT:
275 return MI.getOperand(i: 0).getMBB();
276 }
277}
278
279bool SparcInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
280 MachineBasicBlock *&TBB,
281 MachineBasicBlock *&FBB,
282 SmallVectorImpl<MachineOperand> &Cond,
283 bool AllowModify) const {
284 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
285 if (I == MBB.end())
286 return false;
287
288 if (!isUnpredicatedTerminator(MI: *I))
289 return false;
290
291 // Get the last instruction in the block.
292 MachineInstr *LastInst = &*I;
293 unsigned LastOpc = LastInst->getOpcode();
294
295 // If there is only one terminator instruction, process it.
296 if (I == MBB.begin() || !isUnpredicatedTerminator(MI: *--I)) {
297 if (isUncondBranchOpcode(Opc: LastOpc)) {
298 TBB = LastInst->getOperand(i: 0).getMBB();
299 return false;
300 }
301 if (isCondBranchOpcode(Opc: LastOpc)) {
302 // Block ends with fall-through condbranch.
303 parseCondBranch(LastInst, Target&: TBB, Cond);
304 return false;
305 }
306 return true; // Can't handle indirect branch.
307 }
308
309 // Get the instruction before it if it is a terminator.
310 MachineInstr *SecondLastInst = &*I;
311 unsigned SecondLastOpc = SecondLastInst->getOpcode();
312
313 // If AllowModify is true and the block ends with two or more unconditional
314 // branches, delete all but the first unconditional branch.
315 if (AllowModify && isUncondBranchOpcode(Opc: LastOpc)) {
316 while (isUncondBranchOpcode(Opc: SecondLastOpc)) {
317 LastInst->eraseFromParent();
318 LastInst = SecondLastInst;
319 LastOpc = LastInst->getOpcode();
320 if (I == MBB.begin() || !isUnpredicatedTerminator(MI: *--I)) {
321 // Return now the only terminator is an unconditional branch.
322 TBB = LastInst->getOperand(i: 0).getMBB();
323 return false;
324 } else {
325 SecondLastInst = &*I;
326 SecondLastOpc = SecondLastInst->getOpcode();
327 }
328 }
329 }
330
331 // If there are three terminators, we don't know what sort of block this is.
332 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(MI: *--I))
333 return true;
334
335 // If the block ends with a B and a Bcc, handle it.
336 if (isCondBranchOpcode(Opc: SecondLastOpc) && isUncondBranchOpcode(Opc: LastOpc)) {
337 parseCondBranch(LastInst: SecondLastInst, Target&: TBB, Cond);
338 FBB = LastInst->getOperand(i: 0).getMBB();
339 return false;
340 }
341
342 // If the block ends with two unconditional branches, handle it. The second
343 // one is not executed.
344 if (isUncondBranchOpcode(Opc: SecondLastOpc) && isUncondBranchOpcode(Opc: LastOpc)) {
345 TBB = SecondLastInst->getOperand(i: 0).getMBB();
346 return false;
347 }
348
349 // ...likewise if it ends with an indirect branch followed by an unconditional
350 // branch.
351 if (isIndirectBranchOpcode(Opc: SecondLastOpc) && isUncondBranchOpcode(Opc: LastOpc)) {
352 I = LastInst;
353 if (AllowModify)
354 I->eraseFromParent();
355 return true;
356 }
357
358 // Otherwise, can't handle this.
359 return true;
360}
361
362unsigned SparcInstrInfo::insertBranch(MachineBasicBlock &MBB,
363 MachineBasicBlock *TBB,
364 MachineBasicBlock *FBB,
365 ArrayRef<MachineOperand> Cond,
366 const DebugLoc &DL,
367 int *BytesAdded) const {
368 assert(TBB && "insertBranch must not be told to insert a fallthrough");
369 assert((Cond.size() <= 3) &&
370 "Sparc branch conditions should have at most three components!");
371
372 if (Cond.empty()) {
373 assert(!FBB && "Unconditional branch with multiple successors!");
374 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: SP::BA)).addMBB(MBB: TBB);
375 if (BytesAdded)
376 *BytesAdded = 8;
377 return 1;
378 }
379
380 // Conditional branch
381 unsigned Opc = Cond[0].getImm();
382 unsigned CC = Cond[1].getImm();
383 if (isRegCondBranchOpcode(Opc)) {
384 Register Reg = Cond[2].getReg();
385 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: Opc)).addMBB(MBB: TBB).addImm(Val: CC).addReg(RegNo: Reg);
386 } else {
387 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: Opc)).addMBB(MBB: TBB).addImm(Val: CC);
388 }
389
390 if (!FBB) {
391 if (BytesAdded)
392 *BytesAdded = 8;
393 return 1;
394 }
395
396 BuildMI(BB: &MBB, MIMD: DL, MCID: get(Opcode: SP::BA)).addMBB(MBB: FBB);
397 if (BytesAdded)
398 *BytesAdded = 16;
399 return 2;
400}
401
402unsigned SparcInstrInfo::removeBranch(MachineBasicBlock &MBB,
403 int *BytesRemoved) const {
404 MachineBasicBlock::iterator I = MBB.end();
405 unsigned Count = 0;
406 int Removed = 0;
407 while (I != MBB.begin()) {
408 --I;
409
410 if (I->isDebugInstr())
411 continue;
412
413 if (!isCondBranchOpcode(Opc: I->getOpcode()) &&
414 !isUncondBranchOpcode(Opc: I->getOpcode()))
415 break; // Not a branch
416
417 Removed += getInstSizeInBytes(MI: *I);
418 I->eraseFromParent();
419 I = MBB.end();
420 ++Count;
421 }
422
423 if (BytesRemoved)
424 *BytesRemoved = Removed;
425 return Count;
426}
427
428bool SparcInstrInfo::reverseBranchCondition(
429 SmallVectorImpl<MachineOperand> &Cond) const {
430 assert(Cond.size() <= 3);
431 SPCC::CondCodes CC = static_cast<SPCC::CondCodes>(Cond[1].getImm());
432 Cond[1].setImm(GetOppositeBranchCondition(CC));
433 return false;
434}
435
436bool SparcInstrInfo::isBranchOffsetInRange(unsigned BranchOpc,
437 int64_t Offset) const {
438 assert((Offset & 0b11) == 0 && "Malformed branch offset");
439 switch (BranchOpc) {
440 case SP::BA:
441 case SP::BCOND:
442 case SP::BCONDA:
443 case SP::FBCOND:
444 case SP::FBCONDA:
445 return isIntN(N: 22, x: Offset >> 2);
446
447 case SP::BPICC:
448 case SP::BPICCA:
449 case SP::BPICCNT:
450 case SP::BPICCANT:
451 case SP::BPXCC:
452 case SP::BPXCCA:
453 case SP::BPXCCNT:
454 case SP::BPXCCANT:
455 case SP::BPFCC:
456 case SP::BPFCCA:
457 case SP::BPFCCNT:
458 case SP::BPFCCANT:
459 case SP::FBCOND_V9:
460 case SP::FBCONDA_V9:
461 return isIntN(N: BPccDisplacementBits, x: Offset >> 2);
462
463 case SP::BPR:
464 case SP::BPRA:
465 case SP::BPRNT:
466 case SP::BPRANT:
467 return isIntN(N: BPrDisplacementBits, x: Offset >> 2);
468 }
469
470 llvm_unreachable("Unknown branch instruction!");
471}
472
473void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
474 MachineBasicBlock::iterator I,
475 const DebugLoc &DL, Register DestReg,
476 Register SrcReg, bool KillSrc,
477 bool RenamableDest, bool RenamableSrc) const {
478 unsigned numSubRegs = 0;
479 unsigned movOpc = 0;
480 const unsigned *subRegIdx = nullptr;
481 bool ExtraG0 = false;
482
483 const unsigned DW_SubRegsIdx[] = { SP::sub_even, SP::sub_odd };
484 const unsigned DFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd };
485 const unsigned QFP_DFP_SubRegsIdx[] = { SP::sub_even64, SP::sub_odd64 };
486 const unsigned QFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd,
487 SP::sub_odd64_then_sub_even,
488 SP::sub_odd64_then_sub_odd };
489
490 if (SP::IntRegsRegClass.contains(Reg1: DestReg, Reg2: SrcReg))
491 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: SP::ORrr), DestReg).addReg(RegNo: SP::G0)
492 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrc));
493 else if (SP::IntPairRegClass.contains(Reg1: DestReg, Reg2: SrcReg)) {
494 subRegIdx = DW_SubRegsIdx;
495 numSubRegs = 2;
496 movOpc = SP::ORrr;
497 ExtraG0 = true;
498 } else if (SP::FPRegsRegClass.contains(Reg1: DestReg, Reg2: SrcReg))
499 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: SP::FMOVS), DestReg)
500 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrc));
501 else if (SP::DFPRegsRegClass.contains(Reg1: DestReg, Reg2: SrcReg)) {
502 if (Subtarget.isV9()) {
503 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: SP::FMOVD), DestReg)
504 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrc));
505 } else {
506 // Use two FMOVS instructions.
507 subRegIdx = DFP_FP_SubRegsIdx;
508 numSubRegs = 2;
509 movOpc = SP::FMOVS;
510 }
511 } else if (SP::QFPRegsRegClass.contains(Reg1: DestReg, Reg2: SrcReg)) {
512 if (Subtarget.isV9()) {
513 if (Subtarget.hasHardQuad()) {
514 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: SP::FMOVQ), DestReg)
515 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrc));
516 } else {
517 // Use two FMOVD instructions.
518 subRegIdx = QFP_DFP_SubRegsIdx;
519 numSubRegs = 2;
520 movOpc = SP::FMOVD;
521 }
522 } else {
523 // Use four FMOVS instructions.
524 subRegIdx = QFP_FP_SubRegsIdx;
525 numSubRegs = 4;
526 movOpc = SP::FMOVS;
527 }
528 } else if (SP::ASRRegsRegClass.contains(Reg: DestReg) &&
529 SP::IntRegsRegClass.contains(Reg: SrcReg)) {
530 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: SP::WRASRrr), DestReg)
531 .addReg(RegNo: SP::G0)
532 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrc));
533 } else if (SP::IntRegsRegClass.contains(Reg: DestReg) &&
534 SP::ASRRegsRegClass.contains(Reg: SrcReg)) {
535 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: SP::RDASR), DestReg)
536 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: KillSrc));
537 } else
538 llvm_unreachable("Impossible reg-to-reg copy");
539
540 if (numSubRegs == 0 || subRegIdx == nullptr || movOpc == 0)
541 return;
542
543 const TargetRegisterInfo *TRI = &getRegisterInfo();
544 MachineInstr *MovMI = nullptr;
545
546 for (unsigned i = 0; i != numSubRegs; ++i) {
547 Register Dst = TRI->getSubReg(Reg: DestReg, Idx: subRegIdx[i]);
548 Register Src = TRI->getSubReg(Reg: SrcReg, Idx: subRegIdx[i]);
549 assert(Dst && Src && "Bad sub-register");
550
551 MachineInstrBuilder MIB = BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: movOpc), DestReg: Dst);
552 if (ExtraG0)
553 MIB.addReg(RegNo: SP::G0);
554 MIB.addReg(RegNo: Src);
555 MovMI = MIB.getInstr();
556 }
557 // Add implicit super-register defs and kills to the last MovMI.
558 MovMI->addRegisterDefined(Reg: DestReg, RegInfo: TRI);
559 if (KillSrc)
560 MovMI->addRegisterKilled(IncomingReg: SrcReg, RegInfo: TRI);
561}
562
563void SparcInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
564 MachineBasicBlock::iterator I,
565 Register SrcReg, bool isKill, int FI,
566 const TargetRegisterClass *RC,
567 Register VReg,
568 MachineInstr::MIFlag Flags) const {
569 DebugLoc DL;
570 if (I != MBB.end()) DL = I->getDebugLoc();
571
572 MachineFunction *MF = MBB.getParent();
573 const MachineFrameInfo &MFI = MF->getFrameInfo();
574 MachineMemOperand *MMO = MF->getMachineMemOperand(
575 PtrInfo: MachinePointerInfo::getFixedStack(MF&: *MF, FI), F: MachineMemOperand::MOStore,
576 Size: MFI.getObjectSize(ObjectIdx: FI), BaseAlignment: MFI.getObjectAlign(ObjectIdx: FI));
577
578 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
579 if (RC == &SP::I64RegsRegClass)
580 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: SP::STXri)).addFrameIndex(Idx: FI).addImm(Val: 0)
581 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill)).addMemOperand(MMO);
582 else if (RC == &SP::IntRegsRegClass)
583 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: SP::STri)).addFrameIndex(Idx: FI).addImm(Val: 0)
584 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill)).addMemOperand(MMO);
585 else if (RC == &SP::IntPairRegClass)
586 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: SP::STDri)).addFrameIndex(Idx: FI).addImm(Val: 0)
587 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill)).addMemOperand(MMO);
588 else if (RC == &SP::FPRegsRegClass)
589 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: SP::STFri)).addFrameIndex(Idx: FI).addImm(Val: 0)
590 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill)).addMemOperand(MMO);
591 else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
592 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: SP::STDFri)).addFrameIndex(Idx: FI).addImm(Val: 0)
593 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill)).addMemOperand(MMO);
594 else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
595 // Use STQFri irrespective of its legality. If STQ is not legal, it will be
596 // lowered into two STDs in eliminateFrameIndex.
597 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: SP::STQFri)).addFrameIndex(Idx: FI).addImm(Val: 0)
598 .addReg(RegNo: SrcReg, Flags: getKillRegState(B: isKill)).addMemOperand(MMO);
599 else
600 llvm_unreachable("Can't store this register to stack slot");
601}
602
603void SparcInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
604 MachineBasicBlock::iterator I,
605 Register DestReg, int FI,
606 const TargetRegisterClass *RC,
607 Register VReg, unsigned SubReg,
608 MachineInstr::MIFlag Flags) const {
609 DebugLoc DL;
610 if (I != MBB.end()) DL = I->getDebugLoc();
611
612 MachineFunction *MF = MBB.getParent();
613 const MachineFrameInfo &MFI = MF->getFrameInfo();
614 MachineMemOperand *MMO = MF->getMachineMemOperand(
615 PtrInfo: MachinePointerInfo::getFixedStack(MF&: *MF, FI), F: MachineMemOperand::MOLoad,
616 Size: MFI.getObjectSize(ObjectIdx: FI), BaseAlignment: MFI.getObjectAlign(ObjectIdx: FI));
617
618 if (RC == &SP::I64RegsRegClass)
619 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: SP::LDXri), DestReg).addFrameIndex(Idx: FI).addImm(Val: 0)
620 .addMemOperand(MMO);
621 else if (RC == &SP::IntRegsRegClass)
622 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: SP::LDri), DestReg).addFrameIndex(Idx: FI).addImm(Val: 0)
623 .addMemOperand(MMO);
624 else if (RC == &SP::IntPairRegClass)
625 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: SP::LDDri), DestReg).addFrameIndex(Idx: FI).addImm(Val: 0)
626 .addMemOperand(MMO);
627 else if (RC == &SP::FPRegsRegClass)
628 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: SP::LDFri), DestReg).addFrameIndex(Idx: FI).addImm(Val: 0)
629 .addMemOperand(MMO);
630 else if (SP::DFPRegsRegClass.hasSubClassEq(RC))
631 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: SP::LDDFri), DestReg).addFrameIndex(Idx: FI).addImm(Val: 0)
632 .addMemOperand(MMO);
633 else if (SP::QFPRegsRegClass.hasSubClassEq(RC))
634 // Use LDQFri irrespective of its legality. If LDQ is not legal, it will be
635 // lowered into two LDDs in eliminateFrameIndex.
636 BuildMI(BB&: MBB, I, MIMD: DL, MCID: get(Opcode: SP::LDQFri), DestReg).addFrameIndex(Idx: FI).addImm(Val: 0)
637 .addMemOperand(MMO);
638 else
639 llvm_unreachable("Can't load this register from stack slot");
640}
641
642Register SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
643 SparcMachineFunctionInfo *SparcFI = MF->getInfo<SparcMachineFunctionInfo>();
644 Register GlobalBaseReg = SparcFI->getGlobalBaseReg();
645 if (GlobalBaseReg)
646 return GlobalBaseReg;
647
648 // Insert the set of GlobalBaseReg into the first MBB of the function
649 MachineBasicBlock &FirstMBB = MF->front();
650 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
651 MachineRegisterInfo &RegInfo = MF->getRegInfo();
652
653 const TargetRegisterClass *PtrRC =
654 Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
655 GlobalBaseReg = RegInfo.createVirtualRegister(RegClass: PtrRC);
656
657 DebugLoc dl;
658
659 BuildMI(BB&: FirstMBB, I: MBBI, MIMD: dl, MCID: get(Opcode: SP::GETPCX), DestReg: GlobalBaseReg);
660 SparcFI->setGlobalBaseReg(GlobalBaseReg);
661 return GlobalBaseReg;
662}
663
664bool SparcInstrInfo::needsUnimp(const MachineInstr &MI,
665 unsigned &StructSize) const {
666 if (!MI.isCall())
667 return false;
668
669 unsigned StructSizeOpNum = 0;
670 switch (MI.getOpcode()) {
671 default:
672 llvm_unreachable("Unknown call opcode.");
673 case SP::CALL:
674 StructSizeOpNum = 1;
675 break;
676 case SP::CALLrr:
677 case SP::CALLri:
678 StructSizeOpNum = 2;
679 break;
680 case SP::TLS_CALL:
681 return false;
682 case SP::TAIL_CALLri:
683 case SP::TAIL_CALL:
684 return false;
685 }
686
687 const MachineOperand &MO = MI.getOperand(i: StructSizeOpNum);
688 if (!MO.isImm())
689 return false;
690
691 // A zero-sized return value has nothing for the callee to copy, so GCC emits
692 // no unimp for it and returns to the instruction right after the delay slot.
693 // We replicate this behavior here.
694 StructSize = MO.getImm();
695 return StructSize != 0;
696}
697
698unsigned SparcInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
699 unsigned Opcode = MI.getOpcode();
700
701 if (MI.isInlineAsm()) {
702 const MachineFunction *MF = MI.getParent()->getParent();
703 const char *AsmStr = MI.getOperand(i: 0).getSymbolName();
704 return getInlineAsmLength(Str: AsmStr, MAI: MF->getTarget().getMCAsmInfo());
705 }
706
707 if (Opcode == TargetOpcode::BUNDLE)
708 return getInstBundleSize(MI);
709
710 if (MI.getOpcode() == SP::GETPCX) {
711 const TargetMachine &TM = MI.getParent()->getParent()->getTarget();
712 if (TM.isPositionIndependent())
713 return 16;
714 switch (TM.getCodeModel()) {
715 default:
716 llvm_unreachable("Unsupported absolute code model");
717 case CodeModel::Small:
718 return 8;
719 case CodeModel::Medium:
720 return 16;
721 case CodeModel::Large:
722 return 24;
723 }
724 }
725
726 // If the instruction has a delay slot, be conservative and also include
727 // it for sizing purposes. This is done so that the BranchRelaxation pass
728 // will not mistakenly mark out-of-range branches as in-range.
729 if (MI.hasDelaySlot()) {
730 unsigned StructSize = 0;
731 return get(Opcode).getSize() * (2 + needsUnimp(MI, StructSize));
732 }
733 return get(Opcode).getSize();
734}
735
736bool SparcInstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
737 Register &SrcReg2, int64_t &CmpMask,
738 int64_t &CmpValue) const {
739 Register DstReg;
740 switch (MI.getOpcode()) {
741 default:
742 break;
743 case SP::SUBCCri:
744 DstReg = MI.getOperand(i: 0).getReg();
745 SrcReg = MI.getOperand(i: 1).getReg();
746 SrcReg2 = 0;
747 CmpMask = ~0;
748 CmpValue = MI.getOperand(i: 2).getImm();
749 return DstReg == SP::G0 && CmpValue == 0;
750 case SP::SUBCCrr:
751 DstReg = MI.getOperand(i: 0).getReg();
752 SrcReg = MI.getOperand(i: 1).getReg();
753 SrcReg2 = MI.getOperand(i: 2).getReg();
754 CmpMask = ~0;
755 CmpValue = 0;
756 return DstReg == SP::G0 && SrcReg2 == SP::G0;
757 }
758
759 return false;
760}
761
762bool SparcInstrInfo::optimizeCompareInstr(
763 MachineInstr &CmpInstr, Register SrcReg, Register SrcReg2, int64_t CmpMask,
764 int64_t CmpValue, const MachineRegisterInfo *MRI) const {
765
766 // Get the unique definition of SrcReg.
767 MachineInstr *MI = MRI->getUniqueVRegDef(Reg: SrcReg);
768 if (!MI)
769 return false;
770
771 // Only optimize if defining and comparing instruction in same block.
772 if (MI->getParent() != CmpInstr.getParent())
773 return false;
774
775 unsigned NewOpcode;
776 switch (MI->getOpcode()) {
777 case SP::ANDNrr:
778 NewOpcode = SP::ANDNCCrr;
779 break;
780 case SP::ANDNri:
781 NewOpcode = SP::ANDNCCri;
782 break;
783 case SP::ANDrr:
784 NewOpcode = SP::ANDCCrr;
785 break;
786 case SP::ANDri:
787 NewOpcode = SP::ANDCCri;
788 break;
789 case SP::ORrr:
790 NewOpcode = SP::ORCCrr;
791 break;
792 case SP::ORri:
793 NewOpcode = SP::ORCCri;
794 break;
795 case SP::ORNCCrr:
796 NewOpcode = SP::ORNCCrr;
797 break;
798 case SP::ORNri:
799 NewOpcode = SP::ORNCCri;
800 break;
801 case SP::XORrr:
802 NewOpcode = SP::XORCCrr;
803 break;
804 case SP::XNORri:
805 NewOpcode = SP::XNORCCri;
806 break;
807 case SP::XNORrr:
808 NewOpcode = SP::XNORCCrr;
809 break;
810 case SP::ADDrr:
811 NewOpcode = SP::ADDCCrr;
812 break;
813 case SP::ADDri:
814 NewOpcode = SP::ADDCCri;
815 break;
816 case SP::SUBrr:
817 NewOpcode = SP::SUBCCrr;
818 break;
819 case SP::SUBri:
820 NewOpcode = SP::SUBCCri;
821 break;
822 default:
823 return false;
824 }
825
826 bool IsICCModified = false;
827 MachineBasicBlock::iterator I = MI;
828 MachineBasicBlock::iterator C = CmpInstr;
829 MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
830 const TargetRegisterInfo *TRI = &getRegisterInfo();
831
832 // If ICC is used or modified between MI and CmpInstr we cannot optimize.
833 while (++I != C) {
834 if (I->modifiesRegister(Reg: SP::ICC, TRI) || I->readsRegister(Reg: SP::ICC, TRI))
835 return false;
836 }
837
838 while (++I != E) {
839 // Only allow conditionals on equality.
840 if (I->readsRegister(Reg: SP::ICC, TRI)) {
841 bool IsICCBranch = I->getOpcode() == SP::BCOND ||
842 I->getOpcode() == SP::BPICC ||
843 I->getOpcode() == SP::BPXCC;
844 bool IsICCMove =
845 I->getOpcode() == SP::MOVICCrr || I->getOpcode() == SP::MOVICCri ||
846 I->getOpcode() == SP::MOVXCCrr || I->getOpcode() == SP::MOVXCCri;
847 bool IsICCConditional = IsICCBranch || IsICCMove;
848 if (!IsICCConditional ||
849 (I->getOperand(i: IsICCBranch ? 1 : 3).getImm() != SPCC::ICC_E &&
850 I->getOperand(i: IsICCBranch ? 1 : 3).getImm() != SPCC::ICC_NE))
851 return false;
852 } else if (I->modifiesRegister(Reg: SP::ICC, TRI)) {
853 IsICCModified = true;
854 break;
855 }
856 }
857
858 if (!IsICCModified) {
859 MachineBasicBlock *MBB = CmpInstr.getParent();
860 if (any_of(Range: MBB->successors(),
861 P: [](MachineBasicBlock *Succ) { return Succ->isLiveIn(Reg: SP::ICC); }))
862 return false;
863 }
864
865 if (MRI->hasOneNonDBGUse(RegNo: SrcReg))
866 MI->getOperand(i: 0).setReg(SP::G0);
867
868 MI->setDesc(get(Opcode: NewOpcode));
869 MI->addRegisterDefined(Reg: SP::ICC);
870 CmpInstr.eraseFromParent();
871
872 return true;
873}
874
875bool SparcInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
876 switch (MI.getOpcode()) {
877 case TargetOpcode::LOAD_STACK_GUARD: {
878 assert(Subtarget.getTargetTriple().isOSLinux() &&
879 "Only Linux target is expected to contain LOAD_STACK_GUARD");
880 // offsetof(tcbhead_t, stack_guard) from sysdeps/sparc/nptl/tls.h in glibc.
881 const int64_t Offset = Subtarget.is64Bit() ? 0x28 : 0x14;
882 MI.setDesc(get(Opcode: Subtarget.is64Bit() ? SP::LDXri : SP::LDri));
883 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
884 .addReg(RegNo: SP::G7)
885 .addImm(Val: Offset);
886 return true;
887 }
888 case SP::V8BAR: {
889 assert(!Subtarget.isV9() &&
890 "V8BAR should not be emitted on V9 processors!");
891
892 // Emit stbar; ldstub [%sp-1], %g0
893 // The sequence acts as a full barrier on V8 systems.
894 MachineBasicBlock &MBB = *MI.getParent();
895 MachineInstr &InstSTBAR =
896 *BuildMI(BB&: MBB, I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: SP::STBAR));
897 MachineInstr &InstLDSTUB =
898 *BuildMI(BB&: MBB, I&: MI, MIMD: MI.getDebugLoc(), MCID: get(Opcode: SP::LDSTUBri), DestReg: SP::G0)
899 .addReg(RegNo: SP::O6)
900 .addImm(Val: -1);
901 MIBundleBuilder(MBB, InstSTBAR, InstLDSTUB);
902 MBB.erase(I: MI);
903 return true;
904 }
905 }
906 return false;
907}
908