1//===------- X86ExpandPseudo.cpp - Expand pseudo instructions -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains a pass that expands pseudo instructions into target
10// instructions to allow proper scheduling, if-conversion, other late
11// optimizations, or simply the encoding of the instructions.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86.h"
16#include "X86FrameLowering.h"
17#include "X86InstrInfo.h"
18#include "X86MachineFunctionInfo.h"
19#include "X86Subtarget.h"
20#include "llvm/CodeGen/LivePhysRegs.h"
21#include "llvm/CodeGen/MachineDominators.h"
22#include "llvm/CodeGen/MachineFunctionAnalysisManager.h"
23#include "llvm/CodeGen/MachineFunctionPass.h"
24#include "llvm/CodeGen/MachineInstrBuilder.h"
25#include "llvm/CodeGen/MachineLoopInfo.h"
26#include "llvm/CodeGen/MachinePassManager.h"
27#include "llvm/CodeGen/Passes.h" // For IDs of passes that are preserved.
28#include "llvm/CodeGen/RegisterClassInfo.h"
29#include "llvm/IR/Analysis.h"
30#include "llvm/IR/EHPersonalities.h"
31#include "llvm/IR/GlobalValue.h"
32#include "llvm/Target/TargetMachine.h"
33using namespace llvm;
34
35#define DEBUG_TYPE "x86-expand-pseudo"
36#define X86_EXPAND_PSEUDO_NAME "X86 pseudo instruction expansion pass"
37
38namespace {
39class X86ExpandPseudoImpl {
40public:
41 const X86Subtarget *STI = nullptr;
42 const X86InstrInfo *TII = nullptr;
43 const X86RegisterInfo *TRI = nullptr;
44 const X86MachineFunctionInfo *X86FI = nullptr;
45 const X86FrameLowering *X86FL = nullptr;
46
47 bool runOnMachineFunction(MachineFunction &MF);
48
49private:
50 void expandICallBranchFunnel(MachineBasicBlock *MBB,
51 MachineBasicBlock::iterator MBBI);
52 void expandCALL_RVMARKER(MachineBasicBlock &MBB,
53 MachineBasicBlock::iterator MBBI);
54 bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
55 bool expandMBB(MachineBasicBlock &MBB);
56
57 /// This function expands pseudos which affects control flow.
58 /// It is done in separate pass to simplify blocks navigation in main
59 /// pass(calling expandMBB).
60 bool expandPseudosWhichAffectControlFlow(MachineFunction &MF);
61
62 /// Expand X86::VASTART_SAVE_XMM_REGS into set of xmm copying instructions,
63 /// placed into separate block guarded by check for al register(for SystemV
64 /// abi).
65 void expandVastartSaveXmmRegs(
66 MachineBasicBlock *EntryBlk,
67 MachineBasicBlock::iterator VAStartPseudoInstr) const;
68};
69
70class X86ExpandPseudoLegacy : public MachineFunctionPass {
71public:
72 static char ID;
73 X86ExpandPseudoLegacy() : MachineFunctionPass(ID) {}
74
75 void getAnalysisUsage(AnalysisUsage &AU) const override {
76 AU.setPreservesCFG();
77 MachineFunctionPass::getAnalysisUsage(AU);
78 }
79
80 const X86Subtarget *STI = nullptr;
81 const X86InstrInfo *TII = nullptr;
82 const X86RegisterInfo *TRI = nullptr;
83 const X86MachineFunctionInfo *X86FI = nullptr;
84 const X86FrameLowering *X86FL = nullptr;
85
86 bool runOnMachineFunction(MachineFunction &MF) override;
87
88 MachineFunctionProperties getRequiredProperties() const override {
89 return MachineFunctionProperties().setNoVRegs();
90 }
91
92 StringRef getPassName() const override {
93 return "X86 pseudo instruction expansion pass";
94 }
95};
96char X86ExpandPseudoLegacy::ID = 0;
97} // End anonymous namespace.
98
99INITIALIZE_PASS(X86ExpandPseudoLegacy, DEBUG_TYPE, X86_EXPAND_PSEUDO_NAME,
100 false, false)
101
102void X86ExpandPseudoImpl::expandICallBranchFunnel(
103 MachineBasicBlock *MBB, MachineBasicBlock::iterator MBBI) {
104 MachineBasicBlock *JTMBB = MBB;
105 MachineInstr *JTInst = &*MBBI;
106 MachineFunction *MF = MBB->getParent();
107 const BasicBlock *BB = MBB->getBasicBlock();
108 auto InsPt = MachineFunction::iterator(MBB);
109 ++InsPt;
110
111 std::vector<std::pair<MachineBasicBlock *, unsigned>> TargetMBBs;
112 const DebugLoc &DL = JTInst->getDebugLoc();
113 MachineOperand Selector = JTInst->getOperand(i: 0);
114 const GlobalValue *CombinedGlobal = JTInst->getOperand(i: 1).getGlobal();
115
116 auto CmpTarget = [&](unsigned Target) {
117 if (Selector.isReg())
118 MBB->addLiveIn(PhysReg: Selector.getReg());
119 BuildMI(BB&: *MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: X86::LEA64r), DestReg: X86::R11)
120 .addReg(RegNo: X86::RIP)
121 .addImm(Val: 1)
122 .addReg(RegNo: 0)
123 .addGlobalAddress(GV: CombinedGlobal,
124 Offset: JTInst->getOperand(i: 2 + 2 * Target).getImm())
125 .addReg(RegNo: 0);
126 BuildMI(BB&: *MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: X86::CMP64rr))
127 .add(MO: Selector)
128 .addReg(RegNo: X86::R11);
129 };
130
131 auto CreateMBB = [&]() {
132 auto *NewMBB = MF->CreateMachineBasicBlock(BB);
133 MBB->addSuccessor(Succ: NewMBB);
134 if (!MBB->isLiveIn(Reg: X86::EFLAGS))
135 MBB->addLiveIn(PhysReg: X86::EFLAGS);
136 return NewMBB;
137 };
138
139 auto EmitCondJump = [&](unsigned CC, MachineBasicBlock *ThenMBB) {
140 BuildMI(BB&: *MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: X86::JCC_1)).addMBB(MBB: ThenMBB).addImm(Val: CC);
141
142 auto *ElseMBB = CreateMBB();
143 MF->insert(MBBI: InsPt, MBB: ElseMBB);
144 MBB = ElseMBB;
145 MBBI = MBB->end();
146 };
147
148 auto EmitCondJumpTarget = [&](unsigned CC, unsigned Target) {
149 auto *ThenMBB = CreateMBB();
150 TargetMBBs.push_back(x: {ThenMBB, Target});
151 EmitCondJump(CC, ThenMBB);
152 };
153
154 auto EmitTailCall = [&](unsigned Target) {
155 BuildMI(BB&: *MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: X86::TAILJMPd64))
156 .add(MO: JTInst->getOperand(i: 3 + 2 * Target));
157 };
158
159 std::function<void(unsigned, unsigned)> EmitBranchFunnel =
160 [&](unsigned FirstTarget, unsigned NumTargets) {
161 if (NumTargets == 1) {
162 EmitTailCall(FirstTarget);
163 return;
164 }
165
166 if (NumTargets == 2) {
167 CmpTarget(FirstTarget + 1);
168 EmitCondJumpTarget(X86::COND_B, FirstTarget);
169 EmitTailCall(FirstTarget + 1);
170 return;
171 }
172
173 if (NumTargets < 6) {
174 CmpTarget(FirstTarget + 1);
175 EmitCondJumpTarget(X86::COND_B, FirstTarget);
176 EmitCondJumpTarget(X86::COND_E, FirstTarget + 1);
177 EmitBranchFunnel(FirstTarget + 2, NumTargets - 2);
178 return;
179 }
180
181 auto *ThenMBB = CreateMBB();
182 CmpTarget(FirstTarget + (NumTargets / 2));
183 EmitCondJump(X86::COND_B, ThenMBB);
184 EmitCondJumpTarget(X86::COND_E, FirstTarget + (NumTargets / 2));
185 EmitBranchFunnel(FirstTarget + (NumTargets / 2) + 1,
186 NumTargets - (NumTargets / 2) - 1);
187
188 MF->insert(MBBI: InsPt, MBB: ThenMBB);
189 MBB = ThenMBB;
190 MBBI = MBB->end();
191 EmitBranchFunnel(FirstTarget, NumTargets / 2);
192 };
193
194 EmitBranchFunnel(0, (JTInst->getNumOperands() - 2) / 2);
195 for (auto P : TargetMBBs) {
196 MF->insert(MBBI: InsPt, MBB: P.first);
197 BuildMI(BB: P.first, MIMD: DL, MCID: TII->get(Opcode: X86::TAILJMPd64))
198 .add(MO: JTInst->getOperand(i: 3 + 2 * P.second));
199 }
200 JTMBB->erase(I: JTInst);
201}
202
203void X86ExpandPseudoImpl::expandCALL_RVMARKER(
204 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) {
205 // Expand CALL_RVMARKER pseudo to call instruction, followed by the special
206 //"movq %rax, %rdi" marker.
207 MachineInstr &MI = *MBBI;
208
209 MachineInstr *OriginalCall;
210 assert((MI.getOperand(1).isGlobal() || MI.getOperand(1).isReg()) &&
211 "invalid operand for regular call");
212 unsigned Opc = -1;
213 if (MI.getOpcode() == X86::CALL64m_RVMARKER)
214 Opc = X86::CALL64m;
215 else if (MI.getOpcode() == X86::CALL64r_RVMARKER)
216 Opc = X86::CALL64r;
217 else if (MI.getOpcode() == X86::CALL64pcrel32_RVMARKER)
218 Opc = X86::CALL64pcrel32;
219 else
220 llvm_unreachable("unexpected opcode");
221
222 OriginalCall = BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: Opc)).getInstr();
223 bool RAXImplicitDead = false;
224 for (MachineOperand &Op : llvm::drop_begin(RangeOrContainer: MI.operands())) {
225 // RAX may be 'implicit dead', if there are no other users of the return
226 // value. We introduce a new use, so change it to 'implicit def'.
227 if (Op.isReg() && Op.isImplicit() && Op.isDead() &&
228 TRI->regsOverlap(RegA: Op.getReg(), RegB: X86::RAX)) {
229 Op.setIsDead(false);
230 Op.setIsDef(true);
231 RAXImplicitDead = true;
232 }
233 OriginalCall->addOperand(Op);
234 }
235
236 // Emit marker "movq %rax, %rdi". %rdi is not callee-saved, so it cannot be
237 // live across the earlier call. The call to the ObjC runtime function returns
238 // the first argument, so the value of %rax is unchanged after the ObjC
239 // runtime call. On Windows targets, the runtime call follows the regular
240 // x64 calling convention and expects the first argument in %rcx.
241 auto TargetReg = STI->getTargetTriple().isOSWindows() ? X86::RCX : X86::RDI;
242 auto *Marker = BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: X86::MOV64rr))
243 .addReg(RegNo: TargetReg, Flags: RegState::Define)
244 .addReg(RegNo: X86::RAX)
245 .getInstr();
246 if (MI.shouldUpdateAdditionalCallInfo())
247 MBB.getParent()->moveAdditionalCallInfo(Old: &MI, New: Marker);
248
249 // Emit call to ObjC runtime.
250 const uint32_t *RegMask =
251 TRI->getCallPreservedMask(MF: *MBB.getParent(), CallingConv::C);
252 MachineInstr *RtCall =
253 BuildMI(BB&: MBB, I: MBBI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: X86::CALL64pcrel32))
254 .addGlobalAddress(GV: MI.getOperand(i: 0).getGlobal(), Offset: 0, TargetFlags: 0)
255 .addRegMask(Mask: RegMask)
256 .addReg(RegNo: X86::RAX,
257 Flags: RegState::Implicit |
258 (RAXImplicitDead ? (RegState::Dead | RegState::Define)
259 : RegState::Define))
260 .getInstr();
261 MI.eraseFromParent();
262
263 auto &TM = MBB.getParent()->getTarget();
264 // On Darwin platforms, wrap the expanded sequence in a bundle to prevent
265 // later optimizations from breaking up the sequence.
266 if (TM.getTargetTriple().isOSDarwin())
267 finalizeBundle(MBB, FirstMI: OriginalCall->getIterator(),
268 LastMI: std::next(x: RtCall->getIterator()));
269}
270
271/// If \p MBBI is a pseudo instruction, this method expands
272/// it to the corresponding (sequence of) actual instruction(s).
273/// \returns true if \p MBBI has been expanded.
274bool X86ExpandPseudoImpl::expandMI(MachineBasicBlock &MBB,
275 MachineBasicBlock::iterator MBBI) {
276 MachineInstr &MI = *MBBI;
277 unsigned Opcode = MI.getOpcode();
278 const DebugLoc &DL = MBBI->getDebugLoc();
279#define GET_EGPR_IF_ENABLED(OPC) (STI->hasEGPR() ? OPC##_EVEX : OPC)
280 switch (Opcode) {
281 default:
282 return false;
283 case X86::TCRETURNdi:
284 case X86::TCRETURNdicc:
285 case X86::TCRETURNri:
286 case X86::TCRETURN_WIN64ri:
287 case X86::TCRETURN_HIPE32ri:
288 case X86::TCRETURNmi:
289 case X86::TCRETURNdi64:
290 case X86::TCRETURNdi64cc:
291 case X86::TCRETURNri64:
292 case X86::TCRETURNri64_ImpCall:
293 case X86::TCRETURNmi64:
294 case X86::TCRETURN_WINmi64: {
295 bool isMem = Opcode == X86::TCRETURNmi || Opcode == X86::TCRETURNmi64 ||
296 Opcode == X86::TCRETURN_WINmi64;
297 MachineOperand &JumpTarget = MBBI->getOperand(i: 0);
298 MachineOperand &StackAdjust = MBBI->getOperand(i: isMem ? X86::AddrNumOperands
299 : 1);
300 assert(StackAdjust.isImm() && "Expecting immediate value.");
301
302 // Adjust stack pointer.
303 int StackAdj = StackAdjust.getImm();
304 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
305 int64_t Offset = 0;
306 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
307
308 // Incoporate the retaddr area.
309 Offset = StackAdj - MaxTCDelta;
310 assert(Offset >= 0 && "Offset should never be negative");
311
312 if (Opcode == X86::TCRETURNdicc || Opcode == X86::TCRETURNdi64cc) {
313 assert(Offset == 0 && "Conditional tail call cannot adjust the stack.");
314 }
315
316 if (Offset) {
317 // Check for possible merge with preceding ADD instruction.
318 Offset = X86FL->mergeSPAdd(MBB, MBBI, AddOffset: Offset, doMergeWithPrevious: true);
319 X86FL->emitSPUpdate(MBB, MBBI, DL, NumBytes: Offset, /*InEpilogue=*/true);
320 }
321
322 // Use this predicate to set REX prefix for X86_64 targets.
323 bool IsX64 = STI->isTargetWin64() || STI->isTargetUEFI64();
324 // Jump to label or value in register.
325 if (Opcode == X86::TCRETURNdi || Opcode == X86::TCRETURNdicc ||
326 Opcode == X86::TCRETURNdi64 || Opcode == X86::TCRETURNdi64cc) {
327 unsigned Op;
328 switch (Opcode) {
329 case X86::TCRETURNdi:
330 Op = X86::TAILJMPd;
331 break;
332 case X86::TCRETURNdicc:
333 Op = X86::TAILJMPd_CC;
334 break;
335 case X86::TCRETURNdi64cc:
336 assert(!MBB.getParent()->hasWinCFI() &&
337 "Conditional tail calls confuse "
338 "the Win64 unwinder.");
339 Op = X86::TAILJMPd64_CC;
340 break;
341 default:
342 // Note: Win64 uses REX prefixes indirect jumps out of functions, but
343 // not direct ones.
344 Op = X86::TAILJMPd64;
345 break;
346 }
347 MachineInstrBuilder MIB = BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: Op));
348 if (JumpTarget.isGlobal()) {
349 MIB.addGlobalAddress(GV: JumpTarget.getGlobal(), Offset: JumpTarget.getOffset(),
350 TargetFlags: JumpTarget.getTargetFlags());
351 } else {
352 assert(JumpTarget.isSymbol());
353 MIB.addExternalSymbol(FnName: JumpTarget.getSymbolName(),
354 TargetFlags: JumpTarget.getTargetFlags());
355 }
356 if (Op == X86::TAILJMPd_CC || Op == X86::TAILJMPd64_CC) {
357 MIB.addImm(Val: MBBI->getOperand(i: 2).getImm());
358 }
359
360 } else if (Opcode == X86::TCRETURNmi || Opcode == X86::TCRETURNmi64 ||
361 Opcode == X86::TCRETURN_WINmi64) {
362 unsigned Op = (Opcode == X86::TCRETURNmi)
363 ? X86::TAILJMPm
364 : (IsX64 ? X86::TAILJMPm64_REX : X86::TAILJMPm64);
365 MachineInstrBuilder MIB = BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: Op));
366 for (unsigned i = 0; i != X86::AddrNumOperands; ++i)
367 MIB.add(MO: MBBI->getOperand(i));
368 } else if (Opcode == X86::TCRETURNri64 ||
369 Opcode == X86::TCRETURNri64_ImpCall ||
370 Opcode == X86::TCRETURN_WIN64ri) {
371 JumpTarget.setIsKill();
372 BuildMI(BB&: MBB, I: MBBI, MIMD: DL,
373 MCID: TII->get(Opcode: IsX64 ? X86::TAILJMPr64_REX : X86::TAILJMPr64))
374 .add(MO: JumpTarget);
375 } else {
376 assert(!IsX64 && "Win64 and UEFI64 require REX for indirect jumps.");
377 JumpTarget.setIsKill();
378 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: X86::TAILJMPr))
379 .add(MO: JumpTarget);
380 }
381
382 MachineInstr &NewMI = *std::prev(x: MBBI);
383 NewMI.copyImplicitOps(MF&: *MBBI->getParent()->getParent(), MI: *MBBI);
384 NewMI.setCFIType(MF&: *MBB.getParent(), Type: MI.getCFIType());
385
386 // Update the call info.
387 if (MBBI->isCandidateForAdditionalCallInfo())
388 MBB.getParent()->moveAdditionalCallInfo(Old: &*MBBI, New: &NewMI);
389
390 // Delete the pseudo instruction TCRETURN.
391 MBB.erase(I: MBBI);
392
393 return true;
394 }
395 case X86::EH_RETURN:
396 case X86::EH_RETURN64: {
397 MachineOperand &DestAddr = MBBI->getOperand(i: 0);
398 assert(DestAddr.isReg() && "Offset should be in register!");
399 const bool Uses64BitFramePtr = STI->isTarget64BitLP64();
400 Register StackPtr = TRI->getStackRegister();
401 BuildMI(BB&: MBB, I: MBBI, MIMD: DL,
402 MCID: TII->get(Opcode: Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr), DestReg: StackPtr)
403 .addReg(RegNo: DestAddr.getReg());
404 // The EH_RETURN pseudo is really removed during the MC Lowering.
405 return true;
406 }
407 case X86::IRET: {
408 // Adjust stack to erase error code
409 int64_t StackAdj = MBBI->getOperand(i: 0).getImm();
410 X86FL->emitSPUpdate(MBB, MBBI, DL, NumBytes: StackAdj, InEpilogue: true);
411 // Replace pseudo with machine iret
412 unsigned RetOp = STI->is64Bit() ? X86::IRET64 : X86::IRET32;
413 // Use UIRET if UINTR is present (except for building kernel)
414 if (STI->is64Bit() && STI->hasUINTR() &&
415 MBB.getParent()->getTarget().getCodeModel() != CodeModel::Kernel)
416 RetOp = X86::UIRET;
417 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: RetOp));
418 MBB.erase(I: MBBI);
419 return true;
420 }
421 case X86::RET: {
422 // Adjust stack to erase error code
423 int64_t StackAdj = MBBI->getOperand(i: 0).getImm();
424 MachineInstrBuilder MIB;
425 if (StackAdj == 0) {
426 MIB = BuildMI(BB&: MBB, I: MBBI, MIMD: DL,
427 MCID: TII->get(Opcode: STI->is64Bit() ? X86::RET64 : X86::RET32));
428 } else if (isUInt<16>(x: StackAdj)) {
429 MIB = BuildMI(BB&: MBB, I: MBBI, MIMD: DL,
430 MCID: TII->get(Opcode: STI->is64Bit() ? X86::RETI64 : X86::RETI32))
431 .addImm(Val: StackAdj);
432 } else {
433 assert(!STI->is64Bit() &&
434 "shouldn't need to do this for x86_64 targets!");
435 // A ret can only handle immediates as big as 2**16-1. If we need to pop
436 // off bytes before the return address, we must do it manually.
437 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: X86::POP32r)).addReg(RegNo: X86::ECX, Flags: RegState::Define);
438 X86FL->emitSPUpdate(MBB, MBBI, DL, NumBytes: StackAdj, /*InEpilogue=*/true);
439 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: X86::PUSH32r)).addReg(RegNo: X86::ECX);
440 MIB = BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: X86::RET32));
441 }
442 for (unsigned I = 1, E = MBBI->getNumOperands(); I != E; ++I)
443 MIB.add(MO: MBBI->getOperand(i: I));
444 MBB.erase(I: MBBI);
445 return true;
446 }
447 case X86::LCMPXCHG16B_SAVE_RBX: {
448 // Perform the following transformation.
449 // SaveRbx = pseudocmpxchg Addr, <4 opds for the address>, InArg, SaveRbx
450 // =>
451 // RBX = InArg
452 // actualcmpxchg Addr
453 // RBX = SaveRbx
454 const MachineOperand &InArg = MBBI->getOperand(i: 6);
455 Register SaveRbx = MBBI->getOperand(i: 7).getReg();
456
457 // Copy the input argument of the pseudo into the argument of the
458 // actual instruction.
459 // NOTE: We don't copy the kill flag since the input might be the same reg
460 // as one of the other operands of LCMPXCHG16B.
461 TII->copyPhysReg(MBB, MI: MBBI, DL, DestReg: X86::RBX, SrcReg: InArg.getReg(), KillSrc: false);
462 // Create the actual instruction.
463 MachineInstr *NewInstr = BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: X86::LCMPXCHG16B));
464 // Copy the operands related to the address. If we access a frame variable,
465 // we need to replace the RBX base with SaveRbx, as RBX has another value.
466 const MachineOperand &Base = MBBI->getOperand(i: 1);
467 if (Base.getReg() == X86::RBX || Base.getReg() == X86::EBX)
468 NewInstr->addOperand(Op: MachineOperand::CreateReg(
469 Reg: Base.getReg() == X86::RBX
470 ? SaveRbx
471 : Register(TRI->getSubReg(Reg: SaveRbx, Idx: X86::sub_32bit)),
472 /*IsDef=*/isDef: false));
473 else
474 NewInstr->addOperand(Op: Base);
475 for (unsigned Idx = 1 + 1; Idx < 1 + X86::AddrNumOperands; ++Idx)
476 NewInstr->addOperand(Op: MBBI->getOperand(i: Idx));
477 // Finally, restore the value of RBX.
478 TII->copyPhysReg(MBB, MI: MBBI, DL, DestReg: X86::RBX, SrcReg: SaveRbx,
479 /*SrcIsKill*/ KillSrc: true);
480
481 // Delete the pseudo.
482 MBBI->eraseFromParent();
483 return true;
484 }
485 // Loading/storing mask pairs requires two kmov operations. The second one of
486 // these needs a 2 byte displacement relative to the specified address (with
487 // 32 bit spill size). The pairs of 1bit masks up to 16 bit masks all use the
488 // same spill size, they all are stored using MASKPAIR16STORE, loaded using
489 // MASKPAIR16LOAD.
490 //
491 // The displacement value might wrap around in theory, thus the asserts in
492 // both cases.
493 case X86::MASKPAIR16LOAD: {
494 int64_t Disp = MBBI->getOperand(i: 1 + X86::AddrDisp).getImm();
495 assert(Disp >= 0 && Disp <= INT32_MAX - 2 && "Unexpected displacement");
496 Register Reg = MBBI->getOperand(i: 0).getReg();
497 bool DstIsDead = MBBI->getOperand(i: 0).isDead();
498 Register Reg0 = TRI->getSubReg(Reg, Idx: X86::sub_mask_0);
499 Register Reg1 = TRI->getSubReg(Reg, Idx: X86::sub_mask_1);
500
501 auto MIBLo =
502 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(GET_EGPR_IF_ENABLED(X86::KMOVWkm)))
503 .addReg(RegNo: Reg0, Flags: RegState::Define | getDeadRegState(B: DstIsDead));
504 auto MIBHi =
505 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(GET_EGPR_IF_ENABLED(X86::KMOVWkm)))
506 .addReg(RegNo: Reg1, Flags: RegState::Define | getDeadRegState(B: DstIsDead));
507
508 for (int i = 0; i < X86::AddrNumOperands; ++i) {
509 MIBLo.add(MO: MBBI->getOperand(i: 1 + i));
510 if (i == X86::AddrDisp)
511 MIBHi.addImm(Val: Disp + 2);
512 else
513 MIBHi.add(MO: MBBI->getOperand(i: 1 + i));
514 }
515
516 // Split the memory operand, adjusting the offset and size for the halves.
517 MachineMemOperand *OldMMO = MBBI->memoperands().front();
518 MachineFunction *MF = MBB.getParent();
519 MachineMemOperand *MMOLo = MF->getMachineMemOperand(MMO: OldMMO, Offset: 0, Size: 2);
520 MachineMemOperand *MMOHi = MF->getMachineMemOperand(MMO: OldMMO, Offset: 2, Size: 2);
521
522 MIBLo.setMemRefs(MMOLo);
523 MIBHi.setMemRefs(MMOHi);
524
525 // Delete the pseudo.
526 MBB.erase(I: MBBI);
527 return true;
528 }
529 case X86::MASKPAIR16STORE: {
530 int64_t Disp = MBBI->getOperand(i: X86::AddrDisp).getImm();
531 assert(Disp >= 0 && Disp <= INT32_MAX - 2 && "Unexpected displacement");
532 Register Reg = MBBI->getOperand(i: X86::AddrNumOperands).getReg();
533 bool SrcIsKill = MBBI->getOperand(i: X86::AddrNumOperands).isKill();
534 Register Reg0 = TRI->getSubReg(Reg, Idx: X86::sub_mask_0);
535 Register Reg1 = TRI->getSubReg(Reg, Idx: X86::sub_mask_1);
536
537 auto MIBLo =
538 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(GET_EGPR_IF_ENABLED(X86::KMOVWmk)));
539 auto MIBHi =
540 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(GET_EGPR_IF_ENABLED(X86::KMOVWmk)));
541
542 for (int i = 0; i < X86::AddrNumOperands; ++i) {
543 MIBLo.add(MO: MBBI->getOperand(i));
544 if (i == X86::AddrDisp)
545 MIBHi.addImm(Val: Disp + 2);
546 else
547 MIBHi.add(MO: MBBI->getOperand(i));
548 }
549 MIBLo.addReg(RegNo: Reg0, Flags: getKillRegState(B: SrcIsKill));
550 MIBHi.addReg(RegNo: Reg1, Flags: getKillRegState(B: SrcIsKill));
551
552 // Split the memory operand, adjusting the offset and size for the halves.
553 MachineMemOperand *OldMMO = MBBI->memoperands().front();
554 MachineFunction *MF = MBB.getParent();
555 MachineMemOperand *MMOLo = MF->getMachineMemOperand(MMO: OldMMO, Offset: 0, Size: 2);
556 MachineMemOperand *MMOHi = MF->getMachineMemOperand(MMO: OldMMO, Offset: 2, Size: 2);
557
558 MIBLo.setMemRefs(MMOLo);
559 MIBHi.setMemRefs(MMOHi);
560
561 // Delete the pseudo.
562 MBB.erase(I: MBBI);
563 return true;
564 }
565 case X86::MWAITX_SAVE_RBX: {
566 // Perform the following transformation.
567 // SaveRbx = pseudomwaitx InArg, SaveRbx
568 // =>
569 // [E|R]BX = InArg
570 // actualmwaitx
571 // [E|R]BX = SaveRbx
572 const MachineOperand &InArg = MBBI->getOperand(i: 1);
573 // Copy the input argument of the pseudo into the argument of the
574 // actual instruction.
575 TII->copyPhysReg(MBB, MI: MBBI, DL, DestReg: X86::EBX, SrcReg: InArg.getReg(), KillSrc: InArg.isKill());
576 // Create the actual instruction.
577 BuildMI(BB&: MBB, I: MBBI, MIMD: DL, MCID: TII->get(Opcode: X86::MWAITXrrr));
578 // Finally, restore the value of RBX.
579 Register SaveRbx = MBBI->getOperand(i: 2).getReg();
580 TII->copyPhysReg(MBB, MI: MBBI, DL, DestReg: X86::RBX, SrcReg: SaveRbx, /*SrcIsKill*/ KillSrc: true);
581 // Delete the pseudo.
582 MBBI->eraseFromParent();
583 return true;
584 }
585 case TargetOpcode::ICALL_BRANCH_FUNNEL:
586 expandICallBranchFunnel(MBB: &MBB, MBBI);
587 return true;
588 case X86::PLDTILECFGV: {
589 MI.setDesc(TII->get(GET_EGPR_IF_ENABLED(X86::LDTILECFG)));
590 return true;
591 }
592 case X86::PTILELOADDV:
593 case X86::PTILELOADDT1V:
594 case X86::PTILELOADDRSV:
595 case X86::PTILELOADDRST1V:
596 case X86::PTCVTROWD2PSrteV:
597 case X86::PTCVTROWD2PSrtiV:
598 case X86::PTCVTROWPS2BF16HrteV:
599 case X86::PTCVTROWPS2BF16HrtiV:
600 case X86::PTCVTROWPS2BF16LrteV:
601 case X86::PTCVTROWPS2BF16LrtiV:
602 case X86::PTCVTROWPS2PHHrteV:
603 case X86::PTCVTROWPS2PHHrtiV:
604 case X86::PTCVTROWPS2PHLrteV:
605 case X86::PTCVTROWPS2PHLrtiV:
606 case X86::PTILEMOVROWrteV:
607 case X86::PTILEMOVROWrtiV: {
608 for (unsigned i = 2; i > 0; --i)
609 MI.removeOperand(OpNo: i);
610 unsigned Opc;
611 switch (Opcode) {
612 case X86::PTILELOADDRSV:
613 Opc = GET_EGPR_IF_ENABLED(X86::TILELOADDRS);
614 break;
615 case X86::PTILELOADDRST1V:
616 Opc = GET_EGPR_IF_ENABLED(X86::TILELOADDRST1);
617 break;
618 case X86::PTILELOADDV:
619 Opc = GET_EGPR_IF_ENABLED(X86::TILELOADD);
620 break;
621 case X86::PTILELOADDT1V:
622 Opc = GET_EGPR_IF_ENABLED(X86::TILELOADDT1);
623 break;
624 case X86::PTCVTROWD2PSrteV:
625 Opc = X86::TCVTROWD2PSrte;
626 break;
627 case X86::PTCVTROWD2PSrtiV:
628 Opc = X86::TCVTROWD2PSrti;
629 break;
630 case X86::PTCVTROWPS2BF16HrteV:
631 Opc = X86::TCVTROWPS2BF16Hrte;
632 break;
633 case X86::PTCVTROWPS2BF16HrtiV:
634 Opc = X86::TCVTROWPS2BF16Hrti;
635 break;
636 case X86::PTCVTROWPS2BF16LrteV:
637 Opc = X86::TCVTROWPS2BF16Lrte;
638 break;
639 case X86::PTCVTROWPS2BF16LrtiV:
640 Opc = X86::TCVTROWPS2BF16Lrti;
641 break;
642 case X86::PTCVTROWPS2PHHrteV:
643 Opc = X86::TCVTROWPS2PHHrte;
644 break;
645 case X86::PTCVTROWPS2PHHrtiV:
646 Opc = X86::TCVTROWPS2PHHrti;
647 break;
648 case X86::PTCVTROWPS2PHLrteV:
649 Opc = X86::TCVTROWPS2PHLrte;
650 break;
651 case X86::PTCVTROWPS2PHLrtiV:
652 Opc = X86::TCVTROWPS2PHLrti;
653 break;
654 case X86::PTILEMOVROWrteV:
655 Opc = X86::TILEMOVROWrte;
656 break;
657 case X86::PTILEMOVROWrtiV:
658 Opc = X86::TILEMOVROWrti;
659 break;
660 default:
661 llvm_unreachable("Unexpected Opcode");
662 }
663 MI.setDesc(TII->get(Opcode: Opc));
664 return true;
665 }
666 case X86::PTCMMIMFP16PSV:
667 case X86::PTCMMRLFP16PSV:
668 case X86::PTDPBSSDV:
669 case X86::PTDPBSUDV:
670 case X86::PTDPBUSDV:
671 case X86::PTDPBUUDV:
672 case X86::PTDPBF16PSV:
673 case X86::PTDPFP16PSV:
674 case X86::PTDPBF8PSV:
675 case X86::PTDPBHF8PSV:
676 case X86::PTDPHBF8PSV:
677 case X86::PTDPHF8PSV: {
678 MI.untieRegOperand(OpIdx: 4);
679 for (unsigned i = 3; i > 0; --i)
680 MI.removeOperand(OpNo: i);
681 unsigned Opc;
682 switch (Opcode) {
683 // clang-format off
684 case X86::PTCMMIMFP16PSV: Opc = X86::TCMMIMFP16PS; break;
685 case X86::PTCMMRLFP16PSV: Opc = X86::TCMMRLFP16PS; break;
686 case X86::PTDPBSSDV: Opc = X86::TDPBSSD; break;
687 case X86::PTDPBSUDV: Opc = X86::TDPBSUD; break;
688 case X86::PTDPBUSDV: Opc = X86::TDPBUSD; break;
689 case X86::PTDPBUUDV: Opc = X86::TDPBUUD; break;
690 case X86::PTDPBF16PSV: Opc = X86::TDPBF16PS; break;
691 case X86::PTDPFP16PSV: Opc = X86::TDPFP16PS; break;
692 case X86::PTDPBF8PSV: Opc = X86::TDPBF8PS; break;
693 case X86::PTDPBHF8PSV: Opc = X86::TDPBHF8PS; break;
694 case X86::PTDPHBF8PSV: Opc = X86::TDPHBF8PS; break;
695 case X86::PTDPHF8PSV: Opc = X86::TDPHF8PS; break;
696 // clang-format on
697 default:
698 llvm_unreachable("Unexpected Opcode");
699 }
700 MI.setDesc(TII->get(Opcode: Opc));
701 MI.tieOperands(DefIdx: 0, UseIdx: 1);
702 return true;
703 }
704 case X86::PTILESTOREDV: {
705 for (int i = 1; i >= 0; --i)
706 MI.removeOperand(OpNo: i);
707 MI.setDesc(TII->get(GET_EGPR_IF_ENABLED(X86::TILESTORED)));
708 return true;
709 }
710#undef GET_EGPR_IF_ENABLED
711 case X86::PTILEZEROV: {
712 for (int i = 2; i > 0; --i) // Remove row, col
713 MI.removeOperand(OpNo: i);
714 MI.setDesc(TII->get(Opcode: X86::TILEZERO));
715 return true;
716 }
717 case X86::CALL64pcrel32_RVMARKER:
718 case X86::CALL64r_RVMARKER:
719 case X86::CALL64m_RVMARKER:
720 expandCALL_RVMARKER(MBB, MBBI);
721 return true;
722 case X86::CALL64r_ImpCall:
723 MI.setDesc(TII->get(Opcode: X86::CALL64r));
724 return true;
725 case X86::ADD32mi_ND:
726 case X86::ADD64mi32_ND:
727 case X86::SUB32mi_ND:
728 case X86::SUB64mi32_ND:
729 case X86::AND32mi_ND:
730 case X86::AND64mi32_ND:
731 case X86::OR32mi_ND:
732 case X86::OR64mi32_ND:
733 case X86::XOR32mi_ND:
734 case X86::XOR64mi32_ND:
735 case X86::ADC32mi_ND:
736 case X86::ADC64mi32_ND:
737 case X86::SBB32mi_ND:
738 case X86::SBB64mi32_ND: {
739 // It's possible for an EVEX-encoded legacy instruction to reach the 15-byte
740 // instruction length limit: 4 bytes of EVEX prefix + 1 byte of opcode + 1
741 // byte of ModRM + 1 byte of SIB + 4 bytes of displacement + 4 bytes of
742 // immediate = 15 bytes in total, e.g.
743 //
744 // subq $184, %fs:257(%rbx, %rcx), %rax
745 //
746 // In such a case, no additional (ADSIZE or segment override) prefix can be
747 // used. To resolve the issue, we split the “long” instruction into 2
748 // instructions:
749 //
750 // movq %fs:257(%rbx, %rcx)，%rax
751 // subq $184, %rax
752 //
753 // Therefore we consider the OPmi_ND to be a pseudo instruction to some
754 // extent.
755 const MachineOperand &ImmOp =
756 MI.getOperand(i: MI.getNumExplicitOperands() - 1);
757 // If the immediate is a expr, conservatively estimate 4 bytes.
758 if (ImmOp.isImm() && isInt<8>(x: ImmOp.getImm()))
759 return false;
760 int MemOpNo = X86::getFirstAddrOperandIdx(MI);
761 const MachineOperand &DispOp = MI.getOperand(i: MemOpNo + X86::AddrDisp);
762 Register Base = MI.getOperand(i: MemOpNo + X86::AddrBaseReg).getReg();
763 // If the displacement is a expr, conservatively estimate 4 bytes.
764 if (Base && DispOp.isImm() && isInt<8>(x: DispOp.getImm()))
765 return false;
766 // There can only be one of three: SIB, segment override register, ADSIZE
767 Register Index = MI.getOperand(i: MemOpNo + X86::AddrIndexReg).getReg();
768 unsigned Count = !!MI.getOperand(i: MemOpNo + X86::AddrSegmentReg).getReg();
769 if (X86II::needSIB(BaseReg: Base, IndexReg: Index, /*In64BitMode=*/true))
770 ++Count;
771 if (getX86MCRegisterClass(RC: X86::GR32RegClassID).contains(Reg: Base) ||
772 getX86MCRegisterClass(RC: X86::GR32RegClassID).contains(Reg: Index))
773 ++Count;
774 if (Count < 2)
775 return false;
776 unsigned Opc, LoadOpc;
777 switch (Opcode) {
778#define MI_TO_RI(OP) \
779 case X86::OP##32mi_ND: \
780 Opc = X86::OP##32ri; \
781 LoadOpc = X86::MOV32rm; \
782 break; \
783 case X86::OP##64mi32_ND: \
784 Opc = X86::OP##64ri32; \
785 LoadOpc = X86::MOV64rm; \
786 break;
787
788 default:
789 llvm_unreachable("Unexpected Opcode");
790 MI_TO_RI(ADD);
791 MI_TO_RI(SUB);
792 MI_TO_RI(AND);
793 MI_TO_RI(OR);
794 MI_TO_RI(XOR);
795 MI_TO_RI(ADC);
796 MI_TO_RI(SBB);
797#undef MI_TO_RI
798 }
799 // Insert OPri.
800 Register DestReg = MI.getOperand(i: 0).getReg();
801 BuildMI(BB&: MBB, I: std::next(x: MBBI), MIMD: DL, MCID: TII->get(Opcode: Opc), DestReg)
802 .addReg(RegNo: DestReg)
803 .add(MO: ImmOp);
804 // Change OPmi_ND to MOVrm.
805 for (unsigned I = MI.getNumImplicitOperands() + 1; I != 0; --I)
806 MI.removeOperand(OpNo: MI.getNumOperands() - 1);
807 MI.setDesc(TII->get(Opcode: LoadOpc));
808 return true;
809 }
810 }
811 llvm_unreachable("Previous switch has a fallthrough?");
812}
813
814// This function creates additional block for storing varargs guarded
815// registers. It adds check for %al into entry block, to skip
816// GuardedRegsBlk if xmm registers should not be stored.
817//
818// EntryBlk[VAStartPseudoInstr] EntryBlk
819// | | .
820// | | .
821// | | GuardedRegsBlk
822// | => | .
823// | | .
824// | TailBlk
825// | |
826// | |
827//
828void X86ExpandPseudoImpl::expandVastartSaveXmmRegs(
829 MachineBasicBlock *EntryBlk,
830 MachineBasicBlock::iterator VAStartPseudoInstr) const {
831 assert(VAStartPseudoInstr->getOpcode() == X86::VASTART_SAVE_XMM_REGS);
832
833 MachineFunction *Func = EntryBlk->getParent();
834 const TargetInstrInfo *TII = STI->getInstrInfo();
835 const DebugLoc &DL = VAStartPseudoInstr->getDebugLoc();
836 Register CountReg = VAStartPseudoInstr->getOperand(i: 0).getReg();
837
838 // Calculate liveins for newly created blocks.
839 LivePhysRegs LiveRegs(*STI->getRegisterInfo());
840 SmallVector<std::pair<MCPhysReg, const MachineOperand *>, 8> Clobbers;
841
842 LiveRegs.addLiveIns(MBB: *EntryBlk);
843 for (MachineInstr &MI : EntryBlk->instrs()) {
844 if (MI.getOpcode() == VAStartPseudoInstr->getOpcode())
845 break;
846
847 LiveRegs.stepForward(MI, Clobbers);
848 }
849
850 // Create the new basic blocks. One block contains all the XMM stores,
851 // and another block is the final destination regardless of whether any
852 // stores were performed.
853 const BasicBlock *LLVMBlk = EntryBlk->getBasicBlock();
854 MachineFunction::iterator EntryBlkIter = ++EntryBlk->getIterator();
855 MachineBasicBlock *GuardedRegsBlk = Func->CreateMachineBasicBlock(BB: LLVMBlk);
856 MachineBasicBlock *TailBlk = Func->CreateMachineBasicBlock(BB: LLVMBlk);
857 Func->insert(MBBI: EntryBlkIter, MBB: GuardedRegsBlk);
858 Func->insert(MBBI: EntryBlkIter, MBB: TailBlk);
859
860 // Transfer the remainder of EntryBlk and its successor edges to TailBlk.
861 TailBlk->splice(Where: TailBlk->begin(), Other: EntryBlk,
862 From: std::next(x: MachineBasicBlock::iterator(VAStartPseudoInstr)),
863 To: EntryBlk->end());
864 TailBlk->transferSuccessorsAndUpdatePHIs(FromMBB: EntryBlk);
865
866 uint64_t FrameOffset = VAStartPseudoInstr->getOperand(i: 4).getImm();
867 uint64_t VarArgsRegsOffset = VAStartPseudoInstr->getOperand(i: 6).getImm();
868
869 // TODO: add support for YMM and ZMM here.
870 unsigned MOVOpc = STI->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
871
872 // In the XMM save block, save all the XMM argument registers.
873 for (int64_t OpndIdx = 7, RegIdx = 0;
874 OpndIdx < VAStartPseudoInstr->getNumOperands() - 1;
875 OpndIdx++, RegIdx++) {
876 auto NewMI = BuildMI(BB: GuardedRegsBlk, MIMD: DL, MCID: TII->get(Opcode: MOVOpc));
877 for (int i = 0; i < X86::AddrNumOperands; ++i) {
878 if (i == X86::AddrDisp)
879 NewMI.addImm(Val: FrameOffset + VarArgsRegsOffset + RegIdx * 16);
880 else
881 NewMI.add(MO: VAStartPseudoInstr->getOperand(i: i + 1));
882 }
883 NewMI.addReg(RegNo: VAStartPseudoInstr->getOperand(i: OpndIdx).getReg());
884 assert(VAStartPseudoInstr->getOperand(OpndIdx).getReg().isPhysical());
885 }
886
887 // The original block will now fall through to the GuardedRegsBlk.
888 EntryBlk->addSuccessor(Succ: GuardedRegsBlk);
889 // The GuardedRegsBlk will fall through to the TailBlk.
890 GuardedRegsBlk->addSuccessor(Succ: TailBlk);
891
892 if (!STI->isCallingConvWin64(CC: Func->getFunction().getCallingConv())) {
893 // If %al is 0, branch around the XMM save block.
894 BuildMI(BB: EntryBlk, MIMD: DL, MCID: TII->get(Opcode: X86::TEST8rr))
895 .addReg(RegNo: CountReg)
896 .addReg(RegNo: CountReg);
897 BuildMI(BB: EntryBlk, MIMD: DL, MCID: TII->get(Opcode: X86::JCC_1))
898 .addMBB(MBB: TailBlk)
899 .addImm(Val: X86::COND_E);
900 EntryBlk->addSuccessor(Succ: TailBlk);
901 }
902
903 // Add liveins to the created block.
904 addLiveIns(MBB&: *GuardedRegsBlk, LiveRegs);
905 addLiveIns(MBB&: *TailBlk, LiveRegs);
906
907 // Delete the pseudo.
908 VAStartPseudoInstr->eraseFromParent();
909}
910
911/// Expand all pseudo instructions contained in \p MBB.
912/// \returns true if any expansion occurred for \p MBB.
913bool X86ExpandPseudoImpl::expandMBB(MachineBasicBlock &MBB) {
914 bool Modified = false;
915
916 // MBBI may be invalidated by the expansion.
917 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
918 while (MBBI != E) {
919 MachineBasicBlock::iterator NMBBI = std::next(x: MBBI);
920 Modified |= expandMI(MBB, MBBI);
921 MBBI = NMBBI;
922 }
923
924 return Modified;
925}
926
927bool X86ExpandPseudoImpl::expandPseudosWhichAffectControlFlow(
928 MachineFunction &MF) {
929 // Currently pseudo which affects control flow is only
930 // X86::VASTART_SAVE_XMM_REGS which is located in Entry block.
931 // So we do not need to evaluate other blocks.
932 for (MachineInstr &Instr : MF.front().instrs()) {
933 if (Instr.getOpcode() == X86::VASTART_SAVE_XMM_REGS) {
934 expandVastartSaveXmmRegs(EntryBlk: &(MF.front()), VAStartPseudoInstr: Instr);
935 return true;
936 }
937 }
938
939 return false;
940}
941
942bool X86ExpandPseudoImpl::runOnMachineFunction(MachineFunction &MF) {
943 STI = &MF.getSubtarget<X86Subtarget>();
944 TII = STI->getInstrInfo();
945 TRI = STI->getRegisterInfo();
946 X86FI = MF.getInfo<X86MachineFunctionInfo>();
947 X86FL = STI->getFrameLowering();
948
949 bool Modified = expandPseudosWhichAffectControlFlow(MF);
950
951 for (MachineBasicBlock &MBB : MF)
952 Modified |= expandMBB(MBB);
953 return Modified;
954}
955
956/// Returns an instance of the pseudo instruction expansion pass.
957FunctionPass *llvm::createX86ExpandPseudoLegacyPass() {
958 return new X86ExpandPseudoLegacy();
959}
960
961bool X86ExpandPseudoLegacy::runOnMachineFunction(MachineFunction &MF) {
962 X86ExpandPseudoImpl Impl;
963 return Impl.runOnMachineFunction(MF);
964}
965
966PreservedAnalyses
967X86ExpandPseudoPass::run(MachineFunction &MF,
968 MachineFunctionAnalysisManager &MFAM) {
969 X86ExpandPseudoImpl Impl;
970 bool Changed = Impl.runOnMachineFunction(MF);
971 if (!Changed)
972 return PreservedAnalyses::all();
973
974 PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses();
975 PA.preserveSet<CFGAnalyses>();
976 return PA;
977}
978