1//===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the X86-specific support for the FastISel class. Much
10// of the target-specific code is generated by tablegen in the file
11// X86GenFastISel.inc, which is #included here.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86.h"
16#include "X86CallingConv.h"
17#include "X86InstrBuilder.h"
18#include "X86InstrInfo.h"
19#include "X86MachineFunctionInfo.h"
20#include "X86RegisterInfo.h"
21#include "X86Subtarget.h"
22#include "X86TargetMachine.h"
23#include "llvm/Analysis/BranchProbabilityInfo.h"
24#include "llvm/CodeGen/FastISel.h"
25#include "llvm/CodeGen/FunctionLoweringInfo.h"
26#include "llvm/CodeGen/MachineConstantPool.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineRegisterInfo.h"
29#include "llvm/IR/CallingConv.h"
30#include "llvm/IR/DebugInfo.h"
31#include "llvm/IR/DerivedTypes.h"
32#include "llvm/IR/GetElementPtrTypeIterator.h"
33#include "llvm/IR/GlobalVariable.h"
34#include "llvm/IR/Instructions.h"
35#include "llvm/IR/IntrinsicInst.h"
36#include "llvm/IR/IntrinsicsX86.h"
37#include "llvm/IR/Module.h"
38#include "llvm/IR/Operator.h"
39#include "llvm/MC/MCAsmInfo.h"
40#include "llvm/MC/MCSymbol.h"
41#include "llvm/Support/ErrorHandling.h"
42#include "llvm/Target/TargetOptions.h"
43using namespace llvm;
44
45namespace {
46
47class X86FastISel final : public FastISel {
48 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
49 /// make the right decision when generating code for different targets.
50 const X86Subtarget *Subtarget;
51
52public:
53 explicit X86FastISel(FunctionLoweringInfo &funcInfo,
54 const TargetLibraryInfo *libInfo,
55 const LibcallLoweringInfo *libcallLowering)
56 : FastISel(funcInfo, libInfo, libcallLowering) {
57 Subtarget = &funcInfo.MF->getSubtarget<X86Subtarget>();
58 }
59
60 bool fastSelectInstruction(const Instruction *I) override;
61
62 /// The specified machine instr operand is a vreg, and that
63 /// vreg is being provided by the specified load instruction. If possible,
64 /// try to fold the load as an operand to the instruction, returning true if
65 /// possible.
66 bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
67 const LoadInst *LI) override;
68
69 bool fastLowerArguments() override;
70 bool fastLowerCall(CallLoweringInfo &CLI) override;
71 bool fastLowerIntrinsicCall(const IntrinsicInst *II) override;
72
73#include "X86GenFastISel.inc"
74
75private:
76 bool X86FastEmitCompare(const Value *LHS, const Value *RHS, EVT VT,
77 const DebugLoc &DL);
78
79 bool X86FastEmitLoad(MVT VT, X86AddressMode &AM, MachineMemOperand *MMO,
80 Register &ResultReg, unsigned Alignment = 1);
81
82 bool X86FastEmitStore(EVT VT, const Value *Val, X86AddressMode &AM,
83 MachineMemOperand *MMO = nullptr, bool Aligned = false);
84 bool X86FastEmitStore(EVT VT, Register ValReg, X86AddressMode &AM,
85 MachineMemOperand *MMO = nullptr, bool Aligned = false);
86
87 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, Register Src, EVT SrcVT,
88 Register &ResultReg);
89
90 bool X86SelectAddress(const Value *V, X86AddressMode &AM);
91 bool X86SelectCallAddress(const Value *V, X86AddressMode &AM);
92
93 bool X86SelectLoad(const Instruction *I);
94
95 bool X86SelectStore(const Instruction *I);
96
97 bool X86SelectRet(const Instruction *I);
98
99 bool X86SelectCmp(const Instruction *I);
100
101 bool X86SelectZExt(const Instruction *I);
102
103 bool X86SelectSExt(const Instruction *I);
104
105 bool X86SelectBranch(const Instruction *I);
106
107 bool X86SelectShift(const Instruction *I);
108
109 bool X86SelectDivRem(const Instruction *I);
110
111 bool X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I);
112
113 bool X86FastEmitSSESelect(MVT RetVT, const Instruction *I);
114
115 bool X86FastEmitPseudoSelect(MVT RetVT, const Instruction *I);
116
117 bool X86SelectSelect(const Instruction *I);
118
119 bool X86SelectTrunc(const Instruction *I);
120
121 bool X86SelectFPExtOrFPTrunc(const Instruction *I, unsigned Opc,
122 const TargetRegisterClass *RC);
123
124 bool X86SelectFPExt(const Instruction *I);
125 bool X86SelectFPTrunc(const Instruction *I);
126 bool X86SelectSIToFP(const Instruction *I);
127 bool X86SelectUIToFP(const Instruction *I);
128 bool X86SelectIntToFP(const Instruction *I, bool IsSigned);
129 bool X86SelectBitCast(const Instruction *I);
130
131 const X86InstrInfo *getInstrInfo() const {
132 return Subtarget->getInstrInfo();
133 }
134 const X86TargetMachine *getTargetMachine() const {
135 return static_cast<const X86TargetMachine *>(&TM);
136 }
137
138 bool handleConstantAddresses(const Value *V, X86AddressMode &AM);
139
140 Register X86MaterializeInt(const ConstantInt *CI, MVT VT);
141 Register X86MaterializeFP(const ConstantFP *CFP, MVT VT);
142 Register X86MaterializeGV(const GlobalValue *GV, MVT VT);
143 Register fastMaterializeConstant(const Constant *C) override;
144
145 Register fastMaterializeAlloca(const AllocaInst *C) override;
146
147 Register fastMaterializeFloatZero(const ConstantFP *CF) override;
148
149 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
150 /// computed in an SSE register, not on the X87 floating point stack.
151 bool isScalarFPTypeInSSEReg(EVT VT) const {
152 return (VT == MVT::f64 && Subtarget->hasSSE2()) ||
153 (VT == MVT::f32 && Subtarget->hasSSE1()) || VT == MVT::f16;
154 }
155
156 bool isTypeLegal(Type *Ty, MVT &VT, bool AllowI1 = false);
157
158 bool IsMemcpySmall(uint64_t Len);
159
160 bool TryEmitSmallMemcpy(X86AddressMode DestAM,
161 X86AddressMode SrcAM, uint64_t Len);
162
163 bool foldX86XALUIntrinsic(X86::CondCode &CC, const Instruction *I,
164 const Value *Cond);
165
166 const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
167 X86AddressMode &AM);
168
169 Register fastEmitInst_rrrr(unsigned MachineInstOpcode,
170 const TargetRegisterClass *RC, Register Op0,
171 Register Op1, Register Op2, Register Op3);
172};
173
174} // end anonymous namespace.
175
176static std::pair<unsigned, bool>
177getX86SSEConditionCode(CmpInst::Predicate Predicate) {
178 unsigned CC;
179 bool NeedSwap = false;
180
181 // SSE Condition code mapping:
182 // 0 - EQ
183 // 1 - LT
184 // 2 - LE
185 // 3 - UNORD
186 // 4 - NEQ
187 // 5 - NLT
188 // 6 - NLE
189 // 7 - ORD
190 switch (Predicate) {
191 default: llvm_unreachable("Unexpected predicate");
192 case CmpInst::FCMP_OEQ: CC = 0; break;
193 case CmpInst::FCMP_OGT: NeedSwap = true; [[fallthrough]];
194 case CmpInst::FCMP_OLT: CC = 1; break;
195 case CmpInst::FCMP_OGE: NeedSwap = true; [[fallthrough]];
196 case CmpInst::FCMP_OLE: CC = 2; break;
197 case CmpInst::FCMP_UNO: CC = 3; break;
198 case CmpInst::FCMP_UNE: CC = 4; break;
199 case CmpInst::FCMP_ULE: NeedSwap = true; [[fallthrough]];
200 case CmpInst::FCMP_UGE: CC = 5; break;
201 case CmpInst::FCMP_ULT: NeedSwap = true; [[fallthrough]];
202 case CmpInst::FCMP_UGT: CC = 6; break;
203 case CmpInst::FCMP_ORD: CC = 7; break;
204 case CmpInst::FCMP_UEQ: CC = 8; break;
205 case CmpInst::FCMP_ONE: CC = 12; break;
206 }
207
208 return std::make_pair(x&: CC, y&: NeedSwap);
209}
210
211/// Adds a complex addressing mode to the given machine instr builder.
212/// Note, this will constrain the index register. If its not possible to
213/// constrain the given index register, then a new one will be created. The
214/// IndexReg field of the addressing mode will be updated to match in this case.
215const MachineInstrBuilder &
216X86FastISel::addFullAddress(const MachineInstrBuilder &MIB,
217 X86AddressMode &AM) {
218 // First constrain the index register. It needs to be a GR64_NOSP.
219 AM.IndexReg = constrainOperandRegClass(II: MIB->getDesc(), Op: AM.IndexReg,
220 OpNum: MIB->getNumOperands() +
221 X86::AddrIndexReg);
222 return ::addFullAddress(MIB, AM);
223}
224
225/// Check if it is possible to fold the condition from the XALU intrinsic
226/// into the user. The condition code will only be updated on success.
227bool X86FastISel::foldX86XALUIntrinsic(X86::CondCode &CC, const Instruction *I,
228 const Value *Cond) {
229 if (!isa<ExtractValueInst>(Val: Cond))
230 return false;
231
232 const auto *EV = cast<ExtractValueInst>(Val: Cond);
233 if (!isa<IntrinsicInst>(Val: EV->getAggregateOperand()))
234 return false;
235
236 const auto *II = cast<IntrinsicInst>(Val: EV->getAggregateOperand());
237 MVT RetVT;
238 const Function *Callee = II->getCalledFunction();
239 Type *RetTy =
240 cast<StructType>(Val: Callee->getReturnType())->getTypeAtIndex(N: 0U);
241 if (!isTypeLegal(Ty: RetTy, VT&: RetVT))
242 return false;
243
244 if (RetVT != MVT::i32 && RetVT != MVT::i64)
245 return false;
246
247 X86::CondCode TmpCC;
248 switch (II->getIntrinsicID()) {
249 default: return false;
250 case Intrinsic::sadd_with_overflow:
251 case Intrinsic::ssub_with_overflow:
252 case Intrinsic::smul_with_overflow:
253 case Intrinsic::umul_with_overflow: TmpCC = X86::COND_O; break;
254 case Intrinsic::uadd_with_overflow:
255 case Intrinsic::usub_with_overflow: TmpCC = X86::COND_B; break;
256 }
257
258 // Check if both instructions are in the same basic block.
259 if (II->getParent() != I->getParent())
260 return false;
261
262 // Make sure nothing is in the way
263 BasicBlock::const_iterator Start(I);
264 BasicBlock::const_iterator End(II);
265 for (auto Itr = std::prev(x: Start); Itr != End; --Itr) {
266 // We only expect extractvalue instructions between the intrinsic and the
267 // instruction to be selected.
268 if (!isa<ExtractValueInst>(Val: Itr))
269 return false;
270
271 // Check that the extractvalue operand comes from the intrinsic.
272 const auto *EVI = cast<ExtractValueInst>(Val&: Itr);
273 if (EVI->getAggregateOperand() != II)
274 return false;
275 }
276
277 // Make sure no potentially eflags clobbering phi moves can be inserted in
278 // between.
279 auto HasPhis = [](const BasicBlock *Succ) { return !Succ->phis().empty(); };
280 if (I->isTerminator() && llvm::any_of(Range: successors(I), P: HasPhis))
281 return false;
282
283 // Make sure there are no potentially eflags clobbering constant
284 // materializations in between.
285 if (llvm::any_of(Range: I->operands(), P: [](Value *V) { return isa<Constant>(Val: V); }))
286 return false;
287
288 CC = TmpCC;
289 return true;
290}
291
292bool X86FastISel::isTypeLegal(Type *Ty, MVT &VT, bool AllowI1) {
293 EVT evt = TLI.getValueType(DL, Ty, /*AllowUnknown=*/true);
294 if (evt == MVT::Other || !evt.isSimple())
295 // Unhandled type. Halt "fast" selection and bail.
296 return false;
297
298 VT = evt.getSimpleVT();
299 // For now, require SSE/SSE2 for performing floating-point operations,
300 // since x87 requires additional work.
301 if (VT == MVT::f64 && !Subtarget->hasSSE2())
302 return false;
303 if (VT == MVT::f32 && !Subtarget->hasSSE1())
304 return false;
305 // Similarly, no f80 support yet.
306 if (VT == MVT::f80)
307 return false;
308 // We only handle legal types. For example, on x86-32 the instruction
309 // selector contains all of the 64-bit instructions from x86-64,
310 // under the assumption that i64 won't be used if the target doesn't
311 // support it.
312 return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT);
313}
314
315/// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
316/// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV.
317/// Return true and the result register by reference if it is possible.
318bool X86FastISel::X86FastEmitLoad(MVT VT, X86AddressMode &AM,
319 MachineMemOperand *MMO, Register &ResultReg,
320 unsigned Alignment) {
321 bool HasSSE1 = Subtarget->hasSSE1();
322 bool HasSSE2 = Subtarget->hasSSE2();
323 bool HasSSE41 = Subtarget->hasSSE41();
324 bool HasAVX = Subtarget->hasAVX();
325 bool HasAVX2 = Subtarget->hasAVX2();
326 bool HasAVX512 = Subtarget->hasAVX512();
327 bool HasVLX = Subtarget->hasVLX();
328 bool IsNonTemporal = MMO && MMO->isNonTemporal();
329
330 // Treat i1 loads the same as i8 loads. Masking will be done when storing.
331 if (VT == MVT::i1)
332 VT = MVT::i8;
333
334 // Get opcode and regclass of the output for the given load instruction.
335 unsigned Opc = 0;
336 switch (VT.SimpleTy) {
337 default: return false;
338 case MVT::i8:
339 Opc = X86::MOV8rm;
340 break;
341 case MVT::i16:
342 Opc = X86::MOV16rm;
343 break;
344 case MVT::i32:
345 Opc = X86::MOV32rm;
346 break;
347 case MVT::i64:
348 // Must be in x86-64 mode.
349 Opc = X86::MOV64rm;
350 break;
351 case MVT::f32:
352 Opc = HasAVX512 ? X86::VMOVSSZrm_alt
353 : HasAVX ? X86::VMOVSSrm_alt
354 : HasSSE1 ? X86::MOVSSrm_alt
355 : X86::LD_Fp32m;
356 break;
357 case MVT::f64:
358 Opc = HasAVX512 ? X86::VMOVSDZrm_alt
359 : HasAVX ? X86::VMOVSDrm_alt
360 : HasSSE2 ? X86::MOVSDrm_alt
361 : X86::LD_Fp64m;
362 break;
363 case MVT::f80:
364 // No f80 support yet.
365 return false;
366 case MVT::v4f32:
367 if (IsNonTemporal && Alignment >= 16 && HasSSE41)
368 Opc = HasVLX ? X86::VMOVNTDQAZ128rm :
369 HasAVX ? X86::VMOVNTDQArm : X86::MOVNTDQArm;
370 else if (Alignment >= 16)
371 Opc = HasVLX ? X86::VMOVAPSZ128rm :
372 HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm;
373 else
374 Opc = HasVLX ? X86::VMOVUPSZ128rm :
375 HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm;
376 break;
377 case MVT::v2f64:
378 if (IsNonTemporal && Alignment >= 16 && HasSSE41)
379 Opc = HasVLX ? X86::VMOVNTDQAZ128rm :
380 HasAVX ? X86::VMOVNTDQArm : X86::MOVNTDQArm;
381 else if (Alignment >= 16)
382 Opc = HasVLX ? X86::VMOVAPDZ128rm :
383 HasAVX ? X86::VMOVAPDrm : X86::MOVAPDrm;
384 else
385 Opc = HasVLX ? X86::VMOVUPDZ128rm :
386 HasAVX ? X86::VMOVUPDrm : X86::MOVUPDrm;
387 break;
388 case MVT::v4i32:
389 case MVT::v2i64:
390 case MVT::v8i16:
391 case MVT::v16i8:
392 if (IsNonTemporal && Alignment >= 16 && HasSSE41)
393 Opc = HasVLX ? X86::VMOVNTDQAZ128rm :
394 HasAVX ? X86::VMOVNTDQArm : X86::MOVNTDQArm;
395 else if (Alignment >= 16)
396 Opc = HasVLX ? X86::VMOVDQA64Z128rm :
397 HasAVX ? X86::VMOVDQArm : X86::MOVDQArm;
398 else
399 Opc = HasVLX ? X86::VMOVDQU64Z128rm :
400 HasAVX ? X86::VMOVDQUrm : X86::MOVDQUrm;
401 break;
402 case MVT::v8f32:
403 assert(HasAVX);
404 if (IsNonTemporal && Alignment >= 32 && HasAVX2)
405 Opc = HasVLX ? X86::VMOVNTDQAZ256rm : X86::VMOVNTDQAYrm;
406 else if (IsNonTemporal && Alignment >= 16)
407 return false; // Force split for X86::VMOVNTDQArm
408 else if (Alignment >= 32)
409 Opc = HasVLX ? X86::VMOVAPSZ256rm : X86::VMOVAPSYrm;
410 else
411 Opc = HasVLX ? X86::VMOVUPSZ256rm : X86::VMOVUPSYrm;
412 break;
413 case MVT::v4f64:
414 assert(HasAVX);
415 if (IsNonTemporal && Alignment >= 32 && HasAVX2)
416 Opc = HasVLX ? X86::VMOVNTDQAZ256rm : X86::VMOVNTDQAYrm;
417 else if (IsNonTemporal && Alignment >= 16)
418 return false; // Force split for X86::VMOVNTDQArm
419 else if (Alignment >= 32)
420 Opc = HasVLX ? X86::VMOVAPDZ256rm : X86::VMOVAPDYrm;
421 else
422 Opc = HasVLX ? X86::VMOVUPDZ256rm : X86::VMOVUPDYrm;
423 break;
424 case MVT::v8i32:
425 case MVT::v4i64:
426 case MVT::v16i16:
427 case MVT::v32i8:
428 assert(HasAVX);
429 if (IsNonTemporal && Alignment >= 32 && HasAVX2)
430 Opc = HasVLX ? X86::VMOVNTDQAZ256rm : X86::VMOVNTDQAYrm;
431 else if (IsNonTemporal && Alignment >= 16)
432 return false; // Force split for X86::VMOVNTDQArm
433 else if (Alignment >= 32)
434 Opc = HasVLX ? X86::VMOVDQA64Z256rm : X86::VMOVDQAYrm;
435 else
436 Opc = HasVLX ? X86::VMOVDQU64Z256rm : X86::VMOVDQUYrm;
437 break;
438 case MVT::v16f32:
439 assert(HasAVX512);
440 if (IsNonTemporal && Alignment >= 64)
441 Opc = X86::VMOVNTDQAZrm;
442 else
443 Opc = (Alignment >= 64) ? X86::VMOVAPSZrm : X86::VMOVUPSZrm;
444 break;
445 case MVT::v8f64:
446 assert(HasAVX512);
447 if (IsNonTemporal && Alignment >= 64)
448 Opc = X86::VMOVNTDQAZrm;
449 else
450 Opc = (Alignment >= 64) ? X86::VMOVAPDZrm : X86::VMOVUPDZrm;
451 break;
452 case MVT::v8i64:
453 case MVT::v16i32:
454 case MVT::v32i16:
455 case MVT::v64i8:
456 assert(HasAVX512);
457 // Note: There are a lot more choices based on type with AVX-512, but
458 // there's really no advantage when the load isn't masked.
459 if (IsNonTemporal && Alignment >= 64)
460 Opc = X86::VMOVNTDQAZrm;
461 else
462 Opc = (Alignment >= 64) ? X86::VMOVDQA64Zrm : X86::VMOVDQU64Zrm;
463 break;
464 }
465
466 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
467
468 ResultReg = createResultReg(RC);
469 MachineInstrBuilder MIB =
470 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc), DestReg: ResultReg);
471 addFullAddress(MIB, AM);
472 if (MMO)
473 MIB->addMemOperand(MF&: *FuncInfo.MF, MO: MMO);
474 return true;
475}
476
477/// X86FastEmitStore - Emit a machine instruction to store a value Val of
478/// type VT. The address is either pre-computed, consisted of a base ptr, Ptr
479/// and a displacement offset, or a GlobalAddress,
480/// i.e. V. Return true if it is possible.
481bool X86FastISel::X86FastEmitStore(EVT VT, Register ValReg, X86AddressMode &AM,
482 MachineMemOperand *MMO, bool Aligned) {
483 bool HasSSE1 = Subtarget->hasSSE1();
484 bool HasSSE2 = Subtarget->hasSSE2();
485 bool HasSSE4A = Subtarget->hasSSE4A();
486 bool HasAVX = Subtarget->hasAVX();
487 bool HasAVX512 = Subtarget->hasAVX512();
488 bool HasVLX = Subtarget->hasVLX();
489 bool IsNonTemporal = MMO && MMO->isNonTemporal();
490
491 // Get opcode and regclass of the output for the given store instruction.
492 unsigned Opc = 0;
493 switch (VT.getSimpleVT().SimpleTy) {
494 case MVT::f80: // No f80 support yet.
495 default: return false;
496 case MVT::i1: {
497 // Mask out all but lowest bit.
498 Register AndResult = createResultReg(RC: &X86::GR8RegClass);
499 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
500 MCID: TII.get(Opcode: X86::AND8ri), DestReg: AndResult)
501 .addReg(RegNo: ValReg).addImm(Val: 1);
502 ValReg = AndResult;
503 [[fallthrough]]; // handle i1 as i8.
504 }
505 case MVT::i8: Opc = X86::MOV8mr; break;
506 case MVT::i16: Opc = X86::MOV16mr; break;
507 case MVT::i32:
508 Opc = (IsNonTemporal && HasSSE2) ? X86::MOVNTImr : X86::MOV32mr;
509 break;
510 case MVT::i64:
511 // Must be in x86-64 mode.
512 Opc = (IsNonTemporal && HasSSE2) ? X86::MOVNTI_64mr : X86::MOV64mr;
513 break;
514 case MVT::f32:
515 if (HasSSE1) {
516 if (IsNonTemporal && HasSSE4A)
517 Opc = X86::MOVNTSS;
518 else
519 Opc = HasAVX512 ? X86::VMOVSSZmr :
520 HasAVX ? X86::VMOVSSmr : X86::MOVSSmr;
521 } else
522 Opc = X86::ST_Fp32m;
523 break;
524 case MVT::f64:
525 if (HasSSE2) {
526 if (IsNonTemporal && HasSSE4A)
527 Opc = X86::MOVNTSD;
528 else
529 Opc = HasAVX512 ? X86::VMOVSDZmr :
530 HasAVX ? X86::VMOVSDmr : X86::MOVSDmr;
531 } else
532 Opc = X86::ST_Fp64m;
533 break;
534 case MVT::x86mmx:
535 Opc = (IsNonTemporal && HasSSE1) ? X86::MMX_MOVNTQmr : X86::MMX_MOVQ64mr;
536 break;
537 case MVT::v4f32:
538 if (Aligned) {
539 if (IsNonTemporal)
540 Opc = HasVLX ? X86::VMOVNTPSZ128mr :
541 HasAVX ? X86::VMOVNTPSmr : X86::MOVNTPSmr;
542 else
543 Opc = HasVLX ? X86::VMOVAPSZ128mr :
544 HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr;
545 } else
546 Opc = HasVLX ? X86::VMOVUPSZ128mr :
547 HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr;
548 break;
549 case MVT::v2f64:
550 if (Aligned) {
551 if (IsNonTemporal)
552 Opc = HasVLX ? X86::VMOVNTPDZ128mr :
553 HasAVX ? X86::VMOVNTPDmr : X86::MOVNTPDmr;
554 else
555 Opc = HasVLX ? X86::VMOVAPDZ128mr :
556 HasAVX ? X86::VMOVAPDmr : X86::MOVAPDmr;
557 } else
558 Opc = HasVLX ? X86::VMOVUPDZ128mr :
559 HasAVX ? X86::VMOVUPDmr : X86::MOVUPDmr;
560 break;
561 case MVT::v4i32:
562 case MVT::v2i64:
563 case MVT::v8i16:
564 case MVT::v16i8:
565 if (Aligned) {
566 if (IsNonTemporal)
567 Opc = HasVLX ? X86::VMOVNTDQZ128mr :
568 HasAVX ? X86::VMOVNTDQmr : X86::MOVNTDQmr;
569 else
570 Opc = HasVLX ? X86::VMOVDQA64Z128mr :
571 HasAVX ? X86::VMOVDQAmr : X86::MOVDQAmr;
572 } else
573 Opc = HasVLX ? X86::VMOVDQU64Z128mr :
574 HasAVX ? X86::VMOVDQUmr : X86::MOVDQUmr;
575 break;
576 case MVT::v8f32:
577 assert(HasAVX);
578 if (Aligned) {
579 if (IsNonTemporal)
580 Opc = HasVLX ? X86::VMOVNTPSZ256mr : X86::VMOVNTPSYmr;
581 else
582 Opc = HasVLX ? X86::VMOVAPSZ256mr : X86::VMOVAPSYmr;
583 } else
584 Opc = HasVLX ? X86::VMOVUPSZ256mr : X86::VMOVUPSYmr;
585 break;
586 case MVT::v4f64:
587 assert(HasAVX);
588 if (Aligned) {
589 if (IsNonTemporal)
590 Opc = HasVLX ? X86::VMOVNTPDZ256mr : X86::VMOVNTPDYmr;
591 else
592 Opc = HasVLX ? X86::VMOVAPDZ256mr : X86::VMOVAPDYmr;
593 } else
594 Opc = HasVLX ? X86::VMOVUPDZ256mr : X86::VMOVUPDYmr;
595 break;
596 case MVT::v8i32:
597 case MVT::v4i64:
598 case MVT::v16i16:
599 case MVT::v32i8:
600 assert(HasAVX);
601 if (Aligned) {
602 if (IsNonTemporal)
603 Opc = HasVLX ? X86::VMOVNTDQZ256mr : X86::VMOVNTDQYmr;
604 else
605 Opc = HasVLX ? X86::VMOVDQA64Z256mr : X86::VMOVDQAYmr;
606 } else
607 Opc = HasVLX ? X86::VMOVDQU64Z256mr : X86::VMOVDQUYmr;
608 break;
609 case MVT::v16f32:
610 assert(HasAVX512);
611 if (Aligned)
612 Opc = IsNonTemporal ? X86::VMOVNTPSZmr : X86::VMOVAPSZmr;
613 else
614 Opc = X86::VMOVUPSZmr;
615 break;
616 case MVT::v8f64:
617 assert(HasAVX512);
618 if (Aligned) {
619 Opc = IsNonTemporal ? X86::VMOVNTPDZmr : X86::VMOVAPDZmr;
620 } else
621 Opc = X86::VMOVUPDZmr;
622 break;
623 case MVT::v8i64:
624 case MVT::v16i32:
625 case MVT::v32i16:
626 case MVT::v64i8:
627 assert(HasAVX512);
628 // Note: There are a lot more choices based on type with AVX-512, but
629 // there's really no advantage when the store isn't masked.
630 if (Aligned)
631 Opc = IsNonTemporal ? X86::VMOVNTDQZmr : X86::VMOVDQA64Zmr;
632 else
633 Opc = X86::VMOVDQU64Zmr;
634 break;
635 }
636
637 const MCInstrDesc &Desc = TII.get(Opcode: Opc);
638 // Some of the instructions in the previous switch use FR128 instead
639 // of FR32 for ValReg. Make sure the register we feed the instruction
640 // matches its register class constraints.
641 // Note: This is fine to do a copy from FR32 to FR128, this is the
642 // same registers behind the scene and actually why it did not trigger
643 // any bugs before.
644 ValReg = constrainOperandRegClass(II: Desc, Op: ValReg, OpNum: Desc.getNumOperands() - 1);
645 MachineInstrBuilder MIB =
646 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: Desc);
647 addFullAddress(MIB, AM).addReg(RegNo: ValReg);
648 if (MMO)
649 MIB->addMemOperand(MF&: *FuncInfo.MF, MO: MMO);
650
651 return true;
652}
653
654bool X86FastISel::X86FastEmitStore(EVT VT, const Value *Val,
655 X86AddressMode &AM,
656 MachineMemOperand *MMO, bool Aligned) {
657 // Handle 'null' like i32/i64 0.
658 if (isa<ConstantPointerNull>(Val))
659 Val = Constant::getNullValue(Ty: DL.getIntPtrType(C&: Val->getContext()));
660
661 // If this is a store of a simple constant, fold the constant into the store.
662 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
663 unsigned Opc = 0;
664 bool Signed = true;
665 switch (VT.getSimpleVT().SimpleTy) {
666 default: break;
667 case MVT::i1:
668 Signed = false;
669 [[fallthrough]]; // Handle as i8.
670 case MVT::i8: Opc = X86::MOV8mi; break;
671 case MVT::i16: Opc = X86::MOV16mi; break;
672 case MVT::i32: Opc = X86::MOV32mi; break;
673 case MVT::i64:
674 // Must be a 32-bit sign extended value.
675 if (isInt<32>(x: CI->getSExtValue()))
676 Opc = X86::MOV64mi32;
677 break;
678 }
679
680 if (Opc) {
681 MachineInstrBuilder MIB =
682 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc));
683 addFullAddress(MIB, AM).addImm(Val: Signed ? (uint64_t) CI->getSExtValue()
684 : CI->getZExtValue());
685 if (MMO)
686 MIB->addMemOperand(MF&: *FuncInfo.MF, MO: MMO);
687 return true;
688 }
689 }
690
691 Register ValReg = getRegForValue(V: Val);
692 if (!ValReg)
693 return false;
694
695 return X86FastEmitStore(VT, ValReg, AM, MMO, Aligned);
696}
697
698/// X86FastEmitExtend - Emit a machine instruction to extend a value Src of
699/// type SrcVT to type DstVT using the specified extension opcode Opc (e.g.
700/// ISD::SIGN_EXTEND).
701bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, Register Src,
702 EVT SrcVT, Register &ResultReg) {
703 Register RR = fastEmit_r(VT: SrcVT.getSimpleVT(), RetVT: DstVT.getSimpleVT(), Opcode: Opc, Op0: Src);
704 if (!RR)
705 return false;
706
707 ResultReg = RR;
708 return true;
709}
710
711bool X86FastISel::handleConstantAddresses(const Value *V, X86AddressMode &AM) {
712 // Handle constant address.
713 if (const GlobalValue *GV = dyn_cast<GlobalValue>(Val: V)) {
714 // Can't handle alternate code models yet.
715 if (TM.getCodeModel() != CodeModel::Small &&
716 TM.getCodeModel() != CodeModel::Medium)
717 return false;
718
719 // Can't handle large objects yet.
720 if (TM.isLargeGlobalValue(GV))
721 return false;
722
723 // Can't handle TLS yet.
724 if (GV->isThreadLocal())
725 return false;
726
727 // Can't handle !absolute_symbol references yet.
728 if (GV->isAbsoluteSymbolRef())
729 return false;
730
731 // RIP-relative addresses can't have additional register operands, so if
732 // we've already folded stuff into the addressing mode, just force the
733 // global value into its own register, which we can use as the basereg.
734 if (!Subtarget->isPICStyleRIPRel() ||
735 (AM.Base.Reg == 0 && AM.IndexReg == 0)) {
736 // Okay, we've committed to selecting this global. Set up the address.
737 AM.GV = GV;
738
739 // Allow the subtarget to classify the global.
740 unsigned char GVFlags = Subtarget->classifyGlobalReference(GV);
741
742 // If this reference is relative to the pic base, set it now.
743 if (isGlobalRelativeToPICBase(TargetFlag: GVFlags)) {
744 // FIXME: How do we know Base.Reg is free??
745 AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(MF: FuncInfo.MF);
746 }
747
748 // Unless the ABI requires an extra load, return a direct reference to
749 // the global.
750 if (!isGlobalStubReference(TargetFlag: GVFlags)) {
751 if (Subtarget->isPICStyleRIPRel()) {
752 // Use rip-relative addressing if we can. Above we verified that the
753 // base and index registers are unused.
754 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
755 AM.Base.Reg = X86::RIP;
756 }
757 AM.GVOpFlags = GVFlags;
758 return true;
759 }
760
761 // Ok, we need to do a load from a stub. If we've already loaded from
762 // this stub, reuse the loaded pointer, otherwise emit the load now.
763 DenseMap<const Value *, Register>::iterator I = LocalValueMap.find(Val: V);
764 Register LoadReg;
765 if (I != LocalValueMap.end() && I->second) {
766 LoadReg = I->second;
767 } else {
768 // Issue load from stub.
769 unsigned Opc = 0;
770 const TargetRegisterClass *RC = nullptr;
771 X86AddressMode StubAM;
772 StubAM.Base.Reg = AM.Base.Reg;
773 StubAM.GV = GV;
774 StubAM.GVOpFlags = GVFlags;
775
776 // Prepare for inserting code in the local-value area.
777 SavePoint SaveInsertPt = enterLocalValueArea();
778
779 if (TLI.getPointerTy(DL) == MVT::i64) {
780 Opc = X86::MOV64rm;
781 RC = &X86::GR64RegClass;
782 } else {
783 Opc = X86::MOV32rm;
784 RC = &X86::GR32RegClass;
785 }
786
787 if (Subtarget->isPICStyleRIPRel() || GVFlags == X86II::MO_GOTPCREL ||
788 GVFlags == X86II::MO_GOTPCREL_NORELAX)
789 StubAM.Base.Reg = X86::RIP;
790
791 LoadReg = createResultReg(RC);
792 MachineInstrBuilder LoadMI =
793 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc), DestReg: LoadReg);
794 addFullAddress(MIB: LoadMI, AM&: StubAM);
795
796 // Ok, back to normal mode.
797 leaveLocalValueArea(Old: SaveInsertPt);
798
799 // Prevent loading GV stub multiple times in same MBB.
800 LocalValueMap[V] = LoadReg;
801 }
802
803 // Now construct the final address. Note that the Disp, Scale,
804 // and Index values may already be set here.
805 AM.Base.Reg = LoadReg;
806 AM.GV = nullptr;
807 return true;
808 }
809 }
810
811 // If all else fails, try to materialize the value in a register.
812 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) {
813 if (AM.Base.Reg == 0) {
814 AM.Base.Reg = getRegForValue(V);
815 return AM.Base.Reg != 0;
816 }
817 if (AM.IndexReg == 0) {
818 assert(AM.Scale == 1 && "Scale with no index!");
819 AM.IndexReg = getRegForValue(V);
820 return AM.IndexReg != 0;
821 }
822 }
823
824 return false;
825}
826
827/// X86SelectAddress - Attempt to fill in an address from the given value.
828///
829bool X86FastISel::X86SelectAddress(const Value *V, X86AddressMode &AM) {
830 SmallVector<const Value *, 32> GEPs;
831redo_gep:
832 const User *U = nullptr;
833 unsigned Opcode = Instruction::UserOp1;
834 if (const Instruction *I = dyn_cast<Instruction>(Val: V)) {
835 // Don't walk into other basic blocks; it's possible we haven't
836 // visited them yet, so the instructions may not yet be assigned
837 // virtual registers.
838 if (FuncInfo.StaticAllocaMap.count(Val: static_cast<const AllocaInst *>(V)) ||
839 FuncInfo.getMBB(BB: I->getParent()) == FuncInfo.MBB) {
840 Opcode = I->getOpcode();
841 U = I;
842 }
843 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Val: V)) {
844 Opcode = C->getOpcode();
845 U = C;
846 }
847
848 if (PointerType *Ty = dyn_cast<PointerType>(Val: V->getType()))
849 if (Ty->getAddressSpace() > 255)
850 // Fast instruction selection doesn't support the special
851 // address spaces.
852 return false;
853
854 switch (Opcode) {
855 default: break;
856 case Instruction::BitCast:
857 // Look past bitcasts.
858 return X86SelectAddress(V: U->getOperand(i: 0), AM);
859
860 case Instruction::IntToPtr:
861 // Look past no-op inttoptrs.
862 if (TLI.getValueType(DL, Ty: U->getOperand(i: 0)->getType()) ==
863 TLI.getPointerTy(DL))
864 return X86SelectAddress(V: U->getOperand(i: 0), AM);
865 break;
866
867 case Instruction::PtrToInt:
868 // Look past no-op ptrtoints.
869 if (TLI.getValueType(DL, Ty: U->getType()) == TLI.getPointerTy(DL))
870 return X86SelectAddress(V: U->getOperand(i: 0), AM);
871 break;
872
873 case Instruction::Alloca: {
874 // Do static allocas.
875 const AllocaInst *A = cast<AllocaInst>(Val: V);
876 DenseMap<const AllocaInst *, int>::iterator SI =
877 FuncInfo.StaticAllocaMap.find(Val: A);
878 if (SI != FuncInfo.StaticAllocaMap.end()) {
879 AM.BaseType = X86AddressMode::FrameIndexBase;
880 AM.Base.FrameIndex = SI->second;
881 return true;
882 }
883 break;
884 }
885
886 case Instruction::Add: {
887 // Adds of constants are common and easy enough.
888 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Val: U->getOperand(i: 1))) {
889 uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue();
890 // They have to fit in the 32-bit signed displacement field though.
891 if (isInt<32>(x: Disp)) {
892 AM.Disp = (uint32_t)Disp;
893 return X86SelectAddress(V: U->getOperand(i: 0), AM);
894 }
895 }
896 break;
897 }
898
899 case Instruction::GetElementPtr: {
900 X86AddressMode SavedAM = AM;
901
902 // Pattern-match simple GEPs.
903 uint64_t Disp = (int32_t)AM.Disp;
904 Register IndexReg = AM.IndexReg;
905 unsigned Scale = AM.Scale;
906 MVT PtrVT = TLI.getValueType(DL, Ty: U->getType()).getSimpleVT();
907
908 gep_type_iterator GTI = gep_type_begin(GEP: U);
909 // Iterate through the indices, folding what we can. Constants can be
910 // folded, and one dynamic index can be handled, if the scale is supported.
911 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
912 i != e; ++i, ++GTI) {
913 const Value *Op = *i;
914 if (StructType *STy = GTI.getStructTypeOrNull()) {
915 const StructLayout *SL = DL.getStructLayout(Ty: STy);
916 Disp += SL->getElementOffset(Idx: cast<ConstantInt>(Val: Op)->getZExtValue());
917 continue;
918 }
919
920 // A array/variable index is always of the form i*S where S is the
921 // constant scale size. See if we can push the scale into immediates.
922 uint64_t S = GTI.getSequentialElementStride(DL);
923 for (;;) {
924 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Val: Op)) {
925 // Constant-offset addressing.
926 Disp += CI->getSExtValue() * S;
927 break;
928 }
929 if (canFoldAddIntoGEP(GEP: U, Add: Op)) {
930 // A compatible add with a constant operand. Fold the constant.
931 ConstantInt *CI =
932 cast<ConstantInt>(Val: cast<AddOperator>(Val: Op)->getOperand(i_nocapture: 1));
933 Disp += CI->getSExtValue() * S;
934 // Iterate on the other operand.
935 Op = cast<AddOperator>(Val: Op)->getOperand(i_nocapture: 0);
936 continue;
937 }
938 if (!IndexReg && (!AM.GV || !Subtarget->isPICStyleRIPRel()) &&
939 (S == 1 || S == 2 || S == 4 || S == 8)) {
940 // Scaled-index addressing.
941 Scale = S;
942 IndexReg = getRegForGEPIndex(PtrVT, Idx: Op);
943 if (!IndexReg)
944 return false;
945 break;
946 }
947 // Unsupported.
948 goto unsupported_gep;
949 }
950 }
951
952 // Check for displacement overflow.
953 if (!isInt<32>(x: Disp))
954 break;
955
956 AM.IndexReg = IndexReg;
957 AM.Scale = Scale;
958 AM.Disp = (uint32_t)Disp;
959 GEPs.push_back(Elt: V);
960
961 if (const GetElementPtrInst *GEP =
962 dyn_cast<GetElementPtrInst>(Val: U->getOperand(i: 0))) {
963 // Ok, the GEP indices were covered by constant-offset and scaled-index
964 // addressing. Update the address state and move on to examining the base.
965 V = GEP;
966 goto redo_gep;
967 } else if (X86SelectAddress(V: U->getOperand(i: 0), AM)) {
968 return true;
969 }
970
971 // If we couldn't merge the gep value into this addr mode, revert back to
972 // our address and just match the value instead of completely failing.
973 AM = SavedAM;
974
975 for (const Value *I : reverse(C&: GEPs))
976 if (handleConstantAddresses(V: I, AM))
977 return true;
978
979 return false;
980 unsupported_gep:
981 // Ok, the GEP indices weren't all covered.
982 break;
983 }
984 }
985
986 return handleConstantAddresses(V, AM);
987}
988
989/// X86SelectCallAddress - Attempt to fill in an address from the given value.
990///
991bool X86FastISel::X86SelectCallAddress(const Value *V, X86AddressMode &AM) {
992 const User *U = nullptr;
993 unsigned Opcode = Instruction::UserOp1;
994 const Instruction *I = dyn_cast<Instruction>(Val: V);
995 // Record if the value is defined in the same basic block.
996 //
997 // This information is crucial to know whether or not folding an
998 // operand is valid.
999 // Indeed, FastISel generates or reuses a virtual register for all
1000 // operands of all instructions it selects. Obviously, the definition and
1001 // its uses must use the same virtual register otherwise the produced
1002 // code is incorrect.
1003 // Before instruction selection, FunctionLoweringInfo::set sets the virtual
1004 // registers for values that are alive across basic blocks. This ensures
1005 // that the values are consistently set between across basic block, even
1006 // if different instruction selection mechanisms are used (e.g., a mix of
1007 // SDISel and FastISel).
1008 // For values local to a basic block, the instruction selection process
1009 // generates these virtual registers with whatever method is appropriate
1010 // for its needs. In particular, FastISel and SDISel do not share the way
1011 // local virtual registers are set.
1012 // Therefore, this is impossible (or at least unsafe) to share values
1013 // between basic blocks unless they use the same instruction selection
1014 // method, which is not guarantee for X86.
1015 // Moreover, things like hasOneUse could not be used accurately, if we
1016 // allow to reference values across basic blocks whereas they are not
1017 // alive across basic blocks initially.
1018 bool InMBB = true;
1019 if (I) {
1020 Opcode = I->getOpcode();
1021 U = I;
1022 InMBB = I->getParent() == FuncInfo.MBB->getBasicBlock();
1023 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Val: V)) {
1024 Opcode = C->getOpcode();
1025 U = C;
1026 }
1027
1028 switch (Opcode) {
1029 default: break;
1030 case Instruction::BitCast:
1031 // Look past bitcasts if its operand is in the same BB.
1032 if (InMBB)
1033 return X86SelectCallAddress(V: U->getOperand(i: 0), AM);
1034 break;
1035
1036 case Instruction::IntToPtr:
1037 // Look past no-op inttoptrs if its operand is in the same BB.
1038 if (InMBB &&
1039 TLI.getValueType(DL, Ty: U->getOperand(i: 0)->getType()) ==
1040 TLI.getPointerTy(DL))
1041 return X86SelectCallAddress(V: U->getOperand(i: 0), AM);
1042 break;
1043
1044 case Instruction::PtrToInt:
1045 // Look past no-op ptrtoints if its operand is in the same BB.
1046 if (InMBB && TLI.getValueType(DL, Ty: U->getType()) == TLI.getPointerTy(DL))
1047 return X86SelectCallAddress(V: U->getOperand(i: 0), AM);
1048 break;
1049 }
1050
1051 // Handle constant address.
1052 if (const GlobalValue *GV = dyn_cast<GlobalValue>(Val: V)) {
1053 // Can't handle alternate code models yet.
1054 if (TM.getCodeModel() != CodeModel::Small &&
1055 TM.getCodeModel() != CodeModel::Medium)
1056 return false;
1057
1058 // RIP-relative addresses can't have additional register operands.
1059 if (Subtarget->isPICStyleRIPRel() &&
1060 (AM.Base.Reg != 0 || AM.IndexReg != 0))
1061 return false;
1062
1063 // Can't handle TLS.
1064 if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(Val: GV))
1065 if (GVar->isThreadLocal())
1066 return false;
1067
1068 // Okay, we've committed to selecting this global. Set up the basic address.
1069 AM.GV = GV;
1070
1071 // Return a direct reference to the global. Fastisel can handle calls to
1072 // functions that require loads, such as dllimport and nonlazybind
1073 // functions.
1074 if (Subtarget->isPICStyleRIPRel()) {
1075 // Use rip-relative addressing if we can. Above we verified that the
1076 // base and index registers are unused.
1077 assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
1078 AM.Base.Reg = X86::RIP;
1079 } else {
1080 AM.GVOpFlags = Subtarget->classifyLocalReference(GV: nullptr);
1081 }
1082
1083 return true;
1084 }
1085
1086 // If all else fails, try to materialize the value in a register.
1087 if (!AM.GV || !Subtarget->isPICStyleRIPRel()) {
1088 auto GetCallRegForValue = [this](const Value *V) {
1089 Register Reg = getRegForValue(V);
1090
1091 // In 64-bit mode, we need a 64-bit register even if pointers are 32 bits.
1092 if (Reg && Subtarget->isTarget64BitILP32()) {
1093 Register CopyReg = createResultReg(RC: &X86::GR32RegClass);
1094 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: X86::MOV32rr),
1095 DestReg: CopyReg)
1096 .addReg(RegNo: Reg);
1097
1098 Register ExtReg = createResultReg(RC: &X86::GR64RegClass);
1099 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1100 MCID: TII.get(Opcode: TargetOpcode::SUBREG_TO_REG), DestReg: ExtReg)
1101 .addImm(Val: 0)
1102 .addReg(RegNo: CopyReg)
1103 .addImm(Val: X86::sub_32bit);
1104 Reg = ExtReg;
1105 }
1106
1107 return Reg;
1108 };
1109
1110 if (AM.Base.Reg == 0) {
1111 AM.Base.Reg = GetCallRegForValue(V);
1112 return AM.Base.Reg != 0;
1113 }
1114 if (AM.IndexReg == 0) {
1115 assert(AM.Scale == 1 && "Scale with no index!");
1116 AM.IndexReg = GetCallRegForValue(V);
1117 return AM.IndexReg != 0;
1118 }
1119 }
1120
1121 return false;
1122}
1123
1124
1125/// X86SelectStore - Select and emit code to implement store instructions.
1126bool X86FastISel::X86SelectStore(const Instruction *I) {
1127 // Atomic stores need special handling.
1128 const StoreInst *S = cast<StoreInst>(Val: I);
1129
1130 if (S->isAtomic())
1131 return false;
1132
1133 const Value *PtrV = I->getOperand(i: 1);
1134 if (TLI.supportSwiftError()) {
1135 // Swifterror values can come from either a function parameter with
1136 // swifterror attribute or an alloca with swifterror attribute.
1137 if (const Argument *Arg = dyn_cast<Argument>(Val: PtrV)) {
1138 if (Arg->hasSwiftErrorAttr())
1139 return false;
1140 }
1141
1142 if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(Val: PtrV)) {
1143 if (Alloca->isSwiftError())
1144 return false;
1145 }
1146 }
1147
1148 const Value *Val = S->getValueOperand();
1149 const Value *Ptr = S->getPointerOperand();
1150
1151 MVT VT;
1152 if (!isTypeLegal(Ty: Val->getType(), VT, /*AllowI1=*/true))
1153 return false;
1154
1155 Align Alignment = S->getAlign();
1156 Align ABIAlignment = DL.getABITypeAlign(Ty: Val->getType());
1157 bool Aligned = Alignment >= ABIAlignment;
1158
1159 X86AddressMode AM;
1160 if (!X86SelectAddress(V: Ptr, AM))
1161 return false;
1162
1163 return X86FastEmitStore(VT, Val, AM, MMO: createMachineMemOperandFor(I), Aligned);
1164}
1165
1166/// X86SelectRet - Select and emit code to implement ret instructions.
1167bool X86FastISel::X86SelectRet(const Instruction *I) {
1168 const ReturnInst *Ret = cast<ReturnInst>(Val: I);
1169 const Function &F = *I->getParent()->getParent();
1170 const X86MachineFunctionInfo *X86MFInfo =
1171 FuncInfo.MF->getInfo<X86MachineFunctionInfo>();
1172
1173 if (!FuncInfo.CanLowerReturn)
1174 return false;
1175
1176 if (TLI.supportSwiftError() &&
1177 F.getAttributes().hasAttrSomewhere(Kind: Attribute::SwiftError))
1178 return false;
1179
1180 if (TLI.supportSplitCSR(MF: FuncInfo.MF))
1181 return false;
1182
1183 CallingConv::ID CC = F.getCallingConv();
1184 if (CC != CallingConv::C &&
1185 CC != CallingConv::Fast &&
1186 CC != CallingConv::Tail &&
1187 CC != CallingConv::SwiftTail &&
1188 CC != CallingConv::X86_FastCall &&
1189 CC != CallingConv::X86_StdCall &&
1190 CC != CallingConv::X86_ThisCall &&
1191 CC != CallingConv::X86_64_SysV &&
1192 CC != CallingConv::Win64)
1193 return false;
1194
1195 // Don't handle popping bytes if they don't fit the ret's immediate.
1196 if (!isUInt<16>(x: X86MFInfo->getBytesToPopOnReturn()))
1197 return false;
1198
1199 // fastcc with -tailcallopt is intended to provide a guaranteed
1200 // tail call optimization. Fastisel doesn't know how to do that.
1201 if ((CC == CallingConv::Fast && TM.Options.GuaranteedTailCallOpt) ||
1202 CC == CallingConv::Tail || CC == CallingConv::SwiftTail)
1203 return false;
1204
1205 // Let SDISel handle vararg functions.
1206 if (F.isVarArg())
1207 return false;
1208
1209 // Build a list of return value registers.
1210 SmallVector<Register, 4> RetRegs;
1211
1212 if (Ret->getNumOperands() > 0) {
1213 SmallVector<ISD::OutputArg, 4> Outs;
1214 GetReturnInfo(CC, ReturnType: F.getReturnType(), attr: F.getAttributes(), Outs, TLI, DL);
1215
1216 // Analyze operands of the call, assigning locations to each operand.
1217 SmallVector<CCValAssign, 16> ValLocs;
1218 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, I->getContext());
1219 CCInfo.AnalyzeReturn(Outs, Fn: RetCC_X86);
1220
1221 const Value *RV = Ret->getOperand(i_nocapture: 0);
1222 Register Reg = getRegForValue(V: RV);
1223 if (!Reg)
1224 return false;
1225
1226 // Only handle a single return value for now.
1227 if (ValLocs.size() != 1)
1228 return false;
1229
1230 CCValAssign &VA = ValLocs[0];
1231
1232 // Don't bother handling odd stuff for now.
1233 if (VA.getLocInfo() != CCValAssign::Full)
1234 return false;
1235 // Only handle register returns for now.
1236 if (!VA.isRegLoc())
1237 return false;
1238
1239 // The calling-convention tables for x87 returns don't tell
1240 // the whole story.
1241 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
1242 return false;
1243
1244 Register SrcReg = Reg + VA.getValNo();
1245 EVT SrcVT = TLI.getValueType(DL, Ty: RV->getType());
1246 EVT DstVT = VA.getValVT();
1247 // Special handling for extended integers.
1248 if (SrcVT != DstVT) {
1249 if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16)
1250 return false;
1251
1252 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
1253 return false;
1254
1255 if (SrcVT == MVT::i1) {
1256 if (Outs[0].Flags.isSExt())
1257 return false;
1258 SrcReg = fastEmitZExtFromI1(VT: MVT::i8, Op0: SrcReg);
1259 SrcVT = MVT::i8;
1260 }
1261 if (SrcVT != DstVT) {
1262 unsigned Op =
1263 Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
1264 SrcReg =
1265 fastEmit_r(VT: SrcVT.getSimpleVT(), RetVT: DstVT.getSimpleVT(), Opcode: Op, Op0: SrcReg);
1266 }
1267 }
1268
1269 // Make the copy.
1270 Register DstReg = VA.getLocReg();
1271 const TargetRegisterClass *SrcRC = MRI.getRegClass(Reg: SrcReg);
1272 // Avoid a cross-class copy. This is very unlikely.
1273 if (!SrcRC->contains(Reg: DstReg))
1274 return false;
1275 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1276 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: DstReg).addReg(RegNo: SrcReg);
1277
1278 // Add register to return instruction.
1279 RetRegs.push_back(Elt: VA.getLocReg());
1280 }
1281
1282 // Swift calling convention does not require we copy the sret argument
1283 // into %rax/%eax for the return, and SRetReturnReg is not set for Swift.
1284
1285 // All x86 ABIs require that for returning structs by value we copy
1286 // the sret argument into %rax/%eax (depending on ABI) for the return.
1287 // We saved the argument into a virtual register in the entry block,
1288 // so now we copy the value out and into %rax/%eax.
1289 if (F.hasStructRetAttr() && CC != CallingConv::Swift &&
1290 CC != CallingConv::SwiftTail) {
1291 Register Reg = X86MFInfo->getSRetReturnReg();
1292 assert(Reg &&
1293 "SRetReturnReg should have been set in LowerFormalArguments()!");
1294 Register RetReg = Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX;
1295 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1296 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: RetReg).addReg(RegNo: Reg);
1297 RetRegs.push_back(Elt: RetReg);
1298 }
1299
1300 // Now emit the RET.
1301 MachineInstrBuilder MIB;
1302 if (X86MFInfo->getBytesToPopOnReturn()) {
1303 MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1304 MCID: TII.get(Opcode: Subtarget->is64Bit() ? X86::RETI64 : X86::RETI32))
1305 .addImm(Val: X86MFInfo->getBytesToPopOnReturn());
1306 } else {
1307 MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1308 MCID: TII.get(Opcode: Subtarget->is64Bit() ? X86::RET64 : X86::RET32));
1309 }
1310 for (Register Reg : RetRegs)
1311 MIB.addReg(RegNo: Reg, Flags: RegState::Implicit);
1312 return true;
1313}
1314
1315/// X86SelectLoad - Select and emit code to implement load instructions.
1316///
1317bool X86FastISel::X86SelectLoad(const Instruction *I) {
1318 const LoadInst *LI = cast<LoadInst>(Val: I);
1319
1320 // Atomic loads need special handling.
1321 if (LI->isAtomic())
1322 return false;
1323
1324 const Value *SV = I->getOperand(i: 0);
1325 if (TLI.supportSwiftError()) {
1326 // Swifterror values can come from either a function parameter with
1327 // swifterror attribute or an alloca with swifterror attribute.
1328 if (const Argument *Arg = dyn_cast<Argument>(Val: SV)) {
1329 if (Arg->hasSwiftErrorAttr())
1330 return false;
1331 }
1332
1333 if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(Val: SV)) {
1334 if (Alloca->isSwiftError())
1335 return false;
1336 }
1337 }
1338
1339 MVT VT;
1340 if (!isTypeLegal(Ty: LI->getType(), VT, /*AllowI1=*/true))
1341 return false;
1342
1343 const Value *Ptr = LI->getPointerOperand();
1344
1345 X86AddressMode AM;
1346 if (!X86SelectAddress(V: Ptr, AM))
1347 return false;
1348
1349 Register ResultReg;
1350 if (!X86FastEmitLoad(VT, AM, MMO: createMachineMemOperandFor(I: LI), ResultReg,
1351 Alignment: LI->getAlign().value()))
1352 return false;
1353
1354 updateValueMap(I, Reg: ResultReg);
1355 return true;
1356}
1357
1358static unsigned X86ChooseCmpOpcode(EVT VT, const X86Subtarget *Subtarget) {
1359 bool HasAVX512 = Subtarget->hasAVX512();
1360 bool HasAVX = Subtarget->hasAVX();
1361 bool HasSSE1 = Subtarget->hasSSE1();
1362 bool HasSSE2 = Subtarget->hasSSE2();
1363
1364 switch (VT.getSimpleVT().SimpleTy) {
1365 default: return 0;
1366 case MVT::i8: return X86::CMP8rr;
1367 case MVT::i16: return X86::CMP16rr;
1368 case MVT::i32: return X86::CMP32rr;
1369 case MVT::i64: return X86::CMP64rr;
1370 case MVT::f32:
1371 return HasAVX512 ? X86::VUCOMISSZrr
1372 : HasAVX ? X86::VUCOMISSrr
1373 : HasSSE1 ? X86::UCOMISSrr
1374 : 0;
1375 case MVT::f64:
1376 return HasAVX512 ? X86::VUCOMISDZrr
1377 : HasAVX ? X86::VUCOMISDrr
1378 : HasSSE2 ? X86::UCOMISDrr
1379 : 0;
1380 }
1381}
1382
1383/// If we have a comparison with RHS as the RHS of the comparison, return an
1384/// opcode that works for the compare (e.g. CMP32ri) otherwise return 0.
1385static unsigned X86ChooseCmpImmediateOpcode(EVT VT, const ConstantInt *RHSC) {
1386 switch (VT.getSimpleVT().SimpleTy) {
1387 // Otherwise, we can't fold the immediate into this comparison.
1388 default:
1389 return 0;
1390 case MVT::i8:
1391 return X86::CMP8ri;
1392 case MVT::i16:
1393 return X86::CMP16ri;
1394 case MVT::i32:
1395 return X86::CMP32ri;
1396 case MVT::i64:
1397 // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext
1398 // field.
1399 return isInt<32>(x: RHSC->getSExtValue()) ? X86::CMP64ri32 : 0;
1400 }
1401}
1402
1403bool X86FastISel::X86FastEmitCompare(const Value *Op0, const Value *Op1, EVT VT,
1404 const DebugLoc &CurMIMD) {
1405 Register Op0Reg = getRegForValue(V: Op0);
1406 if (!Op0Reg)
1407 return false;
1408
1409 // Handle 'null' like i32/i64 0.
1410 if (isa<ConstantPointerNull>(Val: Op1))
1411 Op1 = Constant::getNullValue(Ty: DL.getIntPtrType(C&: Op0->getContext()));
1412
1413 // We have two options: compare with register or immediate. If the RHS of
1414 // the compare is an immediate that we can fold into this compare, use
1415 // CMPri, otherwise use CMPrr.
1416 if (const ConstantInt *Op1C = dyn_cast<ConstantInt>(Val: Op1)) {
1417 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, RHSC: Op1C)) {
1418 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD: CurMIMD, MCID: TII.get(Opcode: CompareImmOpc))
1419 .addReg(RegNo: Op0Reg)
1420 .addImm(Val: Op1C->getSExtValue());
1421 return true;
1422 }
1423 }
1424
1425 unsigned CompareOpc = X86ChooseCmpOpcode(VT, Subtarget);
1426 if (CompareOpc == 0) return false;
1427
1428 Register Op1Reg = getRegForValue(V: Op1);
1429 if (!Op1Reg)
1430 return false;
1431 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD: CurMIMD, MCID: TII.get(Opcode: CompareOpc))
1432 .addReg(RegNo: Op0Reg)
1433 .addReg(RegNo: Op1Reg);
1434
1435 return true;
1436}
1437
1438#define GET_SETCC \
1439 ((!Subtarget->hasZU() || Subtarget->preferLegacySetCC()) ? X86::SETCCr \
1440 : X86::SETZUCCr)
1441
1442bool X86FastISel::X86SelectCmp(const Instruction *I) {
1443 const CmpInst *CI = cast<CmpInst>(Val: I);
1444
1445 MVT VT;
1446 if (!isTypeLegal(Ty: I->getOperand(i: 0)->getType(), VT))
1447 return false;
1448
1449 // Below code only works for scalars.
1450 if (VT.isVector())
1451 return false;
1452
1453 // Try to optimize or fold the cmp.
1454 CmpInst::Predicate Predicate = optimizeCmpPredicate(CI);
1455 Register ResultReg;
1456 switch (Predicate) {
1457 default: break;
1458 case CmpInst::FCMP_FALSE: {
1459 ResultReg = createResultReg(RC: &X86::GR32RegClass);
1460 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: X86::MOV32r0),
1461 DestReg: ResultReg);
1462 ResultReg = fastEmitInst_extractsubreg(RetVT: MVT::i8, Op0: ResultReg, Idx: X86::sub_8bit);
1463 if (!ResultReg)
1464 return false;
1465 break;
1466 }
1467 case CmpInst::FCMP_TRUE: {
1468 ResultReg = createResultReg(RC: &X86::GR8RegClass);
1469 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: X86::MOV8ri),
1470 DestReg: ResultReg).addImm(Val: 1);
1471 break;
1472 }
1473 }
1474
1475 if (ResultReg) {
1476 updateValueMap(I, Reg: ResultReg);
1477 return true;
1478 }
1479
1480 const Value *LHS = CI->getOperand(i_nocapture: 0);
1481 const Value *RHS = CI->getOperand(i_nocapture: 1);
1482
1483 // The optimizer might have replaced fcmp oeq %x, %x with fcmp ord %x, 0.0.
1484 // We don't have to materialize a zero constant for this case and can just use
1485 // %x again on the RHS.
1486 if (Predicate == CmpInst::FCMP_ORD || Predicate == CmpInst::FCMP_UNO) {
1487 const auto *RHSC = dyn_cast<ConstantFP>(Val: RHS);
1488 if (RHSC && RHSC->isNullValue())
1489 RHS = LHS;
1490 }
1491
1492 // FCMP_OEQ and FCMP_UNE cannot be checked with a single instruction.
1493 static const uint16_t SETFOpcTable[2][3] = {
1494 { X86::COND_E, X86::COND_NP, X86::AND8rr },
1495 { X86::COND_NE, X86::COND_P, X86::OR8rr }
1496 };
1497 const uint16_t *SETFOpc = nullptr;
1498 switch (Predicate) {
1499 default: break;
1500 case CmpInst::FCMP_OEQ: SETFOpc = &SETFOpcTable[0][0]; break;
1501 case CmpInst::FCMP_UNE: SETFOpc = &SETFOpcTable[1][0]; break;
1502 }
1503
1504 ResultReg = createResultReg(RC: &X86::GR8RegClass);
1505 if (SETFOpc) {
1506 if (!X86FastEmitCompare(Op0: LHS, Op1: RHS, VT, CurMIMD: I->getDebugLoc()))
1507 return false;
1508
1509 Register FlagReg1 = createResultReg(RC: &X86::GR8RegClass);
1510 Register FlagReg2 = createResultReg(RC: &X86::GR8RegClass);
1511 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(GET_SETCC),
1512 DestReg: FlagReg1)
1513 .addImm(Val: SETFOpc[0]);
1514 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(GET_SETCC),
1515 DestReg: FlagReg2)
1516 .addImm(Val: SETFOpc[1]);
1517 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: SETFOpc[2]),
1518 DestReg: ResultReg).addReg(RegNo: FlagReg1).addReg(RegNo: FlagReg2);
1519 updateValueMap(I, Reg: ResultReg);
1520 return true;
1521 }
1522
1523 X86::CondCode CC;
1524 bool SwapArgs;
1525 std::tie(args&: CC, args&: SwapArgs) = X86::getX86ConditionCode(Predicate);
1526 assert(CC <= X86::LAST_VALID_COND && "Unexpected condition code.");
1527
1528 if (SwapArgs)
1529 std::swap(a&: LHS, b&: RHS);
1530
1531 // Emit a compare of LHS/RHS.
1532 if (!X86FastEmitCompare(Op0: LHS, Op1: RHS, VT, CurMIMD: I->getDebugLoc()))
1533 return false;
1534
1535 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(GET_SETCC), DestReg: ResultReg)
1536 .addImm(Val: CC);
1537 updateValueMap(I, Reg: ResultReg);
1538 return true;
1539}
1540
1541bool X86FastISel::X86SelectZExt(const Instruction *I) {
1542 EVT DstVT = TLI.getValueType(DL, Ty: I->getType());
1543 if (!TLI.isTypeLegal(VT: DstVT))
1544 return false;
1545
1546 Register ResultReg = getRegForValue(V: I->getOperand(i: 0));
1547 if (!ResultReg)
1548 return false;
1549
1550 // Handle zero-extension from i1 to i8, which is common.
1551 MVT SrcVT = TLI.getSimpleValueType(DL, Ty: I->getOperand(i: 0)->getType());
1552 if (SrcVT == MVT::i1) {
1553 // Set the high bits to zero.
1554 ResultReg = fastEmitZExtFromI1(VT: MVT::i8, Op0: ResultReg);
1555 SrcVT = MVT::i8;
1556
1557 if (!ResultReg)
1558 return false;
1559 }
1560
1561 if (DstVT == MVT::i64) {
1562 // Handle extension to 64-bits via sub-register shenanigans.
1563 unsigned MovInst;
1564
1565 switch (SrcVT.SimpleTy) {
1566 case MVT::i8: MovInst = X86::MOVZX32rr8; break;
1567 case MVT::i16: MovInst = X86::MOVZX32rr16; break;
1568 case MVT::i32: MovInst = X86::MOV32rr; break;
1569 default: llvm_unreachable("Unexpected zext to i64 source type");
1570 }
1571
1572 Register Result32 = createResultReg(RC: &X86::GR32RegClass);
1573 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: MovInst), DestReg: Result32)
1574 .addReg(RegNo: ResultReg);
1575
1576 ResultReg = createResultReg(RC: &X86::GR64RegClass);
1577 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: TargetOpcode::SUBREG_TO_REG),
1578 DestReg: ResultReg)
1579 .addImm(Val: 0).addReg(RegNo: Result32).addImm(Val: X86::sub_32bit);
1580 } else if (DstVT == MVT::i16) {
1581 // i8->i16 doesn't exist in the autogenerated isel table. Need to zero
1582 // extend to 32-bits and then extract down to 16-bits.
1583 Register Result32 = createResultReg(RC: &X86::GR32RegClass);
1584 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: X86::MOVZX32rr8),
1585 DestReg: Result32).addReg(RegNo: ResultReg);
1586
1587 ResultReg = fastEmitInst_extractsubreg(RetVT: MVT::i16, Op0: Result32, Idx: X86::sub_16bit);
1588 } else if (DstVT != MVT::i8) {
1589 ResultReg = fastEmit_r(VT: MVT::i8, RetVT: DstVT.getSimpleVT(), Opcode: ISD::ZERO_EXTEND,
1590 Op0: ResultReg);
1591 if (!ResultReg)
1592 return false;
1593 }
1594
1595 updateValueMap(I, Reg: ResultReg);
1596 return true;
1597}
1598
1599bool X86FastISel::X86SelectSExt(const Instruction *I) {
1600 EVT DstVT = TLI.getValueType(DL, Ty: I->getType());
1601 if (!TLI.isTypeLegal(VT: DstVT))
1602 return false;
1603
1604 Register ResultReg = getRegForValue(V: I->getOperand(i: 0));
1605 if (!ResultReg)
1606 return false;
1607
1608 // Handle sign-extension from i1 to i8.
1609 MVT SrcVT = TLI.getSimpleValueType(DL, Ty: I->getOperand(i: 0)->getType());
1610 if (SrcVT == MVT::i1) {
1611 // Set the high bits to zero.
1612 Register ZExtReg = fastEmitZExtFromI1(VT: MVT::i8, Op0: ResultReg);
1613 if (!ZExtReg)
1614 return false;
1615
1616 // Negate the result to make an 8-bit sign extended value.
1617 ResultReg = createResultReg(RC: &X86::GR8RegClass);
1618 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: X86::NEG8r),
1619 DestReg: ResultReg).addReg(RegNo: ZExtReg);
1620
1621 SrcVT = MVT::i8;
1622 }
1623
1624 if (DstVT == MVT::i16) {
1625 // i8->i16 doesn't exist in the autogenerated isel table. Need to sign
1626 // extend to 32-bits and then extract down to 16-bits.
1627 Register Result32 = createResultReg(RC: &X86::GR32RegClass);
1628 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: X86::MOVSX32rr8),
1629 DestReg: Result32).addReg(RegNo: ResultReg);
1630
1631 ResultReg = fastEmitInst_extractsubreg(RetVT: MVT::i16, Op0: Result32, Idx: X86::sub_16bit);
1632 } else if (DstVT != MVT::i8) {
1633 ResultReg = fastEmit_r(VT: MVT::i8, RetVT: DstVT.getSimpleVT(), Opcode: ISD::SIGN_EXTEND,
1634 Op0: ResultReg);
1635 if (!ResultReg)
1636 return false;
1637 }
1638
1639 updateValueMap(I, Reg: ResultReg);
1640 return true;
1641}
1642
1643bool X86FastISel::X86SelectBranch(const Instruction *I) {
1644 // Unconditional branches are selected by tablegen-generated code.
1645 // Handle a conditional branch.
1646 const BranchInst *BI = cast<BranchInst>(Val: I);
1647 MachineBasicBlock *TrueMBB = FuncInfo.getMBB(BB: BI->getSuccessor(i: 0));
1648 MachineBasicBlock *FalseMBB = FuncInfo.getMBB(BB: BI->getSuccessor(i: 1));
1649
1650 // Fold the common case of a conditional branch with a comparison
1651 // in the same block (values defined on other blocks may not have
1652 // initialized registers).
1653 X86::CondCode CC;
1654 if (const CmpInst *CI = dyn_cast<CmpInst>(Val: BI->getCondition())) {
1655 if (CI->hasOneUse() && CI->getParent() == I->getParent()) {
1656 EVT VT = TLI.getValueType(DL, Ty: CI->getOperand(i_nocapture: 0)->getType());
1657
1658 // Try to optimize or fold the cmp.
1659 CmpInst::Predicate Predicate = optimizeCmpPredicate(CI);
1660 switch (Predicate) {
1661 default: break;
1662 case CmpInst::FCMP_FALSE: fastEmitBranch(MSucc: FalseMBB, DbgLoc: MIMD.getDL()); return true;
1663 case CmpInst::FCMP_TRUE: fastEmitBranch(MSucc: TrueMBB, DbgLoc: MIMD.getDL()); return true;
1664 }
1665
1666 const Value *CmpLHS = CI->getOperand(i_nocapture: 0);
1667 const Value *CmpRHS = CI->getOperand(i_nocapture: 1);
1668
1669 // The optimizer might have replaced fcmp oeq %x, %x with fcmp ord %x,
1670 // 0.0.
1671 // We don't have to materialize a zero constant for this case and can just
1672 // use %x again on the RHS.
1673 if (Predicate == CmpInst::FCMP_ORD || Predicate == CmpInst::FCMP_UNO) {
1674 const auto *CmpRHSC = dyn_cast<ConstantFP>(Val: CmpRHS);
1675 if (CmpRHSC && CmpRHSC->isNullValue())
1676 CmpRHS = CmpLHS;
1677 }
1678
1679 // Try to take advantage of fallthrough opportunities.
1680 if (FuncInfo.MBB->isLayoutSuccessor(MBB: TrueMBB)) {
1681 std::swap(a&: TrueMBB, b&: FalseMBB);
1682 Predicate = CmpInst::getInversePredicate(pred: Predicate);
1683 }
1684
1685 // FCMP_OEQ and FCMP_UNE cannot be expressed with a single flag/condition
1686 // code check. Instead two branch instructions are required to check all
1687 // the flags. First we change the predicate to a supported condition code,
1688 // which will be the first branch. Later one we will emit the second
1689 // branch.
1690 bool NeedExtraBranch = false;
1691 switch (Predicate) {
1692 default: break;
1693 case CmpInst::FCMP_OEQ:
1694 std::swap(a&: TrueMBB, b&: FalseMBB);
1695 [[fallthrough]];
1696 case CmpInst::FCMP_UNE:
1697 NeedExtraBranch = true;
1698 Predicate = CmpInst::FCMP_ONE;
1699 break;
1700 }
1701
1702 bool SwapArgs;
1703 std::tie(args&: CC, args&: SwapArgs) = X86::getX86ConditionCode(Predicate);
1704 assert(CC <= X86::LAST_VALID_COND && "Unexpected condition code.");
1705
1706 if (SwapArgs)
1707 std::swap(a&: CmpLHS, b&: CmpRHS);
1708
1709 // Emit a compare of the LHS and RHS, setting the flags.
1710 if (!X86FastEmitCompare(Op0: CmpLHS, Op1: CmpRHS, VT, CurMIMD: CI->getDebugLoc()))
1711 return false;
1712
1713 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: X86::JCC_1))
1714 .addMBB(MBB: TrueMBB).addImm(Val: CC);
1715
1716 // X86 requires a second branch to handle UNE (and OEQ, which is mapped
1717 // to UNE above).
1718 if (NeedExtraBranch) {
1719 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: X86::JCC_1))
1720 .addMBB(MBB: TrueMBB).addImm(Val: X86::COND_P);
1721 }
1722
1723 finishCondBranch(BranchBB: BI->getParent(), TrueMBB, FalseMBB);
1724 return true;
1725 }
1726 } else if (TruncInst *TI = dyn_cast<TruncInst>(Val: BI->getCondition())) {
1727 // Handle things like "%cond = trunc i32 %X to i1 / br i1 %cond", which
1728 // typically happen for _Bool and C++ bools.
1729 MVT SourceVT;
1730 if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1731 isTypeLegal(Ty: TI->getOperand(i_nocapture: 0)->getType(), VT&: SourceVT)) {
1732 unsigned TestOpc = 0;
1733 switch (SourceVT.SimpleTy) {
1734 default: break;
1735 case MVT::i8: TestOpc = X86::TEST8ri; break;
1736 case MVT::i16: TestOpc = X86::TEST16ri; break;
1737 case MVT::i32: TestOpc = X86::TEST32ri; break;
1738 case MVT::i64: TestOpc = X86::TEST64ri32; break;
1739 }
1740 if (TestOpc) {
1741 Register OpReg = getRegForValue(V: TI->getOperand(i_nocapture: 0));
1742 if (!OpReg)
1743 return false;
1744
1745 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: TestOpc))
1746 .addReg(RegNo: OpReg).addImm(Val: 1);
1747
1748 unsigned JmpCond = X86::COND_NE;
1749 if (FuncInfo.MBB->isLayoutSuccessor(MBB: TrueMBB)) {
1750 std::swap(a&: TrueMBB, b&: FalseMBB);
1751 JmpCond = X86::COND_E;
1752 }
1753
1754 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: X86::JCC_1))
1755 .addMBB(MBB: TrueMBB).addImm(Val: JmpCond);
1756
1757 finishCondBranch(BranchBB: BI->getParent(), TrueMBB, FalseMBB);
1758 return true;
1759 }
1760 }
1761 } else if (foldX86XALUIntrinsic(CC, I: BI, Cond: BI->getCondition())) {
1762 // Fake request the condition, otherwise the intrinsic might be completely
1763 // optimized away.
1764 Register TmpReg = getRegForValue(V: BI->getCondition());
1765 if (!TmpReg)
1766 return false;
1767
1768 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: X86::JCC_1))
1769 .addMBB(MBB: TrueMBB).addImm(Val: CC);
1770 finishCondBranch(BranchBB: BI->getParent(), TrueMBB, FalseMBB);
1771 return true;
1772 }
1773
1774 // Otherwise do a clumsy setcc and re-test it.
1775 // Note that i1 essentially gets ANY_EXTEND'ed to i8 where it isn't used
1776 // in an explicit cast, so make sure to handle that correctly.
1777 Register OpReg = getRegForValue(V: BI->getCondition());
1778 if (!OpReg)
1779 return false;
1780
1781 // In case OpReg is a K register, COPY to a GPR
1782 if (MRI.getRegClass(Reg: OpReg) == &X86::VK1RegClass) {
1783 Register KOpReg = OpReg;
1784 OpReg = createResultReg(RC: &X86::GR32RegClass);
1785 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1786 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: OpReg)
1787 .addReg(RegNo: KOpReg);
1788 OpReg = fastEmitInst_extractsubreg(RetVT: MVT::i8, Op0: OpReg, Idx: X86::sub_8bit);
1789 }
1790 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: X86::TEST8ri))
1791 .addReg(RegNo: OpReg)
1792 .addImm(Val: 1);
1793 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: X86::JCC_1))
1794 .addMBB(MBB: TrueMBB).addImm(Val: X86::COND_NE);
1795 finishCondBranch(BranchBB: BI->getParent(), TrueMBB, FalseMBB);
1796 return true;
1797}
1798
1799bool X86FastISel::X86SelectShift(const Instruction *I) {
1800 Register CReg;
1801 unsigned OpReg;
1802 const TargetRegisterClass *RC = nullptr;
1803 if (I->getType()->isIntegerTy(Bitwidth: 8)) {
1804 CReg = X86::CL;
1805 RC = &X86::GR8RegClass;
1806 switch (I->getOpcode()) {
1807 case Instruction::LShr: OpReg = X86::SHR8rCL; break;
1808 case Instruction::AShr: OpReg = X86::SAR8rCL; break;
1809 case Instruction::Shl: OpReg = X86::SHL8rCL; break;
1810 default: return false;
1811 }
1812 } else if (I->getType()->isIntegerTy(Bitwidth: 16)) {
1813 CReg = X86::CX;
1814 RC = &X86::GR16RegClass;
1815 switch (I->getOpcode()) {
1816 default: llvm_unreachable("Unexpected shift opcode");
1817 case Instruction::LShr: OpReg = X86::SHR16rCL; break;
1818 case Instruction::AShr: OpReg = X86::SAR16rCL; break;
1819 case Instruction::Shl: OpReg = X86::SHL16rCL; break;
1820 }
1821 } else if (I->getType()->isIntegerTy(Bitwidth: 32)) {
1822 CReg = X86::ECX;
1823 RC = &X86::GR32RegClass;
1824 switch (I->getOpcode()) {
1825 default: llvm_unreachable("Unexpected shift opcode");
1826 case Instruction::LShr: OpReg = X86::SHR32rCL; break;
1827 case Instruction::AShr: OpReg = X86::SAR32rCL; break;
1828 case Instruction::Shl: OpReg = X86::SHL32rCL; break;
1829 }
1830 } else if (I->getType()->isIntegerTy(Bitwidth: 64)) {
1831 CReg = X86::RCX;
1832 RC = &X86::GR64RegClass;
1833 switch (I->getOpcode()) {
1834 default: llvm_unreachable("Unexpected shift opcode");
1835 case Instruction::LShr: OpReg = X86::SHR64rCL; break;
1836 case Instruction::AShr: OpReg = X86::SAR64rCL; break;
1837 case Instruction::Shl: OpReg = X86::SHL64rCL; break;
1838 }
1839 } else {
1840 return false;
1841 }
1842
1843 MVT VT;
1844 if (!isTypeLegal(Ty: I->getType(), VT))
1845 return false;
1846
1847 Register Op0Reg = getRegForValue(V: I->getOperand(i: 0));
1848 if (!Op0Reg)
1849 return false;
1850
1851 Register Op1Reg = getRegForValue(V: I->getOperand(i: 1));
1852 if (!Op1Reg)
1853 return false;
1854 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: TargetOpcode::COPY),
1855 DestReg: CReg).addReg(RegNo: Op1Reg);
1856
1857 // The shift instruction uses X86::CL. If we defined a super-register
1858 // of X86::CL, emit a subreg KILL to precisely describe what we're doing here.
1859 if (CReg != X86::CL)
1860 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1861 MCID: TII.get(Opcode: TargetOpcode::KILL), DestReg: X86::CL)
1862 .addReg(RegNo: CReg, Flags: RegState::Kill);
1863
1864 Register ResultReg = createResultReg(RC);
1865 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: OpReg), DestReg: ResultReg)
1866 .addReg(RegNo: Op0Reg);
1867 updateValueMap(I, Reg: ResultReg);
1868 return true;
1869}
1870
1871bool X86FastISel::X86SelectDivRem(const Instruction *I) {
1872 const static unsigned NumTypes = 4; // i8, i16, i32, i64
1873 const static unsigned NumOps = 4; // SDiv, SRem, UDiv, URem
1874 const static bool S = true; // IsSigned
1875 const static bool U = false; // !IsSigned
1876 const static unsigned Copy = TargetOpcode::COPY;
1877 // For the X86 DIV/IDIV instruction, in most cases the dividend
1878 // (numerator) must be in a specific register pair highreg:lowreg,
1879 // producing the quotient in lowreg and the remainder in highreg.
1880 // For most data types, to set up the instruction, the dividend is
1881 // copied into lowreg, and lowreg is sign-extended or zero-extended
1882 // into highreg. The exception is i8, where the dividend is defined
1883 // as a single register rather than a register pair, and we
1884 // therefore directly sign-extend or zero-extend the dividend into
1885 // lowreg, instead of copying, and ignore the highreg.
1886 const static struct DivRemEntry {
1887 // The following portion depends only on the data type.
1888 const TargetRegisterClass *RC;
1889 unsigned LowInReg; // low part of the register pair
1890 unsigned HighInReg; // high part of the register pair
1891 // The following portion depends on both the data type and the operation.
1892 struct DivRemResult {
1893 unsigned OpDivRem; // The specific DIV/IDIV opcode to use.
1894 unsigned OpSignExtend; // Opcode for sign-extending lowreg into
1895 // highreg, or copying a zero into highreg.
1896 unsigned OpCopy; // Opcode for copying dividend into lowreg, or
1897 // zero/sign-extending into lowreg for i8.
1898 unsigned DivRemResultReg; // Register containing the desired result.
1899 bool IsOpSigned; // Whether to use signed or unsigned form.
1900 } ResultTable[NumOps];
1901 } OpTable[NumTypes] = {
1902 { .RC: &X86::GR8RegClass, .LowInReg: X86::AX, .HighInReg: 0, .ResultTable: {
1903 { .OpDivRem: X86::IDIV8r, .OpSignExtend: 0, .OpCopy: X86::MOVSX16rr8, .DivRemResultReg: X86::AL, .IsOpSigned: S }, // SDiv
1904 { .OpDivRem: X86::IDIV8r, .OpSignExtend: 0, .OpCopy: X86::MOVSX16rr8, .DivRemResultReg: X86::AH, .IsOpSigned: S }, // SRem
1905 { .OpDivRem: X86::DIV8r, .OpSignExtend: 0, .OpCopy: X86::MOVZX16rr8, .DivRemResultReg: X86::AL, .IsOpSigned: U }, // UDiv
1906 { .OpDivRem: X86::DIV8r, .OpSignExtend: 0, .OpCopy: X86::MOVZX16rr8, .DivRemResultReg: X86::AH, .IsOpSigned: U }, // URem
1907 }
1908 }, // i8
1909 { .RC: &X86::GR16RegClass, .LowInReg: X86::AX, .HighInReg: X86::DX, .ResultTable: {
1910 { .OpDivRem: X86::IDIV16r, .OpSignExtend: X86::CWD, .OpCopy: Copy, .DivRemResultReg: X86::AX, .IsOpSigned: S }, // SDiv
1911 { .OpDivRem: X86::IDIV16r, .OpSignExtend: X86::CWD, .OpCopy: Copy, .DivRemResultReg: X86::DX, .IsOpSigned: S }, // SRem
1912 { .OpDivRem: X86::DIV16r, .OpSignExtend: X86::MOV32r0, .OpCopy: Copy, .DivRemResultReg: X86::AX, .IsOpSigned: U }, // UDiv
1913 { .OpDivRem: X86::DIV16r, .OpSignExtend: X86::MOV32r0, .OpCopy: Copy, .DivRemResultReg: X86::DX, .IsOpSigned: U }, // URem
1914 }
1915 }, // i16
1916 { .RC: &X86::GR32RegClass, .LowInReg: X86::EAX, .HighInReg: X86::EDX, .ResultTable: {
1917 { .OpDivRem: X86::IDIV32r, .OpSignExtend: X86::CDQ, .OpCopy: Copy, .DivRemResultReg: X86::EAX, .IsOpSigned: S }, // SDiv
1918 { .OpDivRem: X86::IDIV32r, .OpSignExtend: X86::CDQ, .OpCopy: Copy, .DivRemResultReg: X86::EDX, .IsOpSigned: S }, // SRem
1919 { .OpDivRem: X86::DIV32r, .OpSignExtend: X86::MOV32r0, .OpCopy: Copy, .DivRemResultReg: X86::EAX, .IsOpSigned: U }, // UDiv
1920 { .OpDivRem: X86::DIV32r, .OpSignExtend: X86::MOV32r0, .OpCopy: Copy, .DivRemResultReg: X86::EDX, .IsOpSigned: U }, // URem
1921 }
1922 }, // i32
1923 { .RC: &X86::GR64RegClass, .LowInReg: X86::RAX, .HighInReg: X86::RDX, .ResultTable: {
1924 { .OpDivRem: X86::IDIV64r, .OpSignExtend: X86::CQO, .OpCopy: Copy, .DivRemResultReg: X86::RAX, .IsOpSigned: S }, // SDiv
1925 { .OpDivRem: X86::IDIV64r, .OpSignExtend: X86::CQO, .OpCopy: Copy, .DivRemResultReg: X86::RDX, .IsOpSigned: S }, // SRem
1926 { .OpDivRem: X86::DIV64r, .OpSignExtend: X86::MOV32r0, .OpCopy: Copy, .DivRemResultReg: X86::RAX, .IsOpSigned: U }, // UDiv
1927 { .OpDivRem: X86::DIV64r, .OpSignExtend: X86::MOV32r0, .OpCopy: Copy, .DivRemResultReg: X86::RDX, .IsOpSigned: U }, // URem
1928 }
1929 }, // i64
1930 };
1931
1932 MVT VT;
1933 if (!isTypeLegal(Ty: I->getType(), VT))
1934 return false;
1935
1936 unsigned TypeIndex, OpIndex;
1937 switch (VT.SimpleTy) {
1938 default: return false;
1939 case MVT::i8: TypeIndex = 0; break;
1940 case MVT::i16: TypeIndex = 1; break;
1941 case MVT::i32: TypeIndex = 2; break;
1942 case MVT::i64: TypeIndex = 3;
1943 if (!Subtarget->is64Bit())
1944 return false;
1945 break;
1946 }
1947
1948 switch (I->getOpcode()) {
1949 default: llvm_unreachable("Unexpected div/rem opcode");
1950 case Instruction::SDiv: OpIndex = 0; break;
1951 case Instruction::SRem: OpIndex = 1; break;
1952 case Instruction::UDiv: OpIndex = 2; break;
1953 case Instruction::URem: OpIndex = 3; break;
1954 }
1955
1956 const DivRemEntry &TypeEntry = OpTable[TypeIndex];
1957 const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex];
1958 Register Op0Reg = getRegForValue(V: I->getOperand(i: 0));
1959 if (!Op0Reg)
1960 return false;
1961 Register Op1Reg = getRegForValue(V: I->getOperand(i: 1));
1962 if (!Op1Reg)
1963 return false;
1964
1965 // Move op0 into low-order input register.
1966 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1967 MCID: TII.get(Opcode: OpEntry.OpCopy), DestReg: TypeEntry.LowInReg).addReg(RegNo: Op0Reg);
1968 // Zero-extend or sign-extend into high-order input register.
1969 if (OpEntry.OpSignExtend) {
1970 if (OpEntry.IsOpSigned)
1971 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1972 MCID: TII.get(Opcode: OpEntry.OpSignExtend));
1973 else {
1974 Register Zero32 = createResultReg(RC: &X86::GR32RegClass);
1975 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1976 MCID: TII.get(Opcode: X86::MOV32r0), DestReg: Zero32);
1977
1978 // Copy the zero into the appropriate sub/super/identical physical
1979 // register. Unfortunately the operations needed are not uniform enough
1980 // to fit neatly into the table above.
1981 if (VT == MVT::i16) {
1982 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Copy),
1983 DestReg: TypeEntry.HighInReg)
1984 .addReg(RegNo: Zero32, Flags: {}, SubReg: X86::sub_16bit);
1985 } else if (VT == MVT::i32) {
1986 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1987 MCID: TII.get(Opcode: Copy), DestReg: TypeEntry.HighInReg)
1988 .addReg(RegNo: Zero32);
1989 } else if (VT == MVT::i64) {
1990 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1991 MCID: TII.get(Opcode: TargetOpcode::SUBREG_TO_REG), DestReg: TypeEntry.HighInReg)
1992 .addImm(Val: 0).addReg(RegNo: Zero32).addImm(Val: X86::sub_32bit);
1993 }
1994 }
1995 }
1996 // Generate the DIV/IDIV instruction.
1997 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
1998 MCID: TII.get(Opcode: OpEntry.OpDivRem)).addReg(RegNo: Op1Reg);
1999 // For i8 remainder, we can't reference ah directly, as we'll end
2000 // up with bogus copies like %r9b = COPY %ah. Reference ax
2001 // instead to prevent ah references in a rex instruction.
2002 //
2003 // The current assumption of the fast register allocator is that isel
2004 // won't generate explicit references to the GR8_NOREX registers. If
2005 // the allocator and/or the backend get enhanced to be more robust in
2006 // that regard, this can be, and should be, removed.
2007 Register ResultReg;
2008 if ((I->getOpcode() == Instruction::SRem ||
2009 I->getOpcode() == Instruction::URem) &&
2010 OpEntry.DivRemResultReg == X86::AH && Subtarget->is64Bit()) {
2011 Register SourceSuperReg = createResultReg(RC: &X86::GR16RegClass);
2012 Register ResultSuperReg = createResultReg(RC: &X86::GR16RegClass);
2013 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2014 MCID: TII.get(Opcode: Copy), DestReg: SourceSuperReg).addReg(RegNo: X86::AX);
2015
2016 // Shift AX right by 8 bits instead of using AH.
2017 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: X86::SHR16ri),
2018 DestReg: ResultSuperReg).addReg(RegNo: SourceSuperReg).addImm(Val: 8);
2019
2020 // Now reference the 8-bit subreg of the result.
2021 ResultReg = fastEmitInst_extractsubreg(RetVT: MVT::i8, Op0: ResultSuperReg,
2022 Idx: X86::sub_8bit);
2023 }
2024 // Copy the result out of the physreg if we haven't already.
2025 if (!ResultReg) {
2026 ResultReg = createResultReg(RC: TypeEntry.RC);
2027 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Copy), DestReg: ResultReg)
2028 .addReg(RegNo: OpEntry.DivRemResultReg);
2029 }
2030 updateValueMap(I, Reg: ResultReg);
2031
2032 return true;
2033}
2034
2035/// Emit a conditional move instruction (if the are supported) to lower
2036/// the select.
2037bool X86FastISel::X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I) {
2038 // Check if the subtarget supports these instructions.
2039 if (!Subtarget->canUseCMOV())
2040 return false;
2041
2042 // FIXME: Add support for i8.
2043 if (RetVT < MVT::i16 || RetVT > MVT::i64)
2044 return false;
2045
2046 const Value *Cond = I->getOperand(i: 0);
2047 const TargetRegisterClass *RC = TLI.getRegClassFor(VT: RetVT);
2048 bool NeedTest = true;
2049 X86::CondCode CC = X86::COND_NE;
2050
2051 // Optimize conditions coming from a compare if both instructions are in the
2052 // same basic block (values defined in other basic blocks may not have
2053 // initialized registers).
2054 const auto *CI = dyn_cast<CmpInst>(Val: Cond);
2055 if (CI && (CI->getParent() == I->getParent())) {
2056 CmpInst::Predicate Predicate = optimizeCmpPredicate(CI);
2057
2058 // FCMP_OEQ and FCMP_UNE cannot be checked with a single instruction.
2059 static const uint16_t SETFOpcTable[2][3] = {
2060 { X86::COND_NP, X86::COND_E, X86::TEST8rr },
2061 { X86::COND_P, X86::COND_NE, X86::OR8rr }
2062 };
2063 const uint16_t *SETFOpc = nullptr;
2064 switch (Predicate) {
2065 default: break;
2066 case CmpInst::FCMP_OEQ:
2067 SETFOpc = &SETFOpcTable[0][0];
2068 Predicate = CmpInst::ICMP_NE;
2069 break;
2070 case CmpInst::FCMP_UNE:
2071 SETFOpc = &SETFOpcTable[1][0];
2072 Predicate = CmpInst::ICMP_NE;
2073 break;
2074 }
2075
2076 bool NeedSwap;
2077 std::tie(args&: CC, args&: NeedSwap) = X86::getX86ConditionCode(Predicate);
2078 assert(CC <= X86::LAST_VALID_COND && "Unexpected condition code.");
2079
2080 const Value *CmpLHS = CI->getOperand(i_nocapture: 0);
2081 const Value *CmpRHS = CI->getOperand(i_nocapture: 1);
2082 if (NeedSwap)
2083 std::swap(a&: CmpLHS, b&: CmpRHS);
2084
2085 EVT CmpVT = TLI.getValueType(DL, Ty: CmpLHS->getType());
2086 // Emit a compare of the LHS and RHS, setting the flags.
2087 if (!X86FastEmitCompare(Op0: CmpLHS, Op1: CmpRHS, VT: CmpVT, CurMIMD: CI->getDebugLoc()))
2088 return false;
2089
2090 if (SETFOpc) {
2091 Register FlagReg1 = createResultReg(RC: &X86::GR8RegClass);
2092 Register FlagReg2 = createResultReg(RC: &X86::GR8RegClass);
2093 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(GET_SETCC),
2094 DestReg: FlagReg1)
2095 .addImm(Val: SETFOpc[0]);
2096 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(GET_SETCC),
2097 DestReg: FlagReg2)
2098 .addImm(Val: SETFOpc[1]);
2099 auto const &II = TII.get(Opcode: SETFOpc[2]);
2100 if (II.getNumDefs()) {
2101 Register TmpReg = createResultReg(RC: &X86::GR8RegClass);
2102 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: II, DestReg: TmpReg)
2103 .addReg(RegNo: FlagReg2).addReg(RegNo: FlagReg1);
2104 } else {
2105 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: II)
2106 .addReg(RegNo: FlagReg2).addReg(RegNo: FlagReg1);
2107 }
2108 }
2109 NeedTest = false;
2110 } else if (foldX86XALUIntrinsic(CC, I, Cond)) {
2111 // Fake request the condition, otherwise the intrinsic might be completely
2112 // optimized away.
2113 Register TmpReg = getRegForValue(V: Cond);
2114 if (!TmpReg)
2115 return false;
2116
2117 NeedTest = false;
2118 }
2119
2120 if (NeedTest) {
2121 // Selects operate on i1, however, CondReg is 8 bits width and may contain
2122 // garbage. Indeed, only the less significant bit is supposed to be
2123 // accurate. If we read more than the lsb, we may see non-zero values
2124 // whereas lsb is zero. Therefore, we have to truncate Op0Reg to i1 for
2125 // the select. This is achieved by performing TEST against 1.
2126 Register CondReg = getRegForValue(V: Cond);
2127 if (!CondReg)
2128 return false;
2129
2130 // In case OpReg is a K register, COPY to a GPR
2131 if (MRI.getRegClass(Reg: CondReg) == &X86::VK1RegClass) {
2132 Register KCondReg = CondReg;
2133 CondReg = createResultReg(RC: &X86::GR32RegClass);
2134 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2135 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: CondReg)
2136 .addReg(RegNo: KCondReg);
2137 CondReg = fastEmitInst_extractsubreg(RetVT: MVT::i8, Op0: CondReg, Idx: X86::sub_8bit);
2138 }
2139 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: X86::TEST8ri))
2140 .addReg(RegNo: CondReg)
2141 .addImm(Val: 1);
2142 }
2143
2144 const Value *LHS = I->getOperand(i: 1);
2145 const Value *RHS = I->getOperand(i: 2);
2146
2147 Register RHSReg = getRegForValue(V: RHS);
2148 Register LHSReg = getRegForValue(V: LHS);
2149 if (!LHSReg || !RHSReg)
2150 return false;
2151
2152 const TargetRegisterInfo &TRI = *Subtarget->getRegisterInfo();
2153 unsigned Opc = X86::getCMovOpcode(RegBytes: TRI.getRegSizeInBits(RC: *RC) / 8, HasMemoryOperand: false,
2154 HasNDD: Subtarget->hasNDD());
2155 Register ResultReg = fastEmitInst_rri(MachineInstOpcode: Opc, RC, Op0: RHSReg, Op1: LHSReg, Imm: CC);
2156 updateValueMap(I, Reg: ResultReg);
2157 return true;
2158}
2159
2160/// Emit SSE or AVX instructions to lower the select.
2161///
2162/// Try to use SSE1/SSE2 instructions to simulate a select without branches.
2163/// This lowers fp selects into a CMP/AND/ANDN/OR sequence when the necessary
2164/// SSE instructions are available. If AVX is available, try to use a VBLENDV.
2165bool X86FastISel::X86FastEmitSSESelect(MVT RetVT, const Instruction *I) {
2166 // Optimize conditions coming from a compare if both instructions are in the
2167 // same basic block (values defined in other basic blocks may not have
2168 // initialized registers).
2169 const auto *CI = dyn_cast<FCmpInst>(Val: I->getOperand(i: 0));
2170 if (!CI || (CI->getParent() != I->getParent()))
2171 return false;
2172
2173 if (I->getType() != CI->getOperand(i_nocapture: 0)->getType() ||
2174 !((Subtarget->hasSSE1() && RetVT == MVT::f32) ||
2175 (Subtarget->hasSSE2() && RetVT == MVT::f64)))
2176 return false;
2177
2178 const Value *CmpLHS = CI->getOperand(i_nocapture: 0);
2179 const Value *CmpRHS = CI->getOperand(i_nocapture: 1);
2180 CmpInst::Predicate Predicate = optimizeCmpPredicate(CI);
2181
2182 // The optimizer might have replaced fcmp oeq %x, %x with fcmp ord %x, 0.0.
2183 // We don't have to materialize a zero constant for this case and can just use
2184 // %x again on the RHS.
2185 if (Predicate == CmpInst::FCMP_ORD || Predicate == CmpInst::FCMP_UNO) {
2186 const auto *CmpRHSC = dyn_cast<ConstantFP>(Val: CmpRHS);
2187 if (CmpRHSC && CmpRHSC->isNullValue())
2188 CmpRHS = CmpLHS;
2189 }
2190
2191 unsigned CC;
2192 bool NeedSwap;
2193 std::tie(args&: CC, args&: NeedSwap) = getX86SSEConditionCode(Predicate);
2194 if (CC > 7 && !Subtarget->hasAVX())
2195 return false;
2196
2197 if (NeedSwap)
2198 std::swap(a&: CmpLHS, b&: CmpRHS);
2199
2200 const Value *LHS = I->getOperand(i: 1);
2201 const Value *RHS = I->getOperand(i: 2);
2202
2203 Register LHSReg = getRegForValue(V: LHS);
2204 Register RHSReg = getRegForValue(V: RHS);
2205 Register CmpLHSReg = getRegForValue(V: CmpLHS);
2206 Register CmpRHSReg = getRegForValue(V: CmpRHS);
2207 if (!LHSReg || !RHSReg || !CmpLHSReg || !CmpRHSReg)
2208 return false;
2209
2210 const TargetRegisterClass *RC = TLI.getRegClassFor(VT: RetVT);
2211 Register ResultReg;
2212
2213 if (Subtarget->hasAVX512()) {
2214 // If we have AVX512 we can use a mask compare and masked movss/sd.
2215 const TargetRegisterClass *VR128X = &X86::VR128XRegClass;
2216 const TargetRegisterClass *VK1 = &X86::VK1RegClass;
2217
2218 unsigned CmpOpcode =
2219 (RetVT == MVT::f32) ? X86::VCMPSSZrri : X86::VCMPSDZrri;
2220 Register CmpReg = fastEmitInst_rri(MachineInstOpcode: CmpOpcode, RC: VK1, Op0: CmpLHSReg, Op1: CmpRHSReg,
2221 Imm: CC);
2222
2223 // Need an IMPLICIT_DEF for the input that is used to generate the upper
2224 // bits of the result register since its not based on any of the inputs.
2225 Register ImplicitDefReg = createResultReg(RC: VR128X);
2226 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2227 MCID: TII.get(Opcode: TargetOpcode::IMPLICIT_DEF), DestReg: ImplicitDefReg);
2228
2229 // Place RHSReg is the passthru of the masked movss/sd operation and put
2230 // LHS in the input. The mask input comes from the compare.
2231 unsigned MovOpcode =
2232 (RetVT == MVT::f32) ? X86::VMOVSSZrrk : X86::VMOVSDZrrk;
2233 Register MovReg = fastEmitInst_rrrr(MachineInstOpcode: MovOpcode, RC: VR128X, Op0: RHSReg, Op1: CmpReg,
2234 Op2: ImplicitDefReg, Op3: LHSReg);
2235
2236 ResultReg = createResultReg(RC);
2237 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2238 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: ResultReg).addReg(RegNo: MovReg);
2239
2240 } else if (Subtarget->hasAVX()) {
2241 const TargetRegisterClass *VR128 = &X86::VR128RegClass;
2242
2243 // If we have AVX, create 1 blendv instead of 3 logic instructions.
2244 // Blendv was introduced with SSE 4.1, but the 2 register form implicitly
2245 // uses XMM0 as the selection register. That may need just as many
2246 // instructions as the AND/ANDN/OR sequence due to register moves, so
2247 // don't bother.
2248 unsigned CmpOpcode =
2249 (RetVT == MVT::f32) ? X86::VCMPSSrri : X86::VCMPSDrri;
2250 unsigned BlendOpcode =
2251 (RetVT == MVT::f32) ? X86::VBLENDVPSrrr : X86::VBLENDVPDrrr;
2252
2253 Register CmpReg = fastEmitInst_rri(MachineInstOpcode: CmpOpcode, RC, Op0: CmpLHSReg, Op1: CmpRHSReg,
2254 Imm: CC);
2255 Register VBlendReg = fastEmitInst_rrr(MachineInstOpcode: BlendOpcode, RC: VR128, Op0: RHSReg, Op1: LHSReg,
2256 Op2: CmpReg);
2257 ResultReg = createResultReg(RC);
2258 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2259 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: ResultReg).addReg(RegNo: VBlendReg);
2260 } else {
2261 // Choose the SSE instruction sequence based on data type (float or double).
2262 static const uint16_t OpcTable[2][4] = {
2263 { X86::CMPSSrri, X86::ANDPSrr, X86::ANDNPSrr, X86::ORPSrr },
2264 { X86::CMPSDrri, X86::ANDPDrr, X86::ANDNPDrr, X86::ORPDrr }
2265 };
2266
2267 const uint16_t *Opc = nullptr;
2268 switch (RetVT.SimpleTy) {
2269 default: return false;
2270 case MVT::f32: Opc = &OpcTable[0][0]; break;
2271 case MVT::f64: Opc = &OpcTable[1][0]; break;
2272 }
2273
2274 const TargetRegisterClass *VR128 = &X86::VR128RegClass;
2275 Register CmpReg = fastEmitInst_rri(MachineInstOpcode: Opc[0], RC, Op0: CmpLHSReg, Op1: CmpRHSReg, Imm: CC);
2276 Register AndReg = fastEmitInst_rr(MachineInstOpcode: Opc[1], RC: VR128, Op0: CmpReg, Op1: LHSReg);
2277 Register AndNReg = fastEmitInst_rr(MachineInstOpcode: Opc[2], RC: VR128, Op0: CmpReg, Op1: RHSReg);
2278 Register OrReg = fastEmitInst_rr(MachineInstOpcode: Opc[3], RC: VR128, Op0: AndNReg, Op1: AndReg);
2279 ResultReg = createResultReg(RC);
2280 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2281 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: ResultReg).addReg(RegNo: OrReg);
2282 }
2283 updateValueMap(I, Reg: ResultReg);
2284 return true;
2285}
2286
2287bool X86FastISel::X86FastEmitPseudoSelect(MVT RetVT, const Instruction *I) {
2288 // These are pseudo CMOV instructions and will be later expanded into control-
2289 // flow.
2290 unsigned Opc;
2291 switch (RetVT.SimpleTy) {
2292 default: return false;
2293 case MVT::i8: Opc = X86::CMOV_GR8; break;
2294 case MVT::i16: Opc = X86::CMOV_GR16; break;
2295 case MVT::i32: Opc = X86::CMOV_GR32; break;
2296 case MVT::f16:
2297 Opc = Subtarget->hasAVX512() ? X86::CMOV_FR16X : X86::CMOV_FR16; break;
2298 case MVT::f32:
2299 Opc = Subtarget->hasAVX512() ? X86::CMOV_FR32X : X86::CMOV_FR32; break;
2300 case MVT::f64:
2301 Opc = Subtarget->hasAVX512() ? X86::CMOV_FR64X : X86::CMOV_FR64; break;
2302 }
2303
2304 const Value *Cond = I->getOperand(i: 0);
2305 X86::CondCode CC = X86::COND_NE;
2306
2307 // Optimize conditions coming from a compare if both instructions are in the
2308 // same basic block (values defined in other basic blocks may not have
2309 // initialized registers).
2310 const auto *CI = dyn_cast<CmpInst>(Val: Cond);
2311 if (CI && (CI->getParent() == I->getParent())) {
2312 bool NeedSwap;
2313 std::tie(args&: CC, args&: NeedSwap) = X86::getX86ConditionCode(Predicate: CI->getPredicate());
2314 if (CC > X86::LAST_VALID_COND)
2315 return false;
2316
2317 const Value *CmpLHS = CI->getOperand(i_nocapture: 0);
2318 const Value *CmpRHS = CI->getOperand(i_nocapture: 1);
2319
2320 if (NeedSwap)
2321 std::swap(a&: CmpLHS, b&: CmpRHS);
2322
2323 EVT CmpVT = TLI.getValueType(DL, Ty: CmpLHS->getType());
2324 if (!X86FastEmitCompare(Op0: CmpLHS, Op1: CmpRHS, VT: CmpVT, CurMIMD: CI->getDebugLoc()))
2325 return false;
2326 } else {
2327 Register CondReg = getRegForValue(V: Cond);
2328 if (!CondReg)
2329 return false;
2330
2331 // In case OpReg is a K register, COPY to a GPR
2332 if (MRI.getRegClass(Reg: CondReg) == &X86::VK1RegClass) {
2333 Register KCondReg = CondReg;
2334 CondReg = createResultReg(RC: &X86::GR32RegClass);
2335 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2336 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: CondReg)
2337 .addReg(RegNo: KCondReg);
2338 CondReg = fastEmitInst_extractsubreg(RetVT: MVT::i8, Op0: CondReg, Idx: X86::sub_8bit);
2339 }
2340 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: X86::TEST8ri))
2341 .addReg(RegNo: CondReg)
2342 .addImm(Val: 1);
2343 }
2344
2345 const Value *LHS = I->getOperand(i: 1);
2346 const Value *RHS = I->getOperand(i: 2);
2347
2348 Register LHSReg = getRegForValue(V: LHS);
2349 Register RHSReg = getRegForValue(V: RHS);
2350 if (!LHSReg || !RHSReg)
2351 return false;
2352
2353 const TargetRegisterClass *RC = TLI.getRegClassFor(VT: RetVT);
2354
2355 Register ResultReg =
2356 fastEmitInst_rri(MachineInstOpcode: Opc, RC, Op0: RHSReg, Op1: LHSReg, Imm: CC);
2357 updateValueMap(I, Reg: ResultReg);
2358 return true;
2359}
2360
2361bool X86FastISel::X86SelectSelect(const Instruction *I) {
2362 MVT RetVT;
2363 if (!isTypeLegal(Ty: I->getType(), VT&: RetVT))
2364 return false;
2365
2366 // Check if we can fold the select.
2367 if (const auto *CI = dyn_cast<CmpInst>(Val: I->getOperand(i: 0))) {
2368 CmpInst::Predicate Predicate = optimizeCmpPredicate(CI);
2369 const Value *Opnd = nullptr;
2370 switch (Predicate) {
2371 default: break;
2372 case CmpInst::FCMP_FALSE: Opnd = I->getOperand(i: 2); break;
2373 case CmpInst::FCMP_TRUE: Opnd = I->getOperand(i: 1); break;
2374 }
2375 // No need for a select anymore - this is an unconditional move.
2376 if (Opnd) {
2377 Register OpReg = getRegForValue(V: Opnd);
2378 if (!OpReg)
2379 return false;
2380 const TargetRegisterClass *RC = TLI.getRegClassFor(VT: RetVT);
2381 Register ResultReg = createResultReg(RC);
2382 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2383 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: ResultReg)
2384 .addReg(RegNo: OpReg);
2385 updateValueMap(I, Reg: ResultReg);
2386 return true;
2387 }
2388 }
2389
2390 // First try to use real conditional move instructions.
2391 if (X86FastEmitCMoveSelect(RetVT, I))
2392 return true;
2393
2394 // Try to use a sequence of SSE instructions to simulate a conditional move.
2395 if (X86FastEmitSSESelect(RetVT, I))
2396 return true;
2397
2398 // Fall-back to pseudo conditional move instructions, which will be later
2399 // converted to control-flow.
2400 if (X86FastEmitPseudoSelect(RetVT, I))
2401 return true;
2402
2403 return false;
2404}
2405
2406// Common code for X86SelectSIToFP and X86SelectUIToFP.
2407bool X86FastISel::X86SelectIntToFP(const Instruction *I, bool IsSigned) {
2408 // The target-independent selection algorithm in FastISel already knows how
2409 // to select a SINT_TO_FP if the target is SSE but not AVX.
2410 // Early exit if the subtarget doesn't have AVX.
2411 // Unsigned conversion requires avx512.
2412 bool HasAVX512 = Subtarget->hasAVX512();
2413 if (!Subtarget->hasAVX() || (!IsSigned && !HasAVX512))
2414 return false;
2415
2416 // TODO: We could sign extend narrower types.
2417 EVT SrcVT = TLI.getValueType(DL, Ty: I->getOperand(i: 0)->getType());
2418 if (SrcVT != MVT::i32 && SrcVT != MVT::i64)
2419 return false;
2420
2421 // Select integer to float/double conversion.
2422 Register OpReg = getRegForValue(V: I->getOperand(i: 0));
2423 if (!OpReg)
2424 return false;
2425
2426 unsigned Opcode;
2427
2428 static const uint16_t SCvtOpc[2][2][2] = {
2429 { { X86::VCVTSI2SSrr, X86::VCVTSI642SSrr },
2430 { X86::VCVTSI2SDrr, X86::VCVTSI642SDrr } },
2431 { { X86::VCVTSI2SSZrr, X86::VCVTSI642SSZrr },
2432 { X86::VCVTSI2SDZrr, X86::VCVTSI642SDZrr } },
2433 };
2434 static const uint16_t UCvtOpc[2][2] = {
2435 { X86::VCVTUSI2SSZrr, X86::VCVTUSI642SSZrr },
2436 { X86::VCVTUSI2SDZrr, X86::VCVTUSI642SDZrr },
2437 };
2438 bool Is64Bit = SrcVT == MVT::i64;
2439
2440 if (I->getType()->isDoubleTy()) {
2441 // s/uitofp int -> double
2442 Opcode = IsSigned ? SCvtOpc[HasAVX512][1][Is64Bit] : UCvtOpc[1][Is64Bit];
2443 } else if (I->getType()->isFloatTy()) {
2444 // s/uitofp int -> float
2445 Opcode = IsSigned ? SCvtOpc[HasAVX512][0][Is64Bit] : UCvtOpc[0][Is64Bit];
2446 } else
2447 return false;
2448
2449 MVT DstVT = TLI.getValueType(DL, Ty: I->getType()).getSimpleVT();
2450 const TargetRegisterClass *RC = TLI.getRegClassFor(VT: DstVT);
2451 Register ImplicitDefReg = createResultReg(RC);
2452 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2453 MCID: TII.get(Opcode: TargetOpcode::IMPLICIT_DEF), DestReg: ImplicitDefReg);
2454 Register ResultReg = fastEmitInst_rr(MachineInstOpcode: Opcode, RC, Op0: ImplicitDefReg, Op1: OpReg);
2455 updateValueMap(I, Reg: ResultReg);
2456 return true;
2457}
2458
2459bool X86FastISel::X86SelectSIToFP(const Instruction *I) {
2460 return X86SelectIntToFP(I, /*IsSigned*/true);
2461}
2462
2463bool X86FastISel::X86SelectUIToFP(const Instruction *I) {
2464 return X86SelectIntToFP(I, /*IsSigned*/false);
2465}
2466
2467// Helper method used by X86SelectFPExt and X86SelectFPTrunc.
2468bool X86FastISel::X86SelectFPExtOrFPTrunc(const Instruction *I,
2469 unsigned TargetOpc,
2470 const TargetRegisterClass *RC) {
2471 assert((I->getOpcode() == Instruction::FPExt ||
2472 I->getOpcode() == Instruction::FPTrunc) &&
2473 "Instruction must be an FPExt or FPTrunc!");
2474 bool HasAVX = Subtarget->hasAVX();
2475
2476 Register OpReg = getRegForValue(V: I->getOperand(i: 0));
2477 if (!OpReg)
2478 return false;
2479
2480 Register ImplicitDefReg;
2481 if (HasAVX) {
2482 ImplicitDefReg = createResultReg(RC);
2483 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2484 MCID: TII.get(Opcode: TargetOpcode::IMPLICIT_DEF), DestReg: ImplicitDefReg);
2485
2486 }
2487
2488 Register ResultReg = createResultReg(RC);
2489 MachineInstrBuilder MIB;
2490 MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: TargetOpc),
2491 DestReg: ResultReg);
2492
2493 if (HasAVX)
2494 MIB.addReg(RegNo: ImplicitDefReg);
2495
2496 MIB.addReg(RegNo: OpReg);
2497 updateValueMap(I, Reg: ResultReg);
2498 return true;
2499}
2500
2501bool X86FastISel::X86SelectFPExt(const Instruction *I) {
2502 if (Subtarget->hasSSE2() && I->getType()->isDoubleTy() &&
2503 I->getOperand(i: 0)->getType()->isFloatTy()) {
2504 bool HasAVX512 = Subtarget->hasAVX512();
2505 // fpext from float to double.
2506 unsigned Opc =
2507 HasAVX512 ? X86::VCVTSS2SDZrr
2508 : Subtarget->hasAVX() ? X86::VCVTSS2SDrr : X86::CVTSS2SDrr;
2509 return X86SelectFPExtOrFPTrunc(I, TargetOpc: Opc, RC: TLI.getRegClassFor(VT: MVT::f64));
2510 }
2511
2512 return false;
2513}
2514
2515bool X86FastISel::X86SelectFPTrunc(const Instruction *I) {
2516 if (Subtarget->hasSSE2() && I->getType()->isFloatTy() &&
2517 I->getOperand(i: 0)->getType()->isDoubleTy()) {
2518 bool HasAVX512 = Subtarget->hasAVX512();
2519 // fptrunc from double to float.
2520 unsigned Opc =
2521 HasAVX512 ? X86::VCVTSD2SSZrr
2522 : Subtarget->hasAVX() ? X86::VCVTSD2SSrr : X86::CVTSD2SSrr;
2523 return X86SelectFPExtOrFPTrunc(I, TargetOpc: Opc, RC: TLI.getRegClassFor(VT: MVT::f32));
2524 }
2525
2526 return false;
2527}
2528
2529bool X86FastISel::X86SelectTrunc(const Instruction *I) {
2530 EVT SrcVT = TLI.getValueType(DL, Ty: I->getOperand(i: 0)->getType());
2531 EVT DstVT = TLI.getValueType(DL, Ty: I->getType());
2532
2533 // This code only handles truncation to byte.
2534 if (DstVT != MVT::i8 && DstVT != MVT::i1)
2535 return false;
2536 if (!TLI.isTypeLegal(VT: SrcVT))
2537 return false;
2538
2539 Register InputReg = getRegForValue(V: I->getOperand(i: 0));
2540 if (!InputReg)
2541 // Unhandled operand. Halt "fast" selection and bail.
2542 return false;
2543
2544 if (SrcVT == MVT::i8) {
2545 // Truncate from i8 to i1; no code needed.
2546 updateValueMap(I, Reg: InputReg);
2547 return true;
2548 }
2549
2550 // Issue an extract_subreg.
2551 Register ResultReg = fastEmitInst_extractsubreg(RetVT: MVT::i8, Op0: InputReg,
2552 Idx: X86::sub_8bit);
2553 if (!ResultReg)
2554 return false;
2555
2556 updateValueMap(I, Reg: ResultReg);
2557 return true;
2558}
2559
2560bool X86FastISel::X86SelectBitCast(const Instruction *I) {
2561 // Select SSE2/AVX bitcasts between 128/256/512 bit vector types.
2562 MVT SrcVT, DstVT;
2563 if (!Subtarget->hasSSE2() ||
2564 !isTypeLegal(Ty: I->getOperand(i: 0)->getType(), VT&: SrcVT) ||
2565 !isTypeLegal(Ty: I->getType(), VT&: DstVT))
2566 return false;
2567
2568 // Only allow vectors that use xmm/ymm/zmm.
2569 if (!SrcVT.isVector() || !DstVT.isVector() ||
2570 SrcVT.getVectorElementType() == MVT::i1 ||
2571 DstVT.getVectorElementType() == MVT::i1)
2572 return false;
2573
2574 Register Reg = getRegForValue(V: I->getOperand(i: 0));
2575 if (!Reg)
2576 return false;
2577
2578 // Emit a reg-reg copy so we don't propagate cached known bits information
2579 // with the wrong VT if we fall out of fast isel after selecting this.
2580 const TargetRegisterClass *DstClass = TLI.getRegClassFor(VT: DstVT);
2581 Register ResultReg = createResultReg(RC: DstClass);
2582 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: TargetOpcode::COPY),
2583 DestReg: ResultReg)
2584 .addReg(RegNo: Reg);
2585
2586 updateValueMap(I, Reg: ResultReg);
2587 return true;
2588}
2589
2590bool X86FastISel::IsMemcpySmall(uint64_t Len) {
2591 return Len <= (Subtarget->is64Bit() ? 32 : 16);
2592}
2593
2594bool X86FastISel::TryEmitSmallMemcpy(X86AddressMode DestAM,
2595 X86AddressMode SrcAM, uint64_t Len) {
2596
2597 // Make sure we don't bloat code by inlining very large memcpy's.
2598 if (!IsMemcpySmall(Len))
2599 return false;
2600
2601 bool i64Legal = Subtarget->is64Bit();
2602
2603 // We don't care about alignment here since we just emit integer accesses.
2604 while (Len) {
2605 MVT VT;
2606 if (Len >= 8 && i64Legal)
2607 VT = MVT::i64;
2608 else if (Len >= 4)
2609 VT = MVT::i32;
2610 else if (Len >= 2)
2611 VT = MVT::i16;
2612 else
2613 VT = MVT::i8;
2614
2615 Register Reg;
2616 bool RV = X86FastEmitLoad(VT, AM&: SrcAM, MMO: nullptr, ResultReg&: Reg);
2617 RV &= X86FastEmitStore(VT, ValReg: Reg, AM&: DestAM);
2618 assert(RV && "Failed to emit load or store??");
2619 (void)RV;
2620
2621 unsigned Size = VT.getSizeInBits()/8;
2622 Len -= Size;
2623 DestAM.Disp += Size;
2624 SrcAM.Disp += Size;
2625 }
2626
2627 return true;
2628}
2629
2630bool X86FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
2631 // FIXME: Handle more intrinsics.
2632 switch (II->getIntrinsicID()) {
2633 default:
2634 return false;
2635 case Intrinsic::frameaddress: {
2636 MachineFunction *MF = FuncInfo.MF;
2637 if (MF->getTarget().getMCAsmInfo()->usesWindowsCFI())
2638 return false;
2639
2640 Type *RetTy = II->getCalledFunction()->getReturnType();
2641
2642 MVT VT;
2643 if (!isTypeLegal(Ty: RetTy, VT))
2644 return false;
2645
2646 unsigned Opc;
2647 const TargetRegisterClass *RC = nullptr;
2648
2649 switch (VT.SimpleTy) {
2650 default: llvm_unreachable("Invalid result type for frameaddress.");
2651 case MVT::i32: Opc = X86::MOV32rm; RC = &X86::GR32RegClass; break;
2652 case MVT::i64: Opc = X86::MOV64rm; RC = &X86::GR64RegClass; break;
2653 }
2654
2655 // This needs to be set before we call getPtrSizedFrameRegister, otherwise
2656 // we get the wrong frame register.
2657 MachineFrameInfo &MFI = MF->getFrameInfo();
2658 MFI.setFrameAddressIsTaken(true);
2659
2660 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
2661 Register FrameReg = RegInfo->getPtrSizedFrameRegister(MF: *MF);
2662 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
2663 (FrameReg == X86::EBP && VT == MVT::i32)) &&
2664 "Invalid Frame Register!");
2665
2666 // Always make a copy of the frame register to a vreg first, so that we
2667 // never directly reference the frame register (the TwoAddressInstruction-
2668 // Pass doesn't like that).
2669 Register SrcReg = createResultReg(RC);
2670 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2671 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: SrcReg).addReg(RegNo: FrameReg);
2672
2673 // Now recursively load from the frame address.
2674 // movq (%rbp), %rax
2675 // movq (%rax), %rax
2676 // movq (%rax), %rax
2677 // ...
2678 unsigned Depth = cast<ConstantInt>(Val: II->getOperand(i_nocapture: 0))->getZExtValue();
2679 while (Depth--) {
2680 Register DestReg = createResultReg(RC);
2681 addDirectMem(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2682 MCID: TII.get(Opcode: Opc), DestReg), Reg: SrcReg);
2683 SrcReg = DestReg;
2684 }
2685
2686 updateValueMap(I: II, Reg: SrcReg);
2687 return true;
2688 }
2689 case Intrinsic::memcpy: {
2690 const MemCpyInst *MCI = cast<MemCpyInst>(Val: II);
2691 // Don't handle volatile or variable length memcpys.
2692 if (MCI->isVolatile())
2693 return false;
2694
2695 if (isa<ConstantInt>(Val: MCI->getLength())) {
2696 // Small memcpy's are common enough that we want to do them
2697 // without a call if possible.
2698 uint64_t Len = cast<ConstantInt>(Val: MCI->getLength())->getZExtValue();
2699 if (IsMemcpySmall(Len)) {
2700 X86AddressMode DestAM, SrcAM;
2701 if (!X86SelectAddress(V: MCI->getRawDest(), AM&: DestAM) ||
2702 !X86SelectAddress(V: MCI->getRawSource(), AM&: SrcAM))
2703 return false;
2704 TryEmitSmallMemcpy(DestAM, SrcAM, Len);
2705 return true;
2706 }
2707 }
2708
2709 unsigned SizeWidth = Subtarget->is64Bit() ? 64 : 32;
2710 if (!MCI->getLength()->getType()->isIntegerTy(Bitwidth: SizeWidth))
2711 return false;
2712
2713 if (MCI->getSourceAddressSpace() > 255 || MCI->getDestAddressSpace() > 255)
2714 return false;
2715
2716 return lowerCallTo(CI: II, SymName: "memcpy", NumArgs: II->arg_size() - 1);
2717 }
2718 case Intrinsic::memset: {
2719 const MemSetInst *MSI = cast<MemSetInst>(Val: II);
2720
2721 if (MSI->isVolatile())
2722 return false;
2723
2724 unsigned SizeWidth = Subtarget->is64Bit() ? 64 : 32;
2725 if (!MSI->getLength()->getType()->isIntegerTy(Bitwidth: SizeWidth))
2726 return false;
2727
2728 if (MSI->getDestAddressSpace() > 255)
2729 return false;
2730
2731 return lowerCallTo(CI: II, SymName: "memset", NumArgs: II->arg_size() - 1);
2732 }
2733 case Intrinsic::stackprotector: {
2734 // Emit code to store the stack guard onto the stack.
2735 EVT PtrTy = TLI.getPointerTy(DL);
2736
2737 const Value *Op1 = II->getArgOperand(i: 0); // The guard's value.
2738 const AllocaInst *Slot = cast<AllocaInst>(Val: II->getArgOperand(i: 1));
2739
2740 MFI.setStackProtectorIndex(FuncInfo.StaticAllocaMap[Slot]);
2741
2742 // Grab the frame index.
2743 X86AddressMode AM;
2744 if (!X86SelectAddress(V: Slot, AM)) return false;
2745 if (!X86FastEmitStore(VT: PtrTy, Val: Op1, AM)) return false;
2746 return true;
2747 }
2748 case Intrinsic::dbg_declare: {
2749 const DbgDeclareInst *DI = cast<DbgDeclareInst>(Val: II);
2750 X86AddressMode AM;
2751 assert(DI->getAddress() && "Null address should be checked earlier!");
2752 if (!X86SelectAddress(V: DI->getAddress(), AM))
2753 return false;
2754 const MCInstrDesc &II = TII.get(Opcode: TargetOpcode::DBG_VALUE);
2755 assert(DI->getVariable()->isValidLocationForIntrinsic(MIMD.getDL()) &&
2756 "Expected inlined-at fields to agree");
2757 addFullAddress(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: II), AM)
2758 .addImm(Val: 0)
2759 .addMetadata(MD: DI->getVariable())
2760 .addMetadata(MD: DI->getExpression());
2761 return true;
2762 }
2763 case Intrinsic::trap: {
2764 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: X86::TRAP));
2765 return true;
2766 }
2767 case Intrinsic::sqrt: {
2768 if (!Subtarget->hasSSE1())
2769 return false;
2770
2771 Type *RetTy = II->getCalledFunction()->getReturnType();
2772
2773 MVT VT;
2774 if (!isTypeLegal(Ty: RetTy, VT))
2775 return false;
2776
2777 // Unfortunately we can't use fastEmit_r, because the AVX version of FSQRT
2778 // is not generated by FastISel yet.
2779 // FIXME: Update this code once tablegen can handle it.
2780 static const uint16_t SqrtOpc[3][2] = {
2781 { X86::SQRTSSr, X86::SQRTSDr },
2782 { X86::VSQRTSSr, X86::VSQRTSDr },
2783 { X86::VSQRTSSZr, X86::VSQRTSDZr },
2784 };
2785 unsigned AVXLevel = Subtarget->hasAVX512() ? 2 :
2786 Subtarget->hasAVX() ? 1 :
2787 0;
2788 unsigned Opc;
2789 switch (VT.SimpleTy) {
2790 default: return false;
2791 case MVT::f32: Opc = SqrtOpc[AVXLevel][0]; break;
2792 case MVT::f64: Opc = SqrtOpc[AVXLevel][1]; break;
2793 }
2794
2795 const Value *SrcVal = II->getArgOperand(i: 0);
2796 Register SrcReg = getRegForValue(V: SrcVal);
2797
2798 if (!SrcReg)
2799 return false;
2800
2801 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
2802 Register ImplicitDefReg;
2803 if (AVXLevel > 0) {
2804 ImplicitDefReg = createResultReg(RC);
2805 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2806 MCID: TII.get(Opcode: TargetOpcode::IMPLICIT_DEF), DestReg: ImplicitDefReg);
2807 }
2808
2809 Register ResultReg = createResultReg(RC);
2810 MachineInstrBuilder MIB;
2811 MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc),
2812 DestReg: ResultReg);
2813
2814 if (ImplicitDefReg)
2815 MIB.addReg(RegNo: ImplicitDefReg);
2816
2817 MIB.addReg(RegNo: SrcReg);
2818
2819 updateValueMap(I: II, Reg: ResultReg);
2820 return true;
2821 }
2822 case Intrinsic::sadd_with_overflow:
2823 case Intrinsic::uadd_with_overflow:
2824 case Intrinsic::ssub_with_overflow:
2825 case Intrinsic::usub_with_overflow:
2826 case Intrinsic::smul_with_overflow:
2827 case Intrinsic::umul_with_overflow: {
2828 // This implements the basic lowering of the xalu with overflow intrinsics
2829 // into add/sub/mul followed by either seto or setb.
2830 const Function *Callee = II->getCalledFunction();
2831 auto *Ty = cast<StructType>(Val: Callee->getReturnType());
2832 Type *RetTy = Ty->getTypeAtIndex(N: 0U);
2833 assert(Ty->getTypeAtIndex(1)->isIntegerTy() &&
2834 Ty->getTypeAtIndex(1)->getScalarSizeInBits() == 1 &&
2835 "Overflow value expected to be an i1");
2836
2837 MVT VT;
2838 if (!isTypeLegal(Ty: RetTy, VT))
2839 return false;
2840
2841 if (VT < MVT::i8 || VT > MVT::i64)
2842 return false;
2843
2844 const Value *LHS = II->getArgOperand(i: 0);
2845 const Value *RHS = II->getArgOperand(i: 1);
2846
2847 // Canonicalize immediate to the RHS.
2848 if (isa<ConstantInt>(Val: LHS) && !isa<ConstantInt>(Val: RHS) && II->isCommutative())
2849 std::swap(a&: LHS, b&: RHS);
2850
2851 unsigned BaseOpc, CondCode;
2852 switch (II->getIntrinsicID()) {
2853 default: llvm_unreachable("Unexpected intrinsic!");
2854 case Intrinsic::sadd_with_overflow:
2855 BaseOpc = ISD::ADD; CondCode = X86::COND_O; break;
2856 case Intrinsic::uadd_with_overflow:
2857 BaseOpc = ISD::ADD; CondCode = X86::COND_B; break;
2858 case Intrinsic::ssub_with_overflow:
2859 BaseOpc = ISD::SUB; CondCode = X86::COND_O; break;
2860 case Intrinsic::usub_with_overflow:
2861 BaseOpc = ISD::SUB; CondCode = X86::COND_B; break;
2862 case Intrinsic::smul_with_overflow:
2863 BaseOpc = X86ISD::SMUL; CondCode = X86::COND_O; break;
2864 case Intrinsic::umul_with_overflow:
2865 BaseOpc = X86ISD::UMUL; CondCode = X86::COND_O; break;
2866 }
2867
2868 Register LHSReg = getRegForValue(V: LHS);
2869 if (!LHSReg)
2870 return false;
2871
2872 Register ResultReg;
2873 // Check if we have an immediate version.
2874 if (const auto *CI = dyn_cast<ConstantInt>(Val: RHS)) {
2875 static const uint16_t Opc[2][4] = {
2876 { X86::INC8r, X86::INC16r, X86::INC32r, X86::INC64r },
2877 { X86::DEC8r, X86::DEC16r, X86::DEC32r, X86::DEC64r }
2878 };
2879
2880 if (CI->isOne() && (BaseOpc == ISD::ADD || BaseOpc == ISD::SUB) &&
2881 CondCode == X86::COND_O) {
2882 // We can use INC/DEC.
2883 ResultReg = createResultReg(RC: TLI.getRegClassFor(VT));
2884 bool IsDec = BaseOpc == ISD::SUB;
2885 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2886 MCID: TII.get(Opcode: Opc[IsDec][VT.SimpleTy-MVT::i8]), DestReg: ResultReg)
2887 .addReg(RegNo: LHSReg);
2888 } else
2889 ResultReg = fastEmit_ri(VT, RetVT: VT, Opcode: BaseOpc, Op0: LHSReg, imm1: CI->getZExtValue());
2890 }
2891
2892 Register RHSReg;
2893 if (!ResultReg) {
2894 RHSReg = getRegForValue(V: RHS);
2895 if (!RHSReg)
2896 return false;
2897 ResultReg = fastEmit_rr(VT, RetVT: VT, Opcode: BaseOpc, Op0: LHSReg, Op1: RHSReg);
2898 }
2899
2900 // FastISel doesn't have a pattern for all X86::MUL*r and X86::IMUL*r. Emit
2901 // it manually.
2902 if (BaseOpc == X86ISD::UMUL && !ResultReg) {
2903 static const uint16_t MULOpc[] =
2904 { X86::MUL8r, X86::MUL16r, X86::MUL32r, X86::MUL64r };
2905 static const MCPhysReg Reg[] = { X86::AL, X86::AX, X86::EAX, X86::RAX };
2906 // First copy the first operand into RAX, which is an implicit input to
2907 // the X86::MUL*r instruction.
2908 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2909 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: Reg[VT.SimpleTy-MVT::i8])
2910 .addReg(RegNo: LHSReg);
2911 ResultReg = fastEmitInst_r(MachineInstOpcode: MULOpc[VT.SimpleTy-MVT::i8],
2912 RC: TLI.getRegClassFor(VT), Op0: RHSReg);
2913 } else if (BaseOpc == X86ISD::SMUL && !ResultReg) {
2914 static const uint16_t MULOpc[] =
2915 { X86::IMUL8r, X86::IMUL16rr, X86::IMUL32rr, X86::IMUL64rr };
2916 if (VT == MVT::i8) {
2917 // Copy the first operand into AL, which is an implicit input to the
2918 // X86::IMUL8r instruction.
2919 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
2920 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: X86::AL)
2921 .addReg(RegNo: LHSReg);
2922 ResultReg = fastEmitInst_r(MachineInstOpcode: MULOpc[0], RC: TLI.getRegClassFor(VT), Op0: RHSReg);
2923 } else
2924 ResultReg = fastEmitInst_rr(MachineInstOpcode: MULOpc[VT.SimpleTy-MVT::i8],
2925 RC: TLI.getRegClassFor(VT), Op0: LHSReg, Op1: RHSReg);
2926 }
2927
2928 if (!ResultReg)
2929 return false;
2930
2931 // Assign to a GPR since the overflow return value is lowered to a SETcc.
2932 Register ResultReg2 = createResultReg(RC: &X86::GR8RegClass);
2933 assert((ResultReg+1) == ResultReg2 && "Nonconsecutive result registers.");
2934 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(GET_SETCC),
2935 DestReg: ResultReg2)
2936 .addImm(Val: CondCode);
2937
2938 updateValueMap(I: II, Reg: ResultReg, NumRegs: 2);
2939 return true;
2940 }
2941 case Intrinsic::x86_sse_cvttss2si:
2942 case Intrinsic::x86_sse_cvttss2si64:
2943 case Intrinsic::x86_sse2_cvttsd2si:
2944 case Intrinsic::x86_sse2_cvttsd2si64: {
2945 bool IsInputDouble;
2946 switch (II->getIntrinsicID()) {
2947 default: llvm_unreachable("Unexpected intrinsic.");
2948 case Intrinsic::x86_sse_cvttss2si:
2949 case Intrinsic::x86_sse_cvttss2si64:
2950 if (!Subtarget->hasSSE1())
2951 return false;
2952 IsInputDouble = false;
2953 break;
2954 case Intrinsic::x86_sse2_cvttsd2si:
2955 case Intrinsic::x86_sse2_cvttsd2si64:
2956 if (!Subtarget->hasSSE2())
2957 return false;
2958 IsInputDouble = true;
2959 break;
2960 }
2961
2962 Type *RetTy = II->getCalledFunction()->getReturnType();
2963 MVT VT;
2964 if (!isTypeLegal(Ty: RetTy, VT))
2965 return false;
2966
2967 static const uint16_t CvtOpc[3][2][2] = {
2968 { { X86::CVTTSS2SIrr, X86::CVTTSS2SI64rr },
2969 { X86::CVTTSD2SIrr, X86::CVTTSD2SI64rr } },
2970 { { X86::VCVTTSS2SIrr, X86::VCVTTSS2SI64rr },
2971 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SI64rr } },
2972 { { X86::VCVTTSS2SIZrr, X86::VCVTTSS2SI64Zrr },
2973 { X86::VCVTTSD2SIZrr, X86::VCVTTSD2SI64Zrr } },
2974 };
2975 unsigned AVXLevel = Subtarget->hasAVX512() ? 2 :
2976 Subtarget->hasAVX() ? 1 :
2977 0;
2978 unsigned Opc;
2979 switch (VT.SimpleTy) {
2980 default: llvm_unreachable("Unexpected result type.");
2981 case MVT::i32: Opc = CvtOpc[AVXLevel][IsInputDouble][0]; break;
2982 case MVT::i64: Opc = CvtOpc[AVXLevel][IsInputDouble][1]; break;
2983 }
2984
2985 // Check if we can fold insertelement instructions into the convert.
2986 const Value *Op = II->getArgOperand(i: 0);
2987 while (auto *IE = dyn_cast<InsertElementInst>(Val: Op)) {
2988 const Value *Index = IE->getOperand(i_nocapture: 2);
2989 if (!isa<ConstantInt>(Val: Index))
2990 break;
2991 unsigned Idx = cast<ConstantInt>(Val: Index)->getZExtValue();
2992
2993 if (!Idx) {
2994 Op = IE->getOperand(i_nocapture: 1);
2995 break;
2996 }
2997 Op = IE->getOperand(i_nocapture: 0);
2998 }
2999
3000 Register Reg = getRegForValue(V: Op);
3001 if (!Reg)
3002 return false;
3003
3004 Register ResultReg = createResultReg(RC: TLI.getRegClassFor(VT));
3005 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc), DestReg: ResultReg)
3006 .addReg(RegNo: Reg);
3007
3008 updateValueMap(I: II, Reg: ResultReg);
3009 return true;
3010 }
3011 case Intrinsic::x86_sse42_crc32_32_8:
3012 case Intrinsic::x86_sse42_crc32_32_16:
3013 case Intrinsic::x86_sse42_crc32_32_32:
3014 case Intrinsic::x86_sse42_crc32_64_64: {
3015 if (!Subtarget->hasCRC32())
3016 return false;
3017
3018 Type *RetTy = II->getCalledFunction()->getReturnType();
3019
3020 MVT VT;
3021 if (!isTypeLegal(Ty: RetTy, VT))
3022 return false;
3023
3024 unsigned Opc;
3025 const TargetRegisterClass *RC = nullptr;
3026
3027 switch (II->getIntrinsicID()) {
3028 default:
3029 llvm_unreachable("Unexpected intrinsic.");
3030#define GET_EGPR_IF_ENABLED(OPC) Subtarget->hasEGPR() ? OPC##_EVEX : OPC
3031 case Intrinsic::x86_sse42_crc32_32_8:
3032 Opc = GET_EGPR_IF_ENABLED(X86::CRC32r32r8);
3033 RC = &X86::GR32RegClass;
3034 break;
3035 case Intrinsic::x86_sse42_crc32_32_16:
3036 Opc = GET_EGPR_IF_ENABLED(X86::CRC32r32r16);
3037 RC = &X86::GR32RegClass;
3038 break;
3039 case Intrinsic::x86_sse42_crc32_32_32:
3040 Opc = GET_EGPR_IF_ENABLED(X86::CRC32r32r32);
3041 RC = &X86::GR32RegClass;
3042 break;
3043 case Intrinsic::x86_sse42_crc32_64_64:
3044 Opc = GET_EGPR_IF_ENABLED(X86::CRC32r64r64);
3045 RC = &X86::GR64RegClass;
3046 break;
3047#undef GET_EGPR_IF_ENABLED
3048 }
3049
3050 const Value *LHS = II->getArgOperand(i: 0);
3051 const Value *RHS = II->getArgOperand(i: 1);
3052
3053 Register LHSReg = getRegForValue(V: LHS);
3054 Register RHSReg = getRegForValue(V: RHS);
3055 if (!LHSReg || !RHSReg)
3056 return false;
3057
3058 Register ResultReg = fastEmitInst_rr(MachineInstOpcode: Opc, RC, Op0: LHSReg, Op1: RHSReg);
3059 if (!ResultReg)
3060 return false;
3061
3062 updateValueMap(I: II, Reg: ResultReg);
3063 return true;
3064 }
3065 }
3066}
3067
3068bool X86FastISel::fastLowerArguments() {
3069 if (!FuncInfo.CanLowerReturn)
3070 return false;
3071
3072 const Function *F = FuncInfo.Fn;
3073 if (F->isVarArg())
3074 return false;
3075
3076 CallingConv::ID CC = F->getCallingConv();
3077 if (CC != CallingConv::C)
3078 return false;
3079
3080 if (Subtarget->isCallingConvWin64(CC))
3081 return false;
3082
3083 if (!Subtarget->is64Bit())
3084 return false;
3085
3086 if (Subtarget->useSoftFloat())
3087 return false;
3088
3089 // Only handle simple cases. i.e. Up to 6 i32/i64 scalar arguments.
3090 unsigned GPRCnt = 0;
3091 unsigned FPRCnt = 0;
3092 for (auto const &Arg : F->args()) {
3093 if (Arg.hasAttribute(Kind: Attribute::ByVal) ||
3094 Arg.hasAttribute(Kind: Attribute::InReg) ||
3095 Arg.hasAttribute(Kind: Attribute::StructRet) ||
3096 Arg.hasAttribute(Kind: Attribute::SwiftSelf) ||
3097 Arg.hasAttribute(Kind: Attribute::SwiftAsync) ||
3098 Arg.hasAttribute(Kind: Attribute::SwiftError) ||
3099 Arg.hasAttribute(Kind: Attribute::Nest))
3100 return false;
3101
3102 Type *ArgTy = Arg.getType();
3103 if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy())
3104 return false;
3105
3106 EVT ArgVT = TLI.getValueType(DL, Ty: ArgTy);
3107 if (!ArgVT.isSimple()) return false;
3108 switch (ArgVT.getSimpleVT().SimpleTy) {
3109 default: return false;
3110 case MVT::i32:
3111 case MVT::i64:
3112 ++GPRCnt;
3113 break;
3114 case MVT::f32:
3115 case MVT::f64:
3116 if (!Subtarget->hasSSE1())
3117 return false;
3118 ++FPRCnt;
3119 break;
3120 }
3121
3122 if (GPRCnt > 6)
3123 return false;
3124
3125 if (FPRCnt > 8)
3126 return false;
3127 }
3128
3129 static const MCPhysReg GPR32ArgRegs[] = {
3130 X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
3131 };
3132 static const MCPhysReg GPR64ArgRegs[] = {
3133 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8 , X86::R9
3134 };
3135 static const MCPhysReg XMMArgRegs[] = {
3136 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3137 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3138 };
3139
3140 unsigned GPRIdx = 0;
3141 unsigned FPRIdx = 0;
3142 for (auto const &Arg : F->args()) {
3143 MVT VT = TLI.getSimpleValueType(DL, Ty: Arg.getType());
3144 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
3145 MCRegister SrcReg;
3146 switch (VT.SimpleTy) {
3147 default: llvm_unreachable("Unexpected value type.");
3148 case MVT::i32: SrcReg = GPR32ArgRegs[GPRIdx++]; break;
3149 case MVT::i64: SrcReg = GPR64ArgRegs[GPRIdx++]; break;
3150 case MVT::f32: [[fallthrough]];
3151 case MVT::f64: SrcReg = XMMArgRegs[FPRIdx++]; break;
3152 }
3153 Register DstReg = FuncInfo.MF->addLiveIn(PReg: SrcReg, RC);
3154 // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
3155 // Without this, EmitLiveInCopies may eliminate the livein if its only
3156 // use is a bitcast (which isn't turned into an instruction).
3157 Register ResultReg = createResultReg(RC);
3158 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
3159 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: ResultReg)
3160 .addReg(RegNo: DstReg, Flags: getKillRegState(B: true));
3161 updateValueMap(I: &Arg, Reg: ResultReg);
3162 }
3163 return true;
3164}
3165
3166static unsigned computeBytesPoppedByCalleeForSRet(const X86Subtarget *Subtarget,
3167 CallingConv::ID CC,
3168 const CallBase *CB) {
3169 if (Subtarget->is64Bit())
3170 return 0;
3171 if (Subtarget->getTargetTriple().isOSMSVCRT())
3172 return 0;
3173 if (CC == CallingConv::Fast || CC == CallingConv::GHC ||
3174 CC == CallingConv::HiPE || CC == CallingConv::Tail ||
3175 CC == CallingConv::SwiftTail)
3176 return 0;
3177
3178 if (CB)
3179 if (CB->arg_empty() || !CB->paramHasAttr(ArgNo: 0, Kind: Attribute::StructRet) ||
3180 CB->paramHasAttr(ArgNo: 0, Kind: Attribute::InReg) || Subtarget->isTargetMCU())
3181 return 0;
3182
3183 return 4;
3184}
3185
3186bool X86FastISel::fastLowerCall(CallLoweringInfo &CLI) {
3187 auto &OutVals = CLI.OutVals;
3188 auto &OutFlags = CLI.OutFlags;
3189 auto &OutRegs = CLI.OutRegs;
3190 auto &Ins = CLI.Ins;
3191 auto &InRegs = CLI.InRegs;
3192 CallingConv::ID CC = CLI.CallConv;
3193 bool &IsTailCall = CLI.IsTailCall;
3194 bool IsVarArg = CLI.IsVarArg;
3195 const Value *Callee = CLI.Callee;
3196 MCSymbol *Symbol = CLI.Symbol;
3197 const auto *CB = CLI.CB;
3198
3199 bool Is64Bit = Subtarget->is64Bit();
3200 bool IsWin64 = Subtarget->isCallingConvWin64(CC);
3201
3202 // Call / invoke instructions with NoCfCheck attribute require special
3203 // handling.
3204 if (CB && CB->doesNoCfCheck())
3205 return false;
3206
3207 // Functions with no_caller_saved_registers that need special handling.
3208 if ((CB && isa<CallInst>(Val: CB) && CB->hasFnAttr(Kind: "no_caller_saved_registers")))
3209 return false;
3210
3211 // Functions with no_callee_saved_registers that need special handling.
3212 if ((CB && CB->hasFnAttr(Kind: "no_callee_saved_registers")))
3213 return false;
3214
3215 // Indirect calls with CFI checks need special handling.
3216 if (CB && CB->isIndirectCall() && CB->getOperandBundle(ID: LLVMContext::OB_kcfi))
3217 return false;
3218
3219 // Functions using thunks for indirect calls need to use SDISel.
3220 if (Subtarget->useIndirectThunkCalls())
3221 return false;
3222
3223 // Handle only C and fastcc calling conventions for now.
3224 switch (CC) {
3225 default: return false;
3226 case CallingConv::C:
3227 case CallingConv::Fast:
3228 case CallingConv::Tail:
3229 case CallingConv::Swift:
3230 case CallingConv::SwiftTail:
3231 case CallingConv::X86_FastCall:
3232 case CallingConv::X86_StdCall:
3233 case CallingConv::X86_ThisCall:
3234 case CallingConv::Win64:
3235 case CallingConv::X86_64_SysV:
3236 case CallingConv::CFGuard_Check:
3237 break;
3238 }
3239
3240 // Allow SelectionDAG isel to handle tail calls.
3241 if (IsTailCall)
3242 return false;
3243
3244 // fastcc with -tailcallopt is intended to provide a guaranteed
3245 // tail call optimization. Fastisel doesn't know how to do that.
3246 if ((CC == CallingConv::Fast && TM.Options.GuaranteedTailCallOpt) ||
3247 CC == CallingConv::Tail || CC == CallingConv::SwiftTail)
3248 return false;
3249
3250 // Don't know how to handle Win64 varargs yet. Nothing special needed for
3251 // x86-32. Special handling for x86-64 is implemented.
3252 if (IsVarArg && IsWin64)
3253 return false;
3254
3255 // Don't know about inalloca yet.
3256 if (CLI.CB && CLI.CB->hasInAllocaArgument())
3257 return false;
3258
3259 for (auto Flag : CLI.OutFlags)
3260 if (Flag.isSwiftError() || Flag.isPreallocated())
3261 return false;
3262
3263 // Can't handle import call optimization.
3264 if (Is64Bit &&
3265 MF->getFunction().getParent()->getModuleFlag(Key: "import-call-optimization"))
3266 return false;
3267
3268 SmallVector<MVT, 16> OutVTs;
3269 SmallVector<Type *, 16> ArgTys;
3270 SmallVector<Register, 16> ArgRegs;
3271
3272 // If this is a constant i1/i8/i16 argument, promote to i32 to avoid an extra
3273 // instruction. This is safe because it is common to all FastISel supported
3274 // calling conventions on x86.
3275 for (int i = 0, e = OutVals.size(); i != e; ++i) {
3276 Value *&Val = OutVals[i];
3277 ISD::ArgFlagsTy Flags = OutFlags[i];
3278 if (auto *CI = dyn_cast<ConstantInt>(Val)) {
3279 if (CI->getBitWidth() < 32) {
3280 if (Flags.isSExt())
3281 Val = ConstantInt::get(Context&: CI->getContext(), V: CI->getValue().sext(width: 32));
3282 else
3283 Val = ConstantInt::get(Context&: CI->getContext(), V: CI->getValue().zext(width: 32));
3284 }
3285 }
3286
3287 // Passing bools around ends up doing a trunc to i1 and passing it.
3288 // Codegen this as an argument + "and 1".
3289 MVT VT;
3290 auto *TI = dyn_cast<TruncInst>(Val);
3291 Register ResultReg;
3292 if (TI && TI->getType()->isIntegerTy(Bitwidth: 1) && CLI.CB &&
3293 (TI->getParent() == CLI.CB->getParent()) && TI->hasOneUse()) {
3294 Value *PrevVal = TI->getOperand(i_nocapture: 0);
3295 ResultReg = getRegForValue(V: PrevVal);
3296
3297 if (!ResultReg)
3298 return false;
3299
3300 if (!isTypeLegal(Ty: PrevVal->getType(), VT))
3301 return false;
3302
3303 ResultReg = fastEmit_ri(VT, RetVT: VT, Opcode: ISD::AND, Op0: ResultReg, imm1: 1);
3304 } else {
3305 if (!isTypeLegal(Ty: Val->getType(), VT) ||
3306 (VT.isVector() && VT.getVectorElementType() == MVT::i1))
3307 return false;
3308 ResultReg = getRegForValue(V: Val);
3309 }
3310
3311 if (!ResultReg)
3312 return false;
3313
3314 ArgRegs.push_back(Elt: ResultReg);
3315 OutVTs.push_back(Elt: VT);
3316 ArgTys.push_back(Elt: Val->getType());
3317 }
3318
3319 // Analyze operands of the call, assigning locations to each operand.
3320 SmallVector<CCValAssign, 16> ArgLocs;
3321 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, ArgLocs, CLI.RetTy->getContext());
3322
3323 // Allocate shadow area for Win64
3324 if (IsWin64)
3325 CCInfo.AllocateStack(Size: 32, Alignment: Align(8));
3326
3327 CCInfo.AnalyzeCallOperands(ArgVTs&: OutVTs, Flags&: OutFlags, OrigTys&: ArgTys, Fn: CC_X86);
3328
3329 // Get a count of how many bytes are to be pushed on the stack.
3330 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
3331
3332 // Issue CALLSEQ_START
3333 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
3334 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: AdjStackDown))
3335 .addImm(Val: NumBytes).addImm(Val: 0).addImm(Val: 0);
3336
3337 // Walk the register/memloc assignments, inserting copies/loads.
3338 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3339 for (const CCValAssign &VA : ArgLocs) {
3340 const Value *ArgVal = OutVals[VA.getValNo()];
3341 MVT ArgVT = OutVTs[VA.getValNo()];
3342
3343 if (ArgVT == MVT::x86mmx)
3344 return false;
3345
3346 Register ArgReg = ArgRegs[VA.getValNo()];
3347
3348 // Promote the value if needed.
3349 switch (VA.getLocInfo()) {
3350 case CCValAssign::Full: break;
3351 case CCValAssign::SExt: {
3352 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() &&
3353 "Unexpected extend");
3354
3355 if (ArgVT == MVT::i1)
3356 return false;
3357
3358 bool Emitted = X86FastEmitExtend(Opc: ISD::SIGN_EXTEND, DstVT: VA.getLocVT(), Src: ArgReg,
3359 SrcVT: ArgVT, ResultReg&: ArgReg);
3360 assert(Emitted && "Failed to emit a sext!"); (void)Emitted;
3361 ArgVT = VA.getLocVT();
3362 break;
3363 }
3364 case CCValAssign::ZExt: {
3365 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() &&
3366 "Unexpected extend");
3367
3368 // Handle zero-extension from i1 to i8, which is common.
3369 if (ArgVT == MVT::i1) {
3370 // Set the high bits to zero.
3371 ArgReg = fastEmitZExtFromI1(VT: MVT::i8, Op0: ArgReg);
3372 ArgVT = MVT::i8;
3373
3374 if (!ArgReg)
3375 return false;
3376 }
3377
3378 bool Emitted = X86FastEmitExtend(Opc: ISD::ZERO_EXTEND, DstVT: VA.getLocVT(), Src: ArgReg,
3379 SrcVT: ArgVT, ResultReg&: ArgReg);
3380 assert(Emitted && "Failed to emit a zext!"); (void)Emitted;
3381 ArgVT = VA.getLocVT();
3382 break;
3383 }
3384 case CCValAssign::AExt: {
3385 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() &&
3386 "Unexpected extend");
3387 bool Emitted = X86FastEmitExtend(Opc: ISD::ANY_EXTEND, DstVT: VA.getLocVT(), Src: ArgReg,
3388 SrcVT: ArgVT, ResultReg&: ArgReg);
3389 if (!Emitted)
3390 Emitted = X86FastEmitExtend(Opc: ISD::ZERO_EXTEND, DstVT: VA.getLocVT(), Src: ArgReg,
3391 SrcVT: ArgVT, ResultReg&: ArgReg);
3392 if (!Emitted)
3393 Emitted = X86FastEmitExtend(Opc: ISD::SIGN_EXTEND, DstVT: VA.getLocVT(), Src: ArgReg,
3394 SrcVT: ArgVT, ResultReg&: ArgReg);
3395
3396 assert(Emitted && "Failed to emit a aext!"); (void)Emitted;
3397 ArgVT = VA.getLocVT();
3398 break;
3399 }
3400 case CCValAssign::BCvt: {
3401 ArgReg = fastEmit_r(VT: ArgVT, RetVT: VA.getLocVT(), Opcode: ISD::BITCAST, Op0: ArgReg);
3402 assert(ArgReg && "Failed to emit a bitcast!");
3403 ArgVT = VA.getLocVT();
3404 break;
3405 }
3406 case CCValAssign::VExt:
3407 // VExt has not been implemented, so this should be impossible to reach
3408 // for now. However, fallback to Selection DAG isel once implemented.
3409 return false;
3410 case CCValAssign::AExtUpper:
3411 case CCValAssign::SExtUpper:
3412 case CCValAssign::ZExtUpper:
3413 case CCValAssign::FPExt:
3414 case CCValAssign::Trunc:
3415 llvm_unreachable("Unexpected loc info!");
3416 case CCValAssign::Indirect:
3417 // FIXME: Indirect doesn't need extending, but fast-isel doesn't fully
3418 // support this.
3419 return false;
3420 }
3421
3422 if (VA.isRegLoc()) {
3423 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
3424 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: VA.getLocReg()).addReg(RegNo: ArgReg);
3425 OutRegs.push_back(Elt: VA.getLocReg());
3426 } else {
3427 assert(VA.isMemLoc() && "Unknown value location!");
3428
3429 // Don't emit stores for undef values.
3430 if (isa<UndefValue>(Val: ArgVal))
3431 continue;
3432
3433 unsigned LocMemOffset = VA.getLocMemOffset();
3434 X86AddressMode AM;
3435 AM.Base.Reg = RegInfo->getStackRegister();
3436 AM.Disp = LocMemOffset;
3437 ISD::ArgFlagsTy Flags = OutFlags[VA.getValNo()];
3438 Align Alignment = DL.getABITypeAlign(Ty: ArgVal->getType());
3439 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
3440 PtrInfo: MachinePointerInfo::getStack(MF&: *FuncInfo.MF, Offset: LocMemOffset),
3441 F: MachineMemOperand::MOStore, Size: ArgVT.getStoreSize(), BaseAlignment: Alignment);
3442 if (Flags.isByVal()) {
3443 X86AddressMode SrcAM;
3444 SrcAM.Base.Reg = ArgReg;
3445 if (!TryEmitSmallMemcpy(DestAM: AM, SrcAM, Len: Flags.getByValSize()))
3446 return false;
3447 } else if (isa<ConstantInt>(Val: ArgVal) || isa<ConstantPointerNull>(Val: ArgVal)) {
3448 // If this is a really simple value, emit this with the Value* version
3449 // of X86FastEmitStore. If it isn't simple, we don't want to do this,
3450 // as it can cause us to reevaluate the argument.
3451 if (!X86FastEmitStore(VT: ArgVT, Val: ArgVal, AM, MMO))
3452 return false;
3453 } else {
3454 if (!X86FastEmitStore(VT: ArgVT, ValReg: ArgReg, AM, MMO))
3455 return false;
3456 }
3457 }
3458 }
3459
3460 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3461 // GOT pointer.
3462 if (Subtarget->isPICStyleGOT()) {
3463 Register Base = getInstrInfo()->getGlobalBaseReg(MF: FuncInfo.MF);
3464 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
3465 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: X86::EBX).addReg(RegNo: Base);
3466 }
3467
3468 if (Is64Bit && IsVarArg && !IsWin64) {
3469 // From AMD64 ABI document:
3470 // For calls that may call functions that use varargs or stdargs
3471 // (prototype-less calls or calls to functions containing ellipsis (...) in
3472 // the declaration) %al is used as hidden argument to specify the number
3473 // of SSE registers used. The contents of %al do not need to match exactly
3474 // the number of registers, but must be an ubound on the number of SSE
3475 // registers used and is in the range 0 - 8 inclusive.
3476
3477 // Count the number of XMM registers allocated.
3478 static const MCPhysReg XMMArgRegs[] = {
3479 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3480 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3481 };
3482 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(Regs: XMMArgRegs);
3483 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3484 && "SSE registers cannot be used when SSE is disabled");
3485 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: X86::MOV8ri),
3486 DestReg: X86::AL).addImm(Val: NumXMMRegs);
3487 }
3488
3489 // Materialize callee address in a register. FIXME: GV address can be
3490 // handled with a CALLpcrel32 instead.
3491 X86AddressMode CalleeAM;
3492 if (!X86SelectCallAddress(V: Callee, AM&: CalleeAM))
3493 return false;
3494
3495 Register CalleeOp;
3496 const GlobalValue *GV = nullptr;
3497 if (CalleeAM.GV != nullptr) {
3498 GV = CalleeAM.GV;
3499 } else if (CalleeAM.Base.Reg) {
3500 CalleeOp = CalleeAM.Base.Reg;
3501 } else
3502 return false;
3503
3504 // Issue the call.
3505 MachineInstrBuilder MIB;
3506 if (CalleeOp) {
3507 // Register-indirect call.
3508 unsigned CallOpc = Is64Bit ? X86::CALL64r : X86::CALL32r;
3509 MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: CallOpc))
3510 .addReg(RegNo: CalleeOp);
3511 } else {
3512 // Direct call.
3513 assert(GV && "Not a direct call");
3514 // See if we need any target-specific flags on the GV operand.
3515 unsigned char OpFlags = Subtarget->classifyGlobalFunctionReference(GV);
3516 if (OpFlags == X86II::MO_PLT && !Is64Bit &&
3517 TM.getRelocationModel() == Reloc::Static && isa<Function>(Val: GV) &&
3518 cast<Function>(Val: GV)->isIntrinsic())
3519 OpFlags = X86II::MO_NO_FLAG;
3520
3521 // This will be a direct call, or an indirect call through memory for
3522 // NonLazyBind calls or dllimport calls.
3523 bool NeedLoad = OpFlags == X86II::MO_DLLIMPORT ||
3524 OpFlags == X86II::MO_GOTPCREL ||
3525 OpFlags == X86II::MO_GOTPCREL_NORELAX ||
3526 OpFlags == X86II::MO_COFFSTUB;
3527 unsigned CallOpc = NeedLoad
3528 ? (Is64Bit ? X86::CALL64m : X86::CALL32m)
3529 : (Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32);
3530
3531 MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: CallOpc));
3532 if (NeedLoad)
3533 MIB.addReg(RegNo: Is64Bit ? X86::RIP : X86::NoRegister).addImm(Val: 1).addReg(RegNo: 0);
3534 if (Symbol)
3535 MIB.addSym(Sym: Symbol, TargetFlags: OpFlags);
3536 else
3537 MIB.addGlobalAddress(GV, Offset: 0, TargetFlags: OpFlags);
3538 if (NeedLoad)
3539 MIB.addReg(RegNo: 0);
3540 }
3541
3542 // Add a register mask operand representing the call-preserved registers.
3543 // Proper defs for return values will be added by setPhysRegsDeadExcept().
3544 MIB.addRegMask(Mask: TRI.getCallPreservedMask(MF: *FuncInfo.MF, CC));
3545
3546 // Add an implicit use GOT pointer in EBX.
3547 if (Subtarget->isPICStyleGOT())
3548 MIB.addReg(RegNo: X86::EBX, Flags: RegState::Implicit);
3549
3550 if (Is64Bit && IsVarArg && !IsWin64)
3551 MIB.addReg(RegNo: X86::AL, Flags: RegState::Implicit);
3552
3553 // Add implicit physical register uses to the call.
3554 for (auto Reg : OutRegs)
3555 MIB.addReg(RegNo: Reg, Flags: RegState::Implicit);
3556
3557 // Issue CALLSEQ_END
3558 unsigned NumBytesForCalleeToPop =
3559 X86::isCalleePop(CallingConv: CC, is64Bit: Subtarget->is64Bit(), IsVarArg,
3560 GuaranteeTCO: TM.Options.GuaranteedTailCallOpt)
3561 ? NumBytes // Callee pops everything.
3562 : computeBytesPoppedByCalleeForSRet(Subtarget, CC, CB: CLI.CB);
3563 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
3564 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: AdjStackUp))
3565 .addImm(Val: NumBytes).addImm(Val: NumBytesForCalleeToPop);
3566
3567 // Now handle call return values.
3568 SmallVector<CCValAssign, 16> RVLocs;
3569 CCState CCRetInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs,
3570 CLI.RetTy->getContext());
3571 CCRetInfo.AnalyzeCallResult(Ins, Fn: RetCC_X86);
3572
3573 // Copy all of the result registers out of their specified physreg.
3574 Register ResultReg = FuncInfo.CreateRegs(Ty: CLI.RetTy);
3575 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3576 CCValAssign &VA = RVLocs[i];
3577 EVT CopyVT = VA.getValVT();
3578 Register CopyReg = ResultReg + i;
3579 Register SrcReg = VA.getLocReg();
3580
3581 // If this is x86-64, and we disabled SSE, we can't return FP values
3582 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
3583 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
3584 report_fatal_error(reason: "SSE register return with SSE disabled");
3585 }
3586
3587 // If we prefer to use the value in xmm registers, copy it out as f80 and
3588 // use a truncate to move it from fp stack reg to xmm reg.
3589 if ((SrcReg == X86::FP0 || SrcReg == X86::FP1) &&
3590 isScalarFPTypeInSSEReg(VT: VA.getValVT())) {
3591 CopyVT = MVT::f80;
3592 CopyReg = createResultReg(RC: &X86::RFP80RegClass);
3593 }
3594
3595 // Copy out the result.
3596 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
3597 MCID: TII.get(Opcode: TargetOpcode::COPY), DestReg: CopyReg).addReg(RegNo: SrcReg);
3598 InRegs.push_back(Elt: VA.getLocReg());
3599
3600 // Round the f80 to the right size, which also moves it to the appropriate
3601 // xmm register. This is accomplished by storing the f80 value in memory
3602 // and then loading it back.
3603 if (CopyVT != VA.getValVT()) {
3604 EVT ResVT = VA.getValVT();
3605 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
3606 unsigned MemSize = ResVT.getSizeInBits()/8;
3607 int FI = MFI.CreateStackObject(Size: MemSize, Alignment: Align(MemSize), isSpillSlot: false);
3608 addFrameReference(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
3609 MCID: TII.get(Opcode: Opc)), FI)
3610 .addReg(RegNo: CopyReg);
3611 Opc = ResVT == MVT::f32 ? X86::MOVSSrm_alt : X86::MOVSDrm_alt;
3612 addFrameReference(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
3613 MCID: TII.get(Opcode: Opc), DestReg: ResultReg + i), FI);
3614 }
3615 }
3616
3617 CLI.ResultReg = ResultReg;
3618 CLI.NumResultRegs = RVLocs.size();
3619 CLI.Call = MIB;
3620
3621 // Add call site info for call graph section.
3622 if (TM.Options.EmitCallGraphSection && CB && CB->isIndirectCall()) {
3623 MachineFunction::CallSiteInfo CSInfo(*CB);
3624 MF->addCallSiteInfo(CallI: CLI.Call, CallInfo: std::move(CSInfo));
3625 }
3626
3627 return true;
3628}
3629
3630bool
3631X86FastISel::fastSelectInstruction(const Instruction *I) {
3632 switch (I->getOpcode()) {
3633 default: break;
3634 case Instruction::Load:
3635 return X86SelectLoad(I);
3636 case Instruction::Store:
3637 return X86SelectStore(I);
3638 case Instruction::Ret:
3639 return X86SelectRet(I);
3640 case Instruction::ICmp:
3641 case Instruction::FCmp:
3642 return X86SelectCmp(I);
3643 case Instruction::ZExt:
3644 return X86SelectZExt(I);
3645 case Instruction::SExt:
3646 return X86SelectSExt(I);
3647 case Instruction::Br:
3648 return X86SelectBranch(I);
3649 case Instruction::LShr:
3650 case Instruction::AShr:
3651 case Instruction::Shl:
3652 return X86SelectShift(I);
3653 case Instruction::SDiv:
3654 case Instruction::UDiv:
3655 case Instruction::SRem:
3656 case Instruction::URem:
3657 return X86SelectDivRem(I);
3658 case Instruction::Select:
3659 return X86SelectSelect(I);
3660 case Instruction::Trunc:
3661 return X86SelectTrunc(I);
3662 case Instruction::FPExt:
3663 return X86SelectFPExt(I);
3664 case Instruction::FPTrunc:
3665 return X86SelectFPTrunc(I);
3666 case Instruction::SIToFP:
3667 return X86SelectSIToFP(I);
3668 case Instruction::UIToFP:
3669 return X86SelectUIToFP(I);
3670 case Instruction::IntToPtr: // Deliberate fall-through.
3671 case Instruction::PtrToInt: {
3672 EVT SrcVT = TLI.getValueType(DL, Ty: I->getOperand(i: 0)->getType());
3673 EVT DstVT = TLI.getValueType(DL, Ty: I->getType());
3674 if (DstVT.bitsGT(VT: SrcVT))
3675 return X86SelectZExt(I);
3676 if (DstVT.bitsLT(VT: SrcVT))
3677 return X86SelectTrunc(I);
3678 Register Reg = getRegForValue(V: I->getOperand(i: 0));
3679 if (!Reg)
3680 return false;
3681 updateValueMap(I, Reg);
3682 return true;
3683 }
3684 case Instruction::BitCast:
3685 return X86SelectBitCast(I);
3686 }
3687
3688 return false;
3689}
3690
3691Register X86FastISel::X86MaterializeInt(const ConstantInt *CI, MVT VT) {
3692 if (VT > MVT::i64)
3693 return Register();
3694
3695 uint64_t Imm = CI->getZExtValue();
3696 if (Imm == 0) {
3697 Register SrcReg = fastEmitInst_(MachineInstOpcode: X86::MOV32r0, RC: &X86::GR32RegClass);
3698 switch (VT.SimpleTy) {
3699 default: llvm_unreachable("Unexpected value type");
3700 case MVT::i1:
3701 case MVT::i8:
3702 return fastEmitInst_extractsubreg(RetVT: MVT::i8, Op0: SrcReg, Idx: X86::sub_8bit);
3703 case MVT::i16:
3704 return fastEmitInst_extractsubreg(RetVT: MVT::i16, Op0: SrcReg, Idx: X86::sub_16bit);
3705 case MVT::i32:
3706 return SrcReg;
3707 case MVT::i64: {
3708 Register ResultReg = createResultReg(RC: &X86::GR64RegClass);
3709 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
3710 MCID: TII.get(Opcode: TargetOpcode::SUBREG_TO_REG), DestReg: ResultReg)
3711 .addImm(Val: 0).addReg(RegNo: SrcReg).addImm(Val: X86::sub_32bit);
3712 return ResultReg;
3713 }
3714 }
3715 }
3716
3717 unsigned Opc = 0;
3718 switch (VT.SimpleTy) {
3719 default: llvm_unreachable("Unexpected value type");
3720 case MVT::i1:
3721 VT = MVT::i8;
3722 [[fallthrough]];
3723 case MVT::i8: Opc = X86::MOV8ri; break;
3724 case MVT::i16: Opc = X86::MOV16ri; break;
3725 case MVT::i32: Opc = X86::MOV32ri; break;
3726 case MVT::i64: {
3727 if (isUInt<32>(x: Imm))
3728 Opc = X86::MOV32ri64;
3729 else if (isInt<32>(x: Imm))
3730 Opc = X86::MOV64ri32;
3731 else
3732 Opc = X86::MOV64ri;
3733 break;
3734 }
3735 }
3736 return fastEmitInst_i(MachineInstOpcode: Opc, RC: TLI.getRegClassFor(VT), Imm);
3737}
3738
3739Register X86FastISel::X86MaterializeFP(const ConstantFP *CFP, MVT VT) {
3740 if (CFP->isNullValue())
3741 return fastMaterializeFloatZero(CF: CFP);
3742
3743 // Can't handle alternate code models yet.
3744 CodeModel::Model CM = TM.getCodeModel();
3745 if (CM != CodeModel::Small && CM != CodeModel::Medium &&
3746 CM != CodeModel::Large)
3747 return Register();
3748
3749 // Get opcode and regclass of the output for the given load instruction.
3750 unsigned Opc = 0;
3751 bool HasSSE1 = Subtarget->hasSSE1();
3752 bool HasSSE2 = Subtarget->hasSSE2();
3753 bool HasAVX = Subtarget->hasAVX();
3754 bool HasAVX512 = Subtarget->hasAVX512();
3755 switch (VT.SimpleTy) {
3756 default:
3757 return Register();
3758 case MVT::f32:
3759 Opc = HasAVX512 ? X86::VMOVSSZrm_alt
3760 : HasAVX ? X86::VMOVSSrm_alt
3761 : HasSSE1 ? X86::MOVSSrm_alt
3762 : X86::LD_Fp32m;
3763 break;
3764 case MVT::f64:
3765 Opc = HasAVX512 ? X86::VMOVSDZrm_alt
3766 : HasAVX ? X86::VMOVSDrm_alt
3767 : HasSSE2 ? X86::MOVSDrm_alt
3768 : X86::LD_Fp64m;
3769 break;
3770 case MVT::f80:
3771 // No f80 support yet.
3772 return Register();
3773 }
3774
3775 // MachineConstantPool wants an explicit alignment.
3776 Align Alignment = DL.getPrefTypeAlign(Ty: CFP->getType());
3777
3778 // x86-32 PIC requires a PIC base register for constant pools.
3779 Register PICBase;
3780 unsigned char OpFlag = Subtarget->classifyLocalReference(GV: nullptr);
3781 if (OpFlag == X86II::MO_PIC_BASE_OFFSET)
3782 PICBase = getInstrInfo()->getGlobalBaseReg(MF: FuncInfo.MF);
3783 else if (OpFlag == X86II::MO_GOTOFF)
3784 PICBase = getInstrInfo()->getGlobalBaseReg(MF: FuncInfo.MF);
3785 else if (Subtarget->is64Bit() && TM.getCodeModel() != CodeModel::Large)
3786 PICBase = X86::RIP;
3787
3788 // Create the load from the constant pool.
3789 unsigned CPI = MCP.getConstantPoolIndex(C: CFP, Alignment);
3790 Register ResultReg = createResultReg(RC: TLI.getRegClassFor(VT: VT.SimpleTy));
3791
3792 // Large code model only applies to 64-bit mode.
3793 if (Subtarget->is64Bit() && CM == CodeModel::Large) {
3794 Register AddrReg = createResultReg(RC: &X86::GR64RegClass);
3795 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: X86::MOV64ri),
3796 DestReg: AddrReg)
3797 .addConstantPoolIndex(Idx: CPI, Offset: 0, TargetFlags: OpFlag);
3798 MachineInstrBuilder MIB = BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
3799 MCID: TII.get(Opcode: Opc), DestReg: ResultReg);
3800 addRegReg(MIB, Reg1: AddrReg, isKill1: false, SubReg1: X86::NoSubRegister, Reg2: PICBase, isKill2: false,
3801 SubReg2: X86::NoSubRegister);
3802 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
3803 PtrInfo: MachinePointerInfo::getConstantPool(MF&: *FuncInfo.MF),
3804 F: MachineMemOperand::MOLoad, Size: DL.getPointerSize(), BaseAlignment: Alignment);
3805 MIB->addMemOperand(MF&: *FuncInfo.MF, MO: MMO);
3806 return ResultReg;
3807 }
3808
3809 addConstantPoolReference(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
3810 MCID: TII.get(Opcode: Opc), DestReg: ResultReg),
3811 CPI, GlobalBaseReg: PICBase, OpFlags: OpFlag);
3812 return ResultReg;
3813}
3814
3815Register X86FastISel::X86MaterializeGV(const GlobalValue *GV, MVT VT) {
3816 // Can't handle large GlobalValues yet.
3817 if (TM.getCodeModel() != CodeModel::Small &&
3818 TM.getCodeModel() != CodeModel::Medium)
3819 return Register();
3820 if (TM.isLargeGlobalValue(GV))
3821 return Register();
3822
3823 // Materialize addresses with LEA/MOV instructions.
3824 X86AddressMode AM;
3825 if (X86SelectAddress(V: GV, AM)) {
3826 // If the expression is just a basereg, then we're done, otherwise we need
3827 // to emit an LEA.
3828 if (AM.BaseType == X86AddressMode::RegBase &&
3829 AM.IndexReg == 0 && AM.Disp == 0 && AM.GV == nullptr)
3830 return AM.Base.Reg;
3831
3832 Register ResultReg = createResultReg(RC: TLI.getRegClassFor(VT));
3833 if (TM.getRelocationModel() == Reloc::Static &&
3834 TLI.getPointerTy(DL) == MVT::i64) {
3835 // The displacement code could be more than 32 bits away so we need to use
3836 // an instruction with a 64 bit immediate
3837 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: X86::MOV64ri),
3838 DestReg: ResultReg)
3839 .addGlobalAddress(GV);
3840 } else {
3841 unsigned Opc =
3842 TLI.getPointerTy(DL) == MVT::i32
3843 ? (Subtarget->isTarget64BitILP32() ? X86::LEA64_32r : X86::LEA32r)
3844 : X86::LEA64r;
3845 addFullAddress(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
3846 MCID: TII.get(Opcode: Opc), DestReg: ResultReg), AM);
3847 }
3848 return ResultReg;
3849 }
3850 return Register();
3851}
3852
3853Register X86FastISel::fastMaterializeConstant(const Constant *C) {
3854 EVT CEVT = TLI.getValueType(DL, Ty: C->getType(), AllowUnknown: true);
3855
3856 // Only handle simple types.
3857 if (!CEVT.isSimple())
3858 return Register();
3859 MVT VT = CEVT.getSimpleVT();
3860
3861 if (const auto *CI = dyn_cast<ConstantInt>(Val: C))
3862 return X86MaterializeInt(CI, VT);
3863 if (const auto *CFP = dyn_cast<ConstantFP>(Val: C))
3864 return X86MaterializeFP(CFP, VT);
3865 if (const auto *GV = dyn_cast<GlobalValue>(Val: C))
3866 return X86MaterializeGV(GV, VT);
3867 if (isa<UndefValue>(Val: C)) {
3868 unsigned Opc = 0;
3869 switch (VT.SimpleTy) {
3870 default:
3871 break;
3872 case MVT::f32:
3873 if (!Subtarget->hasSSE1())
3874 Opc = X86::LD_Fp032;
3875 break;
3876 case MVT::f64:
3877 if (!Subtarget->hasSSE2())
3878 Opc = X86::LD_Fp064;
3879 break;
3880 case MVT::f80:
3881 Opc = X86::LD_Fp080;
3882 break;
3883 }
3884
3885 if (Opc) {
3886 Register ResultReg = createResultReg(RC: TLI.getRegClassFor(VT));
3887 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc),
3888 DestReg: ResultReg);
3889 return ResultReg;
3890 }
3891 }
3892
3893 return Register();
3894}
3895
3896Register X86FastISel::fastMaterializeAlloca(const AllocaInst *C) {
3897 // Fail on dynamic allocas. At this point, getRegForValue has already
3898 // checked its CSE maps, so if we're here trying to handle a dynamic
3899 // alloca, we're not going to succeed. X86SelectAddress has a
3900 // check for dynamic allocas, because it's called directly from
3901 // various places, but targetMaterializeAlloca also needs a check
3902 // in order to avoid recursion between getRegForValue,
3903 // X86SelectAddrss, and targetMaterializeAlloca.
3904 if (!FuncInfo.StaticAllocaMap.count(Val: C))
3905 return Register();
3906 assert(C->isStaticAlloca() && "dynamic alloca in the static alloca map?");
3907
3908 X86AddressMode AM;
3909 if (!X86SelectAddress(V: C, AM))
3910 return Register();
3911 unsigned Opc =
3912 TLI.getPointerTy(DL) == MVT::i32
3913 ? (Subtarget->isTarget64BitILP32() ? X86::LEA64_32r : X86::LEA32r)
3914 : X86::LEA64r;
3915 const TargetRegisterClass *RC = TLI.getRegClassFor(VT: TLI.getPointerTy(DL));
3916 Register ResultReg = createResultReg(RC);
3917 addFullAddress(MIB: BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD,
3918 MCID: TII.get(Opcode: Opc), DestReg: ResultReg), AM);
3919 return ResultReg;
3920}
3921
3922Register X86FastISel::fastMaterializeFloatZero(const ConstantFP *CF) {
3923 MVT VT;
3924 if (!isTypeLegal(Ty: CF->getType(), VT))
3925 return Register();
3926
3927 // Get opcode and regclass for the given zero.
3928 bool HasSSE1 = Subtarget->hasSSE1();
3929 bool HasSSE2 = Subtarget->hasSSE2();
3930 bool HasAVX512 = Subtarget->hasAVX512();
3931 unsigned Opc = 0;
3932 switch (VT.SimpleTy) {
3933 default: return 0;
3934 case MVT::f16:
3935 Opc = HasAVX512 ? X86::AVX512_FsFLD0SH : X86::FsFLD0SH;
3936 break;
3937 case MVT::f32:
3938 Opc = HasAVX512 ? X86::AVX512_FsFLD0SS
3939 : HasSSE1 ? X86::FsFLD0SS
3940 : X86::LD_Fp032;
3941 break;
3942 case MVT::f64:
3943 Opc = HasAVX512 ? X86::AVX512_FsFLD0SD
3944 : HasSSE2 ? X86::FsFLD0SD
3945 : X86::LD_Fp064;
3946 break;
3947 case MVT::f80:
3948 // No f80 support yet.
3949 return Register();
3950 }
3951
3952 Register ResultReg = createResultReg(RC: TLI.getRegClassFor(VT));
3953 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: Opc), DestReg: ResultReg);
3954 return ResultReg;
3955}
3956
3957bool X86FastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
3958 const LoadInst *LI) {
3959 const Value *Ptr = LI->getPointerOperand();
3960 X86AddressMode AM;
3961 if (!X86SelectAddress(V: Ptr, AM))
3962 return false;
3963
3964 const X86InstrInfo &XII = (const X86InstrInfo &)TII;
3965
3966 unsigned Size = DL.getTypeAllocSize(Ty: LI->getType());
3967
3968 SmallVector<MachineOperand, 8> AddrOps;
3969 AM.getFullAddress(MO&: AddrOps);
3970
3971 MachineInstr *Result = XII.foldMemoryOperandImpl(
3972 MF&: *FuncInfo.MF, MI&: *MI, OpNum: OpNo, MOs: AddrOps, InsertPt: FuncInfo.InsertPt, Size, Alignment: LI->getAlign(),
3973 /*AllowCommute=*/true);
3974 if (!Result)
3975 return false;
3976
3977 // The index register could be in the wrong register class. Unfortunately,
3978 // foldMemoryOperandImpl could have commuted the instruction so its not enough
3979 // to just look at OpNo + the offset to the index reg. We actually need to
3980 // scan the instruction to find the index reg and see if its the correct reg
3981 // class.
3982 unsigned OperandNo = 0;
3983 for (MachineInstr::mop_iterator I = Result->operands_begin(),
3984 E = Result->operands_end(); I != E; ++I, ++OperandNo) {
3985 MachineOperand &MO = *I;
3986 if (!MO.isReg() || MO.isDef() || MO.getReg() != AM.IndexReg)
3987 continue;
3988 // Found the index reg, now try to rewrite it.
3989 Register IndexReg = constrainOperandRegClass(II: Result->getDesc(),
3990 Op: MO.getReg(), OpNum: OperandNo);
3991 if (IndexReg == MO.getReg())
3992 continue;
3993 MO.setReg(IndexReg);
3994 }
3995
3996 if (MI->isCall())
3997 FuncInfo.MF->moveAdditionalCallInfo(Old: MI, New: Result);
3998 Result->addMemOperand(MF&: *FuncInfo.MF, MO: createMachineMemOperandFor(I: LI));
3999 Result->cloneInstrSymbols(MF&: *FuncInfo.MF, MI: *MI);
4000 MachineBasicBlock::iterator I(MI);
4001 removeDeadCode(I, E: std::next(x: I));
4002 return true;
4003}
4004
4005Register X86FastISel::fastEmitInst_rrrr(unsigned MachineInstOpcode,
4006 const TargetRegisterClass *RC,
4007 Register Op0, Register Op1,
4008 Register Op2, Register Op3) {
4009 const MCInstrDesc &II = TII.get(Opcode: MachineInstOpcode);
4010
4011 Register ResultReg = createResultReg(RC);
4012 Op0 = constrainOperandRegClass(II, Op: Op0, OpNum: II.getNumDefs());
4013 Op1 = constrainOperandRegClass(II, Op: Op1, OpNum: II.getNumDefs() + 1);
4014 Op2 = constrainOperandRegClass(II, Op: Op2, OpNum: II.getNumDefs() + 2);
4015 Op3 = constrainOperandRegClass(II, Op: Op3, OpNum: II.getNumDefs() + 3);
4016
4017 if (II.getNumDefs() >= 1)
4018 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: II, DestReg: ResultReg)
4019 .addReg(RegNo: Op0)
4020 .addReg(RegNo: Op1)
4021 .addReg(RegNo: Op2)
4022 .addReg(RegNo: Op3);
4023 else {
4024 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: II)
4025 .addReg(RegNo: Op0)
4026 .addReg(RegNo: Op1)
4027 .addReg(RegNo: Op2)
4028 .addReg(RegNo: Op3);
4029 BuildMI(BB&: *FuncInfo.MBB, I: FuncInfo.InsertPt, MIMD, MCID: TII.get(Opcode: TargetOpcode::COPY),
4030 DestReg: ResultReg)
4031 .addReg(RegNo: II.implicit_defs()[0]);
4032 }
4033 return ResultReg;
4034}
4035
4036namespace llvm {
4037FastISel *X86::createFastISel(FunctionLoweringInfo &funcInfo,
4038 const TargetLibraryInfo *libInfo,
4039 const LibcallLoweringInfo *libcallLowering) {
4040 return new X86FastISel(funcInfo, libInfo, libcallLowering);
4041}
4042}
4043