1//===- llvm/lib/Target/X86/X86ISelCallLowering.cpp - Call lowering --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// This file implements the lowering of LLVM calls to DAG nodes.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MCTargetDesc/X86MCAsmInfo.h"
15#include "X86.h"
16#include "X86CallingConv.h"
17#include "X86FrameLowering.h"
18#include "X86ISelLowering.h"
19#include "X86InstrBuilder.h"
20#include "X86MachineFunctionInfo.h"
21#include "X86TargetMachine.h"
22#include "llvm/ADT/Statistic.h"
23#include "llvm/Analysis/ObjCARCUtil.h"
24#include "llvm/CodeGen/MachineJumpTableInfo.h"
25#include "llvm/CodeGen/MachineModuleInfo.h"
26#include "llvm/CodeGen/WinEHFuncInfo.h"
27#include "llvm/IR/DiagnosticInfo.h"
28#include "llvm/IR/IRBuilder.h"
29#include "llvm/IR/Module.h"
30#include "llvm/Transforms/CFGuard.h"
31
32#define DEBUG_TYPE "x86-isel"
33
34using namespace llvm;
35
36STATISTIC(NumTailCalls, "Number of tail calls");
37
38/// Call this when the user attempts to do something unsupported, like
39/// returning a double without SSE2 enabled on x86_64. This is not fatal, unlike
40/// report_fatal_error, so calling code should attempt to recover without
41/// crashing.
42static void errorUnsupported(SelectionDAG &DAG, const SDLoc &dl,
43 const char *Msg) {
44 MachineFunction &MF = DAG.getMachineFunction();
45 DAG.getContext()->diagnose(
46 DI: DiagnosticInfoUnsupported(MF.getFunction(), Msg, dl.getDebugLoc()));
47}
48
49/// Returns true if a CC can dynamically exclude a register from the list of
50/// callee-saved-registers (TargetRegistryInfo::getCalleeSavedRegs()) based on
51/// the return registers.
52static bool shouldDisableRetRegFromCSR(CallingConv::ID CC) {
53 switch (CC) {
54 default:
55 return false;
56 case CallingConv::X86_RegCall:
57 case CallingConv::PreserveMost:
58 case CallingConv::PreserveAll:
59 return true;
60 }
61}
62
63/// Returns true if a CC can dynamically exclude a register from the list of
64/// callee-saved-registers (TargetRegistryInfo::getCalleeSavedRegs()) based on
65/// the parameters.
66static bool shouldDisableArgRegFromCSR(CallingConv::ID CC) {
67 return CC == CallingConv::X86_RegCall;
68}
69
70static std::pair<MVT, unsigned>
71handleMaskRegisterForCallingConv(unsigned NumElts, CallingConv::ID CC,
72 const X86Subtarget &Subtarget) {
73 // v2i1/v4i1/v8i1/v16i1 all pass in xmm registers unless the calling
74 // convention is one that uses k registers.
75 if (NumElts == 2)
76 return {MVT::v2i64, 1};
77 if (NumElts == 4)
78 return {MVT::v4i32, 1};
79 if (NumElts == 8 && CC != CallingConv::X86_RegCall &&
80 CC != CallingConv::Intel_OCL_BI)
81 return {MVT::v8i16, 1};
82 if (NumElts == 16 && CC != CallingConv::X86_RegCall &&
83 CC != CallingConv::Intel_OCL_BI)
84 return {MVT::v16i8, 1};
85 // v32i1 passes in ymm unless we have BWI and the calling convention is
86 // regcall.
87 if (NumElts == 32 && (!Subtarget.hasBWI() || CC != CallingConv::X86_RegCall))
88 return {MVT::v32i8, 1};
89 // Split v64i1 vectors if we don't have v64i8 available.
90 if (NumElts == 64 && Subtarget.hasBWI() && CC != CallingConv::X86_RegCall) {
91 if (Subtarget.useAVX512Regs())
92 return {MVT::v64i8, 1};
93 return {MVT::v32i8, 2};
94 }
95
96 // Break wide or odd vXi1 vectors into scalars to match avx2 behavior.
97 if (!isPowerOf2_32(Value: NumElts) || (NumElts == 64 && !Subtarget.hasBWI()) ||
98 NumElts > 64)
99 return {MVT::i8, NumElts};
100
101 return {MVT::INVALID_SIMPLE_VALUE_TYPE, 0};
102}
103
104MVT X86TargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
105 CallingConv::ID CC,
106 EVT VT) const {
107 if (VT.isVector()) {
108 if (VT.getVectorElementType() == MVT::i1 && Subtarget.hasAVX512()) {
109 unsigned NumElts = VT.getVectorNumElements();
110
111 MVT RegisterVT;
112 unsigned NumRegisters;
113 std::tie(args&: RegisterVT, args&: NumRegisters) =
114 handleMaskRegisterForCallingConv(NumElts, CC, Subtarget);
115 if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
116 return RegisterVT;
117 }
118
119 if (VT.getVectorElementType() == MVT::f16 && VT.getVectorNumElements() < 8)
120 return MVT::v8f16;
121 }
122
123 // We will use more GPRs for f64 and f80 on 32 bits when x87 is disabled.
124 if ((VT == MVT::f64 || VT == MVT::f80) && !Subtarget.is64Bit() &&
125 !Subtarget.hasX87())
126 return MVT::i32;
127
128 if (isTypeLegal(VT: MVT::f16)) {
129 if (VT.isVectorOf(EltVT: MVT::bf16))
130 return getRegisterTypeForCallingConv(
131 Context, CC, VT: VT.changeVectorElementType(Context, EltVT: MVT::f16));
132
133 if (VT == MVT::bf16)
134 return MVT::f16;
135 }
136
137 return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
138}
139
140unsigned X86TargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
141 CallingConv::ID CC,
142 EVT VT) const {
143 if (VT.isVector()) {
144 if (VT.getVectorElementType() == MVT::i1 && Subtarget.hasAVX512()) {
145 unsigned NumElts = VT.getVectorNumElements();
146
147 MVT RegisterVT;
148 unsigned NumRegisters;
149 std::tie(args&: RegisterVT, args&: NumRegisters) =
150 handleMaskRegisterForCallingConv(NumElts, CC, Subtarget);
151 if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
152 return NumRegisters;
153 }
154
155 if (VT.getVectorElementType() == MVT::f16 && VT.getVectorNumElements() < 8)
156 return 1;
157 }
158
159 // We have to split f64 to 2 registers and f80 to 3 registers on 32 bits if
160 // x87 is disabled.
161 if (!Subtarget.is64Bit() && !Subtarget.hasX87()) {
162 if (VT == MVT::f64)
163 return 2;
164 if (VT == MVT::f80)
165 return 3;
166 }
167
168 if (VT.isVectorOf(EltVT: MVT::bf16) && isTypeLegal(VT: MVT::f16))
169 return getNumRegistersForCallingConv(
170 Context, CC, VT: VT.changeVectorElementType(Context, EltVT: MVT::f16));
171
172 return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
173}
174
175unsigned X86TargetLowering::getVectorTypeBreakdownForCallingConv(
176 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
177 unsigned &NumIntermediates, MVT &RegisterVT) const {
178 // Break wide or odd vXi1 vectors into scalars to match avx2 behavior.
179 if (VT.isVectorOf(EltVT: MVT::i1) && Subtarget.hasAVX512() &&
180 (!isPowerOf2_32(Value: VT.getVectorNumElements()) ||
181 (VT.getVectorNumElements() == 64 && !Subtarget.hasBWI()) ||
182 VT.getVectorNumElements() > 64)) {
183 RegisterVT = MVT::i8;
184 IntermediateVT = MVT::i1;
185 NumIntermediates = VT.getVectorNumElements();
186 return NumIntermediates;
187 }
188
189 // Split v64i1 vectors if we don't have v64i8 available.
190 if (VT == MVT::v64i1 && Subtarget.hasBWI() && !Subtarget.useAVX512Regs() &&
191 CC != CallingConv::X86_RegCall) {
192 RegisterVT = MVT::v32i8;
193 IntermediateVT = MVT::v32i1;
194 NumIntermediates = 2;
195 return 2;
196 }
197
198 // Split vNbf16 vectors according to vNf16.
199 if (VT.isVectorOf(EltVT: MVT::bf16) && isTypeLegal(VT: MVT::f16))
200 VT = VT.changeVectorElementType(Context, EltVT: MVT::f16);
201
202 return TargetLowering::getVectorTypeBreakdownForCallingConv(Context, CC, VT, IntermediateVT,
203 NumIntermediates, RegisterVT);
204}
205
206EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL,
207 LLVMContext& Context,
208 EVT VT) const {
209 if (!VT.isVector())
210 return MVT::i8;
211
212 if (Subtarget.hasAVX512()) {
213 // Figure out what this type will be legalized to.
214 EVT LegalVT = VT;
215 while (getTypeAction(Context, VT: LegalVT) != TypeLegal)
216 LegalVT = getTypeToTransformTo(Context, VT: LegalVT);
217
218 // If we got a 512-bit vector then we'll definitely have a vXi1 compare.
219 if (LegalVT.getSimpleVT().is512BitVector())
220 return EVT::getVectorVT(Context, VT: MVT::i1, EC: VT.getVectorElementCount());
221
222 if (LegalVT.getSimpleVT().isVector() && Subtarget.hasVLX()) {
223 // If we legalized to less than a 512-bit vector, then we will use a vXi1
224 // compare for vXi32/vXi64 for sure. If we have BWI we will also support
225 // vXi16/vXi8.
226 MVT EltVT = LegalVT.getSimpleVT().getVectorElementType();
227 if (Subtarget.hasBWI() || EltVT.getSizeInBits() >= 32)
228 return EVT::getVectorVT(Context, VT: MVT::i1, EC: VT.getVectorElementCount());
229 }
230 }
231
232 return VT.changeVectorElementTypeToInteger();
233}
234
235bool X86TargetLowering::functionArgumentNeedsConsecutiveRegisters(
236 Type *Ty, CallingConv::ID CallConv, bool isVarArg,
237 const DataLayout &DL) const {
238 // On x86-64 i128 is split into two i64s and needs to be allocated to two
239 // consecutive registers, or spilled to the stack as a whole. On x86-32 i128
240 // is split to four i32s and never actually passed in registers, but we use
241 // the consecutive register mark to match it in TableGen.
242 if (Ty->isIntegerTy(BitWidth: 128))
243 return true;
244
245 // On x86-32, fp128 acts the same as i128.
246 if (Subtarget.is32Bit() && Ty->isFP128Ty())
247 return true;
248
249 return false;
250}
251
252/// Helper for getByValTypeAlignment to determine
253/// the desired ByVal argument alignment.
254static void getMaxByValAlign(Type *Ty, Align &MaxAlign) {
255 if (MaxAlign == 16)
256 return;
257 if (VectorType *VTy = dyn_cast<VectorType>(Val: Ty)) {
258 if (VTy->getPrimitiveSizeInBits().getFixedValue() == 128)
259 MaxAlign = Align(16);
260 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Val: Ty)) {
261 Align EltAlign;
262 getMaxByValAlign(Ty: ATy->getElementType(), MaxAlign&: EltAlign);
263 if (EltAlign > MaxAlign)
264 MaxAlign = EltAlign;
265 } else if (StructType *STy = dyn_cast<StructType>(Val: Ty)) {
266 for (auto *EltTy : STy->elements()) {
267 Align EltAlign;
268 getMaxByValAlign(Ty: EltTy, MaxAlign&: EltAlign);
269 if (EltAlign > MaxAlign)
270 MaxAlign = EltAlign;
271 if (MaxAlign == 16)
272 break;
273 }
274 }
275}
276
277/// Return the desired alignment for ByVal aggregate
278/// function arguments in the caller parameter area. For X86, aggregates
279/// that contain SSE vectors are placed at 16-byte boundaries while the rest
280/// are at 4-byte boundaries.
281Align X86TargetLowering::getByValTypeAlignment(Type *Ty,
282 const DataLayout &DL) const {
283 if (Subtarget.is64Bit())
284 return std::max(a: DL.getABITypeAlign(Ty), b: Align::Constant<8>());
285
286 Align Alignment(4);
287 if (Subtarget.hasSSE1())
288 getMaxByValAlign(Ty, MaxAlign&: Alignment);
289 return Alignment;
290}
291
292/// It returns EVT::Other if the type should be determined using generic
293/// target-independent logic.
294/// For vector ops we check that the overall size isn't larger than our
295/// preferred vector width.
296EVT X86TargetLowering::getOptimalMemOpType(
297 LLVMContext &Context, const MemOp &Op,
298 const AttributeList &FuncAttributes) const {
299 if (!FuncAttributes.hasFnAttr(Kind: Attribute::NoImplicitFloat)) {
300 if (Op.size() >= 16 &&
301 (!Subtarget.isUnalignedMem16Slow() || Op.isAligned(AlignCheck: Align(16)))) {
302 // FIXME: Check if unaligned 64-byte accesses are slow.
303 if (Op.size() >= 64 && Subtarget.hasAVX512() &&
304 (Subtarget.getPreferVectorWidth() >= 512)) {
305 return Subtarget.hasBWI() ? MVT::v64i8 : MVT::v16i32;
306 }
307 // FIXME: Check if unaligned 32-byte accesses are slow.
308 if (Op.size() >= 32 && Subtarget.hasAVX() &&
309 Subtarget.useLight256BitInstructions()) {
310 // Although this isn't a well-supported type for AVX1, we'll let
311 // legalization and shuffle lowering produce the optimal codegen. If we
312 // choose an optimal type with a vector element larger than a byte,
313 // getMemsetStores() may create an intermediate splat (using an integer
314 // multiply) before we splat as a vector.
315 return MVT::v32i8;
316 }
317 if (Subtarget.hasSSE2() && (Subtarget.getPreferVectorWidth() >= 128))
318 return MVT::v16i8;
319 // TODO: Can SSE1 handle a byte vector?
320 // If we have SSE1 registers we should be able to use them.
321 if (Subtarget.hasSSE1() && (Subtarget.is64Bit() || Subtarget.hasX87()) &&
322 (Subtarget.getPreferVectorWidth() >= 128))
323 return MVT::v4f32;
324 } else if (((Op.isMemcpy() && !Op.isMemcpyStrSrc()) || Op.isZeroMemset()) &&
325 Op.size() >= 8 && !Subtarget.is64Bit() && Subtarget.hasSSE2()) {
326 // Do not use f64 to lower memcpy if source is string constant. It's
327 // better to use i32 to avoid the loads.
328 // Also, do not use f64 to lower memset unless this is a memset of zeros.
329 // The gymnastics of splatting a byte value into an XMM register and then
330 // only using 8-byte stores (because this is a CPU with slow unaligned
331 // 16-byte accesses) makes that a loser.
332 return MVT::f64;
333 }
334 }
335 // This is a compromise. If we reach here, unaligned accesses may be slow on
336 // this target. However, creating smaller, aligned accesses could be even
337 // slower and would certainly be a lot more code.
338 if (Subtarget.is64Bit() && Op.size() >= 8)
339 return MVT::i64;
340 return MVT::i32;
341}
342
343bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
344 if (VT == MVT::f32)
345 return Subtarget.hasSSE1();
346 if (VT == MVT::f64)
347 return Subtarget.hasSSE2();
348 return true;
349}
350
351static bool isBitAligned(Align Alignment, uint64_t SizeInBits) {
352 return (8 * Alignment.value()) % SizeInBits == 0;
353}
354
355bool X86TargetLowering::isMemoryAccessFast(EVT VT, Align Alignment) const {
356 if (isBitAligned(Alignment, SizeInBits: VT.getSizeInBits()))
357 return true;
358 switch (VT.getSizeInBits()) {
359 default:
360 // 8-byte and under are always assumed to be fast.
361 return true;
362 case 128:
363 return !Subtarget.isUnalignedMem16Slow();
364 case 256:
365 return !Subtarget.isUnalignedMem32Slow();
366 // TODO: What about AVX-512 (512-bit) accesses?
367 }
368}
369
370bool X86TargetLowering::allowsMisalignedMemoryAccesses(
371 EVT VT, unsigned, Align Alignment, MachineMemOperand::Flags Flags,
372 unsigned *Fast) const {
373 if (Fast)
374 *Fast = isMemoryAccessFast(VT, Alignment);
375 // NonTemporal vector memory ops must be aligned.
376 if (!!(Flags & MachineMemOperand::MONonTemporal) && VT.isVector()) {
377 // NT loads can only be vector aligned, so if its less aligned than the
378 // minimum vector size (which we can split the vector down to), we might as
379 // well use a regular unaligned vector load.
380 // We don't have any NT loads pre-SSE41.
381 if (!!(Flags & MachineMemOperand::MOLoad))
382 return (Alignment < 16 || !Subtarget.hasSSE41());
383 return false;
384 }
385 // Misaligned accesses of any size are always allowed.
386 return true;
387}
388
389bool X86TargetLowering::allowsMemoryAccess(LLVMContext &Context,
390 const DataLayout &DL, EVT VT,
391 unsigned AddrSpace, Align Alignment,
392 MachineMemOperand::Flags Flags,
393 unsigned *Fast) const {
394 if (Fast)
395 *Fast = isMemoryAccessFast(VT, Alignment);
396 if (!!(Flags & MachineMemOperand::MONonTemporal) && VT.isVector()) {
397 if (allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags,
398 /*Fast=*/nullptr))
399 return true;
400 // NonTemporal vector memory ops are special, and must be aligned.
401 if (!isBitAligned(Alignment, SizeInBits: VT.getSizeInBits()))
402 return false;
403 switch (VT.getSizeInBits()) {
404 case 128:
405 if (!!(Flags & MachineMemOperand::MOLoad) && Subtarget.hasSSE41())
406 return true;
407 if (!!(Flags & MachineMemOperand::MOStore) && Subtarget.hasSSE2())
408 return true;
409 return false;
410 case 256:
411 if (!!(Flags & MachineMemOperand::MOLoad) && Subtarget.hasAVX2())
412 return true;
413 if (!!(Flags & MachineMemOperand::MOStore) && Subtarget.hasAVX())
414 return true;
415 return false;
416 case 512:
417 if (Subtarget.hasAVX512())
418 return true;
419 return false;
420 default:
421 return false; // Don't have NonTemporal vector memory ops of this size.
422 }
423 }
424 return true;
425}
426
427/// Return the entry encoding for a jump table in the
428/// current function. The returned value is a member of the
429/// MachineJumpTableInfo::JTEntryKind enum.
430unsigned X86TargetLowering::getJumpTableEncoding() const {
431 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
432 // symbol.
433 if (isPositionIndependent() && Subtarget.isPICStyleGOT())
434 return MachineJumpTableInfo::EK_Custom32;
435 if (isPositionIndependent() &&
436 getTargetMachine().getCodeModel() == CodeModel::Large &&
437 !Subtarget.isTargetCOFF())
438 return MachineJumpTableInfo::EK_LabelDifference64;
439
440 // Otherwise, use the normal jump table encoding heuristics.
441 return TargetLowering::getJumpTableEncoding();
442}
443
444bool X86TargetLowering::useSoftFloat() const {
445 return Subtarget.useSoftFloat();
446}
447
448void X86TargetLowering::markLibCallAttributes(MachineFunction *MF, unsigned CC,
449 ArgListTy &Args) const {
450
451 // Only relabel X86-32 for C / Stdcall CCs.
452 if (Subtarget.is64Bit())
453 return;
454 if (CC != CallingConv::C && CC != CallingConv::X86_StdCall)
455 return;
456 unsigned ParamRegs = 0;
457 if (auto *M = MF->getFunction().getParent())
458 ParamRegs = M->getNumberRegisterParameters();
459
460 // Mark the first N int arguments as having reg
461 for (auto &Arg : Args) {
462 Type *T = Arg.Ty;
463 if (T->isIntOrPtrTy())
464 if (MF->getDataLayout().getTypeAllocSize(Ty: T) <= 8) {
465 unsigned numRegs = 1;
466 if (MF->getDataLayout().getTypeAllocSize(Ty: T) > 4)
467 numRegs = 2;
468 if (ParamRegs < numRegs)
469 return;
470 ParamRegs -= numRegs;
471 Arg.IsInReg = true;
472 }
473 }
474}
475
476const MCExpr *
477X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
478 const MachineBasicBlock *MBB,
479 unsigned uid,MCContext &Ctx) const{
480 assert(isPositionIndependent() && Subtarget.isPICStyleGOT());
481 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
482 // entries.
483 return MCSymbolRefExpr::create(Symbol: MBB->getSymbol(), specifier: X86::S_GOTOFF, Ctx);
484}
485
486/// Returns relocation base for the given PIC jumptable.
487SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
488 SelectionDAG &DAG) const {
489 if (!Subtarget.is64Bit())
490 // This doesn't have SDLoc associated with it, but is not really the
491 // same as a Register.
492 return DAG.getNode(Opcode: X86ISD::GlobalBaseReg, DL: SDLoc(),
493 VT: getPointerTy(DL: DAG.getDataLayout()));
494 return Table;
495}
496
497/// This returns the relocation base for the given PIC jumptable,
498/// the same as getPICJumpTableRelocBase, but as an MCExpr.
499const MCExpr *X86TargetLowering::
500getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
501 MCContext &Ctx) const {
502 // X86-64 uses RIP relative addressing based on the jump table label.
503 if (Subtarget.isPICStyleRIPRel() ||
504 (Subtarget.is64Bit() &&
505 getTargetMachine().getCodeModel() == CodeModel::Large))
506 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
507
508 // Otherwise, the reference is relative to the PIC base.
509 return MCSymbolRefExpr::create(Symbol: MF->getPICBaseSymbol(), Ctx);
510}
511
512std::pair<const TargetRegisterClass *, uint8_t>
513X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
514 MVT VT) const {
515 const TargetRegisterClass *RRC = nullptr;
516 uint8_t Cost = 1;
517 switch (VT.SimpleTy) {
518 default:
519 return TargetLowering::findRepresentativeClass(TRI, VT);
520 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
521 RRC = Subtarget.is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
522 break;
523 case MVT::x86mmx:
524 RRC = &X86::VR64RegClass;
525 break;
526 case MVT::f32: case MVT::f64:
527 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
528 case MVT::v4f32: case MVT::v2f64:
529 case MVT::v32i8: case MVT::v16i16: case MVT::v8i32: case MVT::v4i64:
530 case MVT::v8f32: case MVT::v4f64:
531 case MVT::v64i8: case MVT::v32i16: case MVT::v16i32: case MVT::v8i64:
532 case MVT::v16f32: case MVT::v8f64:
533 RRC = &X86::VR128XRegClass;
534 break;
535 }
536 return std::make_pair(x&: RRC, y&: Cost);
537}
538
539unsigned X86TargetLowering::getAddressSpace() const {
540 if (Subtarget.is64Bit())
541 return (getTargetMachine().getCodeModel() == CodeModel::Kernel) ? X86AS::GS
542 : X86AS::FS;
543 return X86AS::GS;
544}
545
546static bool hasStackGuardSlotTLS(const Triple &TargetTriple) {
547 return TargetTriple.isOSGlibc() || TargetTriple.isMusl() ||
548 TargetTriple.isOSFuchsia() || TargetTriple.isAndroid();
549}
550
551static Constant* SegmentOffset(IRBuilderBase &IRB,
552 int Offset, unsigned AddressSpace) {
553 return ConstantExpr::getIntToPtr(
554 C: ConstantInt::getSigned(Ty: Type::getInt32Ty(C&: IRB.getContext()), V: Offset),
555 Ty: IRB.getPtrTy(AddrSpace: AddressSpace));
556}
557
558Value *
559X86TargetLowering::getIRStackGuard(IRBuilderBase &IRB,
560 const LibcallLoweringInfo &Libcalls) const {
561 // glibc, bionic, and Fuchsia have a special slot for the stack guard in
562 // tcbhead_t; use it instead of the usual global variable (see
563 // sysdeps/{i386,x86_64}/nptl/tls.h)
564 if (hasStackGuardSlotTLS(TargetTriple: Subtarget.getTargetTriple())) {
565 unsigned AddressSpace = getAddressSpace();
566
567 // <zircon/tls.h> defines ZX_TLS_STACK_GUARD_OFFSET with this value.
568 if (Subtarget.isTargetFuchsia())
569 return SegmentOffset(IRB, Offset: 0x10, AddressSpace);
570
571 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
572 // Specially, some users may customize the base reg and offset.
573 int Offset = M->getStackProtectorGuardOffset();
574 // If we don't set -stack-protector-guard-offset value:
575 // %fs:0x28, unless we're using a Kernel code model, in which case
576 // it's %gs:0x28. gs:0x14 on i386.
577 if (Offset == INT_MAX)
578 Offset = (Subtarget.is64Bit()) ? 0x28 : 0x14;
579
580 StringRef GuardReg = M->getStackProtectorGuardReg();
581 if (GuardReg == "fs")
582 AddressSpace = X86AS::FS;
583 else if (GuardReg == "gs")
584 AddressSpace = X86AS::GS;
585
586 // Use symbol guard if user specify.
587 StringRef GuardSymb = M->getStackProtectorGuardSymbol();
588 if (!GuardSymb.empty()) {
589 GlobalVariable *GV = M->getGlobalVariable(Name: GuardSymb);
590 if (!GV) {
591 Type *Ty = Subtarget.is64Bit() ? Type::getInt64Ty(C&: M->getContext())
592 : Type::getInt32Ty(C&: M->getContext());
593 GV = new GlobalVariable(*M, Ty, false, GlobalValue::ExternalLinkage,
594 nullptr, GuardSymb, nullptr,
595 GlobalValue::NotThreadLocal, AddressSpace);
596 if (!Subtarget.isTargetDarwin())
597 GV->setDSOLocal(M->getDirectAccessExternalData());
598 }
599 return GV;
600 }
601
602 return SegmentOffset(IRB, Offset, AddressSpace);
603 }
604 return TargetLowering::getIRStackGuard(IRB, Libcalls);
605}
606
607void X86TargetLowering::insertSSPDeclarations(
608 Module &M, const LibcallLoweringInfo &Libcalls) const {
609 // MSVC CRT provides functionalities for stack protection.
610 RTLIB::LibcallImpl SecurityCheckCookieLibcall =
611 Libcalls.getLibcallImpl(Call: RTLIB::SECURITY_CHECK_COOKIE);
612
613 RTLIB::LibcallImpl SecurityCookieVar =
614 Libcalls.getLibcallImpl(Call: RTLIB::STACK_CHECK_GUARD);
615 if (SecurityCheckCookieLibcall != RTLIB::Unsupported &&
616 SecurityCookieVar != RTLIB::Unsupported) {
617 // MSVC CRT provides functionalities for stack protection.
618 // MSVC CRT has a global variable holding security cookie.
619 M.getOrInsertGlobal(Name: getLibcallImplName(Call: SecurityCookieVar),
620 Ty: PointerType::getUnqual(C&: M.getContext()));
621
622 // MSVC CRT has a function to validate security cookie.
623 FunctionCallee SecurityCheckCookie =
624 M.getOrInsertFunction(Name: getLibcallImplName(Call: SecurityCheckCookieLibcall),
625 RetTy: Type::getVoidTy(C&: M.getContext()),
626 Args: PointerType::getUnqual(C&: M.getContext()));
627
628 if (Function *F = dyn_cast<Function>(Val: SecurityCheckCookie.getCallee())) {
629 F->setCallingConv(CallingConv::X86_FastCall);
630 F->addParamAttr(ArgNo: 0, Kind: Attribute::AttrKind::InReg);
631 }
632 return;
633 }
634
635 StringRef GuardMode = M.getStackProtectorGuard();
636
637 // glibc, bionic, and Fuchsia have a special slot for the stack guard.
638 if ((GuardMode == "tls" || GuardMode.empty()) &&
639 hasStackGuardSlotTLS(TargetTriple: Subtarget.getTargetTriple()))
640 return;
641 TargetLowering::insertSSPDeclarations(M, Libcalls);
642}
643
644Value *X86TargetLowering::getSafeStackPointerLocation(
645 IRBuilderBase &IRB, const LibcallLoweringInfo &Libcalls) const {
646 // Android provides a fixed TLS slot for the SafeStack pointer. See the
647 // definition of TLS_SLOT_SAFESTACK in
648 // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
649 if (Subtarget.isTargetAndroid()) {
650 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
651 // %gs:0x24 on i386
652 int Offset = (Subtarget.is64Bit()) ? 0x48 : 0x24;
653 return SegmentOffset(IRB, Offset, AddressSpace: getAddressSpace());
654 }
655
656 // Fuchsia is similar.
657 if (Subtarget.isTargetFuchsia()) {
658 // <zircon/tls.h> defines ZX_TLS_UNSAFE_SP_OFFSET with this value.
659 return SegmentOffset(IRB, Offset: 0x18, AddressSpace: getAddressSpace());
660 }
661
662 return TargetLowering::getSafeStackPointerLocation(IRB, Libcalls);
663}
664
665//===----------------------------------------------------------------------===//
666// Return Value Calling Convention Implementation
667//===----------------------------------------------------------------------===//
668
669bool X86TargetLowering::CanLowerReturn(
670 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
671 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
672 const Type *RetTy) const {
673 SmallVector<CCValAssign, 16> RVLocs;
674 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
675 return CCInfo.CheckReturn(Outs, Fn: RetCC_X86);
676}
677
678const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
679 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
680 return ScratchRegs;
681}
682
683ArrayRef<MCPhysReg> X86TargetLowering::getRoundingControlRegisters() const {
684 static const MCPhysReg RCRegs[] = {X86::FPCW, X86::MXCSR};
685 return RCRegs;
686}
687
688/// Lowers masks values (v*i1) to the local register values
689/// \returns DAG node after lowering to register type
690static SDValue lowerMasksToReg(const SDValue &ValArg, const EVT &ValLoc,
691 const SDLoc &DL, SelectionDAG &DAG) {
692 EVT ValVT = ValArg.getValueType();
693
694 if (ValVT == MVT::v1i1)
695 return DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: ValLoc, N1: ValArg,
696 N2: DAG.getIntPtrConstant(Val: 0, DL));
697
698 if ((ValVT == MVT::v8i1 && (ValLoc == MVT::i8 || ValLoc == MVT::i32)) ||
699 (ValVT == MVT::v16i1 && (ValLoc == MVT::i16 || ValLoc == MVT::i32))) {
700 // Two stage lowering might be required
701 // bitcast: v8i1 -> i8 / v16i1 -> i16
702 // anyextend: i8 -> i32 / i16 -> i32
703 EVT TempValLoc = ValVT == MVT::v8i1 ? MVT::i8 : MVT::i16;
704 SDValue ValToCopy = DAG.getBitcast(VT: TempValLoc, V: ValArg);
705 if (ValLoc == MVT::i32)
706 ValToCopy = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: ValLoc, Operand: ValToCopy);
707 return ValToCopy;
708 }
709
710 if ((ValVT == MVT::v32i1 && ValLoc == MVT::i32) ||
711 (ValVT == MVT::v64i1 && ValLoc == MVT::i64)) {
712 // One stage lowering is required
713 // bitcast: v32i1 -> i32 / v64i1 -> i64
714 return DAG.getBitcast(VT: ValLoc, V: ValArg);
715 }
716
717 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: ValLoc, Operand: ValArg);
718}
719
720/// Breaks v64i1 value into two registers and adds the new node to the DAG
721static void Passv64i1ArgInRegs(
722 const SDLoc &DL, SelectionDAG &DAG, SDValue &Arg,
723 SmallVectorImpl<std::pair<Register, SDValue>> &RegsToPass, CCValAssign &VA,
724 CCValAssign &NextVA, const X86Subtarget &Subtarget) {
725 assert(Subtarget.hasBWI() && "Expected AVX512BW target!");
726 assert(Subtarget.is32Bit() && "Expecting 32 bit target");
727 assert(Arg.getValueType() == MVT::i64 && "Expecting 64 bit value");
728 assert(VA.isRegLoc() && NextVA.isRegLoc() &&
729 "The value should reside in two registers");
730
731 // Before splitting the value we cast it to i64
732 Arg = DAG.getBitcast(VT: MVT::i64, V: Arg);
733
734 // Splitting the value into two i32 types
735 SDValue Lo, Hi;
736 std::tie(args&: Lo, args&: Hi) = DAG.SplitScalar(N: Arg, DL, LoVT: MVT::i32, HiVT: MVT::i32);
737
738 // Attach the two i32 types into corresponding registers
739 RegsToPass.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: Lo));
740 RegsToPass.push_back(Elt: std::make_pair(x: NextVA.getLocReg(), y&: Hi));
741}
742
743SDValue
744X86TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
745 bool isVarArg,
746 const SmallVectorImpl<ISD::OutputArg> &Outs,
747 const SmallVectorImpl<SDValue> &OutVals,
748 const SDLoc &dl, SelectionDAG &DAG) const {
749 MachineFunction &MF = DAG.getMachineFunction();
750 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
751
752 // In some cases we need to disable registers from the default CSR list.
753 // For example, when they are used as return registers (preserve_* and X86's
754 // regcall) or for argument passing (X86's regcall).
755 bool ShouldDisableCalleeSavedRegister =
756 shouldDisableRetRegFromCSR(CC: CallConv) ||
757 MF.getFunction().hasFnAttribute(Kind: "no_caller_saved_registers");
758
759 if (CallConv == CallingConv::X86_INTR && !Outs.empty())
760 report_fatal_error(reason: "X86 interrupts may not return any value");
761
762 SmallVector<CCValAssign, 16> RVLocs;
763 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
764 CCInfo.AnalyzeReturn(Outs, Fn: RetCC_X86);
765
766 SmallVector<std::pair<Register, SDValue>, 4> RetVals;
767 for (unsigned I = 0, OutsIndex = 0, E = RVLocs.size(); I != E;
768 ++I, ++OutsIndex) {
769 CCValAssign &VA = RVLocs[I];
770 assert(VA.isRegLoc() && "Can only return in registers!");
771
772 // Add the register to the CalleeSaveDisableRegs list.
773 if (ShouldDisableCalleeSavedRegister)
774 MF.getRegInfo().disableCalleeSavedRegister(Reg: VA.getLocReg());
775
776 SDValue ValToCopy = OutVals[OutsIndex];
777 EVT ValVT = ValToCopy.getValueType();
778
779 // Promote values to the appropriate types.
780 if (VA.getLocInfo() == CCValAssign::SExt)
781 ValToCopy = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL: dl, VT: VA.getLocVT(), Operand: ValToCopy);
782 else if (VA.getLocInfo() == CCValAssign::ZExt)
783 ValToCopy = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: VA.getLocVT(), Operand: ValToCopy);
784 else if (VA.getLocInfo() == CCValAssign::AExt) {
785 if (ValVT.isVectorOf(EltVT: MVT::i1))
786 ValToCopy = lowerMasksToReg(ValArg: ValToCopy, ValLoc: VA.getLocVT(), DL: dl, DAG);
787 else
788 ValToCopy = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: VA.getLocVT(), Operand: ValToCopy);
789 }
790 else if (VA.getLocInfo() == CCValAssign::BCvt)
791 ValToCopy = DAG.getBitcast(VT: VA.getLocVT(), V: ValToCopy);
792
793 assert(VA.getLocInfo() != CCValAssign::FPExt &&
794 "Unexpected FP-extend for return value.");
795
796 // Report an error if we have attempted to return a value via an XMM
797 // register and SSE was disabled.
798 if (!Subtarget.hasSSE1() && X86::FR32XRegClass.contains(Reg: VA.getLocReg())) {
799 errorUnsupported(DAG, dl, Msg: "SSE register return with SSE disabled");
800 VA.convertToReg(Reg: X86::FP0); // Set reg to FP0, avoid hitting asserts.
801 } else if (!Subtarget.hasSSE2() &&
802 X86::FR64XRegClass.contains(Reg: VA.getLocReg()) &&
803 ValVT == MVT::f64) {
804 // When returning a double via an XMM register, report an error if SSE2 is
805 // not enabled.
806 errorUnsupported(DAG, dl, Msg: "SSE2 register return with SSE2 disabled");
807 VA.convertToReg(Reg: X86::FP0); // Set reg to FP0, avoid hitting asserts.
808 }
809
810 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
811 // the RET instruction and handled by the FP Stackifier.
812 if (VA.getLocReg() == X86::FP0 ||
813 VA.getLocReg() == X86::FP1) {
814 // If this is a copy from an xmm register to ST(0), use an FPExtend to
815 // change the value to the FP stack register class.
816 if (isScalarFPTypeInSSEReg(VT: VA.getValVT()))
817 ValToCopy = DAG.getNode(Opcode: ISD::FP_EXTEND, DL: dl, VT: MVT::f80, Operand: ValToCopy);
818 RetVals.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: ValToCopy));
819 // Don't emit a copytoreg.
820 continue;
821 }
822
823 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
824 // which is returned in RAX / RDX.
825 if (Subtarget.is64Bit()) {
826 if (ValVT == MVT::x86mmx) {
827 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
828 ValToCopy = DAG.getBitcast(VT: MVT::i64, V: ValToCopy);
829 ValToCopy = DAG.getNode(Opcode: ISD::SCALAR_TO_VECTOR, DL: dl, VT: MVT::v2i64,
830 Operand: ValToCopy);
831 // If we don't have SSE2 available, convert to v4f32 so the generated
832 // register is legal.
833 if (!Subtarget.hasSSE2())
834 ValToCopy = DAG.getBitcast(VT: MVT::v4f32, V: ValToCopy);
835 }
836 }
837 }
838
839 if (VA.needsCustom()) {
840 assert(VA.getValVT() == MVT::v64i1 &&
841 "Currently the only custom case is when we split v64i1 to 2 regs");
842
843 Passv64i1ArgInRegs(DL: dl, DAG, Arg&: ValToCopy, RegsToPass&: RetVals, VA, NextVA&: RVLocs[++I],
844 Subtarget);
845
846 // Add the second register to the CalleeSaveDisableRegs list.
847 if (ShouldDisableCalleeSavedRegister)
848 MF.getRegInfo().disableCalleeSavedRegister(Reg: RVLocs[I].getLocReg());
849 } else {
850 RetVals.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: ValToCopy));
851 }
852 }
853
854 SDValue Glue;
855 SmallVector<SDValue, 6> RetOps;
856 RetOps.push_back(Elt: Chain); // Operand #0 = Chain (updated below)
857 // Operand #1 = Bytes To Pop
858 RetOps.push_back(Elt: DAG.getTargetConstant(Val: FuncInfo->getBytesToPopOnReturn(), DL: dl,
859 VT: MVT::i32));
860
861 // Copy the result values into the output registers.
862 for (auto &RetVal : RetVals) {
863 if (RetVal.first == X86::FP0 || RetVal.first == X86::FP1) {
864 RetOps.push_back(Elt: RetVal.second);
865 continue; // Don't emit a copytoreg.
866 }
867
868 Chain = DAG.getCopyToReg(Chain, dl, Reg: RetVal.first, N: RetVal.second, Glue);
869 Glue = Chain.getValue(R: 1);
870 RetOps.push_back(
871 Elt: DAG.getRegister(Reg: RetVal.first, VT: RetVal.second.getValueType()));
872 }
873
874 // Swift calling convention does not require we copy the sret argument
875 // into %rax/%eax for the return, and SRetReturnReg is not set for Swift.
876
877 // All x86 ABIs require that for returning structs by value we copy
878 // the sret argument into %rax/%eax (depending on ABI) for the return.
879 // We saved the argument into a virtual register in the entry block,
880 // so now we copy the value out and into %rax/%eax.
881 //
882 // Checking Function.hasStructRetAttr() here is insufficient because the IR
883 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
884 // false, then an sret argument may be implicitly inserted in the SelDAG. In
885 // either case FuncInfo->setSRetReturnReg() will have been called.
886 if (Register SRetReg = FuncInfo->getSRetReturnReg()) {
887 // When we have both sret and another return value, we should use the
888 // original Chain stored in RetOps[0], instead of the current Chain updated
889 // in the above loop. If we only have sret, RetOps[0] equals to Chain.
890
891 // For the case of sret and another return value, we have
892 // Chain_0 at the function entry
893 // Chain_1 = getCopyToReg(Chain_0) in the above loop
894 // If we use Chain_1 in getCopyFromReg, we will have
895 // Val = getCopyFromReg(Chain_1)
896 // Chain_2 = getCopyToReg(Chain_1, Val) from below
897
898 // getCopyToReg(Chain_0) will be glued together with
899 // getCopyToReg(Chain_1, Val) into Unit A, getCopyFromReg(Chain_1) will be
900 // in Unit B, and we will have cyclic dependency between Unit A and Unit B:
901 // Data dependency from Unit B to Unit A due to usage of Val in
902 // getCopyToReg(Chain_1, Val)
903 // Chain dependency from Unit A to Unit B
904
905 // So here, we use RetOps[0] (i.e Chain_0) for getCopyFromReg.
906 SDValue Val = DAG.getCopyFromReg(Chain: RetOps[0], dl, Reg: SRetReg,
907 VT: getPointerTy(DL: MF.getDataLayout()));
908
909 Register RetValReg
910 = (Subtarget.is64Bit() && !Subtarget.isTarget64BitILP32()) ?
911 X86::RAX : X86::EAX;
912 Chain = DAG.getCopyToReg(Chain, dl, Reg: RetValReg, N: Val, Glue);
913 Glue = Chain.getValue(R: 1);
914
915 // RAX/EAX now acts like a return value.
916 RetOps.push_back(
917 Elt: DAG.getRegister(Reg: RetValReg, VT: getPointerTy(DL: DAG.getDataLayout())));
918
919 // Add the returned register to the CalleeSaveDisableRegs list. Don't do
920 // this however for preserve_most/preserve_all to minimize the number of
921 // callee-saved registers for these CCs.
922 if (ShouldDisableCalleeSavedRegister &&
923 CallConv != CallingConv::PreserveAll &&
924 CallConv != CallingConv::PreserveMost)
925 MF.getRegInfo().disableCalleeSavedRegister(Reg: RetValReg);
926 }
927
928 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
929 const MCPhysReg *I =
930 TRI->getCalleeSavedRegsViaCopy(MF: &DAG.getMachineFunction());
931 if (I) {
932 for (; *I; ++I) {
933 if (X86::GR64RegClass.contains(Reg: *I))
934 RetOps.push_back(Elt: DAG.getRegister(Reg: *I, VT: MVT::i64));
935 else
936 llvm_unreachable("Unexpected register class in CSRsViaCopy!");
937 }
938 }
939
940 RetOps[0] = Chain; // Update chain.
941
942 // Add the glue if we have it.
943 if (Glue.getNode())
944 RetOps.push_back(Elt: Glue);
945
946 unsigned RetOpcode = X86ISD::RET_GLUE;
947 if (CallConv == CallingConv::X86_INTR)
948 RetOpcode = X86ISD::IRET;
949 return DAG.getNode(Opcode: RetOpcode, DL: dl, VT: MVT::Other, Ops: RetOps);
950}
951
952bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
953 if (N->getNumValues() != 1 || !N->hasNUsesOfValue(NUses: 1, Value: 0))
954 return false;
955
956 SDValue TCChain = Chain;
957 SDNode *Copy = *N->user_begin();
958 if (Copy->getOpcode() == ISD::CopyToReg) {
959 // If the copy has a glue operand, we conservatively assume it isn't safe to
960 // perform a tail call.
961 if (Copy->getOperand(Num: Copy->getNumOperands()-1).getValueType() == MVT::Glue)
962 return false;
963 TCChain = Copy->getOperand(Num: 0);
964 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
965 return false;
966
967 bool HasRet = false;
968 for (const SDNode *U : Copy->users()) {
969 if (U->getOpcode() != X86ISD::RET_GLUE)
970 return false;
971 // If we are returning more than one value, we can definitely
972 // not make a tail call see PR19530
973 if (U->getNumOperands() > 4)
974 return false;
975 if (U->getNumOperands() == 4 &&
976 U->getOperand(Num: U->getNumOperands() - 1).getValueType() != MVT::Glue)
977 return false;
978 HasRet = true;
979 }
980
981 if (!HasRet)
982 return false;
983
984 Chain = TCChain;
985 return true;
986}
987
988EVT X86TargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,
989 ISD::NodeType ExtendKind) const {
990 MVT ReturnMVT = MVT::i32;
991
992 bool Darwin = Subtarget.getTargetTriple().isOSDarwin();
993 if (VT == MVT::i1 || (!Darwin && (VT == MVT::i8 || VT == MVT::i16))) {
994 // The ABI does not require i1, i8 or i16 to be extended.
995 //
996 // On Darwin, there is code in the wild relying on Clang's old behaviour of
997 // always extending i8/i16 return values, so keep doing that for now.
998 // (PR26665).
999 ReturnMVT = MVT::i8;
1000 }
1001
1002 EVT MinVT = getRegisterType(Context, VT: ReturnMVT);
1003 return VT.bitsLT(VT: MinVT) ? MinVT : VT;
1004}
1005
1006/// Reads two 32 bit registers and creates a 64 bit mask value.
1007/// \param VA The current 32 bit value that need to be assigned.
1008/// \param NextVA The next 32 bit value that need to be assigned.
1009/// \param Root The parent DAG node.
1010/// \param [in,out] InGlue Represents SDvalue in the parent DAG node for
1011/// glue purposes. In the case the DAG is already using
1012/// physical register instead of virtual, we should glue
1013/// our new SDValue to InGlue SDvalue.
1014/// \return a new SDvalue of size 64bit.
1015static SDValue getv64i1Argument(CCValAssign &VA, CCValAssign &NextVA,
1016 SDValue &Root, SelectionDAG &DAG,
1017 const SDLoc &DL, const X86Subtarget &Subtarget,
1018 SDValue *InGlue = nullptr) {
1019 assert((Subtarget.hasBWI()) && "Expected AVX512BW target!");
1020 assert(Subtarget.is32Bit() && "Expecting 32 bit target");
1021 assert(VA.getValVT() == MVT::v64i1 &&
1022 "Expecting first location of 64 bit width type");
1023 assert(NextVA.getValVT() == VA.getValVT() &&
1024 "The locations should have the same type");
1025 assert(VA.isRegLoc() && NextVA.isRegLoc() &&
1026 "The values should reside in two registers");
1027
1028 SDValue Lo, Hi;
1029 SDValue ArgValueLo, ArgValueHi;
1030
1031 MachineFunction &MF = DAG.getMachineFunction();
1032 const TargetRegisterClass *RC = &X86::GR32RegClass;
1033
1034 // Read a 32 bit value from the registers.
1035 if (nullptr == InGlue) {
1036 // When no physical register is present,
1037 // create an intermediate virtual register.
1038 Register Reg = MF.addLiveIn(PReg: VA.getLocReg(), RC);
1039 ArgValueLo = DAG.getCopyFromReg(Chain: Root, dl: DL, Reg, VT: MVT::i32);
1040 Reg = MF.addLiveIn(PReg: NextVA.getLocReg(), RC);
1041 ArgValueHi = DAG.getCopyFromReg(Chain: Root, dl: DL, Reg, VT: MVT::i32);
1042 } else {
1043 // When a physical register is available read the value from it and glue
1044 // the reads together.
1045 ArgValueLo =
1046 DAG.getCopyFromReg(Chain: Root, dl: DL, Reg: VA.getLocReg(), VT: MVT::i32, Glue: *InGlue);
1047 *InGlue = ArgValueLo.getValue(R: 2);
1048 ArgValueHi =
1049 DAG.getCopyFromReg(Chain: Root, dl: DL, Reg: NextVA.getLocReg(), VT: MVT::i32, Glue: *InGlue);
1050 *InGlue = ArgValueHi.getValue(R: 2);
1051 }
1052
1053 // Convert the i32 type into v32i1 type.
1054 Lo = DAG.getBitcast(VT: MVT::v32i1, V: ArgValueLo);
1055
1056 // Convert the i32 type into v32i1 type.
1057 Hi = DAG.getBitcast(VT: MVT::v32i1, V: ArgValueHi);
1058
1059 // Concatenate the two values together.
1060 return DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL, VT: MVT::v64i1, N1: Lo, N2: Hi);
1061}
1062
1063/// The function will lower a register of various sizes (8/16/32/64)
1064/// to a mask value of the expected size (v8i1/v16i1/v32i1/v64i1)
1065/// \returns a DAG node contains the operand after lowering to mask type.
1066static SDValue lowerRegToMasks(const SDValue &ValArg, const EVT &ValVT,
1067 const EVT &ValLoc, const SDLoc &DL,
1068 SelectionDAG &DAG) {
1069 SDValue ValReturned = ValArg;
1070
1071 if (ValVT == MVT::v1i1)
1072 return DAG.getNode(Opcode: ISD::SCALAR_TO_VECTOR, DL, VT: MVT::v1i1, Operand: ValReturned);
1073
1074 if (ValVT == MVT::v64i1) {
1075 // In 32 bit machine, this case is handled by getv64i1Argument
1076 assert(ValLoc == MVT::i64 && "Expecting only i64 locations");
1077 // In 64 bit machine, There is no need to truncate the value only bitcast
1078 } else {
1079 MVT MaskLenVT;
1080 switch (ValVT.getSimpleVT().SimpleTy) {
1081 case MVT::v8i1:
1082 MaskLenVT = MVT::i8;
1083 break;
1084 case MVT::v16i1:
1085 MaskLenVT = MVT::i16;
1086 break;
1087 case MVT::v32i1:
1088 MaskLenVT = MVT::i32;
1089 break;
1090 default:
1091 llvm_unreachable("Expecting a vector of i1 types");
1092 }
1093
1094 ValReturned = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: MaskLenVT, Operand: ValReturned);
1095 }
1096 return DAG.getBitcast(VT: ValVT, V: ValReturned);
1097}
1098
1099static SDValue getPopFromX87Reg(SelectionDAG &DAG, SDValue Chain,
1100 const SDLoc &dl, Register Reg, EVT VT,
1101 SDValue Glue) {
1102 SDVTList VTs = DAG.getVTList(VT1: VT, VT2: MVT::Other, VT3: MVT::Glue);
1103 SDValue Ops[] = {Chain, DAG.getRegister(Reg, VT), Glue};
1104 return DAG.getNode(Opcode: X86ISD::POP_FROM_X87_REG, DL: dl, VTList: VTs,
1105 Ops: ArrayRef(Ops, Glue.getNode() ? 3 : 2));
1106}
1107
1108/// Lower the result values of a call into the
1109/// appropriate copies out of appropriate physical registers.
1110///
1111SDValue X86TargetLowering::LowerCallResult(
1112 SDValue Chain, SDValue InGlue, CallingConv::ID CallConv, bool isVarArg,
1113 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1114 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
1115 uint32_t *RegMask) const {
1116
1117 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1118 // Assign locations to each value returned by this call.
1119 SmallVector<CCValAssign, 16> RVLocs;
1120 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1121 *DAG.getContext());
1122 CCInfo.AnalyzeCallResult(Ins, Fn: RetCC_X86);
1123
1124 // Copy all of the result registers out of their specified physreg.
1125 for (unsigned I = 0, InsIndex = 0, E = RVLocs.size(); I != E;
1126 ++I, ++InsIndex) {
1127 CCValAssign &VA = RVLocs[I];
1128 EVT CopyVT = VA.getLocVT();
1129
1130 // In some calling conventions we need to remove the used registers
1131 // from the register mask.
1132 if (RegMask) {
1133 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg: VA.getLocReg()))
1134 RegMask[SubReg / 32] &= ~(1u << (SubReg % 32));
1135 }
1136
1137 // Report an error if there was an attempt to return FP values via XMM
1138 // registers.
1139 if (!Subtarget.hasSSE1() && X86::FR32XRegClass.contains(Reg: VA.getLocReg())) {
1140 errorUnsupported(DAG, dl, Msg: "SSE register return with SSE disabled");
1141 if (VA.getLocReg() == X86::XMM1)
1142 VA.convertToReg(Reg: X86::FP1); // Set reg to FP1, avoid hitting asserts.
1143 else
1144 VA.convertToReg(Reg: X86::FP0); // Set reg to FP0, avoid hitting asserts.
1145 } else if (!Subtarget.hasSSE2() &&
1146 X86::FR64XRegClass.contains(Reg: VA.getLocReg()) &&
1147 CopyVT == MVT::f64) {
1148 errorUnsupported(DAG, dl, Msg: "SSE2 register return with SSE2 disabled");
1149 if (VA.getLocReg() == X86::XMM1)
1150 VA.convertToReg(Reg: X86::FP1); // Set reg to FP1, avoid hitting asserts.
1151 else
1152 VA.convertToReg(Reg: X86::FP0); // Set reg to FP0, avoid hitting asserts.
1153 }
1154
1155 // If we prefer to use the value in xmm registers, copy it out as f80 and
1156 // use a truncate to move it from fp stack reg to xmm reg.
1157 bool RoundAfterCopy = false;
1158 bool X87Result = VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1;
1159 if (X87Result && isScalarFPTypeInSSEReg(VT: VA.getValVT())) {
1160 if (!Subtarget.hasX87())
1161 report_fatal_error(reason: "X87 register return with X87 disabled");
1162 CopyVT = MVT::f80;
1163 RoundAfterCopy = (CopyVT != VA.getLocVT());
1164 }
1165
1166 SDValue Val;
1167 if (VA.needsCustom()) {
1168 assert(VA.getValVT() == MVT::v64i1 &&
1169 "Currently the only custom case is when we split v64i1 to 2 regs");
1170 Val =
1171 getv64i1Argument(VA, NextVA&: RVLocs[++I], Root&: Chain, DAG, DL: dl, Subtarget, InGlue: &InGlue);
1172 } else {
1173 Chain =
1174 X87Result
1175 ? getPopFromX87Reg(DAG, Chain, dl, Reg: VA.getLocReg(), VT: CopyVT, Glue: InGlue)
1176 .getValue(R: 1)
1177 : DAG.getCopyFromReg(Chain, dl, Reg: VA.getLocReg(), VT: CopyVT, Glue: InGlue)
1178 .getValue(R: 1);
1179 Val = Chain.getValue(R: 0);
1180 InGlue = Chain.getValue(R: 2);
1181 }
1182
1183 if (RoundAfterCopy)
1184 Val = DAG.getNode(Opcode: ISD::FP_ROUND, DL: dl, VT: VA.getValVT(), N1: Val,
1185 // This truncation won't change the value.
1186 N2: DAG.getIntPtrConstant(Val: 1, DL: dl, /*isTarget=*/true));
1187
1188 if (VA.isExtInLoc()) {
1189 if (VA.getValVT().isVector() &&
1190 VA.getValVT().getScalarType() == MVT::i1 &&
1191 ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) ||
1192 (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) {
1193 // promoting a mask type (v*i1) into a register of type i64/i32/i16/i8
1194 Val = lowerRegToMasks(ValArg: Val, ValVT: VA.getValVT(), ValLoc: VA.getLocVT(), DL: dl, DAG);
1195 } else
1196 Val = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: VA.getValVT(), Operand: Val);
1197 }
1198
1199 if (VA.getLocInfo() == CCValAssign::BCvt)
1200 Val = DAG.getBitcast(VT: VA.getValVT(), V: Val);
1201
1202 InVals.push_back(Elt: Val);
1203 }
1204
1205 return Chain;
1206}
1207
1208/// Determines whether Args, either a set of outgoing arguments to a call, or a
1209/// set of incoming args of a call, contains an sret pointer that the callee
1210/// pops. This happens on most x86-32, System V platforms, unless register
1211/// parameters are in use (-mregparm=1+, regcallcc, etc).
1212template <typename T>
1213static bool hasCalleePopSRet(const SmallVectorImpl<T> &Args,
1214 const SmallVectorImpl<CCValAssign> &ArgLocs,
1215 const X86Subtarget &Subtarget) {
1216 // Not C++20 (yet), so no concepts available.
1217 static_assert(std::is_same_v<T, ISD::OutputArg> ||
1218 std::is_same_v<T, ISD::InputArg>,
1219 "requires ISD::OutputArg or ISD::InputArg");
1220
1221 // Popping the sret pointer only happens on x86-32 System V ABI platforms
1222 // (Linux, Cygwin, BSDs, Mac, etc). That excludes Windows-minus-Cygwin and
1223 // MCU.
1224 const Triple &TT = Subtarget.getTargetTriple();
1225 if (!TT.isX86_32() || TT.isOSMSVCRT() || TT.isOSIAMCU())
1226 return false;
1227
1228 // Check if the first argument is marked sret and if it is passed in memory.
1229 bool IsSRetInMem = false;
1230 if (!Args.empty())
1231 IsSRetInMem = Args.front().Flags.isSRet() && ArgLocs.front().isMemLoc();
1232 return IsSRetInMem;
1233}
1234
1235/// Make a copy of an aggregate at address specified by "Src" to address
1236/// "Dst" with size and alignment information specified by the specific
1237/// parameter attribute. The copy will be passed as a byval function parameter.
1238static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
1239 SDValue Chain, ISD::ArgFlagsTy Flags,
1240 SelectionDAG &DAG, const SDLoc &dl) {
1241 SDValue SizeNode = DAG.getIntPtrConstant(Val: Flags.getByValSize(), DL: dl);
1242 Align Alignment = Flags.getNonZeroByValAlign();
1243 return DAG.getMemcpy(Chain, dl, Dst, Src, Size: SizeNode, DstAlign: Alignment, SrcAlign: Alignment,
1244 /*isVolatile*/ isVol: false, /*AlwaysInline=*/true,
1245 /*CI=*/nullptr, OverrideTailCall: std::nullopt, DstPtrInfo: MachinePointerInfo(),
1246 SrcPtrInfo: MachinePointerInfo());
1247}
1248
1249/// Return true if the calling convention is one that we can guarantee TCO for.
1250static bool canGuaranteeTCO(CallingConv::ID CC) {
1251 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
1252 CC == CallingConv::X86_RegCall || CC == CallingConv::HiPE ||
1253 CC == CallingConv::Tail || CC == CallingConv::SwiftTail);
1254}
1255
1256/// Return true if we might ever do TCO for calls with this calling convention.
1257static bool mayTailCallThisCC(CallingConv::ID CC) {
1258 switch (CC) {
1259 // C calling conventions:
1260 case CallingConv::C:
1261 case CallingConv::Win64:
1262 case CallingConv::X86_64_SysV:
1263 case CallingConv::PreserveNone:
1264 // Callee pop conventions:
1265 case CallingConv::X86_ThisCall:
1266 case CallingConv::X86_StdCall:
1267 case CallingConv::X86_VectorCall:
1268 case CallingConv::X86_FastCall:
1269 // Swift:
1270 case CallingConv::Swift:
1271 return true;
1272 default:
1273 return canGuaranteeTCO(CC);
1274 }
1275}
1276
1277/// Return true if the function is being made into a tailcall target by
1278/// changing its ABI.
1279static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
1280 return (GuaranteedTailCallOpt && canGuaranteeTCO(CC)) ||
1281 CC == CallingConv::Tail || CC == CallingConv::SwiftTail;
1282}
1283
1284bool X86TargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
1285 if (!CI->isTailCall())
1286 return false;
1287
1288 CallingConv::ID CalleeCC = CI->getCallingConv();
1289 if (!mayTailCallThisCC(CC: CalleeCC))
1290 return false;
1291
1292 return true;
1293}
1294
1295SDValue
1296X86TargetLowering::LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
1297 const SmallVectorImpl<ISD::InputArg> &Ins,
1298 const SDLoc &dl, SelectionDAG &DAG,
1299 const CCValAssign &VA,
1300 MachineFrameInfo &MFI, unsigned i) const {
1301 // Create the nodes corresponding to a load from this parameter slot.
1302 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1303 bool AlwaysUseMutable = shouldGuaranteeTCO(
1304 CC: CallConv, GuaranteedTailCallOpt: DAG.getTarget().Options.GuaranteedTailCallOpt);
1305 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1306 EVT ValVT;
1307 MVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
1308
1309 // If value is passed by pointer we have address passed instead of the value
1310 // itself. No need to extend if the mask value and location share the same
1311 // absolute size.
1312 bool ExtendedInMem =
1313 VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1 &&
1314 VA.getValVT().getSizeInBits() != VA.getLocVT().getSizeInBits();
1315
1316 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
1317 ValVT = VA.getLocVT();
1318 else
1319 ValVT = VA.getValVT();
1320
1321 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1322 // changed with more analysis.
1323 // In case of tail call optimization mark all arguments mutable. Since they
1324 // could be overwritten by lowering of arguments in case of a tail call.
1325 if (Flags.isByVal()) {
1326 unsigned Bytes = Flags.getByValSize();
1327 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1328
1329 // FIXME: For now, all byval parameter objects are marked as aliasing. This
1330 // can be improved with deeper analysis.
1331 int FI = MFI.CreateFixedObject(Size: Bytes, SPOffset: VA.getLocMemOffset(), IsImmutable: isImmutable,
1332 /*isAliased=*/true);
1333 return DAG.getFrameIndex(FI, VT: PtrVT);
1334 }
1335
1336 EVT ArgVT = Ins[i].ArgVT;
1337
1338 // If this is a vector that has been split into multiple parts, don't elide
1339 // the copy. The layout on the stack may not match the packed in-memory
1340 // layout.
1341 bool ScalarizedVector = ArgVT.isVector() && !VA.getLocVT().isVector();
1342
1343 // This is an argument in memory. We might be able to perform copy elision.
1344 // If the argument is passed directly in memory without any extension, then we
1345 // can perform copy elision. Large vector types, for example, may be passed
1346 // indirectly by pointer.
1347 if (Flags.isCopyElisionCandidate() &&
1348 VA.getLocInfo() != CCValAssign::Indirect && !ExtendedInMem &&
1349 !ScalarizedVector) {
1350 SDValue PartAddr;
1351 if (Ins[i].PartOffset == 0) {
1352 // If this is a one-part value or the first part of a multi-part value,
1353 // create a stack object for the entire argument value type and return a
1354 // load from our portion of it. This assumes that if the first part of an
1355 // argument is in memory, the rest will also be in memory.
1356 int FI = MFI.CreateFixedObject(Size: ArgVT.getStoreSize(), SPOffset: VA.getLocMemOffset(),
1357 /*IsImmutable=*/false);
1358 PartAddr = DAG.getFrameIndex(FI, VT: PtrVT);
1359 return DAG.getLoad(
1360 VT: ValVT, dl, Chain, Ptr: PartAddr,
1361 PtrInfo: MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI));
1362 }
1363
1364 // This is not the first piece of an argument in memory. See if there is
1365 // already a fixed stack object including this offset. If so, assume it
1366 // was created by the PartOffset == 0 branch above and create a load from
1367 // the appropriate offset into it.
1368 int64_t PartBegin = VA.getLocMemOffset();
1369 int64_t PartEnd = PartBegin + ValVT.getSizeInBits() / 8;
1370 int FI = MFI.getObjectIndexBegin();
1371 for (; MFI.isFixedObjectIndex(ObjectIdx: FI); ++FI) {
1372 int64_t ObjBegin = MFI.getObjectOffset(ObjectIdx: FI);
1373 int64_t ObjEnd = ObjBegin + MFI.getObjectSize(ObjectIdx: FI);
1374 if (ObjBegin <= PartBegin && PartEnd <= ObjEnd)
1375 break;
1376 }
1377 if (MFI.isFixedObjectIndex(ObjectIdx: FI)) {
1378 SDValue Addr =
1379 DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: PtrVT, N1: DAG.getFrameIndex(FI, VT: PtrVT),
1380 N2: DAG.getIntPtrConstant(Val: Ins[i].PartOffset, DL: dl));
1381 return DAG.getLoad(VT: ValVT, dl, Chain, Ptr: Addr,
1382 PtrInfo: MachinePointerInfo::getFixedStack(
1383 MF&: DAG.getMachineFunction(), FI, Offset: Ins[i].PartOffset));
1384 }
1385 }
1386
1387 int FI = MFI.CreateFixedObject(Size: ValVT.getSizeInBits() / 8,
1388 SPOffset: VA.getLocMemOffset(), IsImmutable: isImmutable);
1389
1390 // Set SExt or ZExt flag.
1391 if (VA.getLocInfo() == CCValAssign::ZExt) {
1392 MFI.setObjectZExt(ObjectIdx: FI, IsZExt: true);
1393 } else if (VA.getLocInfo() == CCValAssign::SExt) {
1394 MFI.setObjectSExt(ObjectIdx: FI, IsSExt: true);
1395 }
1396
1397 MaybeAlign Alignment;
1398 if (Subtarget.isTargetWindowsMSVC() && !Subtarget.is64Bit() &&
1399 ValVT != MVT::f80)
1400 Alignment = MaybeAlign(4);
1401 SDValue FIN = DAG.getFrameIndex(FI, VT: PtrVT);
1402 SDValue Val = DAG.getLoad(
1403 VT: ValVT, dl, Chain, Ptr: FIN,
1404 PtrInfo: MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI),
1405 Alignment);
1406 return ExtendedInMem
1407 ? (VA.getValVT().isVector()
1408 ? DAG.getNode(Opcode: ISD::SCALAR_TO_VECTOR, DL: dl, VT: VA.getValVT(), Operand: Val)
1409 : DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: VA.getValVT(), Operand: Val))
1410 : Val;
1411}
1412
1413// FIXME: Get this from tablegen.
1414static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
1415 const X86Subtarget &Subtarget) {
1416 assert(Subtarget.is64Bit());
1417
1418 if (Subtarget.isCallingConvWin64(CC: CallConv)) {
1419 static const MCPhysReg GPR64ArgRegsWin64[] = {
1420 X86::RCX, X86::RDX, X86::R8, X86::R9
1421 };
1422 return GPR64ArgRegsWin64;
1423 }
1424
1425 static const MCPhysReg GPR64ArgRegs64Bit[] = {
1426 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1427 };
1428 return GPR64ArgRegs64Bit;
1429}
1430
1431// FIXME: Get this from tablegen.
1432static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
1433 CallingConv::ID CallConv,
1434 const X86Subtarget &Subtarget) {
1435 assert(Subtarget.is64Bit());
1436 if (Subtarget.isCallingConvWin64(CC: CallConv)) {
1437 // The XMM registers which might contain var arg parameters are shadowed
1438 // in their paired GPR. So we only need to save the GPR to their home
1439 // slots.
1440 // TODO: __vectorcall will change this.
1441 return {};
1442 }
1443
1444 bool isSoftFloat = Subtarget.useSoftFloat();
1445 if (isSoftFloat || !Subtarget.hasSSE1())
1446 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
1447 // registers.
1448 return {};
1449
1450 static const MCPhysReg XMMArgRegs64Bit[] = {
1451 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1452 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1453 };
1454 return XMMArgRegs64Bit;
1455}
1456
1457#ifndef NDEBUG
1458static bool isSortedByValueNo(ArrayRef<CCValAssign> ArgLocs) {
1459 return llvm::is_sorted(
1460 ArgLocs, [](const CCValAssign &A, const CCValAssign &B) -> bool {
1461 return A.getValNo() < B.getValNo();
1462 });
1463}
1464#endif
1465
1466namespace {
1467/// This is a helper class for lowering variable arguments parameters.
1468class VarArgsLoweringHelper {
1469public:
1470 VarArgsLoweringHelper(X86MachineFunctionInfo *FuncInfo, const SDLoc &Loc,
1471 SelectionDAG &DAG, const X86Subtarget &Subtarget,
1472 CallingConv::ID CallConv, CCState &CCInfo)
1473 : FuncInfo(FuncInfo), DL(Loc), DAG(DAG), Subtarget(Subtarget),
1474 TheMachineFunction(DAG.getMachineFunction()),
1475 TheFunction(TheMachineFunction.getFunction()),
1476 FrameInfo(TheMachineFunction.getFrameInfo()),
1477 FrameLowering(*Subtarget.getFrameLowering()),
1478 TargLowering(DAG.getTargetLoweringInfo()), CallConv(CallConv),
1479 CCInfo(CCInfo) {}
1480
1481 // Lower variable arguments parameters.
1482 void lowerVarArgsParameters(SDValue &Chain, unsigned StackSize);
1483
1484private:
1485 void createVarArgAreaAndStoreRegisters(SDValue &Chain, unsigned StackSize);
1486
1487 void forwardMustTailParameters(SDValue &Chain);
1488
1489 bool is64Bit() const { return Subtarget.is64Bit(); }
1490 bool isWin64() const { return Subtarget.isCallingConvWin64(CC: CallConv); }
1491
1492 X86MachineFunctionInfo *FuncInfo;
1493 const SDLoc &DL;
1494 SelectionDAG &DAG;
1495 const X86Subtarget &Subtarget;
1496 MachineFunction &TheMachineFunction;
1497 const Function &TheFunction;
1498 MachineFrameInfo &FrameInfo;
1499 const TargetFrameLowering &FrameLowering;
1500 const TargetLowering &TargLowering;
1501 CallingConv::ID CallConv;
1502 CCState &CCInfo;
1503};
1504} // namespace
1505
1506void VarArgsLoweringHelper::createVarArgAreaAndStoreRegisters(
1507 SDValue &Chain, unsigned StackSize) {
1508 // If the function takes variable number of arguments, make a frame index for
1509 // the start of the first vararg value... for expansion of llvm.va_start. We
1510 // can skip this if there are no va_start calls.
1511 if (is64Bit() || (CallConv != CallingConv::X86_FastCall &&
1512 CallConv != CallingConv::X86_ThisCall)) {
1513 FuncInfo->setVarArgsFrameIndex(
1514 FrameInfo.CreateFixedObject(Size: 1, SPOffset: StackSize, IsImmutable: true));
1515 }
1516
1517 // 64-bit calling conventions support varargs and register parameters, so we
1518 // have to do extra work to spill them in the prologue.
1519 if (is64Bit()) {
1520 // Find the first unallocated argument registers.
1521 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
1522 ArrayRef<MCPhysReg> ArgXMMs =
1523 get64BitArgumentXMMs(MF&: TheMachineFunction, CallConv, Subtarget);
1524 unsigned NumIntRegs = CCInfo.getFirstUnallocated(Regs: ArgGPRs);
1525 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(Regs: ArgXMMs);
1526
1527 assert(!(NumXMMRegs && !Subtarget.hasSSE1()) &&
1528 "SSE register cannot be used when SSE is disabled!");
1529
1530 if (isWin64()) {
1531 // Get to the caller-allocated home save location. Add 8 to account
1532 // for the return address.
1533 int HomeOffset = FrameLowering.getOffsetOfLocalArea() + 8;
1534 FuncInfo->setRegSaveFrameIndex(
1535 FrameInfo.CreateFixedObject(Size: 1, SPOffset: NumIntRegs * 8 + HomeOffset, IsImmutable: false));
1536 // Fixup to set vararg frame on shadow area (4 x i64).
1537 if (NumIntRegs < 4)
1538 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1539 } else {
1540 // For X86-64, if there are vararg parameters that are passed via
1541 // registers, then we must store them to their spots on the stack so
1542 // they may be loaded by dereferencing the result of va_next.
1543 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1544 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
1545 FuncInfo->setRegSaveFrameIndex(FrameInfo.CreateStackObject(
1546 Size: ArgGPRs.size() * 8 + ArgXMMs.size() * 16, Alignment: Align(16), isSpillSlot: false));
1547 }
1548
1549 SmallVector<SDValue, 6>
1550 LiveGPRs; // list of SDValue for GPR registers keeping live input value
1551 SmallVector<SDValue, 8> LiveXMMRegs; // list of SDValue for XMM registers
1552 // keeping live input value
1553 SDValue ALVal; // if applicable keeps SDValue for %al register
1554
1555 // Gather all the live in physical registers.
1556 for (MCPhysReg Reg : ArgGPRs.slice(N: NumIntRegs)) {
1557 Register GPR = TheMachineFunction.addLiveIn(PReg: Reg, RC: &X86::GR64RegClass);
1558 LiveGPRs.push_back(Elt: DAG.getCopyFromReg(Chain, dl: DL, Reg: GPR, VT: MVT::i64));
1559 }
1560 const auto &AvailableXmms = ArgXMMs.slice(N: NumXMMRegs);
1561 if (!AvailableXmms.empty()) {
1562 Register AL = TheMachineFunction.addLiveIn(PReg: X86::AL, RC: &X86::GR8RegClass);
1563 ALVal = DAG.getCopyFromReg(Chain, dl: DL, Reg: AL, VT: MVT::i8);
1564 for (MCPhysReg Reg : AvailableXmms) {
1565 // FastRegisterAllocator spills virtual registers at basic
1566 // block boundary. That leads to usages of xmm registers
1567 // outside of check for %al. Pass physical registers to
1568 // VASTART_SAVE_XMM_REGS to avoid unneccessary spilling.
1569 TheMachineFunction.getRegInfo().addLiveIn(Reg);
1570 LiveXMMRegs.push_back(Elt: DAG.getRegister(Reg, VT: MVT::v4f32));
1571 }
1572 }
1573
1574 // Store the integer parameter registers.
1575 SmallVector<SDValue, 8> MemOps;
1576 SDValue RSFIN =
1577 DAG.getFrameIndex(FI: FuncInfo->getRegSaveFrameIndex(),
1578 VT: TargLowering.getPointerTy(DL: DAG.getDataLayout()));
1579 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1580 for (SDValue Val : LiveGPRs) {
1581 SDValue FIN = DAG.getNode(Opcode: ISD::ADD, DL,
1582 VT: TargLowering.getPointerTy(DL: DAG.getDataLayout()),
1583 N1: RSFIN, N2: DAG.getIntPtrConstant(Val: Offset, DL));
1584 SDValue Store =
1585 DAG.getStore(Chain: Val.getValue(R: 1), dl: DL, Val, Ptr: FIN,
1586 PtrInfo: MachinePointerInfo::getFixedStack(
1587 MF&: DAG.getMachineFunction(),
1588 FI: FuncInfo->getRegSaveFrameIndex(), Offset));
1589 MemOps.push_back(Elt: Store);
1590 Offset += 8;
1591 }
1592
1593 // Now store the XMM (fp + vector) parameter registers.
1594 if (!LiveXMMRegs.empty()) {
1595 SmallVector<SDValue, 12> SaveXMMOps;
1596 SaveXMMOps.push_back(Elt: Chain);
1597 SaveXMMOps.push_back(Elt: ALVal);
1598 SaveXMMOps.push_back(Elt: RSFIN);
1599 SaveXMMOps.push_back(
1600 Elt: DAG.getTargetConstant(Val: FuncInfo->getVarArgsFPOffset(), DL, VT: MVT::i32));
1601 llvm::append_range(C&: SaveXMMOps, R&: LiveXMMRegs);
1602 MachineMemOperand *StoreMMO =
1603 DAG.getMachineFunction().getMachineMemOperand(
1604 PtrInfo: MachinePointerInfo::getFixedStack(
1605 MF&: DAG.getMachineFunction(), FI: FuncInfo->getRegSaveFrameIndex(),
1606 Offset),
1607 F: MachineMemOperand::MOStore, Size: 128, BaseAlignment: Align(16));
1608 MemOps.push_back(Elt: DAG.getMemIntrinsicNode(Opcode: X86ISD::VASTART_SAVE_XMM_REGS,
1609 dl: DL, VTList: DAG.getVTList(VT: MVT::Other),
1610 Ops: SaveXMMOps, MemVT: MVT::i8, MMO: StoreMMO));
1611 }
1612
1613 if (!MemOps.empty())
1614 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, Ops: MemOps);
1615 }
1616}
1617
1618void VarArgsLoweringHelper::forwardMustTailParameters(SDValue &Chain) {
1619 // Find the largest legal vector type.
1620 MVT VecVT = MVT::Other;
1621 // FIXME: Only some x86_32 calling conventions support AVX512.
1622 if (Subtarget.useAVX512Regs() &&
1623 (is64Bit() || (CallConv == CallingConv::X86_VectorCall ||
1624 CallConv == CallingConv::Intel_OCL_BI)))
1625 VecVT = MVT::v16f32;
1626 else if (Subtarget.hasAVX())
1627 VecVT = MVT::v8f32;
1628 else if (Subtarget.hasSSE2())
1629 VecVT = MVT::v4f32;
1630
1631 // We forward some GPRs and some vector types.
1632 SmallVector<MVT, 2> RegParmTypes;
1633 MVT IntVT = is64Bit() ? MVT::i64 : MVT::i32;
1634 RegParmTypes.push_back(Elt: IntVT);
1635 if (VecVT != MVT::Other)
1636 RegParmTypes.push_back(Elt: VecVT);
1637
1638 // Compute the set of forwarded registers. The rest are scratch.
1639 SmallVectorImpl<ForwardedRegister> &Forwards =
1640 FuncInfo->getForwardedMustTailRegParms();
1641 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, Fn: CC_X86);
1642
1643 // Forward AL for SysV x86_64 targets, since it is used for varargs.
1644 if (is64Bit() && !isWin64() && !CCInfo.isAllocated(Reg: X86::AL)) {
1645 Register ALVReg = TheMachineFunction.addLiveIn(PReg: X86::AL, RC: &X86::GR8RegClass);
1646 Forwards.push_back(Elt: ForwardedRegister(ALVReg, X86::AL, MVT::i8));
1647 }
1648
1649 // Copy all forwards from physical to virtual registers.
1650 for (ForwardedRegister &FR : Forwards) {
1651 // FIXME: Can we use a less constrained schedule?
1652 SDValue RegVal = DAG.getCopyFromReg(Chain, dl: DL, Reg: FR.VReg, VT: FR.VT);
1653 FR.VReg = TheMachineFunction.getRegInfo().createVirtualRegister(
1654 RegClass: TargLowering.getRegClassFor(VT: FR.VT));
1655 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: FR.VReg, N: RegVal);
1656 }
1657}
1658
1659void VarArgsLoweringHelper::lowerVarArgsParameters(SDValue &Chain,
1660 unsigned StackSize) {
1661 // Set FrameIndex to the 0xAAAAAAA value to mark unset state.
1662 // If necessary, it would be set into the correct value later.
1663 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1664 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1665
1666 if (FrameInfo.hasVAStart())
1667 createVarArgAreaAndStoreRegisters(Chain, StackSize);
1668
1669 if (FrameInfo.hasMustTailInVarArgFunc())
1670 forwardMustTailParameters(Chain);
1671}
1672
1673SDValue X86TargetLowering::LowerFormalArguments(
1674 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
1675 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1676 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1677 MachineFunction &MF = DAG.getMachineFunction();
1678 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1679
1680 const Function &F = MF.getFunction();
1681 if (F.hasExternalLinkage() && Subtarget.isTargetCygMing() &&
1682 F.getName() == "main")
1683 FuncInfo->setForceFramePointer(true);
1684
1685 MachineFrameInfo &MFI = MF.getFrameInfo();
1686 bool Is64Bit = Subtarget.is64Bit();
1687 bool IsWin64 = Subtarget.isCallingConvWin64(CC: CallConv);
1688
1689 // On x86_64 with x87 disabled, x86_fp80 cannot be handled: the type would
1690 // need to be returned/passed in x87 registers (FP0/FP1) which are
1691 // unavailable. Emit a clear diagnostic instead of crashing later with
1692 // "Cannot select: build_pair".
1693 if (Is64Bit && !Subtarget.hasX87()) {
1694 if (F.getReturnType()->isX86_FP80Ty() ||
1695 any_of(Range: F.args(), P: [](const Argument &Arg) {
1696 return Arg.getType()->isX86_FP80Ty();
1697 }))
1698 reportFatalUsageError(
1699 reason: "cannot use x86_fp80 type with x87 disabled on x86_64 target");
1700 }
1701
1702 assert(
1703 !(IsVarArg && canGuaranteeTCO(CallConv)) &&
1704 "Var args not supported with calling conv' regcall, fastcc, ghc or hipe");
1705
1706 // Assign locations to all of the incoming arguments.
1707 SmallVector<CCValAssign, 16> ArgLocs;
1708 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
1709
1710 // Allocate shadow area for Win64.
1711 if (IsWin64)
1712 CCInfo.AllocateStack(Size: 32, Alignment: Align(8));
1713
1714 CCInfo.AnalyzeArguments(Ins, Fn: CC_X86);
1715
1716 // In vectorcall calling convention a second pass is required for the HVA
1717 // types.
1718 if (CallingConv::X86_VectorCall == CallConv) {
1719 CCInfo.AnalyzeArgumentsSecondPass(Args: Ins, Fn: CC_X86);
1720 }
1721
1722 // The next loop assumes that the locations are in the same order of the
1723 // input arguments.
1724 assert(isSortedByValueNo(ArgLocs) &&
1725 "Argument Location list must be sorted before lowering");
1726
1727 SDValue ArgValue;
1728 for (unsigned I = 0, InsIndex = 0, E = ArgLocs.size(); I != E;
1729 ++I, ++InsIndex) {
1730 assert(InsIndex < Ins.size() && "Invalid Ins index");
1731 CCValAssign &VA = ArgLocs[I];
1732
1733 if (VA.isRegLoc()) {
1734 EVT RegVT = VA.getLocVT();
1735 if (VA.needsCustom()) {
1736 assert(
1737 VA.getValVT() == MVT::v64i1 &&
1738 "Currently the only custom case is when we split v64i1 to 2 regs");
1739
1740 // v64i1 values, in regcall calling convention, that are
1741 // compiled to 32 bit arch, are split up into two registers.
1742 ArgValue =
1743 getv64i1Argument(VA, NextVA&: ArgLocs[++I], Root&: Chain, DAG, DL: dl, Subtarget);
1744 } else {
1745 const TargetRegisterClass *RC;
1746 if (RegVT == MVT::i8)
1747 RC = &X86::GR8RegClass;
1748 else if (RegVT == MVT::i16)
1749 RC = &X86::GR16RegClass;
1750 else if (RegVT == MVT::i32)
1751 RC = &X86::GR32RegClass;
1752 else if (Is64Bit && RegVT == MVT::i64)
1753 RC = &X86::GR64RegClass;
1754 else if (RegVT == MVT::f16)
1755 RC = Subtarget.hasAVX512() ? &X86::FR16XRegClass : &X86::FR16RegClass;
1756 else if (RegVT == MVT::f32)
1757 RC = Subtarget.hasAVX512() ? &X86::FR32XRegClass : &X86::FR32RegClass;
1758 else if (RegVT == MVT::f64)
1759 RC = Subtarget.hasAVX512() ? &X86::FR64XRegClass : &X86::FR64RegClass;
1760 else if (RegVT == MVT::f80)
1761 RC = &X86::RFP80RegClass;
1762 else if (RegVT == MVT::f128)
1763 RC = &X86::VR128RegClass;
1764 else if (RegVT.is512BitVector())
1765 RC = &X86::VR512RegClass;
1766 else if (RegVT.is256BitVector())
1767 RC = Subtarget.hasVLX() ? &X86::VR256XRegClass : &X86::VR256RegClass;
1768 else if (RegVT.is128BitVector())
1769 RC = Subtarget.hasVLX() ? &X86::VR128XRegClass : &X86::VR128RegClass;
1770 else if (RegVT == MVT::x86mmx)
1771 RC = &X86::VR64RegClass;
1772 else if (RegVT == MVT::v1i1)
1773 RC = &X86::VK1RegClass;
1774 else if (RegVT == MVT::v8i1)
1775 RC = &X86::VK8RegClass;
1776 else if (RegVT == MVT::v16i1)
1777 RC = &X86::VK16RegClass;
1778 else if (RegVT == MVT::v32i1)
1779 RC = &X86::VK32RegClass;
1780 else if (RegVT == MVT::v64i1)
1781 RC = &X86::VK64RegClass;
1782 else
1783 llvm_unreachable("Unknown argument type!");
1784
1785 Register Reg = MF.addLiveIn(PReg: VA.getLocReg(), RC);
1786 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, VT: RegVT);
1787 }
1788
1789 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1790 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1791 // right size.
1792 if (VA.getLocInfo() == CCValAssign::SExt)
1793 ArgValue = DAG.getNode(Opcode: ISD::AssertSext, DL: dl, VT: RegVT, N1: ArgValue,
1794 N2: DAG.getValueType(VA.getValVT()));
1795 else if (VA.getLocInfo() == CCValAssign::ZExt)
1796 ArgValue = DAG.getNode(Opcode: ISD::AssertZext, DL: dl, VT: RegVT, N1: ArgValue,
1797 N2: DAG.getValueType(VA.getValVT()));
1798 else if (VA.getLocInfo() == CCValAssign::BCvt)
1799 ArgValue = DAG.getBitcast(VT: VA.getValVT(), V: ArgValue);
1800
1801 if (VA.isExtInLoc()) {
1802 // Handle MMX values passed in XMM regs.
1803 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
1804 ArgValue = DAG.getNode(Opcode: X86ISD::MOVDQ2Q, DL: dl, VT: VA.getValVT(), Operand: ArgValue);
1805 else if (VA.getValVT().isVector() &&
1806 VA.getValVT().getScalarType() == MVT::i1 &&
1807 ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) ||
1808 (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) {
1809 // Promoting a mask type (v*i1) into a register of type i64/i32/i16/i8
1810 ArgValue = lowerRegToMasks(ValArg: ArgValue, ValVT: VA.getValVT(), ValLoc: RegVT, DL: dl, DAG);
1811 } else
1812 ArgValue = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: VA.getValVT(), Operand: ArgValue);
1813 }
1814 } else {
1815 assert(VA.isMemLoc());
1816 ArgValue =
1817 LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i: InsIndex);
1818 }
1819
1820 // If value is passed via pointer - do a load.
1821 if (VA.getLocInfo() == CCValAssign::Indirect &&
1822 !(Ins[I].Flags.isByVal() && VA.isRegLoc())) {
1823 ArgValue =
1824 DAG.getLoad(VT: VA.getValVT(), dl, Chain, Ptr: ArgValue, PtrInfo: MachinePointerInfo());
1825 }
1826
1827 InVals.push_back(Elt: ArgValue);
1828 }
1829
1830 for (unsigned I = 0, E = Ins.size(); I != E; ++I) {
1831 if (Ins[I].Flags.isSwiftAsync()) {
1832 auto X86FI = MF.getInfo<X86MachineFunctionInfo>();
1833 if (X86::isExtendedSwiftAsyncFrameSupported(Subtarget, MF))
1834 X86FI->setHasSwiftAsyncContext(true);
1835 else {
1836 int PtrSize = Subtarget.is64Bit() ? 8 : 4;
1837 int FI =
1838 MF.getFrameInfo().CreateStackObject(Size: PtrSize, Alignment: Align(PtrSize), isSpillSlot: false);
1839 X86FI->setSwiftAsyncContextFrameIdx(FI);
1840 SDValue St = DAG.getStore(
1841 Chain: DAG.getEntryNode(), dl, Val: InVals[I],
1842 Ptr: DAG.getFrameIndex(FI, VT: PtrSize == 8 ? MVT::i64 : MVT::i32),
1843 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI));
1844 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: St, N2: Chain);
1845 }
1846 }
1847
1848 // Swift calling convention does not require we copy the sret argument
1849 // into %rax/%eax for the return. We don't set SRetReturnReg for Swift.
1850 if (CallConv == CallingConv::Swift || CallConv == CallingConv::SwiftTail)
1851 continue;
1852
1853 // All x86 ABIs require that for returning structs by value we copy the
1854 // sret argument into %rax/%eax (depending on ABI) for the return. Save
1855 // the argument into a virtual register so that we can access it from the
1856 // return points.
1857 if (Ins[I].Flags.isSRet()) {
1858 assert(!FuncInfo->getSRetReturnReg() &&
1859 "SRet return has already been set");
1860 MVT PtrTy = getPointerTy(DL: DAG.getDataLayout());
1861 Register Reg =
1862 MF.getRegInfo().createVirtualRegister(RegClass: getRegClassFor(VT: PtrTy));
1863 FuncInfo->setSRetReturnReg(Reg);
1864 SDValue Copy = DAG.getCopyToReg(Chain: DAG.getEntryNode(), dl, Reg, N: InVals[I]);
1865 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Copy, N2: Chain);
1866 break;
1867 }
1868 }
1869
1870 unsigned StackSize = CCInfo.getStackSize();
1871 // Align stack specially for tail calls.
1872 if (shouldGuaranteeTCO(CC: CallConv,
1873 GuaranteedTailCallOpt: MF.getTarget().Options.GuaranteedTailCallOpt))
1874 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1875
1876 if (IsVarArg)
1877 VarArgsLoweringHelper(FuncInfo, dl, DAG, Subtarget, CallConv, CCInfo)
1878 .lowerVarArgsParameters(Chain, StackSize);
1879
1880 // Some CCs need callee pop.
1881 if (X86::isCalleePop(CallingConv: CallConv, is64Bit: Is64Bit, IsVarArg,
1882 GuaranteeTCO: MF.getTarget().Options.GuaranteedTailCallOpt)) {
1883 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1884 } else if (CallConv == CallingConv::X86_INTR && Ins.size() == 2) {
1885 // X86 interrupts must pop the error code (and the alignment padding) if
1886 // present.
1887 FuncInfo->setBytesToPopOnReturn(Is64Bit ? 16 : 4);
1888 } else {
1889 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1890 // If this is an sret function, the return should pop the hidden pointer.
1891 if (hasCalleePopSRet(Args: Ins, ArgLocs, Subtarget))
1892 FuncInfo->setBytesToPopOnReturn(4);
1893 }
1894
1895 if (!Is64Bit) {
1896 // RegSaveFrameIndex is X86-64 only.
1897 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1898 }
1899
1900 FuncInfo->setArgumentStackSize(StackSize);
1901
1902 if (WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo()) {
1903 EHPersonality Personality = classifyEHPersonality(Pers: F.getPersonalityFn());
1904 if (Personality == EHPersonality::CoreCLR) {
1905 assert(Is64Bit);
1906 // TODO: Add a mechanism to frame lowering that will allow us to indicate
1907 // that we'd prefer this slot be allocated towards the bottom of the frame
1908 // (i.e. near the stack pointer after allocating the frame). Every
1909 // funclet needs a copy of this slot in its (mostly empty) frame, and the
1910 // offset from the bottom of this and each funclet's frame must be the
1911 // same, so the size of funclets' (mostly empty) frames is dictated by
1912 // how far this slot is from the bottom (since they allocate just enough
1913 // space to accommodate holding this slot at the correct offset).
1914 int PSPSymFI = MFI.CreateStackObject(Size: 8, Alignment: Align(8), /*isSpillSlot=*/false);
1915 EHInfo->PSPSymFrameIdx = PSPSymFI;
1916 }
1917 }
1918
1919 if (shouldDisableArgRegFromCSR(CC: CallConv) ||
1920 F.hasFnAttribute(Kind: "no_caller_saved_registers")) {
1921 MachineRegisterInfo &MRI = MF.getRegInfo();
1922 for (std::pair<MCRegister, Register> Pair : MRI.liveins())
1923 MRI.disableCalleeSavedRegister(Reg: Pair.first);
1924 }
1925
1926 if (CallingConv::PreserveNone == CallConv)
1927 for (const ISD::InputArg &In : Ins) {
1928 if (In.Flags.isSwiftSelf() || In.Flags.isSwiftAsync() ||
1929 In.Flags.isSwiftError()) {
1930 errorUnsupported(DAG, dl,
1931 Msg: "Swift attributes can't be used with preserve_none");
1932 break;
1933 }
1934 }
1935
1936 return Chain;
1937}
1938
1939SDValue X86TargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
1940 SDValue Arg, const SDLoc &dl,
1941 SelectionDAG &DAG,
1942 const CCValAssign &VA,
1943 ISD::ArgFlagsTy Flags,
1944 bool isByVal) const {
1945 unsigned LocMemOffset = VA.getLocMemOffset();
1946 SDValue PtrOff = DAG.getIntPtrConstant(Val: LocMemOffset, DL: dl);
1947 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: getPointerTy(DL: DAG.getDataLayout()),
1948 N1: StackPtr, N2: PtrOff);
1949 if (isByVal)
1950 return CreateCopyOfByValArgument(Src: Arg, Dst: PtrOff, Chain, Flags, DAG, dl);
1951
1952 MaybeAlign Alignment;
1953 if (Subtarget.isTargetWindowsMSVC() && !Subtarget.is64Bit() &&
1954 Arg.getSimpleValueType() != MVT::f80)
1955 Alignment = MaybeAlign(4);
1956 return DAG.getStore(
1957 Chain, dl, Val: Arg, Ptr: PtrOff,
1958 PtrInfo: MachinePointerInfo::getStack(MF&: DAG.getMachineFunction(), Offset: LocMemOffset),
1959 Alignment);
1960}
1961
1962/// Emit a load of return address if tail call
1963/// optimization is performed and it is required.
1964SDValue X86TargetLowering::EmitTailCallLoadRetAddr(
1965 SelectionDAG &DAG, SDValue &OutRetAddr, SDValue Chain, bool IsTailCall,
1966 bool Is64Bit, int FPDiff, const SDLoc &dl) const {
1967 // Adjust the Return address stack slot.
1968 EVT VT = getPointerTy(DL: DAG.getDataLayout());
1969 OutRetAddr = getReturnAddressFrameIndex(DAG);
1970
1971 // Load the "old" Return address.
1972 OutRetAddr = DAG.getLoad(VT, dl, Chain, Ptr: OutRetAddr, PtrInfo: MachinePointerInfo());
1973 return SDValue(OutRetAddr.getNode(), 1);
1974}
1975
1976/// Emit a store of the return address if tail call
1977/// optimization is performed and it is required (FPDiff!=0).
1978static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
1979 SDValue Chain, SDValue RetAddrFrIdx,
1980 EVT PtrVT, unsigned SlotSize,
1981 int FPDiff, const SDLoc &dl) {
1982 // Store the return address to the appropriate stack slot.
1983 if (!FPDiff) return Chain;
1984 // Calculate the new stack slot for the return address.
1985 int NewReturnAddrFI =
1986 MF.getFrameInfo().CreateFixedObject(Size: SlotSize, SPOffset: (int64_t)FPDiff - SlotSize,
1987 IsImmutable: false);
1988 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(FI: NewReturnAddrFI, VT: PtrVT);
1989 Chain = DAG.getStore(Chain, dl, Val: RetAddrFrIdx, Ptr: NewRetAddrFrIdx,
1990 PtrInfo: MachinePointerInfo::getFixedStack(
1991 MF&: DAG.getMachineFunction(), FI: NewReturnAddrFI));
1992 return Chain;
1993}
1994
1995/// Returns a vector_shuffle mask for an movs{s|d}, movd
1996/// operation of specified width.
1997SDValue X86TargetLowering::getMOVL(SelectionDAG &DAG, const SDLoc &dl, MVT VT,
1998 SDValue V1, SDValue V2) const {
1999 unsigned NumElems = VT.getVectorNumElements();
2000 SmallVector<int, 8> Mask;
2001 Mask.push_back(Elt: NumElems);
2002 for (unsigned i = 1; i != NumElems; ++i)
2003 Mask.push_back(Elt: i);
2004 return DAG.getVectorShuffle(VT, dl, N1: V1, N2: V2, Mask);
2005}
2006
2007// Returns the type of copying which is required to set up a byval argument to
2008// a tail-called function. This isn't needed for non-tail calls, because they
2009// always need the equivalent of CopyOnce, but tail-calls sometimes need two to
2010// avoid clobbering another argument (CopyViaTemp), and sometimes can be
2011// optimised to zero copies when forwarding an argument from the caller's
2012// caller (NoCopy).
2013X86TargetLowering::ByValCopyKind X86TargetLowering::ByValNeedsCopyForTailCall(
2014 SelectionDAG &DAG, SDValue Src, SDValue Dst, ISD::ArgFlagsTy Flags) const {
2015 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2016
2017 // Globals are always safe to copy from.
2018 if (isa<GlobalAddressSDNode>(Val: Src) || isa<ExternalSymbolSDNode>(Val: Src))
2019 return CopyOnce;
2020
2021 // Can only analyse frame index nodes, conservatively assume we need a
2022 // temporary.
2023 auto *SrcFrameIdxNode = dyn_cast<FrameIndexSDNode>(Val&: Src);
2024 auto *DstFrameIdxNode = dyn_cast<FrameIndexSDNode>(Val&: Dst);
2025 if (!SrcFrameIdxNode || !DstFrameIdxNode)
2026 return CopyViaTemp;
2027
2028 int SrcFI = SrcFrameIdxNode->getIndex();
2029 int DstFI = DstFrameIdxNode->getIndex();
2030 assert(MFI.isFixedObjectIndex(DstFI) &&
2031 "byval passed in non-fixed stack slot");
2032
2033 int64_t SrcOffset = MFI.getObjectOffset(ObjectIdx: SrcFI);
2034 int64_t DstOffset = MFI.getObjectOffset(ObjectIdx: DstFI);
2035
2036 // If the source is in the local frame, then the copy to the argument
2037 // memory is always valid.
2038 bool FixedSrc = MFI.isFixedObjectIndex(ObjectIdx: SrcFI);
2039 if (!FixedSrc || (FixedSrc && SrcOffset < 0))
2040 return CopyOnce;
2041
2042 // If the value is already in the correct location, then no copying is
2043 // needed. If not, then we need to copy via a temporary.
2044 if (SrcOffset == DstOffset)
2045 return NoCopy;
2046 else
2047 return CopyViaTemp;
2048}
2049
2050SDValue
2051X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2052 SmallVectorImpl<SDValue> &InVals) const {
2053 SelectionDAG &DAG = CLI.DAG;
2054 SDLoc &dl = CLI.DL;
2055 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2056 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2057 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2058 SDValue Chain = CLI.Chain;
2059 SDValue Callee = CLI.Callee;
2060 CallingConv::ID CallConv = CLI.CallConv;
2061 bool &isTailCall = CLI.IsTailCall;
2062 bool isVarArg = CLI.IsVarArg;
2063 const auto *CB = CLI.CB;
2064
2065 MachineFunction &MF = DAG.getMachineFunction();
2066 bool Is64Bit = Subtarget.is64Bit();
2067 bool IsWin64 = Subtarget.isCallingConvWin64(CC: CallConv);
2068 bool ShouldGuaranteeTCO = shouldGuaranteeTCO(
2069 CC: CallConv, GuaranteedTailCallOpt: MF.getTarget().Options.GuaranteedTailCallOpt);
2070 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2071 bool HasNCSR = (CB && isa<CallInst>(Val: CB) &&
2072 CB->hasFnAttr(Kind: "no_caller_saved_registers"));
2073 bool IsIndirectCall = (CB && isa<CallInst>(Val: CB) && CB->isIndirectCall());
2074 bool IsCFICall = IsIndirectCall && CLI.CFIType;
2075 const Module *M = MF.getFunction().getParent();
2076
2077 // If the indirect call target has the nocf_check attribute, the call needs
2078 // the NOTRACK prefix. For simplicity just disable tail calls as there are
2079 // so many variants.
2080 // FIXME: This will cause backend errors if the user forces the issue.
2081 bool IsNoTrackIndirectCall = IsIndirectCall && CB->doesNoCfCheck() &&
2082 M->getModuleFlag(Key: "cf-protection-branch");
2083 if (IsNoTrackIndirectCall)
2084 isTailCall = false;
2085
2086 MachineFunction::CallSiteInfo CSInfo;
2087 if (CallConv == CallingConv::X86_INTR)
2088 report_fatal_error(reason: "X86 interrupts may not be called directly");
2089
2090 // Set type id for call site info.
2091 setTypeIdForCallsiteInfo(CB, MF, CSInfo);
2092
2093 if (IsIndirectCall && !IsWin64 &&
2094 M->getModuleFlag(Key: "import-call-optimization"))
2095 errorUnsupported(DAG, dl,
2096 Msg: "Indirect calls must have a normal calling convention if "
2097 "Import Call Optimization is enabled");
2098
2099 // Analyze operands of the call, assigning locations to each operand.
2100 SmallVector<CCValAssign, 16> ArgLocs;
2101 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2102
2103 // Allocate shadow area for Win64.
2104 if (IsWin64)
2105 CCInfo.AllocateStack(Size: 32, Alignment: Align(8));
2106
2107 CCInfo.AnalyzeArguments(Outs, Fn: CC_X86);
2108
2109 // In vectorcall calling convention a second pass is required for the HVA
2110 // types.
2111 if (CallingConv::X86_VectorCall == CallConv) {
2112 CCInfo.AnalyzeArgumentsSecondPass(Args: Outs, Fn: CC_X86);
2113 }
2114
2115 // We cannot guarantee TCO for mismatched calling conventions.
2116 if (isTailCall && ShouldGuaranteeTCO) {
2117 CallingConv::ID CallerCC = MF.getFunction().getCallingConv();
2118 isTailCall = (CallConv == CallerCC);
2119 }
2120
2121 // Check if this tail call is a "sibling" call, which is loosely defined to
2122 // be a tail call that doesn't require heroics like moving the return
2123 // address or swapping byval arguments. We treat some musttail calls as
2124 // sibling calls to avoid unnecessary argument copies.
2125 bool IsMustTail = CLI.CB && CLI.CB->isMustTailCall();
2126 bool IsSibcall = false;
2127 if (isTailCall) {
2128 IsSibcall = isEligibleForSiblingCallOpt(CLI, CCInfo, ArgLocs);
2129 isTailCall = IsSibcall || IsMustTail || ShouldGuaranteeTCO;
2130 }
2131
2132 if (isTailCall)
2133 ++NumTailCalls;
2134
2135 if (IsMustTail && !isTailCall)
2136 report_fatal_error(reason: "failed to perform tail call elimination on a call "
2137 "site marked musttail");
2138
2139 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
2140 "Var args not supported with calling convention fastcc, ghc or hipe");
2141
2142 // Get a count of how many bytes are to be pushed on the stack.
2143 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
2144 if (IsSibcall)
2145 // This is a sibcall. The memory operands are available in caller's
2146 // own caller's stack.
2147 NumBytes = 0;
2148 else if (ShouldGuaranteeTCO && canGuaranteeTCO(CC: CallConv))
2149 NumBytes = GetAlignedArgumentStackSize(StackSize: NumBytes, DAG);
2150
2151 // A sibcall is ABI-compatible and does not need to adjust the stack pointer.
2152 int FPDiff = 0;
2153 if (isTailCall && ShouldGuaranteeTCO && !IsSibcall) {
2154 // Lower arguments at fp - stackoffset + fpdiff.
2155 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2156
2157 FPDiff = NumBytesCallerPushed - NumBytes;
2158
2159 // Set the delta of movement of the returnaddr stackslot.
2160 // But only set if delta is greater than previous delta.
2161 if (FPDiff < X86Info->getTCReturnAddrDelta())
2162 X86Info->setTCReturnAddrDelta(FPDiff);
2163 }
2164
2165 unsigned NumBytesToPush = NumBytes;
2166 unsigned NumBytesToPop = NumBytes;
2167
2168 SDValue StackPtr;
2169 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
2170
2171 // If we are doing a tail-call, any byval arguments will be written to stack
2172 // space which was used for incoming arguments. If any the values being used
2173 // are incoming byval arguments to this function, then they might be
2174 // overwritten by the stores of the outgoing arguments. To avoid this, we
2175 // need to make a temporary copy of them in local stack space, then copy back
2176 // to the argument area.
2177 // FIXME: There's potential to improve the code by using virtual registers for
2178 // temporary storage, and letting the register allocator spill if needed.
2179 SmallVector<SDValue, 8> ByValTemporaries;
2180 SDValue ByValTempChain;
2181 if (isTailCall) {
2182 // Use null SDValue to mean "no temporary recorded for this arg index".
2183 ByValTemporaries.assign(NumElts: OutVals.size(), Elt: SDValue());
2184
2185 SmallVector<SDValue, 8> ByValCopyChains;
2186 for (const CCValAssign &VA : ArgLocs) {
2187 unsigned ArgIdx = VA.getValNo();
2188 SDValue Src = OutVals[ArgIdx];
2189 ISD::ArgFlagsTy Flags = Outs[ArgIdx].Flags;
2190
2191 if (!Flags.isByVal())
2192 continue;
2193
2194 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
2195
2196 if (!StackPtr.getNode())
2197 StackPtr =
2198 DAG.getCopyFromReg(Chain, dl, Reg: RegInfo->getStackRegister(), VT: PtrVT);
2199
2200 // Destination: where this byval should live in the callee’s frame
2201 // after the tail call.
2202 int64_t Offset = VA.getLocMemOffset() + FPDiff;
2203 uint64_t Size = VA.getLocVT().getFixedSizeInBits() / 8;
2204 int FI = MF.getFrameInfo().CreateFixedObject(Size, SPOffset: Offset,
2205 /*IsImmutable=*/true);
2206 SDValue Dst = DAG.getFrameIndex(FI, VT: PtrVT);
2207
2208 ByValCopyKind Copy = ByValNeedsCopyForTailCall(DAG, Src, Dst, Flags);
2209
2210 if (Copy == NoCopy) {
2211 // If the argument is already at the correct offset on the stack
2212 // (because we are forwarding a byval argument from our caller), we
2213 // don't need any copying.
2214 continue;
2215 } else if (Copy == CopyOnce) {
2216 // If the argument is in our local stack frame, no other argument
2217 // preparation can clobber it, so we can copy it to the final location
2218 // later.
2219 ByValTemporaries[ArgIdx] = Src;
2220 } else {
2221 assert(Copy == CopyViaTemp && "unexpected enum value");
2222 // If we might be copying this argument from the outgoing argument
2223 // stack area, we need to copy via a temporary in the local stack
2224 // frame.
2225 MachineFrameInfo &MFI = MF.getFrameInfo();
2226 int TempFrameIdx = MFI.CreateStackObject(Size: Flags.getByValSize(),
2227 Alignment: Flags.getNonZeroByValAlign(),
2228 /*isSS=*/isSpillSlot: false);
2229 SDValue Temp =
2230 DAG.getFrameIndex(FI: TempFrameIdx, VT: getPointerTy(DL: DAG.getDataLayout()));
2231
2232 SDValue CopyChain =
2233 CreateCopyOfByValArgument(Src, Dst: Temp, Chain, Flags, DAG, dl);
2234 ByValCopyChains.push_back(Elt: CopyChain);
2235 ByValTemporaries[ArgIdx] = Temp;
2236 }
2237 }
2238 if (!ByValCopyChains.empty())
2239 ByValTempChain =
2240 DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: ByValCopyChains);
2241 }
2242
2243 // If we have an inalloca argument, all stack space has already been allocated
2244 // for us and be right at the top of the stack. We don't support multiple
2245 // arguments passed in memory when using inalloca.
2246 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2247 NumBytesToPush = 0;
2248 if (!ArgLocs.back().isMemLoc())
2249 report_fatal_error(reason: "cannot use inalloca attribute on a register "
2250 "parameter");
2251 if (ArgLocs.back().getLocMemOffset() != 0)
2252 report_fatal_error(reason: "any parameter with the inalloca attribute must be "
2253 "the only memory argument");
2254 } else if (CLI.IsPreallocated) {
2255 assert(ArgLocs.back().isMemLoc() &&
2256 "cannot use preallocated attribute on a register "
2257 "parameter");
2258 SmallVector<size_t, 4> PreallocatedOffsets;
2259 for (size_t i = 0; i < CLI.OutVals.size(); ++i) {
2260 if (CLI.CB->paramHasAttr(ArgNo: i, Kind: Attribute::Preallocated)) {
2261 PreallocatedOffsets.push_back(Elt: ArgLocs[i].getLocMemOffset());
2262 }
2263 }
2264 auto *MFI = DAG.getMachineFunction().getInfo<X86MachineFunctionInfo>();
2265 size_t PreallocatedId = MFI->getPreallocatedIdForCallSite(CS: CLI.CB);
2266 MFI->setPreallocatedStackSize(Id: PreallocatedId, StackSize: NumBytes);
2267 MFI->setPreallocatedArgOffsets(Id: PreallocatedId, AO: PreallocatedOffsets);
2268 NumBytesToPush = 0;
2269 }
2270
2271 if (!IsSibcall && !IsMustTail)
2272 Chain = DAG.getCALLSEQ_START(Chain, InSize: NumBytesToPush,
2273 OutSize: NumBytes - NumBytesToPush, DL: dl);
2274
2275 SDValue RetAddrFrIdx;
2276 // Load return address for tail calls.
2277 if (isTailCall && FPDiff)
2278 Chain = EmitTailCallLoadRetAddr(DAG, OutRetAddr&: RetAddrFrIdx, Chain, IsTailCall: isTailCall,
2279 Is64Bit, FPDiff, dl);
2280
2281 SmallVector<std::pair<Register, SDValue>, 8> RegsToPass;
2282 SmallVector<SDValue, 8> MemOpChains;
2283
2284 // The next loop assumes that the locations are in the same order of the
2285 // input arguments.
2286 assert(isSortedByValueNo(ArgLocs) &&
2287 "Argument Location list must be sorted before lowering");
2288
2289 // Walk the register/memloc assignments, inserting copies/loads. In the case
2290 // of tail call optimization arguments are handle later.
2291 for (unsigned I = 0, OutIndex = 0, E = ArgLocs.size(); I != E;
2292 ++I, ++OutIndex) {
2293 assert(OutIndex < Outs.size() && "Invalid Out index");
2294 // Skip inalloca/preallocated arguments, they have already been written.
2295 ISD::ArgFlagsTy Flags = Outs[OutIndex].Flags;
2296 if (Flags.isInAlloca() || Flags.isPreallocated())
2297 continue;
2298
2299 CCValAssign &VA = ArgLocs[I];
2300 EVT RegVT = VA.getLocVT();
2301 SDValue Arg = OutVals[OutIndex];
2302 bool isByVal = Flags.isByVal();
2303
2304 // Promote the value if needed.
2305 switch (VA.getLocInfo()) {
2306 default: llvm_unreachable("Unknown loc info!");
2307 case CCValAssign::Full: break;
2308 case CCValAssign::SExt:
2309 Arg = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL: dl, VT: RegVT, Operand: Arg);
2310 break;
2311 case CCValAssign::ZExt:
2312 Arg = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: RegVT, Operand: Arg);
2313 break;
2314 case CCValAssign::AExt:
2315 if (Arg.getValueType().isVector() &&
2316 Arg.getValueType().getVectorElementType() == MVT::i1)
2317 Arg = lowerMasksToReg(ValArg: Arg, ValLoc: RegVT, DL: dl, DAG);
2318 else if (RegVT.is128BitVector()) {
2319 // Special case: passing MMX values in XMM registers.
2320 Arg = DAG.getBitcast(VT: MVT::i64, V: Arg);
2321 Arg = DAG.getNode(Opcode: ISD::SCALAR_TO_VECTOR, DL: dl, VT: MVT::v2i64, Operand: Arg);
2322 Arg = getMOVL(DAG, dl, VT: MVT::v2i64, V1: DAG.getUNDEF(VT: MVT::v2i64), V2: Arg);
2323 } else
2324 Arg = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: RegVT, Operand: Arg);
2325 break;
2326 case CCValAssign::BCvt:
2327 Arg = DAG.getBitcast(VT: RegVT, V: Arg);
2328 break;
2329 case CCValAssign::Indirect: {
2330 if (isByVal) {
2331 // Memcpy the argument to a temporary stack slot to prevent
2332 // the caller from seeing any modifications the callee may make
2333 // as guaranteed by the `byval` attribute.
2334 int FrameIdx = MF.getFrameInfo().CreateStackObject(
2335 Size: Flags.getByValSize(),
2336 Alignment: std::max(a: Align(16), b: Flags.getNonZeroByValAlign()), isSpillSlot: false);
2337 SDValue StackSlot =
2338 DAG.getFrameIndex(FI: FrameIdx, VT: getPointerTy(DL: DAG.getDataLayout()));
2339 Chain =
2340 CreateCopyOfByValArgument(Src: Arg, Dst: StackSlot, Chain, Flags, DAG, dl);
2341 // From now on treat this as a regular pointer
2342 Arg = StackSlot;
2343 isByVal = false;
2344 } else {
2345 // Store the argument.
2346 SDValue SpillSlot = DAG.CreateStackTemporary(VT: VA.getValVT());
2347 int FI = cast<FrameIndexSDNode>(Val&: SpillSlot)->getIndex();
2348 Chain = DAG.getStore(
2349 Chain, dl, Val: Arg, Ptr: SpillSlot,
2350 PtrInfo: MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI));
2351 Arg = SpillSlot;
2352 }
2353 break;
2354 }
2355 }
2356
2357 if (VA.needsCustom()) {
2358 assert(VA.getValVT() == MVT::v64i1 &&
2359 "Currently the only custom case is when we split v64i1 to 2 regs");
2360 // Split v64i1 value into two registers
2361 Passv64i1ArgInRegs(DL: dl, DAG, Arg, RegsToPass, VA, NextVA&: ArgLocs[++I], Subtarget);
2362 } else if (VA.isRegLoc()) {
2363 RegsToPass.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: Arg));
2364 const TargetOptions &Options = DAG.getTarget().Options;
2365 if (Options.EmitCallSiteInfo)
2366 CSInfo.ArgRegPairs.emplace_back(Args: VA.getLocReg(), Args&: I);
2367 if (isVarArg && IsWin64) {
2368 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2369 // shadow reg if callee is a varargs function.
2370 Register ShadowReg;
2371 switch (VA.getLocReg()) {
2372 case X86::XMM0: ShadowReg = X86::RCX; break;
2373 case X86::XMM1: ShadowReg = X86::RDX; break;
2374 case X86::XMM2: ShadowReg = X86::R8; break;
2375 case X86::XMM3: ShadowReg = X86::R9; break;
2376 }
2377 if (ShadowReg)
2378 RegsToPass.push_back(Elt: std::make_pair(x&: ShadowReg, y&: Arg));
2379 }
2380 } else if (!IsSibcall && (!isTailCall || (isByVal && !IsMustTail))) {
2381 assert(VA.isMemLoc());
2382 if (!StackPtr.getNode())
2383 StackPtr = DAG.getCopyFromReg(Chain, dl, Reg: RegInfo->getStackRegister(),
2384 VT: getPointerTy(DL: DAG.getDataLayout()));
2385 MemOpChains.push_back(Elt: LowerMemOpCallTo(Chain, StackPtr, Arg,
2386 dl, DAG, VA, Flags, isByVal));
2387 }
2388 }
2389
2390 if (!MemOpChains.empty())
2391 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: MemOpChains);
2392
2393 if (Subtarget.isPICStyleGOT()) {
2394 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2395 // GOT pointer.
2396 if (!isTailCall) {
2397 // Only PLT calls (GlobalAddress or ExternalSymbol) require the GOT in
2398 // EBX. Indirect calls through a register or an absolute address do not
2399 // go through the PLT and do not need EBX to hold the GOT base.
2400 if ((Callee->getOpcode() == ISD::GlobalAddress ||
2401 Callee->getOpcode() == ISD::ExternalSymbol))
2402 RegsToPass.push_back(Elt: std::make_pair(
2403 x: Register(X86::EBX), y: DAG.getNode(Opcode: X86ISD::GlobalBaseReg, DL: SDLoc(),
2404 VT: getPointerTy(DL: DAG.getDataLayout()))));
2405 } else {
2406 // If we are tail calling and generating PIC/GOT style code load the
2407 // address of the callee into ECX. The value in ecx is used as target of
2408 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2409 // for tail calls on PIC/GOT architectures. Normally we would just put the
2410 // address of GOT into ebx and then call target@PLT. But for tail calls
2411 // ebx would be restored (since ebx is callee saved) before jumping to the
2412 // target@PLT.
2413
2414 // Note: The actual moving to ECX is done further down.
2415 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Val&: Callee);
2416 if (G && !G->getGlobal()->hasLocalLinkage() &&
2417 G->getGlobal()->hasDefaultVisibility())
2418 Callee = LowerGlobalAddress(Op: Callee, DAG);
2419 else if (isa<ExternalSymbolSDNode>(Val: Callee))
2420 Callee = LowerExternalSymbol(Op: Callee, DAG);
2421 }
2422 }
2423
2424 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail &&
2425 (Subtarget.hasSSE1() || !M->getModuleFlag(Key: "SkipRaxSetup"))) {
2426 // From AMD64 ABI document:
2427 // For calls that may call functions that use varargs or stdargs
2428 // (prototype-less calls or calls to functions containing ellipsis (...) in
2429 // the declaration) %al is used as hidden argument to specify the number
2430 // of SSE registers used. The contents of %al do not need to match exactly
2431 // the number of registers, but must be an ubound on the number of SSE
2432 // registers used and is in the range 0 - 8 inclusive.
2433
2434 // Count the number of XMM registers allocated.
2435 static const MCPhysReg XMMArgRegs[] = {
2436 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2437 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2438 };
2439 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(Regs: XMMArgRegs);
2440 assert((Subtarget.hasSSE1() || !NumXMMRegs)
2441 && "SSE registers cannot be used when SSE is disabled");
2442 RegsToPass.push_back(Elt: std::make_pair(x: Register(X86::AL),
2443 y: DAG.getConstant(Val: NumXMMRegs, DL: dl,
2444 VT: MVT::i8)));
2445 }
2446
2447 if (isVarArg && IsMustTail) {
2448 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2449 for (const auto &F : Forwards) {
2450 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg: F.VReg, VT: F.VT);
2451 RegsToPass.push_back(Elt: std::make_pair(x: F.PReg, y&: Val));
2452 }
2453 }
2454
2455 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2456 // don't need this because the eligibility check rejects calls that require
2457 // shuffling arguments passed in memory.
2458 if (isTailCall && !IsSibcall) {
2459 // Force all the incoming stack arguments to be loaded from the stack
2460 // before any new outgoing arguments or the return address are stored to the
2461 // stack, because the outgoing stack slots may alias the incoming argument
2462 // stack slots, and the alias isn't otherwise explicit. This is slightly
2463 // more conservative than necessary, because it means that each store
2464 // effectively depends on every argument instead of just those arguments it
2465 // would clobber.
2466 Chain = DAG.getStackArgumentTokenFactor(Chain);
2467
2468 if (ByValTempChain)
2469 Chain =
2470 DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Chain, N2: ByValTempChain);
2471
2472 SmallVector<SDValue, 8> MemOpChains2;
2473 SDValue FIN;
2474 int FI = 0;
2475 for (unsigned I = 0, OutsIndex = 0, E = ArgLocs.size(); I != E;
2476 ++I, ++OutsIndex) {
2477 CCValAssign &VA = ArgLocs[I];
2478
2479 if (VA.isRegLoc()) {
2480 if (VA.needsCustom()) {
2481 assert((CallConv == CallingConv::X86_RegCall) &&
2482 "Expecting custom case only in regcall calling convention");
2483 // This means that we are in special case where one argument was
2484 // passed through two register locations - Skip the next location
2485 ++I;
2486 }
2487
2488 continue;
2489 }
2490
2491 assert(VA.isMemLoc());
2492 SDValue Arg = OutVals[OutsIndex];
2493 ISD::ArgFlagsTy Flags = Outs[OutsIndex].Flags;
2494 // Skip inalloca/preallocated arguments. They don't require any work.
2495 if (Flags.isInAlloca() || Flags.isPreallocated())
2496 continue;
2497 // Create frame index.
2498 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2499 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2500 FI = MF.getFrameInfo().CreateFixedObject(Size: OpSize, SPOffset: Offset, IsImmutable: true);
2501 FIN = DAG.getFrameIndex(FI, VT: getPointerTy(DL: DAG.getDataLayout()));
2502
2503 if (Flags.isByVal()) {
2504 if (SDValue ByValSrc = ByValTemporaries[OutsIndex]) {
2505 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
2506 SDValue DstAddr = DAG.getFrameIndex(FI, VT: PtrVT);
2507
2508 MemOpChains2.push_back(Elt: CreateCopyOfByValArgument(
2509 Src: ByValSrc, Dst: DstAddr, Chain, Flags, DAG, dl));
2510 }
2511 } else {
2512 // Store relative to framepointer.
2513 MemOpChains2.push_back(Elt: DAG.getStore(
2514 Chain, dl, Val: Arg, Ptr: FIN,
2515 PtrInfo: MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI)));
2516 }
2517 }
2518
2519 if (!MemOpChains2.empty())
2520 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: MemOpChains2);
2521
2522 // Store the return address to the appropriate stack slot.
2523 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2524 PtrVT: getPointerTy(DL: DAG.getDataLayout()),
2525 SlotSize: RegInfo->getSlotSize(), FPDiff, dl);
2526 }
2527
2528 // Build a sequence of copy-to-reg nodes chained together with token chain
2529 // and glue operands which copy the outgoing args into registers.
2530 SDValue InGlue;
2531 for (const auto &[Reg, N] : RegsToPass) {
2532 Chain = DAG.getCopyToReg(Chain, dl, Reg, N, Glue: InGlue);
2533 InGlue = Chain.getValue(R: 1);
2534 }
2535
2536 bool IsImpCall = false;
2537 bool IsCFGuardCall = false;
2538 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
2539 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2540 // In the 64-bit large code model, we have to make all calls
2541 // through a register, since the call instruction's 32-bit
2542 // pc-relative offset may not be large enough to hold the whole
2543 // address.
2544 } else if (Callee->getOpcode() == ISD::GlobalAddress ||
2545 Callee->getOpcode() == ISD::ExternalSymbol) {
2546 // Lower direct calls to global addresses and external symbols. Setting
2547 // ForCall to true here has the effect of removing WrapperRIP when possible
2548 // to allow direct calls to be selected without first materializing the
2549 // address into a register.
2550 Callee = LowerGlobalOrExternal(Op: Callee, DAG, /*ForCall=*/true, IsImpCall: &IsImpCall);
2551 } else if (Subtarget.isTarget64BitILP32() &&
2552 Callee.getValueType() == MVT::i32) {
2553 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
2554 Callee = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: MVT::i64, Operand: Callee);
2555 } else if (Is64Bit && CB && isCFGuardCall(CB)) {
2556 // We'll use a specific psuedo instruction for tail calls to control flow
2557 // guard functions to guarantee the instruction used for the call. To do
2558 // this we need to unwrap the load now and use the CFG Func GV as the
2559 // callee.
2560 IsCFGuardCall = true;
2561 auto *LoadNode = cast<LoadSDNode>(Val&: Callee);
2562 GlobalAddressSDNode *GA =
2563 cast<GlobalAddressSDNode>(Val: unwrapAddress(N: LoadNode->getBasePtr()));
2564 assert(isCFGuardFunction(GA->getGlobal()) &&
2565 "CFG Call should be to a guard function");
2566 assert(LoadNode->getOffset()->isUndef() &&
2567 "CFG Function load should not have an offset");
2568 Callee = DAG.getTargetGlobalAddress(
2569 GV: GA->getGlobal(), DL: dl, VT: GA->getValueType(ResNo: 0), offset: 0, TargetFlags: X86II::MO_NO_FLAG);
2570 }
2571
2572 SmallVector<SDValue, 8> Ops;
2573
2574 if (!IsSibcall && isTailCall && !IsMustTail) {
2575 Chain = DAG.getCALLSEQ_END(Chain, Size1: NumBytesToPop, Size2: 0, Glue: InGlue, DL: dl);
2576 InGlue = Chain.getValue(R: 1);
2577 }
2578
2579 Ops.push_back(Elt: Chain);
2580 Ops.push_back(Elt: Callee);
2581
2582 if (isTailCall)
2583 Ops.push_back(Elt: DAG.getSignedTargetConstant(Val: FPDiff, DL: dl, VT: MVT::i32));
2584
2585 // Add argument registers to the end of the list so that they are known live
2586 // into the call.
2587 for (const auto &[Reg, N] : RegsToPass)
2588 Ops.push_back(Elt: DAG.getRegister(Reg, VT: N.getValueType()));
2589
2590 // Add a register mask operand representing the call-preserved registers.
2591 const uint32_t *Mask = [&]() {
2592 auto AdaptedCC = CallConv;
2593 // If HasNCSR is asserted (attribute NoCallerSavedRegisters exists),
2594 // use X86_INTR calling convention because it has the same CSR mask
2595 // (same preserved registers).
2596 if (HasNCSR)
2597 AdaptedCC = (CallingConv::ID)CallingConv::X86_INTR;
2598 // If NoCalleeSavedRegisters is requested, than use GHC since it happens
2599 // to use the CSR_NoRegs_RegMask.
2600 if (CB && CB->hasFnAttr(Kind: "no_callee_saved_registers"))
2601 AdaptedCC = (CallingConv::ID)CallingConv::GHC;
2602 return RegInfo->getCallPreservedMask(MF, AdaptedCC);
2603 }();
2604 assert(Mask && "Missing call preserved mask for calling convention");
2605
2606 if (MachineOperand::clobbersPhysReg(RegMask: Mask, PhysReg: RegInfo->getFramePtr())) {
2607 X86Info->setFPClobberedByCall(true);
2608 if (CLI.CB && isa<InvokeInst>(Val: CLI.CB))
2609 X86Info->setFPClobberedByInvoke(true);
2610 }
2611 if (MachineOperand::clobbersPhysReg(RegMask: Mask, PhysReg: RegInfo->getBaseRegister())) {
2612 X86Info->setBPClobberedByCall(true);
2613 if (CLI.CB && isa<InvokeInst>(Val: CLI.CB))
2614 X86Info->setBPClobberedByInvoke(true);
2615 }
2616
2617 // If this is an invoke in a 32-bit function using a funclet-based
2618 // personality, assume the function clobbers all registers. If an exception
2619 // is thrown, the runtime will not restore CSRs.
2620 // FIXME: Model this more precisely so that we can register allocate across
2621 // the normal edge and spill and fill across the exceptional edge.
2622 if (!Is64Bit && CLI.CB && isa<InvokeInst>(Val: CLI.CB)) {
2623 const Function &CallerFn = MF.getFunction();
2624 EHPersonality Pers =
2625 CallerFn.hasPersonalityFn()
2626 ? classifyEHPersonality(Pers: CallerFn.getPersonalityFn())
2627 : EHPersonality::Unknown;
2628 if (isFuncletEHPersonality(Pers))
2629 Mask = RegInfo->getNoPreservedMask();
2630 }
2631
2632 // Define a new register mask from the existing mask.
2633 uint32_t *RegMask = nullptr;
2634
2635 // In some calling conventions we need to remove the used physical registers
2636 // from the reg mask. Create a new RegMask for such calling conventions.
2637 // RegMask for calling conventions that disable only return registers (e.g.
2638 // preserve_most) will be modified later in LowerCallResult.
2639 bool ShouldDisableArgRegs = shouldDisableArgRegFromCSR(CC: CallConv) || HasNCSR;
2640 if (ShouldDisableArgRegs || shouldDisableRetRegFromCSR(CC: CallConv)) {
2641 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2642
2643 // Allocate a new Reg Mask and copy Mask.
2644 RegMask = MF.allocateRegMask();
2645 unsigned RegMaskSize = MachineOperand::getRegMaskSize(NumRegs: TRI->getNumRegs());
2646 memcpy(dest: RegMask, src: Mask, n: sizeof(RegMask[0]) * RegMaskSize);
2647
2648 // Make sure all sub registers of the argument registers are reset
2649 // in the RegMask.
2650 if (ShouldDisableArgRegs) {
2651 for (auto const &RegPair : RegsToPass)
2652 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg: RegPair.first))
2653 RegMask[SubReg / 32] &= ~(1u << (SubReg % 32));
2654 }
2655
2656 // Create the RegMask Operand according to our updated mask.
2657 Ops.push_back(Elt: DAG.getRegisterMask(RegMask));
2658 } else {
2659 // Create the RegMask Operand according to the static mask.
2660 Ops.push_back(Elt: DAG.getRegisterMask(RegMask: Mask));
2661 }
2662
2663 if (InGlue.getNode())
2664 Ops.push_back(Elt: InGlue);
2665
2666 if (isTailCall) {
2667 // We used to do:
2668 //// If this is the first return lowered for this function, add the regs
2669 //// to the liveout set for the function.
2670 // This isn't right, although it's probably harmless on x86; liveouts
2671 // should be computed from returns not tail calls. Consider a void
2672 // function making a tail call to a function returning int.
2673 MF.getFrameInfo().setHasTailCall();
2674 auto Opcode =
2675 IsCFGuardCall ? X86ISD::TC_RETURN_GLOBALADDR : X86ISD::TC_RETURN;
2676 SDValue Ret = DAG.getNode(Opcode, DL: dl, VT: MVT::Other, Ops);
2677
2678 if (IsCFICall)
2679 Ret.getNode()->setCFIType(CLI.CFIType->getZExtValue());
2680
2681 DAG.addNoMergeSiteInfo(Node: Ret.getNode(), NoMerge: CLI.NoMerge);
2682 DAG.addCallSiteInfo(Node: Ret.getNode(), CallInfo: std::move(CSInfo));
2683 return Ret;
2684 }
2685
2686 // Returns a chain & a glue for retval copy to use.
2687 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
2688 if (IsImpCall) {
2689 Chain = DAG.getNode(Opcode: X86ISD::IMP_CALL, DL: dl, VTList: NodeTys, Ops);
2690 } else if (IsNoTrackIndirectCall) {
2691 Chain = DAG.getNode(Opcode: X86ISD::NT_CALL, DL: dl, VTList: NodeTys, Ops);
2692 } else if (IsCFGuardCall) {
2693 Chain = DAG.getNode(Opcode: X86ISD::CALL_GLOBALADDR, DL: dl, VTList: NodeTys, Ops);
2694 } else if (CLI.CB && objcarc::hasAttachedCallOpBundle(CB: CLI.CB)) {
2695 // Calls with a "clang.arc.attachedcall" bundle are special. They should be
2696 // expanded to the call, directly followed by a special marker sequence and
2697 // a call to a ObjC library function. Use the CALL_RVMARKER to do that.
2698 assert(!isTailCall &&
2699 "tail calls cannot be marked with clang.arc.attachedcall");
2700 assert(Is64Bit && "clang.arc.attachedcall is only supported in 64bit mode");
2701
2702 // Add a target global address for the retainRV/claimRV runtime function
2703 // just before the call target.
2704 Function *ARCFn = *objcarc::getAttachedARCFunction(CB: CLI.CB);
2705 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
2706 auto GA = DAG.getTargetGlobalAddress(GV: ARCFn, DL: dl, VT: PtrVT);
2707 Ops.insert(I: Ops.begin() + 1, Elt: GA);
2708 Chain = DAG.getNode(Opcode: X86ISD::CALL_RVMARKER, DL: dl, VTList: NodeTys, Ops);
2709 } else {
2710 Chain = DAG.getNode(Opcode: X86ISD::CALL, DL: dl, VTList: NodeTys, Ops);
2711 }
2712
2713 if (IsCFICall)
2714 Chain.getNode()->setCFIType(CLI.CFIType->getZExtValue());
2715
2716 InGlue = Chain.getValue(R: 1);
2717 DAG.addNoMergeSiteInfo(Node: Chain.getNode(), NoMerge: CLI.NoMerge);
2718 DAG.addCallSiteInfo(Node: Chain.getNode(), CallInfo: std::move(CSInfo));
2719
2720 // Save heapallocsite metadata.
2721 if (CLI.CB)
2722 if (MDNode *HeapAlloc = CLI.CB->getMetadata(Kind: "heapallocsite"))
2723 DAG.addHeapAllocSite(Node: Chain.getNode(), MD: HeapAlloc);
2724
2725 // Create the CALLSEQ_END node.
2726 unsigned NumBytesForCalleeToPop = 0; // Callee pops nothing.
2727 if (X86::isCalleePop(CallingConv: CallConv, is64Bit: Is64Bit, IsVarArg: isVarArg,
2728 GuaranteeTCO: DAG.getTarget().Options.GuaranteedTailCallOpt)) {
2729 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
2730 } else if (hasCalleePopSRet(Args: Outs, ArgLocs, Subtarget)) {
2731 // If this call passes a struct-return pointer, the callee
2732 // pops that struct pointer.
2733 NumBytesForCalleeToPop = 4;
2734 }
2735
2736 // Returns a glue for retval copy to use.
2737 if (!IsSibcall) {
2738 Chain = DAG.getCALLSEQ_END(Chain, Size1: NumBytesToPop, Size2: NumBytesForCalleeToPop,
2739 Glue: InGlue, DL: dl);
2740 InGlue = Chain.getValue(R: 1);
2741 }
2742
2743 if (CallingConv::PreserveNone == CallConv)
2744 for (const ISD::OutputArg &Out : Outs) {
2745 if (Out.Flags.isSwiftSelf() || Out.Flags.isSwiftAsync() ||
2746 Out.Flags.isSwiftError()) {
2747 errorUnsupported(DAG, dl,
2748 Msg: "Swift attributes can't be used with preserve_none");
2749 break;
2750 }
2751 }
2752
2753 // Handle result values, copying them out of physregs into vregs that we
2754 // return.
2755 return LowerCallResult(Chain, InGlue, CallConv, isVarArg, Ins, dl, DAG,
2756 InVals, RegMask);
2757}
2758
2759//===----------------------------------------------------------------------===//
2760// Fast Calling Convention (tail call) implementation
2761//===----------------------------------------------------------------------===//
2762
2763// Like std call, callee cleans arguments, convention except that ECX is
2764// reserved for storing the tail called function address. Only 2 registers are
2765// free for argument passing (inreg). Tail call optimization is performed
2766// provided:
2767// * tailcallopt is enabled
2768// * caller/callee are fastcc
2769// On X86_64 architecture with GOT-style position independent code only local
2770// (within module) calls are supported at the moment.
2771// To keep the stack aligned according to platform abi the function
2772// GetAlignedArgumentStackSize ensures that argument delta is always multiples
2773// of stack alignment. (Dynamic linkers need this - Darwin's dyld for example)
2774// If a tail called function callee has more arguments than the caller the
2775// caller needs to make sure that there is room to move the RETADDR to. This is
2776// achieved by reserving an area the size of the argument delta right after the
2777// original RETADDR, but before the saved framepointer or the spilled registers
2778// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2779// stack layout:
2780// arg1
2781// arg2
2782// RETADDR
2783// [ new RETADDR
2784// move area ]
2785// (possible EBP)
2786// ESI
2787// EDI
2788// local1 ..
2789
2790/// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
2791/// requirement.
2792unsigned
2793X86TargetLowering::GetAlignedArgumentStackSize(const unsigned StackSize,
2794 SelectionDAG &DAG) const {
2795 const Align StackAlignment = Subtarget.getFrameLowering()->getStackAlign();
2796 const uint64_t SlotSize = Subtarget.getRegisterInfo()->getSlotSize();
2797 assert(StackSize % SlotSize == 0 &&
2798 "StackSize must be a multiple of SlotSize");
2799 return alignTo(Size: StackSize + SlotSize, A: StackAlignment) - SlotSize;
2800}
2801
2802/// Return true if the given stack call argument is already available in the
2803/// same position (relatively) of the caller's incoming argument stack.
2804static
2805bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2806 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
2807 const X86InstrInfo *TII, const CCValAssign &VA) {
2808 unsigned Bytes = Arg.getValueSizeInBits() / 8;
2809
2810 for (;;) {
2811 // Look through nodes that don't alter the bits of the incoming value.
2812 unsigned Op = Arg.getOpcode();
2813 if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST ||
2814 Op == ISD::AssertZext) {
2815 Arg = Arg.getOperand(i: 0);
2816 continue;
2817 }
2818 if (Op == ISD::TRUNCATE) {
2819 const SDValue &TruncInput = Arg.getOperand(i: 0);
2820 if (TruncInput.getOpcode() == ISD::AssertZext &&
2821 cast<VTSDNode>(Val: TruncInput.getOperand(i: 1))->getVT() ==
2822 Arg.getValueType()) {
2823 Arg = TruncInput.getOperand(i: 0);
2824 continue;
2825 }
2826 }
2827 break;
2828 }
2829
2830 int FI = INT_MAX;
2831 if (Arg.getOpcode() == ISD::CopyFromReg) {
2832 Register VR = cast<RegisterSDNode>(Val: Arg.getOperand(i: 1))->getReg();
2833 if (!VR.isVirtual())
2834 return false;
2835 MachineInstr *Def = MRI->getVRegDef(Reg: VR);
2836 if (!Def)
2837 return false;
2838 if (!Flags.isByVal()) {
2839 if (!TII->isLoadFromStackSlot(MI: *Def, FrameIndex&: FI))
2840 return false;
2841 } else {
2842 unsigned Opcode = Def->getOpcode();
2843 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
2844 Opcode == X86::LEA64_32r) &&
2845 Def->getOperand(i: 1).isFI()) {
2846 FI = Def->getOperand(i: 1).getIndex();
2847 Bytes = Flags.getByValSize();
2848 } else
2849 return false;
2850 }
2851 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Val&: Arg)) {
2852 if (Flags.isByVal())
2853 // ByVal argument is passed in as a pointer but it's now being
2854 // dereferenced. e.g.
2855 // define @foo(%struct.X* %A) {
2856 // tail call @bar(%struct.X* byval %A)
2857 // }
2858 return false;
2859 SDValue Ptr = Ld->getBasePtr();
2860 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Val&: Ptr);
2861 if (!FINode)
2862 return false;
2863 FI = FINode->getIndex();
2864 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2865 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Val&: Arg);
2866 FI = FINode->getIndex();
2867 Bytes = Flags.getByValSize();
2868 } else
2869 return false;
2870
2871 assert(FI != INT_MAX);
2872 if (!MFI.isFixedObjectIndex(ObjectIdx: FI))
2873 return false;
2874
2875 if (Offset != MFI.getObjectOffset(ObjectIdx: FI))
2876 return false;
2877
2878 // If this is not byval, check that the argument stack object is immutable.
2879 // inalloca and argument copy elision can create mutable argument stack
2880 // objects. Byval objects can be mutated, but a byval call intends to pass the
2881 // mutated memory.
2882 if (!Flags.isByVal() && !MFI.isImmutableObjectIndex(ObjectIdx: FI))
2883 return false;
2884
2885 if (VA.getLocVT().getFixedSizeInBits() >
2886 Arg.getValueSizeInBits().getFixedValue()) {
2887 // If the argument location is wider than the argument type, check that any
2888 // extension flags match.
2889 if (Flags.isZExt() != MFI.isObjectZExt(ObjectIdx: FI) ||
2890 Flags.isSExt() != MFI.isObjectSExt(ObjectIdx: FI)) {
2891 return false;
2892 }
2893 }
2894
2895 return Bytes == MFI.getObjectSize(ObjectIdx: FI);
2896}
2897
2898static bool
2899mayBeSRetTailCallCompatible(const TargetLowering::CallLoweringInfo &CLI,
2900 Register CallerSRetReg) {
2901 const auto &Outs = CLI.Outs;
2902 const auto &OutVals = CLI.OutVals;
2903
2904 // We know the caller has a sret pointer argument (CallerSRetReg). Locate the
2905 // operand index within the callee that may have a sret pointer too.
2906 unsigned Pos = 0;
2907 for (unsigned E = Outs.size(); Pos != E; ++Pos)
2908 if (Outs[Pos].Flags.isSRet())
2909 break;
2910 // Bail out if the callee has not any sret argument.
2911 if (Pos == Outs.size())
2912 return false;
2913
2914 // At this point, either the caller is forwarding its sret argument to the
2915 // callee, or the callee is being passed a different sret pointer. We now look
2916 // for a CopyToReg, where the callee sret argument is written into a new vreg
2917 // (which should later be %rax/%eax, if this is returned).
2918 SDValue SRetArgVal = OutVals[Pos];
2919 for (SDNode *User : SRetArgVal->users()) {
2920 if (User->getOpcode() != ISD::CopyToReg)
2921 continue;
2922 Register Reg = cast<RegisterSDNode>(Val: User->getOperand(Num: 1))->getReg();
2923 if (Reg == CallerSRetReg && User->getOperand(Num: 2) == SRetArgVal)
2924 return true;
2925 }
2926
2927 return false;
2928}
2929
2930/// Check whether the call is eligible for sibling call optimization. Sibling
2931/// calls are loosely defined to be simple, profitable tail calls that only
2932/// require adjusting register parameters. We do not speculatively to optimize
2933/// complex calls that require lots of argument memory operations that may
2934/// alias.
2935///
2936/// Note that LLVM supports multiple ways, such as musttail, to force tail call
2937/// emission. Returning false from this function will not prevent tail call
2938/// emission in all cases.
2939bool X86TargetLowering::isEligibleForSiblingCallOpt(
2940 TargetLowering::CallLoweringInfo &CLI, CCState &CCInfo,
2941 SmallVectorImpl<CCValAssign> &ArgLocs) const {
2942 SelectionDAG &DAG = CLI.DAG;
2943 const SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2944 const SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2945 const SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2946 SDValue Callee = CLI.Callee;
2947 CallingConv::ID CalleeCC = CLI.CallConv;
2948 bool isVarArg = CLI.IsVarArg;
2949
2950 if (!mayTailCallThisCC(CC: CalleeCC))
2951 return false;
2952
2953 // If -tailcallopt is specified, make fastcc functions tail-callable.
2954 MachineFunction &MF = DAG.getMachineFunction();
2955 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2956 const Function &CallerF = MF.getFunction();
2957
2958 // If the function return type is x86_fp80 and the callee return type is not,
2959 // then the FP_EXTEND of the call result is not a nop. It's not safe to
2960 // perform a tailcall optimization here.
2961 if (CallerF.getReturnType()->isX86_FP80Ty() && !CLI.RetTy->isX86_FP80Ty())
2962 return false;
2963
2964 // Win64 functions have extra shadow space for argument homing. Don't do the
2965 // sibcall if the caller and callee have mismatched expectations for this
2966 // space.
2967 CallingConv::ID CallerCC = CallerF.getCallingConv();
2968 bool IsCalleeWin64 = Subtarget.isCallingConvWin64(CC: CalleeCC);
2969 bool IsCallerWin64 = Subtarget.isCallingConvWin64(CC: CallerCC);
2970 if (IsCalleeWin64 != IsCallerWin64)
2971 return false;
2972
2973 // If we are using a GOT, don't generate sibling calls to non-local,
2974 // default-visibility symbols. Tail calling such a symbol requires using a GOT
2975 // relocation, which forces early binding of the symbol. This breaks code that
2976 // require lazy function symbol resolution. Using musttail or
2977 // GuaranteedTailCallOpt will override this.
2978 if (Subtarget.isPICStyleGOT()) {
2979 if (isa<ExternalSymbolSDNode>(Val: Callee))
2980 return false;
2981 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Val&: Callee)) {
2982 if (!G->getGlobal()->hasLocalLinkage() &&
2983 G->getGlobal()->hasDefaultVisibility())
2984 return false;
2985 }
2986 }
2987
2988 // Look for obvious safe cases to perform tail call optimization that do not
2989 // require ABI changes. This is what gcc calls sibcall.
2990
2991 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2992 // emit a special epilogue.
2993 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
2994 if (RegInfo->hasStackRealignment(MF))
2995 return false;
2996
2997 // Avoid sibcall optimization if we are an sret return function and the callee
2998 // is incompatible, unless such premises are proven wrong. See comment in
2999 // LowerReturn about why hasStructRetAttr is insufficient.
3000 if (Register SRetReg = FuncInfo->getSRetReturnReg()) {
3001 // For a compatible tail call the callee must return our sret pointer. So it
3002 // needs to be (a) an sret function itself and (b) we pass our sret as its
3003 // sret. Condition #b is harder to determine.
3004 if (!mayBeSRetTailCallCompatible(CLI, CallerSRetReg: SRetReg))
3005 return false;
3006 } else if (hasCalleePopSRet(Args: Outs, ArgLocs, Subtarget))
3007 // The callee pops an sret, so we cannot tail-call, as our caller doesn't
3008 // expect that.
3009 return false;
3010
3011 // Do not sibcall optimize vararg calls unless all arguments are passed via
3012 // registers.
3013 LLVMContext &C = *DAG.getContext();
3014 if (isVarArg && !Outs.empty()) {
3015 // Optimizing for varargs on Win64 is unlikely to be safe without
3016 // additional testing.
3017 if (IsCalleeWin64 || IsCallerWin64)
3018 return false;
3019
3020 for (const auto &VA : ArgLocs)
3021 if (!VA.isRegLoc())
3022 return false;
3023 }
3024
3025 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3026 // stack. Therefore, if it's not used by the call it is not safe to optimize
3027 // this into a sibcall.
3028 bool Unused = false;
3029 for (const auto &In : Ins) {
3030 if (!In.Used) {
3031 Unused = true;
3032 break;
3033 }
3034 }
3035 if (Unused) {
3036 SmallVector<CCValAssign, 16> RVLocs;
3037 CCState RVCCInfo(CalleeCC, false, MF, RVLocs, C);
3038 RVCCInfo.AnalyzeCallResult(Ins, Fn: RetCC_X86);
3039 for (const auto &VA : RVLocs) {
3040 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3041 return false;
3042 }
3043 }
3044
3045 // Check that the call results are passed in the same way.
3046 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins,
3047 CalleeFn: RetCC_X86, CallerFn: RetCC_X86))
3048 return false;
3049 // The callee has to preserve all registers the caller needs to preserve.
3050 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
3051 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
3052 if (CallerCC != CalleeCC) {
3053 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
3054 if (!TRI->regmaskSubsetEqual(mask0: CallerPreserved, mask1: CalleePreserved))
3055 return false;
3056 }
3057
3058 // The stack frame of the caller cannot be replaced by the tail-callee one's
3059 // if the function is required to preserve all the registers. Conservatively
3060 // prevent tail optimization even if hypothetically all the registers are used
3061 // for passing formal parameters or returning values.
3062 if (CallerF.hasFnAttribute(Kind: "no_caller_saved_registers"))
3063 return false;
3064
3065 unsigned StackArgsSize = CCInfo.getStackSize();
3066
3067 // If the callee takes no arguments then go on to check the results of the
3068 // call.
3069 if (!Outs.empty()) {
3070 if (StackArgsSize > 0) {
3071 // Check if the arguments are already laid out in the right way as
3072 // the caller's fixed stack objects.
3073 MachineFrameInfo &MFI = MF.getFrameInfo();
3074 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3075 const X86InstrInfo *TII = Subtarget.getInstrInfo();
3076 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
3077 const CCValAssign &VA = ArgLocs[I];
3078 SDValue Arg = OutVals[I];
3079 ISD::ArgFlagsTy Flags = Outs[I].Flags;
3080 if (VA.getLocInfo() == CCValAssign::Indirect)
3081 return false;
3082 if (!VA.isRegLoc()) {
3083 if (!MatchingStackOffset(Arg, Offset: VA.getLocMemOffset(), Flags, MFI, MRI,
3084 TII, VA))
3085 return false;
3086 }
3087 }
3088 }
3089
3090 bool PositionIndependent = isPositionIndependent();
3091 // If the tailcall address may be in a register, then make sure it's
3092 // possible to register allocate for it. In 32-bit, the call address can
3093 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3094 // callee-saved registers are restored. These happen to be the same
3095 // registers used to pass 'inreg' arguments so watch out for those.
3096 if (!Subtarget.is64Bit() && ((!isa<GlobalAddressSDNode>(Val: Callee) &&
3097 !isa<ExternalSymbolSDNode>(Val: Callee)) ||
3098 PositionIndependent)) {
3099 unsigned NumInRegs = 0;
3100 // In PIC we need an extra register to formulate the address computation
3101 // for the callee.
3102 unsigned MaxInRegs = PositionIndependent ? 2 : 3;
3103
3104 for (const auto &VA : ArgLocs) {
3105 if (!VA.isRegLoc())
3106 continue;
3107 Register Reg = VA.getLocReg();
3108 switch (Reg) {
3109 default: break;
3110 case X86::EAX: case X86::EDX: case X86::ECX:
3111 if (++NumInRegs == MaxInRegs)
3112 return false;
3113 break;
3114 }
3115 }
3116 }
3117
3118 const MachineRegisterInfo &MRI = MF.getRegInfo();
3119 if (!parametersInCSRMatch(MRI, CallerPreservedMask: CallerPreserved, ArgLocs, OutVals))
3120 return false;
3121 }
3122
3123 bool CalleeWillPop =
3124 X86::isCalleePop(CallingConv: CalleeCC, is64Bit: Subtarget.is64Bit(), IsVarArg: isVarArg,
3125 GuaranteeTCO: MF.getTarget().Options.GuaranteedTailCallOpt);
3126
3127 if (unsigned BytesToPop = FuncInfo->getBytesToPopOnReturn()) {
3128 // If we have bytes to pop, the callee must pop them.
3129 bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
3130 if (!CalleePopMatches)
3131 return false;
3132 } else if (CalleeWillPop && StackArgsSize > 0) {
3133 // If we don't have bytes to pop, make sure the callee doesn't pop any.
3134 return false;
3135 }
3136
3137 return true;
3138}
3139
3140/// Determines whether the callee is required to pop its own arguments.
3141/// Callee pop is necessary to support tail calls.
3142bool X86::isCalleePop(CallingConv::ID CallingConv,
3143 bool is64Bit, bool IsVarArg, bool GuaranteeTCO) {
3144 // If GuaranteeTCO is true, we force some calls to be callee pop so that we
3145 // can guarantee TCO.
3146 if (!IsVarArg && shouldGuaranteeTCO(CC: CallingConv, GuaranteedTailCallOpt: GuaranteeTCO))
3147 return true;
3148
3149 switch (CallingConv) {
3150 default:
3151 return false;
3152 case CallingConv::X86_StdCall:
3153 case CallingConv::X86_FastCall:
3154 case CallingConv::X86_ThisCall:
3155 case CallingConv::X86_VectorCall:
3156 return !is64Bit;
3157 }
3158}
3159