1//===- llvm/lib/Target/X86/X86ISelCallLowering.cpp - Call lowering --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// This file implements the lowering of LLVM calls to DAG nodes.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MCTargetDesc/X86MCAsmInfo.h"
15#include "X86.h"
16#include "X86CallingConv.h"
17#include "X86FrameLowering.h"
18#include "X86ISelLowering.h"
19#include "X86InstrBuilder.h"
20#include "X86MachineFunctionInfo.h"
21#include "X86TargetMachine.h"
22#include "llvm/ADT/Statistic.h"
23#include "llvm/Analysis/ObjCARCUtil.h"
24#include "llvm/CodeGen/MachineJumpTableInfo.h"
25#include "llvm/CodeGen/MachineModuleInfo.h"
26#include "llvm/CodeGen/WinEHFuncInfo.h"
27#include "llvm/IR/DiagnosticInfo.h"
28#include "llvm/IR/IRBuilder.h"
29#include "llvm/IR/Module.h"
30#include "llvm/Transforms/CFGuard.h"
31
32#define DEBUG_TYPE "x86-isel"
33
34using namespace llvm;
35
36STATISTIC(NumTailCalls, "Number of tail calls");
37
38/// Call this when the user attempts to do something unsupported, like
39/// returning a double without SSE2 enabled on x86_64. This is not fatal, unlike
40/// report_fatal_error, so calling code should attempt to recover without
41/// crashing.
42static void errorUnsupported(SelectionDAG &DAG, const SDLoc &dl,
43 const char *Msg) {
44 MachineFunction &MF = DAG.getMachineFunction();
45 DAG.getContext()->diagnose(
46 DI: DiagnosticInfoUnsupported(MF.getFunction(), Msg, dl.getDebugLoc()));
47}
48
49/// Returns true if a CC can dynamically exclude a register from the list of
50/// callee-saved-registers (TargetRegistryInfo::getCalleeSavedRegs()) based on
51/// the return registers.
52static bool shouldDisableRetRegFromCSR(CallingConv::ID CC) {
53 switch (CC) {
54 default:
55 return false;
56 case CallingConv::X86_RegCall:
57 case CallingConv::PreserveMost:
58 case CallingConv::PreserveAll:
59 return true;
60 }
61}
62
63/// Returns true if a CC can dynamically exclude a register from the list of
64/// callee-saved-registers (TargetRegistryInfo::getCalleeSavedRegs()) based on
65/// the parameters.
66static bool shouldDisableArgRegFromCSR(CallingConv::ID CC) {
67 return CC == CallingConv::X86_RegCall;
68}
69
70static std::pair<MVT, unsigned>
71handleMaskRegisterForCallingConv(unsigned NumElts, CallingConv::ID CC,
72 const X86Subtarget &Subtarget) {
73 // v2i1/v4i1/v8i1/v16i1 all pass in xmm registers unless the calling
74 // convention is one that uses k registers.
75 if (NumElts == 2)
76 return {MVT::v2i64, 1};
77 if (NumElts == 4)
78 return {MVT::v4i32, 1};
79 if (NumElts == 8 && CC != CallingConv::X86_RegCall &&
80 CC != CallingConv::Intel_OCL_BI)
81 return {MVT::v8i16, 1};
82 if (NumElts == 16 && CC != CallingConv::X86_RegCall &&
83 CC != CallingConv::Intel_OCL_BI)
84 return {MVT::v16i8, 1};
85 // v32i1 passes in ymm unless we have BWI and the calling convention is
86 // regcall.
87 if (NumElts == 32 && (!Subtarget.hasBWI() || CC != CallingConv::X86_RegCall))
88 return {MVT::v32i8, 1};
89 // Split v64i1 vectors if we don't have v64i8 available.
90 if (NumElts == 64 && Subtarget.hasBWI() && CC != CallingConv::X86_RegCall) {
91 if (Subtarget.useAVX512Regs())
92 return {MVT::v64i8, 1};
93 return {MVT::v32i8, 2};
94 }
95
96 // Break wide or odd vXi1 vectors into scalars to match avx2 behavior.
97 if (!isPowerOf2_32(Value: NumElts) || (NumElts == 64 && !Subtarget.hasBWI()) ||
98 NumElts > 64)
99 return {MVT::i8, NumElts};
100
101 return {MVT::INVALID_SIMPLE_VALUE_TYPE, 0};
102}
103
104MVT X86TargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
105 CallingConv::ID CC,
106 EVT VT) const {
107 if (VT.isVector()) {
108 if (VT.getVectorElementType() == MVT::i1 && Subtarget.hasAVX512()) {
109 unsigned NumElts = VT.getVectorNumElements();
110
111 MVT RegisterVT;
112 unsigned NumRegisters;
113 std::tie(args&: RegisterVT, args&: NumRegisters) =
114 handleMaskRegisterForCallingConv(NumElts, CC, Subtarget);
115 if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
116 return RegisterVT;
117 }
118
119 if (VT.getVectorElementType() == MVT::f16 && VT.getVectorNumElements() < 8)
120 return MVT::v8f16;
121 }
122
123 // We will use more GPRs for f64 and f80 on 32 bits when x87 is disabled.
124 if ((VT == MVT::f64 || VT == MVT::f80) && !Subtarget.is64Bit() &&
125 !Subtarget.hasX87())
126 return MVT::i32;
127
128 if (isTypeLegal(VT: MVT::f16)) {
129 if (VT.isVectorOf(EltVT: MVT::bf16))
130 return getRegisterTypeForCallingConv(
131 Context, CC, VT: VT.changeVectorElementType(Context, EltVT: MVT::f16));
132
133 if (VT == MVT::bf16)
134 return MVT::f16;
135 }
136
137 return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
138}
139
140unsigned X86TargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
141 CallingConv::ID CC,
142 EVT VT) const {
143 if (VT.isVector()) {
144 if (VT.getVectorElementType() == MVT::i1 && Subtarget.hasAVX512()) {
145 unsigned NumElts = VT.getVectorNumElements();
146
147 MVT RegisterVT;
148 unsigned NumRegisters;
149 std::tie(args&: RegisterVT, args&: NumRegisters) =
150 handleMaskRegisterForCallingConv(NumElts, CC, Subtarget);
151 if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
152 return NumRegisters;
153 }
154
155 if (VT.getVectorElementType() == MVT::f16 && VT.getVectorNumElements() < 8)
156 return 1;
157 }
158
159 // We have to split f64 to 2 registers and f80 to 3 registers on 32 bits if
160 // x87 is disabled.
161 if (!Subtarget.is64Bit() && !Subtarget.hasX87()) {
162 if (VT == MVT::f64)
163 return 2;
164 if (VT == MVT::f80)
165 return 3;
166 }
167
168 if (VT.isVectorOf(EltVT: MVT::bf16) && isTypeLegal(VT: MVT::f16))
169 return getNumRegistersForCallingConv(
170 Context, CC, VT: VT.changeVectorElementType(Context, EltVT: MVT::f16));
171
172 return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
173}
174
175unsigned X86TargetLowering::getVectorTypeBreakdownForCallingConv(
176 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
177 unsigned &NumIntermediates, MVT &RegisterVT) const {
178 // Break wide or odd vXi1 vectors into scalars to match avx2 behavior.
179 if (VT.isVectorOf(EltVT: MVT::i1) && Subtarget.hasAVX512() &&
180 (!isPowerOf2_32(Value: VT.getVectorNumElements()) ||
181 (VT.getVectorNumElements() == 64 && !Subtarget.hasBWI()) ||
182 VT.getVectorNumElements() > 64)) {
183 RegisterVT = MVT::i8;
184 IntermediateVT = MVT::i1;
185 NumIntermediates = VT.getVectorNumElements();
186 return NumIntermediates;
187 }
188
189 // Split v64i1 vectors if we don't have v64i8 available.
190 if (VT == MVT::v64i1 && Subtarget.hasBWI() && !Subtarget.useAVX512Regs() &&
191 CC != CallingConv::X86_RegCall) {
192 RegisterVT = MVT::v32i8;
193 IntermediateVT = MVT::v32i1;
194 NumIntermediates = 2;
195 return 2;
196 }
197
198 // Split vNbf16 vectors according to vNf16.
199 if (VT.isVectorOf(EltVT: MVT::bf16) && isTypeLegal(VT: MVT::f16))
200 VT = VT.changeVectorElementType(Context, EltVT: MVT::f16);
201
202 return TargetLowering::getVectorTypeBreakdownForCallingConv(Context, CC, VT, IntermediateVT,
203 NumIntermediates, RegisterVT);
204}
205
206EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL,
207 LLVMContext& Context,
208 EVT VT) const {
209 if (!VT.isVector())
210 return MVT::i8;
211
212 if (Subtarget.hasAVX512()) {
213 // Figure out what this type will be legalized to.
214 EVT LegalVT = VT;
215 while (getTypeAction(Context, VT: LegalVT) != TypeLegal)
216 LegalVT = getTypeToTransformTo(Context, VT: LegalVT);
217
218 // If we got a 512-bit vector then we'll definitely have a vXi1 compare.
219 if (LegalVT.getSimpleVT().is512BitVector())
220 return EVT::getVectorVT(Context, VT: MVT::i1, EC: VT.getVectorElementCount());
221
222 if (LegalVT.getSimpleVT().isVector() && Subtarget.hasVLX()) {
223 // If we legalized to less than a 512-bit vector, then we will use a vXi1
224 // compare for vXi32/vXi64 for sure. If we have BWI we will also support
225 // vXi16/vXi8.
226 MVT EltVT = LegalVT.getSimpleVT().getVectorElementType();
227 if (Subtarget.hasBWI() || EltVT.getSizeInBits() >= 32)
228 return EVT::getVectorVT(Context, VT: MVT::i1, EC: VT.getVectorElementCount());
229 }
230 }
231
232 return VT.changeVectorElementTypeToInteger();
233}
234
235bool X86TargetLowering::functionArgumentNeedsConsecutiveRegisters(
236 Type *Ty, CallingConv::ID CallConv, bool isVarArg,
237 const DataLayout &DL) const {
238 // On x86-64 i128 is split into two i64s and needs to be allocated to two
239 // consecutive registers, or spilled to the stack as a whole. On x86-32 i128
240 // is split to four i32s and never actually passed in registers, but we use
241 // the consecutive register mark to match it in TableGen.
242 if (Ty->isIntegerTy(BitWidth: 128))
243 return true;
244
245 // On x86-32, fp128 acts the same as i128.
246 if (Subtarget.is32Bit() && Ty->isFP128Ty())
247 return true;
248
249 return false;
250}
251
252/// Helper for getByValTypeAlignment to determine
253/// the desired ByVal argument alignment.
254static void getMaxByValAlign(Type *Ty, Align &MaxAlign) {
255 if (MaxAlign == 16)
256 return;
257 if (VectorType *VTy = dyn_cast<VectorType>(Val: Ty)) {
258 if (VTy->getPrimitiveSizeInBits().getFixedValue() == 128)
259 MaxAlign = Align(16);
260 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Val: Ty)) {
261 Align EltAlign;
262 getMaxByValAlign(Ty: ATy->getElementType(), MaxAlign&: EltAlign);
263 if (EltAlign > MaxAlign)
264 MaxAlign = EltAlign;
265 } else if (StructType *STy = dyn_cast<StructType>(Val: Ty)) {
266 for (auto *EltTy : STy->elements()) {
267 Align EltAlign;
268 getMaxByValAlign(Ty: EltTy, MaxAlign&: EltAlign);
269 if (EltAlign > MaxAlign)
270 MaxAlign = EltAlign;
271 if (MaxAlign == 16)
272 break;
273 }
274 }
275}
276
277/// Return the desired alignment for ByVal aggregate
278/// function arguments in the caller parameter area. For X86, aggregates
279/// that contain SSE vectors are placed at 16-byte boundaries while the rest
280/// are at 4-byte boundaries.
281Align X86TargetLowering::getByValTypeAlignment(Type *Ty,
282 const DataLayout &DL) const {
283 if (Subtarget.is64Bit())
284 return std::max(a: DL.getABITypeAlign(Ty), b: Align::Constant<8>());
285
286 Align Alignment(4);
287 if (Subtarget.hasSSE1())
288 getMaxByValAlign(Ty, MaxAlign&: Alignment);
289 return Alignment;
290}
291
292/// It returns EVT::Other if the type should be determined using generic
293/// target-independent logic.
294/// For vector ops we check that the overall size isn't larger than our
295/// preferred vector width.
296EVT X86TargetLowering::getOptimalMemOpType(
297 LLVMContext &Context, const MemOp &Op,
298 const AttributeList &FuncAttributes) const {
299 if (!FuncAttributes.hasFnAttr(Kind: Attribute::NoImplicitFloat)) {
300 if (Op.size() >= 16 &&
301 (!Subtarget.isUnalignedMem16Slow() || Op.isAligned(AlignCheck: Align(16)))) {
302 // FIXME: Check if unaligned 64-byte accesses are slow.
303 if (Op.size() >= 64 && Subtarget.hasAVX512() &&
304 (Subtarget.getPreferVectorWidth() >= 512)) {
305 return Subtarget.hasBWI() ? MVT::v64i8 : MVT::v16i32;
306 }
307 // FIXME: Check if unaligned 32-byte accesses are slow.
308 if (Op.size() >= 32 && Subtarget.hasAVX() &&
309 Subtarget.useLight256BitInstructions()) {
310 // Although this isn't a well-supported type for AVX1, we'll let
311 // legalization and shuffle lowering produce the optimal codegen. If we
312 // choose an optimal type with a vector element larger than a byte,
313 // getMemsetStores() may create an intermediate splat (using an integer
314 // multiply) before we splat as a vector.
315 return MVT::v32i8;
316 }
317 if (Subtarget.hasSSE2() && (Subtarget.getPreferVectorWidth() >= 128))
318 return MVT::v16i8;
319 // TODO: Can SSE1 handle a byte vector?
320 // If we have SSE1 registers we should be able to use them.
321 if (Subtarget.hasSSE1() && (Subtarget.is64Bit() || Subtarget.hasX87()) &&
322 (Subtarget.getPreferVectorWidth() >= 128))
323 return MVT::v4f32;
324 } else if (((Op.isMemcpyOrMemmove() && !Op.isMemcpyStrSrc()) ||
325 Op.isZeroMemset()) &&
326 Op.size() >= 8 && !Subtarget.is64Bit() && Subtarget.hasSSE2()) {
327 // Do not use f64 to lower memcpy if source is string constant. It's
328 // better to use i32 to avoid the loads.
329 // Also, do not use f64 to lower memset unless this is a memset of zeros.
330 // The gymnastics of splatting a byte value into an XMM register and then
331 // only using 8-byte stores (because this is a CPU with slow unaligned
332 // 16-byte accesses) makes that a loser.
333 return MVT::f64;
334 }
335 }
336 // This is a compromise. If we reach here, unaligned accesses may be slow on
337 // this target. However, creating smaller, aligned accesses could be even
338 // slower and would certainly be a lot more code.
339 if (Subtarget.is64Bit() && Op.size() >= 8)
340 return MVT::i64;
341 return MVT::i32;
342}
343
344bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
345 if (VT == MVT::f32)
346 return Subtarget.hasSSE1();
347 if (VT == MVT::f64)
348 return Subtarget.hasSSE2();
349 return true;
350}
351
352static bool isBitAligned(Align Alignment, uint64_t SizeInBits) {
353 return (8 * Alignment.value()) % SizeInBits == 0;
354}
355
356bool X86TargetLowering::isMemoryAccessFast(EVT VT, Align Alignment) const {
357 if (isBitAligned(Alignment, SizeInBits: VT.getSizeInBits()))
358 return true;
359 switch (VT.getSizeInBits()) {
360 default:
361 // 8-byte and under are always assumed to be fast.
362 return true;
363 case 128:
364 return !Subtarget.isUnalignedMem16Slow();
365 case 256:
366 return !Subtarget.isUnalignedMem32Slow();
367 // TODO: What about AVX-512 (512-bit) accesses?
368 }
369}
370
371bool X86TargetLowering::allowsMisalignedMemoryAccesses(
372 EVT VT, unsigned, Align Alignment, MachineMemOperand::Flags Flags,
373 unsigned *Fast) const {
374 if (Fast)
375 *Fast = isMemoryAccessFast(VT, Alignment);
376 // NonTemporal vector memory ops must be aligned.
377 if (!!(Flags & MachineMemOperand::MONonTemporal) && VT.isVector()) {
378 // NT loads can only be vector aligned, so if its less aligned than the
379 // minimum vector size (which we can split the vector down to), we might as
380 // well use a regular unaligned vector load.
381 // We don't have any NT loads pre-SSE41.
382 if (!!(Flags & MachineMemOperand::MOLoad))
383 return (Alignment < 16 || !Subtarget.hasSSE41());
384 return false;
385 }
386 // Misaligned accesses of any size are always allowed.
387 return true;
388}
389
390bool X86TargetLowering::allowsMemoryAccess(LLVMContext &Context,
391 const DataLayout &DL, EVT VT,
392 unsigned AddrSpace, Align Alignment,
393 MachineMemOperand::Flags Flags,
394 unsigned *Fast) const {
395 if (Fast)
396 *Fast = isMemoryAccessFast(VT, Alignment);
397 if (!!(Flags & MachineMemOperand::MONonTemporal) && VT.isVector()) {
398 if (allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags,
399 /*Fast=*/nullptr))
400 return true;
401 // NonTemporal vector memory ops are special, and must be aligned.
402 if (!isBitAligned(Alignment, SizeInBits: VT.getSizeInBits()))
403 return false;
404 switch (VT.getSizeInBits()) {
405 case 128:
406 if (!!(Flags & MachineMemOperand::MOLoad) && Subtarget.hasSSE41())
407 return true;
408 if (!!(Flags & MachineMemOperand::MOStore) && Subtarget.hasSSE2())
409 return true;
410 return false;
411 case 256:
412 if (!!(Flags & MachineMemOperand::MOLoad) && Subtarget.hasAVX2())
413 return true;
414 if (!!(Flags & MachineMemOperand::MOStore) && Subtarget.hasAVX())
415 return true;
416 return false;
417 case 512:
418 if (Subtarget.hasAVX512())
419 return true;
420 return false;
421 default:
422 return false; // Don't have NonTemporal vector memory ops of this size.
423 }
424 }
425 return true;
426}
427
428/// Return the entry encoding for a jump table in the
429/// current function. The returned value is a member of the
430/// MachineJumpTableInfo::JTEntryKind enum.
431unsigned X86TargetLowering::getJumpTableEncoding() const {
432 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
433 // symbol.
434 if (isPositionIndependent() && Subtarget.isPICStyleGOT())
435 return MachineJumpTableInfo::EK_Custom32;
436 if (isPositionIndependent() &&
437 getTargetMachine().getCodeModel() == CodeModel::Large &&
438 !Subtarget.isTargetCOFF())
439 return MachineJumpTableInfo::EK_LabelDifference64;
440
441 // Otherwise, use the normal jump table encoding heuristics.
442 return TargetLowering::getJumpTableEncoding();
443}
444
445bool X86TargetLowering::useSoftFloat() const {
446 return Subtarget.useSoftFloat();
447}
448
449void X86TargetLowering::markLibCallAttributes(MachineFunction *MF, unsigned CC,
450 ArgListTy &Args) const {
451
452 // Only relabel X86-32 for C / Stdcall CCs.
453 if (Subtarget.is64Bit())
454 return;
455 if (CC != CallingConv::C && CC != CallingConv::X86_StdCall)
456 return;
457 unsigned ParamRegs = 0;
458 if (auto *M = MF->getFunction().getParent())
459 ParamRegs = M->getNumberRegisterParameters();
460
461 // Mark the first N int arguments as having reg
462 for (auto &Arg : Args) {
463 Type *T = Arg.Ty;
464 if (T->isIntOrPtrTy())
465 if (MF->getDataLayout().getTypeAllocSize(Ty: T) <= 8) {
466 unsigned numRegs = 1;
467 if (MF->getDataLayout().getTypeAllocSize(Ty: T) > 4)
468 numRegs = 2;
469 if (ParamRegs < numRegs)
470 return;
471 ParamRegs -= numRegs;
472 Arg.IsInReg = true;
473 }
474 }
475}
476
477const MCExpr *
478X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
479 const MachineBasicBlock *MBB,
480 unsigned uid,MCContext &Ctx) const{
481 assert(isPositionIndependent() && Subtarget.isPICStyleGOT());
482 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
483 // entries.
484 return MCSymbolRefExpr::create(Symbol: MBB->getSymbol(), specifier: X86::S_GOTOFF, Ctx);
485}
486
487/// Returns relocation base for the given PIC jumptable.
488SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
489 SelectionDAG &DAG) const {
490 if (!Subtarget.is64Bit())
491 // This doesn't have SDLoc associated with it, but is not really the
492 // same as a Register.
493 return DAG.getNode(Opcode: X86ISD::GlobalBaseReg, DL: SDLoc(),
494 VT: getPointerTy(DL: DAG.getDataLayout()));
495 return Table;
496}
497
498/// This returns the relocation base for the given PIC jumptable,
499/// the same as getPICJumpTableRelocBase, but as an MCExpr.
500const MCExpr *X86TargetLowering::
501getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
502 MCContext &Ctx) const {
503 // X86-64 uses RIP relative addressing based on the jump table label.
504 if (Subtarget.isPICStyleRIPRel() ||
505 (Subtarget.is64Bit() &&
506 getTargetMachine().getCodeModel() == CodeModel::Large))
507 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
508
509 // Otherwise, the reference is relative to the PIC base.
510 return MCSymbolRefExpr::create(Symbol: MF->getPICBaseSymbol(), Ctx);
511}
512
513std::pair<const TargetRegisterClass *, uint8_t>
514X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
515 MVT VT) const {
516 const TargetRegisterClass *RRC = nullptr;
517 uint8_t Cost = 1;
518 switch (VT.SimpleTy) {
519 default:
520 return TargetLowering::findRepresentativeClass(TRI, VT);
521 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
522 RRC = Subtarget.is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
523 break;
524 case MVT::x86mmx:
525 RRC = &X86::VR64RegClass;
526 break;
527 case MVT::f32: case MVT::f64:
528 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
529 case MVT::v4f32: case MVT::v2f64:
530 case MVT::v32i8: case MVT::v16i16: case MVT::v8i32: case MVT::v4i64:
531 case MVT::v8f32: case MVT::v4f64:
532 case MVT::v64i8: case MVT::v32i16: case MVT::v16i32: case MVT::v8i64:
533 case MVT::v16f32: case MVT::v8f64:
534 RRC = &X86::VR128XRegClass;
535 break;
536 }
537 return std::make_pair(x&: RRC, y&: Cost);
538}
539
540unsigned X86TargetLowering::getAddressSpace() const {
541 if (Subtarget.is64Bit())
542 return (getTargetMachine().getCodeModel() == CodeModel::Kernel) ? X86AS::GS
543 : X86AS::FS;
544 return X86AS::GS;
545}
546
547static bool hasStackGuardSlotTLS(const Triple &TargetTriple) {
548 return TargetTriple.isOSGlibc() || TargetTriple.isMusl() ||
549 TargetTriple.isOSFuchsia() || TargetTriple.isAndroid();
550}
551
552static Constant* SegmentOffset(IRBuilderBase &IRB,
553 int Offset, unsigned AddressSpace) {
554 return ConstantExpr::getIntToPtr(
555 C: ConstantInt::getSigned(Ty: Type::getInt32Ty(C&: IRB.getContext()), V: Offset),
556 Ty: IRB.getPtrTy(AddrSpace: AddressSpace));
557}
558
559Value *
560X86TargetLowering::getIRStackGuard(IRBuilderBase &IRB,
561 const LibcallLoweringInfo &Libcalls) const {
562 // glibc, bionic, and Fuchsia have a special slot for the stack guard in
563 // tcbhead_t; use it instead of the usual global variable (see
564 // sysdeps/{i386,x86_64}/nptl/tls.h)
565 if (hasStackGuardSlotTLS(TargetTriple: Subtarget.getTargetTriple())) {
566 unsigned AddressSpace = getAddressSpace();
567
568 // <zircon/tls.h> defines ZX_TLS_STACK_GUARD_OFFSET with this value.
569 if (Subtarget.isTargetFuchsia())
570 return SegmentOffset(IRB, Offset: 0x10, AddressSpace);
571
572 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
573 // Specially, some users may customize the base reg and offset.
574 int Offset = M->getStackProtectorGuardOffset();
575 // If we don't set -stack-protector-guard-offset value:
576 // %fs:0x28, unless we're using a Kernel code model, in which case
577 // it's %gs:0x28. gs:0x14 on i386.
578 if (Offset == INT_MAX)
579 Offset = (Subtarget.is64Bit()) ? 0x28 : 0x14;
580
581 StringRef GuardReg = M->getStackProtectorGuardReg();
582 if (GuardReg == "fs")
583 AddressSpace = X86AS::FS;
584 else if (GuardReg == "gs")
585 AddressSpace = X86AS::GS;
586
587 // Use symbol guard if user specify.
588 StringRef GuardSymb = M->getStackProtectorGuardSymbol();
589 if (!GuardSymb.empty()) {
590 GlobalVariable *GV = M->getGlobalVariable(Name: GuardSymb);
591 if (!GV) {
592 Type *Ty = Subtarget.is64Bit() ? Type::getInt64Ty(C&: M->getContext())
593 : Type::getInt32Ty(C&: M->getContext());
594 GV = new GlobalVariable(*M, Ty, false, GlobalValue::ExternalLinkage,
595 nullptr, GuardSymb, nullptr,
596 GlobalValue::NotThreadLocal, AddressSpace);
597 if (!Subtarget.isTargetDarwin())
598 GV->setDSOLocal(M->getDirectAccessExternalData());
599 }
600 return GV;
601 }
602
603 return SegmentOffset(IRB, Offset, AddressSpace);
604 }
605 return TargetLowering::getIRStackGuard(IRB, Libcalls);
606}
607
608void X86TargetLowering::insertSSPDeclarations(
609 Module &M, const LibcallLoweringInfo &Libcalls) const {
610 // MSVC CRT provides functionalities for stack protection.
611 RTLIB::LibcallImpl SecurityCheckCookieLibcall =
612 Libcalls.getLibcallImpl(Call: RTLIB::SECURITY_CHECK_COOKIE);
613
614 RTLIB::LibcallImpl SecurityCookieVar =
615 Libcalls.getLibcallImpl(Call: RTLIB::STACK_CHECK_GUARD);
616 if (SecurityCheckCookieLibcall != RTLIB::Unsupported &&
617 SecurityCookieVar != RTLIB::Unsupported) {
618 // MSVC CRT provides functionalities for stack protection.
619 // MSVC CRT has a global variable holding security cookie.
620 M.getOrInsertGlobal(Name: getLibcallImplName(Call: SecurityCookieVar),
621 Ty: PointerType::getUnqual(C&: M.getContext()));
622
623 // MSVC CRT has a function to validate security cookie.
624 FunctionCallee SecurityCheckCookie =
625 M.getOrInsertFunction(Name: getLibcallImplName(Call: SecurityCheckCookieLibcall),
626 RetTy: Type::getVoidTy(C&: M.getContext()),
627 Args: PointerType::getUnqual(C&: M.getContext()));
628
629 if (Function *F = dyn_cast<Function>(Val: SecurityCheckCookie.getCallee())) {
630 F->setCallingConv(CallingConv::X86_FastCall);
631 F->addParamAttr(ArgNo: 0, Kind: Attribute::AttrKind::InReg);
632 }
633 return;
634 }
635
636 StringRef GuardMode = M.getStackProtectorGuard();
637
638 // glibc, bionic, and Fuchsia have a special slot for the stack guard.
639 if ((GuardMode == "tls" || GuardMode.empty()) &&
640 hasStackGuardSlotTLS(TargetTriple: Subtarget.getTargetTriple()))
641 return;
642 TargetLowering::insertSSPDeclarations(M, Libcalls);
643}
644
645Value *X86TargetLowering::getSafeStackPointerLocation(
646 IRBuilderBase &IRB, const LibcallLoweringInfo &Libcalls) const {
647 // Android provides a fixed TLS slot for the SafeStack pointer. See the
648 // definition of TLS_SLOT_SAFESTACK in
649 // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
650 if (Subtarget.isTargetAndroid()) {
651 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
652 // %gs:0x24 on i386
653 int Offset = (Subtarget.is64Bit()) ? 0x48 : 0x24;
654 return SegmentOffset(IRB, Offset, AddressSpace: getAddressSpace());
655 }
656
657 // Fuchsia is similar.
658 if (Subtarget.isTargetFuchsia()) {
659 // <zircon/tls.h> defines ZX_TLS_UNSAFE_SP_OFFSET with this value.
660 return SegmentOffset(IRB, Offset: 0x18, AddressSpace: getAddressSpace());
661 }
662
663 return TargetLowering::getSafeStackPointerLocation(IRB, Libcalls);
664}
665
666//===----------------------------------------------------------------------===//
667// Return Value Calling Convention Implementation
668//===----------------------------------------------------------------------===//
669
670bool X86TargetLowering::CanLowerReturn(
671 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
672 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
673 const Type *RetTy) const {
674 // Mingw64 GCC returns f128 via sret, and LLVM matches it for compatibility.
675 // This logic exists for libcalls, a frontend should explicitly use sret
676 // rather than rely on the sret demotion here.
677 //
678 // Using sret is a reasonable implementation of the Windows x64 calling
679 // convention:
680 //
681 // https://learn.microsoft.com/en-us/cpp/build/x64-calling-convention?view=msvc-170#return-values
682 //
683 // > Otherwise, the caller must allocate memory for the return value and pass
684 // > a pointer to it as the first argument.
685 //
686 // Although it is not the only reasonable interpretation:
687 //
688 // > Nonscalar types including floats, doubles, and vector types such as
689 // > __m128, __m128i, __m128d are returned in XMM0.
690 //
691 // For now, we prefer compatibility with GCC. If official guidelines are ever
692 // published, this can be revisited.
693 //
694 // Return false, which will perform sret demotion.
695 auto IsWin64F128StackCC = [this](CallingConv::ID CC) -> bool {
696 switch (CC) {
697 case CallingConv::Win64:
698 return true;
699 case CallingConv::C:
700 return Subtarget.isOSWindowsOrUEFI();
701 default:
702 return false;
703 }
704 };
705
706 if (IsWin64F128StackCC(CallConv) &&
707 llvm::any_of(
708 Range: Outs, P: [](const ISD::OutputArg &Out) { return Out.VT == MVT::f128; }))
709 return false;
710
711 SmallVector<CCValAssign, 16> RVLocs;
712 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
713 return CCInfo.CheckReturn(Outs, Fn: RetCC_X86);
714}
715
716const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
717 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
718 return ScratchRegs;
719}
720
721ArrayRef<MCPhysReg> X86TargetLowering::getRoundingControlRegisters() const {
722 static const MCPhysReg RCRegs[] = {X86::FPCW, X86::MXCSR};
723 return RCRegs;
724}
725
726/// Lowers masks values (v*i1) to the local register values
727/// \returns DAG node after lowering to register type
728static SDValue lowerMasksToReg(const SDValue &ValArg, const EVT &ValLoc,
729 const SDLoc &DL, SelectionDAG &DAG) {
730 EVT ValVT = ValArg.getValueType();
731
732 if (ValVT == MVT::v1i1)
733 return DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: ValLoc, N1: ValArg,
734 N2: DAG.getIntPtrConstant(Val: 0, DL));
735
736 if ((ValVT == MVT::v8i1 && (ValLoc == MVT::i8 || ValLoc == MVT::i32)) ||
737 (ValVT == MVT::v16i1 && (ValLoc == MVT::i16 || ValLoc == MVT::i32))) {
738 // Two stage lowering might be required
739 // bitcast: v8i1 -> i8 / v16i1 -> i16
740 // anyextend: i8 -> i32 / i16 -> i32
741 EVT TempValLoc = ValVT == MVT::v8i1 ? MVT::i8 : MVT::i16;
742 SDValue ValToCopy = DAG.getBitcast(VT: TempValLoc, V: ValArg);
743 if (ValLoc == MVT::i32)
744 ValToCopy = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: ValLoc, Operand: ValToCopy);
745 return ValToCopy;
746 }
747
748 if ((ValVT == MVT::v32i1 && ValLoc == MVT::i32) ||
749 (ValVT == MVT::v64i1 && ValLoc == MVT::i64)) {
750 // One stage lowering is required
751 // bitcast: v32i1 -> i32 / v64i1 -> i64
752 return DAG.getBitcast(VT: ValLoc, V: ValArg);
753 }
754
755 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: ValLoc, Operand: ValArg);
756}
757
758/// Breaks v64i1 value into two registers and adds the new node to the DAG
759static void Passv64i1ArgInRegs(
760 const SDLoc &DL, SelectionDAG &DAG, SDValue &Arg,
761 SmallVectorImpl<std::pair<Register, SDValue>> &RegsToPass, CCValAssign &VA,
762 CCValAssign &NextVA, const X86Subtarget &Subtarget) {
763 assert(Subtarget.hasBWI() && "Expected AVX512BW target!");
764 assert(Subtarget.is32Bit() && "Expecting 32 bit target");
765 assert(Arg.getValueType() == MVT::i64 && "Expecting 64 bit value");
766 assert(VA.isRegLoc() && NextVA.isRegLoc() &&
767 "The value should reside in two registers");
768
769 // Before splitting the value we cast it to i64
770 Arg = DAG.getBitcast(VT: MVT::i64, V: Arg);
771
772 // Splitting the value into two i32 types
773 SDValue Lo, Hi;
774 std::tie(args&: Lo, args&: Hi) = DAG.SplitScalar(N: Arg, DL, LoVT: MVT::i32, HiVT: MVT::i32);
775
776 // Attach the two i32 types into corresponding registers
777 RegsToPass.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: Lo));
778 RegsToPass.push_back(Elt: std::make_pair(x: NextVA.getLocReg(), y&: Hi));
779}
780
781SDValue
782X86TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
783 bool isVarArg,
784 const SmallVectorImpl<ISD::OutputArg> &Outs,
785 const SmallVectorImpl<SDValue> &OutVals,
786 const SDLoc &dl, SelectionDAG &DAG) const {
787 MachineFunction &MF = DAG.getMachineFunction();
788 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
789
790 // In some cases we need to disable registers from the default CSR list.
791 // For example, when they are used as return registers (preserve_* and X86's
792 // regcall) or for argument passing (X86's regcall).
793 bool ShouldDisableCalleeSavedRegister =
794 shouldDisableRetRegFromCSR(CC: CallConv) ||
795 MF.getFunction().hasFnAttribute(Kind: "no_caller_saved_registers");
796
797 if (CallConv == CallingConv::X86_INTR && !Outs.empty())
798 report_fatal_error(reason: "X86 interrupts may not return any value");
799
800 SmallVector<CCValAssign, 16> RVLocs;
801 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
802 CCInfo.AnalyzeReturn(Outs, Fn: RetCC_X86);
803
804 SmallVector<std::pair<Register, SDValue>, 4> RetVals;
805 for (unsigned I = 0, OutsIndex = 0, E = RVLocs.size(); I != E;
806 ++I, ++OutsIndex) {
807 CCValAssign &VA = RVLocs[I];
808 assert(VA.isRegLoc() && "Can only return in registers!");
809
810 // Add the register to the CalleeSaveDisableRegs list.
811 if (ShouldDisableCalleeSavedRegister)
812 MF.getRegInfo().disableCalleeSavedRegister(Reg: VA.getLocReg());
813
814 SDValue ValToCopy = OutVals[OutsIndex];
815 EVT ValVT = ValToCopy.getValueType();
816
817 // Promote values to the appropriate types.
818 if (VA.getLocInfo() == CCValAssign::SExt)
819 ValToCopy = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL: dl, VT: VA.getLocVT(), Operand: ValToCopy);
820 else if (VA.getLocInfo() == CCValAssign::ZExt)
821 ValToCopy = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: VA.getLocVT(), Operand: ValToCopy);
822 else if (VA.getLocInfo() == CCValAssign::AExt) {
823 if (ValVT.isVectorOf(EltVT: MVT::i1))
824 ValToCopy = lowerMasksToReg(ValArg: ValToCopy, ValLoc: VA.getLocVT(), DL: dl, DAG);
825 else
826 ValToCopy = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: VA.getLocVT(), Operand: ValToCopy);
827 }
828 else if (VA.getLocInfo() == CCValAssign::BCvt)
829 ValToCopy = DAG.getBitcast(VT: VA.getLocVT(), V: ValToCopy);
830
831 assert(VA.getLocInfo() != CCValAssign::FPExt &&
832 "Unexpected FP-extend for return value.");
833
834 // Report an error if we have attempted to return a value via an XMM
835 // register and SSE was disabled.
836 if (!Subtarget.hasSSE1() && X86::FR32XRegClass.contains(Reg: VA.getLocReg())) {
837 errorUnsupported(DAG, dl, Msg: "SSE register return with SSE disabled");
838 VA.convertToReg(Reg: X86::FP0); // Set reg to FP0, avoid hitting asserts.
839 } else if (!Subtarget.hasSSE2() &&
840 X86::FR64XRegClass.contains(Reg: VA.getLocReg()) &&
841 ValVT == MVT::f64) {
842 // When returning a double via an XMM register, report an error if SSE2 is
843 // not enabled.
844 errorUnsupported(DAG, dl, Msg: "SSE2 register return with SSE2 disabled");
845 VA.convertToReg(Reg: X86::FP0); // Set reg to FP0, avoid hitting asserts.
846 }
847
848 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
849 // the RET instruction and handled by the FP Stackifier.
850 if (VA.getLocReg() == X86::FP0 ||
851 VA.getLocReg() == X86::FP1) {
852 // If this is a copy from an xmm register to ST(0), use an FPExtend to
853 // change the value to the FP stack register class.
854 if (isScalarFPTypeInSSEReg(VT: VA.getValVT()))
855 ValToCopy = DAG.getNode(Opcode: ISD::FP_EXTEND, DL: dl, VT: MVT::f80, Operand: ValToCopy);
856 RetVals.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: ValToCopy));
857 // Don't emit a copytoreg.
858 continue;
859 }
860
861 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
862 // which is returned in RAX / RDX.
863 if (Subtarget.is64Bit()) {
864 if (ValVT == MVT::x86mmx) {
865 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
866 ValToCopy = DAG.getBitcast(VT: MVT::i64, V: ValToCopy);
867 ValToCopy = DAG.getNode(Opcode: ISD::SCALAR_TO_VECTOR, DL: dl, VT: MVT::v2i64,
868 Operand: ValToCopy);
869 // If we don't have SSE2 available, convert to v4f32 so the generated
870 // register is legal.
871 if (!Subtarget.hasSSE2())
872 ValToCopy = DAG.getBitcast(VT: MVT::v4f32, V: ValToCopy);
873 }
874 }
875 }
876
877 if (VA.needsCustom()) {
878 assert(VA.getValVT() == MVT::v64i1 &&
879 "Currently the only custom case is when we split v64i1 to 2 regs");
880
881 Passv64i1ArgInRegs(DL: dl, DAG, Arg&: ValToCopy, RegsToPass&: RetVals, VA, NextVA&: RVLocs[++I],
882 Subtarget);
883
884 // Add the second register to the CalleeSaveDisableRegs list.
885 if (ShouldDisableCalleeSavedRegister)
886 MF.getRegInfo().disableCalleeSavedRegister(Reg: RVLocs[I].getLocReg());
887 } else {
888 RetVals.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: ValToCopy));
889 }
890 }
891
892 SDValue Glue;
893 SmallVector<SDValue, 6> RetOps;
894 RetOps.push_back(Elt: Chain); // Operand #0 = Chain (updated below)
895 // Operand #1 = Bytes To Pop
896 RetOps.push_back(Elt: DAG.getTargetConstant(Val: FuncInfo->getBytesToPopOnReturn(), DL: dl,
897 VT: MVT::i32));
898
899 // Copy the result values into the output registers.
900 for (auto &RetVal : RetVals) {
901 if (RetVal.first == X86::FP0 || RetVal.first == X86::FP1) {
902 RetOps.push_back(Elt: RetVal.second);
903 continue; // Don't emit a copytoreg.
904 }
905
906 Chain = DAG.getCopyToReg(Chain, dl, Reg: RetVal.first, N: RetVal.second, Glue);
907 Glue = Chain.getValue(R: 1);
908 RetOps.push_back(
909 Elt: DAG.getRegister(Reg: RetVal.first, VT: RetVal.second.getValueType()));
910 }
911
912 // Swift calling convention does not require we copy the sret argument
913 // into %rax/%eax for the return, and SRetReturnReg is not set for Swift.
914
915 // All x86 ABIs require that for returning structs by value we copy
916 // the sret argument into %rax/%eax (depending on ABI) for the return.
917 // We saved the argument into a virtual register in the entry block,
918 // so now we copy the value out and into %rax/%eax.
919 //
920 // Checking Function.hasStructRetAttr() here is insufficient because the IR
921 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
922 // false, then an sret argument may be implicitly inserted in the SelDAG. In
923 // either case FuncInfo->setSRetReturnReg() will have been called.
924 if (Register SRetReg = FuncInfo->getSRetReturnReg()) {
925 // When we have both sret and another return value, we should use the
926 // original Chain stored in RetOps[0], instead of the current Chain updated
927 // in the above loop. If we only have sret, RetOps[0] equals to Chain.
928
929 // For the case of sret and another return value, we have
930 // Chain_0 at the function entry
931 // Chain_1 = getCopyToReg(Chain_0) in the above loop
932 // If we use Chain_1 in getCopyFromReg, we will have
933 // Val = getCopyFromReg(Chain_1)
934 // Chain_2 = getCopyToReg(Chain_1, Val) from below
935
936 // getCopyToReg(Chain_0) will be glued together with
937 // getCopyToReg(Chain_1, Val) into Unit A, getCopyFromReg(Chain_1) will be
938 // in Unit B, and we will have cyclic dependency between Unit A and Unit B:
939 // Data dependency from Unit B to Unit A due to usage of Val in
940 // getCopyToReg(Chain_1, Val)
941 // Chain dependency from Unit A to Unit B
942
943 // So here, we use RetOps[0] (i.e Chain_0) for getCopyFromReg.
944 SDValue Val = DAG.getCopyFromReg(Chain: RetOps[0], dl, Reg: SRetReg,
945 VT: getPointerTy(DL: MF.getDataLayout()));
946
947 Register RetValReg
948 = (Subtarget.is64Bit() && !Subtarget.isTarget64BitILP32()) ?
949 X86::RAX : X86::EAX;
950 Chain = DAG.getCopyToReg(Chain, dl, Reg: RetValReg, N: Val, Glue);
951 Glue = Chain.getValue(R: 1);
952
953 // RAX/EAX now acts like a return value.
954 RetOps.push_back(
955 Elt: DAG.getRegister(Reg: RetValReg, VT: getPointerTy(DL: DAG.getDataLayout())));
956
957 // Add the returned register to the CalleeSaveDisableRegs list. Don't do
958 // this however for preserve_most/preserve_all to minimize the number of
959 // callee-saved registers for these CCs.
960 if (ShouldDisableCalleeSavedRegister &&
961 CallConv != CallingConv::PreserveAll &&
962 CallConv != CallingConv::PreserveMost)
963 MF.getRegInfo().disableCalleeSavedRegister(Reg: RetValReg);
964 }
965
966 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
967 const MCPhysReg *I =
968 TRI->getCalleeSavedRegsViaCopy(MF: &DAG.getMachineFunction());
969 if (I) {
970 for (; *I; ++I) {
971 if (X86::GR64RegClass.contains(Reg: *I))
972 RetOps.push_back(Elt: DAG.getRegister(Reg: *I, VT: MVT::i64));
973 else
974 llvm_unreachable("Unexpected register class in CSRsViaCopy!");
975 }
976 }
977
978 RetOps[0] = Chain; // Update chain.
979
980 // Add the glue if we have it.
981 if (Glue.getNode())
982 RetOps.push_back(Elt: Glue);
983
984 unsigned RetOpcode = X86ISD::RET_GLUE;
985 if (CallConv == CallingConv::X86_INTR)
986 RetOpcode = X86ISD::IRET;
987 return DAG.getNode(Opcode: RetOpcode, DL: dl, VT: MVT::Other, Ops: RetOps);
988}
989
990bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
991 if (N->getNumValues() != 1 || !N->hasNUsesOfValue(NUses: 1, Value: 0))
992 return false;
993
994 SDValue TCChain = Chain;
995 SDNode *Copy = *N->user_begin();
996 if (Copy->getOpcode() == ISD::CopyToReg) {
997 // If the copy has a glue operand, we conservatively assume it isn't safe to
998 // perform a tail call.
999 if (Copy->getOperand(Num: Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1000 return false;
1001 TCChain = Copy->getOperand(Num: 0);
1002 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1003 return false;
1004
1005 bool HasRet = false;
1006 for (const SDNode *U : Copy->users()) {
1007 if (U->getOpcode() != X86ISD::RET_GLUE)
1008 return false;
1009 // If we are returning more than one value, we can definitely
1010 // not make a tail call see PR19530
1011 if (U->getNumOperands() > 4)
1012 return false;
1013 if (U->getNumOperands() == 4 &&
1014 U->getOperand(Num: U->getNumOperands() - 1).getValueType() != MVT::Glue)
1015 return false;
1016 HasRet = true;
1017 }
1018
1019 if (!HasRet)
1020 return false;
1021
1022 Chain = TCChain;
1023 return true;
1024}
1025
1026EVT X86TargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,
1027 ISD::NodeType ExtendKind) const {
1028 MVT ReturnMVT = MVT::i32;
1029
1030 bool Darwin = Subtarget.getTargetTriple().isOSDarwin();
1031 if (VT == MVT::i1 || (!Darwin && (VT == MVT::i8 || VT == MVT::i16))) {
1032 // The ABI does not require i1, i8 or i16 to be extended.
1033 //
1034 // On Darwin, there is code in the wild relying on Clang's old behaviour of
1035 // always extending i8/i16 return values, so keep doing that for now.
1036 // (PR26665).
1037 ReturnMVT = MVT::i8;
1038 }
1039
1040 EVT MinVT = getRegisterType(Context, VT: ReturnMVT);
1041 return VT.bitsLT(VT: MinVT) ? MinVT : VT;
1042}
1043
1044/// Reads two 32 bit registers and creates a 64 bit mask value.
1045/// \param VA The current 32 bit value that need to be assigned.
1046/// \param NextVA The next 32 bit value that need to be assigned.
1047/// \param Root The parent DAG node.
1048/// \param [in,out] InGlue Represents SDvalue in the parent DAG node for
1049/// glue purposes. In the case the DAG is already using
1050/// physical register instead of virtual, we should glue
1051/// our new SDValue to InGlue SDvalue.
1052/// \return a new SDvalue of size 64bit.
1053static SDValue getv64i1Argument(CCValAssign &VA, CCValAssign &NextVA,
1054 SDValue &Root, SelectionDAG &DAG,
1055 const SDLoc &DL, const X86Subtarget &Subtarget,
1056 SDValue *InGlue = nullptr) {
1057 assert((Subtarget.hasBWI()) && "Expected AVX512BW target!");
1058 assert(Subtarget.is32Bit() && "Expecting 32 bit target");
1059 assert(VA.getValVT() == MVT::v64i1 &&
1060 "Expecting first location of 64 bit width type");
1061 assert(NextVA.getValVT() == VA.getValVT() &&
1062 "The locations should have the same type");
1063 assert(VA.isRegLoc() && NextVA.isRegLoc() &&
1064 "The values should reside in two registers");
1065
1066 SDValue Lo, Hi;
1067 SDValue ArgValueLo, ArgValueHi;
1068
1069 MachineFunction &MF = DAG.getMachineFunction();
1070 const TargetRegisterClass *RC = &X86::GR32RegClass;
1071
1072 // Read a 32 bit value from the registers.
1073 if (nullptr == InGlue) {
1074 // When no physical register is present,
1075 // create an intermediate virtual register.
1076 Register Reg = MF.addLiveIn(PReg: VA.getLocReg(), RC);
1077 ArgValueLo = DAG.getCopyFromReg(Chain: Root, dl: DL, Reg, VT: MVT::i32);
1078 Reg = MF.addLiveIn(PReg: NextVA.getLocReg(), RC);
1079 ArgValueHi = DAG.getCopyFromReg(Chain: Root, dl: DL, Reg, VT: MVT::i32);
1080 } else {
1081 // When a physical register is available read the value from it and glue
1082 // the reads together.
1083 ArgValueLo =
1084 DAG.getCopyFromReg(Chain: Root, dl: DL, Reg: VA.getLocReg(), VT: MVT::i32, Glue: *InGlue);
1085 *InGlue = ArgValueLo.getValue(R: 2);
1086 ArgValueHi =
1087 DAG.getCopyFromReg(Chain: Root, dl: DL, Reg: NextVA.getLocReg(), VT: MVT::i32, Glue: *InGlue);
1088 *InGlue = ArgValueHi.getValue(R: 2);
1089 }
1090
1091 // Convert the i32 type into v32i1 type.
1092 Lo = DAG.getBitcast(VT: MVT::v32i1, V: ArgValueLo);
1093
1094 // Convert the i32 type into v32i1 type.
1095 Hi = DAG.getBitcast(VT: MVT::v32i1, V: ArgValueHi);
1096
1097 // Concatenate the two values together.
1098 return DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL, VT: MVT::v64i1, N1: Lo, N2: Hi);
1099}
1100
1101/// The function will lower a register of various sizes (8/16/32/64)
1102/// to a mask value of the expected size (v8i1/v16i1/v32i1/v64i1)
1103/// \returns a DAG node contains the operand after lowering to mask type.
1104static SDValue lowerRegToMasks(const SDValue &ValArg, const EVT &ValVT,
1105 const EVT &ValLoc, const SDLoc &DL,
1106 SelectionDAG &DAG) {
1107 SDValue ValReturned = ValArg;
1108
1109 if (ValVT == MVT::v1i1)
1110 return DAG.getNode(Opcode: ISD::SCALAR_TO_VECTOR, DL, VT: MVT::v1i1, Operand: ValReturned);
1111
1112 if (ValVT == MVT::v64i1) {
1113 // In 32 bit machine, this case is handled by getv64i1Argument
1114 assert(ValLoc == MVT::i64 && "Expecting only i64 locations");
1115 // In 64 bit machine, There is no need to truncate the value only bitcast
1116 } else {
1117 MVT MaskLenVT;
1118 switch (ValVT.getSimpleVT().SimpleTy) {
1119 case MVT::v8i1:
1120 MaskLenVT = MVT::i8;
1121 break;
1122 case MVT::v16i1:
1123 MaskLenVT = MVT::i16;
1124 break;
1125 case MVT::v32i1:
1126 MaskLenVT = MVT::i32;
1127 break;
1128 default:
1129 llvm_unreachable("Expecting a vector of i1 types");
1130 }
1131
1132 ValReturned = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: MaskLenVT, Operand: ValReturned);
1133 }
1134 return DAG.getBitcast(VT: ValVT, V: ValReturned);
1135}
1136
1137static SDValue getPopFromX87Reg(SelectionDAG &DAG, SDValue Chain,
1138 const SDLoc &dl, Register Reg, EVT VT,
1139 SDValue Glue) {
1140 SDVTList VTs = DAG.getVTList(VT1: VT, VT2: MVT::Other, VT3: MVT::Glue);
1141 SDValue Ops[] = {Chain, DAG.getRegister(Reg, VT), Glue};
1142 return DAG.getNode(Opcode: X86ISD::POP_FROM_X87_REG, DL: dl, VTList: VTs,
1143 Ops: ArrayRef(Ops, Glue.getNode() ? 3 : 2));
1144}
1145
1146/// Lower the result values of a call into the
1147/// appropriate copies out of appropriate physical registers.
1148///
1149SDValue X86TargetLowering::LowerCallResult(
1150 SDValue Chain, SDValue InGlue, CallingConv::ID CallConv, bool isVarArg,
1151 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1152 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
1153 uint32_t *RegMask) const {
1154
1155 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1156 // Assign locations to each value returned by this call.
1157 SmallVector<CCValAssign, 16> RVLocs;
1158 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1159 *DAG.getContext());
1160 CCInfo.AnalyzeCallResult(Ins, Fn: RetCC_X86);
1161
1162 // Copy all of the result registers out of their specified physreg.
1163 for (unsigned I = 0, E = RVLocs.size(); I != E; ++I) {
1164 CCValAssign &VA = RVLocs[I];
1165 EVT CopyVT = VA.getLocVT();
1166
1167 // In some calling conventions we need to remove the used registers
1168 // from the register mask.
1169 if (RegMask) {
1170 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg: VA.getLocReg()))
1171 RegMask[SubReg / 32] &= ~(1u << (SubReg % 32));
1172 }
1173
1174 // Report an error if there was an attempt to return FP values via XMM
1175 // registers.
1176 if (!Subtarget.hasSSE1() && X86::FR32XRegClass.contains(Reg: VA.getLocReg())) {
1177 errorUnsupported(DAG, dl, Msg: "SSE register return with SSE disabled");
1178 if (VA.getLocReg() == X86::XMM1)
1179 VA.convertToReg(Reg: X86::FP1); // Set reg to FP1, avoid hitting asserts.
1180 else
1181 VA.convertToReg(Reg: X86::FP0); // Set reg to FP0, avoid hitting asserts.
1182 } else if (!Subtarget.hasSSE2() &&
1183 X86::FR64XRegClass.contains(Reg: VA.getLocReg()) &&
1184 CopyVT == MVT::f64) {
1185 errorUnsupported(DAG, dl, Msg: "SSE2 register return with SSE2 disabled");
1186 if (VA.getLocReg() == X86::XMM1)
1187 VA.convertToReg(Reg: X86::FP1); // Set reg to FP1, avoid hitting asserts.
1188 else
1189 VA.convertToReg(Reg: X86::FP0); // Set reg to FP0, avoid hitting asserts.
1190 }
1191
1192 // If we prefer to use the value in xmm registers, copy it out as f80 and
1193 // use a truncate to move it from fp stack reg to xmm reg.
1194 bool RoundAfterCopy = false;
1195 bool X87Result = VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1;
1196 if (X87Result && isScalarFPTypeInSSEReg(VT: VA.getValVT())) {
1197 if (!Subtarget.hasX87())
1198 report_fatal_error(reason: "X87 register return with X87 disabled");
1199 CopyVT = MVT::f80;
1200 RoundAfterCopy = (CopyVT != VA.getLocVT());
1201 }
1202
1203 SDValue Val;
1204 if (VA.needsCustom()) {
1205 assert(VA.getValVT() == MVT::v64i1 &&
1206 "Currently the only custom case is when we split v64i1 to 2 regs");
1207 Val =
1208 getv64i1Argument(VA, NextVA&: RVLocs[++I], Root&: Chain, DAG, DL: dl, Subtarget, InGlue: &InGlue);
1209 } else {
1210 Chain =
1211 X87Result
1212 ? getPopFromX87Reg(DAG, Chain, dl, Reg: VA.getLocReg(), VT: CopyVT, Glue: InGlue)
1213 .getValue(R: 1)
1214 : DAG.getCopyFromReg(Chain, dl, Reg: VA.getLocReg(), VT: CopyVT, Glue: InGlue)
1215 .getValue(R: 1);
1216 Val = Chain.getValue(R: 0);
1217 InGlue = Chain.getValue(R: 2);
1218 }
1219
1220 if (RoundAfterCopy)
1221 Val = DAG.getNode(Opcode: ISD::FP_ROUND, DL: dl, VT: VA.getValVT(), N1: Val,
1222 // This truncation won't change the value.
1223 N2: DAG.getIntPtrConstant(Val: 1, DL: dl, /*isTarget=*/true));
1224
1225 if (VA.isExtInLoc()) {
1226 if (VA.getValVT().isVector() &&
1227 VA.getValVT().getScalarType() == MVT::i1 &&
1228 ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) ||
1229 (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) {
1230 // promoting a mask type (v*i1) into a register of type i64/i32/i16/i8
1231 Val = lowerRegToMasks(ValArg: Val, ValVT: VA.getValVT(), ValLoc: VA.getLocVT(), DL: dl, DAG);
1232 } else
1233 Val = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: VA.getValVT(), Operand: Val);
1234 }
1235
1236 if (VA.getLocInfo() == CCValAssign::BCvt)
1237 Val = DAG.getBitcast(VT: VA.getValVT(), V: Val);
1238
1239 InVals.push_back(Elt: Val);
1240 }
1241
1242 return Chain;
1243}
1244
1245/// Determines whether Args, either a set of outgoing arguments to a call, or a
1246/// set of incoming args of a call, contains an sret pointer that the callee
1247/// pops. This happens on most x86-32, System V platforms, unless register
1248/// parameters are in use (-mregparm=1+, regcallcc, etc).
1249template <typename T>
1250static bool hasCalleePopSRet(const SmallVectorImpl<T> &Args,
1251 const SmallVectorImpl<CCValAssign> &ArgLocs,
1252 const X86Subtarget &Subtarget) {
1253 // Not C++20 (yet), so no concepts available.
1254 static_assert(std::is_same_v<T, ISD::OutputArg> ||
1255 std::is_same_v<T, ISD::InputArg>,
1256 "requires ISD::OutputArg or ISD::InputArg");
1257
1258 // Popping the sret pointer only happens on x86-32 System V ABI platforms
1259 // (Linux, Cygwin, BSDs, Mac, etc). That excludes Windows-minus-Cygwin and
1260 // MCU.
1261 const Triple &TT = Subtarget.getTargetTriple();
1262 if (!TT.isX86_32() || TT.isOSMSVCRT() || TT.isOSIAMCU())
1263 return false;
1264
1265 // Check if the first argument is marked sret and if it is passed in memory.
1266 bool IsSRetInMem = false;
1267 if (!Args.empty())
1268 IsSRetInMem = Args.front().Flags.isSRet() && ArgLocs.front().isMemLoc();
1269 return IsSRetInMem;
1270}
1271
1272/// Make a copy of an aggregate at address specified by "Src" to address
1273/// "Dst" with size and alignment information specified by the specific
1274/// parameter attribute. The copy will be passed as a byval function parameter.
1275static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
1276 SDValue Chain, ISD::ArgFlagsTy Flags,
1277 SelectionDAG &DAG, const SDLoc &dl) {
1278 SDValue SizeNode = DAG.getIntPtrConstant(Val: Flags.getByValSize(), DL: dl);
1279 Align Alignment = Flags.getNonZeroByValAlign();
1280 return DAG.getMemcpy(Chain, dl, Dst, Src, Size: SizeNode, DstAlign: Alignment, SrcAlign: Alignment,
1281 /*isVolatile*/ isVol: false, /*AlwaysInline=*/true,
1282 /*CI=*/nullptr, OverrideTailCall: std::nullopt, DstPtrInfo: MachinePointerInfo(),
1283 SrcPtrInfo: MachinePointerInfo());
1284}
1285
1286/// Return true if the calling convention is one that we can guarantee TCO for.
1287static bool canGuaranteeTCO(CallingConv::ID CC) {
1288 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
1289 CC == CallingConv::X86_RegCall || CC == CallingConv::HiPE ||
1290 CC == CallingConv::Tail || CC == CallingConv::SwiftTail);
1291}
1292
1293/// Return true if we might ever do TCO for calls with this calling convention.
1294static bool mayTailCallThisCC(CallingConv::ID CC) {
1295 switch (CC) {
1296 // C calling conventions:
1297 case CallingConv::C:
1298 case CallingConv::Win64:
1299 case CallingConv::X86_64_SysV:
1300 case CallingConv::PreserveNone:
1301 // Callee pop conventions:
1302 case CallingConv::X86_ThisCall:
1303 case CallingConv::X86_StdCall:
1304 case CallingConv::X86_VectorCall:
1305 case CallingConv::X86_FastCall:
1306 // Swift:
1307 case CallingConv::Swift:
1308 return true;
1309 default:
1310 return canGuaranteeTCO(CC);
1311 }
1312}
1313
1314/// Return true if the function is being made into a tailcall target by
1315/// changing its ABI.
1316static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
1317 return (GuaranteedTailCallOpt && canGuaranteeTCO(CC)) ||
1318 CC == CallingConv::Tail || CC == CallingConv::SwiftTail;
1319}
1320
1321bool X86TargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
1322 if (!CI->isTailCall())
1323 return false;
1324
1325 CallingConv::ID CalleeCC = CI->getCallingConv();
1326 if (!mayTailCallThisCC(CC: CalleeCC))
1327 return false;
1328
1329 return true;
1330}
1331
1332SDValue
1333X86TargetLowering::LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
1334 const SmallVectorImpl<ISD::InputArg> &Ins,
1335 const SDLoc &dl, SelectionDAG &DAG,
1336 const CCValAssign &VA,
1337 MachineFrameInfo &MFI, unsigned i) const {
1338 // Create the nodes corresponding to a load from this parameter slot.
1339 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1340 bool AlwaysUseMutable = shouldGuaranteeTCO(
1341 CC: CallConv, GuaranteedTailCallOpt: DAG.getTarget().Options.GuaranteedTailCallOpt);
1342 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1343 EVT ValVT;
1344 MVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
1345
1346 // If value is passed by pointer we have address passed instead of the value
1347 // itself. No need to extend if the mask value and location share the same
1348 // absolute size.
1349 bool ExtendedInMem =
1350 VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1 &&
1351 VA.getValVT().getSizeInBits() != VA.getLocVT().getSizeInBits();
1352
1353 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
1354 ValVT = VA.getLocVT();
1355 else
1356 ValVT = VA.getValVT();
1357
1358 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1359 // changed with more analysis.
1360 // In case of tail call optimization mark all arguments mutable. Since they
1361 // could be overwritten by lowering of arguments in case of a tail call.
1362 if (Flags.isByVal()) {
1363 unsigned Bytes = Flags.getByValSize();
1364 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1365
1366 // FIXME: For now, all byval parameter objects are marked as aliasing. This
1367 // can be improved with deeper analysis.
1368 int FI = MFI.CreateFixedObject(Size: Bytes, SPOffset: VA.getLocMemOffset(), IsImmutable: isImmutable,
1369 /*isAliased=*/true);
1370 return DAG.getFrameIndex(FI, VT: PtrVT);
1371 }
1372
1373 EVT ArgVT = Ins[i].ArgVT;
1374
1375 // If this is a vector that has been split into multiple parts, don't elide
1376 // the copy. The layout on the stack may not match the packed in-memory
1377 // layout.
1378 bool ScalarizedVector = ArgVT.isVector() && !VA.getLocVT().isVector();
1379
1380 // This is an argument in memory. We might be able to perform copy elision.
1381 // If the argument is passed directly in memory without any extension, then we
1382 // can perform copy elision. Large vector types, for example, may be passed
1383 // indirectly by pointer.
1384 if (Flags.isCopyElisionCandidate() &&
1385 VA.getLocInfo() != CCValAssign::Indirect && !ExtendedInMem &&
1386 !ScalarizedVector) {
1387 SDValue PartAddr;
1388 if (Ins[i].PartOffset == 0) {
1389 // If this is a one-part value or the first part of a multi-part value,
1390 // create a stack object for the entire argument value type and return a
1391 // load from our portion of it. This assumes that if the first part of an
1392 // argument is in memory, the rest will also be in memory.
1393 int FI = MFI.CreateFixedObject(Size: ArgVT.getStoreSize(), SPOffset: VA.getLocMemOffset(),
1394 /*IsImmutable=*/false);
1395 PartAddr = DAG.getFrameIndex(FI, VT: PtrVT);
1396 return DAG.getLoad(
1397 VT: ValVT, dl, Chain, Ptr: PartAddr,
1398 PtrInfo: MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI));
1399 }
1400
1401 // This is not the first piece of an argument in memory. See if there is
1402 // already a fixed stack object including this offset. If so, assume it
1403 // was created by the PartOffset == 0 branch above and create a load from
1404 // the appropriate offset into it.
1405 int64_t PartBegin = VA.getLocMemOffset();
1406 int64_t PartEnd = PartBegin + ValVT.getSizeInBits() / 8;
1407 int FI = MFI.getObjectIndexBegin();
1408 for (; MFI.isFixedObjectIndex(ObjectIdx: FI); ++FI) {
1409 int64_t ObjBegin = MFI.getObjectOffset(ObjectIdx: FI);
1410 int64_t ObjEnd = ObjBegin + MFI.getObjectSize(ObjectIdx: FI);
1411 if (ObjBegin <= PartBegin && PartEnd <= ObjEnd)
1412 break;
1413 }
1414 if (MFI.isFixedObjectIndex(ObjectIdx: FI)) {
1415 SDValue Addr =
1416 DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: PtrVT, N1: DAG.getFrameIndex(FI, VT: PtrVT),
1417 N2: DAG.getIntPtrConstant(Val: Ins[i].PartOffset, DL: dl));
1418 return DAG.getLoad(VT: ValVT, dl, Chain, Ptr: Addr,
1419 PtrInfo: MachinePointerInfo::getFixedStack(
1420 MF&: DAG.getMachineFunction(), FI, Offset: Ins[i].PartOffset));
1421 }
1422 }
1423
1424 int FI = MFI.CreateFixedObject(Size: ValVT.getSizeInBits() / 8,
1425 SPOffset: VA.getLocMemOffset(), IsImmutable: isImmutable);
1426
1427 // Set SExt or ZExt flag.
1428 if (VA.getLocInfo() == CCValAssign::ZExt) {
1429 MFI.setObjectZExt(ObjectIdx: FI, IsZExt: true);
1430 } else if (VA.getLocInfo() == CCValAssign::SExt) {
1431 MFI.setObjectSExt(ObjectIdx: FI, IsSExt: true);
1432 }
1433
1434 MaybeAlign Alignment;
1435 if (Subtarget.isTargetWindowsMSVC() && !Subtarget.is64Bit() &&
1436 ValVT != MVT::f80)
1437 Alignment = MaybeAlign(4);
1438 SDValue FIN = DAG.getFrameIndex(FI, VT: PtrVT);
1439 SDValue Val = DAG.getLoad(
1440 VT: ValVT, dl, Chain, Ptr: FIN,
1441 PtrInfo: MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI),
1442 Alignment);
1443 return ExtendedInMem
1444 ? (VA.getValVT().isVector()
1445 ? DAG.getNode(Opcode: ISD::SCALAR_TO_VECTOR, DL: dl, VT: VA.getValVT(), Operand: Val)
1446 : DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: VA.getValVT(), Operand: Val))
1447 : Val;
1448}
1449
1450// FIXME: Get this from tablegen.
1451static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
1452 const X86Subtarget &Subtarget) {
1453 assert(Subtarget.is64Bit());
1454
1455 if (Subtarget.isCallingConvWin64(CC: CallConv)) {
1456 static const MCPhysReg GPR64ArgRegsWin64[] = {
1457 X86::RCX, X86::RDX, X86::R8, X86::R9
1458 };
1459 return GPR64ArgRegsWin64;
1460 }
1461
1462 static const MCPhysReg GPR64ArgRegs64Bit[] = {
1463 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1464 };
1465 return GPR64ArgRegs64Bit;
1466}
1467
1468// FIXME: Get this from tablegen.
1469static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
1470 CallingConv::ID CallConv,
1471 const X86Subtarget &Subtarget) {
1472 assert(Subtarget.is64Bit());
1473 if (Subtarget.isCallingConvWin64(CC: CallConv)) {
1474 // The XMM registers which might contain var arg parameters are shadowed
1475 // in their paired GPR. So we only need to save the GPR to their home
1476 // slots.
1477 // TODO: __vectorcall will change this.
1478 return {};
1479 }
1480
1481 bool isSoftFloat = Subtarget.useSoftFloat();
1482 if (isSoftFloat || !Subtarget.hasSSE1())
1483 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
1484 // registers.
1485 return {};
1486
1487 static const MCPhysReg XMMArgRegs64Bit[] = {
1488 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1489 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1490 };
1491 return XMMArgRegs64Bit;
1492}
1493
1494#ifndef NDEBUG
1495static bool isSortedByValueNo(ArrayRef<CCValAssign> ArgLocs) {
1496 return llvm::is_sorted(
1497 ArgLocs, [](const CCValAssign &A, const CCValAssign &B) -> bool {
1498 return A.getValNo() < B.getValNo();
1499 });
1500}
1501#endif
1502
1503namespace {
1504/// This is a helper class for lowering variable arguments parameters.
1505class VarArgsLoweringHelper {
1506public:
1507 VarArgsLoweringHelper(X86MachineFunctionInfo *FuncInfo, const SDLoc &Loc,
1508 SelectionDAG &DAG, const X86Subtarget &Subtarget,
1509 CallingConv::ID CallConv, CCState &CCInfo)
1510 : FuncInfo(FuncInfo), DL(Loc), DAG(DAG), Subtarget(Subtarget),
1511 TheMachineFunction(DAG.getMachineFunction()),
1512 TheFunction(TheMachineFunction.getFunction()),
1513 FrameInfo(TheMachineFunction.getFrameInfo()),
1514 FrameLowering(*Subtarget.getFrameLowering()),
1515 TargLowering(DAG.getTargetLoweringInfo()), CallConv(CallConv),
1516 CCInfo(CCInfo) {}
1517
1518 // Lower variable arguments parameters.
1519 void lowerVarArgsParameters(SDValue &Chain, unsigned StackSize);
1520
1521private:
1522 void createVarArgAreaAndStoreRegisters(SDValue &Chain, unsigned StackSize);
1523
1524 void forwardMustTailParameters(SDValue &Chain);
1525
1526 bool is64Bit() const { return Subtarget.is64Bit(); }
1527 bool isWin64() const { return Subtarget.isCallingConvWin64(CC: CallConv); }
1528
1529 X86MachineFunctionInfo *FuncInfo;
1530 const SDLoc &DL;
1531 SelectionDAG &DAG;
1532 const X86Subtarget &Subtarget;
1533 MachineFunction &TheMachineFunction;
1534 const Function &TheFunction;
1535 MachineFrameInfo &FrameInfo;
1536 const TargetFrameLowering &FrameLowering;
1537 const TargetLowering &TargLowering;
1538 CallingConv::ID CallConv;
1539 CCState &CCInfo;
1540};
1541} // namespace
1542
1543void VarArgsLoweringHelper::createVarArgAreaAndStoreRegisters(
1544 SDValue &Chain, unsigned StackSize) {
1545 // If the function takes variable number of arguments, make a frame index for
1546 // the start of the first vararg value... for expansion of llvm.va_start. We
1547 // can skip this if there are no va_start calls.
1548 if (is64Bit() || (CallConv != CallingConv::X86_FastCall &&
1549 CallConv != CallingConv::X86_ThisCall)) {
1550 FuncInfo->setVarArgsFrameIndex(
1551 FrameInfo.CreateFixedObject(Size: 1, SPOffset: StackSize, IsImmutable: true));
1552 }
1553
1554 // 64-bit calling conventions support varargs and register parameters, so we
1555 // have to do extra work to spill them in the prologue.
1556 if (is64Bit()) {
1557 // Find the first unallocated argument registers.
1558 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
1559 ArrayRef<MCPhysReg> ArgXMMs =
1560 get64BitArgumentXMMs(MF&: TheMachineFunction, CallConv, Subtarget);
1561 unsigned NumIntRegs = CCInfo.getFirstUnallocated(Regs: ArgGPRs);
1562 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(Regs: ArgXMMs);
1563
1564 assert(!(NumXMMRegs && !Subtarget.hasSSE1()) &&
1565 "SSE register cannot be used when SSE is disabled!");
1566
1567 if (isWin64()) {
1568 // Get to the caller-allocated home save location. Add 8 to account
1569 // for the return address.
1570 int HomeOffset = FrameLowering.getOffsetOfLocalArea() + 8;
1571 FuncInfo->setRegSaveFrameIndex(
1572 FrameInfo.CreateFixedObject(Size: 1, SPOffset: NumIntRegs * 8 + HomeOffset, IsImmutable: false));
1573 // Fixup to set vararg frame on shadow area (4 x i64).
1574 if (NumIntRegs < 4)
1575 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1576 } else {
1577 // For X86-64, if there are vararg parameters that are passed via
1578 // registers, then we must store them to their spots on the stack so
1579 // they may be loaded by dereferencing the result of va_next.
1580 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1581 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
1582 FuncInfo->setRegSaveFrameIndex(FrameInfo.CreateStackObject(
1583 Size: ArgGPRs.size() * 8 + ArgXMMs.size() * 16, Alignment: Align(16), isSpillSlot: false));
1584 }
1585
1586 SmallVector<SDValue, 6>
1587 LiveGPRs; // list of SDValue for GPR registers keeping live input value
1588 SmallVector<SDValue, 8> LiveXMMRegs; // list of SDValue for XMM registers
1589 // keeping live input value
1590 SDValue ALVal; // if applicable keeps SDValue for %al register
1591
1592 // Gather all the live in physical registers.
1593 for (MCPhysReg Reg : ArgGPRs.slice(N: NumIntRegs)) {
1594 Register GPR = TheMachineFunction.addLiveIn(PReg: Reg, RC: &X86::GR64RegClass);
1595 LiveGPRs.push_back(Elt: DAG.getCopyFromReg(Chain, dl: DL, Reg: GPR, VT: MVT::i64));
1596 }
1597 const auto &AvailableXmms = ArgXMMs.slice(N: NumXMMRegs);
1598 if (!AvailableXmms.empty()) {
1599 Register AL = TheMachineFunction.addLiveIn(PReg: X86::AL, RC: &X86::GR8RegClass);
1600 ALVal = DAG.getCopyFromReg(Chain, dl: DL, Reg: AL, VT: MVT::i8);
1601 for (MCPhysReg Reg : AvailableXmms) {
1602 // FastRegisterAllocator spills virtual registers at basic
1603 // block boundary. That leads to usages of xmm registers
1604 // outside of check for %al. Pass physical registers to
1605 // VASTART_SAVE_XMM_REGS to avoid unneccessary spilling.
1606 TheMachineFunction.getRegInfo().addLiveIn(Reg);
1607 LiveXMMRegs.push_back(Elt: DAG.getRegister(Reg, VT: MVT::v4f32));
1608 }
1609 }
1610
1611 // Store the integer parameter registers.
1612 SmallVector<SDValue, 8> MemOps;
1613 SDValue RSFIN =
1614 DAG.getFrameIndex(FI: FuncInfo->getRegSaveFrameIndex(),
1615 VT: TargLowering.getPointerTy(DL: DAG.getDataLayout()));
1616 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1617 for (SDValue Val : LiveGPRs) {
1618 SDValue FIN = DAG.getNode(Opcode: ISD::ADD, DL,
1619 VT: TargLowering.getPointerTy(DL: DAG.getDataLayout()),
1620 N1: RSFIN, N2: DAG.getIntPtrConstant(Val: Offset, DL));
1621 SDValue Store =
1622 DAG.getStore(Chain: Val.getValue(R: 1), dl: DL, Val, Ptr: FIN,
1623 PtrInfo: MachinePointerInfo::getFixedStack(
1624 MF&: DAG.getMachineFunction(),
1625 FI: FuncInfo->getRegSaveFrameIndex(), Offset));
1626 MemOps.push_back(Elt: Store);
1627 Offset += 8;
1628 }
1629
1630 // Now store the XMM (fp + vector) parameter registers.
1631 if (!LiveXMMRegs.empty()) {
1632 SmallVector<SDValue, 12> SaveXMMOps;
1633 SaveXMMOps.push_back(Elt: Chain);
1634 SaveXMMOps.push_back(Elt: ALVal);
1635 SaveXMMOps.push_back(Elt: RSFIN);
1636 SaveXMMOps.push_back(
1637 Elt: DAG.getTargetConstant(Val: FuncInfo->getVarArgsFPOffset(), DL, VT: MVT::i32));
1638 llvm::append_range(C&: SaveXMMOps, R&: LiveXMMRegs);
1639 MachineMemOperand *StoreMMO =
1640 DAG.getMachineFunction().getMachineMemOperand(
1641 PtrInfo: MachinePointerInfo::getFixedStack(
1642 MF&: DAG.getMachineFunction(), FI: FuncInfo->getRegSaveFrameIndex(),
1643 Offset),
1644 F: MachineMemOperand::MOStore, Size: 128, BaseAlignment: Align(16));
1645 MemOps.push_back(Elt: DAG.getMemIntrinsicNode(Opcode: X86ISD::VASTART_SAVE_XMM_REGS,
1646 dl: DL, VTList: DAG.getVTList(VT: MVT::Other),
1647 Ops: SaveXMMOps, MemVT: MVT::i8, MMO: StoreMMO));
1648 }
1649
1650 if (!MemOps.empty())
1651 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, Ops: MemOps);
1652 }
1653}
1654
1655void VarArgsLoweringHelper::forwardMustTailParameters(SDValue &Chain) {
1656 // Find the largest legal vector type.
1657 MVT VecVT = MVT::Other;
1658 // FIXME: Only some x86_32 calling conventions support AVX512.
1659 if (Subtarget.useAVX512Regs() &&
1660 (is64Bit() || (CallConv == CallingConv::X86_VectorCall ||
1661 CallConv == CallingConv::Intel_OCL_BI)))
1662 VecVT = MVT::v16f32;
1663 else if (Subtarget.hasAVX())
1664 VecVT = MVT::v8f32;
1665 else if (Subtarget.hasSSE2())
1666 VecVT = MVT::v4f32;
1667
1668 // We forward some GPRs and some vector types.
1669 SmallVector<MVT, 2> RegParmTypes;
1670 MVT IntVT = is64Bit() ? MVT::i64 : MVT::i32;
1671 RegParmTypes.push_back(Elt: IntVT);
1672 if (VecVT != MVT::Other)
1673 RegParmTypes.push_back(Elt: VecVT);
1674
1675 // Compute the set of forwarded registers. The rest are scratch.
1676 SmallVectorImpl<ForwardedRegister> &Forwards =
1677 FuncInfo->getForwardedMustTailRegParms();
1678 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, Fn: CC_X86);
1679
1680 // Forward AL for SysV x86_64 targets, since it is used for varargs.
1681 if (is64Bit() && !isWin64() && !CCInfo.isAllocated(Reg: X86::AL)) {
1682 Register ALVReg = TheMachineFunction.addLiveIn(PReg: X86::AL, RC: &X86::GR8RegClass);
1683 Forwards.push_back(Elt: ForwardedRegister(ALVReg, X86::AL, MVT::i8));
1684 }
1685
1686 // Copy all forwards from physical to virtual registers.
1687 for (ForwardedRegister &FR : Forwards) {
1688 // FIXME: Can we use a less constrained schedule?
1689 SDValue RegVal = DAG.getCopyFromReg(Chain, dl: DL, Reg: FR.VReg, VT: FR.VT);
1690 FR.VReg = TheMachineFunction.getRegInfo().createVirtualRegister(
1691 RegClass: TargLowering.getRegClassFor(VT: FR.VT));
1692 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: FR.VReg, N: RegVal);
1693 }
1694}
1695
1696void VarArgsLoweringHelper::lowerVarArgsParameters(SDValue &Chain,
1697 unsigned StackSize) {
1698 // Set FrameIndex to the 0xAAAAAAA value to mark unset state.
1699 // If necessary, it would be set into the correct value later.
1700 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1701 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1702
1703 if (FrameInfo.hasVAStart())
1704 createVarArgAreaAndStoreRegisters(Chain, StackSize);
1705
1706 if (FrameInfo.hasMustTailInVarArgFunc())
1707 forwardMustTailParameters(Chain);
1708}
1709
1710SDValue X86TargetLowering::LowerFormalArguments(
1711 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
1712 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1713 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1714 MachineFunction &MF = DAG.getMachineFunction();
1715 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1716
1717 const Function &F = MF.getFunction();
1718 if (F.hasExternalLinkage() && Subtarget.isTargetCygMing() &&
1719 F.getName() == "main")
1720 FuncInfo->setForceFramePointer(true);
1721
1722 MachineFrameInfo &MFI = MF.getFrameInfo();
1723 bool Is64Bit = Subtarget.is64Bit();
1724 bool IsWin64 = Subtarget.isCallingConvWin64(CC: CallConv);
1725
1726 // On x86_64 with x87 disabled, x86_fp80 cannot be handled: the type would
1727 // need to be returned/passed in x87 registers (FP0/FP1) which are
1728 // unavailable. Emit a clear diagnostic instead of crashing later with
1729 // "Cannot select: build_pair".
1730 if (Is64Bit && !Subtarget.hasX87()) {
1731 if (F.getReturnType()->isX86_FP80Ty() ||
1732 any_of(Range: F.args(), P: [](const Argument &Arg) {
1733 return Arg.getType()->isX86_FP80Ty();
1734 }))
1735 reportFatalUsageError(
1736 reason: "cannot use x86_fp80 type with x87 disabled on x86_64 target");
1737 }
1738
1739 assert(
1740 !(IsVarArg && canGuaranteeTCO(CallConv)) &&
1741 "Var args not supported with calling conv' regcall, fastcc, ghc or hipe");
1742
1743 // Assign locations to all of the incoming arguments.
1744 SmallVector<CCValAssign, 16> ArgLocs;
1745 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
1746
1747 // Allocate shadow area for Win64.
1748 if (IsWin64)
1749 CCInfo.AllocateStack(Size: 32, Alignment: Align(8));
1750
1751 CCInfo.AnalyzeArguments(Ins, Fn: CC_X86);
1752
1753 // In vectorcall calling convention a second pass is required for the HVA
1754 // types.
1755 if (CallingConv::X86_VectorCall == CallConv) {
1756 CCInfo.AnalyzeArgumentsSecondPass(Args: Ins, Fn: CC_X86);
1757 }
1758
1759 // The next loop assumes that the locations are in the same order of the
1760 // input arguments.
1761 assert(isSortedByValueNo(ArgLocs) &&
1762 "Argument Location list must be sorted before lowering");
1763
1764 SDValue ArgValue;
1765 for (unsigned I = 0, InsIndex = 0, E = ArgLocs.size(); I != E;
1766 ++I, ++InsIndex) {
1767 assert(InsIndex < Ins.size() && "Invalid Ins index");
1768 CCValAssign &VA = ArgLocs[I];
1769
1770 if (VA.isRegLoc()) {
1771 EVT RegVT = VA.getLocVT();
1772 if (VA.needsCustom()) {
1773 assert(
1774 VA.getValVT() == MVT::v64i1 &&
1775 "Currently the only custom case is when we split v64i1 to 2 regs");
1776
1777 // v64i1 values, in regcall calling convention, that are
1778 // compiled to 32 bit arch, are split up into two registers.
1779 ArgValue =
1780 getv64i1Argument(VA, NextVA&: ArgLocs[++I], Root&: Chain, DAG, DL: dl, Subtarget);
1781 } else {
1782 const TargetRegisterClass *RC;
1783 if (RegVT == MVT::i8)
1784 RC = &X86::GR8RegClass;
1785 else if (RegVT == MVT::i16)
1786 RC = &X86::GR16RegClass;
1787 else if (RegVT == MVT::i32)
1788 RC = &X86::GR32RegClass;
1789 else if (Is64Bit && RegVT == MVT::i64)
1790 RC = &X86::GR64RegClass;
1791 else if (RegVT == MVT::f16)
1792 RC = Subtarget.hasAVX512() ? &X86::FR16XRegClass : &X86::FR16RegClass;
1793 else if (RegVT == MVT::f32)
1794 RC = Subtarget.hasAVX512() ? &X86::FR32XRegClass : &X86::FR32RegClass;
1795 else if (RegVT == MVT::f64)
1796 RC = Subtarget.hasAVX512() ? &X86::FR64XRegClass : &X86::FR64RegClass;
1797 else if (RegVT == MVT::f80)
1798 RC = &X86::RFP80RegClass;
1799 else if (RegVT == MVT::f128)
1800 RC = &X86::VR128RegClass;
1801 else if (RegVT.is512BitVector())
1802 RC = &X86::VR512RegClass;
1803 else if (RegVT.is256BitVector())
1804 RC = Subtarget.hasVLX() ? &X86::VR256XRegClass : &X86::VR256RegClass;
1805 else if (RegVT.is128BitVector())
1806 RC = Subtarget.hasVLX() ? &X86::VR128XRegClass : &X86::VR128RegClass;
1807 else if (RegVT == MVT::x86mmx)
1808 RC = &X86::VR64RegClass;
1809 else if (RegVT == MVT::v1i1)
1810 RC = &X86::VK1RegClass;
1811 else if (RegVT == MVT::v8i1)
1812 RC = &X86::VK8RegClass;
1813 else if (RegVT == MVT::v16i1)
1814 RC = &X86::VK16RegClass;
1815 else if (RegVT == MVT::v32i1)
1816 RC = &X86::VK32RegClass;
1817 else if (RegVT == MVT::v64i1)
1818 RC = &X86::VK64RegClass;
1819 else
1820 llvm_unreachable("Unknown argument type!");
1821
1822 Register Reg = MF.addLiveIn(PReg: VA.getLocReg(), RC);
1823 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, VT: RegVT);
1824 }
1825
1826 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1827 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1828 // right size.
1829 if (VA.getLocInfo() == CCValAssign::SExt)
1830 ArgValue = DAG.getNode(Opcode: ISD::AssertSext, DL: dl, VT: RegVT, N1: ArgValue,
1831 N2: DAG.getValueType(VA.getValVT()));
1832 else if (VA.getLocInfo() == CCValAssign::ZExt)
1833 ArgValue = DAG.getNode(Opcode: ISD::AssertZext, DL: dl, VT: RegVT, N1: ArgValue,
1834 N2: DAG.getValueType(VA.getValVT()));
1835 else if (VA.getLocInfo() == CCValAssign::BCvt)
1836 ArgValue = DAG.getBitcast(VT: VA.getValVT(), V: ArgValue);
1837
1838 if (VA.isExtInLoc()) {
1839 // Handle MMX values passed in XMM regs.
1840 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
1841 ArgValue = DAG.getNode(Opcode: X86ISD::MOVDQ2Q, DL: dl, VT: VA.getValVT(), Operand: ArgValue);
1842 else if (VA.getValVT().isVector() &&
1843 VA.getValVT().getScalarType() == MVT::i1 &&
1844 ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) ||
1845 (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) {
1846 // Promoting a mask type (v*i1) into a register of type i64/i32/i16/i8
1847 ArgValue = lowerRegToMasks(ValArg: ArgValue, ValVT: VA.getValVT(), ValLoc: RegVT, DL: dl, DAG);
1848 } else
1849 ArgValue = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: VA.getValVT(), Operand: ArgValue);
1850 }
1851 } else {
1852 assert(VA.isMemLoc());
1853 ArgValue =
1854 LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i: InsIndex);
1855 }
1856
1857 // If value is passed via pointer - do a load.
1858 if (VA.getLocInfo() == CCValAssign::Indirect &&
1859 !(Ins[I].Flags.isByVal() && VA.isRegLoc())) {
1860 ArgValue =
1861 DAG.getLoad(VT: VA.getValVT(), dl, Chain, Ptr: ArgValue, PtrInfo: MachinePointerInfo());
1862 }
1863
1864 InVals.push_back(Elt: ArgValue);
1865 }
1866
1867 for (unsigned I = 0, E = Ins.size(); I != E; ++I) {
1868 if (Ins[I].Flags.isSwiftAsync()) {
1869 auto X86FI = MF.getInfo<X86MachineFunctionInfo>();
1870 if (X86::isExtendedSwiftAsyncFrameSupported(Subtarget, MF))
1871 X86FI->setHasSwiftAsyncContext(true);
1872 else {
1873 int PtrSize = Subtarget.is64Bit() ? 8 : 4;
1874 int FI =
1875 MF.getFrameInfo().CreateStackObject(Size: PtrSize, Alignment: Align(PtrSize), isSpillSlot: false);
1876 X86FI->setSwiftAsyncContextFrameIdx(FI);
1877 SDValue St = DAG.getStore(
1878 Chain: DAG.getEntryNode(), dl, Val: InVals[I],
1879 Ptr: DAG.getFrameIndex(FI, VT: PtrSize == 8 ? MVT::i64 : MVT::i32),
1880 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI));
1881 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: St, N2: Chain);
1882 }
1883 }
1884
1885 // Swift calling convention does not require we copy the sret argument
1886 // into %rax/%eax for the return. We don't set SRetReturnReg for Swift.
1887 if (CallConv == CallingConv::Swift || CallConv == CallingConv::SwiftTail)
1888 continue;
1889
1890 // All x86 ABIs require that for returning structs by value we copy the
1891 // sret argument into %rax/%eax (depending on ABI) for the return. Save
1892 // the argument into a virtual register so that we can access it from the
1893 // return points.
1894 if (Ins[I].Flags.isSRet()) {
1895 assert(!FuncInfo->getSRetReturnReg() &&
1896 "SRet return has already been set");
1897 MVT PtrTy = getPointerTy(DL: DAG.getDataLayout());
1898 Register Reg =
1899 MF.getRegInfo().createVirtualRegister(RegClass: getRegClassFor(VT: PtrTy));
1900 FuncInfo->setSRetReturnReg(Reg);
1901 SDValue Copy = DAG.getCopyToReg(Chain: DAG.getEntryNode(), dl, Reg, N: InVals[I]);
1902 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Copy, N2: Chain);
1903 break;
1904 }
1905 }
1906
1907 unsigned StackSize = CCInfo.getStackSize();
1908 // Align stack specially for tail calls.
1909 if (shouldGuaranteeTCO(CC: CallConv,
1910 GuaranteedTailCallOpt: MF.getTarget().Options.GuaranteedTailCallOpt))
1911 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1912
1913 if (IsVarArg)
1914 VarArgsLoweringHelper(FuncInfo, dl, DAG, Subtarget, CallConv, CCInfo)
1915 .lowerVarArgsParameters(Chain, StackSize);
1916
1917 // Some CCs need callee pop.
1918 if (X86::isCalleePop(CallingConv: CallConv, is64Bit: Is64Bit, IsVarArg,
1919 GuaranteeTCO: MF.getTarget().Options.GuaranteedTailCallOpt)) {
1920 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1921 } else if (CallConv == CallingConv::X86_INTR && Ins.size() == 2) {
1922 // X86 interrupts must pop the error code (and the alignment padding) if
1923 // present.
1924 FuncInfo->setBytesToPopOnReturn(Is64Bit ? 16 : 4);
1925 } else {
1926 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1927 // If this is an sret function, the return should pop the hidden pointer.
1928 if (hasCalleePopSRet(Args: Ins, ArgLocs, Subtarget))
1929 FuncInfo->setBytesToPopOnReturn(4);
1930 }
1931
1932 if (!Is64Bit) {
1933 // RegSaveFrameIndex is X86-64 only.
1934 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1935 }
1936
1937 FuncInfo->setArgumentStackSize(StackSize);
1938
1939 if (WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo()) {
1940 EHPersonality Personality = classifyEHPersonality(Pers: F.getPersonalityFn());
1941 if (Personality == EHPersonality::CoreCLR) {
1942 assert(Is64Bit);
1943 // TODO: Add a mechanism to frame lowering that will allow us to indicate
1944 // that we'd prefer this slot be allocated towards the bottom of the frame
1945 // (i.e. near the stack pointer after allocating the frame). Every
1946 // funclet needs a copy of this slot in its (mostly empty) frame, and the
1947 // offset from the bottom of this and each funclet's frame must be the
1948 // same, so the size of funclets' (mostly empty) frames is dictated by
1949 // how far this slot is from the bottom (since they allocate just enough
1950 // space to accommodate holding this slot at the correct offset).
1951 int PSPSymFI = MFI.CreateStackObject(Size: 8, Alignment: Align(8), /*isSpillSlot=*/false);
1952 EHInfo->PSPSymFrameIdx = PSPSymFI;
1953 }
1954 }
1955
1956 if (shouldDisableArgRegFromCSR(CC: CallConv) ||
1957 F.hasFnAttribute(Kind: "no_caller_saved_registers")) {
1958 MachineRegisterInfo &MRI = MF.getRegInfo();
1959 for (std::pair<MCRegister, Register> Pair : MRI.liveins())
1960 MRI.disableCalleeSavedRegister(Reg: Pair.first);
1961 }
1962
1963 if (CallingConv::PreserveNone == CallConv)
1964 for (const ISD::InputArg &In : Ins) {
1965 if (In.Flags.isSwiftSelf() || In.Flags.isSwiftAsync() ||
1966 In.Flags.isSwiftError()) {
1967 errorUnsupported(DAG, dl,
1968 Msg: "Swift attributes can't be used with preserve_none");
1969 break;
1970 }
1971 }
1972
1973 return Chain;
1974}
1975
1976SDValue X86TargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
1977 SDValue Arg, const SDLoc &dl,
1978 SelectionDAG &DAG,
1979 const CCValAssign &VA,
1980 ISD::ArgFlagsTy Flags,
1981 bool isByVal) const {
1982 unsigned LocMemOffset = VA.getLocMemOffset();
1983 SDValue PtrOff = DAG.getIntPtrConstant(Val: LocMemOffset, DL: dl);
1984 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: getPointerTy(DL: DAG.getDataLayout()),
1985 N1: StackPtr, N2: PtrOff);
1986 if (isByVal)
1987 return CreateCopyOfByValArgument(Src: Arg, Dst: PtrOff, Chain, Flags, DAG, dl);
1988
1989 MaybeAlign Alignment;
1990 if (Subtarget.isTargetWindowsMSVC() && !Subtarget.is64Bit() &&
1991 Arg.getSimpleValueType() != MVT::f80)
1992 Alignment = MaybeAlign(4);
1993 return DAG.getStore(
1994 Chain, dl, Val: Arg, Ptr: PtrOff,
1995 PtrInfo: MachinePointerInfo::getStack(MF&: DAG.getMachineFunction(), Offset: LocMemOffset),
1996 Alignment);
1997}
1998
1999/// Emit a load of return address if tail call
2000/// optimization is performed and it is required.
2001SDValue X86TargetLowering::EmitTailCallLoadRetAddr(
2002 SelectionDAG &DAG, SDValue &OutRetAddr, SDValue Chain, bool IsTailCall,
2003 bool Is64Bit, int FPDiff, const SDLoc &dl) const {
2004 // Adjust the Return address stack slot.
2005 EVT VT = getPointerTy(DL: DAG.getDataLayout());
2006 OutRetAddr = getReturnAddressFrameIndex(DAG);
2007
2008 // Load the "old" Return address.
2009 OutRetAddr = DAG.getLoad(VT, dl, Chain, Ptr: OutRetAddr, PtrInfo: MachinePointerInfo());
2010 return SDValue(OutRetAddr.getNode(), 1);
2011}
2012
2013/// Emit a store of the return address if tail call
2014/// optimization is performed and it is required (FPDiff!=0).
2015static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2016 SDValue Chain, SDValue RetAddrFrIdx,
2017 EVT PtrVT, unsigned SlotSize,
2018 int FPDiff, const SDLoc &dl) {
2019 // Store the return address to the appropriate stack slot.
2020 if (!FPDiff) return Chain;
2021 // Calculate the new stack slot for the return address.
2022 int NewReturnAddrFI =
2023 MF.getFrameInfo().CreateFixedObject(Size: SlotSize, SPOffset: (int64_t)FPDiff - SlotSize,
2024 IsImmutable: false);
2025 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(FI: NewReturnAddrFI, VT: PtrVT);
2026 Chain = DAG.getStore(Chain, dl, Val: RetAddrFrIdx, Ptr: NewRetAddrFrIdx,
2027 PtrInfo: MachinePointerInfo::getFixedStack(
2028 MF&: DAG.getMachineFunction(), FI: NewReturnAddrFI));
2029 return Chain;
2030}
2031
2032/// Returns a vector_shuffle mask for an movs{s|d}, movd
2033/// operation of specified width.
2034SDValue X86TargetLowering::getMOVL(SelectionDAG &DAG, const SDLoc &dl, MVT VT,
2035 SDValue V1, SDValue V2) const {
2036 unsigned NumElems = VT.getVectorNumElements();
2037 SmallVector<int, 8> Mask;
2038 Mask.push_back(Elt: NumElems);
2039 for (unsigned i = 1; i != NumElems; ++i)
2040 Mask.push_back(Elt: i);
2041 return DAG.getVectorShuffle(VT, dl, N1: V1, N2: V2, Mask);
2042}
2043
2044// Returns the type of copying which is required to set up a byval argument to
2045// a tail-called function. This isn't needed for non-tail calls, because they
2046// always need the equivalent of CopyOnce, but tail-calls sometimes need two to
2047// avoid clobbering another argument (CopyViaTemp), and sometimes can be
2048// optimised to zero copies when forwarding an argument from the caller's
2049// caller (NoCopy).
2050X86TargetLowering::ByValCopyKind X86TargetLowering::ByValNeedsCopyForTailCall(
2051 SelectionDAG &DAG, SDValue Src, SDValue Dst, ISD::ArgFlagsTy Flags) const {
2052 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2053
2054 // Globals are always safe to copy from.
2055 if (isa<GlobalAddressSDNode>(Val: Src) || isa<ExternalSymbolSDNode>(Val: Src))
2056 return CopyOnce;
2057
2058 // Can only analyse frame index nodes, conservatively assume we need a
2059 // temporary.
2060 auto *SrcFrameIdxNode = dyn_cast<FrameIndexSDNode>(Val&: Src);
2061 auto *DstFrameIdxNode = dyn_cast<FrameIndexSDNode>(Val&: Dst);
2062 if (!SrcFrameIdxNode || !DstFrameIdxNode)
2063 return CopyViaTemp;
2064
2065 int SrcFI = SrcFrameIdxNode->getIndex();
2066 int DstFI = DstFrameIdxNode->getIndex();
2067 assert(MFI.isFixedObjectIndex(DstFI) &&
2068 "byval passed in non-fixed stack slot");
2069
2070 int64_t SrcOffset = MFI.getObjectOffset(ObjectIdx: SrcFI);
2071 int64_t DstOffset = MFI.getObjectOffset(ObjectIdx: DstFI);
2072
2073 // If the source is in the local frame, then the copy to the argument
2074 // memory is always valid.
2075 bool FixedSrc = MFI.isFixedObjectIndex(ObjectIdx: SrcFI);
2076 if (!FixedSrc || (FixedSrc && SrcOffset < 0))
2077 return CopyOnce;
2078
2079 // If the value is already in the correct location, then no copying is
2080 // needed. If not, then we need to copy via a temporary.
2081 if (SrcOffset == DstOffset)
2082 return NoCopy;
2083 else
2084 return CopyViaTemp;
2085}
2086
2087SDValue
2088X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2089 SmallVectorImpl<SDValue> &InVals) const {
2090 SelectionDAG &DAG = CLI.DAG;
2091 SDLoc &dl = CLI.DL;
2092 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2093 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2094 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2095 SDValue Chain = CLI.Chain;
2096 SDValue Callee = CLI.Callee;
2097 CallingConv::ID CallConv = CLI.CallConv;
2098 bool &isTailCall = CLI.IsTailCall;
2099 bool isVarArg = CLI.IsVarArg;
2100 const auto *CB = CLI.CB;
2101
2102 MachineFunction &MF = DAG.getMachineFunction();
2103 bool Is64Bit = Subtarget.is64Bit();
2104 bool IsWin64 = Subtarget.isCallingConvWin64(CC: CallConv);
2105 bool ShouldGuaranteeTCO = shouldGuaranteeTCO(
2106 CC: CallConv, GuaranteedTailCallOpt: MF.getTarget().Options.GuaranteedTailCallOpt);
2107 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2108 bool HasNCSR = (CB && isa<CallInst>(Val: CB) &&
2109 CB->hasFnAttr(Kind: "no_caller_saved_registers"));
2110 bool IsIndirectCall = (CB && isa<CallInst>(Val: CB) && CB->isIndirectCall());
2111 bool IsCFICall = IsIndirectCall && CLI.CFIType;
2112 const Module *M = MF.getFunction().getParent();
2113
2114 // If the indirect call target has the nocf_check attribute, the call needs
2115 // the NOTRACK prefix. For simplicity just disable tail calls as there are
2116 // so many variants.
2117 // FIXME: This will cause backend errors if the user forces the issue.
2118 bool IsNoTrackIndirectCall = IsIndirectCall && CB->doesNoCfCheck() &&
2119 M->getModuleFlag(Key: "cf-protection-branch");
2120 if (IsNoTrackIndirectCall)
2121 isTailCall = false;
2122
2123 MachineFunction::CallSiteInfo CSInfo;
2124 if (CallConv == CallingConv::X86_INTR)
2125 report_fatal_error(reason: "X86 interrupts may not be called directly");
2126
2127 // Set type id for call site info.
2128 setTypeIdForCallsiteInfo(CB, MF, CSInfo);
2129
2130 if (IsIndirectCall && !IsWin64 &&
2131 M->getModuleFlag(Key: "import-call-optimization"))
2132 errorUnsupported(DAG, dl,
2133 Msg: "Indirect calls must have a normal calling convention if "
2134 "Import Call Optimization is enabled");
2135
2136 // Analyze operands of the call, assigning locations to each operand.
2137 SmallVector<CCValAssign, 16> ArgLocs;
2138 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2139
2140 // Allocate shadow area for Win64.
2141 if (IsWin64)
2142 CCInfo.AllocateStack(Size: 32, Alignment: Align(8));
2143
2144 CCInfo.AnalyzeArguments(Outs, Fn: CC_X86);
2145
2146 // In vectorcall calling convention a second pass is required for the HVA
2147 // types.
2148 if (CallingConv::X86_VectorCall == CallConv) {
2149 CCInfo.AnalyzeArgumentsSecondPass(Args: Outs, Fn: CC_X86);
2150 }
2151
2152 // We cannot guarantee TCO for mismatched calling conventions.
2153 if (isTailCall && ShouldGuaranteeTCO) {
2154 CallingConv::ID CallerCC = MF.getFunction().getCallingConv();
2155 isTailCall = (CallConv == CallerCC);
2156 }
2157
2158 // Check if this tail call is a "sibling" call, which is loosely defined to
2159 // be a tail call that doesn't require heroics like moving the return
2160 // address or swapping byval arguments. We treat some musttail calls as
2161 // sibling calls to avoid unnecessary argument copies.
2162 bool IsMustTail = CLI.CB && CLI.CB->isMustTailCall();
2163 bool IsSibcall = false;
2164 if (isTailCall) {
2165 IsSibcall = isEligibleForSiblingCallOpt(CLI, CCInfo, ArgLocs);
2166 isTailCall = IsSibcall || IsMustTail || ShouldGuaranteeTCO;
2167 }
2168
2169 if (isTailCall)
2170 ++NumTailCalls;
2171
2172 if (IsMustTail && !isTailCall)
2173 report_fatal_error(reason: "failed to perform tail call elimination on a call "
2174 "site marked musttail");
2175
2176 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
2177 "Var args not supported with calling convention fastcc, ghc or hipe");
2178
2179 // Get a count of how many bytes are to be pushed on the stack.
2180 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
2181 if (IsSibcall)
2182 // This is a sibcall. The memory operands are available in caller's
2183 // own caller's stack.
2184 NumBytes = 0;
2185 else if (ShouldGuaranteeTCO && canGuaranteeTCO(CC: CallConv))
2186 NumBytes = GetAlignedArgumentStackSize(StackSize: NumBytes, DAG);
2187
2188 // A sibcall is ABI-compatible and does not need to adjust the stack pointer.
2189 int FPDiff = 0;
2190 if (isTailCall && ShouldGuaranteeTCO && !IsSibcall) {
2191 // Lower arguments at fp - stackoffset + fpdiff.
2192 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2193
2194 FPDiff = NumBytesCallerPushed - NumBytes;
2195
2196 // Set the delta of movement of the returnaddr stackslot.
2197 // But only set if delta is greater than previous delta.
2198 if (FPDiff < X86Info->getTCReturnAddrDelta())
2199 X86Info->setTCReturnAddrDelta(FPDiff);
2200 }
2201
2202 unsigned NumBytesToPush = NumBytes;
2203 unsigned NumBytesToPop = NumBytes;
2204
2205 SDValue StackPtr;
2206 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
2207
2208 // If we are doing a tail-call, any byval arguments will be written to stack
2209 // space which was used for incoming arguments. If any the values being used
2210 // are incoming byval arguments to this function, then they might be
2211 // overwritten by the stores of the outgoing arguments. To avoid this, we
2212 // need to make a temporary copy of them in local stack space, then copy back
2213 // to the argument area.
2214 // FIXME: There's potential to improve the code by using virtual registers for
2215 // temporary storage, and letting the register allocator spill if needed.
2216 SmallVector<SDValue, 8> ByValTemporaries;
2217 SDValue ByValTempChain;
2218 if (isTailCall) {
2219 // Use null SDValue to mean "no temporary recorded for this arg index".
2220 ByValTemporaries.assign(NumElts: OutVals.size(), Elt: SDValue());
2221
2222 SmallVector<SDValue, 8> ByValCopyChains;
2223 for (const CCValAssign &VA : ArgLocs) {
2224 unsigned ArgIdx = VA.getValNo();
2225 SDValue Src = OutVals[ArgIdx];
2226 ISD::ArgFlagsTy Flags = Outs[ArgIdx].Flags;
2227
2228 if (!Flags.isByVal())
2229 continue;
2230
2231 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
2232
2233 if (!StackPtr.getNode())
2234 StackPtr =
2235 DAG.getCopyFromReg(Chain, dl, Reg: RegInfo->getStackRegister(), VT: PtrVT);
2236
2237 // Destination: where this byval should live in the callee’s frame
2238 // after the tail call.
2239 int64_t Offset = VA.getLocMemOffset() + FPDiff;
2240 uint64_t Size = VA.getLocVT().getFixedSizeInBits() / 8;
2241 int FI = MF.getFrameInfo().CreateFixedObject(Size, SPOffset: Offset,
2242 /*IsImmutable=*/true);
2243 SDValue Dst = DAG.getFrameIndex(FI, VT: PtrVT);
2244
2245 ByValCopyKind Copy = ByValNeedsCopyForTailCall(DAG, Src, Dst, Flags);
2246
2247 if (Copy == NoCopy) {
2248 // If the argument is already at the correct offset on the stack
2249 // (because we are forwarding a byval argument from our caller), we
2250 // don't need any copying.
2251 continue;
2252 } else if (Copy == CopyOnce) {
2253 // If the argument is in our local stack frame, no other argument
2254 // preparation can clobber it, so we can copy it to the final location
2255 // later.
2256 ByValTemporaries[ArgIdx] = Src;
2257 } else {
2258 assert(Copy == CopyViaTemp && "unexpected enum value");
2259 // If we might be copying this argument from the outgoing argument
2260 // stack area, we need to copy via a temporary in the local stack
2261 // frame.
2262 MachineFrameInfo &MFI = MF.getFrameInfo();
2263 int TempFrameIdx = MFI.CreateStackObject(Size: Flags.getByValSize(),
2264 Alignment: Flags.getNonZeroByValAlign(),
2265 /*isSS=*/isSpillSlot: false);
2266 SDValue Temp =
2267 DAG.getFrameIndex(FI: TempFrameIdx, VT: getPointerTy(DL: DAG.getDataLayout()));
2268
2269 SDValue CopyChain =
2270 CreateCopyOfByValArgument(Src, Dst: Temp, Chain, Flags, DAG, dl);
2271 ByValCopyChains.push_back(Elt: CopyChain);
2272 ByValTemporaries[ArgIdx] = Temp;
2273 }
2274 }
2275 if (!ByValCopyChains.empty())
2276 ByValTempChain =
2277 DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: ByValCopyChains);
2278 }
2279
2280 // If we have an inalloca argument, all stack space has already been allocated
2281 // for us and be right at the top of the stack. We don't support multiple
2282 // arguments passed in memory when using inalloca.
2283 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2284 NumBytesToPush = 0;
2285 if (!ArgLocs.back().isMemLoc())
2286 report_fatal_error(reason: "cannot use inalloca attribute on a register "
2287 "parameter");
2288 if (ArgLocs.back().getLocMemOffset() != 0)
2289 report_fatal_error(reason: "any parameter with the inalloca attribute must be "
2290 "the only memory argument");
2291 } else if (CLI.IsPreallocated) {
2292 assert(ArgLocs.back().isMemLoc() &&
2293 "cannot use preallocated attribute on a register "
2294 "parameter");
2295 SmallVector<size_t, 4> PreallocatedOffsets;
2296 for (size_t i = 0; i < CLI.OutVals.size(); ++i) {
2297 if (CLI.CB->paramHasAttr(ArgNo: i, Kind: Attribute::Preallocated)) {
2298 PreallocatedOffsets.push_back(Elt: ArgLocs[i].getLocMemOffset());
2299 }
2300 }
2301 auto *MFI = DAG.getMachineFunction().getInfo<X86MachineFunctionInfo>();
2302 size_t PreallocatedId = MFI->getPreallocatedIdForCallSite(CS: CLI.CB);
2303 MFI->setPreallocatedStackSize(Id: PreallocatedId, StackSize: NumBytes);
2304 MFI->setPreallocatedArgOffsets(Id: PreallocatedId, AO: PreallocatedOffsets);
2305 NumBytesToPush = 0;
2306 }
2307
2308 if (!IsSibcall && !IsMustTail)
2309 Chain = DAG.getCALLSEQ_START(Chain, InSize: NumBytesToPush,
2310 OutSize: NumBytes - NumBytesToPush, DL: dl);
2311
2312 SDValue RetAddrFrIdx;
2313 // Load return address for tail calls.
2314 if (isTailCall && FPDiff)
2315 Chain = EmitTailCallLoadRetAddr(DAG, OutRetAddr&: RetAddrFrIdx, Chain, IsTailCall: isTailCall,
2316 Is64Bit, FPDiff, dl);
2317
2318 SmallVector<std::pair<Register, SDValue>, 8> RegsToPass;
2319 SmallVector<SDValue, 8> MemOpChains;
2320
2321 // The next loop assumes that the locations are in the same order of the
2322 // input arguments.
2323 assert(isSortedByValueNo(ArgLocs) &&
2324 "Argument Location list must be sorted before lowering");
2325
2326 // Walk the register/memloc assignments, inserting copies/loads. In the case
2327 // of tail call optimization arguments are handle later.
2328 for (unsigned I = 0, OutIndex = 0, E = ArgLocs.size(); I != E;
2329 ++I, ++OutIndex) {
2330 assert(OutIndex < Outs.size() && "Invalid Out index");
2331 // Skip inalloca/preallocated arguments, they have already been written.
2332 ISD::ArgFlagsTy Flags = Outs[OutIndex].Flags;
2333 if (Flags.isInAlloca() || Flags.isPreallocated())
2334 continue;
2335
2336 CCValAssign &VA = ArgLocs[I];
2337 EVT RegVT = VA.getLocVT();
2338 SDValue Arg = OutVals[OutIndex];
2339 bool isByVal = Flags.isByVal();
2340
2341 // Promote the value if needed.
2342 switch (VA.getLocInfo()) {
2343 default: llvm_unreachable("Unknown loc info!");
2344 case CCValAssign::Full: break;
2345 case CCValAssign::SExt:
2346 Arg = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL: dl, VT: RegVT, Operand: Arg);
2347 break;
2348 case CCValAssign::ZExt:
2349 Arg = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: RegVT, Operand: Arg);
2350 break;
2351 case CCValAssign::AExt:
2352 if (Arg.getValueType().isVector() &&
2353 Arg.getValueType().getVectorElementType() == MVT::i1)
2354 Arg = lowerMasksToReg(ValArg: Arg, ValLoc: RegVT, DL: dl, DAG);
2355 else if (RegVT.is128BitVector()) {
2356 // Special case: passing MMX values in XMM registers.
2357 Arg = DAG.getBitcast(VT: MVT::i64, V: Arg);
2358 Arg = DAG.getNode(Opcode: ISD::SCALAR_TO_VECTOR, DL: dl, VT: MVT::v2i64, Operand: Arg);
2359 Arg = getMOVL(DAG, dl, VT: MVT::v2i64, V1: DAG.getUNDEF(VT: MVT::v2i64), V2: Arg);
2360 } else
2361 Arg = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: RegVT, Operand: Arg);
2362 break;
2363 case CCValAssign::BCvt:
2364 Arg = DAG.getBitcast(VT: RegVT, V: Arg);
2365 break;
2366 case CCValAssign::Indirect: {
2367 if (isByVal) {
2368 // Memcpy the argument to a temporary stack slot to prevent
2369 // the caller from seeing any modifications the callee may make
2370 // as guaranteed by the `byval` attribute.
2371 int FrameIdx = MF.getFrameInfo().CreateStackObject(
2372 Size: Flags.getByValSize(),
2373 Alignment: std::max(a: Align(16), b: Flags.getNonZeroByValAlign()), isSpillSlot: false);
2374 SDValue StackSlot =
2375 DAG.getFrameIndex(FI: FrameIdx, VT: getPointerTy(DL: DAG.getDataLayout()));
2376 Chain =
2377 CreateCopyOfByValArgument(Src: Arg, Dst: StackSlot, Chain, Flags, DAG, dl);
2378 // From now on treat this as a regular pointer
2379 Arg = StackSlot;
2380 isByVal = false;
2381 } else {
2382 // Store the argument.
2383 SDValue SpillSlot = DAG.CreateStackTemporary(VT: VA.getValVT());
2384 int FI = cast<FrameIndexSDNode>(Val&: SpillSlot)->getIndex();
2385 Chain = DAG.getStore(
2386 Chain, dl, Val: Arg, Ptr: SpillSlot,
2387 PtrInfo: MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI));
2388 Arg = SpillSlot;
2389 }
2390 break;
2391 }
2392 }
2393
2394 if (VA.needsCustom()) {
2395 assert(VA.getValVT() == MVT::v64i1 &&
2396 "Currently the only custom case is when we split v64i1 to 2 regs");
2397 // Split v64i1 value into two registers
2398 Passv64i1ArgInRegs(DL: dl, DAG, Arg, RegsToPass, VA, NextVA&: ArgLocs[++I], Subtarget);
2399 } else if (VA.isRegLoc()) {
2400 RegsToPass.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: Arg));
2401 const TargetOptions &Options = DAG.getTarget().Options;
2402 if (Options.EmitCallSiteInfo)
2403 CSInfo.ArgRegPairs.emplace_back(Args: VA.getLocReg(), Args&: I);
2404 if (isVarArg && IsWin64) {
2405 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2406 // shadow reg if callee is a varargs function.
2407 Register ShadowReg;
2408 switch (VA.getLocReg()) {
2409 case X86::XMM0: ShadowReg = X86::RCX; break;
2410 case X86::XMM1: ShadowReg = X86::RDX; break;
2411 case X86::XMM2: ShadowReg = X86::R8; break;
2412 case X86::XMM3: ShadowReg = X86::R9; break;
2413 }
2414 if (ShadowReg)
2415 RegsToPass.push_back(Elt: std::make_pair(x&: ShadowReg, y&: Arg));
2416 }
2417 } else if (!IsSibcall && (!isTailCall || (isByVal && !IsMustTail))) {
2418 assert(VA.isMemLoc());
2419 if (!StackPtr.getNode())
2420 StackPtr = DAG.getCopyFromReg(Chain, dl, Reg: RegInfo->getStackRegister(),
2421 VT: getPointerTy(DL: DAG.getDataLayout()));
2422 MemOpChains.push_back(Elt: LowerMemOpCallTo(Chain, StackPtr, Arg,
2423 dl, DAG, VA, Flags, isByVal));
2424 }
2425 }
2426
2427 if (!MemOpChains.empty())
2428 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: MemOpChains);
2429
2430 if (Subtarget.isPICStyleGOT()) {
2431 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2432 // GOT pointer.
2433 if (!isTailCall) {
2434 // Only PLT calls (GlobalAddress or ExternalSymbol) require the GOT in
2435 // EBX. Indirect calls through a register or an absolute address do not
2436 // go through the PLT and do not need EBX to hold the GOT base.
2437 if ((Callee->getOpcode() == ISD::GlobalAddress ||
2438 Callee->getOpcode() == ISD::ExternalSymbol))
2439 RegsToPass.push_back(Elt: std::make_pair(
2440 x: Register(X86::EBX), y: DAG.getNode(Opcode: X86ISD::GlobalBaseReg, DL: SDLoc(),
2441 VT: getPointerTy(DL: DAG.getDataLayout()))));
2442 } else {
2443 // If we are tail calling and generating PIC/GOT style code load the
2444 // address of the callee into ECX. The value in ecx is used as target of
2445 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2446 // for tail calls on PIC/GOT architectures. Normally we would just put the
2447 // address of GOT into ebx and then call target@PLT. But for tail calls
2448 // ebx would be restored (since ebx is callee saved) before jumping to the
2449 // target@PLT.
2450
2451 // Note: The actual moving to ECX is done further down.
2452 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Val&: Callee);
2453 if (G && !G->getGlobal()->hasLocalLinkage() &&
2454 G->getGlobal()->hasDefaultVisibility())
2455 Callee = LowerGlobalAddress(Op: Callee, DAG);
2456 else if (isa<ExternalSymbolSDNode>(Val: Callee))
2457 Callee = LowerExternalSymbol(Op: Callee, DAG);
2458 }
2459 }
2460
2461 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail &&
2462 (Subtarget.hasSSE1() || !M->getModuleFlag(Key: "SkipRaxSetup"))) {
2463 // From AMD64 ABI document:
2464 // For calls that may call functions that use varargs or stdargs
2465 // (prototype-less calls or calls to functions containing ellipsis (...) in
2466 // the declaration) %al is used as hidden argument to specify the number
2467 // of SSE registers used. The contents of %al do not need to match exactly
2468 // the number of registers, but must be an ubound on the number of SSE
2469 // registers used and is in the range 0 - 8 inclusive.
2470
2471 // Count the number of XMM registers allocated.
2472 static const MCPhysReg XMMArgRegs[] = {
2473 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2474 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2475 };
2476 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(Regs: XMMArgRegs);
2477 assert((Subtarget.hasSSE1() || !NumXMMRegs)
2478 && "SSE registers cannot be used when SSE is disabled");
2479 RegsToPass.push_back(Elt: std::make_pair(x: Register(X86::AL),
2480 y: DAG.getConstant(Val: NumXMMRegs, DL: dl,
2481 VT: MVT::i8)));
2482 }
2483
2484 if (isVarArg && IsMustTail) {
2485 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2486 for (const auto &F : Forwards) {
2487 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg: F.VReg, VT: F.VT);
2488 RegsToPass.push_back(Elt: std::make_pair(x: F.PReg, y&: Val));
2489 }
2490 }
2491
2492 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2493 // don't need this because the eligibility check rejects calls that require
2494 // shuffling arguments passed in memory.
2495 if (isTailCall && !IsSibcall) {
2496 // Force all the incoming stack arguments to be loaded from the stack
2497 // before any new outgoing arguments or the return address are stored to the
2498 // stack, because the outgoing stack slots may alias the incoming argument
2499 // stack slots, and the alias isn't otherwise explicit. This is slightly
2500 // more conservative than necessary, because it means that each store
2501 // effectively depends on every argument instead of just those arguments it
2502 // would clobber.
2503 Chain = DAG.getStackArgumentTokenFactor(Chain);
2504
2505 if (ByValTempChain)
2506 Chain =
2507 DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Chain, N2: ByValTempChain);
2508
2509 SmallVector<SDValue, 8> MemOpChains2;
2510 SDValue FIN;
2511 int FI = 0;
2512 for (unsigned I = 0, OutsIndex = 0, E = ArgLocs.size(); I != E;
2513 ++I, ++OutsIndex) {
2514 CCValAssign &VA = ArgLocs[I];
2515
2516 if (VA.isRegLoc()) {
2517 if (VA.needsCustom()) {
2518 assert((CallConv == CallingConv::X86_RegCall) &&
2519 "Expecting custom case only in regcall calling convention");
2520 // This means that we are in special case where one argument was
2521 // passed through two register locations - Skip the next location
2522 ++I;
2523 }
2524
2525 continue;
2526 }
2527
2528 assert(VA.isMemLoc());
2529 SDValue Arg = OutVals[OutsIndex];
2530 ISD::ArgFlagsTy Flags = Outs[OutsIndex].Flags;
2531 // Skip inalloca/preallocated arguments. They don't require any work.
2532 if (Flags.isInAlloca() || Flags.isPreallocated())
2533 continue;
2534 // Create frame index.
2535 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2536 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2537 FI = MF.getFrameInfo().CreateFixedObject(Size: OpSize, SPOffset: Offset, IsImmutable: true);
2538 FIN = DAG.getFrameIndex(FI, VT: getPointerTy(DL: DAG.getDataLayout()));
2539
2540 if (Flags.isByVal()) {
2541 if (SDValue ByValSrc = ByValTemporaries[OutsIndex]) {
2542 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
2543 SDValue DstAddr = DAG.getFrameIndex(FI, VT: PtrVT);
2544
2545 MemOpChains2.push_back(Elt: CreateCopyOfByValArgument(
2546 Src: ByValSrc, Dst: DstAddr, Chain, Flags, DAG, dl));
2547 }
2548 } else {
2549 // Store relative to framepointer.
2550 MemOpChains2.push_back(Elt: DAG.getStore(
2551 Chain, dl, Val: Arg, Ptr: FIN,
2552 PtrInfo: MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI)));
2553 }
2554 }
2555
2556 if (!MemOpChains2.empty())
2557 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: MemOpChains2);
2558
2559 // Store the return address to the appropriate stack slot.
2560 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2561 PtrVT: getPointerTy(DL: DAG.getDataLayout()),
2562 SlotSize: RegInfo->getSlotSize(), FPDiff, dl);
2563 }
2564
2565 // Build a sequence of copy-to-reg nodes chained together with token chain
2566 // and glue operands which copy the outgoing args into registers.
2567 SDValue InGlue;
2568 for (const auto &[Reg, N] : RegsToPass) {
2569 Chain = DAG.getCopyToReg(Chain, dl, Reg, N, Glue: InGlue);
2570 InGlue = Chain.getValue(R: 1);
2571 }
2572
2573 bool IsImpCall = false;
2574 bool IsCFGuardCall = false;
2575 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
2576 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2577 // In the 64-bit large code model, we have to make all calls
2578 // through a register, since the call instruction's 32-bit
2579 // pc-relative offset may not be large enough to hold the whole
2580 // address.
2581 } else if (Callee->getOpcode() == ISD::GlobalAddress ||
2582 Callee->getOpcode() == ISD::ExternalSymbol) {
2583 // Lower direct calls to global addresses and external symbols. Setting
2584 // ForCall to true here has the effect of removing WrapperRIP when possible
2585 // to allow direct calls to be selected without first materializing the
2586 // address into a register.
2587 Callee = LowerGlobalOrExternal(Op: Callee, DAG, /*ForCall=*/true, IsImpCall: &IsImpCall);
2588 } else if (Subtarget.isTarget64BitILP32() &&
2589 Callee.getValueType() == MVT::i32) {
2590 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
2591 Callee = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: MVT::i64, Operand: Callee);
2592 } else if (Is64Bit && CB && isCFGuardCall(CB)) {
2593 // We'll use a specific psuedo instruction for tail calls to control flow
2594 // guard functions to guarantee the instruction used for the call. To do
2595 // this we need to unwrap the load now and use the CFG Func GV as the
2596 // callee.
2597 IsCFGuardCall = true;
2598 auto *LoadNode = cast<LoadSDNode>(Val&: Callee);
2599 GlobalAddressSDNode *GA =
2600 cast<GlobalAddressSDNode>(Val: unwrapAddress(N: LoadNode->getBasePtr()));
2601 assert(isCFGuardFunction(GA->getGlobal()) &&
2602 "CFG Call should be to a guard function");
2603 assert(LoadNode->getOffset()->isUndef() &&
2604 "CFG Function load should not have an offset");
2605 Callee = DAG.getTargetGlobalAddress(
2606 GV: GA->getGlobal(), DL: dl, VT: GA->getValueType(ResNo: 0), offset: 0, TargetFlags: X86II::MO_NO_FLAG);
2607 }
2608
2609 SmallVector<SDValue, 8> Ops;
2610
2611 if (!IsSibcall && isTailCall && !IsMustTail) {
2612 Chain = DAG.getCALLSEQ_END(Chain, Size1: NumBytesToPop, Size2: 0, Glue: InGlue, DL: dl);
2613 InGlue = Chain.getValue(R: 1);
2614 }
2615
2616 Ops.push_back(Elt: Chain);
2617 Ops.push_back(Elt: Callee);
2618
2619 if (isTailCall)
2620 Ops.push_back(Elt: DAG.getSignedTargetConstant(Val: FPDiff, DL: dl, VT: MVT::i32));
2621
2622 // Add argument registers to the end of the list so that they are known live
2623 // into the call.
2624 for (const auto &[Reg, N] : RegsToPass)
2625 Ops.push_back(Elt: DAG.getRegister(Reg, VT: N.getValueType()));
2626
2627 // Add a register mask operand representing the call-preserved registers.
2628 const uint32_t *Mask = [&]() {
2629 auto AdaptedCC = CallConv;
2630 // If HasNCSR is asserted (attribute NoCallerSavedRegisters exists),
2631 // use X86_INTR calling convention because it has the same CSR mask
2632 // (same preserved registers).
2633 if (HasNCSR)
2634 AdaptedCC = (CallingConv::ID)CallingConv::X86_INTR;
2635 // If NoCalleeSavedRegisters is requested, than use GHC since it happens
2636 // to use the CSR_NoRegs_RegMask.
2637 if (CB && CB->hasFnAttr(Kind: "no_callee_saved_registers"))
2638 AdaptedCC = (CallingConv::ID)CallingConv::GHC;
2639 return RegInfo->getCallPreservedMask(MF, AdaptedCC);
2640 }();
2641 assert(Mask && "Missing call preserved mask for calling convention");
2642
2643 if (MachineOperand::clobbersPhysReg(RegMask: Mask, PhysReg: RegInfo->getFramePtr())) {
2644 X86Info->setFPClobberedByCall(true);
2645 if (CLI.CB && isa<InvokeInst>(Val: CLI.CB))
2646 X86Info->setFPClobberedByInvoke(true);
2647 }
2648 if (MachineOperand::clobbersPhysReg(RegMask: Mask, PhysReg: RegInfo->getBaseRegister())) {
2649 X86Info->setBPClobberedByCall(true);
2650 if (CLI.CB && isa<InvokeInst>(Val: CLI.CB))
2651 X86Info->setBPClobberedByInvoke(true);
2652 }
2653
2654 // If this is an invoke in a 32-bit function using a funclet-based
2655 // personality, assume the function clobbers all registers. If an exception
2656 // is thrown, the runtime will not restore CSRs.
2657 // FIXME: Model this more precisely so that we can register allocate across
2658 // the normal edge and spill and fill across the exceptional edge.
2659 if (!Is64Bit && CLI.CB && isa<InvokeInst>(Val: CLI.CB)) {
2660 const Function &CallerFn = MF.getFunction();
2661 EHPersonality Pers =
2662 CallerFn.hasPersonalityFn()
2663 ? classifyEHPersonality(Pers: CallerFn.getPersonalityFn())
2664 : EHPersonality::Unknown;
2665 if (isFuncletEHPersonality(Pers))
2666 Mask = RegInfo->getNoPreservedMask();
2667 }
2668
2669 // Define a new register mask from the existing mask.
2670 uint32_t *RegMask = nullptr;
2671
2672 // In some calling conventions we need to remove the used physical registers
2673 // from the reg mask. Create a new RegMask for such calling conventions.
2674 // RegMask for calling conventions that disable only return registers (e.g.
2675 // preserve_most) will be modified later in LowerCallResult.
2676 bool ShouldDisableArgRegs = shouldDisableArgRegFromCSR(CC: CallConv) || HasNCSR;
2677 if (ShouldDisableArgRegs || shouldDisableRetRegFromCSR(CC: CallConv)) {
2678 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2679
2680 // Allocate a new Reg Mask and copy Mask.
2681 RegMask = MF.allocateRegMask();
2682 unsigned RegMaskSize = MachineOperand::getRegMaskSize(NumRegs: TRI->getNumRegs());
2683 memcpy(dest: RegMask, src: Mask, n: sizeof(RegMask[0]) * RegMaskSize);
2684
2685 // Make sure all sub registers of the argument registers are reset
2686 // in the RegMask.
2687 if (ShouldDisableArgRegs) {
2688 for (auto const &RegPair : RegsToPass)
2689 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg: RegPair.first))
2690 RegMask[SubReg / 32] &= ~(1u << (SubReg % 32));
2691 }
2692
2693 // Create the RegMask Operand according to our updated mask.
2694 Ops.push_back(Elt: DAG.getRegisterMask(RegMask));
2695 } else {
2696 // Create the RegMask Operand according to the static mask.
2697 Ops.push_back(Elt: DAG.getRegisterMask(RegMask: Mask));
2698 }
2699
2700 if (InGlue.getNode())
2701 Ops.push_back(Elt: InGlue);
2702
2703 if (isTailCall) {
2704 // We used to do:
2705 //// If this is the first return lowered for this function, add the regs
2706 //// to the liveout set for the function.
2707 // This isn't right, although it's probably harmless on x86; liveouts
2708 // should be computed from returns not tail calls. Consider a void
2709 // function making a tail call to a function returning int.
2710 MF.getFrameInfo().setHasTailCall();
2711 auto Opcode =
2712 IsCFGuardCall ? X86ISD::TC_RETURN_GLOBALADDR : X86ISD::TC_RETURN;
2713 SDValue Ret = DAG.getNode(Opcode, DL: dl, VT: MVT::Other, Ops);
2714
2715 if (IsCFICall)
2716 Ret.getNode()->setCFIType(CLI.CFIType->getZExtValue());
2717
2718 DAG.addNoMergeSiteInfo(Node: Ret.getNode(), NoMerge: CLI.NoMerge);
2719 DAG.addCallSiteInfo(Node: Ret.getNode(), CallInfo: std::move(CSInfo));
2720 return Ret;
2721 }
2722
2723 // Returns a chain & a glue for retval copy to use.
2724 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
2725 if (IsImpCall) {
2726 Chain = DAG.getNode(Opcode: X86ISD::IMP_CALL, DL: dl, VTList: NodeTys, Ops);
2727 } else if (IsNoTrackIndirectCall) {
2728 Chain = DAG.getNode(Opcode: X86ISD::NT_CALL, DL: dl, VTList: NodeTys, Ops);
2729 } else if (IsCFGuardCall) {
2730 Chain = DAG.getNode(Opcode: X86ISD::CALL_GLOBALADDR, DL: dl, VTList: NodeTys, Ops);
2731 } else if (CLI.CB && objcarc::hasAttachedCallOpBundle(CB: CLI.CB)) {
2732 // Calls with a "clang.arc.attachedcall" bundle are special. They should be
2733 // expanded to the call, directly followed by a special marker sequence and
2734 // a call to a ObjC library function. Use the CALL_RVMARKER to do that.
2735 assert(!isTailCall &&
2736 "tail calls cannot be marked with clang.arc.attachedcall");
2737 assert(Is64Bit && "clang.arc.attachedcall is only supported in 64bit mode");
2738
2739 // Add a target global address for the retainRV/claimRV runtime function
2740 // just before the call target.
2741 Function *ARCFn = *objcarc::getAttachedARCFunction(CB: CLI.CB);
2742 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
2743 auto GA = DAG.getTargetGlobalAddress(GV: ARCFn, DL: dl, VT: PtrVT);
2744 Ops.insert(I: Ops.begin() + 1, Elt: GA);
2745 Chain = DAG.getNode(Opcode: X86ISD::CALL_RVMARKER, DL: dl, VTList: NodeTys, Ops);
2746 } else {
2747 Chain = DAG.getNode(Opcode: X86ISD::CALL, DL: dl, VTList: NodeTys, Ops);
2748 }
2749
2750 if (IsCFICall)
2751 Chain.getNode()->setCFIType(CLI.CFIType->getZExtValue());
2752
2753 InGlue = Chain.getValue(R: 1);
2754 DAG.addNoMergeSiteInfo(Node: Chain.getNode(), NoMerge: CLI.NoMerge);
2755 DAG.addCallSiteInfo(Node: Chain.getNode(), CallInfo: std::move(CSInfo));
2756
2757 // Save heapallocsite metadata.
2758 if (CLI.CB)
2759 if (MDNode *HeapAlloc = CLI.CB->getMetadata(Kind: "heapallocsite"))
2760 DAG.addHeapAllocSite(Node: Chain.getNode(), MD: HeapAlloc);
2761
2762 // Create the CALLSEQ_END node.
2763 unsigned NumBytesForCalleeToPop = 0; // Callee pops nothing.
2764 if (X86::isCalleePop(CallingConv: CallConv, is64Bit: Is64Bit, IsVarArg: isVarArg,
2765 GuaranteeTCO: DAG.getTarget().Options.GuaranteedTailCallOpt)) {
2766 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
2767 } else if (hasCalleePopSRet(Args: Outs, ArgLocs, Subtarget)) {
2768 // If this call passes a struct-return pointer, the callee
2769 // pops that struct pointer.
2770 NumBytesForCalleeToPop = 4;
2771 }
2772
2773 // Returns a glue for retval copy to use.
2774 if (!IsSibcall) {
2775 Chain = DAG.getCALLSEQ_END(Chain, Size1: NumBytesToPop, Size2: NumBytesForCalleeToPop,
2776 Glue: InGlue, DL: dl);
2777 InGlue = Chain.getValue(R: 1);
2778 }
2779
2780 if (CallingConv::PreserveNone == CallConv)
2781 for (const ISD::OutputArg &Out : Outs) {
2782 if (Out.Flags.isSwiftSelf() || Out.Flags.isSwiftAsync() ||
2783 Out.Flags.isSwiftError()) {
2784 errorUnsupported(DAG, dl,
2785 Msg: "Swift attributes can't be used with preserve_none");
2786 break;
2787 }
2788 }
2789
2790 // Handle result values, copying them out of physregs into vregs that we
2791 // return.
2792 return LowerCallResult(Chain, InGlue, CallConv, isVarArg, Ins, dl, DAG,
2793 InVals, RegMask);
2794}
2795
2796//===----------------------------------------------------------------------===//
2797// Fast Calling Convention (tail call) implementation
2798//===----------------------------------------------------------------------===//
2799
2800// Like std call, callee cleans arguments, convention except that ECX is
2801// reserved for storing the tail called function address. Only 2 registers are
2802// free for argument passing (inreg). Tail call optimization is performed
2803// provided:
2804// * tailcallopt is enabled
2805// * caller/callee are fastcc
2806// On X86_64 architecture with GOT-style position independent code only local
2807// (within module) calls are supported at the moment.
2808// To keep the stack aligned according to platform abi the function
2809// GetAlignedArgumentStackSize ensures that argument delta is always multiples
2810// of stack alignment. (Dynamic linkers need this - Darwin's dyld for example)
2811// If a tail called function callee has more arguments than the caller the
2812// caller needs to make sure that there is room to move the RETADDR to. This is
2813// achieved by reserving an area the size of the argument delta right after the
2814// original RETADDR, but before the saved framepointer or the spilled registers
2815// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2816// stack layout:
2817// arg1
2818// arg2
2819// RETADDR
2820// [ new RETADDR
2821// move area ]
2822// (possible EBP)
2823// ESI
2824// EDI
2825// local1 ..
2826
2827/// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
2828/// requirement.
2829unsigned
2830X86TargetLowering::GetAlignedArgumentStackSize(const unsigned StackSize,
2831 SelectionDAG &DAG) const {
2832 const Align StackAlignment = Subtarget.getFrameLowering()->getStackAlign();
2833 const uint64_t SlotSize = Subtarget.getRegisterInfo()->getSlotSize();
2834 assert(StackSize % SlotSize == 0 &&
2835 "StackSize must be a multiple of SlotSize");
2836 return alignTo(Size: StackSize + SlotSize, A: StackAlignment) - SlotSize;
2837}
2838
2839/// Return true if the given stack call argument is already available in the
2840/// same position (relatively) of the caller's incoming argument stack.
2841static
2842bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2843 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
2844 const X86InstrInfo *TII, const CCValAssign &VA) {
2845 unsigned Bytes = Arg.getValueSizeInBits() / 8;
2846
2847 for (;;) {
2848 // Look through nodes that don't alter the bits of the incoming value.
2849 unsigned Op = Arg.getOpcode();
2850 if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST ||
2851 Op == ISD::AssertZext) {
2852 Arg = Arg.getOperand(i: 0);
2853 continue;
2854 }
2855 if (Op == ISD::TRUNCATE) {
2856 const SDValue &TruncInput = Arg.getOperand(i: 0);
2857 if (TruncInput.getOpcode() == ISD::AssertZext &&
2858 cast<VTSDNode>(Val: TruncInput.getOperand(i: 1))->getVT() ==
2859 Arg.getValueType()) {
2860 Arg = TruncInput.getOperand(i: 0);
2861 continue;
2862 }
2863 }
2864 break;
2865 }
2866
2867 int FI = INT_MAX;
2868 if (Arg.getOpcode() == ISD::CopyFromReg) {
2869 Register VR = cast<RegisterSDNode>(Val: Arg.getOperand(i: 1))->getReg();
2870 if (!VR.isVirtual())
2871 return false;
2872 MachineInstr *Def = MRI->getVRegDef(Reg: VR);
2873 if (!Def)
2874 return false;
2875 if (!Flags.isByVal()) {
2876 if (!TII->isLoadFromStackSlot(MI: *Def, FrameIndex&: FI))
2877 return false;
2878 } else {
2879 unsigned Opcode = Def->getOpcode();
2880 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
2881 Opcode == X86::LEA64_32r) &&
2882 Def->getOperand(i: 1).isFI()) {
2883 FI = Def->getOperand(i: 1).getIndex();
2884 Bytes = Flags.getByValSize();
2885 } else
2886 return false;
2887 }
2888 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Val&: Arg)) {
2889 if (Flags.isByVal())
2890 // ByVal argument is passed in as a pointer but it's now being
2891 // dereferenced. e.g.
2892 // define @foo(%struct.X* %A) {
2893 // tail call @bar(%struct.X* byval %A)
2894 // }
2895 return false;
2896 SDValue Ptr = Ld->getBasePtr();
2897 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Val&: Ptr);
2898 if (!FINode)
2899 return false;
2900 FI = FINode->getIndex();
2901 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2902 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Val&: Arg);
2903 FI = FINode->getIndex();
2904 Bytes = Flags.getByValSize();
2905 } else
2906 return false;
2907
2908 assert(FI != INT_MAX);
2909 if (!MFI.isFixedObjectIndex(ObjectIdx: FI))
2910 return false;
2911
2912 if (Offset != MFI.getObjectOffset(ObjectIdx: FI))
2913 return false;
2914
2915 // If this is not byval, check that the argument stack object is immutable.
2916 // inalloca and argument copy elision can create mutable argument stack
2917 // objects. Byval objects can be mutated, but a byval call intends to pass the
2918 // mutated memory.
2919 if (!Flags.isByVal() && !MFI.isImmutableObjectIndex(ObjectIdx: FI))
2920 return false;
2921
2922 if (VA.getLocVT().getFixedSizeInBits() >
2923 Arg.getValueSizeInBits().getFixedValue()) {
2924 // If the argument location is wider than the argument type, check that any
2925 // extension flags match.
2926 if (Flags.isZExt() != MFI.isObjectZExt(ObjectIdx: FI) ||
2927 Flags.isSExt() != MFI.isObjectSExt(ObjectIdx: FI)) {
2928 return false;
2929 }
2930 }
2931
2932 return Bytes == MFI.getObjectSize(ObjectIdx: FI);
2933}
2934
2935static bool
2936mayBeSRetTailCallCompatible(const TargetLowering::CallLoweringInfo &CLI,
2937 Register CallerSRetReg) {
2938 const auto &Outs = CLI.Outs;
2939 const auto &OutVals = CLI.OutVals;
2940
2941 // We know the caller has a sret pointer argument (CallerSRetReg). Locate the
2942 // operand index within the callee that may have a sret pointer too.
2943 unsigned Pos = 0;
2944 for (unsigned E = Outs.size(); Pos != E; ++Pos)
2945 if (Outs[Pos].Flags.isSRet())
2946 break;
2947 // Bail out if the callee has not any sret argument.
2948 if (Pos == Outs.size())
2949 return false;
2950
2951 // At this point, either the caller is forwarding its sret argument to the
2952 // callee, or the callee is being passed a different sret pointer. We now look
2953 // for a CopyToReg, where the callee sret argument is written into a new vreg
2954 // (which should later be %rax/%eax, if this is returned).
2955 SDValue SRetArgVal = OutVals[Pos];
2956 for (SDNode *User : SRetArgVal->users()) {
2957 if (User->getOpcode() != ISD::CopyToReg)
2958 continue;
2959 Register Reg = cast<RegisterSDNode>(Val: User->getOperand(Num: 1))->getReg();
2960 if (Reg == CallerSRetReg && User->getOperand(Num: 2) == SRetArgVal)
2961 return true;
2962 }
2963
2964 return false;
2965}
2966
2967/// Check whether the call is eligible for sibling call optimization. Sibling
2968/// calls are loosely defined to be simple, profitable tail calls that only
2969/// require adjusting register parameters. We do not speculatively to optimize
2970/// complex calls that require lots of argument memory operations that may
2971/// alias.
2972///
2973/// Note that LLVM supports multiple ways, such as musttail, to force tail call
2974/// emission. Returning false from this function will not prevent tail call
2975/// emission in all cases.
2976bool X86TargetLowering::isEligibleForSiblingCallOpt(
2977 TargetLowering::CallLoweringInfo &CLI, CCState &CCInfo,
2978 SmallVectorImpl<CCValAssign> &ArgLocs) const {
2979 SelectionDAG &DAG = CLI.DAG;
2980 const SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2981 const SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2982 const SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2983 SDValue Callee = CLI.Callee;
2984 CallingConv::ID CalleeCC = CLI.CallConv;
2985 bool isVarArg = CLI.IsVarArg;
2986
2987 if (!mayTailCallThisCC(CC: CalleeCC))
2988 return false;
2989
2990 // If -tailcallopt is specified, make fastcc functions tail-callable.
2991 MachineFunction &MF = DAG.getMachineFunction();
2992 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2993 const Function &CallerF = MF.getFunction();
2994
2995 // If the function return type is x86_fp80 and the callee return type is not,
2996 // then the FP_EXTEND of the call result is not a nop. It's not safe to
2997 // perform a tailcall optimization here.
2998 if (CallerF.getReturnType()->isX86_FP80Ty() && !CLI.RetTy->isX86_FP80Ty())
2999 return false;
3000
3001 // Win64 functions have extra shadow space for argument homing. Don't do the
3002 // sibcall if the caller and callee have mismatched expectations for this
3003 // space.
3004 CallingConv::ID CallerCC = CallerF.getCallingConv();
3005 bool IsCalleeWin64 = Subtarget.isCallingConvWin64(CC: CalleeCC);
3006 bool IsCallerWin64 = Subtarget.isCallingConvWin64(CC: CallerCC);
3007 if (IsCalleeWin64 != IsCallerWin64)
3008 return false;
3009
3010 // Do not optimize vararg calls with 6 arguments for LFI since LFI reserves
3011 // %r11, meaning there will not be enough registers available.
3012 if (Subtarget.isLFI() && ArgLocs.size() > 5)
3013 return false;
3014
3015 // If we are using a GOT, don't generate sibling calls to non-local,
3016 // default-visibility symbols. Tail calling such a symbol requires using a GOT
3017 // relocation, which forces early binding of the symbol. This breaks code that
3018 // require lazy function symbol resolution. Using musttail or
3019 // GuaranteedTailCallOpt will override this.
3020 if (Subtarget.isPICStyleGOT()) {
3021 if (isa<ExternalSymbolSDNode>(Val: Callee))
3022 return false;
3023 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Val&: Callee)) {
3024 if (!G->getGlobal()->hasLocalLinkage() &&
3025 G->getGlobal()->hasDefaultVisibility())
3026 return false;
3027 }
3028 }
3029
3030 // Look for obvious safe cases to perform tail call optimization that do not
3031 // require ABI changes. This is what gcc calls sibcall.
3032
3033 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3034 // emit a special epilogue.
3035 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
3036 if (RegInfo->hasStackRealignment(MF))
3037 return false;
3038
3039 // Avoid sibcall optimization if we are an sret return function and the callee
3040 // is incompatible, unless such premises are proven wrong. See comment in
3041 // LowerReturn about why hasStructRetAttr is insufficient.
3042 if (Register SRetReg = FuncInfo->getSRetReturnReg()) {
3043 // For a compatible tail call the callee must return our sret pointer. So it
3044 // needs to be (a) an sret function itself and (b) we pass our sret as its
3045 // sret. Condition #b is harder to determine.
3046 if (!mayBeSRetTailCallCompatible(CLI, CallerSRetReg: SRetReg))
3047 return false;
3048 } else if (hasCalleePopSRet(Args: Outs, ArgLocs, Subtarget))
3049 // The callee pops an sret, so we cannot tail-call, as our caller doesn't
3050 // expect that.
3051 return false;
3052
3053 // Do not sibcall optimize vararg calls unless all arguments are passed via
3054 // registers.
3055 LLVMContext &C = *DAG.getContext();
3056 if (isVarArg && !Outs.empty()) {
3057 // Optimizing for varargs on Win64 is unlikely to be safe without
3058 // additional testing.
3059 if (IsCalleeWin64 || IsCallerWin64)
3060 return false;
3061
3062 for (const auto &VA : ArgLocs)
3063 if (!VA.isRegLoc())
3064 return false;
3065 }
3066
3067 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3068 // stack. Therefore, if it's not used by the call it is not safe to optimize
3069 // this into a sibcall.
3070 bool Unused = false;
3071 for (const auto &In : Ins) {
3072 if (!In.Used) {
3073 Unused = true;
3074 break;
3075 }
3076 }
3077 if (Unused) {
3078 SmallVector<CCValAssign, 16> RVLocs;
3079 CCState RVCCInfo(CalleeCC, false, MF, RVLocs, C);
3080 RVCCInfo.AnalyzeCallResult(Ins, Fn: RetCC_X86);
3081 for (const auto &VA : RVLocs) {
3082 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3083 return false;
3084 }
3085 }
3086
3087 // Check that the call results are passed in the same way.
3088 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins,
3089 CalleeFn: RetCC_X86, CallerFn: RetCC_X86))
3090 return false;
3091 // The callee has to preserve all registers the caller needs to preserve.
3092 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
3093 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
3094 if (CallerCC != CalleeCC) {
3095 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
3096 if (!TRI->regmaskSubsetEqual(mask0: CallerPreserved, mask1: CalleePreserved))
3097 return false;
3098 }
3099
3100 // The stack frame of the caller cannot be replaced by the tail-callee one's
3101 // if the function is required to preserve all the registers. Conservatively
3102 // prevent tail optimization even if hypothetically all the registers are used
3103 // for passing formal parameters or returning values.
3104 if (CallerF.hasFnAttribute(Kind: "no_caller_saved_registers"))
3105 return false;
3106
3107 unsigned StackArgsSize = CCInfo.getStackSize();
3108
3109 // If the callee takes no arguments then go on to check the results of the
3110 // call.
3111 if (!Outs.empty()) {
3112 if (StackArgsSize > 0) {
3113 // Check if the arguments are already laid out in the right way as
3114 // the caller's fixed stack objects.
3115 MachineFrameInfo &MFI = MF.getFrameInfo();
3116 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3117 const X86InstrInfo *TII = Subtarget.getInstrInfo();
3118 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
3119 const CCValAssign &VA = ArgLocs[I];
3120 SDValue Arg = OutVals[I];
3121 ISD::ArgFlagsTy Flags = Outs[I].Flags;
3122 if (VA.getLocInfo() == CCValAssign::Indirect)
3123 return false;
3124 if (!VA.isRegLoc()) {
3125 if (!MatchingStackOffset(Arg, Offset: VA.getLocMemOffset(), Flags, MFI, MRI,
3126 TII, VA))
3127 return false;
3128 }
3129 }
3130 }
3131
3132 bool PositionIndependent = isPositionIndependent();
3133 // If the tailcall address may be in a register, then make sure it's
3134 // possible to register allocate for it. In 32-bit, the call address can
3135 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3136 // callee-saved registers are restored. These happen to be the same
3137 // registers used to pass 'inreg' arguments so watch out for those.
3138 if (!Subtarget.is64Bit() && ((!isa<GlobalAddressSDNode>(Val: Callee) &&
3139 !isa<ExternalSymbolSDNode>(Val: Callee)) ||
3140 PositionIndependent)) {
3141 unsigned NumInRegs = 0;
3142 // In PIC we need an extra register to formulate the address computation
3143 // for the callee.
3144 unsigned MaxInRegs = PositionIndependent ? 2 : 3;
3145
3146 for (const auto &VA : ArgLocs) {
3147 if (!VA.isRegLoc())
3148 continue;
3149 Register Reg = VA.getLocReg();
3150 switch (Reg) {
3151 default: break;
3152 case X86::EAX: case X86::EDX: case X86::ECX:
3153 if (++NumInRegs == MaxInRegs)
3154 return false;
3155 break;
3156 }
3157 }
3158 }
3159
3160 const MachineRegisterInfo &MRI = MF.getRegInfo();
3161 if (!parametersInCSRMatch(MRI, CallerPreservedMask: CallerPreserved, ArgLocs, OutVals))
3162 return false;
3163 }
3164
3165 bool CalleeWillPop =
3166 X86::isCalleePop(CallingConv: CalleeCC, is64Bit: Subtarget.is64Bit(), IsVarArg: isVarArg,
3167 GuaranteeTCO: MF.getTarget().Options.GuaranteedTailCallOpt);
3168
3169 if (unsigned BytesToPop = FuncInfo->getBytesToPopOnReturn()) {
3170 // If we have bytes to pop, the callee must pop them.
3171 bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
3172 if (!CalleePopMatches)
3173 return false;
3174 } else if (CalleeWillPop && StackArgsSize > 0) {
3175 // If we don't have bytes to pop, make sure the callee doesn't pop any.
3176 return false;
3177 }
3178
3179 return true;
3180}
3181
3182/// Determines whether the callee is required to pop its own arguments.
3183/// Callee pop is necessary to support tail calls.
3184bool X86::isCalleePop(CallingConv::ID CallingConv,
3185 bool is64Bit, bool IsVarArg, bool GuaranteeTCO) {
3186 // If GuaranteeTCO is true, we force some calls to be callee pop so that we
3187 // can guarantee TCO.
3188 if (!IsVarArg && shouldGuaranteeTCO(CC: CallingConv, GuaranteedTailCallOpt: GuaranteeTCO))
3189 return true;
3190
3191 switch (CallingConv) {
3192 default:
3193 return false;
3194 case CallingConv::X86_StdCall:
3195 case CallingConv::X86_FastCall:
3196 case CallingConv::X86_ThisCall:
3197 case CallingConv::X86_VectorCall:
3198 return !is64Bit;
3199 }
3200}
3201