1//===- llvm/lib/Target/X86/X86ISelCallLowering.cpp - Call lowering --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// This file implements the lowering of LLVM calls to DAG nodes.
11//
12//===----------------------------------------------------------------------===//
13
14#include "MCTargetDesc/X86MCAsmInfo.h"
15#include "X86.h"
16#include "X86CallingConv.h"
17#include "X86FrameLowering.h"
18#include "X86ISelLowering.h"
19#include "X86InstrBuilder.h"
20#include "X86MachineFunctionInfo.h"
21#include "X86TargetMachine.h"
22#include "llvm/ADT/Statistic.h"
23#include "llvm/Analysis/ObjCARCUtil.h"
24#include "llvm/CodeGen/MachineJumpTableInfo.h"
25#include "llvm/CodeGen/MachineModuleInfo.h"
26#include "llvm/CodeGen/WinEHFuncInfo.h"
27#include "llvm/IR/DiagnosticInfo.h"
28#include "llvm/IR/IRBuilder.h"
29#include "llvm/IR/Module.h"
30#include "llvm/Transforms/CFGuard.h"
31
32#define DEBUG_TYPE "x86-isel"
33
34using namespace llvm;
35
36STATISTIC(NumTailCalls, "Number of tail calls");
37
38/// Call this when the user attempts to do something unsupported, like
39/// returning a double without SSE2 enabled on x86_64. This is not fatal, unlike
40/// report_fatal_error, so calling code should attempt to recover without
41/// crashing.
42static void errorUnsupported(SelectionDAG &DAG, const SDLoc &dl,
43 const char *Msg) {
44 MachineFunction &MF = DAG.getMachineFunction();
45 DAG.getContext()->diagnose(
46 DI: DiagnosticInfoUnsupported(MF.getFunction(), Msg, dl.getDebugLoc()));
47}
48
49/// Returns true if a CC can dynamically exclude a register from the list of
50/// callee-saved-registers (TargetRegistryInfo::getCalleeSavedRegs()) based on
51/// the return registers.
52static bool shouldDisableRetRegFromCSR(CallingConv::ID CC) {
53 switch (CC) {
54 default:
55 return false;
56 case CallingConv::X86_RegCall:
57 case CallingConv::PreserveMost:
58 case CallingConv::PreserveAll:
59 return true;
60 }
61}
62
63/// Returns true if a CC can dynamically exclude a register from the list of
64/// callee-saved-registers (TargetRegistryInfo::getCalleeSavedRegs()) based on
65/// the parameters.
66static bool shouldDisableArgRegFromCSR(CallingConv::ID CC) {
67 return CC == CallingConv::X86_RegCall;
68}
69
70static std::pair<MVT, unsigned>
71handleMaskRegisterForCallingConv(unsigned NumElts, CallingConv::ID CC,
72 const X86Subtarget &Subtarget) {
73 // v2i1/v4i1/v8i1/v16i1 all pass in xmm registers unless the calling
74 // convention is one that uses k registers.
75 if (NumElts == 2)
76 return {MVT::v2i64, 1};
77 if (NumElts == 4)
78 return {MVT::v4i32, 1};
79 if (NumElts == 8 && CC != CallingConv::X86_RegCall &&
80 CC != CallingConv::Intel_OCL_BI)
81 return {MVT::v8i16, 1};
82 if (NumElts == 16 && CC != CallingConv::X86_RegCall &&
83 CC != CallingConv::Intel_OCL_BI)
84 return {MVT::v16i8, 1};
85 // v32i1 passes in ymm unless we have BWI and the calling convention is
86 // regcall.
87 if (NumElts == 32 && (!Subtarget.hasBWI() || CC != CallingConv::X86_RegCall))
88 return {MVT::v32i8, 1};
89 // Split v64i1 vectors if we don't have v64i8 available.
90 if (NumElts == 64 && Subtarget.hasBWI() && CC != CallingConv::X86_RegCall) {
91 if (Subtarget.useAVX512Regs())
92 return {MVT::v64i8, 1};
93 return {MVT::v32i8, 2};
94 }
95
96 // Break wide or odd vXi1 vectors into scalars to match avx2 behavior.
97 if (!isPowerOf2_32(Value: NumElts) || (NumElts == 64 && !Subtarget.hasBWI()) ||
98 NumElts > 64)
99 return {MVT::i8, NumElts};
100
101 return {MVT::INVALID_SIMPLE_VALUE_TYPE, 0};
102}
103
104MVT X86TargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
105 CallingConv::ID CC,
106 EVT VT) const {
107 if (VT.isVector()) {
108 if (VT.getVectorElementType() == MVT::i1 && Subtarget.hasAVX512()) {
109 unsigned NumElts = VT.getVectorNumElements();
110
111 MVT RegisterVT;
112 unsigned NumRegisters;
113 std::tie(args&: RegisterVT, args&: NumRegisters) =
114 handleMaskRegisterForCallingConv(NumElts, CC, Subtarget);
115 if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
116 return RegisterVT;
117 }
118
119 if (VT.getVectorElementType() == MVT::f16 && VT.getVectorNumElements() < 8)
120 return MVT::v8f16;
121 }
122
123 // We will use more GPRs for f64 and f80 on 32 bits when x87 is disabled.
124 if ((VT == MVT::f64 || VT == MVT::f80) && !Subtarget.is64Bit() &&
125 !Subtarget.hasX87())
126 return MVT::i32;
127
128 if (isTypeLegal(VT: MVT::f16)) {
129 if (VT.isVectorOf(EltVT: MVT::bf16))
130 return getRegisterTypeForCallingConv(
131 Context, CC, VT: VT.changeVectorElementType(Context, EltVT: MVT::f16));
132
133 if (VT == MVT::bf16)
134 return MVT::f16;
135 }
136
137 return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
138}
139
140unsigned X86TargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
141 CallingConv::ID CC,
142 EVT VT) const {
143 if (VT.isVector()) {
144 if (VT.getVectorElementType() == MVT::i1 && Subtarget.hasAVX512()) {
145 unsigned NumElts = VT.getVectorNumElements();
146
147 MVT RegisterVT;
148 unsigned NumRegisters;
149 std::tie(args&: RegisterVT, args&: NumRegisters) =
150 handleMaskRegisterForCallingConv(NumElts, CC, Subtarget);
151 if (RegisterVT != MVT::INVALID_SIMPLE_VALUE_TYPE)
152 return NumRegisters;
153 }
154
155 if (VT.getVectorElementType() == MVT::f16 && VT.getVectorNumElements() < 8)
156 return 1;
157 }
158
159 // We have to split f64 to 2 registers and f80 to 3 registers on 32 bits if
160 // x87 is disabled.
161 if (!Subtarget.is64Bit() && !Subtarget.hasX87()) {
162 if (VT == MVT::f64)
163 return 2;
164 if (VT == MVT::f80)
165 return 3;
166 }
167
168 if (VT.isVectorOf(EltVT: MVT::bf16) && isTypeLegal(VT: MVT::f16))
169 return getNumRegistersForCallingConv(
170 Context, CC, VT: VT.changeVectorElementType(Context, EltVT: MVT::f16));
171
172 return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
173}
174
175unsigned X86TargetLowering::getVectorTypeBreakdownForCallingConv(
176 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
177 unsigned &NumIntermediates, MVT &RegisterVT) const {
178 // Break wide or odd vXi1 vectors into scalars to match avx2 behavior.
179 if (VT.isVectorOf(EltVT: MVT::i1) && Subtarget.hasAVX512() &&
180 (!isPowerOf2_32(Value: VT.getVectorNumElements()) ||
181 (VT.getVectorNumElements() == 64 && !Subtarget.hasBWI()) ||
182 VT.getVectorNumElements() > 64)) {
183 RegisterVT = MVT::i8;
184 IntermediateVT = MVT::i1;
185 NumIntermediates = VT.getVectorNumElements();
186 return NumIntermediates;
187 }
188
189 // Split v64i1 vectors if we don't have v64i8 available.
190 if (VT == MVT::v64i1 && Subtarget.hasBWI() && !Subtarget.useAVX512Regs() &&
191 CC != CallingConv::X86_RegCall) {
192 RegisterVT = MVT::v32i8;
193 IntermediateVT = MVT::v32i1;
194 NumIntermediates = 2;
195 return 2;
196 }
197
198 // Split vNbf16 vectors according to vNf16.
199 if (VT.isVectorOf(EltVT: MVT::bf16) && isTypeLegal(VT: MVT::f16))
200 VT = VT.changeVectorElementType(Context, EltVT: MVT::f16);
201
202 return TargetLowering::getVectorTypeBreakdownForCallingConv(Context, CC, VT, IntermediateVT,
203 NumIntermediates, RegisterVT);
204}
205
206EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL,
207 LLVMContext& Context,
208 EVT VT) const {
209 if (!VT.isVector())
210 return MVT::i8;
211
212 if (Subtarget.hasAVX512()) {
213 // Figure out what this type will be legalized to.
214 EVT LegalVT = VT;
215 while (getTypeAction(Context, VT: LegalVT) != TypeLegal)
216 LegalVT = getTypeToTransformTo(Context, VT: LegalVT);
217
218 // If we got a 512-bit vector then we'll definitely have a vXi1 compare.
219 if (LegalVT.getSimpleVT().is512BitVector())
220 return EVT::getVectorVT(Context, VT: MVT::i1, EC: VT.getVectorElementCount());
221
222 if (LegalVT.getSimpleVT().isVector() && Subtarget.hasVLX()) {
223 // If we legalized to less than a 512-bit vector, then we will use a vXi1
224 // compare for vXi32/vXi64 for sure. If we have BWI we will also support
225 // vXi16/vXi8.
226 MVT EltVT = LegalVT.getSimpleVT().getVectorElementType();
227 if (Subtarget.hasBWI() || EltVT.getSizeInBits() >= 32)
228 return EVT::getVectorVT(Context, VT: MVT::i1, EC: VT.getVectorElementCount());
229 }
230 }
231
232 return VT.changeVectorElementTypeToInteger();
233}
234
235bool X86TargetLowering::functionArgumentNeedsConsecutiveRegisters(
236 Type *Ty, CallingConv::ID CallConv, bool isVarArg,
237 const DataLayout &DL) const {
238 // On x86-64 i128 is split into two i64s and needs to be allocated to two
239 // consecutive registers, or spilled to the stack as a whole. On x86-32 i128
240 // is split to four i32s and never actually passed in registers, but we use
241 // the consecutive register mark to match it in TableGen.
242 if (Ty->isIntegerTy(BitWidth: 128))
243 return true;
244
245 // On x86-32, fp128 acts the same as i128.
246 if (Subtarget.is32Bit() && Ty->isFP128Ty())
247 return true;
248
249 return false;
250}
251
252/// Helper for getByValTypeAlignment to determine
253/// the desired ByVal argument alignment.
254static void getMaxByValAlign(Type *Ty, Align &MaxAlign) {
255 if (MaxAlign == 16)
256 return;
257 if (VectorType *VTy = dyn_cast<VectorType>(Val: Ty)) {
258 if (VTy->getPrimitiveSizeInBits().getFixedValue() == 128)
259 MaxAlign = Align(16);
260 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Val: Ty)) {
261 Align EltAlign;
262 getMaxByValAlign(Ty: ATy->getElementType(), MaxAlign&: EltAlign);
263 if (EltAlign > MaxAlign)
264 MaxAlign = EltAlign;
265 } else if (StructType *STy = dyn_cast<StructType>(Val: Ty)) {
266 for (auto *EltTy : STy->elements()) {
267 Align EltAlign;
268 getMaxByValAlign(Ty: EltTy, MaxAlign&: EltAlign);
269 if (EltAlign > MaxAlign)
270 MaxAlign = EltAlign;
271 if (MaxAlign == 16)
272 break;
273 }
274 }
275}
276
277/// Return the desired alignment for ByVal aggregate
278/// function arguments in the caller parameter area. For X86, aggregates
279/// that contain SSE vectors are placed at 16-byte boundaries while the rest
280/// are at 4-byte boundaries.
281Align X86TargetLowering::getByValTypeAlignment(Type *Ty,
282 const DataLayout &DL) const {
283 if (Subtarget.is64Bit())
284 return std::max(a: DL.getABITypeAlign(Ty), b: Align::Constant<8>());
285
286 Align Alignment(4);
287 if (Subtarget.hasSSE1())
288 getMaxByValAlign(Ty, MaxAlign&: Alignment);
289 return Alignment;
290}
291
292/// It returns EVT::Other if the type should be determined using generic
293/// target-independent logic.
294/// For vector ops we check that the overall size isn't larger than our
295/// preferred vector width.
296EVT X86TargetLowering::getOptimalMemOpType(
297 LLVMContext &Context, const MemOp &Op,
298 const AttributeList &FuncAttributes) const {
299 if (!FuncAttributes.hasFnAttr(Kind: Attribute::NoImplicitFloat)) {
300 if (Op.size() >= 16 &&
301 (!Subtarget.isUnalignedMem16Slow() || Op.isAligned(AlignCheck: Align(16)))) {
302 // FIXME: Check if unaligned 64-byte accesses are slow.
303 if (Op.size() >= 64 && Subtarget.hasAVX512() &&
304 (Subtarget.getPreferVectorWidth() >= 512)) {
305 return Subtarget.hasBWI() ? MVT::v64i8 : MVT::v16i32;
306 }
307 // FIXME: Check if unaligned 32-byte accesses are slow.
308 if (Op.size() >= 32 && Subtarget.hasAVX() &&
309 Subtarget.useLight256BitInstructions()) {
310 // Although this isn't a well-supported type for AVX1, we'll let
311 // legalization and shuffle lowering produce the optimal codegen. If we
312 // choose an optimal type with a vector element larger than a byte,
313 // getMemsetStores() may create an intermediate splat (using an integer
314 // multiply) before we splat as a vector.
315 return MVT::v32i8;
316 }
317 if (Subtarget.hasSSE2() && (Subtarget.getPreferVectorWidth() >= 128))
318 return MVT::v16i8;
319 // TODO: Can SSE1 handle a byte vector?
320 // If we have SSE1 registers we should be able to use them.
321 if (Subtarget.hasSSE1() && (Subtarget.is64Bit() || Subtarget.hasX87()) &&
322 (Subtarget.getPreferVectorWidth() >= 128))
323 return MVT::v4f32;
324 } else if (((Op.isMemcpyOrMemmove() && !Op.isMemcpyStrSrc()) ||
325 Op.isZeroMemset()) &&
326 Op.size() >= 8 && !Subtarget.is64Bit() && Subtarget.hasSSE2()) {
327 // Do not use f64 to lower memcpy if source is string constant. It's
328 // better to use i32 to avoid the loads.
329 // Also, do not use f64 to lower memset unless this is a memset of zeros.
330 // The gymnastics of splatting a byte value into an XMM register and then
331 // only using 8-byte stores (because this is a CPU with slow unaligned
332 // 16-byte accesses) makes that a loser.
333 return MVT::f64;
334 }
335 }
336 // This is a compromise. If we reach here, unaligned accesses may be slow on
337 // this target. However, creating smaller, aligned accesses could be even
338 // slower and would certainly be a lot more code.
339 if (Subtarget.is64Bit() && Op.size() >= 8)
340 return MVT::i64;
341 return MVT::i32;
342}
343
344bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
345 if (VT == MVT::f32)
346 return Subtarget.hasSSE1();
347 if (VT == MVT::f64)
348 return Subtarget.hasSSE2();
349 return true;
350}
351
352static bool isBitAligned(Align Alignment, uint64_t SizeInBits) {
353 return (8 * Alignment.value()) % SizeInBits == 0;
354}
355
356bool X86TargetLowering::isMemoryAccessFast(EVT VT, Align Alignment) const {
357 if (isBitAligned(Alignment, SizeInBits: VT.getSizeInBits()))
358 return true;
359 switch (VT.getSizeInBits()) {
360 default:
361 // 8-byte and under are always assumed to be fast.
362 return true;
363 case 128:
364 return !Subtarget.isUnalignedMem16Slow();
365 case 256:
366 return !Subtarget.isUnalignedMem32Slow();
367 // TODO: What about AVX-512 (512-bit) accesses?
368 }
369}
370
371bool X86TargetLowering::allowsMisalignedMemoryAccesses(
372 EVT VT, unsigned, Align Alignment, MachineMemOperand::Flags Flags,
373 unsigned *Fast) const {
374 if (Fast)
375 *Fast = isMemoryAccessFast(VT, Alignment);
376 // NonTemporal vector memory ops must be aligned.
377 if (!!(Flags & MachineMemOperand::MONonTemporal) && VT.isVector()) {
378 // NT loads can only be vector aligned, so if its less aligned than the
379 // minimum vector size (which we can split the vector down to), we might as
380 // well use a regular unaligned vector load.
381 // We don't have any NT loads pre-SSE41.
382 if (!!(Flags & MachineMemOperand::MOLoad))
383 return (Alignment < 16 || !Subtarget.hasSSE41());
384 return false;
385 }
386 // Misaligned accesses of any size are always allowed.
387 return true;
388}
389
390bool X86TargetLowering::allowsMemoryAccess(LLVMContext &Context,
391 const DataLayout &DL, EVT VT,
392 unsigned AddrSpace, Align Alignment,
393 MachineMemOperand::Flags Flags,
394 unsigned *Fast) const {
395 if (Fast)
396 *Fast = isMemoryAccessFast(VT, Alignment);
397 if (!!(Flags & MachineMemOperand::MONonTemporal) && VT.isVector()) {
398 if (allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags,
399 /*Fast=*/nullptr))
400 return true;
401 // NonTemporal vector memory ops are special, and must be aligned.
402 if (!isBitAligned(Alignment, SizeInBits: VT.getSizeInBits()))
403 return false;
404 switch (VT.getSizeInBits()) {
405 case 128:
406 if (!!(Flags & MachineMemOperand::MOLoad) && Subtarget.hasSSE41())
407 return true;
408 if (!!(Flags & MachineMemOperand::MOStore) && Subtarget.hasSSE2())
409 return true;
410 return false;
411 case 256:
412 if (!!(Flags & MachineMemOperand::MOLoad) && Subtarget.hasAVX2())
413 return true;
414 if (!!(Flags & MachineMemOperand::MOStore) && Subtarget.hasAVX())
415 return true;
416 return false;
417 case 512:
418 if (Subtarget.hasAVX512())
419 return true;
420 return false;
421 default:
422 return false; // Don't have NonTemporal vector memory ops of this size.
423 }
424 }
425 return true;
426}
427
428/// Return the entry encoding for a jump table in the
429/// current function. The returned value is a member of the
430/// MachineJumpTableInfo::JTEntryKind enum.
431unsigned X86TargetLowering::getJumpTableEncoding() const {
432 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
433 // symbol.
434 if (isPositionIndependent() && Subtarget.isPICStyleGOT())
435 return MachineJumpTableInfo::EK_Custom32;
436 if (isPositionIndependent() &&
437 getTargetMachine().getCodeModel() == CodeModel::Large &&
438 !Subtarget.isTargetCOFF())
439 return MachineJumpTableInfo::EK_LabelDifference64;
440
441 // Otherwise, use the normal jump table encoding heuristics.
442 return TargetLowering::getJumpTableEncoding();
443}
444
445bool X86TargetLowering::useSoftFloat() const {
446 return Subtarget.useSoftFloat();
447}
448
449void X86TargetLowering::markLibCallAttributes(MachineFunction *MF, unsigned CC,
450 ArgListTy &Args) const {
451
452 // Only relabel X86-32 for C / Stdcall CCs.
453 if (Subtarget.is64Bit())
454 return;
455 if (CC != CallingConv::C && CC != CallingConv::X86_StdCall)
456 return;
457 unsigned ParamRegs = 0;
458 if (auto *M = MF->getFunction().getParent())
459 ParamRegs = M->getNumberRegisterParameters();
460
461 // Mark the first N int arguments as having reg
462 for (auto &Arg : Args) {
463 Type *T = Arg.Ty;
464 if (T->isIntOrPtrTy())
465 if (MF->getDataLayout().getTypeAllocSize(Ty: T) <= 8) {
466 unsigned numRegs = 1;
467 if (MF->getDataLayout().getTypeAllocSize(Ty: T) > 4)
468 numRegs = 2;
469 if (ParamRegs < numRegs)
470 return;
471 ParamRegs -= numRegs;
472 Arg.IsInReg = true;
473 }
474 }
475}
476
477const MCExpr *
478X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
479 const MachineBasicBlock *MBB,
480 unsigned uid,MCContext &Ctx) const{
481 assert(isPositionIndependent() && Subtarget.isPICStyleGOT());
482 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
483 // entries.
484 return MCSymbolRefExpr::create(Symbol: MBB->getSymbol(), specifier: X86::S_GOTOFF, Ctx);
485}
486
487/// Returns relocation base for the given PIC jumptable.
488SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
489 SelectionDAG &DAG) const {
490 if (!Subtarget.is64Bit())
491 // This doesn't have SDLoc associated with it, but is not really the
492 // same as a Register.
493 return DAG.getNode(Opcode: X86ISD::GlobalBaseReg, DL: SDLoc(),
494 VT: getPointerTy(DL: DAG.getDataLayout()));
495 return Table;
496}
497
498/// This returns the relocation base for the given PIC jumptable,
499/// the same as getPICJumpTableRelocBase, but as an MCExpr.
500const MCExpr *X86TargetLowering::
501getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
502 MCContext &Ctx) const {
503 // X86-64 uses RIP relative addressing based on the jump table label.
504 if (Subtarget.isPICStyleRIPRel() ||
505 (Subtarget.is64Bit() &&
506 getTargetMachine().getCodeModel() == CodeModel::Large))
507 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
508
509 // Otherwise, the reference is relative to the PIC base.
510 return MCSymbolRefExpr::create(Symbol: MF->getPICBaseSymbol(), Ctx);
511}
512
513std::pair<const TargetRegisterClass *, uint8_t>
514X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
515 MVT VT) const {
516 const TargetRegisterClass *RRC = nullptr;
517 uint8_t Cost = 1;
518 switch (VT.SimpleTy) {
519 default:
520 return TargetLowering::findRepresentativeClass(TRI, VT);
521 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
522 RRC = Subtarget.is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
523 break;
524 case MVT::x86mmx:
525 RRC = &X86::VR64RegClass;
526 break;
527 case MVT::f32: case MVT::f64:
528 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
529 case MVT::v4f32: case MVT::v2f64:
530 case MVT::v32i8: case MVT::v16i16: case MVT::v8i32: case MVT::v4i64:
531 case MVT::v8f32: case MVT::v4f64:
532 case MVT::v64i8: case MVT::v32i16: case MVT::v16i32: case MVT::v8i64:
533 case MVT::v16f32: case MVT::v8f64:
534 RRC = &X86::VR128XRegClass;
535 break;
536 }
537 return std::make_pair(x&: RRC, y&: Cost);
538}
539
540unsigned X86TargetLowering::getAddressSpace() const {
541 if (Subtarget.is64Bit())
542 return (getTargetMachine().getCodeModel() == CodeModel::Kernel) ? X86AS::GS
543 : X86AS::FS;
544 return X86AS::GS;
545}
546
547static bool hasStackGuardSlotTLS(const Triple &TargetTriple) {
548 return TargetTriple.isOSGlibc() || TargetTriple.isMusl() ||
549 TargetTriple.isOSFuchsia() || TargetTriple.isAndroid();
550}
551
552static Constant* SegmentOffset(IRBuilderBase &IRB,
553 int Offset, unsigned AddressSpace) {
554 return ConstantExpr::getIntToPtr(
555 C: ConstantInt::getSigned(Ty: Type::getInt32Ty(C&: IRB.getContext()), V: Offset),
556 Ty: IRB.getPtrTy(AddrSpace: AddressSpace));
557}
558
559Value *
560X86TargetLowering::getIRStackGuard(IRBuilderBase &IRB,
561 const LibcallLoweringInfo &Libcalls) const {
562 // glibc, bionic, and Fuchsia have a special slot for the stack guard in
563 // tcbhead_t; use it instead of the usual global variable (see
564 // sysdeps/{i386,x86_64}/nptl/tls.h)
565 if (hasStackGuardSlotTLS(TargetTriple: Subtarget.getTargetTriple())) {
566 unsigned AddressSpace = getAddressSpace();
567
568 // <zircon/tls.h> defines ZX_TLS_STACK_GUARD_OFFSET with this value.
569 if (Subtarget.isTargetFuchsia())
570 return SegmentOffset(IRB, Offset: 0x10, AddressSpace);
571
572 Module *M = IRB.GetInsertBlock()->getParent()->getParent();
573 // Specially, some users may customize the base reg and offset.
574 int Offset = M->getStackProtectorGuardOffset();
575 // If we don't set -stack-protector-guard-offset value:
576 // %fs:0x28, unless we're using a Kernel code model, in which case
577 // it's %gs:0x28. gs:0x14 on i386.
578 if (Offset == INT_MAX)
579 Offset = (Subtarget.is64Bit()) ? 0x28 : 0x14;
580
581 StringRef GuardReg = M->getStackProtectorGuardReg();
582 if (GuardReg == "fs")
583 AddressSpace = X86AS::FS;
584 else if (GuardReg == "gs")
585 AddressSpace = X86AS::GS;
586
587 // Use symbol guard if user specify.
588 StringRef GuardSymb = M->getStackProtectorGuardSymbol();
589 if (!GuardSymb.empty()) {
590 GlobalVariable *GV = M->getGlobalVariable(Name: GuardSymb);
591 if (!GV) {
592 Type *Ty = Subtarget.is64Bit() ? Type::getInt64Ty(C&: M->getContext())
593 : Type::getInt32Ty(C&: M->getContext());
594 GV = new GlobalVariable(*M, Ty, false, GlobalValue::ExternalLinkage,
595 nullptr, GuardSymb, nullptr,
596 GlobalValue::NotThreadLocal, AddressSpace);
597 if (!Subtarget.isTargetDarwin())
598 GV->setDSOLocal(M->getDirectAccessExternalData());
599 }
600 return GV;
601 }
602
603 return SegmentOffset(IRB, Offset, AddressSpace);
604 }
605 return TargetLowering::getIRStackGuard(IRB, Libcalls);
606}
607
608void X86TargetLowering::insertSSPDeclarations(
609 Module &M, const LibcallLoweringInfo &Libcalls) const {
610 // MSVC CRT provides functionalities for stack protection.
611 RTLIB::LibcallImpl SecurityCheckCookieLibcall =
612 Libcalls.getLibcallImpl(Call: RTLIB::SECURITY_CHECK_COOKIE);
613
614 RTLIB::LibcallImpl SecurityCookieVar =
615 Libcalls.getLibcallImpl(Call: RTLIB::STACK_CHECK_GUARD);
616 if (SecurityCheckCookieLibcall != RTLIB::Unsupported &&
617 SecurityCookieVar != RTLIB::Unsupported) {
618 // MSVC CRT provides functionalities for stack protection.
619 // MSVC CRT has a global variable holding security cookie.
620 M.getOrInsertGlobal(Name: getLibcallImplName(Call: SecurityCookieVar),
621 Ty: PointerType::getUnqual(C&: M.getContext()));
622
623 // MSVC CRT has a function to validate security cookie.
624 FunctionCallee SecurityCheckCookie =
625 M.getOrInsertFunction(Name: getLibcallImplName(Call: SecurityCheckCookieLibcall),
626 RetTy: Type::getVoidTy(C&: M.getContext()),
627 Args: PointerType::getUnqual(C&: M.getContext()));
628
629 if (Function *F = dyn_cast<Function>(Val: SecurityCheckCookie.getCallee())) {
630 F->setCallingConv(CallingConv::X86_FastCall);
631 F->addParamAttr(ArgNo: 0, Kind: Attribute::AttrKind::InReg);
632 }
633 return;
634 }
635
636 StringRef GuardMode = M.getStackProtectorGuard();
637
638 // glibc, bionic, and Fuchsia have a special slot for the stack guard.
639 if ((GuardMode == "tls" || GuardMode.empty()) &&
640 hasStackGuardSlotTLS(TargetTriple: Subtarget.getTargetTriple()))
641 return;
642 TargetLowering::insertSSPDeclarations(M, Libcalls);
643}
644
645Value *X86TargetLowering::getSafeStackPointerLocation(
646 IRBuilderBase &IRB, const LibcallLoweringInfo &Libcalls) const {
647 // Android provides a fixed TLS slot for the SafeStack pointer. See the
648 // definition of TLS_SLOT_SAFESTACK in
649 // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
650 if (Subtarget.isTargetAndroid()) {
651 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
652 // %gs:0x24 on i386
653 int Offset = (Subtarget.is64Bit()) ? 0x48 : 0x24;
654 return SegmentOffset(IRB, Offset, AddressSpace: getAddressSpace());
655 }
656
657 // Fuchsia is similar.
658 if (Subtarget.isTargetFuchsia()) {
659 // <zircon/tls.h> defines ZX_TLS_UNSAFE_SP_OFFSET with this value.
660 return SegmentOffset(IRB, Offset: 0x18, AddressSpace: getAddressSpace());
661 }
662
663 return TargetLowering::getSafeStackPointerLocation(IRB, Libcalls);
664}
665
666//===----------------------------------------------------------------------===//
667// Return Value Calling Convention Implementation
668//===----------------------------------------------------------------------===//
669
670bool X86TargetLowering::CanLowerReturn(
671 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
672 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context,
673 const Type *RetTy) const {
674 // Mingw64 GCC returns f128 via sret, and LLVM matches it for compatibility.
675 // This logic exists for libcalls, a frontend should explicitly use sret
676 // rather than rely on the sret demotion here.
677 //
678 // Using sret is a reasonable implementation of the Windows x64 calling
679 // convention:
680 //
681 // https://learn.microsoft.com/en-us/cpp/build/x64-calling-convention?view=msvc-170#return-values
682 //
683 // > Otherwise, the caller must allocate memory for the return value and pass
684 // > a pointer to it as the first argument.
685 //
686 // Although it is not the only reasonable interpretation:
687 //
688 // > Nonscalar types including floats, doubles, and vector types such as
689 // > __m128, __m128i, __m128d are returned in XMM0.
690 //
691 // For now, we prefer compatibility with GCC. If official guidelines are ever
692 // published, this can be revisited.
693 //
694 // Return false, which will perform sret demotion.
695 auto IsWin64F128StackCC = [this](CallingConv::ID CC) -> bool {
696 switch (CC) {
697 case CallingConv::Win64:
698 return true;
699 case CallingConv::C:
700 return Subtarget.isOSWindowsOrUEFI();
701 default:
702 return false;
703 }
704 };
705
706 if (IsWin64F128StackCC(CallConv) &&
707 llvm::any_of(
708 Range: Outs, P: [](const ISD::OutputArg &Out) { return Out.VT == MVT::f128; }))
709 return false;
710
711 SmallVector<CCValAssign, 16> RVLocs;
712 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
713 return CCInfo.CheckReturn(Outs, Fn: RetCC_X86);
714}
715
716const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
717 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
718 return ScratchRegs;
719}
720
721ArrayRef<MCPhysReg> X86TargetLowering::getRoundingControlRegisters() const {
722 static const MCPhysReg RCRegs[] = {X86::FPCW, X86::MXCSR};
723 return RCRegs;
724}
725
726/// Lowers masks values (v*i1) to the local register values
727/// \returns DAG node after lowering to register type
728static SDValue lowerMasksToReg(const SDValue &ValArg, const EVT &ValLoc,
729 const SDLoc &DL, SelectionDAG &DAG) {
730 EVT ValVT = ValArg.getValueType();
731
732 if (ValVT == MVT::v1i1)
733 return DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: ValLoc, N1: ValArg,
734 N2: DAG.getIntPtrConstant(Val: 0, DL));
735
736 if ((ValVT == MVT::v8i1 && (ValLoc == MVT::i8 || ValLoc == MVT::i32)) ||
737 (ValVT == MVT::v16i1 && (ValLoc == MVT::i16 || ValLoc == MVT::i32))) {
738 // Two stage lowering might be required
739 // bitcast: v8i1 -> i8 / v16i1 -> i16
740 // anyextend: i8 -> i32 / i16 -> i32
741 EVT TempValLoc = ValVT == MVT::v8i1 ? MVT::i8 : MVT::i16;
742 SDValue ValToCopy = DAG.getBitcast(VT: TempValLoc, V: ValArg);
743 if (ValLoc == MVT::i32)
744 ValToCopy = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: ValLoc, Operand: ValToCopy);
745 return ValToCopy;
746 }
747
748 if ((ValVT == MVT::v32i1 && ValLoc == MVT::i32) ||
749 (ValVT == MVT::v64i1 && ValLoc == MVT::i64)) {
750 // One stage lowering is required
751 // bitcast: v32i1 -> i32 / v64i1 -> i64
752 return DAG.getBitcast(VT: ValLoc, V: ValArg);
753 }
754
755 return DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: ValLoc, Operand: ValArg);
756}
757
758/// Breaks v64i1 value into two registers and adds the new node to the DAG
759static void Passv64i1ArgInRegs(
760 const SDLoc &DL, SelectionDAG &DAG, SDValue &Arg,
761 SmallVectorImpl<std::pair<Register, SDValue>> &RegsToPass, CCValAssign &VA,
762 CCValAssign &NextVA, const X86Subtarget &Subtarget) {
763 assert(Subtarget.hasBWI() && "Expected AVX512BW target!");
764 assert(Subtarget.is32Bit() && "Expecting 32 bit target");
765 assert(Arg.getValueType() == MVT::i64 && "Expecting 64 bit value");
766 assert(VA.isRegLoc() && NextVA.isRegLoc() &&
767 "The value should reside in two registers");
768
769 // Before splitting the value we cast it to i64
770 Arg = DAG.getBitcast(VT: MVT::i64, V: Arg);
771
772 // Splitting the value into two i32 types
773 SDValue Lo, Hi;
774 std::tie(args&: Lo, args&: Hi) = DAG.SplitScalar(N: Arg, DL, LoVT: MVT::i32, HiVT: MVT::i32);
775
776 // Attach the two i32 types into corresponding registers
777 RegsToPass.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: Lo));
778 RegsToPass.push_back(Elt: std::make_pair(x: NextVA.getLocReg(), y&: Hi));
779}
780
781SDValue
782X86TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
783 bool isVarArg,
784 const SmallVectorImpl<ISD::OutputArg> &Outs,
785 const SmallVectorImpl<SDValue> &OutVals,
786 const SDLoc &dl, SelectionDAG &DAG) const {
787 MachineFunction &MF = DAG.getMachineFunction();
788 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
789
790 // In some cases we need to disable registers from the default CSR list.
791 // For example, when they are used as return registers (preserve_* and X86's
792 // regcall) or for argument passing (X86's regcall).
793 bool ShouldDisableCalleeSavedRegister =
794 shouldDisableRetRegFromCSR(CC: CallConv) ||
795 MF.getFunction().hasFnAttribute(Kind: "no_caller_saved_registers");
796
797 if (CallConv == CallingConv::X86_INTR && !Outs.empty())
798 report_fatal_error(reason: "X86 interrupts may not return any value");
799
800 SmallVector<CCValAssign, 16> RVLocs;
801 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
802 CCInfo.AnalyzeReturn(Outs, Fn: RetCC_X86);
803
804 SmallVector<std::pair<Register, SDValue>, 4> RetVals;
805 for (unsigned I = 0, OutsIndex = 0, E = RVLocs.size(); I != E;
806 ++I, ++OutsIndex) {
807 CCValAssign &VA = RVLocs[I];
808 assert(VA.isRegLoc() && "Can only return in registers!");
809
810 // Add the register to the CalleeSaveDisableRegs list.
811 if (ShouldDisableCalleeSavedRegister)
812 MF.getRegInfo().disableCalleeSavedRegister(Reg: VA.getLocReg());
813
814 SDValue ValToCopy = OutVals[OutsIndex];
815 EVT ValVT = ValToCopy.getValueType();
816
817 // Promote values to the appropriate types.
818 if (VA.getLocInfo() == CCValAssign::SExt)
819 ValToCopy = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL: dl, VT: VA.getLocVT(), Operand: ValToCopy);
820 else if (VA.getLocInfo() == CCValAssign::ZExt)
821 ValToCopy = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: VA.getLocVT(), Operand: ValToCopy);
822 else if (VA.getLocInfo() == CCValAssign::AExt) {
823 if (ValVT.isVectorOf(EltVT: MVT::i1))
824 ValToCopy = lowerMasksToReg(ValArg: ValToCopy, ValLoc: VA.getLocVT(), DL: dl, DAG);
825 else
826 ValToCopy = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: VA.getLocVT(), Operand: ValToCopy);
827 }
828 else if (VA.getLocInfo() == CCValAssign::BCvt)
829 ValToCopy = DAG.getBitcast(VT: VA.getLocVT(), V: ValToCopy);
830
831 assert(VA.getLocInfo() != CCValAssign::FPExt &&
832 "Unexpected FP-extend for return value.");
833
834 // Report an error if we have attempted to return a value via an XMM
835 // register and SSE was disabled.
836 if (!Subtarget.hasSSE1() && X86::FR32XRegClass.contains(Reg: VA.getLocReg())) {
837 errorUnsupported(DAG, dl, Msg: "SSE register return with SSE disabled");
838 VA.convertToReg(Reg: X86::FP0); // Set reg to FP0, avoid hitting asserts.
839 } else if (!Subtarget.hasSSE2() &&
840 X86::FR64XRegClass.contains(Reg: VA.getLocReg()) &&
841 ValVT == MVT::f64) {
842 // When returning a double via an XMM register, report an error if SSE2 is
843 // not enabled.
844 errorUnsupported(DAG, dl, Msg: "SSE2 register return with SSE2 disabled");
845 VA.convertToReg(Reg: X86::FP0); // Set reg to FP0, avoid hitting asserts.
846 }
847
848 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
849 // the RET instruction and handled by the FP Stackifier.
850 if (VA.getLocReg() == X86::FP0 ||
851 VA.getLocReg() == X86::FP1) {
852 // If this is a copy from an xmm register to ST(0), use an FPExtend to
853 // change the value to the FP stack register class.
854 if (isScalarFPTypeInSSEReg(VT: VA.getValVT()))
855 ValToCopy = DAG.getNode(Opcode: ISD::FP_EXTEND, DL: dl, VT: MVT::f80, Operand: ValToCopy);
856 RetVals.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: ValToCopy));
857 // Don't emit a copytoreg.
858 continue;
859 }
860
861 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
862 // which is returned in RAX / RDX.
863 if (Subtarget.is64Bit()) {
864 if (ValVT == MVT::x86mmx) {
865 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
866 ValToCopy = DAG.getBitcast(VT: MVT::i64, V: ValToCopy);
867 ValToCopy = DAG.getNode(Opcode: ISD::SCALAR_TO_VECTOR, DL: dl, VT: MVT::v2i64,
868 Operand: ValToCopy);
869 // If we don't have SSE2 available, convert to v4f32 so the generated
870 // register is legal.
871 if (!Subtarget.hasSSE2())
872 ValToCopy = DAG.getBitcast(VT: MVT::v4f32, V: ValToCopy);
873 }
874 }
875 }
876
877 if (VA.needsCustom()) {
878 assert(VA.getValVT() == MVT::v64i1 &&
879 "Currently the only custom case is when we split v64i1 to 2 regs");
880
881 Passv64i1ArgInRegs(DL: dl, DAG, Arg&: ValToCopy, RegsToPass&: RetVals, VA, NextVA&: RVLocs[++I],
882 Subtarget);
883
884 // Add the second register to the CalleeSaveDisableRegs list.
885 if (ShouldDisableCalleeSavedRegister)
886 MF.getRegInfo().disableCalleeSavedRegister(Reg: RVLocs[I].getLocReg());
887 } else {
888 RetVals.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: ValToCopy));
889 }
890 }
891
892 SDValue Glue;
893 SmallVector<SDValue, 6> RetOps;
894 RetOps.push_back(Elt: Chain); // Operand #0 = Chain (updated below)
895 // Operand #1 = Bytes To Pop
896 RetOps.push_back(Elt: DAG.getTargetConstant(Val: FuncInfo->getBytesToPopOnReturn(), DL: dl,
897 VT: MVT::i32));
898
899 // Copy the result values into the output registers.
900 for (auto &RetVal : RetVals) {
901 if (RetVal.first == X86::FP0 || RetVal.first == X86::FP1) {
902 RetOps.push_back(Elt: RetVal.second);
903 continue; // Don't emit a copytoreg.
904 }
905
906 Chain = DAG.getCopyToReg(Chain, dl, Reg: RetVal.first, N: RetVal.second, Glue);
907 Glue = Chain.getValue(R: 1);
908 RetOps.push_back(
909 Elt: DAG.getRegister(Reg: RetVal.first, VT: RetVal.second.getValueType()));
910 }
911
912 // Swift calling convention does not require we copy the sret argument
913 // into %rax/%eax for the return, and SRetReturnReg is not set for Swift.
914
915 // All x86 ABIs require that for returning structs by value we copy
916 // the sret argument into %rax/%eax (depending on ABI) for the return.
917 // We saved the argument into a virtual register in the entry block,
918 // so now we copy the value out and into %rax/%eax.
919 //
920 // Checking Function.hasStructRetAttr() here is insufficient because the IR
921 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
922 // false, then an sret argument may be implicitly inserted in the SelDAG. In
923 // either case FuncInfo->setSRetReturnReg() will have been called.
924 if (Register SRetReg = FuncInfo->getSRetReturnReg()) {
925 // When we have both sret and another return value, we should use the
926 // original Chain stored in RetOps[0], instead of the current Chain updated
927 // in the above loop. If we only have sret, RetOps[0] equals to Chain.
928
929 // For the case of sret and another return value, we have
930 // Chain_0 at the function entry
931 // Chain_1 = getCopyToReg(Chain_0) in the above loop
932 // If we use Chain_1 in getCopyFromReg, we will have
933 // Val = getCopyFromReg(Chain_1)
934 // Chain_2 = getCopyToReg(Chain_1, Val) from below
935
936 // getCopyToReg(Chain_0) will be glued together with
937 // getCopyToReg(Chain_1, Val) into Unit A, getCopyFromReg(Chain_1) will be
938 // in Unit B, and we will have cyclic dependency between Unit A and Unit B:
939 // Data dependency from Unit B to Unit A due to usage of Val in
940 // getCopyToReg(Chain_1, Val)
941 // Chain dependency from Unit A to Unit B
942
943 // So here, we use RetOps[0] (i.e Chain_0) for getCopyFromReg.
944 SDValue Val = DAG.getCopyFromReg(Chain: RetOps[0], dl, Reg: SRetReg,
945 VT: getPointerTy(DL: MF.getDataLayout()));
946
947 Register RetValReg
948 = (Subtarget.is64Bit() && !Subtarget.isTarget64BitILP32()) ?
949 X86::RAX : X86::EAX;
950 Chain = DAG.getCopyToReg(Chain, dl, Reg: RetValReg, N: Val, Glue);
951 Glue = Chain.getValue(R: 1);
952
953 // RAX/EAX now acts like a return value.
954 RetOps.push_back(
955 Elt: DAG.getRegister(Reg: RetValReg, VT: getPointerTy(DL: DAG.getDataLayout())));
956
957 // Add the returned register to the CalleeSaveDisableRegs list. Don't do
958 // this however for preserve_most/preserve_all to minimize the number of
959 // callee-saved registers for these CCs.
960 if (ShouldDisableCalleeSavedRegister &&
961 CallConv != CallingConv::PreserveAll &&
962 CallConv != CallingConv::PreserveMost)
963 MF.getRegInfo().disableCalleeSavedRegister(Reg: RetValReg);
964 }
965
966 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
967 const MCPhysReg *I =
968 TRI->getCalleeSavedRegsViaCopy(MF: &DAG.getMachineFunction());
969 if (I) {
970 for (; *I; ++I) {
971 if (X86::GR64RegClass.contains(Reg: *I))
972 RetOps.push_back(Elt: DAG.getRegister(Reg: *I, VT: MVT::i64));
973 else
974 llvm_unreachable("Unexpected register class in CSRsViaCopy!");
975 }
976 }
977
978 RetOps[0] = Chain; // Update chain.
979
980 // Add the glue if we have it.
981 if (Glue.getNode())
982 RetOps.push_back(Elt: Glue);
983
984 unsigned RetOpcode = X86ISD::RET_GLUE;
985 if (CallConv == CallingConv::X86_INTR)
986 RetOpcode = X86ISD::IRET;
987 return DAG.getNode(Opcode: RetOpcode, DL: dl, VT: MVT::Other, Ops: RetOps);
988}
989
990bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
991 if (N->getNumValues() != 1 || !N->hasNUsesOfValue(NUses: 1, Value: 0))
992 return false;
993
994 SDValue TCChain = Chain;
995 SDNode *Copy = *N->user_begin();
996 if (Copy->getOpcode() == ISD::CopyToReg) {
997 // If the copy has a glue operand, we conservatively assume it isn't safe to
998 // perform a tail call.
999 if (Copy->getOperand(Num: Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1000 return false;
1001 TCChain = Copy->getOperand(Num: 0);
1002 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1003 return false;
1004
1005 bool HasRet = false;
1006 for (const SDNode *U : Copy->users()) {
1007 if (U->getOpcode() != X86ISD::RET_GLUE)
1008 return false;
1009 // If we are returning more than one value, we can definitely
1010 // not make a tail call see PR19530
1011 if (U->getNumOperands() > 4)
1012 return false;
1013 if (U->getNumOperands() == 4 &&
1014 U->getOperand(Num: U->getNumOperands() - 1).getValueType() != MVT::Glue)
1015 return false;
1016 HasRet = true;
1017 }
1018
1019 if (!HasRet)
1020 return false;
1021
1022 Chain = TCChain;
1023 return true;
1024}
1025
1026EVT X86TargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,
1027 ISD::NodeType ExtendKind) const {
1028 MVT ReturnMVT = MVT::i32;
1029
1030 bool Darwin = Subtarget.getTargetTriple().isOSDarwin();
1031 if (VT == MVT::i1 || (!Darwin && (VT == MVT::i8 || VT == MVT::i16))) {
1032 // The ABI does not require i1, i8 or i16 to be extended.
1033 //
1034 // On Darwin, there is code in the wild relying on Clang's old behaviour of
1035 // always extending i8/i16 return values, so keep doing that for now.
1036 // (PR26665).
1037 ReturnMVT = MVT::i8;
1038 }
1039
1040 EVT MinVT = getRegisterType(Context, VT: ReturnMVT);
1041 return VT.bitsLT(VT: MinVT) ? MinVT : VT;
1042}
1043
1044/// Reads two 32 bit registers and creates a 64 bit mask value.
1045/// \param VA The current 32 bit value that need to be assigned.
1046/// \param NextVA The next 32 bit value that need to be assigned.
1047/// \param Root The parent DAG node.
1048/// \param [in,out] InGlue Represents SDvalue in the parent DAG node for
1049/// glue purposes. In the case the DAG is already using
1050/// physical register instead of virtual, we should glue
1051/// our new SDValue to InGlue SDvalue.
1052/// \return a new SDvalue of size 64bit.
1053static SDValue getv64i1Argument(CCValAssign &VA, CCValAssign &NextVA,
1054 SDValue &Root, SelectionDAG &DAG,
1055 const SDLoc &DL, const X86Subtarget &Subtarget,
1056 SDValue *InGlue = nullptr) {
1057 assert((Subtarget.hasBWI()) && "Expected AVX512BW target!");
1058 assert(Subtarget.is32Bit() && "Expecting 32 bit target");
1059 assert(VA.getValVT() == MVT::v64i1 &&
1060 "Expecting first location of 64 bit width type");
1061 assert(NextVA.getValVT() == VA.getValVT() &&
1062 "The locations should have the same type");
1063 assert(VA.isRegLoc() && NextVA.isRegLoc() &&
1064 "The values should reside in two registers");
1065
1066 SDValue Lo, Hi;
1067 SDValue ArgValueLo, ArgValueHi;
1068
1069 MachineFunction &MF = DAG.getMachineFunction();
1070 const TargetRegisterClass *RC = &X86::GR32RegClass;
1071
1072 // Read a 32 bit value from the registers.
1073 if (nullptr == InGlue) {
1074 // When no physical register is present,
1075 // create an intermediate virtual register.
1076 Register Reg = MF.addLiveIn(PReg: VA.getLocReg(), RC);
1077 ArgValueLo = DAG.getCopyFromReg(Chain: Root, dl: DL, Reg, VT: MVT::i32);
1078 Reg = MF.addLiveIn(PReg: NextVA.getLocReg(), RC);
1079 ArgValueHi = DAG.getCopyFromReg(Chain: Root, dl: DL, Reg, VT: MVT::i32);
1080 } else {
1081 // When a physical register is available read the value from it and glue
1082 // the reads together.
1083 ArgValueLo =
1084 DAG.getCopyFromReg(Chain: Root, dl: DL, Reg: VA.getLocReg(), VT: MVT::i32, Glue: *InGlue);
1085 *InGlue = ArgValueLo.getValue(R: 2);
1086 ArgValueHi =
1087 DAG.getCopyFromReg(Chain: Root, dl: DL, Reg: NextVA.getLocReg(), VT: MVT::i32, Glue: *InGlue);
1088 *InGlue = ArgValueHi.getValue(R: 2);
1089 }
1090
1091 // Convert the i32 type into v32i1 type.
1092 Lo = DAG.getBitcast(VT: MVT::v32i1, V: ArgValueLo);
1093
1094 // Convert the i32 type into v32i1 type.
1095 Hi = DAG.getBitcast(VT: MVT::v32i1, V: ArgValueHi);
1096
1097 // Concatenate the two values together.
1098 return DAG.getNode(Opcode: ISD::CONCAT_VECTORS, DL, VT: MVT::v64i1, N1: Lo, N2: Hi);
1099}
1100
1101/// The function will lower a register of various sizes (8/16/32/64)
1102/// to a mask value of the expected size (v8i1/v16i1/v32i1/v64i1)
1103/// \returns a DAG node contains the operand after lowering to mask type.
1104static SDValue lowerRegToMasks(const SDValue &ValArg, const EVT &ValVT,
1105 const EVT &ValLoc, const SDLoc &DL,
1106 SelectionDAG &DAG) {
1107 SDValue ValReturned = ValArg;
1108
1109 if (ValVT == MVT::v1i1)
1110 return DAG.getNode(Opcode: ISD::SCALAR_TO_VECTOR, DL, VT: MVT::v1i1, Operand: ValReturned);
1111
1112 if (ValVT == MVT::v64i1) {
1113 // In 32 bit machine, this case is handled by getv64i1Argument
1114 assert(ValLoc == MVT::i64 && "Expecting only i64 locations");
1115 // In 64 bit machine, There is no need to truncate the value only bitcast
1116 } else {
1117 MVT MaskLenVT;
1118 switch (ValVT.getSimpleVT().SimpleTy) {
1119 case MVT::v8i1:
1120 MaskLenVT = MVT::i8;
1121 break;
1122 case MVT::v16i1:
1123 MaskLenVT = MVT::i16;
1124 break;
1125 case MVT::v32i1:
1126 MaskLenVT = MVT::i32;
1127 break;
1128 default:
1129 llvm_unreachable("Expecting a vector of i1 types");
1130 }
1131
1132 ValReturned = DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: MaskLenVT, Operand: ValReturned);
1133 }
1134 return DAG.getBitcast(VT: ValVT, V: ValReturned);
1135}
1136
1137static SDValue getPopFromX87Reg(SelectionDAG &DAG, SDValue Chain,
1138 const SDLoc &dl, Register Reg, EVT VT,
1139 SDValue Glue) {
1140 SDVTList VTs = DAG.getVTList(VT1: VT, VT2: MVT::Other, VT3: MVT::Glue);
1141 SDValue Ops[] = {Chain, DAG.getRegister(Reg, VT), Glue};
1142 return DAG.getNode(Opcode: X86ISD::POP_FROM_X87_REG, DL: dl, VTList: VTs,
1143 Ops: ArrayRef(Ops, Glue.getNode() ? 3 : 2));
1144}
1145
1146/// Lower the result values of a call into the
1147/// appropriate copies out of appropriate physical registers.
1148///
1149SDValue X86TargetLowering::LowerCallResult(
1150 SDValue Chain, SDValue InGlue, CallingConv::ID CallConv, bool isVarArg,
1151 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1152 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
1153 uint32_t *RegMask) const {
1154
1155 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1156 // Assign locations to each value returned by this call.
1157 SmallVector<CCValAssign, 16> RVLocs;
1158 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1159 *DAG.getContext());
1160 CCInfo.AnalyzeCallResult(Ins, Fn: RetCC_X86);
1161
1162 // Copy all of the result registers out of their specified physreg.
1163 for (unsigned I = 0, InsIndex = 0, E = RVLocs.size(); I != E;
1164 ++I, ++InsIndex) {
1165 CCValAssign &VA = RVLocs[I];
1166 EVT CopyVT = VA.getLocVT();
1167
1168 // In some calling conventions we need to remove the used registers
1169 // from the register mask.
1170 if (RegMask) {
1171 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg: VA.getLocReg()))
1172 RegMask[SubReg / 32] &= ~(1u << (SubReg % 32));
1173 }
1174
1175 // Report an error if there was an attempt to return FP values via XMM
1176 // registers.
1177 if (!Subtarget.hasSSE1() && X86::FR32XRegClass.contains(Reg: VA.getLocReg())) {
1178 errorUnsupported(DAG, dl, Msg: "SSE register return with SSE disabled");
1179 if (VA.getLocReg() == X86::XMM1)
1180 VA.convertToReg(Reg: X86::FP1); // Set reg to FP1, avoid hitting asserts.
1181 else
1182 VA.convertToReg(Reg: X86::FP0); // Set reg to FP0, avoid hitting asserts.
1183 } else if (!Subtarget.hasSSE2() &&
1184 X86::FR64XRegClass.contains(Reg: VA.getLocReg()) &&
1185 CopyVT == MVT::f64) {
1186 errorUnsupported(DAG, dl, Msg: "SSE2 register return with SSE2 disabled");
1187 if (VA.getLocReg() == X86::XMM1)
1188 VA.convertToReg(Reg: X86::FP1); // Set reg to FP1, avoid hitting asserts.
1189 else
1190 VA.convertToReg(Reg: X86::FP0); // Set reg to FP0, avoid hitting asserts.
1191 }
1192
1193 // If we prefer to use the value in xmm registers, copy it out as f80 and
1194 // use a truncate to move it from fp stack reg to xmm reg.
1195 bool RoundAfterCopy = false;
1196 bool X87Result = VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1;
1197 if (X87Result && isScalarFPTypeInSSEReg(VT: VA.getValVT())) {
1198 if (!Subtarget.hasX87())
1199 report_fatal_error(reason: "X87 register return with X87 disabled");
1200 CopyVT = MVT::f80;
1201 RoundAfterCopy = (CopyVT != VA.getLocVT());
1202 }
1203
1204 SDValue Val;
1205 if (VA.needsCustom()) {
1206 assert(VA.getValVT() == MVT::v64i1 &&
1207 "Currently the only custom case is when we split v64i1 to 2 regs");
1208 Val =
1209 getv64i1Argument(VA, NextVA&: RVLocs[++I], Root&: Chain, DAG, DL: dl, Subtarget, InGlue: &InGlue);
1210 } else {
1211 Chain =
1212 X87Result
1213 ? getPopFromX87Reg(DAG, Chain, dl, Reg: VA.getLocReg(), VT: CopyVT, Glue: InGlue)
1214 .getValue(R: 1)
1215 : DAG.getCopyFromReg(Chain, dl, Reg: VA.getLocReg(), VT: CopyVT, Glue: InGlue)
1216 .getValue(R: 1);
1217 Val = Chain.getValue(R: 0);
1218 InGlue = Chain.getValue(R: 2);
1219 }
1220
1221 if (RoundAfterCopy)
1222 Val = DAG.getNode(Opcode: ISD::FP_ROUND, DL: dl, VT: VA.getValVT(), N1: Val,
1223 // This truncation won't change the value.
1224 N2: DAG.getIntPtrConstant(Val: 1, DL: dl, /*isTarget=*/true));
1225
1226 if (VA.isExtInLoc()) {
1227 if (VA.getValVT().isVector() &&
1228 VA.getValVT().getScalarType() == MVT::i1 &&
1229 ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) ||
1230 (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) {
1231 // promoting a mask type (v*i1) into a register of type i64/i32/i16/i8
1232 Val = lowerRegToMasks(ValArg: Val, ValVT: VA.getValVT(), ValLoc: VA.getLocVT(), DL: dl, DAG);
1233 } else
1234 Val = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: VA.getValVT(), Operand: Val);
1235 }
1236
1237 if (VA.getLocInfo() == CCValAssign::BCvt)
1238 Val = DAG.getBitcast(VT: VA.getValVT(), V: Val);
1239
1240 InVals.push_back(Elt: Val);
1241 }
1242
1243 return Chain;
1244}
1245
1246/// Determines whether Args, either a set of outgoing arguments to a call, or a
1247/// set of incoming args of a call, contains an sret pointer that the callee
1248/// pops. This happens on most x86-32, System V platforms, unless register
1249/// parameters are in use (-mregparm=1+, regcallcc, etc).
1250template <typename T>
1251static bool hasCalleePopSRet(const SmallVectorImpl<T> &Args,
1252 const SmallVectorImpl<CCValAssign> &ArgLocs,
1253 const X86Subtarget &Subtarget) {
1254 // Not C++20 (yet), so no concepts available.
1255 static_assert(std::is_same_v<T, ISD::OutputArg> ||
1256 std::is_same_v<T, ISD::InputArg>,
1257 "requires ISD::OutputArg or ISD::InputArg");
1258
1259 // Popping the sret pointer only happens on x86-32 System V ABI platforms
1260 // (Linux, Cygwin, BSDs, Mac, etc). That excludes Windows-minus-Cygwin and
1261 // MCU.
1262 const Triple &TT = Subtarget.getTargetTriple();
1263 if (!TT.isX86_32() || TT.isOSMSVCRT() || TT.isOSIAMCU())
1264 return false;
1265
1266 // Check if the first argument is marked sret and if it is passed in memory.
1267 bool IsSRetInMem = false;
1268 if (!Args.empty())
1269 IsSRetInMem = Args.front().Flags.isSRet() && ArgLocs.front().isMemLoc();
1270 return IsSRetInMem;
1271}
1272
1273/// Make a copy of an aggregate at address specified by "Src" to address
1274/// "Dst" with size and alignment information specified by the specific
1275/// parameter attribute. The copy will be passed as a byval function parameter.
1276static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
1277 SDValue Chain, ISD::ArgFlagsTy Flags,
1278 SelectionDAG &DAG, const SDLoc &dl) {
1279 SDValue SizeNode = DAG.getIntPtrConstant(Val: Flags.getByValSize(), DL: dl);
1280 Align Alignment = Flags.getNonZeroByValAlign();
1281 return DAG.getMemcpy(Chain, dl, Dst, Src, Size: SizeNode, DstAlign: Alignment, SrcAlign: Alignment,
1282 /*isVolatile*/ isVol: false, /*AlwaysInline=*/true,
1283 /*CI=*/nullptr, OverrideTailCall: std::nullopt, DstPtrInfo: MachinePointerInfo(),
1284 SrcPtrInfo: MachinePointerInfo());
1285}
1286
1287/// Return true if the calling convention is one that we can guarantee TCO for.
1288static bool canGuaranteeTCO(CallingConv::ID CC) {
1289 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
1290 CC == CallingConv::X86_RegCall || CC == CallingConv::HiPE ||
1291 CC == CallingConv::Tail || CC == CallingConv::SwiftTail);
1292}
1293
1294/// Return true if we might ever do TCO for calls with this calling convention.
1295static bool mayTailCallThisCC(CallingConv::ID CC) {
1296 switch (CC) {
1297 // C calling conventions:
1298 case CallingConv::C:
1299 case CallingConv::Win64:
1300 case CallingConv::X86_64_SysV:
1301 case CallingConv::PreserveNone:
1302 // Callee pop conventions:
1303 case CallingConv::X86_ThisCall:
1304 case CallingConv::X86_StdCall:
1305 case CallingConv::X86_VectorCall:
1306 case CallingConv::X86_FastCall:
1307 // Swift:
1308 case CallingConv::Swift:
1309 return true;
1310 default:
1311 return canGuaranteeTCO(CC);
1312 }
1313}
1314
1315/// Return true if the function is being made into a tailcall target by
1316/// changing its ABI.
1317static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
1318 return (GuaranteedTailCallOpt && canGuaranteeTCO(CC)) ||
1319 CC == CallingConv::Tail || CC == CallingConv::SwiftTail;
1320}
1321
1322bool X86TargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
1323 if (!CI->isTailCall())
1324 return false;
1325
1326 CallingConv::ID CalleeCC = CI->getCallingConv();
1327 if (!mayTailCallThisCC(CC: CalleeCC))
1328 return false;
1329
1330 return true;
1331}
1332
1333SDValue
1334X86TargetLowering::LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
1335 const SmallVectorImpl<ISD::InputArg> &Ins,
1336 const SDLoc &dl, SelectionDAG &DAG,
1337 const CCValAssign &VA,
1338 MachineFrameInfo &MFI, unsigned i) const {
1339 // Create the nodes corresponding to a load from this parameter slot.
1340 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1341 bool AlwaysUseMutable = shouldGuaranteeTCO(
1342 CC: CallConv, GuaranteedTailCallOpt: DAG.getTarget().Options.GuaranteedTailCallOpt);
1343 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1344 EVT ValVT;
1345 MVT PtrVT = getPointerTy(DL: DAG.getDataLayout());
1346
1347 // If value is passed by pointer we have address passed instead of the value
1348 // itself. No need to extend if the mask value and location share the same
1349 // absolute size.
1350 bool ExtendedInMem =
1351 VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1 &&
1352 VA.getValVT().getSizeInBits() != VA.getLocVT().getSizeInBits();
1353
1354 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
1355 ValVT = VA.getLocVT();
1356 else
1357 ValVT = VA.getValVT();
1358
1359 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1360 // changed with more analysis.
1361 // In case of tail call optimization mark all arguments mutable. Since they
1362 // could be overwritten by lowering of arguments in case of a tail call.
1363 if (Flags.isByVal()) {
1364 unsigned Bytes = Flags.getByValSize();
1365 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1366
1367 // FIXME: For now, all byval parameter objects are marked as aliasing. This
1368 // can be improved with deeper analysis.
1369 int FI = MFI.CreateFixedObject(Size: Bytes, SPOffset: VA.getLocMemOffset(), IsImmutable: isImmutable,
1370 /*isAliased=*/true);
1371 return DAG.getFrameIndex(FI, VT: PtrVT);
1372 }
1373
1374 EVT ArgVT = Ins[i].ArgVT;
1375
1376 // If this is a vector that has been split into multiple parts, don't elide
1377 // the copy. The layout on the stack may not match the packed in-memory
1378 // layout.
1379 bool ScalarizedVector = ArgVT.isVector() && !VA.getLocVT().isVector();
1380
1381 // This is an argument in memory. We might be able to perform copy elision.
1382 // If the argument is passed directly in memory without any extension, then we
1383 // can perform copy elision. Large vector types, for example, may be passed
1384 // indirectly by pointer.
1385 if (Flags.isCopyElisionCandidate() &&
1386 VA.getLocInfo() != CCValAssign::Indirect && !ExtendedInMem &&
1387 !ScalarizedVector) {
1388 SDValue PartAddr;
1389 if (Ins[i].PartOffset == 0) {
1390 // If this is a one-part value or the first part of a multi-part value,
1391 // create a stack object for the entire argument value type and return a
1392 // load from our portion of it. This assumes that if the first part of an
1393 // argument is in memory, the rest will also be in memory.
1394 int FI = MFI.CreateFixedObject(Size: ArgVT.getStoreSize(), SPOffset: VA.getLocMemOffset(),
1395 /*IsImmutable=*/false);
1396 PartAddr = DAG.getFrameIndex(FI, VT: PtrVT);
1397 return DAG.getLoad(
1398 VT: ValVT, dl, Chain, Ptr: PartAddr,
1399 PtrInfo: MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI));
1400 }
1401
1402 // This is not the first piece of an argument in memory. See if there is
1403 // already a fixed stack object including this offset. If so, assume it
1404 // was created by the PartOffset == 0 branch above and create a load from
1405 // the appropriate offset into it.
1406 int64_t PartBegin = VA.getLocMemOffset();
1407 int64_t PartEnd = PartBegin + ValVT.getSizeInBits() / 8;
1408 int FI = MFI.getObjectIndexBegin();
1409 for (; MFI.isFixedObjectIndex(ObjectIdx: FI); ++FI) {
1410 int64_t ObjBegin = MFI.getObjectOffset(ObjectIdx: FI);
1411 int64_t ObjEnd = ObjBegin + MFI.getObjectSize(ObjectIdx: FI);
1412 if (ObjBegin <= PartBegin && PartEnd <= ObjEnd)
1413 break;
1414 }
1415 if (MFI.isFixedObjectIndex(ObjectIdx: FI)) {
1416 SDValue Addr =
1417 DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: PtrVT, N1: DAG.getFrameIndex(FI, VT: PtrVT),
1418 N2: DAG.getIntPtrConstant(Val: Ins[i].PartOffset, DL: dl));
1419 return DAG.getLoad(VT: ValVT, dl, Chain, Ptr: Addr,
1420 PtrInfo: MachinePointerInfo::getFixedStack(
1421 MF&: DAG.getMachineFunction(), FI, Offset: Ins[i].PartOffset));
1422 }
1423 }
1424
1425 int FI = MFI.CreateFixedObject(Size: ValVT.getSizeInBits() / 8,
1426 SPOffset: VA.getLocMemOffset(), IsImmutable: isImmutable);
1427
1428 // Set SExt or ZExt flag.
1429 if (VA.getLocInfo() == CCValAssign::ZExt) {
1430 MFI.setObjectZExt(ObjectIdx: FI, IsZExt: true);
1431 } else if (VA.getLocInfo() == CCValAssign::SExt) {
1432 MFI.setObjectSExt(ObjectIdx: FI, IsSExt: true);
1433 }
1434
1435 MaybeAlign Alignment;
1436 if (Subtarget.isTargetWindowsMSVC() && !Subtarget.is64Bit() &&
1437 ValVT != MVT::f80)
1438 Alignment = MaybeAlign(4);
1439 SDValue FIN = DAG.getFrameIndex(FI, VT: PtrVT);
1440 SDValue Val = DAG.getLoad(
1441 VT: ValVT, dl, Chain, Ptr: FIN,
1442 PtrInfo: MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI),
1443 Alignment);
1444 return ExtendedInMem
1445 ? (VA.getValVT().isVector()
1446 ? DAG.getNode(Opcode: ISD::SCALAR_TO_VECTOR, DL: dl, VT: VA.getValVT(), Operand: Val)
1447 : DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: VA.getValVT(), Operand: Val))
1448 : Val;
1449}
1450
1451// FIXME: Get this from tablegen.
1452static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
1453 const X86Subtarget &Subtarget) {
1454 assert(Subtarget.is64Bit());
1455
1456 if (Subtarget.isCallingConvWin64(CC: CallConv)) {
1457 static const MCPhysReg GPR64ArgRegsWin64[] = {
1458 X86::RCX, X86::RDX, X86::R8, X86::R9
1459 };
1460 return GPR64ArgRegsWin64;
1461 }
1462
1463 static const MCPhysReg GPR64ArgRegs64Bit[] = {
1464 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1465 };
1466 return GPR64ArgRegs64Bit;
1467}
1468
1469// FIXME: Get this from tablegen.
1470static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
1471 CallingConv::ID CallConv,
1472 const X86Subtarget &Subtarget) {
1473 assert(Subtarget.is64Bit());
1474 if (Subtarget.isCallingConvWin64(CC: CallConv)) {
1475 // The XMM registers which might contain var arg parameters are shadowed
1476 // in their paired GPR. So we only need to save the GPR to their home
1477 // slots.
1478 // TODO: __vectorcall will change this.
1479 return {};
1480 }
1481
1482 bool isSoftFloat = Subtarget.useSoftFloat();
1483 if (isSoftFloat || !Subtarget.hasSSE1())
1484 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
1485 // registers.
1486 return {};
1487
1488 static const MCPhysReg XMMArgRegs64Bit[] = {
1489 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1490 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1491 };
1492 return XMMArgRegs64Bit;
1493}
1494
1495#ifndef NDEBUG
1496static bool isSortedByValueNo(ArrayRef<CCValAssign> ArgLocs) {
1497 return llvm::is_sorted(
1498 ArgLocs, [](const CCValAssign &A, const CCValAssign &B) -> bool {
1499 return A.getValNo() < B.getValNo();
1500 });
1501}
1502#endif
1503
1504namespace {
1505/// This is a helper class for lowering variable arguments parameters.
1506class VarArgsLoweringHelper {
1507public:
1508 VarArgsLoweringHelper(X86MachineFunctionInfo *FuncInfo, const SDLoc &Loc,
1509 SelectionDAG &DAG, const X86Subtarget &Subtarget,
1510 CallingConv::ID CallConv, CCState &CCInfo)
1511 : FuncInfo(FuncInfo), DL(Loc), DAG(DAG), Subtarget(Subtarget),
1512 TheMachineFunction(DAG.getMachineFunction()),
1513 TheFunction(TheMachineFunction.getFunction()),
1514 FrameInfo(TheMachineFunction.getFrameInfo()),
1515 FrameLowering(*Subtarget.getFrameLowering()),
1516 TargLowering(DAG.getTargetLoweringInfo()), CallConv(CallConv),
1517 CCInfo(CCInfo) {}
1518
1519 // Lower variable arguments parameters.
1520 void lowerVarArgsParameters(SDValue &Chain, unsigned StackSize);
1521
1522private:
1523 void createVarArgAreaAndStoreRegisters(SDValue &Chain, unsigned StackSize);
1524
1525 void forwardMustTailParameters(SDValue &Chain);
1526
1527 bool is64Bit() const { return Subtarget.is64Bit(); }
1528 bool isWin64() const { return Subtarget.isCallingConvWin64(CC: CallConv); }
1529
1530 X86MachineFunctionInfo *FuncInfo;
1531 const SDLoc &DL;
1532 SelectionDAG &DAG;
1533 const X86Subtarget &Subtarget;
1534 MachineFunction &TheMachineFunction;
1535 const Function &TheFunction;
1536 MachineFrameInfo &FrameInfo;
1537 const TargetFrameLowering &FrameLowering;
1538 const TargetLowering &TargLowering;
1539 CallingConv::ID CallConv;
1540 CCState &CCInfo;
1541};
1542} // namespace
1543
1544void VarArgsLoweringHelper::createVarArgAreaAndStoreRegisters(
1545 SDValue &Chain, unsigned StackSize) {
1546 // If the function takes variable number of arguments, make a frame index for
1547 // the start of the first vararg value... for expansion of llvm.va_start. We
1548 // can skip this if there are no va_start calls.
1549 if (is64Bit() || (CallConv != CallingConv::X86_FastCall &&
1550 CallConv != CallingConv::X86_ThisCall)) {
1551 FuncInfo->setVarArgsFrameIndex(
1552 FrameInfo.CreateFixedObject(Size: 1, SPOffset: StackSize, IsImmutable: true));
1553 }
1554
1555 // 64-bit calling conventions support varargs and register parameters, so we
1556 // have to do extra work to spill them in the prologue.
1557 if (is64Bit()) {
1558 // Find the first unallocated argument registers.
1559 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
1560 ArrayRef<MCPhysReg> ArgXMMs =
1561 get64BitArgumentXMMs(MF&: TheMachineFunction, CallConv, Subtarget);
1562 unsigned NumIntRegs = CCInfo.getFirstUnallocated(Regs: ArgGPRs);
1563 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(Regs: ArgXMMs);
1564
1565 assert(!(NumXMMRegs && !Subtarget.hasSSE1()) &&
1566 "SSE register cannot be used when SSE is disabled!");
1567
1568 if (isWin64()) {
1569 // Get to the caller-allocated home save location. Add 8 to account
1570 // for the return address.
1571 int HomeOffset = FrameLowering.getOffsetOfLocalArea() + 8;
1572 FuncInfo->setRegSaveFrameIndex(
1573 FrameInfo.CreateFixedObject(Size: 1, SPOffset: NumIntRegs * 8 + HomeOffset, IsImmutable: false));
1574 // Fixup to set vararg frame on shadow area (4 x i64).
1575 if (NumIntRegs < 4)
1576 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1577 } else {
1578 // For X86-64, if there are vararg parameters that are passed via
1579 // registers, then we must store them to their spots on the stack so
1580 // they may be loaded by dereferencing the result of va_next.
1581 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1582 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
1583 FuncInfo->setRegSaveFrameIndex(FrameInfo.CreateStackObject(
1584 Size: ArgGPRs.size() * 8 + ArgXMMs.size() * 16, Alignment: Align(16), isSpillSlot: false));
1585 }
1586
1587 SmallVector<SDValue, 6>
1588 LiveGPRs; // list of SDValue for GPR registers keeping live input value
1589 SmallVector<SDValue, 8> LiveXMMRegs; // list of SDValue for XMM registers
1590 // keeping live input value
1591 SDValue ALVal; // if applicable keeps SDValue for %al register
1592
1593 // Gather all the live in physical registers.
1594 for (MCPhysReg Reg : ArgGPRs.slice(N: NumIntRegs)) {
1595 Register GPR = TheMachineFunction.addLiveIn(PReg: Reg, RC: &X86::GR64RegClass);
1596 LiveGPRs.push_back(Elt: DAG.getCopyFromReg(Chain, dl: DL, Reg: GPR, VT: MVT::i64));
1597 }
1598 const auto &AvailableXmms = ArgXMMs.slice(N: NumXMMRegs);
1599 if (!AvailableXmms.empty()) {
1600 Register AL = TheMachineFunction.addLiveIn(PReg: X86::AL, RC: &X86::GR8RegClass);
1601 ALVal = DAG.getCopyFromReg(Chain, dl: DL, Reg: AL, VT: MVT::i8);
1602 for (MCPhysReg Reg : AvailableXmms) {
1603 // FastRegisterAllocator spills virtual registers at basic
1604 // block boundary. That leads to usages of xmm registers
1605 // outside of check for %al. Pass physical registers to
1606 // VASTART_SAVE_XMM_REGS to avoid unneccessary spilling.
1607 TheMachineFunction.getRegInfo().addLiveIn(Reg);
1608 LiveXMMRegs.push_back(Elt: DAG.getRegister(Reg, VT: MVT::v4f32));
1609 }
1610 }
1611
1612 // Store the integer parameter registers.
1613 SmallVector<SDValue, 8> MemOps;
1614 SDValue RSFIN =
1615 DAG.getFrameIndex(FI: FuncInfo->getRegSaveFrameIndex(),
1616 VT: TargLowering.getPointerTy(DL: DAG.getDataLayout()));
1617 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1618 for (SDValue Val : LiveGPRs) {
1619 SDValue FIN = DAG.getNode(Opcode: ISD::ADD, DL,
1620 VT: TargLowering.getPointerTy(DL: DAG.getDataLayout()),
1621 N1: RSFIN, N2: DAG.getIntPtrConstant(Val: Offset, DL));
1622 SDValue Store =
1623 DAG.getStore(Chain: Val.getValue(R: 1), dl: DL, Val, Ptr: FIN,
1624 PtrInfo: MachinePointerInfo::getFixedStack(
1625 MF&: DAG.getMachineFunction(),
1626 FI: FuncInfo->getRegSaveFrameIndex(), Offset));
1627 MemOps.push_back(Elt: Store);
1628 Offset += 8;
1629 }
1630
1631 // Now store the XMM (fp + vector) parameter registers.
1632 if (!LiveXMMRegs.empty()) {
1633 SmallVector<SDValue, 12> SaveXMMOps;
1634 SaveXMMOps.push_back(Elt: Chain);
1635 SaveXMMOps.push_back(Elt: ALVal);
1636 SaveXMMOps.push_back(Elt: RSFIN);
1637 SaveXMMOps.push_back(
1638 Elt: DAG.getTargetConstant(Val: FuncInfo->getVarArgsFPOffset(), DL, VT: MVT::i32));
1639 llvm::append_range(C&: SaveXMMOps, R&: LiveXMMRegs);
1640 MachineMemOperand *StoreMMO =
1641 DAG.getMachineFunction().getMachineMemOperand(
1642 PtrInfo: MachinePointerInfo::getFixedStack(
1643 MF&: DAG.getMachineFunction(), FI: FuncInfo->getRegSaveFrameIndex(),
1644 Offset),
1645 F: MachineMemOperand::MOStore, Size: 128, BaseAlignment: Align(16));
1646 MemOps.push_back(Elt: DAG.getMemIntrinsicNode(Opcode: X86ISD::VASTART_SAVE_XMM_REGS,
1647 dl: DL, VTList: DAG.getVTList(VT: MVT::Other),
1648 Ops: SaveXMMOps, MemVT: MVT::i8, MMO: StoreMMO));
1649 }
1650
1651 if (!MemOps.empty())
1652 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL, VT: MVT::Other, Ops: MemOps);
1653 }
1654}
1655
1656void VarArgsLoweringHelper::forwardMustTailParameters(SDValue &Chain) {
1657 // Find the largest legal vector type.
1658 MVT VecVT = MVT::Other;
1659 // FIXME: Only some x86_32 calling conventions support AVX512.
1660 if (Subtarget.useAVX512Regs() &&
1661 (is64Bit() || (CallConv == CallingConv::X86_VectorCall ||
1662 CallConv == CallingConv::Intel_OCL_BI)))
1663 VecVT = MVT::v16f32;
1664 else if (Subtarget.hasAVX())
1665 VecVT = MVT::v8f32;
1666 else if (Subtarget.hasSSE2())
1667 VecVT = MVT::v4f32;
1668
1669 // We forward some GPRs and some vector types.
1670 SmallVector<MVT, 2> RegParmTypes;
1671 MVT IntVT = is64Bit() ? MVT::i64 : MVT::i32;
1672 RegParmTypes.push_back(Elt: IntVT);
1673 if (VecVT != MVT::Other)
1674 RegParmTypes.push_back(Elt: VecVT);
1675
1676 // Compute the set of forwarded registers. The rest are scratch.
1677 SmallVectorImpl<ForwardedRegister> &Forwards =
1678 FuncInfo->getForwardedMustTailRegParms();
1679 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, Fn: CC_X86);
1680
1681 // Forward AL for SysV x86_64 targets, since it is used for varargs.
1682 if (is64Bit() && !isWin64() && !CCInfo.isAllocated(Reg: X86::AL)) {
1683 Register ALVReg = TheMachineFunction.addLiveIn(PReg: X86::AL, RC: &X86::GR8RegClass);
1684 Forwards.push_back(Elt: ForwardedRegister(ALVReg, X86::AL, MVT::i8));
1685 }
1686
1687 // Copy all forwards from physical to virtual registers.
1688 for (ForwardedRegister &FR : Forwards) {
1689 // FIXME: Can we use a less constrained schedule?
1690 SDValue RegVal = DAG.getCopyFromReg(Chain, dl: DL, Reg: FR.VReg, VT: FR.VT);
1691 FR.VReg = TheMachineFunction.getRegInfo().createVirtualRegister(
1692 RegClass: TargLowering.getRegClassFor(VT: FR.VT));
1693 Chain = DAG.getCopyToReg(Chain, dl: DL, Reg: FR.VReg, N: RegVal);
1694 }
1695}
1696
1697void VarArgsLoweringHelper::lowerVarArgsParameters(SDValue &Chain,
1698 unsigned StackSize) {
1699 // Set FrameIndex to the 0xAAAAAAA value to mark unset state.
1700 // If necessary, it would be set into the correct value later.
1701 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1702 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1703
1704 if (FrameInfo.hasVAStart())
1705 createVarArgAreaAndStoreRegisters(Chain, StackSize);
1706
1707 if (FrameInfo.hasMustTailInVarArgFunc())
1708 forwardMustTailParameters(Chain);
1709}
1710
1711SDValue X86TargetLowering::LowerFormalArguments(
1712 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
1713 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1714 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1715 MachineFunction &MF = DAG.getMachineFunction();
1716 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1717
1718 const Function &F = MF.getFunction();
1719 if (F.hasExternalLinkage() && Subtarget.isTargetCygMing() &&
1720 F.getName() == "main")
1721 FuncInfo->setForceFramePointer(true);
1722
1723 MachineFrameInfo &MFI = MF.getFrameInfo();
1724 bool Is64Bit = Subtarget.is64Bit();
1725 bool IsWin64 = Subtarget.isCallingConvWin64(CC: CallConv);
1726
1727 // On x86_64 with x87 disabled, x86_fp80 cannot be handled: the type would
1728 // need to be returned/passed in x87 registers (FP0/FP1) which are
1729 // unavailable. Emit a clear diagnostic instead of crashing later with
1730 // "Cannot select: build_pair".
1731 if (Is64Bit && !Subtarget.hasX87()) {
1732 if (F.getReturnType()->isX86_FP80Ty() ||
1733 any_of(Range: F.args(), P: [](const Argument &Arg) {
1734 return Arg.getType()->isX86_FP80Ty();
1735 }))
1736 reportFatalUsageError(
1737 reason: "cannot use x86_fp80 type with x87 disabled on x86_64 target");
1738 }
1739
1740 assert(
1741 !(IsVarArg && canGuaranteeTCO(CallConv)) &&
1742 "Var args not supported with calling conv' regcall, fastcc, ghc or hipe");
1743
1744 // Assign locations to all of the incoming arguments.
1745 SmallVector<CCValAssign, 16> ArgLocs;
1746 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
1747
1748 // Allocate shadow area for Win64.
1749 if (IsWin64)
1750 CCInfo.AllocateStack(Size: 32, Alignment: Align(8));
1751
1752 CCInfo.AnalyzeArguments(Ins, Fn: CC_X86);
1753
1754 // In vectorcall calling convention a second pass is required for the HVA
1755 // types.
1756 if (CallingConv::X86_VectorCall == CallConv) {
1757 CCInfo.AnalyzeArgumentsSecondPass(Args: Ins, Fn: CC_X86);
1758 }
1759
1760 // The next loop assumes that the locations are in the same order of the
1761 // input arguments.
1762 assert(isSortedByValueNo(ArgLocs) &&
1763 "Argument Location list must be sorted before lowering");
1764
1765 SDValue ArgValue;
1766 for (unsigned I = 0, InsIndex = 0, E = ArgLocs.size(); I != E;
1767 ++I, ++InsIndex) {
1768 assert(InsIndex < Ins.size() && "Invalid Ins index");
1769 CCValAssign &VA = ArgLocs[I];
1770
1771 if (VA.isRegLoc()) {
1772 EVT RegVT = VA.getLocVT();
1773 if (VA.needsCustom()) {
1774 assert(
1775 VA.getValVT() == MVT::v64i1 &&
1776 "Currently the only custom case is when we split v64i1 to 2 regs");
1777
1778 // v64i1 values, in regcall calling convention, that are
1779 // compiled to 32 bit arch, are split up into two registers.
1780 ArgValue =
1781 getv64i1Argument(VA, NextVA&: ArgLocs[++I], Root&: Chain, DAG, DL: dl, Subtarget);
1782 } else {
1783 const TargetRegisterClass *RC;
1784 if (RegVT == MVT::i8)
1785 RC = &X86::GR8RegClass;
1786 else if (RegVT == MVT::i16)
1787 RC = &X86::GR16RegClass;
1788 else if (RegVT == MVT::i32)
1789 RC = &X86::GR32RegClass;
1790 else if (Is64Bit && RegVT == MVT::i64)
1791 RC = &X86::GR64RegClass;
1792 else if (RegVT == MVT::f16)
1793 RC = Subtarget.hasAVX512() ? &X86::FR16XRegClass : &X86::FR16RegClass;
1794 else if (RegVT == MVT::f32)
1795 RC = Subtarget.hasAVX512() ? &X86::FR32XRegClass : &X86::FR32RegClass;
1796 else if (RegVT == MVT::f64)
1797 RC = Subtarget.hasAVX512() ? &X86::FR64XRegClass : &X86::FR64RegClass;
1798 else if (RegVT == MVT::f80)
1799 RC = &X86::RFP80RegClass;
1800 else if (RegVT == MVT::f128)
1801 RC = &X86::VR128RegClass;
1802 else if (RegVT.is512BitVector())
1803 RC = &X86::VR512RegClass;
1804 else if (RegVT.is256BitVector())
1805 RC = Subtarget.hasVLX() ? &X86::VR256XRegClass : &X86::VR256RegClass;
1806 else if (RegVT.is128BitVector())
1807 RC = Subtarget.hasVLX() ? &X86::VR128XRegClass : &X86::VR128RegClass;
1808 else if (RegVT == MVT::x86mmx)
1809 RC = &X86::VR64RegClass;
1810 else if (RegVT == MVT::v1i1)
1811 RC = &X86::VK1RegClass;
1812 else if (RegVT == MVT::v8i1)
1813 RC = &X86::VK8RegClass;
1814 else if (RegVT == MVT::v16i1)
1815 RC = &X86::VK16RegClass;
1816 else if (RegVT == MVT::v32i1)
1817 RC = &X86::VK32RegClass;
1818 else if (RegVT == MVT::v64i1)
1819 RC = &X86::VK64RegClass;
1820 else
1821 llvm_unreachable("Unknown argument type!");
1822
1823 Register Reg = MF.addLiveIn(PReg: VA.getLocReg(), RC);
1824 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, VT: RegVT);
1825 }
1826
1827 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1828 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1829 // right size.
1830 if (VA.getLocInfo() == CCValAssign::SExt)
1831 ArgValue = DAG.getNode(Opcode: ISD::AssertSext, DL: dl, VT: RegVT, N1: ArgValue,
1832 N2: DAG.getValueType(VA.getValVT()));
1833 else if (VA.getLocInfo() == CCValAssign::ZExt)
1834 ArgValue = DAG.getNode(Opcode: ISD::AssertZext, DL: dl, VT: RegVT, N1: ArgValue,
1835 N2: DAG.getValueType(VA.getValVT()));
1836 else if (VA.getLocInfo() == CCValAssign::BCvt)
1837 ArgValue = DAG.getBitcast(VT: VA.getValVT(), V: ArgValue);
1838
1839 if (VA.isExtInLoc()) {
1840 // Handle MMX values passed in XMM regs.
1841 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
1842 ArgValue = DAG.getNode(Opcode: X86ISD::MOVDQ2Q, DL: dl, VT: VA.getValVT(), Operand: ArgValue);
1843 else if (VA.getValVT().isVector() &&
1844 VA.getValVT().getScalarType() == MVT::i1 &&
1845 ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) ||
1846 (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) {
1847 // Promoting a mask type (v*i1) into a register of type i64/i32/i16/i8
1848 ArgValue = lowerRegToMasks(ValArg: ArgValue, ValVT: VA.getValVT(), ValLoc: RegVT, DL: dl, DAG);
1849 } else
1850 ArgValue = DAG.getNode(Opcode: ISD::TRUNCATE, DL: dl, VT: VA.getValVT(), Operand: ArgValue);
1851 }
1852 } else {
1853 assert(VA.isMemLoc());
1854 ArgValue =
1855 LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i: InsIndex);
1856 }
1857
1858 // If value is passed via pointer - do a load.
1859 if (VA.getLocInfo() == CCValAssign::Indirect &&
1860 !(Ins[I].Flags.isByVal() && VA.isRegLoc())) {
1861 ArgValue =
1862 DAG.getLoad(VT: VA.getValVT(), dl, Chain, Ptr: ArgValue, PtrInfo: MachinePointerInfo());
1863 }
1864
1865 InVals.push_back(Elt: ArgValue);
1866 }
1867
1868 for (unsigned I = 0, E = Ins.size(); I != E; ++I) {
1869 if (Ins[I].Flags.isSwiftAsync()) {
1870 auto X86FI = MF.getInfo<X86MachineFunctionInfo>();
1871 if (X86::isExtendedSwiftAsyncFrameSupported(Subtarget, MF))
1872 X86FI->setHasSwiftAsyncContext(true);
1873 else {
1874 int PtrSize = Subtarget.is64Bit() ? 8 : 4;
1875 int FI =
1876 MF.getFrameInfo().CreateStackObject(Size: PtrSize, Alignment: Align(PtrSize), isSpillSlot: false);
1877 X86FI->setSwiftAsyncContextFrameIdx(FI);
1878 SDValue St = DAG.getStore(
1879 Chain: DAG.getEntryNode(), dl, Val: InVals[I],
1880 Ptr: DAG.getFrameIndex(FI, VT: PtrSize == 8 ? MVT::i64 : MVT::i32),
1881 PtrInfo: MachinePointerInfo::getFixedStack(MF, FI));
1882 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: St, N2: Chain);
1883 }
1884 }
1885
1886 // Swift calling convention does not require we copy the sret argument
1887 // into %rax/%eax for the return. We don't set SRetReturnReg for Swift.
1888 if (CallConv == CallingConv::Swift || CallConv == CallingConv::SwiftTail)
1889 continue;
1890
1891 // All x86 ABIs require that for returning structs by value we copy the
1892 // sret argument into %rax/%eax (depending on ABI) for the return. Save
1893 // the argument into a virtual register so that we can access it from the
1894 // return points.
1895 if (Ins[I].Flags.isSRet()) {
1896 assert(!FuncInfo->getSRetReturnReg() &&
1897 "SRet return has already been set");
1898 MVT PtrTy = getPointerTy(DL: DAG.getDataLayout());
1899 Register Reg =
1900 MF.getRegInfo().createVirtualRegister(RegClass: getRegClassFor(VT: PtrTy));
1901 FuncInfo->setSRetReturnReg(Reg);
1902 SDValue Copy = DAG.getCopyToReg(Chain: DAG.getEntryNode(), dl, Reg, N: InVals[I]);
1903 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Copy, N2: Chain);
1904 break;
1905 }
1906 }
1907
1908 unsigned StackSize = CCInfo.getStackSize();
1909 // Align stack specially for tail calls.
1910 if (shouldGuaranteeTCO(CC: CallConv,
1911 GuaranteedTailCallOpt: MF.getTarget().Options.GuaranteedTailCallOpt))
1912 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1913
1914 if (IsVarArg)
1915 VarArgsLoweringHelper(FuncInfo, dl, DAG, Subtarget, CallConv, CCInfo)
1916 .lowerVarArgsParameters(Chain, StackSize);
1917
1918 // Some CCs need callee pop.
1919 if (X86::isCalleePop(CallingConv: CallConv, is64Bit: Is64Bit, IsVarArg,
1920 GuaranteeTCO: MF.getTarget().Options.GuaranteedTailCallOpt)) {
1921 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1922 } else if (CallConv == CallingConv::X86_INTR && Ins.size() == 2) {
1923 // X86 interrupts must pop the error code (and the alignment padding) if
1924 // present.
1925 FuncInfo->setBytesToPopOnReturn(Is64Bit ? 16 : 4);
1926 } else {
1927 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1928 // If this is an sret function, the return should pop the hidden pointer.
1929 if (hasCalleePopSRet(Args: Ins, ArgLocs, Subtarget))
1930 FuncInfo->setBytesToPopOnReturn(4);
1931 }
1932
1933 if (!Is64Bit) {
1934 // RegSaveFrameIndex is X86-64 only.
1935 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1936 }
1937
1938 FuncInfo->setArgumentStackSize(StackSize);
1939
1940 if (WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo()) {
1941 EHPersonality Personality = classifyEHPersonality(Pers: F.getPersonalityFn());
1942 if (Personality == EHPersonality::CoreCLR) {
1943 assert(Is64Bit);
1944 // TODO: Add a mechanism to frame lowering that will allow us to indicate
1945 // that we'd prefer this slot be allocated towards the bottom of the frame
1946 // (i.e. near the stack pointer after allocating the frame). Every
1947 // funclet needs a copy of this slot in its (mostly empty) frame, and the
1948 // offset from the bottom of this and each funclet's frame must be the
1949 // same, so the size of funclets' (mostly empty) frames is dictated by
1950 // how far this slot is from the bottom (since they allocate just enough
1951 // space to accommodate holding this slot at the correct offset).
1952 int PSPSymFI = MFI.CreateStackObject(Size: 8, Alignment: Align(8), /*isSpillSlot=*/false);
1953 EHInfo->PSPSymFrameIdx = PSPSymFI;
1954 }
1955 }
1956
1957 if (shouldDisableArgRegFromCSR(CC: CallConv) ||
1958 F.hasFnAttribute(Kind: "no_caller_saved_registers")) {
1959 MachineRegisterInfo &MRI = MF.getRegInfo();
1960 for (std::pair<MCRegister, Register> Pair : MRI.liveins())
1961 MRI.disableCalleeSavedRegister(Reg: Pair.first);
1962 }
1963
1964 if (CallingConv::PreserveNone == CallConv)
1965 for (const ISD::InputArg &In : Ins) {
1966 if (In.Flags.isSwiftSelf() || In.Flags.isSwiftAsync() ||
1967 In.Flags.isSwiftError()) {
1968 errorUnsupported(DAG, dl,
1969 Msg: "Swift attributes can't be used with preserve_none");
1970 break;
1971 }
1972 }
1973
1974 return Chain;
1975}
1976
1977SDValue X86TargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
1978 SDValue Arg, const SDLoc &dl,
1979 SelectionDAG &DAG,
1980 const CCValAssign &VA,
1981 ISD::ArgFlagsTy Flags,
1982 bool isByVal) const {
1983 unsigned LocMemOffset = VA.getLocMemOffset();
1984 SDValue PtrOff = DAG.getIntPtrConstant(Val: LocMemOffset, DL: dl);
1985 PtrOff = DAG.getNode(Opcode: ISD::ADD, DL: dl, VT: getPointerTy(DL: DAG.getDataLayout()),
1986 N1: StackPtr, N2: PtrOff);
1987 if (isByVal)
1988 return CreateCopyOfByValArgument(Src: Arg, Dst: PtrOff, Chain, Flags, DAG, dl);
1989
1990 MaybeAlign Alignment;
1991 if (Subtarget.isTargetWindowsMSVC() && !Subtarget.is64Bit() &&
1992 Arg.getSimpleValueType() != MVT::f80)
1993 Alignment = MaybeAlign(4);
1994 return DAG.getStore(
1995 Chain, dl, Val: Arg, Ptr: PtrOff,
1996 PtrInfo: MachinePointerInfo::getStack(MF&: DAG.getMachineFunction(), Offset: LocMemOffset),
1997 Alignment);
1998}
1999
2000/// Emit a load of return address if tail call
2001/// optimization is performed and it is required.
2002SDValue X86TargetLowering::EmitTailCallLoadRetAddr(
2003 SelectionDAG &DAG, SDValue &OutRetAddr, SDValue Chain, bool IsTailCall,
2004 bool Is64Bit, int FPDiff, const SDLoc &dl) const {
2005 // Adjust the Return address stack slot.
2006 EVT VT = getPointerTy(DL: DAG.getDataLayout());
2007 OutRetAddr = getReturnAddressFrameIndex(DAG);
2008
2009 // Load the "old" Return address.
2010 OutRetAddr = DAG.getLoad(VT, dl, Chain, Ptr: OutRetAddr, PtrInfo: MachinePointerInfo());
2011 return SDValue(OutRetAddr.getNode(), 1);
2012}
2013
2014/// Emit a store of the return address if tail call
2015/// optimization is performed and it is required (FPDiff!=0).
2016static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2017 SDValue Chain, SDValue RetAddrFrIdx,
2018 EVT PtrVT, unsigned SlotSize,
2019 int FPDiff, const SDLoc &dl) {
2020 // Store the return address to the appropriate stack slot.
2021 if (!FPDiff) return Chain;
2022 // Calculate the new stack slot for the return address.
2023 int NewReturnAddrFI =
2024 MF.getFrameInfo().CreateFixedObject(Size: SlotSize, SPOffset: (int64_t)FPDiff - SlotSize,
2025 IsImmutable: false);
2026 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(FI: NewReturnAddrFI, VT: PtrVT);
2027 Chain = DAG.getStore(Chain, dl, Val: RetAddrFrIdx, Ptr: NewRetAddrFrIdx,
2028 PtrInfo: MachinePointerInfo::getFixedStack(
2029 MF&: DAG.getMachineFunction(), FI: NewReturnAddrFI));
2030 return Chain;
2031}
2032
2033/// Returns a vector_shuffle mask for an movs{s|d}, movd
2034/// operation of specified width.
2035SDValue X86TargetLowering::getMOVL(SelectionDAG &DAG, const SDLoc &dl, MVT VT,
2036 SDValue V1, SDValue V2) const {
2037 unsigned NumElems = VT.getVectorNumElements();
2038 SmallVector<int, 8> Mask;
2039 Mask.push_back(Elt: NumElems);
2040 for (unsigned i = 1; i != NumElems; ++i)
2041 Mask.push_back(Elt: i);
2042 return DAG.getVectorShuffle(VT, dl, N1: V1, N2: V2, Mask);
2043}
2044
2045// Returns the type of copying which is required to set up a byval argument to
2046// a tail-called function. This isn't needed for non-tail calls, because they
2047// always need the equivalent of CopyOnce, but tail-calls sometimes need two to
2048// avoid clobbering another argument (CopyViaTemp), and sometimes can be
2049// optimised to zero copies when forwarding an argument from the caller's
2050// caller (NoCopy).
2051X86TargetLowering::ByValCopyKind X86TargetLowering::ByValNeedsCopyForTailCall(
2052 SelectionDAG &DAG, SDValue Src, SDValue Dst, ISD::ArgFlagsTy Flags) const {
2053 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2054
2055 // Globals are always safe to copy from.
2056 if (isa<GlobalAddressSDNode>(Val: Src) || isa<ExternalSymbolSDNode>(Val: Src))
2057 return CopyOnce;
2058
2059 // Can only analyse frame index nodes, conservatively assume we need a
2060 // temporary.
2061 auto *SrcFrameIdxNode = dyn_cast<FrameIndexSDNode>(Val&: Src);
2062 auto *DstFrameIdxNode = dyn_cast<FrameIndexSDNode>(Val&: Dst);
2063 if (!SrcFrameIdxNode || !DstFrameIdxNode)
2064 return CopyViaTemp;
2065
2066 int SrcFI = SrcFrameIdxNode->getIndex();
2067 int DstFI = DstFrameIdxNode->getIndex();
2068 assert(MFI.isFixedObjectIndex(DstFI) &&
2069 "byval passed in non-fixed stack slot");
2070
2071 int64_t SrcOffset = MFI.getObjectOffset(ObjectIdx: SrcFI);
2072 int64_t DstOffset = MFI.getObjectOffset(ObjectIdx: DstFI);
2073
2074 // If the source is in the local frame, then the copy to the argument
2075 // memory is always valid.
2076 bool FixedSrc = MFI.isFixedObjectIndex(ObjectIdx: SrcFI);
2077 if (!FixedSrc || (FixedSrc && SrcOffset < 0))
2078 return CopyOnce;
2079
2080 // If the value is already in the correct location, then no copying is
2081 // needed. If not, then we need to copy via a temporary.
2082 if (SrcOffset == DstOffset)
2083 return NoCopy;
2084 else
2085 return CopyViaTemp;
2086}
2087
2088SDValue
2089X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2090 SmallVectorImpl<SDValue> &InVals) const {
2091 SelectionDAG &DAG = CLI.DAG;
2092 SDLoc &dl = CLI.DL;
2093 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2094 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2095 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2096 SDValue Chain = CLI.Chain;
2097 SDValue Callee = CLI.Callee;
2098 CallingConv::ID CallConv = CLI.CallConv;
2099 bool &isTailCall = CLI.IsTailCall;
2100 bool isVarArg = CLI.IsVarArg;
2101 const auto *CB = CLI.CB;
2102
2103 MachineFunction &MF = DAG.getMachineFunction();
2104 bool Is64Bit = Subtarget.is64Bit();
2105 bool IsWin64 = Subtarget.isCallingConvWin64(CC: CallConv);
2106 bool ShouldGuaranteeTCO = shouldGuaranteeTCO(
2107 CC: CallConv, GuaranteedTailCallOpt: MF.getTarget().Options.GuaranteedTailCallOpt);
2108 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2109 bool HasNCSR = (CB && isa<CallInst>(Val: CB) &&
2110 CB->hasFnAttr(Kind: "no_caller_saved_registers"));
2111 bool IsIndirectCall = (CB && isa<CallInst>(Val: CB) && CB->isIndirectCall());
2112 bool IsCFICall = IsIndirectCall && CLI.CFIType;
2113 const Module *M = MF.getFunction().getParent();
2114
2115 // If the indirect call target has the nocf_check attribute, the call needs
2116 // the NOTRACK prefix. For simplicity just disable tail calls as there are
2117 // so many variants.
2118 // FIXME: This will cause backend errors if the user forces the issue.
2119 bool IsNoTrackIndirectCall = IsIndirectCall && CB->doesNoCfCheck() &&
2120 M->getModuleFlag(Key: "cf-protection-branch");
2121 if (IsNoTrackIndirectCall)
2122 isTailCall = false;
2123
2124 MachineFunction::CallSiteInfo CSInfo;
2125 if (CallConv == CallingConv::X86_INTR)
2126 report_fatal_error(reason: "X86 interrupts may not be called directly");
2127
2128 // Set type id for call site info.
2129 setTypeIdForCallsiteInfo(CB, MF, CSInfo);
2130
2131 if (IsIndirectCall && !IsWin64 &&
2132 M->getModuleFlag(Key: "import-call-optimization"))
2133 errorUnsupported(DAG, dl,
2134 Msg: "Indirect calls must have a normal calling convention if "
2135 "Import Call Optimization is enabled");
2136
2137 // Analyze operands of the call, assigning locations to each operand.
2138 SmallVector<CCValAssign, 16> ArgLocs;
2139 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2140
2141 // Allocate shadow area for Win64.
2142 if (IsWin64)
2143 CCInfo.AllocateStack(Size: 32, Alignment: Align(8));
2144
2145 CCInfo.AnalyzeArguments(Outs, Fn: CC_X86);
2146
2147 // In vectorcall calling convention a second pass is required for the HVA
2148 // types.
2149 if (CallingConv::X86_VectorCall == CallConv) {
2150 CCInfo.AnalyzeArgumentsSecondPass(Args: Outs, Fn: CC_X86);
2151 }
2152
2153 // We cannot guarantee TCO for mismatched calling conventions.
2154 if (isTailCall && ShouldGuaranteeTCO) {
2155 CallingConv::ID CallerCC = MF.getFunction().getCallingConv();
2156 isTailCall = (CallConv == CallerCC);
2157 }
2158
2159 // Check if this tail call is a "sibling" call, which is loosely defined to
2160 // be a tail call that doesn't require heroics like moving the return
2161 // address or swapping byval arguments. We treat some musttail calls as
2162 // sibling calls to avoid unnecessary argument copies.
2163 bool IsMustTail = CLI.CB && CLI.CB->isMustTailCall();
2164 bool IsSibcall = false;
2165 if (isTailCall) {
2166 IsSibcall = isEligibleForSiblingCallOpt(CLI, CCInfo, ArgLocs);
2167 isTailCall = IsSibcall || IsMustTail || ShouldGuaranteeTCO;
2168 }
2169
2170 if (isTailCall)
2171 ++NumTailCalls;
2172
2173 if (IsMustTail && !isTailCall)
2174 report_fatal_error(reason: "failed to perform tail call elimination on a call "
2175 "site marked musttail");
2176
2177 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
2178 "Var args not supported with calling convention fastcc, ghc or hipe");
2179
2180 // Get a count of how many bytes are to be pushed on the stack.
2181 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
2182 if (IsSibcall)
2183 // This is a sibcall. The memory operands are available in caller's
2184 // own caller's stack.
2185 NumBytes = 0;
2186 else if (ShouldGuaranteeTCO && canGuaranteeTCO(CC: CallConv))
2187 NumBytes = GetAlignedArgumentStackSize(StackSize: NumBytes, DAG);
2188
2189 // A sibcall is ABI-compatible and does not need to adjust the stack pointer.
2190 int FPDiff = 0;
2191 if (isTailCall && ShouldGuaranteeTCO && !IsSibcall) {
2192 // Lower arguments at fp - stackoffset + fpdiff.
2193 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2194
2195 FPDiff = NumBytesCallerPushed - NumBytes;
2196
2197 // Set the delta of movement of the returnaddr stackslot.
2198 // But only set if delta is greater than previous delta.
2199 if (FPDiff < X86Info->getTCReturnAddrDelta())
2200 X86Info->setTCReturnAddrDelta(FPDiff);
2201 }
2202
2203 unsigned NumBytesToPush = NumBytes;
2204 unsigned NumBytesToPop = NumBytes;
2205
2206 SDValue StackPtr;
2207 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
2208
2209 // If we are doing a tail-call, any byval arguments will be written to stack
2210 // space which was used for incoming arguments. If any the values being used
2211 // are incoming byval arguments to this function, then they might be
2212 // overwritten by the stores of the outgoing arguments. To avoid this, we
2213 // need to make a temporary copy of them in local stack space, then copy back
2214 // to the argument area.
2215 // FIXME: There's potential to improve the code by using virtual registers for
2216 // temporary storage, and letting the register allocator spill if needed.
2217 SmallVector<SDValue, 8> ByValTemporaries;
2218 SDValue ByValTempChain;
2219 if (isTailCall) {
2220 // Use null SDValue to mean "no temporary recorded for this arg index".
2221 ByValTemporaries.assign(NumElts: OutVals.size(), Elt: SDValue());
2222
2223 SmallVector<SDValue, 8> ByValCopyChains;
2224 for (const CCValAssign &VA : ArgLocs) {
2225 unsigned ArgIdx = VA.getValNo();
2226 SDValue Src = OutVals[ArgIdx];
2227 ISD::ArgFlagsTy Flags = Outs[ArgIdx].Flags;
2228
2229 if (!Flags.isByVal())
2230 continue;
2231
2232 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
2233
2234 if (!StackPtr.getNode())
2235 StackPtr =
2236 DAG.getCopyFromReg(Chain, dl, Reg: RegInfo->getStackRegister(), VT: PtrVT);
2237
2238 // Destination: where this byval should live in the callee’s frame
2239 // after the tail call.
2240 int64_t Offset = VA.getLocMemOffset() + FPDiff;
2241 uint64_t Size = VA.getLocVT().getFixedSizeInBits() / 8;
2242 int FI = MF.getFrameInfo().CreateFixedObject(Size, SPOffset: Offset,
2243 /*IsImmutable=*/true);
2244 SDValue Dst = DAG.getFrameIndex(FI, VT: PtrVT);
2245
2246 ByValCopyKind Copy = ByValNeedsCopyForTailCall(DAG, Src, Dst, Flags);
2247
2248 if (Copy == NoCopy) {
2249 // If the argument is already at the correct offset on the stack
2250 // (because we are forwarding a byval argument from our caller), we
2251 // don't need any copying.
2252 continue;
2253 } else if (Copy == CopyOnce) {
2254 // If the argument is in our local stack frame, no other argument
2255 // preparation can clobber it, so we can copy it to the final location
2256 // later.
2257 ByValTemporaries[ArgIdx] = Src;
2258 } else {
2259 assert(Copy == CopyViaTemp && "unexpected enum value");
2260 // If we might be copying this argument from the outgoing argument
2261 // stack area, we need to copy via a temporary in the local stack
2262 // frame.
2263 MachineFrameInfo &MFI = MF.getFrameInfo();
2264 int TempFrameIdx = MFI.CreateStackObject(Size: Flags.getByValSize(),
2265 Alignment: Flags.getNonZeroByValAlign(),
2266 /*isSS=*/isSpillSlot: false);
2267 SDValue Temp =
2268 DAG.getFrameIndex(FI: TempFrameIdx, VT: getPointerTy(DL: DAG.getDataLayout()));
2269
2270 SDValue CopyChain =
2271 CreateCopyOfByValArgument(Src, Dst: Temp, Chain, Flags, DAG, dl);
2272 ByValCopyChains.push_back(Elt: CopyChain);
2273 ByValTemporaries[ArgIdx] = Temp;
2274 }
2275 }
2276 if (!ByValCopyChains.empty())
2277 ByValTempChain =
2278 DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: ByValCopyChains);
2279 }
2280
2281 // If we have an inalloca argument, all stack space has already been allocated
2282 // for us and be right at the top of the stack. We don't support multiple
2283 // arguments passed in memory when using inalloca.
2284 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2285 NumBytesToPush = 0;
2286 if (!ArgLocs.back().isMemLoc())
2287 report_fatal_error(reason: "cannot use inalloca attribute on a register "
2288 "parameter");
2289 if (ArgLocs.back().getLocMemOffset() != 0)
2290 report_fatal_error(reason: "any parameter with the inalloca attribute must be "
2291 "the only memory argument");
2292 } else if (CLI.IsPreallocated) {
2293 assert(ArgLocs.back().isMemLoc() &&
2294 "cannot use preallocated attribute on a register "
2295 "parameter");
2296 SmallVector<size_t, 4> PreallocatedOffsets;
2297 for (size_t i = 0; i < CLI.OutVals.size(); ++i) {
2298 if (CLI.CB->paramHasAttr(ArgNo: i, Kind: Attribute::Preallocated)) {
2299 PreallocatedOffsets.push_back(Elt: ArgLocs[i].getLocMemOffset());
2300 }
2301 }
2302 auto *MFI = DAG.getMachineFunction().getInfo<X86MachineFunctionInfo>();
2303 size_t PreallocatedId = MFI->getPreallocatedIdForCallSite(CS: CLI.CB);
2304 MFI->setPreallocatedStackSize(Id: PreallocatedId, StackSize: NumBytes);
2305 MFI->setPreallocatedArgOffsets(Id: PreallocatedId, AO: PreallocatedOffsets);
2306 NumBytesToPush = 0;
2307 }
2308
2309 if (!IsSibcall && !IsMustTail)
2310 Chain = DAG.getCALLSEQ_START(Chain, InSize: NumBytesToPush,
2311 OutSize: NumBytes - NumBytesToPush, DL: dl);
2312
2313 SDValue RetAddrFrIdx;
2314 // Load return address for tail calls.
2315 if (isTailCall && FPDiff)
2316 Chain = EmitTailCallLoadRetAddr(DAG, OutRetAddr&: RetAddrFrIdx, Chain, IsTailCall: isTailCall,
2317 Is64Bit, FPDiff, dl);
2318
2319 SmallVector<std::pair<Register, SDValue>, 8> RegsToPass;
2320 SmallVector<SDValue, 8> MemOpChains;
2321
2322 // The next loop assumes that the locations are in the same order of the
2323 // input arguments.
2324 assert(isSortedByValueNo(ArgLocs) &&
2325 "Argument Location list must be sorted before lowering");
2326
2327 // Walk the register/memloc assignments, inserting copies/loads. In the case
2328 // of tail call optimization arguments are handle later.
2329 for (unsigned I = 0, OutIndex = 0, E = ArgLocs.size(); I != E;
2330 ++I, ++OutIndex) {
2331 assert(OutIndex < Outs.size() && "Invalid Out index");
2332 // Skip inalloca/preallocated arguments, they have already been written.
2333 ISD::ArgFlagsTy Flags = Outs[OutIndex].Flags;
2334 if (Flags.isInAlloca() || Flags.isPreallocated())
2335 continue;
2336
2337 CCValAssign &VA = ArgLocs[I];
2338 EVT RegVT = VA.getLocVT();
2339 SDValue Arg = OutVals[OutIndex];
2340 bool isByVal = Flags.isByVal();
2341
2342 // Promote the value if needed.
2343 switch (VA.getLocInfo()) {
2344 default: llvm_unreachable("Unknown loc info!");
2345 case CCValAssign::Full: break;
2346 case CCValAssign::SExt:
2347 Arg = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL: dl, VT: RegVT, Operand: Arg);
2348 break;
2349 case CCValAssign::ZExt:
2350 Arg = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: RegVT, Operand: Arg);
2351 break;
2352 case CCValAssign::AExt:
2353 if (Arg.getValueType().isVector() &&
2354 Arg.getValueType().getVectorElementType() == MVT::i1)
2355 Arg = lowerMasksToReg(ValArg: Arg, ValLoc: RegVT, DL: dl, DAG);
2356 else if (RegVT.is128BitVector()) {
2357 // Special case: passing MMX values in XMM registers.
2358 Arg = DAG.getBitcast(VT: MVT::i64, V: Arg);
2359 Arg = DAG.getNode(Opcode: ISD::SCALAR_TO_VECTOR, DL: dl, VT: MVT::v2i64, Operand: Arg);
2360 Arg = getMOVL(DAG, dl, VT: MVT::v2i64, V1: DAG.getUNDEF(VT: MVT::v2i64), V2: Arg);
2361 } else
2362 Arg = DAG.getNode(Opcode: ISD::ANY_EXTEND, DL: dl, VT: RegVT, Operand: Arg);
2363 break;
2364 case CCValAssign::BCvt:
2365 Arg = DAG.getBitcast(VT: RegVT, V: Arg);
2366 break;
2367 case CCValAssign::Indirect: {
2368 if (isByVal) {
2369 // Memcpy the argument to a temporary stack slot to prevent
2370 // the caller from seeing any modifications the callee may make
2371 // as guaranteed by the `byval` attribute.
2372 int FrameIdx = MF.getFrameInfo().CreateStackObject(
2373 Size: Flags.getByValSize(),
2374 Alignment: std::max(a: Align(16), b: Flags.getNonZeroByValAlign()), isSpillSlot: false);
2375 SDValue StackSlot =
2376 DAG.getFrameIndex(FI: FrameIdx, VT: getPointerTy(DL: DAG.getDataLayout()));
2377 Chain =
2378 CreateCopyOfByValArgument(Src: Arg, Dst: StackSlot, Chain, Flags, DAG, dl);
2379 // From now on treat this as a regular pointer
2380 Arg = StackSlot;
2381 isByVal = false;
2382 } else {
2383 // Store the argument.
2384 SDValue SpillSlot = DAG.CreateStackTemporary(VT: VA.getValVT());
2385 int FI = cast<FrameIndexSDNode>(Val&: SpillSlot)->getIndex();
2386 Chain = DAG.getStore(
2387 Chain, dl, Val: Arg, Ptr: SpillSlot,
2388 PtrInfo: MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI));
2389 Arg = SpillSlot;
2390 }
2391 break;
2392 }
2393 }
2394
2395 if (VA.needsCustom()) {
2396 assert(VA.getValVT() == MVT::v64i1 &&
2397 "Currently the only custom case is when we split v64i1 to 2 regs");
2398 // Split v64i1 value into two registers
2399 Passv64i1ArgInRegs(DL: dl, DAG, Arg, RegsToPass, VA, NextVA&: ArgLocs[++I], Subtarget);
2400 } else if (VA.isRegLoc()) {
2401 RegsToPass.push_back(Elt: std::make_pair(x: VA.getLocReg(), y&: Arg));
2402 const TargetOptions &Options = DAG.getTarget().Options;
2403 if (Options.EmitCallSiteInfo)
2404 CSInfo.ArgRegPairs.emplace_back(Args: VA.getLocReg(), Args&: I);
2405 if (isVarArg && IsWin64) {
2406 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2407 // shadow reg if callee is a varargs function.
2408 Register ShadowReg;
2409 switch (VA.getLocReg()) {
2410 case X86::XMM0: ShadowReg = X86::RCX; break;
2411 case X86::XMM1: ShadowReg = X86::RDX; break;
2412 case X86::XMM2: ShadowReg = X86::R8; break;
2413 case X86::XMM3: ShadowReg = X86::R9; break;
2414 }
2415 if (ShadowReg)
2416 RegsToPass.push_back(Elt: std::make_pair(x&: ShadowReg, y&: Arg));
2417 }
2418 } else if (!IsSibcall && (!isTailCall || (isByVal && !IsMustTail))) {
2419 assert(VA.isMemLoc());
2420 if (!StackPtr.getNode())
2421 StackPtr = DAG.getCopyFromReg(Chain, dl, Reg: RegInfo->getStackRegister(),
2422 VT: getPointerTy(DL: DAG.getDataLayout()));
2423 MemOpChains.push_back(Elt: LowerMemOpCallTo(Chain, StackPtr, Arg,
2424 dl, DAG, VA, Flags, isByVal));
2425 }
2426 }
2427
2428 if (!MemOpChains.empty())
2429 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: MemOpChains);
2430
2431 if (Subtarget.isPICStyleGOT()) {
2432 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2433 // GOT pointer.
2434 if (!isTailCall) {
2435 // Only PLT calls (GlobalAddress or ExternalSymbol) require the GOT in
2436 // EBX. Indirect calls through a register or an absolute address do not
2437 // go through the PLT and do not need EBX to hold the GOT base.
2438 if ((Callee->getOpcode() == ISD::GlobalAddress ||
2439 Callee->getOpcode() == ISD::ExternalSymbol))
2440 RegsToPass.push_back(Elt: std::make_pair(
2441 x: Register(X86::EBX), y: DAG.getNode(Opcode: X86ISD::GlobalBaseReg, DL: SDLoc(),
2442 VT: getPointerTy(DL: DAG.getDataLayout()))));
2443 } else {
2444 // If we are tail calling and generating PIC/GOT style code load the
2445 // address of the callee into ECX. The value in ecx is used as target of
2446 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2447 // for tail calls on PIC/GOT architectures. Normally we would just put the
2448 // address of GOT into ebx and then call target@PLT. But for tail calls
2449 // ebx would be restored (since ebx is callee saved) before jumping to the
2450 // target@PLT.
2451
2452 // Note: The actual moving to ECX is done further down.
2453 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Val&: Callee);
2454 if (G && !G->getGlobal()->hasLocalLinkage() &&
2455 G->getGlobal()->hasDefaultVisibility())
2456 Callee = LowerGlobalAddress(Op: Callee, DAG);
2457 else if (isa<ExternalSymbolSDNode>(Val: Callee))
2458 Callee = LowerExternalSymbol(Op: Callee, DAG);
2459 }
2460 }
2461
2462 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail &&
2463 (Subtarget.hasSSE1() || !M->getModuleFlag(Key: "SkipRaxSetup"))) {
2464 // From AMD64 ABI document:
2465 // For calls that may call functions that use varargs or stdargs
2466 // (prototype-less calls or calls to functions containing ellipsis (...) in
2467 // the declaration) %al is used as hidden argument to specify the number
2468 // of SSE registers used. The contents of %al do not need to match exactly
2469 // the number of registers, but must be an ubound on the number of SSE
2470 // registers used and is in the range 0 - 8 inclusive.
2471
2472 // Count the number of XMM registers allocated.
2473 static const MCPhysReg XMMArgRegs[] = {
2474 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2475 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2476 };
2477 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(Regs: XMMArgRegs);
2478 assert((Subtarget.hasSSE1() || !NumXMMRegs)
2479 && "SSE registers cannot be used when SSE is disabled");
2480 RegsToPass.push_back(Elt: std::make_pair(x: Register(X86::AL),
2481 y: DAG.getConstant(Val: NumXMMRegs, DL: dl,
2482 VT: MVT::i8)));
2483 }
2484
2485 if (isVarArg && IsMustTail) {
2486 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2487 for (const auto &F : Forwards) {
2488 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg: F.VReg, VT: F.VT);
2489 RegsToPass.push_back(Elt: std::make_pair(x: F.PReg, y&: Val));
2490 }
2491 }
2492
2493 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2494 // don't need this because the eligibility check rejects calls that require
2495 // shuffling arguments passed in memory.
2496 if (isTailCall && !IsSibcall) {
2497 // Force all the incoming stack arguments to be loaded from the stack
2498 // before any new outgoing arguments or the return address are stored to the
2499 // stack, because the outgoing stack slots may alias the incoming argument
2500 // stack slots, and the alias isn't otherwise explicit. This is slightly
2501 // more conservative than necessary, because it means that each store
2502 // effectively depends on every argument instead of just those arguments it
2503 // would clobber.
2504 Chain = DAG.getStackArgumentTokenFactor(Chain);
2505
2506 if (ByValTempChain)
2507 Chain =
2508 DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, N1: Chain, N2: ByValTempChain);
2509
2510 SmallVector<SDValue, 8> MemOpChains2;
2511 SDValue FIN;
2512 int FI = 0;
2513 for (unsigned I = 0, OutsIndex = 0, E = ArgLocs.size(); I != E;
2514 ++I, ++OutsIndex) {
2515 CCValAssign &VA = ArgLocs[I];
2516
2517 if (VA.isRegLoc()) {
2518 if (VA.needsCustom()) {
2519 assert((CallConv == CallingConv::X86_RegCall) &&
2520 "Expecting custom case only in regcall calling convention");
2521 // This means that we are in special case where one argument was
2522 // passed through two register locations - Skip the next location
2523 ++I;
2524 }
2525
2526 continue;
2527 }
2528
2529 assert(VA.isMemLoc());
2530 SDValue Arg = OutVals[OutsIndex];
2531 ISD::ArgFlagsTy Flags = Outs[OutsIndex].Flags;
2532 // Skip inalloca/preallocated arguments. They don't require any work.
2533 if (Flags.isInAlloca() || Flags.isPreallocated())
2534 continue;
2535 // Create frame index.
2536 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2537 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2538 FI = MF.getFrameInfo().CreateFixedObject(Size: OpSize, SPOffset: Offset, IsImmutable: true);
2539 FIN = DAG.getFrameIndex(FI, VT: getPointerTy(DL: DAG.getDataLayout()));
2540
2541 if (Flags.isByVal()) {
2542 if (SDValue ByValSrc = ByValTemporaries[OutsIndex]) {
2543 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
2544 SDValue DstAddr = DAG.getFrameIndex(FI, VT: PtrVT);
2545
2546 MemOpChains2.push_back(Elt: CreateCopyOfByValArgument(
2547 Src: ByValSrc, Dst: DstAddr, Chain, Flags, DAG, dl));
2548 }
2549 } else {
2550 // Store relative to framepointer.
2551 MemOpChains2.push_back(Elt: DAG.getStore(
2552 Chain, dl, Val: Arg, Ptr: FIN,
2553 PtrInfo: MachinePointerInfo::getFixedStack(MF&: DAG.getMachineFunction(), FI)));
2554 }
2555 }
2556
2557 if (!MemOpChains2.empty())
2558 Chain = DAG.getNode(Opcode: ISD::TokenFactor, DL: dl, VT: MVT::Other, Ops: MemOpChains2);
2559
2560 // Store the return address to the appropriate stack slot.
2561 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2562 PtrVT: getPointerTy(DL: DAG.getDataLayout()),
2563 SlotSize: RegInfo->getSlotSize(), FPDiff, dl);
2564 }
2565
2566 // Build a sequence of copy-to-reg nodes chained together with token chain
2567 // and glue operands which copy the outgoing args into registers.
2568 SDValue InGlue;
2569 for (const auto &[Reg, N] : RegsToPass) {
2570 Chain = DAG.getCopyToReg(Chain, dl, Reg, N, Glue: InGlue);
2571 InGlue = Chain.getValue(R: 1);
2572 }
2573
2574 bool IsImpCall = false;
2575 bool IsCFGuardCall = false;
2576 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
2577 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2578 // In the 64-bit large code model, we have to make all calls
2579 // through a register, since the call instruction's 32-bit
2580 // pc-relative offset may not be large enough to hold the whole
2581 // address.
2582 } else if (Callee->getOpcode() == ISD::GlobalAddress ||
2583 Callee->getOpcode() == ISD::ExternalSymbol) {
2584 // Lower direct calls to global addresses and external symbols. Setting
2585 // ForCall to true here has the effect of removing WrapperRIP when possible
2586 // to allow direct calls to be selected without first materializing the
2587 // address into a register.
2588 Callee = LowerGlobalOrExternal(Op: Callee, DAG, /*ForCall=*/true, IsImpCall: &IsImpCall);
2589 } else if (Subtarget.isTarget64BitILP32() &&
2590 Callee.getValueType() == MVT::i32) {
2591 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
2592 Callee = DAG.getNode(Opcode: ISD::ZERO_EXTEND, DL: dl, VT: MVT::i64, Operand: Callee);
2593 } else if (Is64Bit && CB && isCFGuardCall(CB)) {
2594 // We'll use a specific psuedo instruction for tail calls to control flow
2595 // guard functions to guarantee the instruction used for the call. To do
2596 // this we need to unwrap the load now and use the CFG Func GV as the
2597 // callee.
2598 IsCFGuardCall = true;
2599 auto *LoadNode = cast<LoadSDNode>(Val&: Callee);
2600 GlobalAddressSDNode *GA =
2601 cast<GlobalAddressSDNode>(Val: unwrapAddress(N: LoadNode->getBasePtr()));
2602 assert(isCFGuardFunction(GA->getGlobal()) &&
2603 "CFG Call should be to a guard function");
2604 assert(LoadNode->getOffset()->isUndef() &&
2605 "CFG Function load should not have an offset");
2606 Callee = DAG.getTargetGlobalAddress(
2607 GV: GA->getGlobal(), DL: dl, VT: GA->getValueType(ResNo: 0), offset: 0, TargetFlags: X86II::MO_NO_FLAG);
2608 }
2609
2610 SmallVector<SDValue, 8> Ops;
2611
2612 if (!IsSibcall && isTailCall && !IsMustTail) {
2613 Chain = DAG.getCALLSEQ_END(Chain, Size1: NumBytesToPop, Size2: 0, Glue: InGlue, DL: dl);
2614 InGlue = Chain.getValue(R: 1);
2615 }
2616
2617 Ops.push_back(Elt: Chain);
2618 Ops.push_back(Elt: Callee);
2619
2620 if (isTailCall)
2621 Ops.push_back(Elt: DAG.getSignedTargetConstant(Val: FPDiff, DL: dl, VT: MVT::i32));
2622
2623 // Add argument registers to the end of the list so that they are known live
2624 // into the call.
2625 for (const auto &[Reg, N] : RegsToPass)
2626 Ops.push_back(Elt: DAG.getRegister(Reg, VT: N.getValueType()));
2627
2628 // Add a register mask operand representing the call-preserved registers.
2629 const uint32_t *Mask = [&]() {
2630 auto AdaptedCC = CallConv;
2631 // If HasNCSR is asserted (attribute NoCallerSavedRegisters exists),
2632 // use X86_INTR calling convention because it has the same CSR mask
2633 // (same preserved registers).
2634 if (HasNCSR)
2635 AdaptedCC = (CallingConv::ID)CallingConv::X86_INTR;
2636 // If NoCalleeSavedRegisters is requested, than use GHC since it happens
2637 // to use the CSR_NoRegs_RegMask.
2638 if (CB && CB->hasFnAttr(Kind: "no_callee_saved_registers"))
2639 AdaptedCC = (CallingConv::ID)CallingConv::GHC;
2640 return RegInfo->getCallPreservedMask(MF, AdaptedCC);
2641 }();
2642 assert(Mask && "Missing call preserved mask for calling convention");
2643
2644 if (MachineOperand::clobbersPhysReg(RegMask: Mask, PhysReg: RegInfo->getFramePtr())) {
2645 X86Info->setFPClobberedByCall(true);
2646 if (CLI.CB && isa<InvokeInst>(Val: CLI.CB))
2647 X86Info->setFPClobberedByInvoke(true);
2648 }
2649 if (MachineOperand::clobbersPhysReg(RegMask: Mask, PhysReg: RegInfo->getBaseRegister())) {
2650 X86Info->setBPClobberedByCall(true);
2651 if (CLI.CB && isa<InvokeInst>(Val: CLI.CB))
2652 X86Info->setBPClobberedByInvoke(true);
2653 }
2654
2655 // If this is an invoke in a 32-bit function using a funclet-based
2656 // personality, assume the function clobbers all registers. If an exception
2657 // is thrown, the runtime will not restore CSRs.
2658 // FIXME: Model this more precisely so that we can register allocate across
2659 // the normal edge and spill and fill across the exceptional edge.
2660 if (!Is64Bit && CLI.CB && isa<InvokeInst>(Val: CLI.CB)) {
2661 const Function &CallerFn = MF.getFunction();
2662 EHPersonality Pers =
2663 CallerFn.hasPersonalityFn()
2664 ? classifyEHPersonality(Pers: CallerFn.getPersonalityFn())
2665 : EHPersonality::Unknown;
2666 if (isFuncletEHPersonality(Pers))
2667 Mask = RegInfo->getNoPreservedMask();
2668 }
2669
2670 // Define a new register mask from the existing mask.
2671 uint32_t *RegMask = nullptr;
2672
2673 // In some calling conventions we need to remove the used physical registers
2674 // from the reg mask. Create a new RegMask for such calling conventions.
2675 // RegMask for calling conventions that disable only return registers (e.g.
2676 // preserve_most) will be modified later in LowerCallResult.
2677 bool ShouldDisableArgRegs = shouldDisableArgRegFromCSR(CC: CallConv) || HasNCSR;
2678 if (ShouldDisableArgRegs || shouldDisableRetRegFromCSR(CC: CallConv)) {
2679 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2680
2681 // Allocate a new Reg Mask and copy Mask.
2682 RegMask = MF.allocateRegMask();
2683 unsigned RegMaskSize = MachineOperand::getRegMaskSize(NumRegs: TRI->getNumRegs());
2684 memcpy(dest: RegMask, src: Mask, n: sizeof(RegMask[0]) * RegMaskSize);
2685
2686 // Make sure all sub registers of the argument registers are reset
2687 // in the RegMask.
2688 if (ShouldDisableArgRegs) {
2689 for (auto const &RegPair : RegsToPass)
2690 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg: RegPair.first))
2691 RegMask[SubReg / 32] &= ~(1u << (SubReg % 32));
2692 }
2693
2694 // Create the RegMask Operand according to our updated mask.
2695 Ops.push_back(Elt: DAG.getRegisterMask(RegMask));
2696 } else {
2697 // Create the RegMask Operand according to the static mask.
2698 Ops.push_back(Elt: DAG.getRegisterMask(RegMask: Mask));
2699 }
2700
2701 if (InGlue.getNode())
2702 Ops.push_back(Elt: InGlue);
2703
2704 if (isTailCall) {
2705 // We used to do:
2706 //// If this is the first return lowered for this function, add the regs
2707 //// to the liveout set for the function.
2708 // This isn't right, although it's probably harmless on x86; liveouts
2709 // should be computed from returns not tail calls. Consider a void
2710 // function making a tail call to a function returning int.
2711 MF.getFrameInfo().setHasTailCall();
2712 auto Opcode =
2713 IsCFGuardCall ? X86ISD::TC_RETURN_GLOBALADDR : X86ISD::TC_RETURN;
2714 SDValue Ret = DAG.getNode(Opcode, DL: dl, VT: MVT::Other, Ops);
2715
2716 if (IsCFICall)
2717 Ret.getNode()->setCFIType(CLI.CFIType->getZExtValue());
2718
2719 DAG.addNoMergeSiteInfo(Node: Ret.getNode(), NoMerge: CLI.NoMerge);
2720 DAG.addCallSiteInfo(Node: Ret.getNode(), CallInfo: std::move(CSInfo));
2721 return Ret;
2722 }
2723
2724 // Returns a chain & a glue for retval copy to use.
2725 SDVTList NodeTys = DAG.getVTList(VT1: MVT::Other, VT2: MVT::Glue);
2726 if (IsImpCall) {
2727 Chain = DAG.getNode(Opcode: X86ISD::IMP_CALL, DL: dl, VTList: NodeTys, Ops);
2728 } else if (IsNoTrackIndirectCall) {
2729 Chain = DAG.getNode(Opcode: X86ISD::NT_CALL, DL: dl, VTList: NodeTys, Ops);
2730 } else if (IsCFGuardCall) {
2731 Chain = DAG.getNode(Opcode: X86ISD::CALL_GLOBALADDR, DL: dl, VTList: NodeTys, Ops);
2732 } else if (CLI.CB && objcarc::hasAttachedCallOpBundle(CB: CLI.CB)) {
2733 // Calls with a "clang.arc.attachedcall" bundle are special. They should be
2734 // expanded to the call, directly followed by a special marker sequence and
2735 // a call to a ObjC library function. Use the CALL_RVMARKER to do that.
2736 assert(!isTailCall &&
2737 "tail calls cannot be marked with clang.arc.attachedcall");
2738 assert(Is64Bit && "clang.arc.attachedcall is only supported in 64bit mode");
2739
2740 // Add a target global address for the retainRV/claimRV runtime function
2741 // just before the call target.
2742 Function *ARCFn = *objcarc::getAttachedARCFunction(CB: CLI.CB);
2743 auto PtrVT = getPointerTy(DL: DAG.getDataLayout());
2744 auto GA = DAG.getTargetGlobalAddress(GV: ARCFn, DL: dl, VT: PtrVT);
2745 Ops.insert(I: Ops.begin() + 1, Elt: GA);
2746 Chain = DAG.getNode(Opcode: X86ISD::CALL_RVMARKER, DL: dl, VTList: NodeTys, Ops);
2747 } else {
2748 Chain = DAG.getNode(Opcode: X86ISD::CALL, DL: dl, VTList: NodeTys, Ops);
2749 }
2750
2751 if (IsCFICall)
2752 Chain.getNode()->setCFIType(CLI.CFIType->getZExtValue());
2753
2754 InGlue = Chain.getValue(R: 1);
2755 DAG.addNoMergeSiteInfo(Node: Chain.getNode(), NoMerge: CLI.NoMerge);
2756 DAG.addCallSiteInfo(Node: Chain.getNode(), CallInfo: std::move(CSInfo));
2757
2758 // Save heapallocsite metadata.
2759 if (CLI.CB)
2760 if (MDNode *HeapAlloc = CLI.CB->getMetadata(Kind: "heapallocsite"))
2761 DAG.addHeapAllocSite(Node: Chain.getNode(), MD: HeapAlloc);
2762
2763 // Create the CALLSEQ_END node.
2764 unsigned NumBytesForCalleeToPop = 0; // Callee pops nothing.
2765 if (X86::isCalleePop(CallingConv: CallConv, is64Bit: Is64Bit, IsVarArg: isVarArg,
2766 GuaranteeTCO: DAG.getTarget().Options.GuaranteedTailCallOpt)) {
2767 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
2768 } else if (hasCalleePopSRet(Args: Outs, ArgLocs, Subtarget)) {
2769 // If this call passes a struct-return pointer, the callee
2770 // pops that struct pointer.
2771 NumBytesForCalleeToPop = 4;
2772 }
2773
2774 // Returns a glue for retval copy to use.
2775 if (!IsSibcall) {
2776 Chain = DAG.getCALLSEQ_END(Chain, Size1: NumBytesToPop, Size2: NumBytesForCalleeToPop,
2777 Glue: InGlue, DL: dl);
2778 InGlue = Chain.getValue(R: 1);
2779 }
2780
2781 if (CallingConv::PreserveNone == CallConv)
2782 for (const ISD::OutputArg &Out : Outs) {
2783 if (Out.Flags.isSwiftSelf() || Out.Flags.isSwiftAsync() ||
2784 Out.Flags.isSwiftError()) {
2785 errorUnsupported(DAG, dl,
2786 Msg: "Swift attributes can't be used with preserve_none");
2787 break;
2788 }
2789 }
2790
2791 // Handle result values, copying them out of physregs into vregs that we
2792 // return.
2793 return LowerCallResult(Chain, InGlue, CallConv, isVarArg, Ins, dl, DAG,
2794 InVals, RegMask);
2795}
2796
2797//===----------------------------------------------------------------------===//
2798// Fast Calling Convention (tail call) implementation
2799//===----------------------------------------------------------------------===//
2800
2801// Like std call, callee cleans arguments, convention except that ECX is
2802// reserved for storing the tail called function address. Only 2 registers are
2803// free for argument passing (inreg). Tail call optimization is performed
2804// provided:
2805// * tailcallopt is enabled
2806// * caller/callee are fastcc
2807// On X86_64 architecture with GOT-style position independent code only local
2808// (within module) calls are supported at the moment.
2809// To keep the stack aligned according to platform abi the function
2810// GetAlignedArgumentStackSize ensures that argument delta is always multiples
2811// of stack alignment. (Dynamic linkers need this - Darwin's dyld for example)
2812// If a tail called function callee has more arguments than the caller the
2813// caller needs to make sure that there is room to move the RETADDR to. This is
2814// achieved by reserving an area the size of the argument delta right after the
2815// original RETADDR, but before the saved framepointer or the spilled registers
2816// e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2817// stack layout:
2818// arg1
2819// arg2
2820// RETADDR
2821// [ new RETADDR
2822// move area ]
2823// (possible EBP)
2824// ESI
2825// EDI
2826// local1 ..
2827
2828/// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
2829/// requirement.
2830unsigned
2831X86TargetLowering::GetAlignedArgumentStackSize(const unsigned StackSize,
2832 SelectionDAG &DAG) const {
2833 const Align StackAlignment = Subtarget.getFrameLowering()->getStackAlign();
2834 const uint64_t SlotSize = Subtarget.getRegisterInfo()->getSlotSize();
2835 assert(StackSize % SlotSize == 0 &&
2836 "StackSize must be a multiple of SlotSize");
2837 return alignTo(Size: StackSize + SlotSize, A: StackAlignment) - SlotSize;
2838}
2839
2840/// Return true if the given stack call argument is already available in the
2841/// same position (relatively) of the caller's incoming argument stack.
2842static
2843bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2844 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
2845 const X86InstrInfo *TII, const CCValAssign &VA) {
2846 unsigned Bytes = Arg.getValueSizeInBits() / 8;
2847
2848 for (;;) {
2849 // Look through nodes that don't alter the bits of the incoming value.
2850 unsigned Op = Arg.getOpcode();
2851 if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST ||
2852 Op == ISD::AssertZext) {
2853 Arg = Arg.getOperand(i: 0);
2854 continue;
2855 }
2856 if (Op == ISD::TRUNCATE) {
2857 const SDValue &TruncInput = Arg.getOperand(i: 0);
2858 if (TruncInput.getOpcode() == ISD::AssertZext &&
2859 cast<VTSDNode>(Val: TruncInput.getOperand(i: 1))->getVT() ==
2860 Arg.getValueType()) {
2861 Arg = TruncInput.getOperand(i: 0);
2862 continue;
2863 }
2864 }
2865 break;
2866 }
2867
2868 int FI = INT_MAX;
2869 if (Arg.getOpcode() == ISD::CopyFromReg) {
2870 Register VR = cast<RegisterSDNode>(Val: Arg.getOperand(i: 1))->getReg();
2871 if (!VR.isVirtual())
2872 return false;
2873 MachineInstr *Def = MRI->getVRegDef(Reg: VR);
2874 if (!Def)
2875 return false;
2876 if (!Flags.isByVal()) {
2877 if (!TII->isLoadFromStackSlot(MI: *Def, FrameIndex&: FI))
2878 return false;
2879 } else {
2880 unsigned Opcode = Def->getOpcode();
2881 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
2882 Opcode == X86::LEA64_32r) &&
2883 Def->getOperand(i: 1).isFI()) {
2884 FI = Def->getOperand(i: 1).getIndex();
2885 Bytes = Flags.getByValSize();
2886 } else
2887 return false;
2888 }
2889 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Val&: Arg)) {
2890 if (Flags.isByVal())
2891 // ByVal argument is passed in as a pointer but it's now being
2892 // dereferenced. e.g.
2893 // define @foo(%struct.X* %A) {
2894 // tail call @bar(%struct.X* byval %A)
2895 // }
2896 return false;
2897 SDValue Ptr = Ld->getBasePtr();
2898 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Val&: Ptr);
2899 if (!FINode)
2900 return false;
2901 FI = FINode->getIndex();
2902 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2903 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Val&: Arg);
2904 FI = FINode->getIndex();
2905 Bytes = Flags.getByValSize();
2906 } else
2907 return false;
2908
2909 assert(FI != INT_MAX);
2910 if (!MFI.isFixedObjectIndex(ObjectIdx: FI))
2911 return false;
2912
2913 if (Offset != MFI.getObjectOffset(ObjectIdx: FI))
2914 return false;
2915
2916 // If this is not byval, check that the argument stack object is immutable.
2917 // inalloca and argument copy elision can create mutable argument stack
2918 // objects. Byval objects can be mutated, but a byval call intends to pass the
2919 // mutated memory.
2920 if (!Flags.isByVal() && !MFI.isImmutableObjectIndex(ObjectIdx: FI))
2921 return false;
2922
2923 if (VA.getLocVT().getFixedSizeInBits() >
2924 Arg.getValueSizeInBits().getFixedValue()) {
2925 // If the argument location is wider than the argument type, check that any
2926 // extension flags match.
2927 if (Flags.isZExt() != MFI.isObjectZExt(ObjectIdx: FI) ||
2928 Flags.isSExt() != MFI.isObjectSExt(ObjectIdx: FI)) {
2929 return false;
2930 }
2931 }
2932
2933 return Bytes == MFI.getObjectSize(ObjectIdx: FI);
2934}
2935
2936static bool
2937mayBeSRetTailCallCompatible(const TargetLowering::CallLoweringInfo &CLI,
2938 Register CallerSRetReg) {
2939 const auto &Outs = CLI.Outs;
2940 const auto &OutVals = CLI.OutVals;
2941
2942 // We know the caller has a sret pointer argument (CallerSRetReg). Locate the
2943 // operand index within the callee that may have a sret pointer too.
2944 unsigned Pos = 0;
2945 for (unsigned E = Outs.size(); Pos != E; ++Pos)
2946 if (Outs[Pos].Flags.isSRet())
2947 break;
2948 // Bail out if the callee has not any sret argument.
2949 if (Pos == Outs.size())
2950 return false;
2951
2952 // At this point, either the caller is forwarding its sret argument to the
2953 // callee, or the callee is being passed a different sret pointer. We now look
2954 // for a CopyToReg, where the callee sret argument is written into a new vreg
2955 // (which should later be %rax/%eax, if this is returned).
2956 SDValue SRetArgVal = OutVals[Pos];
2957 for (SDNode *User : SRetArgVal->users()) {
2958 if (User->getOpcode() != ISD::CopyToReg)
2959 continue;
2960 Register Reg = cast<RegisterSDNode>(Val: User->getOperand(Num: 1))->getReg();
2961 if (Reg == CallerSRetReg && User->getOperand(Num: 2) == SRetArgVal)
2962 return true;
2963 }
2964
2965 return false;
2966}
2967
2968/// Check whether the call is eligible for sibling call optimization. Sibling
2969/// calls are loosely defined to be simple, profitable tail calls that only
2970/// require adjusting register parameters. We do not speculatively to optimize
2971/// complex calls that require lots of argument memory operations that may
2972/// alias.
2973///
2974/// Note that LLVM supports multiple ways, such as musttail, to force tail call
2975/// emission. Returning false from this function will not prevent tail call
2976/// emission in all cases.
2977bool X86TargetLowering::isEligibleForSiblingCallOpt(
2978 TargetLowering::CallLoweringInfo &CLI, CCState &CCInfo,
2979 SmallVectorImpl<CCValAssign> &ArgLocs) const {
2980 SelectionDAG &DAG = CLI.DAG;
2981 const SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2982 const SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2983 const SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2984 SDValue Callee = CLI.Callee;
2985 CallingConv::ID CalleeCC = CLI.CallConv;
2986 bool isVarArg = CLI.IsVarArg;
2987
2988 if (!mayTailCallThisCC(CC: CalleeCC))
2989 return false;
2990
2991 // If -tailcallopt is specified, make fastcc functions tail-callable.
2992 MachineFunction &MF = DAG.getMachineFunction();
2993 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2994 const Function &CallerF = MF.getFunction();
2995
2996 // If the function return type is x86_fp80 and the callee return type is not,
2997 // then the FP_EXTEND of the call result is not a nop. It's not safe to
2998 // perform a tailcall optimization here.
2999 if (CallerF.getReturnType()->isX86_FP80Ty() && !CLI.RetTy->isX86_FP80Ty())
3000 return false;
3001
3002 // Win64 functions have extra shadow space for argument homing. Don't do the
3003 // sibcall if the caller and callee have mismatched expectations for this
3004 // space.
3005 CallingConv::ID CallerCC = CallerF.getCallingConv();
3006 bool IsCalleeWin64 = Subtarget.isCallingConvWin64(CC: CalleeCC);
3007 bool IsCallerWin64 = Subtarget.isCallingConvWin64(CC: CallerCC);
3008 if (IsCalleeWin64 != IsCallerWin64)
3009 return false;
3010
3011 // Do not optimize vararg calls with 6 arguments for LFI since LFI reserves
3012 // %r11, meaning there will not be enough registers available.
3013 if (Subtarget.isLFI() && ArgLocs.size() > 5)
3014 return false;
3015
3016 // If we are using a GOT, don't generate sibling calls to non-local,
3017 // default-visibility symbols. Tail calling such a symbol requires using a GOT
3018 // relocation, which forces early binding of the symbol. This breaks code that
3019 // require lazy function symbol resolution. Using musttail or
3020 // GuaranteedTailCallOpt will override this.
3021 if (Subtarget.isPICStyleGOT()) {
3022 if (isa<ExternalSymbolSDNode>(Val: Callee))
3023 return false;
3024 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Val&: Callee)) {
3025 if (!G->getGlobal()->hasLocalLinkage() &&
3026 G->getGlobal()->hasDefaultVisibility())
3027 return false;
3028 }
3029 }
3030
3031 // Look for obvious safe cases to perform tail call optimization that do not
3032 // require ABI changes. This is what gcc calls sibcall.
3033
3034 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3035 // emit a special epilogue.
3036 const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
3037 if (RegInfo->hasStackRealignment(MF))
3038 return false;
3039
3040 // Avoid sibcall optimization if we are an sret return function and the callee
3041 // is incompatible, unless such premises are proven wrong. See comment in
3042 // LowerReturn about why hasStructRetAttr is insufficient.
3043 if (Register SRetReg = FuncInfo->getSRetReturnReg()) {
3044 // For a compatible tail call the callee must return our sret pointer. So it
3045 // needs to be (a) an sret function itself and (b) we pass our sret as its
3046 // sret. Condition #b is harder to determine.
3047 if (!mayBeSRetTailCallCompatible(CLI, CallerSRetReg: SRetReg))
3048 return false;
3049 } else if (hasCalleePopSRet(Args: Outs, ArgLocs, Subtarget))
3050 // The callee pops an sret, so we cannot tail-call, as our caller doesn't
3051 // expect that.
3052 return false;
3053
3054 // Do not sibcall optimize vararg calls unless all arguments are passed via
3055 // registers.
3056 LLVMContext &C = *DAG.getContext();
3057 if (isVarArg && !Outs.empty()) {
3058 // Optimizing for varargs on Win64 is unlikely to be safe without
3059 // additional testing.
3060 if (IsCalleeWin64 || IsCallerWin64)
3061 return false;
3062
3063 for (const auto &VA : ArgLocs)
3064 if (!VA.isRegLoc())
3065 return false;
3066 }
3067
3068 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3069 // stack. Therefore, if it's not used by the call it is not safe to optimize
3070 // this into a sibcall.
3071 bool Unused = false;
3072 for (const auto &In : Ins) {
3073 if (!In.Used) {
3074 Unused = true;
3075 break;
3076 }
3077 }
3078 if (Unused) {
3079 SmallVector<CCValAssign, 16> RVLocs;
3080 CCState RVCCInfo(CalleeCC, false, MF, RVLocs, C);
3081 RVCCInfo.AnalyzeCallResult(Ins, Fn: RetCC_X86);
3082 for (const auto &VA : RVLocs) {
3083 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3084 return false;
3085 }
3086 }
3087
3088 // Check that the call results are passed in the same way.
3089 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins,
3090 CalleeFn: RetCC_X86, CallerFn: RetCC_X86))
3091 return false;
3092 // The callee has to preserve all registers the caller needs to preserve.
3093 const X86RegisterInfo *TRI = Subtarget.getRegisterInfo();
3094 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
3095 if (CallerCC != CalleeCC) {
3096 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
3097 if (!TRI->regmaskSubsetEqual(mask0: CallerPreserved, mask1: CalleePreserved))
3098 return false;
3099 }
3100
3101 // The stack frame of the caller cannot be replaced by the tail-callee one's
3102 // if the function is required to preserve all the registers. Conservatively
3103 // prevent tail optimization even if hypothetically all the registers are used
3104 // for passing formal parameters or returning values.
3105 if (CallerF.hasFnAttribute(Kind: "no_caller_saved_registers"))
3106 return false;
3107
3108 unsigned StackArgsSize = CCInfo.getStackSize();
3109
3110 // If the callee takes no arguments then go on to check the results of the
3111 // call.
3112 if (!Outs.empty()) {
3113 if (StackArgsSize > 0) {
3114 // Check if the arguments are already laid out in the right way as
3115 // the caller's fixed stack objects.
3116 MachineFrameInfo &MFI = MF.getFrameInfo();
3117 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3118 const X86InstrInfo *TII = Subtarget.getInstrInfo();
3119 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
3120 const CCValAssign &VA = ArgLocs[I];
3121 SDValue Arg = OutVals[I];
3122 ISD::ArgFlagsTy Flags = Outs[I].Flags;
3123 if (VA.getLocInfo() == CCValAssign::Indirect)
3124 return false;
3125 if (!VA.isRegLoc()) {
3126 if (!MatchingStackOffset(Arg, Offset: VA.getLocMemOffset(), Flags, MFI, MRI,
3127 TII, VA))
3128 return false;
3129 }
3130 }
3131 }
3132
3133 bool PositionIndependent = isPositionIndependent();
3134 // If the tailcall address may be in a register, then make sure it's
3135 // possible to register allocate for it. In 32-bit, the call address can
3136 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3137 // callee-saved registers are restored. These happen to be the same
3138 // registers used to pass 'inreg' arguments so watch out for those.
3139 if (!Subtarget.is64Bit() && ((!isa<GlobalAddressSDNode>(Val: Callee) &&
3140 !isa<ExternalSymbolSDNode>(Val: Callee)) ||
3141 PositionIndependent)) {
3142 unsigned NumInRegs = 0;
3143 // In PIC we need an extra register to formulate the address computation
3144 // for the callee.
3145 unsigned MaxInRegs = PositionIndependent ? 2 : 3;
3146
3147 for (const auto &VA : ArgLocs) {
3148 if (!VA.isRegLoc())
3149 continue;
3150 Register Reg = VA.getLocReg();
3151 switch (Reg) {
3152 default: break;
3153 case X86::EAX: case X86::EDX: case X86::ECX:
3154 if (++NumInRegs == MaxInRegs)
3155 return false;
3156 break;
3157 }
3158 }
3159 }
3160
3161 const MachineRegisterInfo &MRI = MF.getRegInfo();
3162 if (!parametersInCSRMatch(MRI, CallerPreservedMask: CallerPreserved, ArgLocs, OutVals))
3163 return false;
3164 }
3165
3166 bool CalleeWillPop =
3167 X86::isCalleePop(CallingConv: CalleeCC, is64Bit: Subtarget.is64Bit(), IsVarArg: isVarArg,
3168 GuaranteeTCO: MF.getTarget().Options.GuaranteedTailCallOpt);
3169
3170 if (unsigned BytesToPop = FuncInfo->getBytesToPopOnReturn()) {
3171 // If we have bytes to pop, the callee must pop them.
3172 bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
3173 if (!CalleePopMatches)
3174 return false;
3175 } else if (CalleeWillPop && StackArgsSize > 0) {
3176 // If we don't have bytes to pop, make sure the callee doesn't pop any.
3177 return false;
3178 }
3179
3180 return true;
3181}
3182
3183/// Determines whether the callee is required to pop its own arguments.
3184/// Callee pop is necessary to support tail calls.
3185bool X86::isCalleePop(CallingConv::ID CallingConv,
3186 bool is64Bit, bool IsVarArg, bool GuaranteeTCO) {
3187 // If GuaranteeTCO is true, we force some calls to be callee pop so that we
3188 // can guarantee TCO.
3189 if (!IsVarArg && shouldGuaranteeTCO(CC: CallingConv, GuaranteedTailCallOpt: GuaranteeTCO))
3190 return true;
3191
3192 switch (CallingConv) {
3193 default:
3194 return false;
3195 case CallingConv::X86_StdCall:
3196 case CallingConv::X86_FastCall:
3197 case CallingConv::X86_ThisCall:
3198 case CallingConv::X86_VectorCall:
3199 return !is64Bit;
3200 }
3201}
3202