1//===- X86OptimizeLEAs.cpp - optimize usage of LEA instructions -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the pass that performs some optimizations with LEA
10// instructions in order to improve performance and code size.
11// Currently, it does two things:
12// 1) If there are two LEA instructions calculating addresses which only differ
13// by displacement inside a basic block, one of them is removed.
14// 2) Address calculations in load and store instructions are replaced by
15// existing LEA def registers where possible.
16//
17//===----------------------------------------------------------------------===//
18
19#include "MCTargetDesc/X86BaseInfo.h"
20#include "X86.h"
21#include "X86InstrInfo.h"
22#include "X86Subtarget.h"
23#include "llvm/ADT/DenseMap.h"
24#include "llvm/ADT/DenseMapInfo.h"
25#include "llvm/ADT/Hashing.h"
26#include "llvm/ADT/SmallVector.h"
27#include "llvm/ADT/Statistic.h"
28#include "llvm/Analysis/ProfileSummaryInfo.h"
29#include "llvm/CodeGen/LazyMachineBlockFrequencyInfo.h"
30#include "llvm/CodeGen/MachineBasicBlock.h"
31#include "llvm/CodeGen/MachineFunction.h"
32#include "llvm/CodeGen/MachineFunctionPass.h"
33#include "llvm/CodeGen/MachineInstr.h"
34#include "llvm/CodeGen/MachineInstrBuilder.h"
35#include "llvm/CodeGen/MachineOperand.h"
36#include "llvm/CodeGen/MachineRegisterInfo.h"
37#include "llvm/CodeGen/MachineSizeOpts.h"
38#include "llvm/CodeGen/RegisterClassInfo.h"
39#include "llvm/CodeGen/TargetOpcodes.h"
40#include "llvm/CodeGen/TargetRegisterInfo.h"
41#include "llvm/IR/DebugInfoMetadata.h"
42#include "llvm/IR/DebugLoc.h"
43#include "llvm/IR/Function.h"
44#include "llvm/MC/MCInstrDesc.h"
45#include "llvm/Support/CommandLine.h"
46#include "llvm/Support/Debug.h"
47#include "llvm/Support/ErrorHandling.h"
48#include "llvm/Support/MathExtras.h"
49#include "llvm/Support/raw_ostream.h"
50#include <cassert>
51#include <cstdint>
52#include <iterator>
53
54using namespace llvm;
55
56#define DEBUG_TYPE "x86-optimize-leas"
57
58static cl::opt<bool>
59 DisableX86LEAOpt("disable-x86-lea-opt", cl::Hidden,
60 cl::desc("X86: Disable LEA optimizations."),
61 cl::init(Val: false));
62
63STATISTIC(NumSubstLEAs, "Number of LEA instruction substitutions");
64STATISTIC(NumRedundantLEAs, "Number of redundant LEA instructions removed");
65
66/// Returns true if two machine operands are identical and they are not
67/// physical registers.
68static inline bool isIdenticalOp(const MachineOperand &MO1,
69 const MachineOperand &MO2);
70
71/// Returns true if two address displacement operands are of the same
72/// type and use the same symbol/index/address regardless of the offset.
73static bool isSimilarDispOp(const MachineOperand &MO1,
74 const MachineOperand &MO2);
75
76/// Returns true if the instruction is LEA.
77static inline bool isLEA(const MachineInstr &MI);
78
79namespace {
80
81/// A key based on instruction's memory operands.
82class MemOpKey {
83public:
84 MemOpKey(const MachineOperand *Base, const MachineOperand *Scale,
85 const MachineOperand *Index, const MachineOperand *Segment,
86 const MachineOperand *Disp)
87 : Disp(Disp) {
88 Operands[0] = Base;
89 Operands[1] = Scale;
90 Operands[2] = Index;
91 Operands[3] = Segment;
92 }
93
94 bool operator==(const MemOpKey &Other) const {
95 // Addresses' bases, scales, indices and segments must be identical.
96 for (int i = 0; i < 4; ++i)
97 if (!isIdenticalOp(MO1: *Operands[i], MO2: *Other.Operands[i]))
98 return false;
99
100 // Addresses' displacements don't have to be exactly the same. It only
101 // matters that they use the same symbol/index/address. Immediates' or
102 // offsets' differences will be taken care of during instruction
103 // substitution.
104 return isSimilarDispOp(MO1: *Disp, MO2: *Other.Disp);
105 }
106
107 // Address' base, scale, index and segment operands.
108 const MachineOperand *Operands[4];
109
110 // Address' displacement operand.
111 const MachineOperand *Disp;
112};
113
114} // end anonymous namespace
115
116namespace llvm {
117
118/// Provide DenseMapInfo for MemOpKey.
119template <> struct DenseMapInfo<MemOpKey> {
120 using PtrInfo = DenseMapInfo<const MachineOperand *>;
121
122 static unsigned getHashValue(const MemOpKey &Val) {
123 hash_code Hash = hash_combine(args: *Val.Operands[0], args: *Val.Operands[1],
124 args: *Val.Operands[2], args: *Val.Operands[3]);
125
126 // If the address displacement is an immediate, it should not affect the
127 // hash so that memory operands which differ only be immediate displacement
128 // would have the same hash. If the address displacement is something else,
129 // we should reflect symbol/index/address in the hash.
130 switch (Val.Disp->getType()) {
131 case MachineOperand::MO_Immediate:
132 break;
133 case MachineOperand::MO_ConstantPoolIndex:
134 case MachineOperand::MO_JumpTableIndex:
135 Hash = hash_combine(args: Hash, args: Val.Disp->getIndex());
136 break;
137 case MachineOperand::MO_ExternalSymbol:
138 Hash = hash_combine(args: Hash, args: Val.Disp->getSymbolName());
139 break;
140 case MachineOperand::MO_GlobalAddress:
141 Hash = hash_combine(args: Hash, args: Val.Disp->getGlobal());
142 break;
143 case MachineOperand::MO_BlockAddress:
144 Hash = hash_combine(args: Hash, args: Val.Disp->getBlockAddress());
145 break;
146 case MachineOperand::MO_MCSymbol:
147 Hash = hash_combine(args: Hash, args: Val.Disp->getMCSymbol());
148 break;
149 case MachineOperand::MO_MachineBasicBlock:
150 Hash = hash_combine(args: Hash, args: Val.Disp->getMBB());
151 break;
152 default:
153 llvm_unreachable("Invalid address displacement operand");
154 }
155
156 return (unsigned)Hash;
157 }
158
159 static bool isEqual(const MemOpKey &LHS, const MemOpKey &RHS) {
160 return LHS == RHS;
161 }
162};
163
164} // end namespace llvm
165
166/// Returns a hash table key based on memory operands of \p MI. The
167/// number of the first memory operand of \p MI is specified through \p N.
168static inline MemOpKey getMemOpKey(const MachineInstr &MI, unsigned N) {
169 assert((isLEA(MI) || MI.mayLoadOrStore()) &&
170 "The instruction must be a LEA, a load or a store");
171 return MemOpKey(&MI.getOperand(i: N + X86::AddrBaseReg),
172 &MI.getOperand(i: N + X86::AddrScaleAmt),
173 &MI.getOperand(i: N + X86::AddrIndexReg),
174 &MI.getOperand(i: N + X86::AddrSegmentReg),
175 &MI.getOperand(i: N + X86::AddrDisp));
176}
177
178static inline bool isIdenticalOp(const MachineOperand &MO1,
179 const MachineOperand &MO2) {
180 return MO1.isIdenticalTo(Other: MO2) && (!MO1.isReg() || !MO1.getReg().isPhysical());
181}
182
183#ifndef NDEBUG
184static bool isValidDispOp(const MachineOperand &MO) {
185 return MO.isImm() || MO.isCPI() || MO.isJTI() || MO.isSymbol() ||
186 MO.isGlobal() || MO.isBlockAddress() || MO.isMCSymbol() || MO.isMBB();
187}
188#endif
189
190static bool isSimilarDispOp(const MachineOperand &MO1,
191 const MachineOperand &MO2) {
192 assert(isValidDispOp(MO1) && isValidDispOp(MO2) &&
193 "Address displacement operand is not valid");
194 return (MO1.isImm() && MO2.isImm()) ||
195 (MO1.isCPI() && MO2.isCPI() && MO1.getIndex() == MO2.getIndex()) ||
196 (MO1.isJTI() && MO2.isJTI() && MO1.getIndex() == MO2.getIndex()) ||
197 (MO1.isSymbol() && MO2.isSymbol() &&
198 MO1.getSymbolName() == MO2.getSymbolName()) ||
199 (MO1.isGlobal() && MO2.isGlobal() &&
200 MO1.getGlobal() == MO2.getGlobal()) ||
201 (MO1.isBlockAddress() && MO2.isBlockAddress() &&
202 MO1.getBlockAddress() == MO2.getBlockAddress()) ||
203 (MO1.isMCSymbol() && MO2.isMCSymbol() &&
204 MO1.getMCSymbol() == MO2.getMCSymbol()) ||
205 (MO1.isMBB() && MO2.isMBB() && MO1.getMBB() == MO2.getMBB());
206}
207
208static inline bool isLEA(const MachineInstr &MI) {
209 unsigned Opcode = MI.getOpcode();
210 return Opcode == X86::LEA16r || Opcode == X86::LEA32r ||
211 Opcode == X86::LEA64r || Opcode == X86::LEA64_32r;
212}
213
214namespace {
215
216class X86OptimizeLEAsImpl {
217public:
218 bool runOnMachineFunction(MachineFunction &MF, ProfileSummaryInfo *PSI,
219 MachineBlockFrequencyInfo *MBFI);
220
221private:
222 using MemOpMap = DenseMap<MemOpKey, SmallVector<MachineInstr *, 16>>;
223
224 /// Returns a distance between two instructions inside one basic block.
225 /// Negative result means, that instructions occur in reverse order.
226 int calcInstrDist(const MachineInstr &First, const MachineInstr &Last);
227
228 /// Choose the best \p LEA instruction from the \p List to replace
229 /// address calculation in \p MI instruction. Return the address displacement
230 /// and the distance between \p MI and the chosen \p BestLEA in
231 /// \p AddrDispShift and \p Dist.
232 bool chooseBestLEA(const SmallVectorImpl<MachineInstr *> &List,
233 const MachineInstr &MI, MachineInstr *&BestLEA,
234 int64_t &AddrDispShift, int &Dist);
235
236 /// Returns the difference between addresses' displacements of \p MI1
237 /// and \p MI2. The numbers of the first memory operands for the instructions
238 /// are specified through \p N1 and \p N2.
239 int64_t getAddrDispShift(const MachineInstr &MI1, unsigned N1,
240 const MachineInstr &MI2, unsigned N2) const;
241
242 /// Returns true if the \p Last LEA instruction can be replaced by the
243 /// \p First. The difference between displacements of the addresses calculated
244 /// by these LEAs is returned in \p AddrDispShift. It'll be used for proper
245 /// replacement of the \p Last LEA's uses with the \p First's def register.
246 bool isReplaceable(const MachineInstr &First, const MachineInstr &Last,
247 int64_t &AddrDispShift) const;
248
249 /// Find all LEA instructions in the basic block. Also, assign position
250 /// numbers to all instructions in the basic block to speed up calculation of
251 /// distance between them.
252 void findLEAs(const MachineBasicBlock &MBB, MemOpMap &LEAs);
253
254 /// Removes redundant address calculations.
255 bool removeRedundantAddrCalc(MemOpMap &LEAs);
256
257 /// Replace debug value MI with a new debug value instruction using register
258 /// VReg with an appropriate offset and DIExpression to incorporate the
259 /// address displacement AddrDispShift. Return new debug value instruction.
260 MachineInstr *replaceDebugValue(MachineInstr &MI, Register OldReg,
261 Register NewReg, int64_t AddrDispShift);
262
263 /// Removes LEAs which calculate similar addresses.
264 bool removeRedundantLEAs(MemOpMap &LEAs);
265
266 DenseMap<const MachineInstr *, unsigned> InstrPos;
267
268 MachineRegisterInfo *MRI = nullptr;
269 const X86InstrInfo *TII = nullptr;
270 const X86RegisterInfo *TRI = nullptr;
271};
272
273class X86OptimizeLEAsLegacy : public MachineFunctionPass {
274public:
275 X86OptimizeLEAsLegacy() : MachineFunctionPass(ID) {}
276
277 StringRef getPassName() const override { return "X86 LEA Optimize"; }
278
279 /// Loop over all of the basic blocks, replacing address
280 /// calculations in load and store instructions, if it's already
281 /// been calculated by LEA. Also, remove redundant LEAs.
282 bool runOnMachineFunction(MachineFunction &MF) override;
283
284 static char ID;
285
286 void getAnalysisUsage(AnalysisUsage &AU) const override {
287 AU.addRequired<ProfileSummaryInfoWrapperPass>();
288 AU.addRequired<LazyMachineBlockFrequencyInfoPass>();
289 AU.addPreserved<MachineRegisterClassInfoWrapperPass>();
290 MachineFunctionPass::getAnalysisUsage(AU);
291 }
292};
293
294} // end anonymous namespace
295
296char X86OptimizeLEAsLegacy::ID = 0;
297
298FunctionPass *llvm::createX86OptimizeLEAsLegacyPass() {
299 return new X86OptimizeLEAsLegacy();
300}
301INITIALIZE_PASS(X86OptimizeLEAsLegacy, DEBUG_TYPE, "X86 optimize LEA pass",
302 false, false)
303
304int X86OptimizeLEAsImpl::calcInstrDist(const MachineInstr &First,
305 const MachineInstr &Last) {
306 // Both instructions must be in the same basic block and they must be
307 // presented in InstrPos.
308 assert(Last.getParent() == First.getParent() &&
309 "Instructions are in different basic blocks");
310 assert(InstrPos.contains(&First) && InstrPos.contains(&Last) &&
311 "Instructions' positions are undefined");
312
313 return InstrPos[&Last] - InstrPos[&First];
314}
315
316// Find the best LEA instruction in the List to replace address recalculation in
317// MI. Such LEA must meet these requirements:
318// 1) The address calculated by the LEA differs only by the displacement from
319// the address used in MI.
320// 2) The register class of the definition of the LEA is compatible with the
321// register class of the address base register of MI.
322// 3) Displacement of the new memory operand should fit in 1 byte if possible.
323// 4) The LEA should be as close to MI as possible, and prior to it if
324// possible.
325bool X86OptimizeLEAsImpl::chooseBestLEA(
326 const SmallVectorImpl<MachineInstr *> &List, const MachineInstr &MI,
327 MachineInstr *&BestLEA, int64_t &AddrDispShift, int &Dist) {
328 const MCInstrDesc &Desc = MI.getDesc();
329 int MemOpNo = X86II::getMemoryOperandIdx(Desc);
330 assert(MemOpNo >= 0 && "Expected a memory operand");
331
332 BestLEA = nullptr;
333
334 // Loop over all LEA instructions.
335 for (auto *DefMI : List) {
336 // Get new address displacement.
337 int64_t AddrDispShiftTemp = getAddrDispShift(MI1: MI, N1: MemOpNo, MI2: *DefMI, N2: 1);
338
339 // Make sure address displacement fits 4 bytes.
340 if (!isInt<32>(x: AddrDispShiftTemp))
341 continue;
342
343 // Check that LEA def register can be used as MI address base. Some
344 // instructions can use a limited set of registers as address base, for
345 // example MOV8mr_NOREX. We could constrain the register class of the LEA
346 // def to suit MI, however since this case is very rare and hard to
347 // reproduce in a test it's just more reliable to skip the LEA.
348 if (TII->getRegClass(MCID: Desc, OpNum: MemOpNo + X86::AddrBaseReg) !=
349 MRI->getRegClass(Reg: DefMI->getOperand(i: 0).getReg()))
350 continue;
351
352 // Choose the closest LEA instruction from the list, prior to MI if
353 // possible. Note that we took into account resulting address displacement
354 // as well. Also note that the list is sorted by the order in which the LEAs
355 // occur, so the break condition is pretty simple.
356 int DistTemp = calcInstrDist(First: *DefMI, Last: MI);
357 assert(DistTemp != 0 &&
358 "The distance between two different instructions cannot be zero");
359 if (DistTemp > 0 || BestLEA == nullptr) {
360 // Do not update return LEA, if the current one provides a displacement
361 // which fits in 1 byte, while the new candidate does not.
362 if (BestLEA != nullptr && !isInt<8>(x: AddrDispShiftTemp) &&
363 isInt<8>(x: AddrDispShift))
364 continue;
365
366 BestLEA = DefMI;
367 AddrDispShift = AddrDispShiftTemp;
368 Dist = DistTemp;
369 }
370
371 // FIXME: Maybe we should not always stop at the first LEA after MI.
372 if (DistTemp < 0)
373 break;
374 }
375
376 return BestLEA != nullptr;
377}
378
379// Get the difference between the addresses' displacements of the two
380// instructions \p MI1 and \p MI2. The numbers of the first memory operands are
381// passed through \p N1 and \p N2.
382int64_t X86OptimizeLEAsImpl::getAddrDispShift(const MachineInstr &MI1,
383 unsigned N1,
384 const MachineInstr &MI2,
385 unsigned N2) const {
386 const MachineOperand &Op1 = MI1.getOperand(i: N1 + X86::AddrDisp);
387 const MachineOperand &Op2 = MI2.getOperand(i: N2 + X86::AddrDisp);
388
389 assert(isSimilarDispOp(Op1, Op2) &&
390 "Address displacement operands are not compatible");
391
392 // After the assert above we can be sure that both operands are of the same
393 // valid type and use the same symbol/index/address, thus displacement shift
394 // calculation is rather simple.
395 if (Op1.isJTI())
396 return 0;
397 return Op1.isImm() ? Op1.getImm() - Op2.getImm()
398 : Op1.getOffset() - Op2.getOffset();
399}
400
401// Check that the Last LEA can be replaced by the First LEA. To be so,
402// these requirements must be met:
403// 1) Addresses calculated by LEAs differ only by displacement.
404// 2) Def registers of LEAs belong to the same class.
405// 3) All uses of the Last LEA def register are replaceable, thus the
406// register is used only as address base.
407bool X86OptimizeLEAsImpl::isReplaceable(const MachineInstr &First,
408 const MachineInstr &Last,
409 int64_t &AddrDispShift) const {
410 assert(isLEA(First) && isLEA(Last) &&
411 "The function works only with LEA instructions");
412
413 // Make sure that LEA def registers belong to the same class. There may be
414 // instructions (like MOV8mr_NOREX) which allow a limited set of registers to
415 // be used as their operands, so we must be sure that replacing one LEA
416 // with another won't lead to putting a wrong register in the instruction.
417 if (MRI->getRegClass(Reg: First.getOperand(i: 0).getReg()) !=
418 MRI->getRegClass(Reg: Last.getOperand(i: 0).getReg()))
419 return false;
420
421 // Get new address displacement.
422 AddrDispShift = getAddrDispShift(MI1: Last, N1: 1, MI2: First, N2: 1);
423
424 // Loop over all uses of the Last LEA to check that its def register is
425 // used only as address base for memory accesses. If so, it can be
426 // replaced, otherwise - no.
427 for (auto &MO : MRI->use_nodbg_operands(Reg: Last.getOperand(i: 0).getReg())) {
428 MachineInstr &MI = *MO.getParent();
429
430 // Get the number of the first memory operand.
431 int MemOpNo = X86II::getMemoryOperandIdx(Desc: MI.getDesc());
432
433 // If the use instruction has no memory operand - the LEA is not
434 // replaceable.
435 if (MemOpNo < 0)
436 return false;
437
438 // If the address base of the use instruction is not the LEA def register -
439 // the LEA is not replaceable.
440 if (!isIdenticalOp(MO1: MI.getOperand(i: MemOpNo + X86::AddrBaseReg), MO2: MO))
441 return false;
442
443 // If the LEA def register is used as any other operand of the use
444 // instruction - the LEA is not replaceable.
445 for (unsigned i = 0; i < MI.getNumOperands(); i++)
446 if (i != (unsigned)(MemOpNo + X86::AddrBaseReg) &&
447 isIdenticalOp(MO1: MI.getOperand(i), MO2: MO))
448 return false;
449
450 // Check that the new address displacement will fit 4 bytes.
451 if (MI.getOperand(i: MemOpNo + X86::AddrDisp).isImm() &&
452 !isInt<32>(x: MI.getOperand(i: MemOpNo + X86::AddrDisp).getImm() +
453 AddrDispShift))
454 return false;
455 }
456
457 return true;
458}
459
460void X86OptimizeLEAsImpl::findLEAs(const MachineBasicBlock &MBB,
461 MemOpMap &LEAs) {
462 unsigned Pos = 0;
463 for (auto &MI : MBB) {
464 // Assign the position number to the instruction. Note that we are going to
465 // move some instructions during the optimization however there will never
466 // be a need to move two instructions before any selected instruction. So to
467 // avoid multiple positions' updates during moves we just increase position
468 // counter by two leaving a free space for instructions which will be moved.
469 InstrPos[&MI] = Pos += 2;
470
471 if (isLEA(MI))
472 LEAs[getMemOpKey(MI, N: 1)].push_back(Elt: const_cast<MachineInstr *>(&MI));
473 }
474}
475
476// Try to find load and store instructions which recalculate addresses already
477// calculated by some LEA and replace their memory operands with its def
478// register.
479bool X86OptimizeLEAsImpl::removeRedundantAddrCalc(MemOpMap &LEAs) {
480 bool Changed = false;
481
482 assert(!LEAs.empty());
483 MachineBasicBlock *MBB = (*LEAs.begin()->second.begin())->getParent();
484
485 // Process all instructions in basic block.
486 for (MachineInstr &MI : llvm::make_early_inc_range(Range&: *MBB)) {
487 // Instruction must be load or store.
488 if (!MI.mayLoadOrStore())
489 continue;
490
491 // Get the number of the first memory operand.
492 int MemOpNo = X86II::getMemoryOperandIdx(Desc: MI.getDesc());
493
494 // If instruction has no memory operand - skip it.
495 if (MemOpNo < 0)
496 continue;
497
498 // Do not call chooseBestLEA if there was no matching LEA
499 auto Insns = LEAs.find(Val: getMemOpKey(MI, N: MemOpNo));
500 if (Insns == LEAs.end())
501 continue;
502
503 // Get the best LEA instruction to replace address calculation.
504 MachineInstr *DefMI;
505 int64_t AddrDispShift;
506 int Dist;
507 if (!chooseBestLEA(List: Insns->second, MI, BestLEA&: DefMI, AddrDispShift, Dist))
508 continue;
509
510 // If LEA occurs before current instruction, we can freely replace
511 // the instruction. If LEA occurs after, we can lift LEA above the
512 // instruction and this way to be able to replace it. Since LEA and the
513 // instruction have similar memory operands (thus, the same def
514 // instructions for these operands), we can always do that, without
515 // worries of using registers before their defs.
516 if (Dist < 0) {
517 DefMI->removeFromParent();
518 MBB->insert(I: MachineBasicBlock::iterator(&MI), MI: DefMI);
519 InstrPos[DefMI] = InstrPos[&MI] - 1;
520
521 // Make sure the instructions' position numbers are sane.
522 assert(((InstrPos[DefMI] == 1 &&
523 MachineBasicBlock::iterator(DefMI) == MBB->begin()) ||
524 InstrPos[DefMI] >
525 InstrPos[&*std::prev(MachineBasicBlock::iterator(DefMI))]) &&
526 "Instruction positioning is broken");
527 }
528
529 // Since we can possibly extend register lifetime, clear kill flags.
530 MRI->clearKillFlags(Reg: DefMI->getOperand(i: 0).getReg());
531
532 ++NumSubstLEAs;
533 LLVM_DEBUG(dbgs() << "OptimizeLEAs: Candidate to replace: "; MI.dump(););
534
535 // Change instruction operands.
536 MI.getOperand(i: MemOpNo + X86::AddrBaseReg)
537 .ChangeToRegister(Reg: DefMI->getOperand(i: 0).getReg(), isDef: false);
538 MI.getOperand(i: MemOpNo + X86::AddrScaleAmt).ChangeToImmediate(ImmVal: 1);
539 MI.getOperand(i: MemOpNo + X86::AddrIndexReg)
540 .ChangeToRegister(Reg: X86::NoRegister, isDef: false);
541 MI.getOperand(i: MemOpNo + X86::AddrDisp).ChangeToImmediate(ImmVal: AddrDispShift);
542 MI.getOperand(i: MemOpNo + X86::AddrSegmentReg)
543 .ChangeToRegister(Reg: X86::NoRegister, isDef: false);
544
545 LLVM_DEBUG(dbgs() << "OptimizeLEAs: Replaced by: "; MI.dump(););
546
547 Changed = true;
548 }
549
550 return Changed;
551}
552
553MachineInstr *X86OptimizeLEAsImpl::replaceDebugValue(MachineInstr &MI,
554 Register OldReg,
555 Register NewReg,
556 int64_t AddrDispShift) {
557 const DIExpression *Expr = MI.getDebugExpression();
558 if (AddrDispShift != 0) {
559 if (MI.isNonListDebugValue()) {
560 Expr =
561 DIExpression::prepend(Expr, Flags: DIExpression::StackValue, Offset: AddrDispShift);
562 } else {
563 // Update the Expression, appending an offset of `AddrDispShift` to the
564 // Op corresponding to `OldReg`.
565 SmallVector<uint64_t, 3> Ops;
566 DIExpression::appendOffset(Ops, Offset: AddrDispShift);
567 for (MachineOperand &Op : MI.getDebugOperandsForReg(Reg: OldReg)) {
568 unsigned OpIdx = MI.getDebugOperandIndex(Op: &Op);
569 Expr = DIExpression::appendOpsToArg(Expr, Ops, ArgNo: OpIdx);
570 }
571 }
572 }
573
574 // Replace DBG_VALUE instruction with modified version.
575 MachineBasicBlock *MBB = MI.getParent();
576 DebugLoc DL = MI.getDebugLoc();
577 bool IsIndirect = MI.isIndirectDebugValue();
578 const MDNode *Var = MI.getDebugVariable();
579 unsigned Opcode = MI.isNonListDebugValue() ? TargetOpcode::DBG_VALUE
580 : TargetOpcode::DBG_VALUE_LIST;
581 if (IsIndirect)
582 assert(MI.getDebugOffset().getImm() == 0 &&
583 "DBG_VALUE with nonzero offset");
584 SmallVector<MachineOperand, 4> NewOps;
585 // If we encounter an operand using the old register, replace it with an
586 // operand that uses the new register; otherwise keep the old operand.
587 auto replaceOldReg = [OldReg, NewReg](const MachineOperand &Op) {
588 if (Op.isReg() && Op.getReg() == OldReg)
589 return MachineOperand::CreateReg(Reg: NewReg, isDef: false, isImp: false, isKill: false, isDead: false,
590 isUndef: false, isEarlyClobber: false, SubReg: false, isDebug: false, isInternalRead: false,
591 /*IsRenamable*/ isRenamable: true);
592 return Op;
593 };
594 for (const MachineOperand &Op : MI.debug_operands())
595 NewOps.push_back(Elt: replaceOldReg(Op));
596 return BuildMI(BB&: *MBB, I: MBB->erase(I: &MI), DL, MCID: TII->get(Opcode), IsIndirect,
597 MOs: NewOps, Variable: Var, Expr);
598}
599
600// Try to find similar LEAs in the list and replace one with another.
601bool X86OptimizeLEAsImpl::removeRedundantLEAs(MemOpMap &LEAs) {
602 bool Changed = false;
603
604 // Loop over all entries in the table.
605 for (auto &E : LEAs) {
606 auto &List = E.second;
607
608 // Loop over all LEA pairs.
609 auto I1 = List.begin();
610 while (I1 != List.end()) {
611 MachineInstr &First = **I1;
612 auto I2 = std::next(x: I1);
613 while (I2 != List.end()) {
614 MachineInstr &Last = **I2;
615 int64_t AddrDispShift;
616
617 // LEAs should be in occurrence order in the list, so we can freely
618 // replace later LEAs with earlier ones.
619 assert(calcInstrDist(First, Last) > 0 &&
620 "LEAs must be in occurrence order in the list");
621
622 // Check that the Last LEA instruction can be replaced by the First.
623 if (!isReplaceable(First, Last, AddrDispShift)) {
624 ++I2;
625 continue;
626 }
627
628 // Loop over all uses of the Last LEA and update their operands. Note
629 // that the correctness of this has already been checked in the
630 // isReplaceable function.
631 Register FirstVReg = First.getOperand(i: 0).getReg();
632 Register LastVReg = Last.getOperand(i: 0).getReg();
633 // We use MRI->use_empty here instead of the combination of
634 // llvm::make_early_inc_range and MRI->use_operands because we could
635 // replace two or more uses in a debug instruction in one iteration, and
636 // that would deeply confuse llvm::make_early_inc_range.
637 while (!MRI->use_empty(RegNo: LastVReg)) {
638 MachineOperand &MO = *MRI->use_begin(RegNo: LastVReg);
639 MachineInstr &MI = *MO.getParent();
640
641 if (MI.isDebugValue()) {
642 // Replace DBG_VALUE instruction with modified version using the
643 // register from the replacing LEA and the address displacement
644 // between the LEA instructions.
645 replaceDebugValue(MI, OldReg: LastVReg, NewReg: FirstVReg, AddrDispShift);
646 continue;
647 }
648
649 // Get the number of the first memory operand.
650 int MemOpNo = X86II::getMemoryOperandIdx(Desc: MI.getDesc());
651 assert(MemOpNo >= 0 && "Expected a memory operand");
652
653 // Update address base.
654 MO.setReg(FirstVReg);
655
656 // Update address disp.
657 MachineOperand &Op = MI.getOperand(i: MemOpNo + X86::AddrDisp);
658 if (Op.isImm())
659 Op.setImm(Op.getImm() + AddrDispShift);
660 else if (!Op.isJTI())
661 Op.setOffset(Op.getOffset() + AddrDispShift);
662 }
663
664 // Since we can possibly extend register lifetime, clear kill flags.
665 MRI->clearKillFlags(Reg: FirstVReg);
666
667 ++NumRedundantLEAs;
668 LLVM_DEBUG(dbgs() << "OptimizeLEAs: Remove redundant LEA: ";
669 Last.dump(););
670
671 // By this moment, all of the Last LEA's uses must be replaced. So we
672 // can freely remove it.
673 assert(MRI->use_empty(LastVReg) &&
674 "The LEA's def register must have no uses");
675 Last.eraseFromParent();
676
677 // Erase removed LEA from the list.
678 I2 = List.erase(CI: I2);
679
680 Changed = true;
681 }
682 ++I1;
683 }
684 }
685
686 return Changed;
687}
688
689bool X86OptimizeLEAsImpl::runOnMachineFunction(
690 MachineFunction &MF, ProfileSummaryInfo *PSI,
691 MachineBlockFrequencyInfo *MBFI) {
692 bool Changed = false;
693
694 if (DisableX86LEAOpt)
695 return false;
696
697 MRI = &MF.getRegInfo();
698 TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
699 TRI = MF.getSubtarget<X86Subtarget>().getRegisterInfo();
700
701 // Process all basic blocks.
702 for (auto &MBB : MF) {
703 MemOpMap LEAs;
704 InstrPos.clear();
705
706 // Find all LEA instructions in basic block.
707 findLEAs(MBB, LEAs);
708
709 // If current basic block has no LEAs, move on to the next one.
710 if (LEAs.empty())
711 continue;
712
713 // Remove redundant LEA instructions.
714 Changed |= removeRedundantLEAs(LEAs);
715
716 // Remove redundant address calculations. Do it only for -Os/-Oz since only
717 // a code size gain is expected from this part of the pass.
718 if (llvm::shouldOptimizeForSize(MBB: &MBB, PSI, MBFI))
719 Changed |= removeRedundantAddrCalc(LEAs);
720 }
721
722 return Changed;
723}
724
725bool X86OptimizeLEAsLegacy::runOnMachineFunction(MachineFunction &MF) {
726 if (skipFunction(F: MF.getFunction()))
727 return false;
728 ProfileSummaryInfo *PSI =
729 &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI();
730 MachineBlockFrequencyInfo *MBFI =
731 (PSI && PSI->hasProfileSummary())
732 ? &getAnalysis<LazyMachineBlockFrequencyInfoPass>().getBFI()
733 : nullptr;
734 X86OptimizeLEAsImpl PassImpl;
735 return PassImpl.runOnMachineFunction(MF, PSI, MBFI);
736}
737
738PreservedAnalyses
739X86OptimizeLEAsPass::run(MachineFunction &MF,
740 MachineFunctionAnalysisManager &MFAM) {
741 ProfileSummaryInfo *PSI =
742 MFAM.getResult<ModuleAnalysisManagerMachineFunctionProxy>(IR&: MF)
743 .getCachedResult<ProfileSummaryAnalysis>(
744 IR&: *MF.getFunction().getParent());
745 MachineBlockFrequencyInfo *MBFI =
746 (PSI && PSI->hasProfileSummary())
747 ? &MFAM.getResult<MachineBlockFrequencyAnalysis>(IR&: MF)
748 : nullptr;
749 X86OptimizeLEAsImpl PassImpl;
750 bool Changed = PassImpl.runOnMachineFunction(MF, PSI, MBFI);
751 if (!Changed)
752 return PreservedAnalyses::all();
753 return getMachineFunctionPassPreservedAnalyses().preserveSet<CFGAnalyses>();
754}
755