1//===-- HexagonISelDAGToDAG.cpp - A dag to dag inst selector for Hexagon --===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines an instruction selector for the Hexagon target.
10//
11//===----------------------------------------------------------------------===//
12
13#include "HexagonISelDAGToDAG.h"
14#include "Hexagon.h"
15#include "HexagonISelLowering.h"
16#include "HexagonMachineFunctionInfo.h"
17#include "HexagonTargetMachine.h"
18#include "llvm/CodeGen/FunctionLoweringInfo.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/CodeGen/SelectionDAGISel.h"
21#include "llvm/IR/Intrinsics.h"
22#include "llvm/IR/IntrinsicsHexagon.h"
23#include "llvm/Support/CommandLine.h"
24#include "llvm/Support/Debug.h"
25using namespace llvm;
26
27#define DEBUG_TYPE "hexagon-isel"
28#define PASS_NAME "Hexagon DAG->DAG Pattern Instruction Selection"
29
30static
31cl::opt<bool>
32EnableAddressRebalancing("isel-rebalance-addr", cl::Hidden, cl::init(Val: true),
33 cl::desc("Rebalance address calculation trees to improve "
34 "instruction selection"));
35
36// Rebalance only if this allows e.g. combining a GA with an offset or
37// factoring out a shift.
38static
39cl::opt<bool>
40RebalanceOnlyForOptimizations("rebalance-only-opt", cl::Hidden, cl::init(Val: false),
41 cl::desc("Rebalance address tree only if this allows optimizations"));
42
43static
44cl::opt<bool>
45RebalanceOnlyImbalancedTrees("rebalance-only-imbal", cl::Hidden,
46 cl::init(Val: false), cl::desc("Rebalance address tree only if it is imbalanced"));
47
48static cl::opt<bool> CheckSingleUse("hexagon-isel-su", cl::Hidden,
49 cl::init(Val: true), cl::desc("Enable checking of SDNode's single-use status"));
50
51//===----------------------------------------------------------------------===//
52// Instruction Selector Implementation
53//===----------------------------------------------------------------------===//
54
55#define GET_DAGISEL_BODY HexagonDAGToDAGISel
56#include "HexagonGenDAGISel.inc"
57
58namespace llvm {
59/// createHexagonISelDag - This pass converts a legalized DAG into a
60/// Hexagon-specific DAG, ready for instruction scheduling.
61FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
62 CodeGenOptLevel OptLevel) {
63 return new HexagonDAGToDAGISelLegacy(TM, OptLevel);
64}
65}
66
67HexagonDAGToDAGISelLegacy::HexagonDAGToDAGISelLegacy(HexagonTargetMachine &tm,
68 CodeGenOptLevel OptLevel)
69 : SelectionDAGISelLegacy(
70 ID, std::make_unique<HexagonDAGToDAGISel>(args&: tm, args&: OptLevel)) {}
71
72char HexagonDAGToDAGISelLegacy::ID = 0;
73
74INITIALIZE_PASS(HexagonDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false)
75
76void HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl) {
77 SDValue Chain = LD->getChain();
78 SDValue Base = LD->getBasePtr();
79 SDValue Offset = LD->getOffset();
80 int32_t Inc = cast<ConstantSDNode>(Val: Offset.getNode())->getSExtValue();
81 EVT LoadedVT = LD->getMemoryVT();
82 unsigned Opcode = 0;
83
84 // Check for zero extended loads. Treat any-extend loads as zero extended
85 // loads.
86 ISD::LoadExtType ExtType = LD->getExtensionType();
87 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD);
88 bool IsValidInc = HII->isValidAutoIncImm(VT: LoadedVT, Offset: Inc);
89
90 assert(LoadedVT.isSimple());
91 switch (LoadedVT.getSimpleVT().SimpleTy) {
92 case MVT::i8:
93 if (IsZeroExt)
94 Opcode = IsValidInc ? Hexagon::L2_loadrub_pi : Hexagon::L2_loadrub_io;
95 else
96 Opcode = IsValidInc ? Hexagon::L2_loadrb_pi : Hexagon::L2_loadrb_io;
97 break;
98 case MVT::i16:
99 if (IsZeroExt)
100 Opcode = IsValidInc ? Hexagon::L2_loadruh_pi : Hexagon::L2_loadruh_io;
101 else
102 Opcode = IsValidInc ? Hexagon::L2_loadrh_pi : Hexagon::L2_loadrh_io;
103 break;
104 case MVT::i32:
105 case MVT::f32:
106 case MVT::v2i16:
107 case MVT::v4i8:
108 Opcode = IsValidInc ? Hexagon::L2_loadri_pi : Hexagon::L2_loadri_io;
109 break;
110 case MVT::i64:
111 case MVT::f64:
112 case MVT::v2i32:
113 case MVT::v4i16:
114 case MVT::v8i8:
115 Opcode = IsValidInc ? Hexagon::L2_loadrd_pi : Hexagon::L2_loadrd_io;
116 break;
117 case MVT::v64i8:
118 case MVT::v32i16:
119 case MVT::v16i32:
120 case MVT::v8i64:
121 case MVT::v128i8:
122 case MVT::v64i16:
123 case MVT::v32i32:
124 case MVT::v16i64:
125 if (isAlignedMemNode(N: LD)) {
126 if (LD->isNonTemporal())
127 Opcode = IsValidInc ? Hexagon::V6_vL32b_nt_pi : Hexagon::V6_vL32b_nt_ai;
128 else
129 Opcode = IsValidInc ? Hexagon::V6_vL32b_pi : Hexagon::V6_vL32b_ai;
130 } else {
131 Opcode = IsValidInc ? Hexagon::V6_vL32Ub_pi : Hexagon::V6_vL32Ub_ai;
132 }
133 break;
134 default:
135 llvm_unreachable("Unexpected memory type in indexed load");
136 }
137
138 SDValue IncV = CurDAG->getSignedTargetConstant(Val: Inc, DL: dl, VT: MVT::i32);
139 MachineMemOperand *MemOp = LD->getMemOperand();
140
141 auto getExt64 = [this,ExtType] (MachineSDNode *N, const SDLoc &dl)
142 -> MachineSDNode* {
143 if (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD) {
144 SDValue Zero = CurDAG->getTargetConstant(Val: 0, DL: dl, VT: MVT::i32);
145 return CurDAG->getMachineNode(Opcode: Hexagon::A4_combineir, dl, VT: MVT::i64,
146 Op1: Zero, Op2: SDValue(N, 0));
147 }
148 if (ExtType == ISD::SEXTLOAD)
149 return CurDAG->getMachineNode(Opcode: Hexagon::A2_sxtw, dl, VT: MVT::i64,
150 Op1: SDValue(N, 0));
151 return N;
152 };
153
154 // Loaded value Next address Chain
155 SDValue From[3] = { SDValue(LD,0), SDValue(LD,1), SDValue(LD,2) };
156 SDValue To[3];
157
158 EVT ValueVT = LD->getValueType(ResNo: 0);
159 if (ValueVT == MVT::i64 && ExtType != ISD::NON_EXTLOAD) {
160 // A load extending to i64 will actually produce i32, which will then
161 // need to be extended to i64.
162 assert(LoadedVT.getSizeInBits() <= 32);
163 ValueVT = MVT::i32;
164 }
165
166 if (IsValidInc) {
167 MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, VT1: ValueVT,
168 VT2: MVT::i32, VT3: MVT::Other, Op1: Base,
169 Op2: IncV, Op3: Chain);
170 CurDAG->setNodeMemRefs(N: L, NewMemRefs: {MemOp});
171 To[1] = SDValue(L, 1); // Next address.
172 To[2] = SDValue(L, 2); // Chain.
173 // Handle special case for extension to i64.
174 if (LD->getValueType(ResNo: 0) == MVT::i64)
175 L = getExt64(L, dl);
176 To[0] = SDValue(L, 0); // Loaded (extended) value.
177 } else {
178 SDValue Zero = CurDAG->getTargetConstant(Val: 0, DL: dl, VT: MVT::i32);
179 MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, VT1: ValueVT, VT2: MVT::Other,
180 Op1: Base, Op2: Zero, Op3: Chain);
181 CurDAG->setNodeMemRefs(N: L, NewMemRefs: {MemOp});
182 To[2] = SDValue(L, 1); // Chain.
183 MachineSDNode *A = CurDAG->getMachineNode(Opcode: Hexagon::A2_addi, dl, VT: MVT::i32,
184 Op1: Base, Op2: IncV);
185 To[1] = SDValue(A, 0); // Next address.
186 // Handle special case for extension to i64.
187 if (LD->getValueType(ResNo: 0) == MVT::i64)
188 L = getExt64(L, dl);
189 To[0] = SDValue(L, 0); // Loaded (extended) value.
190 }
191 ReplaceUses(F: From, T: To, Num: 3);
192 CurDAG->RemoveDeadNode(N: LD);
193}
194
195MachineSDNode *HexagonDAGToDAGISel::LoadInstrForLoadIntrinsic(SDNode *IntN) {
196 if (IntN->getOpcode() != ISD::INTRINSIC_W_CHAIN)
197 return nullptr;
198
199 SDLoc dl(IntN);
200 unsigned IntNo = IntN->getConstantOperandVal(Num: 1);
201
202 static std::map<unsigned,unsigned> LoadPciMap = {
203 { Intrinsic::hexagon_circ_ldb, Hexagon::L2_loadrb_pci },
204 { Intrinsic::hexagon_circ_ldub, Hexagon::L2_loadrub_pci },
205 { Intrinsic::hexagon_circ_ldh, Hexagon::L2_loadrh_pci },
206 { Intrinsic::hexagon_circ_lduh, Hexagon::L2_loadruh_pci },
207 { Intrinsic::hexagon_circ_ldw, Hexagon::L2_loadri_pci },
208 { Intrinsic::hexagon_circ_ldd, Hexagon::L2_loadrd_pci },
209 };
210 auto FLC = LoadPciMap.find(x: IntNo);
211 if (FLC != LoadPciMap.end()) {
212 EVT ValTy = (IntNo == Intrinsic::hexagon_circ_ldd) ? MVT::i64 : MVT::i32;
213 EVT RTys[] = { ValTy, MVT::i32, MVT::Other };
214 // Operands: { Base, Increment, Modifier, Chain }
215 auto Inc = cast<ConstantSDNode>(Val: IntN->getOperand(Num: 5));
216 SDValue I =
217 CurDAG->getSignedTargetConstant(Val: Inc->getSExtValue(), DL: dl, VT: MVT::i32);
218 MachineSDNode *Res = CurDAG->getMachineNode(Opcode: FLC->second, dl, ResultTys: RTys,
219 Ops: { IntN->getOperand(Num: 2), I, IntN->getOperand(Num: 4),
220 IntN->getOperand(Num: 0) });
221 return Res;
222 }
223
224 return nullptr;
225}
226
227SDNode *HexagonDAGToDAGISel::StoreInstrForLoadIntrinsic(MachineSDNode *LoadN,
228 SDNode *IntN) {
229 // The "LoadN" is just a machine load instruction. The intrinsic also
230 // involves storing it. Generate an appropriate store to the location
231 // given in the intrinsic's operand(3).
232 uint64_t F = HII->get(Opcode: LoadN->getMachineOpcode()).TSFlags;
233 unsigned SizeBits = (F >> HexagonII::MemAccessSizePos) &
234 HexagonII::MemAccesSizeMask;
235 unsigned Size = 1U << (SizeBits-1);
236
237 SDLoc dl(IntN);
238 MachinePointerInfo PI;
239 SDValue TS;
240 SDValue Loc = IntN->getOperand(Num: 3);
241
242 if (Size >= 4)
243 TS = CurDAG->getStore(Chain: SDValue(LoadN, 2), dl, Val: SDValue(LoadN, 0), Ptr: Loc, PtrInfo: PI,
244 Alignment: Align(Size));
245 else
246 TS = CurDAG->getTruncStore(Chain: SDValue(LoadN, 2), dl, Val: SDValue(LoadN, 0), Ptr: Loc,
247 PtrInfo: PI, SVT: MVT::getIntegerVT(BitWidth: Size * 8), Alignment: Align(Size));
248
249 SDNode *StoreN;
250 {
251 HandleSDNode Handle(TS);
252 SelectStore(N: TS.getNode());
253 StoreN = Handle.getValue().getNode();
254 }
255
256 // Load's results are { Loaded value, Updated pointer, Chain }
257 ReplaceUses(F: SDValue(IntN, 0), T: SDValue(LoadN, 1));
258 ReplaceUses(F: SDValue(IntN, 1), T: SDValue(StoreN, 0));
259 return StoreN;
260}
261
262bool HexagonDAGToDAGISel::tryLoadOfLoadIntrinsic(LoadSDNode *N) {
263 // The intrinsics for load circ/brev perform two operations:
264 // 1. Load a value V from the specified location, using the addressing
265 // mode corresponding to the intrinsic.
266 // 2. Store V into a specified location. This location is typically a
267 // local, temporary object.
268 // In many cases, the program using these intrinsics will immediately
269 // load V again from the local object. In those cases, when certain
270 // conditions are met, the last load can be removed.
271 // This function identifies and optimizes this pattern. If the pattern
272 // cannot be optimized, it returns nullptr, which will cause the load
273 // to be selected separately from the intrinsic (which will be handled
274 // in SelectIntrinsicWChain).
275
276 SDValue Ch = N->getOperand(Num: 0);
277 SDValue Loc = N->getOperand(Num: 1);
278
279 // Assume that the load and the intrinsic are connected directly with a
280 // chain:
281 // t1: i32,ch = int.load ..., ..., ..., Loc, ... // <-- C
282 // t2: i32,ch = load t1:1, Loc, ...
283 SDNode *C = Ch.getNode();
284
285 if (C->getOpcode() != ISD::INTRINSIC_W_CHAIN)
286 return false;
287
288 // The second load can only be eliminated if its extension type matches
289 // that of the load instruction corresponding to the intrinsic. The user
290 // can provide an address of an unsigned variable to store the result of
291 // a sign-extending intrinsic into (or the other way around).
292 ISD::LoadExtType IntExt;
293 switch (C->getConstantOperandVal(Num: 1)) {
294 case Intrinsic::hexagon_circ_ldub:
295 case Intrinsic::hexagon_circ_lduh:
296 IntExt = ISD::ZEXTLOAD;
297 break;
298 case Intrinsic::hexagon_circ_ldw:
299 case Intrinsic::hexagon_circ_ldd:
300 IntExt = ISD::NON_EXTLOAD;
301 break;
302 default:
303 IntExt = ISD::SEXTLOAD;
304 break;
305 }
306 if (N->getExtensionType() != IntExt)
307 return false;
308
309 // Make sure the target location for the loaded value in the load intrinsic
310 // is the location from which LD (or N) is loading.
311 if (C->getNumOperands() < 4 || Loc.getNode() != C->getOperand(Num: 3).getNode())
312 return false;
313
314 if (MachineSDNode *L = LoadInstrForLoadIntrinsic(IntN: C)) {
315 SDNode *S = StoreInstrForLoadIntrinsic(LoadN: L, IntN: C);
316 SDValue F[] = { SDValue(N,0), SDValue(N,1), SDValue(C,0), SDValue(C,1) };
317 SDValue T[] = { SDValue(L,0), SDValue(S,0), SDValue(L,1), SDValue(S,0) };
318 ReplaceUses(F, T, Num: std::size(T));
319 // This transformation will leave the intrinsic dead. If it remains in
320 // the DAG, the selection code will see it again, but without the load,
321 // and it will generate a store that is normally required for it.
322 CurDAG->RemoveDeadNode(N: C);
323 return true;
324 }
325 return false;
326}
327
328// Convert the bit-reverse load intrinsic to appropriate target instruction.
329bool HexagonDAGToDAGISel::SelectBrevLdIntrinsic(SDNode *IntN) {
330 if (IntN->getOpcode() != ISD::INTRINSIC_W_CHAIN)
331 return false;
332
333 const SDLoc &dl(IntN);
334 unsigned IntNo = IntN->getConstantOperandVal(Num: 1);
335
336 static const std::map<unsigned, unsigned> LoadBrevMap = {
337 { Intrinsic::hexagon_L2_loadrb_pbr, Hexagon::L2_loadrb_pbr },
338 { Intrinsic::hexagon_L2_loadrub_pbr, Hexagon::L2_loadrub_pbr },
339 { Intrinsic::hexagon_L2_loadrh_pbr, Hexagon::L2_loadrh_pbr },
340 { Intrinsic::hexagon_L2_loadruh_pbr, Hexagon::L2_loadruh_pbr },
341 { Intrinsic::hexagon_L2_loadri_pbr, Hexagon::L2_loadri_pbr },
342 { Intrinsic::hexagon_L2_loadrd_pbr, Hexagon::L2_loadrd_pbr }
343 };
344 auto FLI = LoadBrevMap.find(x: IntNo);
345 if (FLI != LoadBrevMap.end()) {
346 EVT ValTy =
347 (IntNo == Intrinsic::hexagon_L2_loadrd_pbr) ? MVT::i64 : MVT::i32;
348 EVT RTys[] = { ValTy, MVT::i32, MVT::Other };
349 // Operands of Intrinsic: {chain, enum ID of intrinsic, baseptr,
350 // modifier}.
351 // Operands of target instruction: { Base, Modifier, Chain }.
352 MachineSDNode *Res = CurDAG->getMachineNode(
353 Opcode: FLI->second, dl, ResultTys: RTys,
354 Ops: {IntN->getOperand(Num: 2), IntN->getOperand(Num: 3), IntN->getOperand(Num: 0)});
355
356 MachineMemOperand *MemOp = cast<MemIntrinsicSDNode>(Val: IntN)->getMemOperand();
357 CurDAG->setNodeMemRefs(N: Res, NewMemRefs: {MemOp});
358
359 ReplaceUses(F: SDValue(IntN, 0), T: SDValue(Res, 0));
360 ReplaceUses(F: SDValue(IntN, 1), T: SDValue(Res, 1));
361 ReplaceUses(F: SDValue(IntN, 2), T: SDValue(Res, 2));
362 CurDAG->RemoveDeadNode(N: IntN);
363 return true;
364 }
365 return false;
366}
367
368/// Generate a machine instruction node for the new circular buffer intrinsics.
369/// The new versions use a CSx register instead of the K field.
370bool HexagonDAGToDAGISel::SelectNewCircIntrinsic(SDNode *IntN) {
371 if (IntN->getOpcode() != ISD::INTRINSIC_W_CHAIN)
372 return false;
373
374 SDLoc DL(IntN);
375 unsigned IntNo = IntN->getConstantOperandVal(Num: 1);
376 SmallVector<SDValue, 7> Ops;
377
378 static std::map<unsigned,unsigned> LoadNPcMap = {
379 { Intrinsic::hexagon_L2_loadrub_pci, Hexagon::PS_loadrub_pci },
380 { Intrinsic::hexagon_L2_loadrb_pci, Hexagon::PS_loadrb_pci },
381 { Intrinsic::hexagon_L2_loadruh_pci, Hexagon::PS_loadruh_pci },
382 { Intrinsic::hexagon_L2_loadrh_pci, Hexagon::PS_loadrh_pci },
383 { Intrinsic::hexagon_L2_loadri_pci, Hexagon::PS_loadri_pci },
384 { Intrinsic::hexagon_L2_loadrd_pci, Hexagon::PS_loadrd_pci },
385 { Intrinsic::hexagon_L2_loadrub_pcr, Hexagon::PS_loadrub_pcr },
386 { Intrinsic::hexagon_L2_loadrb_pcr, Hexagon::PS_loadrb_pcr },
387 { Intrinsic::hexagon_L2_loadruh_pcr, Hexagon::PS_loadruh_pcr },
388 { Intrinsic::hexagon_L2_loadrh_pcr, Hexagon::PS_loadrh_pcr },
389 { Intrinsic::hexagon_L2_loadri_pcr, Hexagon::PS_loadri_pcr },
390 { Intrinsic::hexagon_L2_loadrd_pcr, Hexagon::PS_loadrd_pcr }
391 };
392 auto FLI = LoadNPcMap.find (x: IntNo);
393 if (FLI != LoadNPcMap.end()) {
394 EVT ValTy = MVT::i32;
395 if (IntNo == Intrinsic::hexagon_L2_loadrd_pci ||
396 IntNo == Intrinsic::hexagon_L2_loadrd_pcr)
397 ValTy = MVT::i64;
398 EVT RTys[] = { ValTy, MVT::i32, MVT::Other };
399 // Handle load.*_pci case which has 6 operands.
400 if (IntN->getNumOperands() == 6) {
401 auto Inc = cast<ConstantSDNode>(Val: IntN->getOperand(Num: 3));
402 SDValue I = CurDAG->getTargetConstant(Val: Inc->getSExtValue(), DL, VT: MVT::i32);
403 // Operands: { Base, Increment, Modifier, Start, Chain }.
404 Ops = { IntN->getOperand(Num: 2), I, IntN->getOperand(Num: 4), IntN->getOperand(Num: 5),
405 IntN->getOperand(Num: 0) };
406 } else
407 // Handle load.*_pcr case which has 5 operands.
408 // Operands: { Base, Modifier, Start, Chain }.
409 Ops = { IntN->getOperand(Num: 2), IntN->getOperand(Num: 3), IntN->getOperand(Num: 4),
410 IntN->getOperand(Num: 0) };
411 MachineSDNode *Res = CurDAG->getMachineNode(Opcode: FLI->second, dl: DL, ResultTys: RTys, Ops);
412 ReplaceUses(F: SDValue(IntN, 0), T: SDValue(Res, 0));
413 ReplaceUses(F: SDValue(IntN, 1), T: SDValue(Res, 1));
414 ReplaceUses(F: SDValue(IntN, 2), T: SDValue(Res, 2));
415 CurDAG->RemoveDeadNode(N: IntN);
416 return true;
417 }
418
419 static std::map<unsigned,unsigned> StoreNPcMap = {
420 { Intrinsic::hexagon_S2_storerb_pci, Hexagon::PS_storerb_pci },
421 { Intrinsic::hexagon_S2_storerh_pci, Hexagon::PS_storerh_pci },
422 { Intrinsic::hexagon_S2_storerf_pci, Hexagon::PS_storerf_pci },
423 { Intrinsic::hexagon_S2_storeri_pci, Hexagon::PS_storeri_pci },
424 { Intrinsic::hexagon_S2_storerd_pci, Hexagon::PS_storerd_pci },
425 { Intrinsic::hexagon_S2_storerb_pcr, Hexagon::PS_storerb_pcr },
426 { Intrinsic::hexagon_S2_storerh_pcr, Hexagon::PS_storerh_pcr },
427 { Intrinsic::hexagon_S2_storerf_pcr, Hexagon::PS_storerf_pcr },
428 { Intrinsic::hexagon_S2_storeri_pcr, Hexagon::PS_storeri_pcr },
429 { Intrinsic::hexagon_S2_storerd_pcr, Hexagon::PS_storerd_pcr }
430 };
431 auto FSI = StoreNPcMap.find (x: IntNo);
432 if (FSI != StoreNPcMap.end()) {
433 EVT RTys[] = { MVT::i32, MVT::Other };
434 // Handle store.*_pci case which has 7 operands.
435 if (IntN->getNumOperands() == 7) {
436 auto Inc = cast<ConstantSDNode>(Val: IntN->getOperand(Num: 3));
437 SDValue I = CurDAG->getTargetConstant(Val: Inc->getSExtValue(), DL, VT: MVT::i32);
438 // Operands: { Base, Increment, Modifier, Value, Start, Chain }.
439 Ops = { IntN->getOperand(Num: 2), I, IntN->getOperand(Num: 4), IntN->getOperand(Num: 5),
440 IntN->getOperand(Num: 6), IntN->getOperand(Num: 0) };
441 } else
442 // Handle store.*_pcr case which has 6 operands.
443 // Operands: { Base, Modifier, Value, Start, Chain }.
444 Ops = { IntN->getOperand(Num: 2), IntN->getOperand(Num: 3), IntN->getOperand(Num: 4),
445 IntN->getOperand(Num: 5), IntN->getOperand(Num: 0) };
446 MachineSDNode *Res = CurDAG->getMachineNode(Opcode: FSI->second, dl: DL, ResultTys: RTys, Ops);
447 ReplaceUses(F: SDValue(IntN, 0), T: SDValue(Res, 0));
448 ReplaceUses(F: SDValue(IntN, 1), T: SDValue(Res, 1));
449 CurDAG->RemoveDeadNode(N: IntN);
450 return true;
451 }
452
453 return false;
454}
455
456void HexagonDAGToDAGISel::SelectLoad(SDNode *N) {
457 SDLoc dl(N);
458 LoadSDNode *LD = cast<LoadSDNode>(Val: N);
459
460 // Handle indexed loads.
461 ISD::MemIndexedMode AM = LD->getAddressingMode();
462 if (AM != ISD::UNINDEXED) {
463 SelectIndexedLoad(LD, dl);
464 return;
465 }
466
467 // Handle patterns using circ/brev load intrinsics.
468 if (tryLoadOfLoadIntrinsic(N: LD))
469 return;
470
471 SelectCode(N: LD);
472}
473
474void HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, const SDLoc &dl) {
475 SDValue Chain = ST->getChain();
476 SDValue Base = ST->getBasePtr();
477 SDValue Offset = ST->getOffset();
478 SDValue Value = ST->getValue();
479 // Get the constant value.
480 int32_t Inc = cast<ConstantSDNode>(Val: Offset.getNode())->getSExtValue();
481 EVT StoredVT = ST->getMemoryVT();
482 EVT ValueVT = Value.getValueType();
483
484 bool IsValidInc = HII->isValidAutoIncImm(VT: StoredVT, Offset: Inc);
485 unsigned Opcode = 0;
486
487 assert(StoredVT.isSimple());
488 switch (StoredVT.getSimpleVT().SimpleTy) {
489 case MVT::i8:
490 Opcode = IsValidInc ? Hexagon::S2_storerb_pi : Hexagon::S2_storerb_io;
491 break;
492 case MVT::i16:
493 Opcode = IsValidInc ? Hexagon::S2_storerh_pi : Hexagon::S2_storerh_io;
494 break;
495 case MVT::i32:
496 case MVT::f32:
497 case MVT::v2i16:
498 case MVT::v4i8:
499 Opcode = IsValidInc ? Hexagon::S2_storeri_pi : Hexagon::S2_storeri_io;
500 break;
501 case MVT::i64:
502 case MVT::f64:
503 case MVT::v2i32:
504 case MVT::v4i16:
505 case MVT::v8i8:
506 Opcode = IsValidInc ? Hexagon::S2_storerd_pi : Hexagon::S2_storerd_io;
507 break;
508 case MVT::v64i8:
509 case MVT::v32i16:
510 case MVT::v16i32:
511 case MVT::v8i64:
512 case MVT::v128i8:
513 case MVT::v64i16:
514 case MVT::v32i32:
515 case MVT::v16i64:
516 if (isAlignedMemNode(N: ST)) {
517 if (ST->isNonTemporal())
518 Opcode = IsValidInc ? Hexagon::V6_vS32b_nt_pi : Hexagon::V6_vS32b_nt_ai;
519 else
520 Opcode = IsValidInc ? Hexagon::V6_vS32b_pi : Hexagon::V6_vS32b_ai;
521 } else {
522 Opcode = IsValidInc ? Hexagon::V6_vS32Ub_pi : Hexagon::V6_vS32Ub_ai;
523 }
524 break;
525 default:
526 llvm_unreachable("Unexpected memory type in indexed store");
527 }
528
529 if (ST->isTruncatingStore() && ValueVT.getSizeInBits() == 64) {
530 assert(StoredVT.getSizeInBits() < 64 && "Not a truncating store");
531 Value = CurDAG->getTargetExtractSubreg(SRIdx: Hexagon::isub_lo,
532 DL: dl, VT: MVT::i32, Operand: Value);
533 }
534
535 SDValue IncV = CurDAG->getSignedTargetConstant(Val: Inc, DL: dl, VT: MVT::i32);
536 MachineMemOperand *MemOp = ST->getMemOperand();
537
538 // Next address Chain
539 SDValue From[2] = { SDValue(ST,0), SDValue(ST,1) };
540 SDValue To[2];
541
542 if (IsValidInc) {
543 // Build post increment store.
544 SDValue Ops[] = { Base, IncV, Value, Chain };
545 MachineSDNode *S = CurDAG->getMachineNode(Opcode, dl, VT1: MVT::i32, VT2: MVT::Other,
546 Ops);
547 CurDAG->setNodeMemRefs(N: S, NewMemRefs: {MemOp});
548 To[0] = SDValue(S, 0);
549 To[1] = SDValue(S, 1);
550 } else {
551 SDValue Zero = CurDAG->getTargetConstant(Val: 0, DL: dl, VT: MVT::i32);
552 SDValue Ops[] = { Base, Zero, Value, Chain };
553 MachineSDNode *S = CurDAG->getMachineNode(Opcode, dl, VT: MVT::Other, Ops);
554 CurDAG->setNodeMemRefs(N: S, NewMemRefs: {MemOp});
555 To[1] = SDValue(S, 0);
556 MachineSDNode *A = CurDAG->getMachineNode(Opcode: Hexagon::A2_addi, dl, VT: MVT::i32,
557 Op1: Base, Op2: IncV);
558 To[0] = SDValue(A, 0);
559 }
560
561 ReplaceUses(F: From, T: To, Num: 2);
562 CurDAG->RemoveDeadNode(N: ST);
563}
564
565void HexagonDAGToDAGISel::SelectStore(SDNode *N) {
566 SDLoc dl(N);
567 StoreSDNode *ST = cast<StoreSDNode>(Val: N);
568
569 // Handle indexed stores.
570 ISD::MemIndexedMode AM = ST->getAddressingMode();
571 if (AM != ISD::UNINDEXED) {
572 SelectIndexedStore(ST, dl);
573 return;
574 }
575
576 SelectCode(N: ST);
577}
578
579void HexagonDAGToDAGISel::SelectSHL(SDNode *N) {
580 SDLoc dl(N);
581 SDValue Shl_0 = N->getOperand(Num: 0);
582 SDValue Shl_1 = N->getOperand(Num: 1);
583
584 auto Default = [this,N] () -> void { SelectCode(N); };
585
586 if (N->getValueType(ResNo: 0) != MVT::i32 || Shl_1.getOpcode() != ISD::Constant)
587 return Default();
588
589 // RHS is const.
590 int32_t ShlConst = cast<ConstantSDNode>(Val&: Shl_1)->getSExtValue();
591
592 if (Shl_0.getOpcode() == ISD::MUL) {
593 SDValue Mul_0 = Shl_0.getOperand(i: 0); // Val
594 SDValue Mul_1 = Shl_0.getOperand(i: 1); // Const
595 // RHS of mul is const.
596 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val&: Mul_1)) {
597 int32_t ValConst = C->getSExtValue() << ShlConst;
598 if (isInt<9>(x: ValConst)) {
599 SDValue Val = CurDAG->getTargetConstant(Val: ValConst, DL: dl, VT: MVT::i32);
600 SDNode *Result = CurDAG->getMachineNode(Opcode: Hexagon::M2_mpysmi, dl,
601 VT: MVT::i32, Op1: Mul_0, Op2: Val);
602 ReplaceNode(F: N, T: Result);
603 return;
604 }
605 }
606 return Default();
607 }
608
609 if (Shl_0.getOpcode() == ISD::SUB) {
610 SDValue Sub_0 = Shl_0.getOperand(i: 0); // Const 0
611 SDValue Sub_1 = Shl_0.getOperand(i: 1); // Val
612 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(Val&: Sub_0)) {
613 if (C1->getSExtValue() != 0 || Sub_1.getOpcode() != ISD::SHL)
614 return Default();
615 SDValue Shl2_0 = Sub_1.getOperand(i: 0); // Val
616 SDValue Shl2_1 = Sub_1.getOperand(i: 1); // Const
617 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(Val&: Shl2_1)) {
618 int32_t ValConst = 1 << (ShlConst + C2->getSExtValue());
619 if (isInt<9>(x: -ValConst)) {
620 SDValue Val =
621 CurDAG->getSignedTargetConstant(Val: -ValConst, DL: dl, VT: MVT::i32);
622 SDNode *Result = CurDAG->getMachineNode(Opcode: Hexagon::M2_mpysmi, dl,
623 VT: MVT::i32, Op1: Shl2_0, Op2: Val);
624 ReplaceNode(F: N, T: Result);
625 return;
626 }
627 }
628 }
629 }
630
631 return Default();
632}
633
634//
635// Handling intrinsics for circular load and bitreverse load.
636//
637void HexagonDAGToDAGISel::SelectIntrinsicWChain(SDNode *N) {
638 if (MachineSDNode *L = LoadInstrForLoadIntrinsic(IntN: N)) {
639 StoreInstrForLoadIntrinsic(LoadN: L, IntN: N);
640 CurDAG->RemoveDeadNode(N);
641 return;
642 }
643
644 // Handle bit-reverse load intrinsics.
645 if (SelectBrevLdIntrinsic(IntN: N))
646 return;
647
648 if (SelectNewCircIntrinsic(IntN: N))
649 return;
650
651 unsigned IntNo = N->getConstantOperandVal(Num: 1);
652 if (IntNo == Intrinsic::hexagon_V6_vgathermw ||
653 IntNo == Intrinsic::hexagon_V6_vgathermw_128B ||
654 IntNo == Intrinsic::hexagon_V6_vgathermh ||
655 IntNo == Intrinsic::hexagon_V6_vgathermh_128B ||
656 IntNo == Intrinsic::hexagon_V6_vgathermhw ||
657 IntNo == Intrinsic::hexagon_V6_vgathermhw_128B) {
658 SelectV65Gather(N);
659 return;
660 }
661 if (IntNo == Intrinsic::hexagon_V6_vgathermwq ||
662 IntNo == Intrinsic::hexagon_V6_vgathermwq_128B ||
663 IntNo == Intrinsic::hexagon_V6_vgathermhq ||
664 IntNo == Intrinsic::hexagon_V6_vgathermhq_128B ||
665 IntNo == Intrinsic::hexagon_V6_vgathermhwq ||
666 IntNo == Intrinsic::hexagon_V6_vgathermhwq_128B) {
667 SelectV65GatherPred(N);
668 return;
669 }
670
671 SelectCode(N);
672}
673
674void HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) {
675 unsigned IID = N->getConstantOperandVal(Num: 0);
676 unsigned Bits;
677 switch (IID) {
678 case Intrinsic::hexagon_S2_vsplatrb:
679 Bits = 8;
680 break;
681 case Intrinsic::hexagon_S2_vsplatrh:
682 Bits = 16;
683 break;
684 case Intrinsic::hexagon_V6_vaddcarry:
685 case Intrinsic::hexagon_V6_vaddcarry_128B:
686 case Intrinsic::hexagon_V6_vsubcarry:
687 case Intrinsic::hexagon_V6_vsubcarry_128B:
688 SelectHVXDualOutput(N);
689 return;
690 default:
691 SelectCode(N);
692 return;
693 }
694
695 SDValue V = N->getOperand(Num: 1);
696 SDValue U;
697 // Splat intrinsics.
698 if (keepsLowBits(Val: V, NumBits: Bits, Src&: U)) {
699 SDValue R = CurDAG->getNode(Opcode: N->getOpcode(), DL: SDLoc(N), VT: N->getValueType(ResNo: 0),
700 N1: N->getOperand(Num: 0), N2: U);
701 ReplaceNode(F: N, T: R.getNode());
702 SelectCode(N: R.getNode());
703 return;
704 }
705 SelectCode(N);
706}
707
708void HexagonDAGToDAGISel::SelectExtractSubvector(SDNode *N) {
709 SDValue Inp = N->getOperand(Num: 0);
710 MVT ResTy = N->getValueType(ResNo: 0).getSimpleVT();
711 unsigned Idx = N->getConstantOperandVal(Num: 1);
712
713 [[maybe_unused]] MVT InpTy = Inp.getValueType().getSimpleVT();
714 [[maybe_unused]] unsigned ResLen = ResTy.getVectorNumElements();
715 assert(InpTy.getVectorElementType() == ResTy.getVectorElementType());
716 assert(2 * ResLen == InpTy.getVectorNumElements());
717 assert(ResTy.getSizeInBits() == 32);
718 assert(Idx == 0 || Idx == ResLen);
719
720 unsigned SubReg = Idx == 0 ? Hexagon::isub_lo : Hexagon::isub_hi;
721 SDValue Ext = CurDAG->getTargetExtractSubreg(SRIdx: SubReg, DL: SDLoc(N), VT: ResTy, Operand: Inp);
722
723 ReplaceNode(F: N, T: Ext.getNode());
724}
725
726//
727// Map floating point constant values.
728//
729void HexagonDAGToDAGISel::SelectConstantFP(SDNode *N) {
730 SDLoc dl(N);
731 auto *CN = cast<ConstantFPSDNode>(Val: N);
732 APInt A = CN->getValueAPF().bitcastToAPInt();
733 if (N->getValueType(ResNo: 0) == MVT::f32) {
734 SDValue V = CurDAG->getTargetConstant(Val: A.getZExtValue(), DL: dl, VT: MVT::i32);
735 ReplaceNode(F: N, T: CurDAG->getMachineNode(Opcode: Hexagon::A2_tfrsi, dl, VT: MVT::f32, Op1: V));
736 return;
737 }
738 if (N->getValueType(ResNo: 0) == MVT::f64) {
739 SDValue V = CurDAG->getTargetConstant(Val: A.getZExtValue(), DL: dl, VT: MVT::i64);
740 ReplaceNode(F: N, T: CurDAG->getMachineNode(Opcode: Hexagon::CONST64, dl, VT: MVT::f64, Op1: V));
741 return;
742 }
743
744 SelectCode(N);
745}
746
747//
748// Map boolean values.
749//
750void HexagonDAGToDAGISel::SelectConstant(SDNode *N) {
751 if (N->getValueType(ResNo: 0) == MVT::i1) {
752 assert(!(N->getAsZExtVal() >> 1));
753 unsigned Opc = (cast<ConstantSDNode>(Val: N)->getSExtValue() != 0)
754 ? Hexagon::PS_true
755 : Hexagon::PS_false;
756 ReplaceNode(F: N, T: CurDAG->getMachineNode(Opcode: Opc, dl: SDLoc(N), VT: MVT::i1));
757 return;
758 }
759
760 SelectCode(N);
761}
762
763void HexagonDAGToDAGISel::SelectFrameIndex(SDNode *N) {
764 MachineFrameInfo &MFI = MF->getFrameInfo();
765 const HexagonFrameLowering *HFI = HST->getFrameLowering();
766 int FX = cast<FrameIndexSDNode>(Val: N)->getIndex();
767 Align StkA = HFI->getStackAlign();
768 Align MaxA = MFI.getMaxAlign();
769 SDValue FI = CurDAG->getTargetFrameIndex(FI: FX, VT: MVT::i32);
770 SDLoc DL(N);
771 SDValue Zero = CurDAG->getTargetConstant(Val: 0, DL, VT: MVT::i32);
772 SDNode *R = nullptr;
773
774 // Use PS_fi when:
775 // - the object is fixed, or
776 // - there are no objects with higher-than-default alignment, or
777 // - there are no dynamically allocated objects.
778 // Otherwise, use PS_fia.
779 if (FX < 0 || MaxA <= StkA || !MFI.hasVarSizedObjects()) {
780 R = CurDAG->getMachineNode(Opcode: Hexagon::PS_fi, dl: DL, VT: MVT::i32, Op1: FI, Op2: Zero);
781 } else {
782 auto &HMFI = *MF->getInfo<HexagonMachineFunctionInfo>();
783 Register AR = HMFI.getStackAlignBaseReg();
784 SDValue CH = CurDAG->getEntryNode();
785 SDValue Ops[] = { CurDAG->getCopyFromReg(Chain: CH, dl: DL, Reg: AR, VT: MVT::i32), FI, Zero };
786 R = CurDAG->getMachineNode(Opcode: Hexagon::PS_fia, dl: DL, VT: MVT::i32, Ops);
787 }
788
789 ReplaceNode(F: N, T: R);
790}
791
792void HexagonDAGToDAGISel::SelectAddSubCarry(SDNode *N) {
793 unsigned OpcCarry = N->getOpcode() == HexagonISD::ADDC ? Hexagon::A4_addp_c
794 : Hexagon::A4_subp_c;
795 SDNode *C = CurDAG->getMachineNode(Opcode: OpcCarry, dl: SDLoc(N), VTs: N->getVTList(),
796 Ops: { N->getOperand(Num: 0), N->getOperand(Num: 1),
797 N->getOperand(Num: 2) });
798 ReplaceNode(F: N, T: C);
799}
800
801void HexagonDAGToDAGISel::SelectVAlign(SDNode *N) {
802 MVT ResTy = N->getValueType(ResNo: 0).getSimpleVT();
803 if (HST->isHVXVectorType(VecTy: ResTy, IncludeBool: true))
804 return SelectHvxVAlign(N);
805
806 const SDLoc &dl(N);
807 unsigned VecLen = ResTy.getSizeInBits();
808 if (VecLen == 32) {
809 SDValue Ops[] = {
810 CurDAG->getTargetConstant(Val: Hexagon::DoubleRegsRegClassID, DL: dl, VT: MVT::i32),
811 N->getOperand(Num: 0),
812 CurDAG->getTargetConstant(Val: Hexagon::isub_hi, DL: dl, VT: MVT::i32),
813 N->getOperand(Num: 1),
814 CurDAG->getTargetConstant(Val: Hexagon::isub_lo, DL: dl, VT: MVT::i32)
815 };
816 SDNode *R = CurDAG->getMachineNode(Opcode: TargetOpcode::REG_SEQUENCE, dl,
817 VT: MVT::i64, Ops);
818
819 // Shift right by "(Addr & 0x3) * 8" bytes.
820 SDNode *C;
821 SDValue M0 = CurDAG->getTargetConstant(Val: 0x18, DL: dl, VT: MVT::i32);
822 SDValue M1 = CurDAG->getTargetConstant(Val: 0x03, DL: dl, VT: MVT::i32);
823 if (HST->useCompound()) {
824 C = CurDAG->getMachineNode(Opcode: Hexagon::S4_andi_asl_ri, dl, VT: MVT::i32,
825 Op1: M0, Op2: N->getOperand(Num: 2), Op3: M1);
826 } else {
827 SDNode *T = CurDAG->getMachineNode(Opcode: Hexagon::S2_asl_i_r, dl, VT: MVT::i32,
828 Op1: N->getOperand(Num: 2), Op2: M1);
829 C = CurDAG->getMachineNode(Opcode: Hexagon::A2_andir, dl, VT: MVT::i32,
830 Op1: SDValue(T, 0), Op2: M0);
831 }
832 SDNode *S = CurDAG->getMachineNode(Opcode: Hexagon::S2_lsr_r_p, dl, VT: MVT::i64,
833 Op1: SDValue(R, 0), Op2: SDValue(C, 0));
834 SDValue E = CurDAG->getTargetExtractSubreg(SRIdx: Hexagon::isub_lo, DL: dl, VT: ResTy,
835 Operand: SDValue(S, 0));
836 ReplaceNode(F: N, T: E.getNode());
837 } else {
838 assert(VecLen == 64);
839 SDNode *Pu = CurDAG->getMachineNode(Opcode: Hexagon::C2_tfrrp, dl, VT: MVT::v8i1,
840 Op1: N->getOperand(Num: 2));
841 SDNode *VA = CurDAG->getMachineNode(Opcode: Hexagon::S2_valignrb, dl, VT: ResTy,
842 Op1: N->getOperand(Num: 0), Op2: N->getOperand(Num: 1),
843 Op3: SDValue(Pu,0));
844 ReplaceNode(F: N, T: VA);
845 }
846}
847
848void HexagonDAGToDAGISel::SelectVAlignAddr(SDNode *N) {
849 const SDLoc &dl(N);
850 SDValue A = N->getOperand(Num: 1);
851 int Mask = -cast<ConstantSDNode>(Val: A.getNode())->getSExtValue();
852 assert(isPowerOf2_32(-Mask));
853
854 SDValue M = CurDAG->getTargetConstant(Val: Mask, DL: dl, VT: MVT::i32);
855 SDNode *AA = CurDAG->getMachineNode(Opcode: Hexagon::A2_andir, dl, VT: MVT::i32,
856 Op1: N->getOperand(Num: 0), Op2: M);
857 ReplaceNode(F: N, T: AA);
858}
859
860// Handle these nodes here to avoid having to write patterns for all
861// combinations of input/output types. In all cases, the resulting
862// instruction is the same.
863void HexagonDAGToDAGISel::SelectTypecast(SDNode *N) {
864 SDValue Op = N->getOperand(Num: 0);
865 MVT OpTy = Op.getValueType().getSimpleVT();
866 SDNode *T = CurDAG->MorphNodeTo(N, Opc: N->getOpcode(),
867 VTs: CurDAG->getVTList(VT: OpTy), Ops: {Op});
868 ReplaceNode(F: T, T: Op.getNode());
869}
870
871void HexagonDAGToDAGISel::SelectP2D(SDNode *N) {
872 MVT ResTy = N->getValueType(ResNo: 0).getSimpleVT();
873 SDNode *T = CurDAG->getMachineNode(Opcode: Hexagon::C2_mask, dl: SDLoc(N), VT: ResTy,
874 Op1: N->getOperand(Num: 0));
875 ReplaceNode(F: N, T);
876}
877
878void HexagonDAGToDAGISel::SelectD2P(SDNode *N) {
879 const SDLoc &dl(N);
880 MVT ResTy = N->getValueType(ResNo: 0).getSimpleVT();
881 SDValue Zero = CurDAG->getTargetConstant(Val: 0, DL: dl, VT: MVT::i32);
882 SDNode *T = CurDAG->getMachineNode(Opcode: Hexagon::A4_vcmpbgtui, dl, VT: ResTy,
883 Op1: N->getOperand(Num: 0), Op2: Zero);
884 ReplaceNode(F: N, T);
885}
886
887void HexagonDAGToDAGISel::SelectV2Q(SDNode *N) {
888 const SDLoc &dl(N);
889 MVT ResTy = N->getValueType(ResNo: 0).getSimpleVT();
890 // The argument to V2Q should be a single vector.
891 MVT OpTy = N->getOperand(Num: 0).getValueType().getSimpleVT(); (void)OpTy;
892 assert(HST->getVectorLength() * 8 == OpTy.getSizeInBits());
893
894 SDValue C = CurDAG->getSignedTargetConstant(Val: -1, DL: dl, VT: MVT::i32);
895 SDNode *R = CurDAG->getMachineNode(Opcode: Hexagon::A2_tfrsi, dl, VT: MVT::i32, Op1: C);
896 SDNode *T = CurDAG->getMachineNode(Opcode: Hexagon::V6_vandvrt, dl, VT: ResTy,
897 Op1: N->getOperand(Num: 0), Op2: SDValue(R,0));
898 ReplaceNode(F: N, T);
899}
900
901void HexagonDAGToDAGISel::SelectQ2V(SDNode *N) {
902 const SDLoc &dl(N);
903 MVT ResTy = N->getValueType(ResNo: 0).getSimpleVT();
904 // The result of V2Q should be a single vector.
905 assert(HST->getVectorLength() * 8 == ResTy.getSizeInBits());
906
907 SDValue C = CurDAG->getSignedTargetConstant(Val: -1, DL: dl, VT: MVT::i32);
908 SDNode *R = CurDAG->getMachineNode(Opcode: Hexagon::A2_tfrsi, dl, VT: MVT::i32, Op1: C);
909 SDNode *T = CurDAG->getMachineNode(Opcode: Hexagon::V6_vandqrt, dl, VT: ResTy,
910 Op1: N->getOperand(Num: 0), Op2: SDValue(R,0));
911 ReplaceNode(F: N, T);
912}
913
914void HexagonDAGToDAGISel::FDiv(SDNode *N) {
915 const SDLoc &dl(N);
916 ArrayRef<EVT> ResultType(N->value_begin(), N->value_end());
917 SmallVector<SDValue, 2> Ops;
918 Ops = {N->getOperand(Num: 0), N->getOperand(Num: 1)};
919 SDVTList VTs;
920 VTs = CurDAG->getVTList(VT1: MVT::f32, VT2: MVT::f32);
921 SDNode *ResScale = CurDAG->getMachineNode(Opcode: Hexagon::F2_sfrecipa, dl, VTs, Ops);
922 SDNode *D = CurDAG->getMachineNode(Opcode: Hexagon::F2_sffixupd, dl, VT: MVT::f32, Ops);
923
924 SDValue C = CurDAG->getTargetConstant(Val: 0x3f800000, DL: dl, VT: MVT::i32);
925 SDNode *constNode =
926 CurDAG->getMachineNode(Opcode: Hexagon::A2_tfrsi, dl, VT: MVT::f32, Op1: C);
927
928 SDNode *n = CurDAG->getMachineNode(Opcode: Hexagon::F2_sffixupn, dl, VT: MVT::f32, Ops);
929 SDNode *Err = CurDAG->getMachineNode(Opcode: Hexagon::F2_sffms_lib, dl, VT: MVT::f32,
930 Op1: SDValue(constNode, 0), Op2: SDValue(D, 0),
931 Op3: SDValue(ResScale, 0));
932 SDNode *NewRec = CurDAG->getMachineNode(Opcode: Hexagon::F2_sffma_lib, dl, VT: MVT::f32,
933 Op1: SDValue(ResScale, 0), Op2: SDValue(Err, 0),
934 Op3: SDValue(ResScale, 0));
935 SDNode *newErr = CurDAG->getMachineNode(Opcode: Hexagon::F2_sffms_lib, dl, VT: MVT::f32,
936 Op1: SDValue(constNode, 0), Op2: SDValue(D, 0),
937 Op3: SDValue(NewRec, 0));
938 SDNode *q = CurDAG->getMachineNode(
939 Opcode: Hexagon::A2_andir, dl, VT: MVT::f32, Op1: SDValue(n, 0),
940 Op2: CurDAG->getTargetConstant(Val: 0x80000000, DL: dl, VT: MVT::i32));
941 SDNode *NewQ =
942 CurDAG->getMachineNode(Opcode: Hexagon::F2_sffma_lib, dl, VT: MVT::f32, Op1: SDValue(q, 0),
943 Op2: SDValue(n, 0), Op3: SDValue(NewRec, 0));
944 SDNode *NNewRec = CurDAG->getMachineNode(
945 Opcode: Hexagon::F2_sffma_lib, dl, VT: MVT::f32, Op1: SDValue(NewRec, 0),
946 Op2: SDValue(newErr, 0), Op3: SDValue(NewRec, 0));
947 SDNode *qErr =
948 CurDAG->getMachineNode(Opcode: Hexagon::F2_sffms_lib, dl, VT: MVT::f32, Op1: SDValue(n, 0),
949 Op2: SDValue(D, 0), Op3: SDValue(NewQ, 0));
950 SDNode *NNewQ = CurDAG->getMachineNode(Opcode: Hexagon::F2_sffma_lib, dl, VT: MVT::f32,
951 Op1: SDValue(NewQ, 0), Op2: SDValue(qErr, 0),
952 Op3: SDValue(NNewRec, 0));
953
954 SDNode *NqErr =
955 CurDAG->getMachineNode(Opcode: Hexagon::F2_sffms_lib, dl, VT: MVT::f32, Op1: SDValue(n, 0),
956 Op2: SDValue(NNewQ, 0), Op3: SDValue(D, 0));
957 std::array<SDValue, 4> temp1 = {SDValue(NNewQ, 0), SDValue(NqErr, 0),
958 SDValue(NNewRec, 0), SDValue(ResScale, 1)};
959 ArrayRef<SDValue> OpValue1(temp1);
960 SDNode *FinalNewQ =
961 CurDAG->getMachineNode(Opcode: Hexagon::F2_sffma_sc, dl, VT: MVT::f32, Ops: OpValue1);
962 ReplaceNode(F: N, T: FinalNewQ);
963}
964
965void HexagonDAGToDAGISel::FastFDiv(SDNode *N) {
966 const SDLoc &dl(N);
967 ArrayRef<EVT> ResultType(N->value_begin(), N->value_end());
968 SmallVector<SDValue, 2> Ops;
969 Ops = {N->getOperand(Num: 0), N->getOperand(Num: 1)};
970 SDVTList VTs;
971 VTs = CurDAG->getVTList(VT1: MVT::f32, VT2: MVT::f32);
972 SDNode *ResScale = CurDAG->getMachineNode(Opcode: Hexagon::F2_sfrecipa, dl, VTs, Ops);
973 SDNode *D = CurDAG->getMachineNode(Opcode: Hexagon::F2_sffixupd, dl, VT: MVT::f32, Ops);
974
975 SDValue C = CurDAG->getTargetConstant(Val: 0x3f800000, DL: dl, VT: MVT::i32);
976 SDNode *constNode =
977 CurDAG->getMachineNode(Opcode: Hexagon::A2_tfrsi, dl, VT: MVT::f32, Op1: C);
978
979 SDNode *n = CurDAG->getMachineNode(Opcode: Hexagon::F2_sffixupn, dl, VT: MVT::f32, Ops);
980 SDNode *Err = CurDAG->getMachineNode(Opcode: Hexagon::F2_sffms_lib, dl, VT: MVT::f32,
981 Op1: SDValue(constNode, 0), Op2: SDValue(D, 0),
982 Op3: SDValue(ResScale, 0));
983 SDNode *NewRec = CurDAG->getMachineNode(Opcode: Hexagon::F2_sffma_lib, dl, VT: MVT::f32,
984 Op1: SDValue(ResScale, 0), Op2: SDValue(Err, 0),
985 Op3: SDValue(ResScale, 0));
986 SDNode *newErr = CurDAG->getMachineNode(Opcode: Hexagon::F2_sffms_lib, dl, VT: MVT::f32,
987 Op1: SDValue(constNode, 0), Op2: SDValue(D, 0),
988 Op3: SDValue(NewRec, 0));
989
990 SDNode *NNewRec = CurDAG->getMachineNode(
991 Opcode: Hexagon::F2_sffma_lib, dl, VT: MVT::f32, Op1: SDValue(NewRec, 0),
992 Op2: SDValue(newErr, 0), Op3: SDValue(NewRec, 0));
993 SDNode *FinalNewQ = CurDAG->getMachineNode(
994 Opcode: Hexagon::F2_sfmpy, dl, VT: MVT::f32, Op1: SDValue(NNewRec, 0), Op2: SDValue(n, 0));
995 ReplaceNode(F: N, T: FinalNewQ);
996}
997
998void HexagonDAGToDAGISel::SelectFDiv(SDNode *N) {
999 if (N->getFlags().hasAllowReassociation())
1000 FastFDiv(N);
1001 else
1002 FDiv(N);
1003}
1004
1005void HexagonDAGToDAGISel::Select(SDNode *N) {
1006 if (N->isMachineOpcode())
1007 return N->setNodeId(-1); // Already selected.
1008
1009 auto isHvxOp = [this](SDNode *N) {
1010 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
1011 if (HST->isHVXVectorType(VecTy: N->getValueType(ResNo: i), IncludeBool: true))
1012 return true;
1013 }
1014 for (SDValue I : N->ops()) {
1015 if (HST->isHVXVectorType(VecTy: I.getValueType(), IncludeBool: true))
1016 return true;
1017 }
1018 return false;
1019 };
1020
1021 if (HST->useHVXOps() && isHvxOp(N)) {
1022 switch (N->getOpcode()) {
1023 case ISD::EXTRACT_SUBVECTOR: return SelectHvxExtractSubvector(N);
1024 case ISD::VECTOR_SHUFFLE: return SelectHvxShuffle(N);
1025
1026 case HexagonISD::VROR: return SelectHvxRor(N);
1027 }
1028 }
1029
1030 switch (N->getOpcode()) {
1031 case ISD::Constant: return SelectConstant(N);
1032 case ISD::ConstantFP: return SelectConstantFP(N);
1033 case ISD::FrameIndex: return SelectFrameIndex(N);
1034 case ISD::SHL: return SelectSHL(N);
1035 case ISD::LOAD: return SelectLoad(N);
1036 case ISD::STORE: return SelectStore(N);
1037 case ISD::INTRINSIC_W_CHAIN: return SelectIntrinsicWChain(N);
1038 case ISD::INTRINSIC_WO_CHAIN: return SelectIntrinsicWOChain(N);
1039 case ISD::EXTRACT_SUBVECTOR: return SelectExtractSubvector(N);
1040
1041 case HexagonISD::ADDC:
1042 case HexagonISD::SUBC: return SelectAddSubCarry(N);
1043 case HexagonISD::VALIGN: return SelectVAlign(N);
1044 case HexagonISD::VALIGNADDR: return SelectVAlignAddr(N);
1045 case HexagonISD::TYPECAST: return SelectTypecast(N);
1046 case HexagonISD::P2D: return SelectP2D(N);
1047 case HexagonISD::D2P: return SelectD2P(N);
1048 case HexagonISD::Q2V: return SelectQ2V(N);
1049 case HexagonISD::V2Q: return SelectV2Q(N);
1050 case ISD::FDIV:
1051 return SelectFDiv(N);
1052 }
1053
1054 SelectCode(N);
1055}
1056
1057bool HexagonDAGToDAGISel::SelectInlineAsmMemoryOperand(
1058 const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
1059 std::vector<SDValue> &OutOps) {
1060 SDValue Inp = Op, Res;
1061
1062 switch (ConstraintID) {
1063 default:
1064 return true;
1065 case InlineAsm::ConstraintCode::o: // Offsetable.
1066 case InlineAsm::ConstraintCode::v: // Not offsetable.
1067 case InlineAsm::ConstraintCode::m: // Memory.
1068 if (SelectAddrFI(N&: Inp, R&: Res))
1069 OutOps.push_back(x: Res);
1070 else
1071 OutOps.push_back(x: Inp);
1072 break;
1073 }
1074
1075 OutOps.push_back(x: CurDAG->getTargetConstant(Val: 0, DL: SDLoc(Op), VT: MVT::i32));
1076 return false;
1077}
1078
1079static bool isMemOPCandidate(SDNode *I, SDNode *U) {
1080 // I is an operand of U. Check if U is an arithmetic (binary) operation
1081 // usable in a memop, where the other operand is a loaded value, and the
1082 // result of U is stored in the same location.
1083
1084 if (!U->hasOneUse())
1085 return false;
1086 unsigned Opc = U->getOpcode();
1087 switch (Opc) {
1088 case ISD::ADD:
1089 case ISD::SUB:
1090 case ISD::AND:
1091 case ISD::OR:
1092 break;
1093 default:
1094 return false;
1095 }
1096
1097 SDValue S0 = U->getOperand(Num: 0);
1098 SDValue S1 = U->getOperand(Num: 1);
1099 SDValue SY = (S0.getNode() == I) ? S1 : S0;
1100
1101 SDNode *UUse = *U->user_begin();
1102 if (UUse->getNumValues() != 1)
1103 return false;
1104
1105 // Check if one of the inputs to U is a load instruction and the output
1106 // is used by a store instruction. If so and they also have the same
1107 // base pointer, then don't preoprocess this node sequence as it
1108 // can be matched to a memop.
1109 SDNode *SYNode = SY.getNode();
1110 if (UUse->getOpcode() == ISD::STORE && SYNode->getOpcode() == ISD::LOAD) {
1111 SDValue LDBasePtr = cast<MemSDNode>(Val: SYNode)->getBasePtr();
1112 SDValue STBasePtr = cast<MemSDNode>(Val: UUse)->getBasePtr();
1113 if (LDBasePtr == STBasePtr)
1114 return true;
1115 }
1116 return false;
1117}
1118
1119
1120// Transform: (or (select c x 0) z) -> (select c (or x z) z)
1121// (or (select c 0 y) z) -> (select c z (or y z))
1122void HexagonDAGToDAGISel::ppSimplifyOrSelect0(std::vector<SDNode*> &&Nodes) {
1123 SelectionDAG &DAG = *CurDAG;
1124
1125 for (auto *I : Nodes) {
1126 if (I->getOpcode() != ISD::OR)
1127 continue;
1128
1129 auto IsSelect0 = [](const SDValue &Op) -> bool {
1130 if (Op.getOpcode() != ISD::SELECT)
1131 return false;
1132 return isNullConstant(V: Op.getOperand(i: 1)) ||
1133 isNullConstant(V: Op.getOperand(i: 2));
1134 };
1135
1136 SDValue N0 = I->getOperand(Num: 0), N1 = I->getOperand(Num: 1);
1137 EVT VT = I->getValueType(ResNo: 0);
1138 bool SelN0 = IsSelect0(N0);
1139 SDValue SOp = SelN0 ? N0 : N1;
1140 SDValue VOp = SelN0 ? N1 : N0;
1141
1142 if (SOp.getOpcode() == ISD::SELECT && SOp.getNode()->hasOneUse()) {
1143 SDValue SC = SOp.getOperand(i: 0);
1144 SDValue SX = SOp.getOperand(i: 1);
1145 SDValue SY = SOp.getOperand(i: 2);
1146 SDLoc DLS = SOp;
1147 if (isNullConstant(V: SY)) {
1148 SDValue NewOr = DAG.getNode(Opcode: ISD::OR, DL: DLS, VT, N1: SX, N2: VOp);
1149 SDValue NewSel = DAG.getNode(Opcode: ISD::SELECT, DL: DLS, VT, N1: SC, N2: NewOr, N3: VOp);
1150 DAG.ReplaceAllUsesWith(From: I, To: NewSel.getNode());
1151 } else if (isNullConstant(V: SX)) {
1152 SDValue NewOr = DAG.getNode(Opcode: ISD::OR, DL: DLS, VT, N1: SY, N2: VOp);
1153 SDValue NewSel = DAG.getNode(Opcode: ISD::SELECT, DL: DLS, VT, N1: SC, N2: VOp, N3: NewOr);
1154 DAG.ReplaceAllUsesWith(From: I, To: NewSel.getNode());
1155 }
1156 }
1157 }
1158}
1159
1160// Transform: (store ch val (add x (add (shl y c) e)))
1161// to: (store ch val (add x (shl (add y d) c))),
1162// where e = (shl d c) for some integer d.
1163// The purpose of this is to enable generation of loads/stores with
1164// shifted addressing mode, i.e. mem(x+y<<#c). For that, the shift
1165// value c must be 0, 1 or 2.
1166void HexagonDAGToDAGISel::ppAddrReorderAddShl(std::vector<SDNode*> &&Nodes) {
1167 SelectionDAG &DAG = *CurDAG;
1168
1169 for (auto *I : Nodes) {
1170 if (I->getOpcode() != ISD::STORE)
1171 continue;
1172
1173 // I matched: (store ch val Off)
1174 SDValue Off = I->getOperand(Num: 2);
1175 // Off needs to match: (add x (add (shl y c) (shl d c))))
1176 if (Off.getOpcode() != ISD::ADD)
1177 continue;
1178 // Off matched: (add x T0)
1179 SDValue T0 = Off.getOperand(i: 1);
1180 // T0 needs to match: (add T1 T2):
1181 if (T0.getOpcode() != ISD::ADD)
1182 continue;
1183 // T0 matched: (add T1 T2)
1184 SDValue T1 = T0.getOperand(i: 0);
1185 SDValue T2 = T0.getOperand(i: 1);
1186 // T1 needs to match: (shl y c)
1187 if (T1.getOpcode() != ISD::SHL)
1188 continue;
1189 SDValue C = T1.getOperand(i: 1);
1190 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val: C.getNode());
1191 if (CN == nullptr)
1192 continue;
1193 unsigned CV = CN->getZExtValue();
1194 if (CV > 2)
1195 continue;
1196 // T2 needs to match e, where e = (shl d c) for some d.
1197 ConstantSDNode *EN = dyn_cast<ConstantSDNode>(Val: T2.getNode());
1198 if (EN == nullptr)
1199 continue;
1200 unsigned EV = EN->getZExtValue();
1201 if (EV % (1 << CV) != 0)
1202 continue;
1203 unsigned DV = EV / (1 << CV);
1204
1205 // Replace T0 with: (shl (add y d) c)
1206 SDLoc DL = SDLoc(I);
1207 EVT VT = T0.getValueType();
1208 SDValue D = DAG.getConstant(Val: DV, DL, VT);
1209 // NewAdd = (add y d)
1210 SDValue NewAdd = DAG.getNode(Opcode: ISD::ADD, DL, VT, N1: T1.getOperand(i: 0), N2: D);
1211 // NewShl = (shl NewAdd c)
1212 SDValue NewShl = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: NewAdd, N2: C);
1213 ReplaceNode(F: T0.getNode(), T: NewShl.getNode());
1214 }
1215}
1216
1217// Transform: (load ch (add x (and (srl y c) Mask)))
1218// to: (load ch (add x (shl (srl y d) d-c)))
1219// where
1220// Mask = 00..0 111..1 0.0
1221// | | +-- d-c 0s, and d-c is 0, 1 or 2.
1222// | +-------- 1s
1223// +-------------- at most c 0s
1224// Motivating example:
1225// DAG combiner optimizes (add x (shl (srl y 5) 2))
1226// to (add x (and (srl y 3) 1FFFFFFC))
1227// which results in a constant-extended and(##...,lsr). This transformation
1228// undoes this simplification for cases where the shl can be folded into
1229// an addressing mode.
1230void HexagonDAGToDAGISel::ppAddrRewriteAndSrl(std::vector<SDNode*> &&Nodes) {
1231 SelectionDAG &DAG = *CurDAG;
1232
1233 for (SDNode *N : Nodes) {
1234 unsigned Opc = N->getOpcode();
1235 if (Opc != ISD::LOAD && Opc != ISD::STORE)
1236 continue;
1237 SDValue Addr = Opc == ISD::LOAD ? N->getOperand(Num: 1) : N->getOperand(Num: 2);
1238 // Addr must match: (add x T0)
1239 if (Addr.getOpcode() != ISD::ADD)
1240 continue;
1241 SDValue T0 = Addr.getOperand(i: 1);
1242 // T0 must match: (and T1 Mask)
1243 if (T0.getOpcode() != ISD::AND)
1244 continue;
1245
1246 // We have an AND.
1247 //
1248 // Check the first operand. It must be: (srl y c).
1249 SDValue S = T0.getOperand(i: 0);
1250 if (S.getOpcode() != ISD::SRL)
1251 continue;
1252 ConstantSDNode *SN = dyn_cast<ConstantSDNode>(Val: S.getOperand(i: 1).getNode());
1253 if (SN == nullptr)
1254 continue;
1255 if (SN->getAPIntValue().getBitWidth() != 32)
1256 continue;
1257 uint32_t CV = SN->getZExtValue();
1258
1259 // Check the second operand: the supposed mask.
1260 ConstantSDNode *MN = dyn_cast<ConstantSDNode>(Val: T0.getOperand(i: 1).getNode());
1261 if (MN == nullptr)
1262 continue;
1263 if (MN->getAPIntValue().getBitWidth() != 32)
1264 continue;
1265 uint32_t Mask = MN->getZExtValue();
1266 // Examine the mask.
1267 uint32_t TZ = llvm::countr_zero(Val: Mask);
1268 uint32_t M1 = llvm::countr_one(Value: Mask >> TZ);
1269 uint32_t LZ = llvm::countl_zero(Val: Mask);
1270 // Trailing zeros + middle ones + leading zeros must equal the width.
1271 if (TZ + M1 + LZ != 32)
1272 continue;
1273 // The number of trailing zeros will be encoded in the addressing mode.
1274 if (TZ > 2)
1275 continue;
1276 // The number of leading zeros must be at most c.
1277 if (LZ > CV)
1278 continue;
1279
1280 // All looks good.
1281 SDValue Y = S.getOperand(i: 0);
1282 EVT VT = Addr.getValueType();
1283 SDLoc dl(S);
1284 // TZ = D-C, so D = TZ+C.
1285 SDValue D = DAG.getConstant(Val: TZ+CV, DL: dl, VT);
1286 SDValue DC = DAG.getConstant(Val: TZ, DL: dl, VT);
1287 SDValue NewSrl = DAG.getNode(Opcode: ISD::SRL, DL: dl, VT, N1: Y, N2: D);
1288 SDValue NewShl = DAG.getNode(Opcode: ISD::SHL, DL: dl, VT, N1: NewSrl, N2: DC);
1289 ReplaceNode(F: T0.getNode(), T: NewShl.getNode());
1290 }
1291}
1292
1293// Transform: (op ... (zext i1 c) ...) -> (select c (op ... 0 ...)
1294// (op ... 1 ...))
1295void HexagonDAGToDAGISel::ppHoistZextI1(std::vector<SDNode*> &&Nodes) {
1296 SelectionDAG &DAG = *CurDAG;
1297
1298 for (SDNode *N : Nodes) {
1299 unsigned Opc = N->getOpcode();
1300 if (Opc != ISD::ZERO_EXTEND)
1301 continue;
1302 SDValue OpI1 = N->getOperand(Num: 0);
1303 EVT OpVT = OpI1.getValueType();
1304 if (!OpVT.isSimple() || OpVT.getSimpleVT() != MVT::i1)
1305 continue;
1306 for (SDUse &Use : N->uses()) {
1307 SDNode *U = Use.getUser();
1308 if (U->getNumValues() != 1)
1309 continue;
1310 EVT UVT = U->getValueType(ResNo: 0);
1311 if (!UVT.isSimple() || !UVT.isInteger() || UVT.getSimpleVT() == MVT::i1)
1312 continue;
1313 // Do not generate select for all i1 vector type.
1314 if (UVT.isVector() && UVT.getVectorElementType() == MVT::i1)
1315 continue;
1316 if (isMemOPCandidate(I: N, U))
1317 continue;
1318
1319 // Potentially simplifiable operation.
1320 unsigned I1N = Use.getOperandNo();
1321 SmallVector<SDValue,2> Ops(U->getNumOperands());
1322 for (unsigned i = 0, n = U->getNumOperands(); i != n; ++i)
1323 Ops[i] = U->getOperand(Num: i);
1324 EVT BVT = Ops[I1N].getValueType();
1325
1326 const SDLoc &dl(U);
1327 SDValue C0 = DAG.getConstant(Val: 0, DL: dl, VT: BVT);
1328 SDValue C1 = DAG.getConstant(Val: 1, DL: dl, VT: BVT);
1329 SDValue If0, If1;
1330
1331 if (isa<MachineSDNode>(Val: U)) {
1332 unsigned UseOpc = U->getMachineOpcode();
1333 Ops[I1N] = C0;
1334 If0 = SDValue(DAG.getMachineNode(Opcode: UseOpc, dl, VT: UVT, Ops), 0);
1335 Ops[I1N] = C1;
1336 If1 = SDValue(DAG.getMachineNode(Opcode: UseOpc, dl, VT: UVT, Ops), 0);
1337 } else {
1338 unsigned UseOpc = U->getOpcode();
1339 Ops[I1N] = C0;
1340 If0 = DAG.getNode(Opcode: UseOpc, DL: dl, VT: UVT, Ops);
1341 Ops[I1N] = C1;
1342 If1 = DAG.getNode(Opcode: UseOpc, DL: dl, VT: UVT, Ops);
1343 }
1344 // We're generating a SELECT way after legalization, so keep the types
1345 // simple.
1346 unsigned UW = UVT.getSizeInBits();
1347 EVT SVT = (UW == 32 || UW == 64) ? MVT::getIntegerVT(BitWidth: UW) : UVT;
1348 SDValue Sel = DAG.getNode(Opcode: ISD::SELECT, DL: dl, VT: SVT, N1: OpI1,
1349 N2: DAG.getBitcast(VT: SVT, V: If1),
1350 N3: DAG.getBitcast(VT: SVT, V: If0));
1351 SDValue Ret = DAG.getBitcast(VT: UVT, V: Sel);
1352 DAG.ReplaceAllUsesWith(From: U, To: Ret.getNode());
1353 }
1354 }
1355}
1356
1357void HexagonDAGToDAGISel::PreprocessISelDAG() {
1358 // Repack all nodes before calling each preprocessing function,
1359 // because each of them can modify the set of nodes.
1360 auto getNodes = [this]() -> std::vector<SDNode *> {
1361 std::vector<SDNode *> T;
1362 T.reserve(n: CurDAG->allnodes_size());
1363 for (SDNode &N : CurDAG->allnodes())
1364 T.push_back(x: &N);
1365 return T;
1366 };
1367
1368 if (HST->useHVXOps())
1369 PreprocessHvxISelDAG();
1370
1371 // Transform: (or (select c x 0) z) -> (select c (or x z) z)
1372 // (or (select c 0 y) z) -> (select c z (or y z))
1373 ppSimplifyOrSelect0(Nodes: getNodes());
1374
1375 // Transform: (store ch val (add x (add (shl y c) e)))
1376 // to: (store ch val (add x (shl (add y d) c))),
1377 // where e = (shl d c) for some integer d.
1378 // The purpose of this is to enable generation of loads/stores with
1379 // shifted addressing mode, i.e. mem(x+y<<#c). For that, the shift
1380 // value c must be 0, 1 or 2.
1381 ppAddrReorderAddShl(Nodes: getNodes());
1382
1383 // Transform: (load ch (add x (and (srl y c) Mask)))
1384 // to: (load ch (add x (shl (srl y d) d-c)))
1385 // where
1386 // Mask = 00..0 111..1 0.0
1387 // | | +-- d-c 0s, and d-c is 0, 1 or 2.
1388 // | +-------- 1s
1389 // +-------------- at most c 0s
1390 // Motivating example:
1391 // DAG combiner optimizes (add x (shl (srl y 5) 2))
1392 // to (add x (and (srl y 3) 1FFFFFFC))
1393 // which results in a constant-extended and(##...,lsr). This transformation
1394 // undoes this simplification for cases where the shl can be folded into
1395 // an addressing mode.
1396 ppAddrRewriteAndSrl(Nodes: getNodes());
1397
1398 // Transform: (op ... (zext i1 c) ...) -> (select c (op ... 0 ...)
1399 // (op ... 1 ...))
1400 ppHoistZextI1(Nodes: getNodes());
1401
1402 DEBUG_WITH_TYPE("isel", {
1403 dbgs() << "Preprocessed (Hexagon) selection DAG:";
1404 CurDAG->dump();
1405 });
1406
1407 if (EnableAddressRebalancing) {
1408 rebalanceAddressTrees();
1409
1410 DEBUG_WITH_TYPE("isel", {
1411 dbgs() << "Address tree balanced selection DAG:";
1412 CurDAG->dump();
1413 });
1414 }
1415}
1416
1417void HexagonDAGToDAGISel::emitFunctionEntryCode() {
1418 auto &HST = MF->getSubtarget<HexagonSubtarget>();
1419 auto &HFI = *HST.getFrameLowering();
1420 if (!HFI.needsAligna(MF: *MF))
1421 return;
1422
1423 MachineFrameInfo &MFI = MF->getFrameInfo();
1424 MachineBasicBlock *EntryBB = &MF->front();
1425 Align EntryMaxA = MFI.getMaxAlign();
1426
1427 // Reserve the first non-volatile register.
1428 Register AP = 0;
1429 auto &HRI = *HST.getRegisterInfo();
1430 BitVector Reserved = HRI.getReservedRegs(MF: *MF);
1431 for (const MCPhysReg *R = HRI.getCalleeSavedRegs(MF); *R; ++R) {
1432 if (Reserved[*R])
1433 continue;
1434 AP = *R;
1435 break;
1436 }
1437 assert(AP.isValid() && "Couldn't reserve stack align register");
1438 BuildMI(BB: EntryBB, MIMD: DebugLoc(), MCID: HII->get(Opcode: Hexagon::PS_aligna), DestReg: AP)
1439 .addImm(Val: EntryMaxA.value());
1440 MF->getInfo<HexagonMachineFunctionInfo>()->setStackAlignBaseReg(AP);
1441}
1442
1443void HexagonDAGToDAGISel::updateAligna() {
1444 auto &HFI = *MF->getSubtarget<HexagonSubtarget>().getFrameLowering();
1445 if (!HFI.needsAligna(MF: *MF))
1446 return;
1447 auto *AlignaI = const_cast<MachineInstr*>(HFI.getAlignaInstr(MF: *MF));
1448 assert(AlignaI != nullptr);
1449 unsigned MaxA = MF->getFrameInfo().getMaxAlign().value();
1450 if (AlignaI->getOperand(i: 1).getImm() < MaxA)
1451 AlignaI->getOperand(i: 1).setImm(MaxA);
1452}
1453
1454// Match a frame index that can be used in an addressing mode.
1455bool HexagonDAGToDAGISel::SelectAddrFI(SDValue &N, SDValue &R) {
1456 if (N.getOpcode() != ISD::FrameIndex)
1457 return false;
1458 auto &HFI = *HST->getFrameLowering();
1459 MachineFrameInfo &MFI = MF->getFrameInfo();
1460 int FX = cast<FrameIndexSDNode>(Val&: N)->getIndex();
1461 if (!MFI.isFixedObjectIndex(ObjectIdx: FX) && HFI.needsAligna(MF: *MF))
1462 return false;
1463 R = CurDAG->getTargetFrameIndex(FI: FX, VT: MVT::i32);
1464 return true;
1465}
1466
1467inline bool HexagonDAGToDAGISel::SelectAddrGA(SDValue &N, SDValue &R) {
1468 return SelectGlobalAddress(N, R, UseGP: false, Alignment: Align(1));
1469}
1470
1471inline bool HexagonDAGToDAGISel::SelectAddrGP(SDValue &N, SDValue &R) {
1472 return SelectGlobalAddress(N, R, UseGP: true, Alignment: Align(1));
1473}
1474
1475inline bool HexagonDAGToDAGISel::SelectAnyImm(SDValue &N, SDValue &R) {
1476 return SelectAnyImmediate(N, R, Alignment: Align(1));
1477}
1478
1479inline bool HexagonDAGToDAGISel::SelectAnyImm0(SDValue &N, SDValue &R) {
1480 return SelectAnyImmediate(N, R, Alignment: Align(1));
1481}
1482inline bool HexagonDAGToDAGISel::SelectAnyImm1(SDValue &N, SDValue &R) {
1483 return SelectAnyImmediate(N, R, Alignment: Align(2));
1484}
1485inline bool HexagonDAGToDAGISel::SelectAnyImm2(SDValue &N, SDValue &R) {
1486 return SelectAnyImmediate(N, R, Alignment: Align(4));
1487}
1488inline bool HexagonDAGToDAGISel::SelectAnyImm3(SDValue &N, SDValue &R) {
1489 return SelectAnyImmediate(N, R, Alignment: Align(8));
1490}
1491
1492inline bool HexagonDAGToDAGISel::SelectAnyInt(SDValue &N, SDValue &R) {
1493 EVT T = N.getValueType();
1494 if (!T.isInteger() || T.getSizeInBits() != 32 || !isa<ConstantSDNode>(Val: N))
1495 return false;
1496 uint32_t V = cast<const ConstantSDNode>(Val&: N)->getZExtValue();
1497 R = CurDAG->getTargetConstant(Val: V, DL: SDLoc(N), VT: N.getValueType());
1498 return true;
1499}
1500
1501bool HexagonDAGToDAGISel::SelectAnyImmediate(SDValue &N, SDValue &R,
1502 Align Alignment) {
1503 switch (N.getOpcode()) {
1504 case ISD::Constant: {
1505 if (N.getValueType() != MVT::i32)
1506 return false;
1507 uint32_t V = cast<const ConstantSDNode>(Val&: N)->getZExtValue();
1508 if (!isAligned(Lhs: Alignment, SizeInBytes: V))
1509 return false;
1510 R = CurDAG->getTargetConstant(Val: V, DL: SDLoc(N), VT: N.getValueType());
1511 return true;
1512 }
1513 case HexagonISD::JT:
1514 case HexagonISD::CP:
1515 // These are assumed to always be aligned at least 8-byte boundary.
1516 if (Alignment > Align(8))
1517 return false;
1518 R = N.getOperand(i: 0);
1519 return true;
1520 case ISD::ExternalSymbol:
1521 // Symbols may be aligned at any boundary.
1522 if (Alignment > Align(1))
1523 return false;
1524 R = N;
1525 return true;
1526 case ISD::BlockAddress:
1527 // Block address is always aligned at least 4-byte boundary.
1528 if (Alignment > Align(4) ||
1529 !isAligned(Lhs: Alignment, SizeInBytes: cast<BlockAddressSDNode>(Val&: N)->getOffset()))
1530 return false;
1531 R = N;
1532 return true;
1533 }
1534
1535 if (SelectGlobalAddress(N, R, UseGP: false, Alignment) ||
1536 SelectGlobalAddress(N, R, UseGP: true, Alignment))
1537 return true;
1538
1539 return false;
1540}
1541
1542bool HexagonDAGToDAGISel::SelectGlobalAddress(SDValue &N, SDValue &R,
1543 bool UseGP, Align Alignment) {
1544 switch (N.getOpcode()) {
1545 case ISD::ADD: {
1546 SDValue N0 = N.getOperand(i: 0);
1547 SDValue N1 = N.getOperand(i: 1);
1548 unsigned GAOpc = N0.getOpcode();
1549 if (UseGP && GAOpc != HexagonISD::CONST32_GP)
1550 return false;
1551 if (!UseGP && GAOpc != HexagonISD::CONST32)
1552 return false;
1553 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Val&: N1)) {
1554 if (!isAligned(Lhs: Alignment, SizeInBytes: Const->getZExtValue()))
1555 return false;
1556 SDValue Addr = N0.getOperand(i: 0);
1557 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Val&: Addr)) {
1558 if (GA->getOpcode() == ISD::TargetGlobalAddress) {
1559 uint64_t NewOff = GA->getOffset() + (uint64_t)Const->getSExtValue();
1560 R = CurDAG->getTargetGlobalAddress(GV: GA->getGlobal(), DL: SDLoc(Const),
1561 VT: N.getValueType(), offset: NewOff);
1562 return true;
1563 }
1564 }
1565 }
1566 break;
1567 }
1568 case HexagonISD::CP:
1569 case HexagonISD::JT:
1570 case HexagonISD::CONST32:
1571 // The operand(0) of CONST32 is TargetGlobalAddress, which is what we
1572 // want in the instruction.
1573 if (!UseGP)
1574 R = N.getOperand(i: 0);
1575 return !UseGP;
1576 case HexagonISD::CONST32_GP:
1577 if (UseGP)
1578 R = N.getOperand(i: 0);
1579 return UseGP;
1580 default:
1581 return false;
1582 }
1583
1584 return false;
1585}
1586
1587bool HexagonDAGToDAGISel::DetectUseSxtw(SDValue &N, SDValue &R) {
1588 // This (complex pattern) function is meant to detect a sign-extension
1589 // i32->i64 on a per-operand basis. This would allow writing single
1590 // patterns that would cover a number of combinations of different ways
1591 // a sign-extensions could be written. For example:
1592 // (mul (DetectUseSxtw x) (DetectUseSxtw y)) -> (M2_dpmpyss_s0 x y)
1593 // could match either one of these:
1594 // (mul (sext x) (sext_inreg y))
1595 // (mul (sext-load *p) (sext_inreg y))
1596 // (mul (sext_inreg x) (sext y))
1597 // etc.
1598 //
1599 // The returned value will have type i64 and its low word will
1600 // contain the value being extended. The high bits are not specified.
1601 // The returned type is i64 because the original type of N was i64,
1602 // but the users of this function should only use the low-word of the
1603 // result, e.g.
1604 // (mul sxtw:x, sxtw:y) -> (M2_dpmpyss_s0 (LoReg sxtw:x), (LoReg sxtw:y))
1605
1606 if (N.getValueType() != MVT::i64)
1607 return false;
1608 unsigned Opc = N.getOpcode();
1609 switch (Opc) {
1610 case ISD::SIGN_EXTEND:
1611 case ISD::SIGN_EXTEND_INREG: {
1612 // sext_inreg has the source type as a separate operand.
1613 EVT T = Opc == ISD::SIGN_EXTEND
1614 ? N.getOperand(i: 0).getValueType()
1615 : cast<VTSDNode>(Val: N.getOperand(i: 1))->getVT();
1616 unsigned SW = T.getSizeInBits();
1617 if (SW == 32)
1618 R = N.getOperand(i: 0);
1619 else if (SW < 32)
1620 R = N;
1621 else
1622 return false;
1623 break;
1624 }
1625 case ISD::LOAD: {
1626 LoadSDNode *L = cast<LoadSDNode>(Val&: N);
1627 if (L->getExtensionType() != ISD::SEXTLOAD)
1628 return false;
1629 // All extending loads extend to i32, so even if the value in
1630 // memory is shorter than 32 bits, it will be i32 after the load.
1631 if (L->getMemoryVT().getSizeInBits() > 32)
1632 return false;
1633 R = N;
1634 break;
1635 }
1636 case ISD::SRA: {
1637 auto *S = dyn_cast<ConstantSDNode>(Val: N.getOperand(i: 1));
1638 if (!S || S->getZExtValue() != 32)
1639 return false;
1640 R = N;
1641 break;
1642 }
1643 default:
1644 return false;
1645 }
1646 EVT RT = R.getValueType();
1647 if (RT == MVT::i64)
1648 return true;
1649 assert(RT == MVT::i32);
1650 // This is only to produce a value of type i64. Do not rely on the
1651 // high bits produced by this.
1652 const SDLoc &dl(N);
1653 SDValue Ops[] = {
1654 CurDAG->getTargetConstant(Val: Hexagon::DoubleRegsRegClassID, DL: dl, VT: MVT::i32),
1655 R, CurDAG->getTargetConstant(Val: Hexagon::isub_hi, DL: dl, VT: MVT::i32),
1656 R, CurDAG->getTargetConstant(Val: Hexagon::isub_lo, DL: dl, VT: MVT::i32)
1657 };
1658 SDNode *T = CurDAG->getMachineNode(Opcode: TargetOpcode::REG_SEQUENCE, dl,
1659 VT: MVT::i64, Ops);
1660 R = SDValue(T, 0);
1661 return true;
1662}
1663
1664bool HexagonDAGToDAGISel::keepsLowBits(const SDValue &Val, unsigned NumBits,
1665 SDValue &Src) {
1666 unsigned Opc = Val.getOpcode();
1667 switch (Opc) {
1668 case ISD::SIGN_EXTEND:
1669 case ISD::ZERO_EXTEND:
1670 case ISD::ANY_EXTEND: {
1671 const SDValue &Op0 = Val.getOperand(i: 0);
1672 EVT T = Op0.getValueType();
1673 if (T.isInteger() && T.getSizeInBits() == NumBits) {
1674 Src = Op0;
1675 return true;
1676 }
1677 break;
1678 }
1679 case ISD::SIGN_EXTEND_INREG:
1680 case ISD::AssertSext:
1681 case ISD::AssertZext:
1682 if (Val.getOperand(i: 0).getValueType().isInteger()) {
1683 VTSDNode *T = cast<VTSDNode>(Val: Val.getOperand(i: 1));
1684 if (T->getVT().getSizeInBits() == NumBits) {
1685 Src = Val.getOperand(i: 0);
1686 return true;
1687 }
1688 }
1689 break;
1690 case ISD::AND: {
1691 // Check if this is an AND with NumBits of lower bits set to 1.
1692 uint64_t Mask = (1ULL << NumBits) - 1;
1693 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val: Val.getOperand(i: 0))) {
1694 if (C->getZExtValue() == Mask) {
1695 Src = Val.getOperand(i: 1);
1696 return true;
1697 }
1698 }
1699 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val: Val.getOperand(i: 1))) {
1700 if (C->getZExtValue() == Mask) {
1701 Src = Val.getOperand(i: 0);
1702 return true;
1703 }
1704 }
1705 break;
1706 }
1707 case ISD::OR:
1708 case ISD::XOR: {
1709 // OR/XOR with the lower NumBits bits set to 0.
1710 uint64_t Mask = (1ULL << NumBits) - 1;
1711 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val: Val.getOperand(i: 0))) {
1712 if ((C->getZExtValue() & Mask) == 0) {
1713 Src = Val.getOperand(i: 1);
1714 return true;
1715 }
1716 }
1717 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val: Val.getOperand(i: 1))) {
1718 if ((C->getZExtValue() & Mask) == 0) {
1719 Src = Val.getOperand(i: 0);
1720 return true;
1721 }
1722 }
1723 break;
1724 }
1725 default:
1726 break;
1727 }
1728 return false;
1729}
1730
1731bool HexagonDAGToDAGISel::isAlignedMemNode(const MemSDNode *N) const {
1732 return N->getAlign().value() >= N->getMemoryVT().getStoreSize();
1733}
1734
1735bool HexagonDAGToDAGISel::isSmallStackStore(const StoreSDNode *N) const {
1736 unsigned StackSize = MF->getFrameInfo().estimateStackSize(MF: *MF);
1737 switch (N->getMemoryVT().getStoreSize()) {
1738 case 1:
1739 return StackSize <= 56; // 1*2^6 - 8
1740 case 2:
1741 return StackSize <= 120; // 2*2^6 - 8
1742 case 4:
1743 return StackSize <= 248; // 4*2^6 - 8
1744 default:
1745 return false;
1746 }
1747}
1748
1749// Return true when the given node fits in a positive half word.
1750bool HexagonDAGToDAGISel::isPositiveHalfWord(const SDNode *N) const {
1751 if (const ConstantSDNode *CN = dyn_cast<const ConstantSDNode>(Val: N)) {
1752 int64_t V = CN->getSExtValue();
1753 return V > 0 && isInt<16>(x: V);
1754 }
1755 if (N->getOpcode() == ISD::SIGN_EXTEND_INREG) {
1756 const VTSDNode *VN = dyn_cast<const VTSDNode>(Val: N->getOperand(Num: 1));
1757 return VN->getVT().getSizeInBits() <= 16;
1758 }
1759 return false;
1760}
1761
1762bool HexagonDAGToDAGISel::hasOneUse(const SDNode *N) const {
1763 return !CheckSingleUse || N->hasOneUse();
1764}
1765
1766////////////////////////////////////////////////////////////////////////////////
1767// Rebalancing of address calculation trees
1768
1769static bool isOpcodeHandled(const SDNode *N) {
1770 switch (N->getOpcode()) {
1771 case ISD::ADD:
1772 case ISD::MUL:
1773 return true;
1774 case ISD::SHL:
1775 // We only handle constant shifts because these can be easily flattened
1776 // into multiplications by 2^Op1.
1777 return isa<ConstantSDNode>(Val: N->getOperand(Num: 1).getNode());
1778 default:
1779 return false;
1780 }
1781}
1782
1783/// Return the weight of an SDNode
1784int HexagonDAGToDAGISel::getWeight(SDNode *N) {
1785 if (!isOpcodeHandled(N))
1786 return 1;
1787 assert(RootWeights.count(N) && "Cannot get weight of unseen root!");
1788 assert(RootWeights[N] != -1 && "Cannot get weight of unvisited root!");
1789 assert(RootWeights[N] != -2 && "Cannot get weight of RAWU'd root!");
1790 return RootWeights[N];
1791}
1792
1793int HexagonDAGToDAGISel::getHeight(SDNode *N) {
1794 if (!isOpcodeHandled(N))
1795 return 0;
1796 assert(RootWeights.count(N) && RootWeights[N] >= 0 &&
1797 "Cannot query height of unvisited/RAUW'd node!");
1798 return RootHeights[N];
1799}
1800
1801namespace {
1802struct WeightedLeaf {
1803 SDValue Value;
1804 int Weight;
1805 int InsertionOrder;
1806
1807 WeightedLeaf() {}
1808
1809 WeightedLeaf(SDValue Value, int Weight, int InsertionOrder) :
1810 Value(Value), Weight(Weight), InsertionOrder(InsertionOrder) {
1811 assert(Weight >= 0 && "Weight must be >= 0");
1812 }
1813
1814 static bool Compare(const WeightedLeaf &A, const WeightedLeaf &B) {
1815 assert(A.Value.getNode() && B.Value.getNode());
1816 return A.Weight == B.Weight ?
1817 (A.InsertionOrder > B.InsertionOrder) :
1818 (A.Weight > B.Weight);
1819 }
1820};
1821
1822/// A specialized priority queue for WeigthedLeaves. It automatically folds
1823/// constants and allows removal of non-top elements while maintaining the
1824/// priority order.
1825class LeafPrioQueue {
1826 SmallVector<WeightedLeaf, 8> Q;
1827 bool HaveConst;
1828 WeightedLeaf ConstElt;
1829 unsigned Opcode;
1830
1831public:
1832 bool empty() {
1833 return (!HaveConst && Q.empty());
1834 }
1835
1836 size_t size() {
1837 return Q.size() + HaveConst;
1838 }
1839
1840 bool hasConst() {
1841 return HaveConst;
1842 }
1843
1844 const WeightedLeaf &top() {
1845 if (HaveConst)
1846 return ConstElt;
1847 return Q.front();
1848 }
1849
1850 WeightedLeaf pop() {
1851 if (HaveConst) {
1852 HaveConst = false;
1853 return ConstElt;
1854 }
1855 std::pop_heap(first: Q.begin(), last: Q.end(), comp: WeightedLeaf::Compare);
1856 return Q.pop_back_val();
1857 }
1858
1859 void push(WeightedLeaf L, bool SeparateConst=true) {
1860 if (!HaveConst && SeparateConst && isa<ConstantSDNode>(Val: L.Value)) {
1861 if (Opcode == ISD::MUL &&
1862 cast<ConstantSDNode>(Val&: L.Value)->getSExtValue() == 1)
1863 return;
1864 if (Opcode == ISD::ADD &&
1865 cast<ConstantSDNode>(Val&: L.Value)->getSExtValue() == 0)
1866 return;
1867
1868 HaveConst = true;
1869 ConstElt = L;
1870 } else {
1871 Q.push_back(Elt: L);
1872 std::push_heap(first: Q.begin(), last: Q.end(), comp: WeightedLeaf::Compare);
1873 }
1874 }
1875
1876 /// Push L to the bottom of the queue regardless of its weight. If L is
1877 /// constant, it will not be folded with other constants in the queue.
1878 void pushToBottom(WeightedLeaf L) {
1879 L.Weight = 1000;
1880 push(L, SeparateConst: false);
1881 }
1882
1883 /// Search for a SHL(x, [<=MaxAmount]) subtree in the queue, return the one of
1884 /// lowest weight and remove it from the queue.
1885 WeightedLeaf findSHL(uint64_t MaxAmount);
1886
1887 WeightedLeaf findMULbyConst();
1888
1889 LeafPrioQueue(unsigned Opcode) :
1890 HaveConst(false), Opcode(Opcode) { }
1891};
1892} // end anonymous namespace
1893
1894WeightedLeaf LeafPrioQueue::findSHL(uint64_t MaxAmount) {
1895 int ResultPos;
1896 WeightedLeaf Result;
1897
1898 for (int Pos = 0, End = Q.size(); Pos != End; ++Pos) {
1899 const WeightedLeaf &L = Q[Pos];
1900 const SDValue &Val = L.Value;
1901 if (Val.getOpcode() != ISD::SHL ||
1902 !isa<ConstantSDNode>(Val: Val.getOperand(i: 1)) ||
1903 Val.getConstantOperandVal(i: 1) > MaxAmount)
1904 continue;
1905 if (!Result.Value.getNode() || Result.Weight > L.Weight ||
1906 (Result.Weight == L.Weight && Result.InsertionOrder > L.InsertionOrder))
1907 {
1908 Result = L;
1909 ResultPos = Pos;
1910 }
1911 }
1912
1913 if (Result.Value.getNode()) {
1914 Q.erase(CI: &Q[ResultPos]);
1915 std::make_heap(first: Q.begin(), last: Q.end(), comp: WeightedLeaf::Compare);
1916 }
1917
1918 return Result;
1919}
1920
1921WeightedLeaf LeafPrioQueue::findMULbyConst() {
1922 int ResultPos;
1923 WeightedLeaf Result;
1924
1925 for (int Pos = 0, End = Q.size(); Pos != End; ++Pos) {
1926 const WeightedLeaf &L = Q[Pos];
1927 const SDValue &Val = L.Value;
1928 if (Val.getOpcode() != ISD::MUL ||
1929 !isa<ConstantSDNode>(Val: Val.getOperand(i: 1)) ||
1930 Val.getConstantOperandVal(i: 1) > 127)
1931 continue;
1932 if (!Result.Value.getNode() || Result.Weight > L.Weight ||
1933 (Result.Weight == L.Weight && Result.InsertionOrder > L.InsertionOrder))
1934 {
1935 Result = L;
1936 ResultPos = Pos;
1937 }
1938 }
1939
1940 if (Result.Value.getNode()) {
1941 Q.erase(CI: &Q[ResultPos]);
1942 std::make_heap(first: Q.begin(), last: Q.end(), comp: WeightedLeaf::Compare);
1943 }
1944
1945 return Result;
1946}
1947
1948SDValue HexagonDAGToDAGISel::getMultiplierForSHL(SDNode *N) {
1949 uint64_t MulFactor = 1ull << N->getConstantOperandVal(Num: 1);
1950 return CurDAG->getConstant(Val: MulFactor, DL: SDLoc(N),
1951 VT: N->getOperand(Num: 1).getValueType());
1952}
1953
1954/// @returns the value x for which 2^x is a factor of Val
1955static unsigned getPowerOf2Factor(SDValue Val) {
1956 if (Val.getOpcode() == ISD::MUL) {
1957 unsigned MaxFactor = 0;
1958 for (int i = 0; i < 2; ++i) {
1959 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val: Val.getOperand(i));
1960 if (!C)
1961 continue;
1962 const APInt &CInt = C->getAPIntValue();
1963 if (CInt.getBoolValue())
1964 MaxFactor = CInt.countr_zero();
1965 }
1966 return MaxFactor;
1967 }
1968 if (Val.getOpcode() == ISD::SHL) {
1969 if (!isa<ConstantSDNode>(Val: Val.getOperand(i: 1).getNode()))
1970 return 0;
1971 return (unsigned) Val.getConstantOperandVal(i: 1);
1972 }
1973
1974 return 0;
1975}
1976
1977/// @returns true if V>>Amount will eliminate V's operation on its child
1978static bool willShiftRightEliminate(SDValue V, unsigned Amount) {
1979 if (V.getOpcode() == ISD::MUL) {
1980 SDValue Ops[] = { V.getOperand(i: 0), V.getOperand(i: 1) };
1981 for (int i = 0; i < 2; ++i)
1982 if (isa<ConstantSDNode>(Val: Ops[i].getNode()) &&
1983 V.getConstantOperandVal(i) % (1ULL << Amount) == 0) {
1984 uint64_t NewConst = V.getConstantOperandVal(i) >> Amount;
1985 return (NewConst == 1);
1986 }
1987 } else if (V.getOpcode() == ISD::SHL) {
1988 return (Amount == V.getConstantOperandVal(i: 1));
1989 }
1990
1991 return false;
1992}
1993
1994SDValue HexagonDAGToDAGISel::factorOutPowerOf2(SDValue V, unsigned Power) {
1995 SDValue Ops[] = { V.getOperand(i: 0), V.getOperand(i: 1) };
1996 if (V.getOpcode() == ISD::MUL) {
1997 for (int i=0; i < 2; ++i) {
1998 if (isa<ConstantSDNode>(Val: Ops[i].getNode()) &&
1999 V.getConstantOperandVal(i) % ((uint64_t)1 << Power) == 0) {
2000 uint64_t NewConst = V.getConstantOperandVal(i) >> Power;
2001 if (NewConst == 1)
2002 return Ops[!i];
2003 Ops[i] = CurDAG->getConstant(Val: NewConst,
2004 DL: SDLoc(V), VT: V.getValueType());
2005 break;
2006 }
2007 }
2008 } else if (V.getOpcode() == ISD::SHL) {
2009 uint64_t ShiftAmount = V.getConstantOperandVal(i: 1);
2010 if (ShiftAmount == Power)
2011 return Ops[0];
2012 Ops[1] = CurDAG->getConstant(Val: ShiftAmount - Power,
2013 DL: SDLoc(V), VT: V.getValueType());
2014 }
2015
2016 return CurDAG->getNode(Opcode: V.getOpcode(), DL: SDLoc(V), VT: V.getValueType(), Ops);
2017}
2018
2019static bool isTargetConstant(const SDValue &V) {
2020 return V.getOpcode() == HexagonISD::CONST32 ||
2021 V.getOpcode() == HexagonISD::CONST32_GP;
2022}
2023
2024unsigned HexagonDAGToDAGISel::getUsesInFunction(const Value *V) {
2025 auto [It, Inserted] = GAUsesInFunction.try_emplace(Key: V);
2026 if (!Inserted)
2027 return It->second;
2028
2029 unsigned Result = 0;
2030 const Function &CurF = CurDAG->getMachineFunction().getFunction();
2031 for (const User *U : V->users()) {
2032 if (isa<Instruction>(Val: U) &&
2033 cast<Instruction>(Val: U)->getParent()->getParent() == &CurF)
2034 ++Result;
2035 }
2036
2037 It->second = Result;
2038
2039 return Result;
2040}
2041
2042/// Note - After calling this, N may be dead. It may have been replaced by a
2043/// new node, so always use the returned value in place of N.
2044///
2045/// @returns The SDValue taking the place of N (which could be N if it is
2046/// unchanged)
2047SDValue HexagonDAGToDAGISel::balanceSubTree(SDNode *N, bool TopLevel) {
2048 assert(RootWeights.count(N) && "Cannot balance non-root node.");
2049 assert(RootWeights[N] != -2 && "This node was RAUW'd!");
2050 assert(!TopLevel || N->getOpcode() == ISD::ADD);
2051
2052 // Return early if this node was already visited
2053 if (RootWeights[N] != -1)
2054 return SDValue(N, 0);
2055
2056 assert(isOpcodeHandled(N));
2057
2058 SDValue Op0 = N->getOperand(Num: 0);
2059 SDValue Op1 = N->getOperand(Num: 1);
2060
2061 // Return early if the operands will remain unchanged or are all roots
2062 if ((!isOpcodeHandled(N: Op0.getNode()) || RootWeights.count(Val: Op0.getNode())) &&
2063 (!isOpcodeHandled(N: Op1.getNode()) || RootWeights.count(Val: Op1.getNode()))) {
2064 SDNode *Op0N = Op0.getNode();
2065 int Weight;
2066 if (isOpcodeHandled(N: Op0N) && RootWeights[Op0N] == -1) {
2067 Weight = getWeight(N: balanceSubTree(N: Op0N).getNode());
2068 // Weight = calculateWeight(Op0N);
2069 } else
2070 Weight = getWeight(N: Op0N);
2071
2072 SDNode *Op1N = N->getOperand(Num: 1).getNode(); // Op1 may have been RAUWd
2073 if (isOpcodeHandled(N: Op1N) && RootWeights[Op1N] == -1) {
2074 Weight += getWeight(N: balanceSubTree(N: Op1N).getNode());
2075 // Weight += calculateWeight(Op1N);
2076 } else
2077 Weight += getWeight(N: Op1N);
2078
2079 RootWeights[N] = Weight;
2080 RootHeights[N] = std::max(a: getHeight(N: N->getOperand(Num: 0).getNode()),
2081 b: getHeight(N: N->getOperand(Num: 1).getNode())) + 1;
2082
2083 LLVM_DEBUG(dbgs() << "--> No need to balance root (Weight=" << Weight
2084 << " Height=" << RootHeights[N] << "): ");
2085 LLVM_DEBUG(N->dump(CurDAG));
2086
2087 return SDValue(N, 0);
2088 }
2089
2090 LLVM_DEBUG(dbgs() << "** Balancing root node: ");
2091 LLVM_DEBUG(N->dump(CurDAG));
2092
2093 unsigned NOpcode = N->getOpcode();
2094
2095 LeafPrioQueue Leaves(NOpcode);
2096 SmallVector<SDValue, 4> Worklist;
2097 Worklist.push_back(Elt: SDValue(N, 0));
2098
2099 // SHL nodes will be converted to MUL nodes
2100 if (NOpcode == ISD::SHL)
2101 NOpcode = ISD::MUL;
2102
2103 bool CanFactorize = false;
2104 WeightedLeaf Mul1, Mul2;
2105 unsigned MaxPowerOf2 = 0;
2106 WeightedLeaf GA;
2107
2108 // Do not try to factor out a shift if there is already a shift at the tip of
2109 // the tree.
2110 bool HaveTopLevelShift = false;
2111 if (TopLevel &&
2112 ((isOpcodeHandled(N: Op0.getNode()) && Op0.getOpcode() == ISD::SHL &&
2113 Op0.getConstantOperandVal(i: 1) < 4) ||
2114 (isOpcodeHandled(N: Op1.getNode()) && Op1.getOpcode() == ISD::SHL &&
2115 Op1.getConstantOperandVal(i: 1) < 4)))
2116 HaveTopLevelShift = true;
2117
2118 // Flatten the subtree into an ordered list of leaves; at the same time
2119 // determine whether the tree is already balanced.
2120 int InsertionOrder = 0;
2121 SmallDenseMap<SDValue, int> NodeHeights;
2122 bool Imbalanced = false;
2123 int CurrentWeight = 0;
2124 while (!Worklist.empty()) {
2125 SDValue Child = Worklist.pop_back_val();
2126
2127 if (Child.getNode() != N && RootWeights.count(Val: Child.getNode())) {
2128 // CASE 1: Child is a root note
2129
2130 int Weight = RootWeights[Child.getNode()];
2131 if (Weight == -1) {
2132 Child = balanceSubTree(N: Child.getNode());
2133 // calculateWeight(Child.getNode());
2134 Weight = getWeight(N: Child.getNode());
2135 } else if (Weight == -2) {
2136 // Whoops, this node was RAUWd by one of the balanceSubTree calls we
2137 // made. Our worklist isn't up to date anymore.
2138 // Restart the whole process.
2139 LLVM_DEBUG(dbgs() << "--> Subtree was RAUWd. Restarting...\n");
2140 return balanceSubTree(N, TopLevel);
2141 }
2142
2143 NodeHeights[Child] = 1;
2144 CurrentWeight += Weight;
2145
2146 unsigned PowerOf2;
2147 if (TopLevel && !CanFactorize && !HaveTopLevelShift &&
2148 (Child.getOpcode() == ISD::MUL || Child.getOpcode() == ISD::SHL) &&
2149 Child.hasOneUse() && (PowerOf2 = getPowerOf2Factor(Val: Child))) {
2150 // Try to identify two factorizable MUL/SHL children greedily. Leave
2151 // them out of the priority queue for now so we can deal with them
2152 // after.
2153 if (!Mul1.Value.getNode()) {
2154 Mul1 = WeightedLeaf(Child, Weight, InsertionOrder++);
2155 MaxPowerOf2 = PowerOf2;
2156 } else {
2157 Mul2 = WeightedLeaf(Child, Weight, InsertionOrder++);
2158 MaxPowerOf2 = std::min(a: MaxPowerOf2, b: PowerOf2);
2159
2160 // Our addressing modes can only shift by a maximum of 3
2161 if (MaxPowerOf2 > 3)
2162 MaxPowerOf2 = 3;
2163
2164 CanFactorize = true;
2165 }
2166 } else
2167 Leaves.push(L: WeightedLeaf(Child, Weight, InsertionOrder++));
2168 } else if (!isOpcodeHandled(N: Child.getNode())) {
2169 // CASE 2: Child is an unhandled kind of node (e.g. constant)
2170 int Weight = getWeight(N: Child.getNode());
2171
2172 NodeHeights[Child] = getHeight(N: Child.getNode());
2173 CurrentWeight += Weight;
2174
2175 if (isTargetConstant(V: Child) && !GA.Value.getNode())
2176 GA = WeightedLeaf(Child, Weight, InsertionOrder++);
2177 else
2178 Leaves.push(L: WeightedLeaf(Child, Weight, InsertionOrder++));
2179 } else {
2180 // CASE 3: Child is a subtree of same opcode
2181 // Visit children first, then flatten.
2182 unsigned ChildOpcode = Child.getOpcode();
2183 assert(ChildOpcode == NOpcode ||
2184 (NOpcode == ISD::MUL && ChildOpcode == ISD::SHL));
2185
2186 // Convert SHL to MUL
2187 SDValue Op1;
2188 if (ChildOpcode == ISD::SHL)
2189 Op1 = getMultiplierForSHL(N: Child.getNode());
2190 else
2191 Op1 = Child->getOperand(Num: 1);
2192
2193 if (!NodeHeights.count(Val: Op1) || !NodeHeights.count(Val: Child->getOperand(Num: 0))) {
2194 assert(!NodeHeights.count(Child) && "Parent visited before children?");
2195 // Visit children first, then re-visit this node
2196 Worklist.push_back(Elt: Child);
2197 Worklist.push_back(Elt: Op1);
2198 Worklist.push_back(Elt: Child->getOperand(Num: 0));
2199 } else {
2200 // Back at this node after visiting the children
2201 if (std::abs(x: NodeHeights[Op1] - NodeHeights[Child->getOperand(Num: 0)]) > 1)
2202 Imbalanced = true;
2203
2204 NodeHeights[Child] = std::max(a: NodeHeights[Op1],
2205 b: NodeHeights[Child->getOperand(Num: 0)]) + 1;
2206 }
2207 }
2208 }
2209
2210 LLVM_DEBUG(dbgs() << "--> Current height=" << NodeHeights[SDValue(N, 0)]
2211 << " weight=" << CurrentWeight
2212 << " imbalanced=" << Imbalanced << "\n");
2213
2214 // Transform MUL(x, C * 2^Y) + SHL(z, Y) -> SHL(ADD(MUL(x, C), z), Y)
2215 // This factors out a shift in order to match memw(a<<Y+b).
2216 if (CanFactorize && (willShiftRightEliminate(V: Mul1.Value, Amount: MaxPowerOf2) ||
2217 willShiftRightEliminate(V: Mul2.Value, Amount: MaxPowerOf2))) {
2218 LLVM_DEBUG(dbgs() << "--> Found common factor for two MUL children!\n");
2219 int Weight = Mul1.Weight + Mul2.Weight;
2220 int Height = std::max(a: NodeHeights[Mul1.Value], b: NodeHeights[Mul2.Value]) + 1;
2221 SDValue Mul1Factored = factorOutPowerOf2(V: Mul1.Value, Power: MaxPowerOf2);
2222 SDValue Mul2Factored = factorOutPowerOf2(V: Mul2.Value, Power: MaxPowerOf2);
2223 SDValue Sum = CurDAG->getNode(Opcode: ISD::ADD, DL: SDLoc(N), VT: Mul1.Value.getValueType(),
2224 N1: Mul1Factored, N2: Mul2Factored);
2225 SDValue Const = CurDAG->getConstant(Val: MaxPowerOf2, DL: SDLoc(N),
2226 VT: Mul1.Value.getValueType());
2227 SDValue New = CurDAG->getNode(Opcode: ISD::SHL, DL: SDLoc(N), VT: Mul1.Value.getValueType(),
2228 N1: Sum, N2: Const);
2229 NodeHeights[New] = Height;
2230 Leaves.push(L: WeightedLeaf(New, Weight, Mul1.InsertionOrder));
2231 } else if (Mul1.Value.getNode()) {
2232 // We failed to factorize two MULs, so now the Muls are left outside the
2233 // queue... add them back.
2234 Leaves.push(L: Mul1);
2235 if (Mul2.Value.getNode())
2236 Leaves.push(L: Mul2);
2237 CanFactorize = false;
2238 }
2239
2240 // Combine GA + Constant -> GA+Offset, but only if GA is not used elsewhere
2241 // and the root node itself is not used more than twice. This reduces the
2242 // amount of additional constant extenders introduced by this optimization.
2243 bool CombinedGA = false;
2244 if (NOpcode == ISD::ADD && GA.Value.getNode() && Leaves.hasConst() &&
2245 GA.Value.hasOneUse() && N->use_size() < 3) {
2246 GlobalAddressSDNode *GANode =
2247 cast<GlobalAddressSDNode>(Val: GA.Value.getOperand(i: 0));
2248 ConstantSDNode *Offset = cast<ConstantSDNode>(Val: Leaves.top().Value);
2249
2250 if (getUsesInFunction(V: GANode->getGlobal()) == 1 && Offset->hasOneUse() &&
2251 getTargetLowering()->isOffsetFoldingLegal(GA: GANode)) {
2252 LLVM_DEBUG(dbgs() << "--> Combining GA and offset ("
2253 << Offset->getSExtValue() << "): ");
2254 LLVM_DEBUG(GANode->dump(CurDAG));
2255
2256 SDValue NewTGA =
2257 CurDAG->getTargetGlobalAddress(GV: GANode->getGlobal(), DL: SDLoc(GA.Value),
2258 VT: GANode->getValueType(ResNo: 0),
2259 offset: GANode->getOffset() + (uint64_t)Offset->getSExtValue());
2260 GA.Value = CurDAG->getNode(Opcode: GA.Value.getOpcode(), DL: SDLoc(GA.Value),
2261 VT: GA.Value.getValueType(), Operand: NewTGA);
2262 GA.Weight += Leaves.top().Weight;
2263
2264 NodeHeights[GA.Value] = getHeight(N: GA.Value.getNode());
2265 CombinedGA = true;
2266
2267 Leaves.pop(); // Remove the offset constant from the queue
2268 }
2269 }
2270
2271 if ((RebalanceOnlyForOptimizations && !CanFactorize && !CombinedGA) ||
2272 (RebalanceOnlyImbalancedTrees && !Imbalanced)) {
2273 RootWeights[N] = CurrentWeight;
2274 RootHeights[N] = NodeHeights[SDValue(N, 0)];
2275
2276 return SDValue(N, 0);
2277 }
2278
2279 // Combine GA + SHL(x, C<=31) so we will match Rx=add(#u8,asl(Rx,#U5))
2280 if (NOpcode == ISD::ADD && GA.Value.getNode()) {
2281 WeightedLeaf SHL = Leaves.findSHL(MaxAmount: 31);
2282 if (SHL.Value.getNode()) {
2283 int Height = std::max(a: NodeHeights[GA.Value], b: NodeHeights[SHL.Value]) + 1;
2284 GA.Value = CurDAG->getNode(Opcode: ISD::ADD, DL: SDLoc(GA.Value),
2285 VT: GA.Value.getValueType(),
2286 N1: GA.Value, N2: SHL.Value);
2287 GA.Weight = SHL.Weight; // Specifically ignore the GA weight here
2288 NodeHeights[GA.Value] = Height;
2289 }
2290 }
2291
2292 if (GA.Value.getNode())
2293 Leaves.push(L: GA);
2294
2295 // If this is the top level and we haven't factored out a shift, we should try
2296 // to move a constant to the bottom to match addressing modes like memw(rX+C)
2297 if (TopLevel && !CanFactorize && Leaves.hasConst()) {
2298 LLVM_DEBUG(dbgs() << "--> Pushing constant to tip of tree.");
2299 Leaves.pushToBottom(L: Leaves.pop());
2300 }
2301
2302 const DataLayout &DL = CurDAG->getDataLayout();
2303 const TargetLowering &TLI = *getTargetLowering();
2304
2305 // Rebuild the tree using Huffman's algorithm
2306 while (Leaves.size() > 1) {
2307 WeightedLeaf L0 = Leaves.pop();
2308
2309 // See whether we can grab a MUL to form an add(Rx,mpyi(Ry,#u6)),
2310 // otherwise just get the next leaf
2311 WeightedLeaf L1 = Leaves.findMULbyConst();
2312 if (!L1.Value.getNode())
2313 L1 = Leaves.pop();
2314
2315 assert(L0.Weight <= L1.Weight && "Priority queue is broken!");
2316
2317 SDValue V0 = L0.Value;
2318 int V0Weight = L0.Weight;
2319 SDValue V1 = L1.Value;
2320 int V1Weight = L1.Weight;
2321
2322 // Make sure that none of these nodes have been RAUW'd
2323 if ((RootWeights.count(Val: V0.getNode()) && RootWeights[V0.getNode()] == -2) ||
2324 (RootWeights.count(Val: V1.getNode()) && RootWeights[V1.getNode()] == -2)) {
2325 LLVM_DEBUG(dbgs() << "--> Subtree was RAUWd. Restarting...\n");
2326 return balanceSubTree(N, TopLevel);
2327 }
2328
2329 ConstantSDNode *V0C = dyn_cast<ConstantSDNode>(Val&: V0);
2330 ConstantSDNode *V1C = dyn_cast<ConstantSDNode>(Val&: V1);
2331 EVT VT = N->getValueType(ResNo: 0);
2332 SDValue NewNode;
2333
2334 if (V0C && !V1C) {
2335 std::swap(a&: V0, b&: V1);
2336 std::swap(a&: V0C, b&: V1C);
2337 }
2338
2339 // Calculate height of this node
2340 assert(NodeHeights.count(V0) && NodeHeights.count(V1) &&
2341 "Children must have been visited before re-combining them!");
2342 int Height = std::max(a: NodeHeights[V0], b: NodeHeights[V1]) + 1;
2343
2344 // Rebuild this node (and restore SHL from MUL if needed)
2345 if (V1C && NOpcode == ISD::MUL && V1C->getAPIntValue().isPowerOf2())
2346 NewNode = CurDAG->getNode(
2347 Opcode: ISD::SHL, DL: SDLoc(V0), VT, N1: V0,
2348 N2: CurDAG->getConstant(
2349 Val: V1C->getAPIntValue().logBase2(), DL: SDLoc(N),
2350 VT: TLI.getScalarShiftAmountTy(DL, V0.getValueType())));
2351 else
2352 NewNode = CurDAG->getNode(Opcode: NOpcode, DL: SDLoc(N), VT, N1: V0, N2: V1);
2353
2354 NodeHeights[NewNode] = Height;
2355
2356 int Weight = V0Weight + V1Weight;
2357 Leaves.push(L: WeightedLeaf(NewNode, Weight, L0.InsertionOrder));
2358
2359 LLVM_DEBUG(dbgs() << "--> Built new node (Weight=" << Weight
2360 << ",Height=" << Height << "):\n");
2361 LLVM_DEBUG(NewNode.dump());
2362 }
2363
2364 assert(Leaves.size() == 1);
2365 SDValue NewRoot = Leaves.top().Value;
2366
2367 assert(NodeHeights.count(NewRoot));
2368 int Height = NodeHeights[NewRoot];
2369
2370 // Restore SHL if we earlier converted it to a MUL
2371 if (NewRoot.getOpcode() == ISD::MUL) {
2372 ConstantSDNode *V1C = dyn_cast<ConstantSDNode>(Val: NewRoot.getOperand(i: 1));
2373 if (V1C && V1C->getAPIntValue().isPowerOf2()) {
2374 EVT VT = NewRoot.getValueType();
2375 SDValue V0 = NewRoot.getOperand(i: 0);
2376 NewRoot = CurDAG->getNode(
2377 Opcode: ISD::SHL, DL: SDLoc(NewRoot), VT, N1: V0,
2378 N2: CurDAG->getConstant(
2379 Val: V1C->getAPIntValue().logBase2(), DL: SDLoc(NewRoot),
2380 VT: TLI.getScalarShiftAmountTy(DL, V0.getValueType())));
2381 }
2382 }
2383
2384 if (N != NewRoot.getNode()) {
2385 LLVM_DEBUG(dbgs() << "--> Root is now: ");
2386 LLVM_DEBUG(NewRoot.dump());
2387
2388 // Replace all uses of old root by new root
2389 CurDAG->ReplaceAllUsesWith(From: N, To: NewRoot.getNode());
2390 // Mark that we have RAUW'd N
2391 RootWeights[N] = -2;
2392 } else {
2393 LLVM_DEBUG(dbgs() << "--> Root unchanged.\n");
2394 }
2395
2396 RootWeights[NewRoot.getNode()] = Leaves.top().Weight;
2397 RootHeights[NewRoot.getNode()] = Height;
2398
2399 return NewRoot;
2400}
2401
2402void HexagonDAGToDAGISel::rebalanceAddressTrees() {
2403 for (SDNode &Node : llvm::make_early_inc_range(Range: CurDAG->allnodes())) {
2404 SDNode *N = &Node;
2405 if (N->getOpcode() != ISD::LOAD && N->getOpcode() != ISD::STORE)
2406 continue;
2407
2408 SDValue BasePtr = cast<MemSDNode>(Val: N)->getBasePtr();
2409 if (BasePtr.getOpcode() != ISD::ADD)
2410 continue;
2411
2412 // We've already processed this node
2413 if (RootWeights.count(Val: BasePtr.getNode()))
2414 continue;
2415
2416 LLVM_DEBUG(dbgs() << "** Rebalancing address calculation in node: ");
2417 LLVM_DEBUG(N->dump(CurDAG));
2418
2419 // FindRoots
2420 SmallVector<SDNode *, 4> Worklist;
2421
2422 Worklist.push_back(Elt: BasePtr.getOperand(i: 0).getNode());
2423 Worklist.push_back(Elt: BasePtr.getOperand(i: 1).getNode());
2424
2425 while (!Worklist.empty()) {
2426 SDNode *N = Worklist.pop_back_val();
2427 unsigned Opcode = N->getOpcode();
2428
2429 if (!isOpcodeHandled(N))
2430 continue;
2431
2432 Worklist.push_back(Elt: N->getOperand(Num: 0).getNode());
2433 Worklist.push_back(Elt: N->getOperand(Num: 1).getNode());
2434
2435 // Not a root if it has only one use and same opcode as its parent
2436 if (N->hasOneUse() && Opcode == N->user_begin()->getOpcode())
2437 continue;
2438
2439 // This root node has already been processed
2440 RootWeights.try_emplace(Key: N, Args: -1);
2441 }
2442
2443 // Balance node itself
2444 RootWeights[BasePtr.getNode()] = -1;
2445 SDValue NewBasePtr = balanceSubTree(N: BasePtr.getNode(), /*TopLevel=*/ true);
2446
2447 if (N->getOpcode() == ISD::LOAD)
2448 N = CurDAG->UpdateNodeOperands(N, Op1: N->getOperand(Num: 0),
2449 Op2: NewBasePtr, Op3: N->getOperand(Num: 2));
2450 else
2451 N = CurDAG->UpdateNodeOperands(N, Op1: N->getOperand(Num: 0), Op2: N->getOperand(Num: 1),
2452 Op3: NewBasePtr, Op4: N->getOperand(Num: 3));
2453
2454 LLVM_DEBUG(dbgs() << "--> Final node: ");
2455 LLVM_DEBUG(N->dump(CurDAG));
2456 }
2457
2458 CurDAG->RemoveDeadNodes();
2459 GAUsesInFunction.clear();
2460 RootHeights.clear();
2461 RootWeights.clear();
2462}
2463