1//===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Code to lower AMDGPU MachineInstrs to their corresponding MCInst.
11//
12//===----------------------------------------------------------------------===//
13//
14
15#include "AMDGPUMCInstLower.h"
16#include "AMDGPU.h"
17#include "AMDGPUAsmPrinter.h"
18#include "AMDGPUMachineFunctionInfo.h"
19#include "MCTargetDesc/AMDGPUInstPrinter.h"
20#include "MCTargetDesc/AMDGPUMCExpr.h"
21#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
22#include "SIMachineFunctionInfo.h"
23#include "llvm/CodeGen/MachineBasicBlock.h"
24#include "llvm/CodeGen/MachineInstr.h"
25#include "llvm/IR/Constants.h"
26#include "llvm/IR/Function.h"
27#include "llvm/IR/GlobalVariable.h"
28#include "llvm/MC/MCCodeEmitter.h"
29#include "llvm/MC/MCContext.h"
30#include "llvm/MC/MCExpr.h"
31#include "llvm/MC/MCInst.h"
32#include "llvm/MC/MCObjectStreamer.h"
33#include "llvm/MC/MCStreamer.h"
34#include "llvm/Support/Endian.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/Format.h"
37#include <algorithm>
38
39using namespace llvm;
40
41#include "AMDGPUGenMCPseudoLowering.inc"
42
43AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx,
44 const TargetSubtargetInfo &st,
45 const AsmPrinter &ap):
46 Ctx(ctx), ST(st), AP(ap) { }
47
48static AMDGPUMCExpr::Specifier getSpecifier(unsigned MOFlags) {
49 switch (MOFlags) {
50 default:
51 return AMDGPUMCExpr::S_None;
52 case SIInstrInfo::MO_GOTPCREL:
53 case SIInstrInfo::MO_GOTPCREL64:
54 return AMDGPUMCExpr::S_GOTPCREL;
55 case SIInstrInfo::MO_GOTPCREL32_LO:
56 return AMDGPUMCExpr::S_GOTPCREL32_LO;
57 case SIInstrInfo::MO_GOTPCREL32_HI:
58 return AMDGPUMCExpr::S_GOTPCREL32_HI;
59 case SIInstrInfo::MO_REL32_LO:
60 return AMDGPUMCExpr::S_REL32_LO;
61 case SIInstrInfo::MO_REL32_HI:
62 return AMDGPUMCExpr::S_REL32_HI;
63 case SIInstrInfo::MO_REL64:
64 return AMDGPUMCExpr::S_REL64;
65 case SIInstrInfo::MO_ABS32_LO:
66 return AMDGPUMCExpr::S_ABS32_LO;
67 case SIInstrInfo::MO_ABS32_HI:
68 return AMDGPUMCExpr::S_ABS32_HI;
69 case SIInstrInfo::MO_ABS64:
70 return AMDGPUMCExpr::S_ABS64;
71 }
72}
73
74bool AMDGPUMCInstLower::lowerOperand(const MachineOperand &MO,
75 MCOperand &MCOp) const {
76 switch (MO.getType()) {
77 default:
78 break;
79 case MachineOperand::MO_Immediate:
80 MCOp = MCOperand::createImm(Val: MO.getImm());
81 return true;
82 case MachineOperand::MO_Register:
83 MCOp = MCOperand::createReg(Reg: AMDGPU::getMCReg(Reg: MO.getReg(), STI: ST));
84 return true;
85 case MachineOperand::MO_MachineBasicBlock:
86 MCOp = MCOperand::createExpr(
87 Val: MCSymbolRefExpr::create(Symbol: MO.getMBB()->getSymbol(), Ctx));
88 return true;
89 case MachineOperand::MO_GlobalAddress: {
90 const GlobalValue *GV = MO.getGlobal();
91 SmallString<128> SymbolName;
92 AP.getNameWithPrefix(Name&: SymbolName, GV);
93 MCSymbol *Sym = Ctx.getOrCreateSymbol(Name: SymbolName);
94 const MCExpr *Expr =
95 MCSymbolRefExpr::create(Symbol: Sym, specifier: getSpecifier(MOFlags: MO.getTargetFlags()), Ctx);
96 int64_t Offset = MO.getOffset();
97 if (Offset != 0) {
98 Expr = MCBinaryExpr::createAdd(LHS: Expr,
99 RHS: MCConstantExpr::create(Value: Offset, Ctx), Ctx);
100 }
101 MCOp = MCOperand::createExpr(Val: Expr);
102 return true;
103 }
104 case MachineOperand::MO_ExternalSymbol: {
105 MCSymbol *Sym = Ctx.getOrCreateSymbol(Name: StringRef(MO.getSymbolName()));
106 const MCExpr *Expr =
107 MCSymbolRefExpr::create(Symbol: Sym, specifier: getSpecifier(MOFlags: MO.getTargetFlags()), Ctx);
108 MCOp = MCOperand::createExpr(Val: Expr);
109 return true;
110 }
111 case MachineOperand::MO_BlockAddress: {
112 MCSymbol *Sym = AP.GetBlockAddressSymbol(BA: MO.getBlockAddress());
113 const MCSymbolRefExpr *Expr =
114 MCSymbolRefExpr::create(Symbol: Sym, specifier: getSpecifier(MOFlags: MO.getTargetFlags()), Ctx);
115 assert(MO.getOffset() == 0);
116 MCOp = MCOperand::createExpr(Val: Expr);
117 return true;
118 }
119 case MachineOperand::MO_RegisterMask:
120 // Regmasks are like implicit defs.
121 return false;
122 case MachineOperand::MO_MCSymbol:
123 if (MO.getTargetFlags() == SIInstrInfo::MO_FAR_BRANCH_OFFSET) {
124 MCSymbol *Sym = MO.getMCSymbol();
125 MCOp = MCOperand::createExpr(Val: Sym->getVariableValue());
126 return true;
127 }
128 break;
129 }
130 llvm_unreachable("unknown operand type");
131}
132
133// Lower true16 D16 Pseudo instruction to d16_lo/d16_hi MCInst based on
134// Dst/Data's .l/.h selection
135void AMDGPUMCInstLower::lowerT16D16Helper(const MachineInstr *MI,
136 MCInst &OutMI) const {
137 unsigned Opcode = MI->getOpcode();
138 const auto *TII = static_cast<const SIInstrInfo*>(ST.getInstrInfo());
139 const SIRegisterInfo &TRI = TII->getRegisterInfo();
140 const auto *Info = AMDGPU::getT16D16Helper(T16Op: Opcode);
141
142 llvm::AMDGPU::OpName OpName;
143 if (TII->isDS(Opcode)) {
144 if (MI->mayLoad())
145 OpName = llvm::AMDGPU::OpName::vdst;
146 else if (MI->mayStore())
147 OpName = llvm::AMDGPU::OpName::data0;
148 else
149 llvm_unreachable("LDS load or store expected");
150 } else {
151 OpName = AMDGPU::hasNamedOperand(Opcode, NamedIdx: llvm::AMDGPU::OpName::vdata)
152 ? llvm::AMDGPU::OpName::vdata
153 : llvm::AMDGPU::OpName::vdst;
154 }
155
156 // select Dst/Data
157 int VDstOrVDataIdx = AMDGPU::getNamedOperandIdx(Opcode, Name: OpName);
158 const MachineOperand &MIVDstOrVData = MI->getOperand(i: VDstOrVDataIdx);
159
160 // select hi/lo MCInst
161 bool IsHi = AMDGPU::isHi16Reg(Reg: MIVDstOrVData.getReg(), MRI: TRI);
162 Opcode = IsHi ? Info->HiOp : Info->LoOp;
163
164 int MCOpcode = TII->pseudoToMCOpcode(Opcode);
165 assert(MCOpcode != -1 &&
166 "Pseudo instruction doesn't have a target-specific version");
167 OutMI.setOpcode(MCOpcode);
168
169 // lower operands
170 for (int I = 0, E = MI->getNumExplicitOperands(); I < E; I++) {
171 const MachineOperand &MO = MI->getOperand(i: I);
172 MCOperand MCOp;
173 if (I == VDstOrVDataIdx)
174 MCOp = MCOperand::createReg(Reg: TRI.get32BitRegister(Reg: MIVDstOrVData.getReg()));
175 else
176 lowerOperand(MO, MCOp);
177 OutMI.addOperand(Op: MCOp);
178 }
179
180 if (AMDGPU::hasNamedOperand(Opcode: MCOpcode, NamedIdx: AMDGPU::OpName::vdst_in)) {
181 MCOperand MCOp;
182 lowerOperand(MO: MIVDstOrVData, MCOp);
183 OutMI.addOperand(Op: MCOp);
184 }
185}
186
187void AMDGPUMCInstLower::lowerT16FmaMixFP16(const MachineInstr *MI,
188 MCInst &OutMI) const {
189 unsigned Opcode = MI->getOpcode();
190 const auto *TII = static_cast<const SIInstrInfo *>(ST.getInstrInfo());
191 const SIRegisterInfo &TRI = TII->getRegisterInfo();
192
193 int VDstIdx = AMDGPU::getNamedOperandIdx(Opcode, Name: llvm::AMDGPU::OpName::vdst);
194 const MachineOperand &VDst = MI->getOperand(i: VDstIdx);
195 bool IsHi = AMDGPU::isHi16Reg(Reg: VDst.getReg(), MRI: TRI);
196 switch (Opcode) {
197 case AMDGPU::V_FMA_MIX_F16_t16:
198 Opcode = IsHi ? AMDGPU::V_FMA_MIXHI_F16 : AMDGPU::V_FMA_MIXLO_F16;
199 break;
200 case AMDGPU::V_FMA_MIX_BF16_t16:
201 Opcode = IsHi ? AMDGPU::V_FMA_MIXHI_BF16 : AMDGPU::V_FMA_MIXLO_BF16;
202 break;
203 }
204 int MCOpcode = TII->pseudoToMCOpcode(Opcode);
205 assert(MCOpcode != -1 &&
206 "Pseudo instruction doesn't have a target-specific version");
207 OutMI.setOpcode(MCOpcode);
208
209 // lower operands
210 for (int I = 0, E = MI->getNumExplicitOperands(); I < E; I++) {
211 const MachineOperand &MO = MI->getOperand(i: I);
212 MCOperand MCOp;
213 if (I == VDstIdx)
214 MCOp = MCOperand::createReg(Reg: TRI.get32BitRegister(Reg: VDst.getReg()));
215 else
216 lowerOperand(MO, MCOp);
217 OutMI.addOperand(Op: MCOp);
218 }
219}
220
221void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
222 unsigned Opcode = MI->getOpcode();
223 const auto *TII = static_cast<const SIInstrInfo *>(ST.getInstrInfo());
224
225 // FIXME: Should be able to handle this with lowerPseudoInstExpansion. We
226 // need to select it to the subtarget specific version, and there's no way to
227 // do that with a single pseudo source operation.
228 if (Opcode == AMDGPU::S_SETPC_B64_return)
229 Opcode = AMDGPU::S_SETPC_B64;
230 else if (Opcode == AMDGPU::SI_CALL) {
231 // SI_CALL is just S_SWAPPC_B64 with an additional operand to track the
232 // called function (which we need to remove here).
233 OutMI.setOpcode(TII->pseudoToMCOpcode(Opcode: AMDGPU::S_SWAPPC_B64));
234 MCOperand Dest, Src;
235 lowerOperand(MO: MI->getOperand(i: 0), MCOp&: Dest);
236 lowerOperand(MO: MI->getOperand(i: 1), MCOp&: Src);
237 OutMI.addOperand(Op: Dest);
238 OutMI.addOperand(Op: Src);
239 return;
240 } else if (Opcode == AMDGPU::SI_TCRETURN ||
241 Opcode == AMDGPU::SI_TCRETURN_GFX ||
242 Opcode == AMDGPU::SI_TCRETURN_CHAIN) {
243 // TODO: How to use branch immediate and avoid register+add?
244 Opcode = AMDGPU::S_SETPC_B64;
245 } else if (AMDGPU::getT16D16Helper(T16Op: Opcode)) {
246 lowerT16D16Helper(MI, OutMI);
247 return;
248 } else if (Opcode == AMDGPU::V_FMA_MIX_F16_t16 ||
249 Opcode == AMDGPU::V_FMA_MIX_BF16_t16) {
250 lowerT16FmaMixFP16(MI, OutMI);
251 return;
252 }
253
254 int MCOpcode = TII->pseudoToMCOpcode(Opcode);
255 if (MCOpcode == -1) {
256 LLVMContext &C = MI->getMF()->getFunction().getContext();
257 C.emitError(ErrorStr: "AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "
258 "a target-specific version: " + Twine(MI->getOpcode()));
259 return;
260 }
261
262 OutMI.setOpcode(MCOpcode);
263
264 for (const MachineOperand &MO : MI->explicit_operands()) {
265 MCOperand MCOp;
266 lowerOperand(MO, MCOp);
267 OutMI.addOperand(Op: MCOp);
268 }
269
270 int FIIdx = AMDGPU::getNamedOperandIdx(Opcode: MCOpcode, Name: AMDGPU::OpName::fi);
271 if (FIIdx >= (int)OutMI.getNumOperands())
272 OutMI.addOperand(Op: MCOperand::createImm(Val: 0));
273}
274
275bool AMDGPUAsmPrinter::lowerOperand(const MachineOperand &MO,
276 MCOperand &MCOp) const {
277 const GCNSubtarget &STI = MF->getSubtarget<GCNSubtarget>();
278 AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
279 return MCInstLowering.lowerOperand(MO, MCOp);
280}
281
282const MCExpr *AMDGPUAsmPrinter::lowerConstant(const Constant *CV,
283 const Constant *BaseCV,
284 uint64_t Offset) {
285
286 // Intercept LDS variables with known addresses
287 if (const GlobalVariable *GV = dyn_cast<const GlobalVariable>(Val: CV)) {
288 if (std::optional<uint32_t> Address =
289 AMDGPUMachineFunctionInfo::getLDSAbsoluteAddress(GV: *GV)) {
290 auto *IntTy = Type::getInt32Ty(C&: CV->getContext());
291 return AsmPrinter::lowerConstant(CV: ConstantInt::get(Ty: IntTy, V: *Address),
292 BaseCV, Offset);
293 }
294 }
295
296 if (const MCExpr *E = lowerAddrSpaceCast(CV, OutContext))
297 return E;
298 return AsmPrinter::lowerConstant(CV, BaseCV, Offset);
299}
300
301static void emitVGPRBlockComment(const MachineInstr *MI, const SIInstrInfo *TII,
302 const TargetRegisterInfo *TRI,
303 const SIMachineFunctionInfo *MFI,
304 MCStreamer &OS) {
305 // The instruction will only transfer a subset of the registers in the block,
306 // based on the mask that is stored in m0. We could search for the instruction
307 // that sets m0, but most of the time we'll already have the mask stored in
308 // the machine function info. Try to use that. This assumes that we only use
309 // block loads/stores for CSR spills.
310 Register RegBlock =
311 TII->getNamedOperand(MI: *MI, OperandName: MI->mayLoad() ? AMDGPU::OpName::vdst
312 : AMDGPU::OpName::vdata)
313 ->getReg();
314 Register FirstRegInBlock = TRI->getSubReg(Reg: RegBlock, Idx: AMDGPU::sub0);
315 uint32_t Mask = MFI->getMaskForVGPRBlockOps(RegisterBlock: RegBlock);
316
317 if (!Mask)
318 return; // Nothing to report
319
320 SmallString<512> TransferredRegs;
321 for (unsigned I = 0; I < sizeof(Mask) * 8; ++I) {
322 if (Mask & (1 << I)) {
323 (llvm::Twine(" ") + TRI->getRegAsmName(Reg: FirstRegInBlock + I))
324 .toVector(Out&: TransferredRegs);
325 }
326 }
327
328 OS.emitRawComment(T: " transferring at most " + TransferredRegs);
329}
330
331void AMDGPUAsmPrinter::emitInstruction(const MachineInstr *MI) {
332 if (MI->isCall())
333 collectCallEdge(MI: *MI);
334
335 // FIXME: Enable feature predicate checks once all the test pass.
336 // AMDGPU_MC::verifyInstructionPredicates(MI->getOpcode(),
337 // getSubtargetInfo().getFeatureBits());
338
339 if (MCInst OutInst; lowerPseudoInstExpansion(MI, Inst&: OutInst)) {
340 EmitToStreamer(S&: *OutStreamer, Inst: OutInst);
341 return;
342 }
343
344 const GCNSubtarget &STI = MF->getSubtarget<GCNSubtarget>();
345 AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this);
346
347 StringRef Err;
348 if (!STI.getInstrInfo()->verifyInstruction(MI: *MI, ErrInfo&: Err)) {
349 LLVMContext &C = MI->getMF()->getFunction().getContext();
350 C.emitError(ErrorStr: "Illegal instruction detected: " + Err);
351 MI->print(OS&: errs());
352 }
353
354 if (MI->isBundle()) {
355 const MachineBasicBlock *MBB = MI->getParent();
356 MachineBasicBlock::const_instr_iterator I = ++MI->getIterator();
357 while (I != MBB->instr_end() && I->isInsideBundle()) {
358 emitInstruction(MI: &*I);
359 ++I;
360 }
361 } else {
362 // We don't want these pseudo instructions encoded. They are
363 // placeholder instructions and should only be printed as
364 // comments.
365 if (MI->getOpcode() == AMDGPU::SI_RETURN_TO_EPILOG) {
366 if (isVerbose())
367 OutStreamer->emitRawComment(T: " return to shader part epilog");
368 return;
369 }
370
371 if (MI->getOpcode() == AMDGPU::WAVE_BARRIER) {
372 if (isVerbose())
373 OutStreamer->emitRawComment(T: " wave barrier");
374 return;
375 }
376
377 if (MI->getOpcode() == AMDGPU::ASYNCMARK) {
378 if (isVerbose())
379 OutStreamer->emitRawComment(T: " asyncmark");
380 return;
381 }
382
383 if (MI->getOpcode() == AMDGPU::WAIT_ASYNCMARK) {
384 if (isVerbose()) {
385 OutStreamer->emitRawComment(T: " wait_asyncmark(" +
386 Twine(MI->getOperand(i: 0).getImm()) + ")");
387 }
388 return;
389 }
390
391 if (MI->getOpcode() == AMDGPU::SCHED_BARRIER) {
392 if (isVerbose()) {
393 std::string HexString;
394 raw_string_ostream HexStream(HexString);
395 HexStream << format_hex(N: MI->getOperand(i: 0).getImm(), Width: 10, Upper: true);
396 OutStreamer->emitRawComment(T: " sched_barrier mask(" + HexString + ")");
397 }
398 return;
399 }
400
401 if (MI->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER) {
402 if (isVerbose()) {
403 std::string HexString;
404 raw_string_ostream HexStream(HexString);
405 HexStream << format_hex(N: MI->getOperand(i: 0).getImm(), Width: 10, Upper: true);
406 OutStreamer->emitRawComment(
407 T: " sched_group_barrier mask(" + HexString + ") size(" +
408 Twine(MI->getOperand(i: 1).getImm()) + ") SyncID(" +
409 Twine(MI->getOperand(i: 2).getImm()) + ")");
410 }
411 return;
412 }
413
414 if (MI->getOpcode() == AMDGPU::IGLP_OPT) {
415 if (isVerbose()) {
416 std::string HexString;
417 raw_string_ostream HexStream(HexString);
418 HexStream << format_hex(N: MI->getOperand(i: 0).getImm(), Width: 10, Upper: true);
419 OutStreamer->emitRawComment(T: " iglp_opt mask(" + HexString + ")");
420 }
421 return;
422 }
423
424 if (MI->getOpcode() == AMDGPU::SI_MASKED_UNREACHABLE) {
425 if (isVerbose())
426 OutStreamer->emitRawComment(T: " divergent unreachable");
427 return;
428 }
429
430 if (MI->isMetaInstruction()) {
431 if (isVerbose())
432 OutStreamer->emitRawComment(T: " meta instruction");
433 return;
434 }
435
436 unsigned Opc = MI->getOpcode();
437 if (LLVM_UNLIKELY(Opc == TargetOpcode::STATEPOINT ||
438 Opc == TargetOpcode::STACKMAP ||
439 Opc == TargetOpcode::PATCHPOINT)) {
440 LLVMContext &Ctx = MI->getMF()->getFunction().getContext();
441 Ctx.emitError(ErrorStr: "unhandled statepoint-like instruction");
442 OutStreamer->emitRawComment(T: "unsupported statepoint/stackmap/patchpoint");
443 return;
444 }
445
446 if (isVerbose())
447 if (STI.getInstrInfo()->isBlockLoadStore(Opcode: MI->getOpcode()))
448 emitVGPRBlockComment(MI, TII: STI.getInstrInfo(), TRI: STI.getRegisterInfo(),
449 MFI: MF->getInfo<SIMachineFunctionInfo>(),
450 OS&: *OutStreamer);
451
452 if (isVerbose() && (MI->getOpcode() == AMDGPU::S_SET_VGPR_MSB ||
453 (MI->getOpcode() == AMDGPU::S_SETREG_IMM32_B32 &&
454 STI.has1024AddressableVGPRs()))) {
455 std::optional<unsigned> V;
456 if (MI->getOpcode() == AMDGPU::S_SETREG_IMM32_B32)
457 V = AMDGPU::convertSetRegImmToVgprMSBs(MI: *MI,
458 HasSetregVGPRMSBFixup: STI.hasSetregVGPRMSBFixup());
459 else
460 V = MI->getOperand(i: 0).getImm() & 0xff;
461 if (V.has_value())
462 OutStreamer->AddComment(
463 T: " msbs: dst=" + Twine(*V >> 6) + " src0=" + Twine(*V & 3) +
464 " src1=" + Twine((*V >> 2) & 3) + " src2=" + Twine((*V >> 4) & 3));
465 }
466
467 MCInst TmpInst;
468 MCInstLowering.lower(MI, OutMI&: TmpInst);
469 EmitToStreamer(S&: *OutStreamer, Inst: TmpInst);
470
471 if (DumpCodeInstEmitter) {
472 // Disassemble instruction/operands to text
473 DisasmLines.resize(new_size: DisasmLines.size() + 1);
474 std::string &DisasmLine = DisasmLines.back();
475 raw_string_ostream DisasmStream(DisasmLine);
476
477 AMDGPUInstPrinter InstPrinter(TM.getMCAsmInfo(), *STI.getInstrInfo(),
478 *STI.getRegisterInfo());
479 InstPrinter.printInst(MI: &TmpInst, Address: 0, Annot: StringRef(), STI, O&: DisasmStream);
480
481 // Disassemble instruction/operands to hex representation.
482 SmallVector<MCFixup, 4> Fixups;
483 SmallVector<char, 16> CodeBytes;
484
485 DumpCodeInstEmitter->encodeInstruction(
486 Inst: TmpInst, CB&: CodeBytes, Fixups, STI: MF->getSubtarget<MCSubtargetInfo>());
487 HexLines.resize(new_size: HexLines.size() + 1);
488 std::string &HexLine = HexLines.back();
489 raw_string_ostream HexStream(HexLine);
490
491 for (size_t i = 0; i < CodeBytes.size(); i += 4) {
492 unsigned int CodeDWord =
493 support::endian::read32le(P: CodeBytes.data() + i);
494 HexStream << format(Fmt: "%s%08X", Vals: (i > 0 ? " " : ""), Vals: CodeDWord);
495 }
496
497 DisasmLineMaxLen = std::max(a: DisasmLineMaxLen, b: DisasmLine.size());
498 }
499 }
500}
501