1//===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Custom DAG lowering for R600
11//
12//===----------------------------------------------------------------------===//
13
14#include "R600ISelLowering.h"
15#include "AMDGPU.h"
16#include "AMDGPUSelectionDAGInfo.h"
17#include "MCTargetDesc/R600MCTargetDesc.h"
18#include "R600Defines.h"
19#include "R600MachineFunctionInfo.h"
20#include "R600Subtarget.h"
21#include "R600TargetMachine.h"
22#include "llvm/CodeGen/MachineFunction.h"
23#include "llvm/IR/IntrinsicsAMDGPU.h"
24#include "llvm/IR/IntrinsicsR600.h"
25#include "llvm/Passes/CodeGenPassBuilder.h"
26
27using namespace llvm;
28
29#define GET_CALLING_CONV_IMPL
30#include "R600GenCallingConv.inc"
31
32R600TargetLowering::R600TargetLowering(const TargetMachine &TM,
33 const R600Subtarget &STI)
34 : AMDGPUTargetLowering(TM, STI, STI), Subtarget(&STI),
35 Gen(STI.getGeneration()) {
36 addRegisterClass(VT: MVT::f32, RC: &R600::R600_Reg32RegClass);
37 addRegisterClass(VT: MVT::i32, RC: &R600::R600_Reg32RegClass);
38 addRegisterClass(VT: MVT::v2f32, RC: &R600::R600_Reg64RegClass);
39 addRegisterClass(VT: MVT::v2i32, RC: &R600::R600_Reg64RegClass);
40 addRegisterClass(VT: MVT::v4f32, RC: &R600::R600_Reg128RegClass);
41 addRegisterClass(VT: MVT::v4i32, RC: &R600::R600_Reg128RegClass);
42
43 setBooleanContents(ZeroOrNegativeOneBooleanContent);
44 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
45
46 computeRegisterProperties(TRI: Subtarget->getRegisterInfo());
47
48 // Legalize loads and stores to the private address space.
49 setOperationAction(Ops: ISD::LOAD, VTs: {MVT::i32, MVT::v2i32, MVT::v4i32}, Action: Custom);
50
51 // EXTLOAD should be the same as ZEXTLOAD. It is legal for some address
52 // spaces, so it is custom lowered to handle those where it isn't.
53 for (auto Op : {ISD::SEXTLOAD, ISD::ZEXTLOAD, ISD::EXTLOAD})
54 for (MVT VT : MVT::integer_valuetypes()) {
55 setLoadExtAction(ExtType: Op, ValVT: VT, MemVT: MVT::i1, Action: Promote);
56 setLoadExtAction(ExtType: Op, ValVT: VT, MemVT: MVT::i8, Action: Custom);
57 setLoadExtAction(ExtType: Op, ValVT: VT, MemVT: MVT::i16, Action: Custom);
58 }
59
60 // Workaround for LegalizeDAG asserting on expansion of i1 vector loads.
61 setLoadExtAction(ExtTypes: {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, ValVT: MVT::v2i32,
62 MemVT: MVT::v2i1, Action: Expand);
63
64 setLoadExtAction(ExtTypes: {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, ValVT: MVT::v4i32,
65 MemVT: MVT::v4i1, Action: Expand);
66
67 setOperationAction(Ops: ISD::STORE, VTs: {MVT::i8, MVT::i32, MVT::v2i32, MVT::v4i32},
68 Action: Custom);
69
70 setTruncStoreAction(ValVT: MVT::i32, MemVT: MVT::i8, Action: Custom);
71 setTruncStoreAction(ValVT: MVT::i32, MemVT: MVT::i16, Action: Custom);
72 // We need to include these since trunc STORES to PRIVATE need
73 // special handling to accommodate RMW
74 setTruncStoreAction(ValVT: MVT::v2i32, MemVT: MVT::v2i16, Action: Custom);
75 setTruncStoreAction(ValVT: MVT::v4i32, MemVT: MVT::v4i16, Action: Custom);
76 setTruncStoreAction(ValVT: MVT::v8i32, MemVT: MVT::v8i16, Action: Custom);
77 setTruncStoreAction(ValVT: MVT::v16i32, MemVT: MVT::v16i16, Action: Custom);
78 setTruncStoreAction(ValVT: MVT::v32i32, MemVT: MVT::v32i16, Action: Custom);
79 setTruncStoreAction(ValVT: MVT::v2i32, MemVT: MVT::v2i8, Action: Custom);
80 setTruncStoreAction(ValVT: MVT::v4i32, MemVT: MVT::v4i8, Action: Custom);
81 setTruncStoreAction(ValVT: MVT::v8i32, MemVT: MVT::v8i8, Action: Custom);
82 setTruncStoreAction(ValVT: MVT::v16i32, MemVT: MVT::v16i8, Action: Custom);
83 setTruncStoreAction(ValVT: MVT::v32i32, MemVT: MVT::v32i8, Action: Custom);
84
85 // Workaround for LegalizeDAG asserting on expansion of i1 vector stores.
86 setTruncStoreAction(ValVT: MVT::v2i32, MemVT: MVT::v2i1, Action: Expand);
87 setTruncStoreAction(ValVT: MVT::v4i32, MemVT: MVT::v4i1, Action: Expand);
88
89 // Set condition code actions
90 setCondCodeAction(CCs: {ISD::SETO, ISD::SETUO, ISD::SETLT, ISD::SETLE, ISD::SETOLT,
91 ISD::SETOLE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGE,
92 ISD::SETUGT, ISD::SETULT, ISD::SETULE},
93 VT: MVT::f32, Action: Expand);
94
95 setCondCodeAction(CCs: {ISD::SETLE, ISD::SETLT, ISD::SETULE, ISD::SETULT},
96 VT: MVT::i32, Action: Expand);
97
98 setOperationAction(Ops: {ISD::FCOS, ISD::FSIN}, VT: MVT::f32, Action: Custom);
99
100 setOperationAction(Ops: ISD::SETCC, VTs: {MVT::v4i32, MVT::v2i32}, Action: Expand);
101
102 setOperationAction(Ops: ISD::BR_CC, VTs: {MVT::i32, MVT::f32}, Action: Expand);
103 setOperationAction(Op: ISD::BRCOND, VT: MVT::Other, Action: Custom);
104
105 setOperationAction(Op: ISD::FSUB, VT: MVT::f32, Action: Expand);
106
107 setOperationAction(Ops: ISD::IS_FPCLASS,
108 VTs: {MVT::f32, MVT::v2f32, MVT::v3f32, MVT::v4f32, MVT::v5f32,
109 MVT::v6f32, MVT::v7f32, MVT::v8f32, MVT::v16f32},
110 Action: Expand);
111
112 setOperationAction(Ops: {ISD::FCEIL, ISD::FTRUNC, ISD::FROUNDEVEN, ISD::FFLOOR},
113 VT: MVT::f64, Action: Custom);
114
115 setOperationAction(Ops: ISD::SELECT_CC, VTs: {MVT::f32, MVT::i32}, Action: Custom);
116
117 setOperationAction(Ops: ISD::SETCC, VTs: {MVT::i32, MVT::f32}, Action: Expand);
118 setOperationAction(Ops: {ISD::FP_TO_UINT, ISD::FP_TO_SINT}, VTs: {MVT::i1, MVT::i64},
119 Action: Custom);
120
121 setOperationAction(Ops: ISD::SELECT, VTs: {MVT::i32, MVT::f32, MVT::v2i32, MVT::v4i32},
122 Action: Expand);
123
124 // ADD, SUB overflow.
125 // TODO: turn these into Legal?
126 if (Subtarget->hasCARRY())
127 setOperationAction(Op: ISD::UADDO, VT: MVT::i32, Action: Custom);
128
129 if (Subtarget->hasBORROW())
130 setOperationAction(Op: ISD::USUBO, VT: MVT::i32, Action: Custom);
131
132 // Expand sign extension of vectors
133 if (!Subtarget->hasBFE())
134 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: MVT::i1, Action: Expand);
135
136 setOperationAction(Ops: ISD::SIGN_EXTEND_INREG, VTs: {MVT::v2i1, MVT::v4i1}, Action: Expand);
137
138 if (!Subtarget->hasBFE())
139 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: MVT::i8, Action: Expand);
140 setOperationAction(Ops: ISD::SIGN_EXTEND_INREG, VTs: {MVT::v2i8, MVT::v4i8}, Action: Expand);
141
142 if (!Subtarget->hasBFE())
143 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: MVT::i16, Action: Expand);
144 setOperationAction(Ops: ISD::SIGN_EXTEND_INREG, VTs: {MVT::v2i16, MVT::v4i16}, Action: Expand);
145
146 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: MVT::i32, Action: Legal);
147 setOperationAction(Ops: ISD::SIGN_EXTEND_INREG, VTs: {MVT::v2i32, MVT::v4i32}, Action: Expand);
148
149 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: MVT::Other, Action: Expand);
150
151 setOperationAction(Op: ISD::FrameIndex, VT: MVT::i32, Action: Custom);
152
153 setOperationAction(Ops: ISD::EXTRACT_VECTOR_ELT,
154 VTs: {MVT::v2i32, MVT::v2f32, MVT::v4i32, MVT::v4f32}, Action: Custom);
155
156 setOperationAction(Ops: ISD::INSERT_VECTOR_ELT,
157 VTs: {MVT::v2i32, MVT::v2f32, MVT::v4i32, MVT::v4f32}, Action: Custom);
158
159 // We don't have 64-bit shifts. Thus we need either SHX i64 or SHX_PARTS i32
160 // to be Legal/Custom in order to avoid library calls.
161 setOperationAction(Ops: {ISD::SHL_PARTS, ISD::SRL_PARTS, ISD::SRA_PARTS}, VT: MVT::i32,
162 Action: Custom);
163
164 if (!Subtarget->hasFMA())
165 setOperationAction(Ops: ISD::FMA, VTs: {MVT::f32, MVT::f64}, Action: Expand);
166
167 // FIXME: May need no denormals check
168 setOperationAction(Op: ISD::FMAD, VT: MVT::f32, Action: Legal);
169
170 if (!Subtarget->hasBFI())
171 // fcopysign can be done in a single instruction with BFI.
172 setOperationAction(Ops: ISD::FCOPYSIGN, VTs: {MVT::f32, MVT::f64}, Action: Expand);
173
174 if (!Subtarget->hasBCNT(Size: 32))
175 setOperationAction(Op: ISD::CTPOP, VT: MVT::i32, Action: Expand);
176
177 if (!Subtarget->hasBCNT(Size: 64))
178 setOperationAction(Op: ISD::CTPOP, VT: MVT::i64, Action: Expand);
179
180 if (Subtarget->hasFFBH())
181 setOperationAction(Op: ISD::CTLZ_ZERO_POISON, VT: MVT::i32, Action: Custom);
182
183 if (Subtarget->hasFFBL())
184 setOperationAction(Op: ISD::CTTZ_ZERO_POISON, VT: MVT::i32, Action: Custom);
185
186 // FIXME: This was moved from AMDGPUTargetLowering, I'm not sure if we
187 // need it for R600.
188 if (Subtarget->hasBFE())
189 setHasExtractBitsInsn(true);
190
191 setOperationAction(Op: ISD::GlobalAddress, VT: MVT::i32, Action: Custom);
192 setOperationAction(Op: ISD::ADDRSPACECAST, VT: MVT::i32, Action: Custom);
193
194 // LLVM will expand these to atomic_cmp_swap(0)
195 // and atomic_swap, respectively.
196 setOperationAction(Ops: {ISD::ATOMIC_LOAD, ISD::ATOMIC_STORE}, VT: MVT::i32, Action: Expand);
197
198 // We need to custom lower some of the intrinsics
199 setOperationAction(Ops: {ISD::INTRINSIC_VOID, ISD::INTRINSIC_WO_CHAIN}, VT: MVT::Other,
200 Action: Custom);
201
202 setSchedulingPreference(Sched::Source);
203
204 setTargetDAGCombine({ISD::FP_ROUND, ISD::FP_TO_SINT, ISD::EXTRACT_VECTOR_ELT,
205 ISD::SELECT_CC, ISD::INSERT_VECTOR_ELT, ISD::LOAD});
206}
207
208static inline bool isEOP(MachineBasicBlock::iterator I) {
209 if (std::next(x: I) == I->getParent()->end())
210 return false;
211 return std::next(x: I)->getOpcode() == R600::RETURN;
212}
213
214MachineBasicBlock *
215R600TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
216 MachineBasicBlock *BB) const {
217 MachineFunction *MF = BB->getParent();
218 MachineRegisterInfo &MRI = MF->getRegInfo();
219 MachineBasicBlock::iterator I = MI;
220 const R600InstrInfo *TII = Subtarget->getInstrInfo();
221
222 switch (MI.getOpcode()) {
223 default:
224 // Replace LDS_*_RET instruction that don't have any uses with the
225 // equivalent LDS_*_NORET instruction.
226 if (TII->isLDSRetInstr(Opcode: MI.getOpcode())) {
227 int DstIdx = TII->getOperandIdx(Opcode: MI.getOpcode(), Op: R600::OpName::dst);
228 assert(DstIdx != -1);
229 MachineInstrBuilder NewMI;
230 // FIXME: getLDSNoRetOp method only handles LDS_1A1D LDS ops. Add
231 // LDS_1A2D support and remove this special case.
232 if (!MRI.use_empty(RegNo: MI.getOperand(i: DstIdx).getReg()) ||
233 MI.getOpcode() == R600::LDS_CMPST_RET)
234 return BB;
235
236 NewMI = BuildMI(BB&: *BB, I, MIMD: BB->findDebugLoc(MBBI: I),
237 MCID: TII->get(Opcode: R600::getLDSNoRetOp(Opcode: MI.getOpcode())));
238 for (const MachineOperand &MO : llvm::drop_begin(RangeOrContainer: MI.operands()))
239 NewMI.add(MO);
240 } else {
241 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, MBB: BB);
242 }
243 break;
244
245 case R600::FABS_R600: {
246 MachineInstr *NewMI = TII->buildDefaultInstruction(
247 MBB&: *BB, I, Opcode: R600::MOV, DstReg: MI.getOperand(i: 0).getReg(),
248 Src0Reg: MI.getOperand(i: 1).getReg());
249 TII->addFlag(MI&: *NewMI, SrcIdx: 0, MO_FLAG_ABS);
250 break;
251 }
252
253 case R600::FNEG_R600: {
254 MachineInstr *NewMI = TII->buildDefaultInstruction(
255 MBB&: *BB, I, Opcode: R600::MOV, DstReg: MI.getOperand(i: 0).getReg(),
256 Src0Reg: MI.getOperand(i: 1).getReg());
257 TII->addFlag(MI&: *NewMI, SrcIdx: 0, MO_FLAG_NEG);
258 break;
259 }
260
261 case R600::MASK_WRITE: {
262 Register maskedRegister = MI.getOperand(i: 0).getReg();
263 assert(maskedRegister.isVirtual());
264 MachineInstr * defInstr = MRI.getVRegDef(Reg: maskedRegister);
265 TII->addFlag(MI&: *defInstr, SrcIdx: 0, MO_FLAG_MASK);
266 break;
267 }
268
269 case R600::MOV_IMM_F32:
270 TII->buildMovImm(BB&: *BB, I, DstReg: MI.getOperand(i: 0).getReg(), Imm: MI.getOperand(i: 1)
271 .getFPImm()
272 ->getValueAPF()
273 .bitcastToAPInt()
274 .getZExtValue());
275 break;
276
277 case R600::MOV_IMM_I32:
278 TII->buildMovImm(BB&: *BB, I, DstReg: MI.getOperand(i: 0).getReg(),
279 Imm: MI.getOperand(i: 1).getImm());
280 break;
281
282 case R600::MOV_IMM_GLOBAL_ADDR: {
283 //TODO: Perhaps combine this instruction with the next if possible
284 auto MIB = TII->buildDefaultInstruction(
285 MBB&: *BB, I: MI, Opcode: R600::MOV, DstReg: MI.getOperand(i: 0).getReg(), Src0Reg: R600::ALU_LITERAL_X);
286 int Idx = TII->getOperandIdx(MI: *MIB, Op: R600::OpName::literal);
287 //TODO: Ugh this is rather ugly
288 const MachineOperand &MO = MI.getOperand(i: 1);
289 MIB->getOperand(i: Idx).ChangeToGA(GV: MO.getGlobal(), Offset: MO.getOffset(),
290 TargetFlags: MO.getTargetFlags());
291 break;
292 }
293
294 case R600::CONST_COPY: {
295 MachineInstr *NewMI = TII->buildDefaultInstruction(
296 MBB&: *BB, I: MI, Opcode: R600::MOV, DstReg: MI.getOperand(i: 0).getReg(), Src0Reg: R600::ALU_CONST);
297 TII->setImmOperand(MI&: *NewMI, Op: R600::OpName::src0_sel,
298 Imm: MI.getOperand(i: 1).getImm());
299 break;
300 }
301
302 case R600::RAT_WRITE_CACHELESS_32_eg:
303 case R600::RAT_WRITE_CACHELESS_64_eg:
304 case R600::RAT_WRITE_CACHELESS_128_eg:
305 BuildMI(BB&: *BB, I, MIMD: BB->findDebugLoc(MBBI: I), MCID: TII->get(Opcode: MI.getOpcode()))
306 .add(MO: MI.getOperand(i: 0))
307 .add(MO: MI.getOperand(i: 1))
308 .addImm(Val: isEOP(I)); // Set End of program bit
309 break;
310
311 case R600::RAT_STORE_TYPED_eg:
312 BuildMI(BB&: *BB, I, MIMD: BB->findDebugLoc(MBBI: I), MCID: TII->get(Opcode: MI.getOpcode()))
313 .add(MO: MI.getOperand(i: 0))
314 .add(MO: MI.getOperand(i: 1))
315 .add(MO: MI.getOperand(i: 2))
316 .addImm(Val: isEOP(I)); // Set End of program bit
317 break;
318
319 case R600::BRANCH:
320 BuildMI(BB&: *BB, I, MIMD: BB->findDebugLoc(MBBI: I), MCID: TII->get(Opcode: R600::JUMP))
321 .add(MO: MI.getOperand(i: 0));
322 break;
323
324 case R600::BRANCH_COND_f32: {
325 MachineInstr *NewMI =
326 BuildMI(BB&: *BB, I, MIMD: BB->findDebugLoc(MBBI: I), MCID: TII->get(Opcode: R600::PRED_X),
327 DestReg: R600::PREDICATE_BIT)
328 .add(MO: MI.getOperand(i: 1))
329 .addImm(Val: R600::PRED_SETNE)
330 .addImm(Val: 0); // Flags
331 TII->addFlag(MI&: *NewMI, SrcIdx: 0, MO_FLAG_PUSH);
332 BuildMI(BB&: *BB, I, MIMD: BB->findDebugLoc(MBBI: I), MCID: TII->get(Opcode: R600::JUMP_COND))
333 .add(MO: MI.getOperand(i: 0))
334 .addReg(RegNo: R600::PREDICATE_BIT, Flags: RegState::Kill);
335 break;
336 }
337
338 case R600::BRANCH_COND_i32: {
339 MachineInstr *NewMI =
340 BuildMI(BB&: *BB, I, MIMD: BB->findDebugLoc(MBBI: I), MCID: TII->get(Opcode: R600::PRED_X),
341 DestReg: R600::PREDICATE_BIT)
342 .add(MO: MI.getOperand(i: 1))
343 .addImm(Val: R600::PRED_SETNE_INT)
344 .addImm(Val: 0); // Flags
345 TII->addFlag(MI&: *NewMI, SrcIdx: 0, MO_FLAG_PUSH);
346 BuildMI(BB&: *BB, I, MIMD: BB->findDebugLoc(MBBI: I), MCID: TII->get(Opcode: R600::JUMP_COND))
347 .add(MO: MI.getOperand(i: 0))
348 .addReg(RegNo: R600::PREDICATE_BIT, Flags: RegState::Kill);
349 break;
350 }
351
352 case R600::EG_ExportSwz:
353 case R600::R600_ExportSwz: {
354 // Instruction is left unmodified if its not the last one of its type
355 bool isLastInstructionOfItsType = true;
356 unsigned InstExportType = MI.getOperand(i: 1).getImm();
357 for (MachineBasicBlock::iterator NextExportInst = std::next(x: I),
358 EndBlock = BB->end(); NextExportInst != EndBlock;
359 NextExportInst = std::next(x: NextExportInst)) {
360 if (NextExportInst->getOpcode() == R600::EG_ExportSwz ||
361 NextExportInst->getOpcode() == R600::R600_ExportSwz) {
362 unsigned CurrentInstExportType = NextExportInst->getOperand(i: 1)
363 .getImm();
364 if (CurrentInstExportType == InstExportType) {
365 isLastInstructionOfItsType = false;
366 break;
367 }
368 }
369 }
370 bool EOP = isEOP(I);
371 if (!EOP && !isLastInstructionOfItsType)
372 return BB;
373 unsigned CfInst = (MI.getOpcode() == R600::EG_ExportSwz) ? 84 : 40;
374 BuildMI(BB&: *BB, I, MIMD: BB->findDebugLoc(MBBI: I), MCID: TII->get(Opcode: MI.getOpcode()))
375 .add(MO: MI.getOperand(i: 0))
376 .add(MO: MI.getOperand(i: 1))
377 .add(MO: MI.getOperand(i: 2))
378 .add(MO: MI.getOperand(i: 3))
379 .add(MO: MI.getOperand(i: 4))
380 .add(MO: MI.getOperand(i: 5))
381 .add(MO: MI.getOperand(i: 6))
382 .addImm(Val: CfInst)
383 .addImm(Val: EOP);
384 break;
385 }
386 case R600::RETURN: {
387 return BB;
388 }
389 }
390
391 MI.eraseFromParent();
392 return BB;
393}
394
395//===----------------------------------------------------------------------===//
396// Custom DAG Lowering Operations
397//===----------------------------------------------------------------------===//
398
399SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
400 MachineFunction &MF = DAG.getMachineFunction();
401 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
402 switch (Op.getOpcode()) {
403 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
404 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
405 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
406 case ISD::SHL_PARTS:
407 case ISD::SRA_PARTS:
408 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
409 case ISD::UADDO: return LowerUADDSUBO(Op, DAG, mainop: ISD::ADD, ovf: AMDGPUISD::CARRY);
410 case ISD::USUBO: return LowerUADDSUBO(Op, DAG, mainop: ISD::SUB, ovf: AMDGPUISD::BORROW);
411 case ISD::FCOS:
412 case ISD::FSIN: return LowerTrig(Op, DAG);
413 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
414 case ISD::STORE: return LowerSTORE(Op, DAG);
415 case ISD::LOAD: {
416 SDValue Result = LowerLOAD(Op, DAG);
417 assert((!Result.getNode() ||
418 Result.getNode()->getNumValues() == 2) &&
419 "Load should return a value and a chain");
420 return Result;
421 }
422
423 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
424 case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
425 case ISD::FrameIndex: return lowerFrameIndex(Op, DAG);
426 case ISD::ADDRSPACECAST:
427 return lowerADDRSPACECAST(Op, DAG);
428 case ISD::INTRINSIC_VOID: {
429 SDValue Chain = Op.getOperand(i: 0);
430 unsigned IntrinsicID = Op.getConstantOperandVal(i: 1);
431 switch (IntrinsicID) {
432 case Intrinsic::r600_store_swizzle: {
433 SDLoc DL(Op);
434 const SDValue Args[8] = {
435 Chain,
436 Op.getOperand(i: 2), // Export Value
437 Op.getOperand(i: 3), // ArrayBase
438 Op.getOperand(i: 4), // Type
439 DAG.getConstant(Val: 0, DL, VT: MVT::i32), // SWZ_X
440 DAG.getConstant(Val: 1, DL, VT: MVT::i32), // SWZ_Y
441 DAG.getConstant(Val: 2, DL, VT: MVT::i32), // SWZ_Z
442 DAG.getConstant(Val: 3, DL, VT: MVT::i32) // SWZ_W
443 };
444 return DAG.getNode(Opcode: AMDGPUISD::R600_EXPORT, DL, VT: Op.getValueType(), Ops: Args);
445 }
446
447 // default for switch(IntrinsicID)
448 default: break;
449 }
450 // break out of case ISD::INTRINSIC_VOID in switch(Op.getOpcode())
451 break;
452 }
453 case ISD::INTRINSIC_WO_CHAIN: {
454 unsigned IntrinsicID = Op.getConstantOperandVal(i: 0);
455 EVT VT = Op.getValueType();
456 SDLoc DL(Op);
457 switch (IntrinsicID) {
458 case Intrinsic::r600_tex:
459 case Intrinsic::r600_texc: {
460 unsigned TextureOp;
461 switch (IntrinsicID) {
462 case Intrinsic::r600_tex:
463 TextureOp = 0;
464 break;
465 case Intrinsic::r600_texc:
466 TextureOp = 1;
467 break;
468 default:
469 llvm_unreachable("unhandled texture operation");
470 }
471
472 SDValue TexArgs[19] = {
473 DAG.getConstant(Val: TextureOp, DL, VT: MVT::i32),
474 Op.getOperand(i: 1),
475 DAG.getConstant(Val: 0, DL, VT: MVT::i32),
476 DAG.getConstant(Val: 1, DL, VT: MVT::i32),
477 DAG.getConstant(Val: 2, DL, VT: MVT::i32),
478 DAG.getConstant(Val: 3, DL, VT: MVT::i32),
479 Op.getOperand(i: 2),
480 Op.getOperand(i: 3),
481 Op.getOperand(i: 4),
482 DAG.getConstant(Val: 0, DL, VT: MVT::i32),
483 DAG.getConstant(Val: 1, DL, VT: MVT::i32),
484 DAG.getConstant(Val: 2, DL, VT: MVT::i32),
485 DAG.getConstant(Val: 3, DL, VT: MVT::i32),
486 Op.getOperand(i: 5),
487 Op.getOperand(i: 6),
488 Op.getOperand(i: 7),
489 Op.getOperand(i: 8),
490 Op.getOperand(i: 9),
491 Op.getOperand(i: 10)
492 };
493 return DAG.getNode(Opcode: AMDGPUISD::TEXTURE_FETCH, DL, VT: MVT::v4f32, Ops: TexArgs);
494 }
495 case Intrinsic::r600_dot4: {
496 SDValue Args[8] = {
497 DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: MVT::f32, N1: Op.getOperand(i: 1),
498 N2: DAG.getConstant(Val: 0, DL, VT: MVT::i32)),
499 DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: MVT::f32, N1: Op.getOperand(i: 2),
500 N2: DAG.getConstant(Val: 0, DL, VT: MVT::i32)),
501 DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: MVT::f32, N1: Op.getOperand(i: 1),
502 N2: DAG.getConstant(Val: 1, DL, VT: MVT::i32)),
503 DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: MVT::f32, N1: Op.getOperand(i: 2),
504 N2: DAG.getConstant(Val: 1, DL, VT: MVT::i32)),
505 DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: MVT::f32, N1: Op.getOperand(i: 1),
506 N2: DAG.getConstant(Val: 2, DL, VT: MVT::i32)),
507 DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: MVT::f32, N1: Op.getOperand(i: 2),
508 N2: DAG.getConstant(Val: 2, DL, VT: MVT::i32)),
509 DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: MVT::f32, N1: Op.getOperand(i: 1),
510 N2: DAG.getConstant(Val: 3, DL, VT: MVT::i32)),
511 DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: MVT::f32, N1: Op.getOperand(i: 2),
512 N2: DAG.getConstant(Val: 3, DL, VT: MVT::i32))
513 };
514 return DAG.getNode(Opcode: AMDGPUISD::DOT4, DL, VT: MVT::f32, Ops: Args);
515 }
516
517 case Intrinsic::r600_implicitarg_ptr: {
518 MVT PtrVT = getPointerTy(DL: DAG.getDataLayout(), AS: AMDGPUAS::PARAM_I_ADDRESS);
519 uint32_t ByteOffset = getImplicitParameterOffset(MF, Param: FIRST_IMPLICIT);
520 return DAG.getConstant(Val: ByteOffset, DL, VT: PtrVT);
521 }
522 case Intrinsic::r600_read_ngroups_x:
523 return LowerImplicitParameter(DAG, VT, DL, DwordOffset: 0);
524 case Intrinsic::r600_read_ngroups_y:
525 return LowerImplicitParameter(DAG, VT, DL, DwordOffset: 1);
526 case Intrinsic::r600_read_ngroups_z:
527 return LowerImplicitParameter(DAG, VT, DL, DwordOffset: 2);
528 case Intrinsic::r600_read_global_size_x:
529 return LowerImplicitParameter(DAG, VT, DL, DwordOffset: 3);
530 case Intrinsic::r600_read_global_size_y:
531 return LowerImplicitParameter(DAG, VT, DL, DwordOffset: 4);
532 case Intrinsic::r600_read_global_size_z:
533 return LowerImplicitParameter(DAG, VT, DL, DwordOffset: 5);
534 case Intrinsic::r600_read_local_size_x:
535 return LowerImplicitParameter(DAG, VT, DL, DwordOffset: 6);
536 case Intrinsic::r600_read_local_size_y:
537 return LowerImplicitParameter(DAG, VT, DL, DwordOffset: 7);
538 case Intrinsic::r600_read_local_size_z:
539 return LowerImplicitParameter(DAG, VT, DL, DwordOffset: 8);
540
541 case Intrinsic::r600_read_tgid_x:
542 case Intrinsic::amdgcn_workgroup_id_x:
543 return CreateLiveInRegisterRaw(DAG, RC: &R600::R600_TReg32RegClass,
544 Reg: R600::T1_X, VT);
545 case Intrinsic::r600_read_tgid_y:
546 case Intrinsic::amdgcn_workgroup_id_y:
547 return CreateLiveInRegisterRaw(DAG, RC: &R600::R600_TReg32RegClass,
548 Reg: R600::T1_Y, VT);
549 case Intrinsic::r600_read_tgid_z:
550 case Intrinsic::amdgcn_workgroup_id_z:
551 return CreateLiveInRegisterRaw(DAG, RC: &R600::R600_TReg32RegClass,
552 Reg: R600::T1_Z, VT);
553 case Intrinsic::r600_read_tidig_x:
554 case Intrinsic::amdgcn_workitem_id_x:
555 return CreateLiveInRegisterRaw(DAG, RC: &R600::R600_TReg32RegClass,
556 Reg: R600::T0_X, VT);
557 case Intrinsic::r600_read_tidig_y:
558 case Intrinsic::amdgcn_workitem_id_y:
559 return CreateLiveInRegisterRaw(DAG, RC: &R600::R600_TReg32RegClass,
560 Reg: R600::T0_Y, VT);
561 case Intrinsic::r600_read_tidig_z:
562 case Intrinsic::amdgcn_workitem_id_z:
563 return CreateLiveInRegisterRaw(DAG, RC: &R600::R600_TReg32RegClass,
564 Reg: R600::T0_Z, VT);
565
566 case Intrinsic::r600_recipsqrt_ieee:
567 return DAG.getNode(Opcode: AMDGPUISD::RSQ, DL, VT, Operand: Op.getOperand(i: 1));
568
569 case Intrinsic::r600_recipsqrt_clamped:
570 return DAG.getNode(Opcode: AMDGPUISD::RSQ_CLAMP, DL, VT, Operand: Op.getOperand(i: 1));
571 default:
572 return Op;
573 }
574
575 // break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())
576 break;
577 }
578 } // end switch(Op.getOpcode())
579 return SDValue();
580}
581
582void R600TargetLowering::ReplaceNodeResults(SDNode *N,
583 SmallVectorImpl<SDValue> &Results,
584 SelectionDAG &DAG) const {
585 switch (N->getOpcode()) {
586 default:
587 AMDGPUTargetLowering::ReplaceNodeResults(N, Results, DAG);
588 return;
589 case ISD::FP_TO_UINT:
590 if (N->getValueType(ResNo: 0) == MVT::i1) {
591 Results.push_back(Elt: lowerFP_TO_UINT(Op: N->getOperand(Num: 0), DAG));
592 return;
593 }
594 // Since we don't care about out of bounds values we can use FP_TO_SINT for
595 // uints too. The DAGLegalizer code for uint considers some extra cases
596 // which are not necessary here.
597 [[fallthrough]];
598 case ISD::FP_TO_SINT: {
599 if (N->getValueType(ResNo: 0) == MVT::i1) {
600 Results.push_back(Elt: lowerFP_TO_SINT(Op: N->getOperand(Num: 0), DAG));
601 return;
602 }
603
604 SDValue Result;
605 if (expandFP_TO_SINT(N, Result, DAG))
606 Results.push_back(Elt: Result);
607 return;
608 }
609 case ISD::SDIVREM: {
610 SDValue Op = SDValue(N, 1);
611 SDValue RES = LowerSDIVREM(Op, DAG);
612 Results.push_back(Elt: RES);
613 Results.push_back(Elt: RES.getValue(R: 1));
614 break;
615 }
616 case ISD::UDIVREM: {
617 SDValue Op = SDValue(N, 0);
618 LowerUDIVREM64(Op, DAG, Results);
619 break;
620 }
621 }
622}
623
624SDValue R600TargetLowering::vectorToVerticalVector(SelectionDAG &DAG,
625 SDValue Vector) const {
626 SDLoc DL(Vector);
627 EVT VecVT = Vector.getValueType();
628 EVT EltVT = VecVT.getVectorElementType();
629 SmallVector<SDValue, 8> Args;
630
631 for (unsigned i = 0, e = VecVT.getVectorNumElements(); i != e; ++i) {
632 Args.push_back(Elt: DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: EltVT, N1: Vector,
633 N2: DAG.getVectorIdxConstant(Val: i, DL)));
634 }
635
636 return DAG.getNode(Opcode: AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VT: VecVT, Ops: Args);
637}
638
639SDValue R600TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
640 SelectionDAG &DAG) const {
641 SDLoc DL(Op);
642 SDValue Vector = Op.getOperand(i: 0);
643 SDValue Index = Op.getOperand(i: 1);
644
645 if (isa<ConstantSDNode>(Val: Index) ||
646 Vector.getOpcode() == AMDGPUISD::BUILD_VERTICAL_VECTOR)
647 return Op;
648
649 Vector = vectorToVerticalVector(DAG, Vector);
650 return DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: Op.getValueType(),
651 N1: Vector, N2: Index);
652}
653
654SDValue R600TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
655 SelectionDAG &DAG) const {
656 SDLoc DL(Op);
657 SDValue Vector = Op.getOperand(i: 0);
658 SDValue Value = Op.getOperand(i: 1);
659 SDValue Index = Op.getOperand(i: 2);
660
661 if (isa<ConstantSDNode>(Val: Index) ||
662 Vector.getOpcode() == AMDGPUISD::BUILD_VERTICAL_VECTOR)
663 return Op;
664
665 Vector = vectorToVerticalVector(DAG, Vector);
666 SDValue Insert = DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL, VT: Op.getValueType(),
667 N1: Vector, N2: Value, N3: Index);
668 return vectorToVerticalVector(DAG, Vector: Insert);
669}
670
671SDValue R600TargetLowering::LowerGlobalAddress(AMDGPUMachineFunctionInfo *MFI,
672 SDValue Op,
673 SelectionDAG &DAG) const {
674 GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Val&: Op);
675 if (GSD->getAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
676 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
677
678 const DataLayout &DL = DAG.getDataLayout();
679 const GlobalValue *GV = GSD->getGlobal();
680 MVT ConstPtrVT = getPointerTy(DL, AS: AMDGPUAS::CONSTANT_ADDRESS);
681
682 SDValue GA = DAG.getTargetGlobalAddress(GV, DL: SDLoc(GSD), VT: ConstPtrVT);
683 return DAG.getNode(Opcode: AMDGPUISD::CONST_DATA_PTR, DL: SDLoc(GSD), VT: ConstPtrVT, Operand: GA);
684}
685
686SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
687 // On hw >= R700, COS/SIN input must be between -1. and 1.
688 // Thus we lower them to TRIG ( FRACT ( x / 2Pi + 0.5) - 0.5)
689 EVT VT = Op.getValueType();
690 SDValue Arg = Op.getOperand(i: 0);
691 SDLoc DL(Op);
692
693 // TODO: Should this propagate fast-math-flags?
694 SDValue FractPart = DAG.getNode(Opcode: AMDGPUISD::FRACT, DL, VT,
695 Operand: DAG.getNode(Opcode: ISD::FADD, DL, VT,
696 N1: DAG.getNode(Opcode: ISD::FMUL, DL, VT, N1: Arg,
697 N2: DAG.getConstantFP(Val: 0.15915494309, DL, VT: MVT::f32)),
698 N2: DAG.getConstantFP(Val: 0.5, DL, VT: MVT::f32)));
699 unsigned TrigNode;
700 switch (Op.getOpcode()) {
701 case ISD::FCOS:
702 TrigNode = AMDGPUISD::COS_HW;
703 break;
704 case ISD::FSIN:
705 TrigNode = AMDGPUISD::SIN_HW;
706 break;
707 default:
708 llvm_unreachable("Wrong trig opcode");
709 }
710 SDValue TrigVal = DAG.getNode(Opcode: TrigNode, DL, VT,
711 Operand: DAG.getNode(Opcode: ISD::FADD, DL, VT, N1: FractPart,
712 N2: DAG.getConstantFP(Val: -0.5, DL, VT: MVT::f32)));
713 if (Gen >= AMDGPUSubtarget::R700)
714 return TrigVal;
715 // On R600 hw, COS/SIN input must be between -Pi and Pi.
716 return DAG.getNode(Opcode: ISD::FMUL, DL, VT, N1: TrigVal,
717 N2: DAG.getConstantFP(Val: numbers::pif, DL, VT: MVT::f32));
718}
719
720SDValue R600TargetLowering::LowerShiftParts(SDValue Op,
721 SelectionDAG &DAG) const {
722 SDValue Lo, Hi;
723 expandShiftParts(N: Op.getNode(), Lo, Hi, DAG);
724 return DAG.getMergeValues(Ops: {Lo, Hi}, dl: SDLoc(Op));
725}
726
727SDValue R600TargetLowering::LowerUADDSUBO(SDValue Op, SelectionDAG &DAG,
728 unsigned mainop, unsigned ovf) const {
729 SDLoc DL(Op);
730 EVT VT = Op.getValueType();
731
732 SDValue Lo = Op.getOperand(i: 0);
733 SDValue Hi = Op.getOperand(i: 1);
734
735 SDValue OVF = DAG.getNode(Opcode: ovf, DL, VT, N1: Lo, N2: Hi);
736 // Extend sign.
737 OVF = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL, VT, N1: OVF,
738 N2: DAG.getValueType(MVT::i1));
739
740 SDValue Res = DAG.getNode(Opcode: mainop, DL, VT, N1: Lo, N2: Hi);
741
742 return DAG.getNode(Opcode: ISD::MERGE_VALUES, DL, VTList: DAG.getVTList(VT1: VT, VT2: VT), N1: Res, N2: OVF);
743}
744
745SDValue R600TargetLowering::lowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const {
746 SDLoc DL(Op);
747 return DAG.getNode(
748 Opcode: ISD::SETCC,
749 DL,
750 VT: MVT::i1,
751 N1: Op, N2: DAG.getConstantFP(Val: 1.0f, DL, VT: MVT::f32),
752 N3: DAG.getCondCode(Cond: ISD::SETEQ));
753}
754
755SDValue R600TargetLowering::lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const {
756 SDLoc DL(Op);
757 return DAG.getNode(
758 Opcode: ISD::SETCC,
759 DL,
760 VT: MVT::i1,
761 N1: Op, N2: DAG.getConstantFP(Val: -1.0f, DL, VT: MVT::f32),
762 N3: DAG.getCondCode(Cond: ISD::SETEQ));
763}
764
765SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
766 const SDLoc &DL,
767 unsigned DwordOffset) const {
768 unsigned ByteOffset = DwordOffset * 4;
769 PointerType *PtrType =
770 PointerType::get(C&: *DAG.getContext(), AddressSpace: AMDGPUAS::PARAM_I_ADDRESS);
771
772 // We shouldn't be using an offset wider than 16-bits for implicit parameters.
773 assert(isInt<16>(ByteOffset));
774
775 return DAG.getLoad(VT, dl: DL, Chain: DAG.getEntryNode(),
776 Ptr: DAG.getConstant(Val: ByteOffset, DL, VT: MVT::i32), // PTR
777 PtrInfo: MachinePointerInfo(ConstantPointerNull::get(T: PtrType)));
778}
779
780bool R600TargetLowering::isZero(SDValue Op) const {
781 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Val&: Op))
782 return Cst->isZero();
783 if (ConstantFPSDNode *CstFP = dyn_cast<ConstantFPSDNode>(Val&: Op))
784 return CstFP->isZero();
785 return false;
786}
787
788bool R600TargetLowering::isHWTrueValue(SDValue Op) const {
789 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Val&: Op)) {
790 return CFP->isOne();
791 }
792 return isAllOnesConstant(V: Op);
793}
794
795bool R600TargetLowering::isHWFalseValue(SDValue Op) const {
796 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Val&: Op)) {
797 return CFP->getValueAPF().isZero();
798 }
799 return isNullConstant(V: Op);
800}
801
802SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
803 SDLoc DL(Op);
804 EVT VT = Op.getValueType();
805
806 SDValue LHS = Op.getOperand(i: 0);
807 SDValue RHS = Op.getOperand(i: 1);
808 SDValue True = Op.getOperand(i: 2);
809 SDValue False = Op.getOperand(i: 3);
810 SDValue CC = Op.getOperand(i: 4);
811 SDValue Temp;
812
813 if (VT == MVT::f32) {
814 DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr);
815 SDValue MinMax = combineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI);
816 if (MinMax)
817 return MinMax;
818 }
819
820 // LHS and RHS are guaranteed to be the same value type
821 EVT CompareVT = LHS.getValueType();
822
823 // Check if we can lower this to a native operation.
824
825 // Try to lower to a SET* instruction:
826 //
827 // SET* can match the following patterns:
828 //
829 // select_cc f32, f32, -1, 0, cc_supported
830 // select_cc f32, f32, 1.0f, 0.0f, cc_supported
831 // select_cc i32, i32, -1, 0, cc_supported
832 //
833
834 // Move hardware True/False values to the correct operand.
835 if (isHWTrueValue(Op: False) && isHWFalseValue(Op: True)) {
836 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(Val&: CC)->get();
837 ISD::CondCode InverseCC = ISD::getSetCCInverse(Operation: CCOpcode, Type: CompareVT);
838 if (isCondCodeLegal(CC: InverseCC, VT: CompareVT.getSimpleVT())) {
839 std::swap(a&: False, b&: True);
840 CC = DAG.getCondCode(Cond: InverseCC);
841 } else {
842 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(Operation: InverseCC);
843 if (isCondCodeLegal(CC: SwapInvCC, VT: CompareVT.getSimpleVT())) {
844 std::swap(a&: False, b&: True);
845 std::swap(a&: LHS, b&: RHS);
846 CC = DAG.getCondCode(Cond: SwapInvCC);
847 }
848 }
849 }
850
851 if (isHWTrueValue(Op: True) && isHWFalseValue(Op: False) &&
852 (CompareVT == VT || VT == MVT::i32)) {
853 // This can be matched by a SET* instruction.
854 return DAG.getNode(Opcode: ISD::SELECT_CC, DL, VT, N1: LHS, N2: RHS, N3: True, N4: False, N5: CC);
855 }
856
857 // Try to lower to a CND* instruction:
858 //
859 // CND* can match the following patterns:
860 //
861 // select_cc f32, 0.0, f32, f32, cc_supported
862 // select_cc f32, 0.0, i32, i32, cc_supported
863 // select_cc i32, 0, f32, f32, cc_supported
864 // select_cc i32, 0, i32, i32, cc_supported
865 //
866
867 // Try to move the zero value to the RHS
868 if (isZero(Op: LHS)) {
869 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(Val&: CC)->get();
870 // Try swapping the operands
871 ISD::CondCode CCSwapped = ISD::getSetCCSwappedOperands(Operation: CCOpcode);
872 if (isCondCodeLegal(CC: CCSwapped, VT: CompareVT.getSimpleVT())) {
873 std::swap(a&: LHS, b&: RHS);
874 CC = DAG.getCondCode(Cond: CCSwapped);
875 } else {
876 // Try inverting the condition and then swapping the operands
877 ISD::CondCode CCInv = ISD::getSetCCInverse(Operation: CCOpcode, Type: CompareVT);
878 CCSwapped = ISD::getSetCCSwappedOperands(Operation: CCInv);
879 if (isCondCodeLegal(CC: CCSwapped, VT: CompareVT.getSimpleVT())) {
880 std::swap(a&: True, b&: False);
881 std::swap(a&: LHS, b&: RHS);
882 CC = DAG.getCondCode(Cond: CCSwapped);
883 }
884 }
885 }
886 if (isZero(Op: RHS)) {
887 SDValue Cond = LHS;
888 SDValue Zero = RHS;
889 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(Val&: CC)->get();
890 if (CompareVT != VT) {
891 // Bitcast True / False to the correct types. This will end up being
892 // a nop, but it allows us to define only a single pattern in the
893 // .TD files for each CND* instruction rather than having to have
894 // one pattern for integer True/False and one for fp True/False
895 True = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: CompareVT, Operand: True);
896 False = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: CompareVT, Operand: False);
897 }
898
899 switch (CCOpcode) {
900 case ISD::SETONE:
901 case ISD::SETUNE:
902 case ISD::SETNE:
903 CCOpcode = ISD::getSetCCInverse(Operation: CCOpcode, Type: CompareVT);
904 Temp = True;
905 True = False;
906 False = Temp;
907 break;
908 default:
909 break;
910 }
911 SDValue SelectNode = DAG.getNode(Opcode: ISD::SELECT_CC, DL, VT: CompareVT,
912 N1: Cond, N2: Zero,
913 N3: True, N4: False,
914 N5: DAG.getCondCode(Cond: CCOpcode));
915 return DAG.getNode(Opcode: ISD::BITCAST, DL, VT, Operand: SelectNode);
916 }
917
918 // If we make it this for it means we have no native instructions to handle
919 // this SELECT_CC, so we must lower it.
920 SDValue HWTrue, HWFalse;
921
922 if (CompareVT == MVT::f32) {
923 HWTrue = DAG.getConstantFP(Val: 1.0f, DL, VT: CompareVT);
924 HWFalse = DAG.getConstantFP(Val: 0.0f, DL, VT: CompareVT);
925 } else if (CompareVT == MVT::i32) {
926 HWTrue = DAG.getAllOnesConstant(DL, VT: CompareVT);
927 HWFalse = DAG.getConstant(Val: 0, DL, VT: CompareVT);
928 }
929 else {
930 llvm_unreachable("Unhandled value type in LowerSELECT_CC");
931 }
932
933 // Lower this unsupported SELECT_CC into a combination of two supported
934 // SELECT_CC operations.
935 SDValue Cond = DAG.getNode(Opcode: ISD::SELECT_CC, DL, VT: CompareVT, N1: LHS, N2: RHS, N3: HWTrue, N4: HWFalse, N5: CC);
936
937 return DAG.getNode(Opcode: ISD::SELECT_CC, DL, VT,
938 N1: Cond, N2: HWFalse,
939 N3: True, N4: False,
940 N5: DAG.getCondCode(Cond: ISD::SETNE));
941}
942
943SDValue R600TargetLowering::lowerADDRSPACECAST(SDValue Op,
944 SelectionDAG &DAG) const {
945 SDLoc SL(Op);
946 EVT VT = Op.getValueType();
947
948 const AddrSpaceCastSDNode *ASC = cast<AddrSpaceCastSDNode>(Val&: Op);
949 unsigned SrcAS = ASC->getSrcAddressSpace();
950 unsigned DestAS = ASC->getDestAddressSpace();
951
952 if (isNullConstant(V: Op.getOperand(i: 0)) && SrcAS == AMDGPUAS::FLAT_ADDRESS)
953 return DAG.getSignedConstant(Val: AMDGPU::getNullPointerValue(AS: DestAS), DL: SL, VT);
954
955 return Op;
956}
957
958/// LLVM generates byte-addressed pointers. For indirect addressing, we need to
959/// convert these pointers to a register index. Each register holds
960/// 16 bytes, (4 x 32bit sub-register), but we need to take into account the
961/// \p StackWidth, which tells us how many of the 4 sub-registers will be used
962/// for indirect addressing.
963SDValue R600TargetLowering::stackPtrToRegIndex(SDValue Ptr,
964 unsigned StackWidth,
965 SelectionDAG &DAG) const {
966 unsigned SRLPad;
967 switch(StackWidth) {
968 case 1:
969 SRLPad = 2;
970 break;
971 case 2:
972 SRLPad = 3;
973 break;
974 case 4:
975 SRLPad = 4;
976 break;
977 default: llvm_unreachable("Invalid stack width");
978 }
979
980 SDLoc DL(Ptr);
981 return DAG.getNode(Opcode: ISD::SRL, DL, VT: Ptr.getValueType(), N1: Ptr,
982 N2: DAG.getConstant(Val: SRLPad, DL, VT: MVT::i32));
983}
984
985void R600TargetLowering::getStackAddress(unsigned StackWidth,
986 unsigned ElemIdx,
987 unsigned &Channel,
988 unsigned &PtrIncr) const {
989 switch (StackWidth) {
990 default:
991 case 1:
992 Channel = 0;
993 if (ElemIdx > 0) {
994 PtrIncr = 1;
995 } else {
996 PtrIncr = 0;
997 }
998 break;
999 case 2:
1000 Channel = ElemIdx % 2;
1001 if (ElemIdx == 2) {
1002 PtrIncr = 1;
1003 } else {
1004 PtrIncr = 0;
1005 }
1006 break;
1007 case 4:
1008 Channel = ElemIdx;
1009 PtrIncr = 0;
1010 break;
1011 }
1012}
1013
1014SDValue R600TargetLowering::lowerPrivateTruncStore(StoreSDNode *Store,
1015 SelectionDAG &DAG) const {
1016 SDLoc DL(Store);
1017 //TODO: Who creates the i8 stores?
1018 assert(Store->isTruncatingStore()
1019 || Store->getValue().getValueType() == MVT::i8);
1020 assert(Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS);
1021
1022 SDValue Mask;
1023 if (Store->getMemoryVT() == MVT::i8) {
1024 assert(Store->getAlign() >= 1);
1025 Mask = DAG.getConstant(Val: 0xff, DL, VT: MVT::i32);
1026 } else if (Store->getMemoryVT() == MVT::i16) {
1027 assert(Store->getAlign() >= 2);
1028 Mask = DAG.getConstant(Val: 0xffff, DL, VT: MVT::i32);
1029 } else {
1030 llvm_unreachable("Unsupported private trunc store");
1031 }
1032
1033 SDValue OldChain = Store->getChain();
1034 bool VectorTrunc = (OldChain.getOpcode() == AMDGPUISD::DUMMY_CHAIN);
1035 // Skip dummy
1036 SDValue Chain = VectorTrunc ? OldChain->getOperand(Num: 0) : OldChain;
1037 SDValue BasePtr = Store->getBasePtr();
1038 SDValue Offset = Store->getOffset();
1039 EVT MemVT = Store->getMemoryVT();
1040
1041 SDValue LoadPtr = BasePtr;
1042 if (!Offset.isUndef()) {
1043 LoadPtr = DAG.getNode(Opcode: ISD::ADD, DL, VT: MVT::i32, N1: BasePtr, N2: Offset);
1044 }
1045
1046 // Get dword location
1047 // TODO: this should be eliminated by the future SHR ptr, 2
1048 SDValue Ptr = DAG.getNode(Opcode: ISD::AND, DL, VT: MVT::i32, N1: LoadPtr,
1049 N2: DAG.getConstant(Val: 0xfffffffc, DL, VT: MVT::i32));
1050
1051 // Load dword
1052 // TODO: can we be smarter about machine pointer info?
1053 MachinePointerInfo PtrInfo(AMDGPUAS::PRIVATE_ADDRESS);
1054 SDValue Dst = DAG.getLoad(VT: MVT::i32, dl: DL, Chain, Ptr, PtrInfo);
1055
1056 Chain = Dst.getValue(R: 1);
1057
1058 // Get offset in dword
1059 SDValue ByteIdx = DAG.getNode(Opcode: ISD::AND, DL, VT: MVT::i32, N1: LoadPtr,
1060 N2: DAG.getConstant(Val: 0x3, DL, VT: MVT::i32));
1061
1062 // Convert byte offset to bit shift
1063 SDValue ShiftAmt = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i32, N1: ByteIdx,
1064 N2: DAG.getConstant(Val: 3, DL, VT: MVT::i32));
1065
1066 // TODO: Contrary to the name of the function,
1067 // it also handles sub i32 non-truncating stores (like i1)
1068 SDValue SExtValue = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL, VT: MVT::i32,
1069 Operand: Store->getValue());
1070
1071 // Mask the value to the right type
1072 SDValue MaskedValue = DAG.getZeroExtendInReg(Op: SExtValue, DL, VT: MemVT);
1073
1074 // Shift the value in place
1075 SDValue ShiftedValue = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i32,
1076 N1: MaskedValue, N2: ShiftAmt);
1077
1078 // Shift the mask in place
1079 SDValue DstMask = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i32, N1: Mask, N2: ShiftAmt);
1080
1081 // Invert the mask. NOTE: if we had native ROL instructions we could
1082 // use inverted mask
1083 DstMask = DAG.getNOT(DL, Val: DstMask, VT: MVT::i32);
1084
1085 // Cleanup the target bits
1086 Dst = DAG.getNode(Opcode: ISD::AND, DL, VT: MVT::i32, N1: Dst, N2: DstMask);
1087
1088 // Add the new bits
1089 SDValue Value = DAG.getNode(Opcode: ISD::OR, DL, VT: MVT::i32, N1: Dst, N2: ShiftedValue);
1090
1091 // Store dword
1092 // TODO: Can we be smarter about MachinePointerInfo?
1093 SDValue NewStore = DAG.getStore(Chain, dl: DL, Val: Value, Ptr, PtrInfo);
1094
1095 // If we are part of expanded vector, make our neighbors depend on this store
1096 if (VectorTrunc) {
1097 // Make all other vector elements depend on this store
1098 Chain = DAG.getNode(Opcode: AMDGPUISD::DUMMY_CHAIN, DL, VT: MVT::Other, Operand: NewStore);
1099 DAG.ReplaceAllUsesOfValueWith(From: OldChain, To: Chain);
1100 }
1101 return NewStore;
1102}
1103
1104SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1105 StoreSDNode *StoreNode = cast<StoreSDNode>(Val&: Op);
1106 unsigned AS = StoreNode->getAddressSpace();
1107
1108 SDValue Chain = StoreNode->getChain();
1109 SDValue Ptr = StoreNode->getBasePtr();
1110 SDValue Value = StoreNode->getValue();
1111
1112 EVT VT = Value.getValueType();
1113 EVT MemVT = StoreNode->getMemoryVT();
1114 EVT PtrVT = Ptr.getValueType();
1115
1116 SDLoc DL(Op);
1117
1118 const bool TruncatingStore = StoreNode->isTruncatingStore();
1119
1120 // Neither LOCAL nor PRIVATE can do vectors at the moment
1121 if ((AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::PRIVATE_ADDRESS ||
1122 TruncatingStore) &&
1123 VT.isVector()) {
1124 if ((AS == AMDGPUAS::PRIVATE_ADDRESS) && TruncatingStore) {
1125 // Add an extra level of chain to isolate this vector
1126 SDValue NewChain = DAG.getNode(Opcode: AMDGPUISD::DUMMY_CHAIN, DL, VT: MVT::Other, Operand: Chain);
1127 SmallVector<SDValue, 4> NewOps(StoreNode->ops());
1128 NewOps[0] = NewChain;
1129 StoreNode = cast<StoreSDNode>(Val: DAG.UpdateNodeOperands(N: StoreNode, Ops: NewOps));
1130 }
1131
1132 return scalarizeVectorStore(ST: StoreNode, DAG);
1133 }
1134
1135 Align Alignment = StoreNode->getAlign();
1136 if (Alignment < MemVT.getStoreSize() &&
1137 !allowsMisalignedMemoryAccesses(VT: MemVT, AS, Alignment,
1138 Flags: StoreNode->getMemOperand()->getFlags(),
1139 IsFast: nullptr)) {
1140 return expandUnalignedStore(ST: StoreNode, DAG);
1141 }
1142
1143 SDValue DWordAddr = DAG.getNode(Opcode: ISD::SRL, DL, VT: PtrVT, N1: Ptr,
1144 N2: DAG.getConstant(Val: 2, DL, VT: PtrVT));
1145
1146 if (AS == AMDGPUAS::GLOBAL_ADDRESS) {
1147 // It is beneficial to create MSKOR here instead of combiner to avoid
1148 // artificial dependencies introduced by RMW
1149 if (TruncatingStore) {
1150 assert(VT.bitsLE(MVT::i32));
1151 SDValue MaskConstant;
1152 if (MemVT == MVT::i8) {
1153 MaskConstant = DAG.getConstant(Val: 0xFF, DL, VT: MVT::i32);
1154 } else {
1155 assert(MemVT == MVT::i16);
1156 assert(StoreNode->getAlign() >= 2);
1157 MaskConstant = DAG.getConstant(Val: 0xFFFF, DL, VT: MVT::i32);
1158 }
1159
1160 SDValue ByteIndex = DAG.getNode(Opcode: ISD::AND, DL, VT: PtrVT, N1: Ptr,
1161 N2: DAG.getConstant(Val: 0x00000003, DL, VT: PtrVT));
1162 SDValue BitShift = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: ByteIndex,
1163 N2: DAG.getConstant(Val: 3, DL, VT));
1164
1165 // Put the mask in correct place
1166 SDValue Mask = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: MaskConstant, N2: BitShift);
1167
1168 // Put the value bits in correct place
1169 SDValue TruncValue = DAG.getNode(Opcode: ISD::AND, DL, VT, N1: Value, N2: MaskConstant);
1170 SDValue ShiftedValue = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: TruncValue, N2: BitShift);
1171
1172 // XXX: If we add a 64-bit ZW register class, then we could use a 2 x i32
1173 // vector instead.
1174 SDValue Src[4] = {
1175 ShiftedValue,
1176 DAG.getConstant(Val: 0, DL, VT: MVT::i32),
1177 DAG.getConstant(Val: 0, DL, VT: MVT::i32),
1178 Mask
1179 };
1180 SDValue Input = DAG.getBuildVector(VT: MVT::v4i32, DL, Ops: Src);
1181 SDValue Args[3] = { Chain, Input, DWordAddr };
1182 return DAG.getMemIntrinsicNode(Opcode: AMDGPUISD::STORE_MSKOR, dl: DL,
1183 VTList: Op->getVTList(), Ops: Args, MemVT,
1184 MMO: StoreNode->getMemOperand());
1185 }
1186 if (Ptr->getOpcode() != AMDGPUISD::DWORDADDR && VT.bitsGE(VT: MVT::i32)) {
1187 // Convert pointer from byte address to dword address.
1188 Ptr = DAG.getNode(Opcode: AMDGPUISD::DWORDADDR, DL, VT: PtrVT, Operand: DWordAddr);
1189
1190 if (StoreNode->isIndexed()) {
1191 llvm_unreachable("Indexed stores not supported yet");
1192 } else {
1193 Chain = DAG.getStore(Chain, dl: DL, Val: Value, Ptr, MMO: StoreNode->getMemOperand());
1194 }
1195 return Chain;
1196 }
1197 }
1198
1199 // GLOBAL_ADDRESS has been handled above, LOCAL_ADDRESS allows all sizes
1200 if (AS != AMDGPUAS::PRIVATE_ADDRESS)
1201 return SDValue();
1202
1203 if (MemVT.bitsLT(VT: MVT::i32))
1204 return lowerPrivateTruncStore(Store: StoreNode, DAG);
1205
1206 // Standard i32+ store, tag it with DWORDADDR to note that the address
1207 // has been shifted
1208 if (Ptr.getOpcode() != AMDGPUISD::DWORDADDR) {
1209 Ptr = DAG.getNode(Opcode: AMDGPUISD::DWORDADDR, DL, VT: PtrVT, Operand: DWordAddr);
1210 return DAG.getStore(Chain, dl: DL, Val: Value, Ptr, MMO: StoreNode->getMemOperand());
1211 }
1212
1213 // Tagged i32+ stores will be matched by patterns
1214 return SDValue();
1215}
1216
1217// return (512 + (kc_bank << 12)
1218static int
1219ConstantAddressBlock(unsigned AddressSpace) {
1220 switch (AddressSpace) {
1221 case AMDGPUAS::CONSTANT_BUFFER_0:
1222 return 512;
1223 case AMDGPUAS::CONSTANT_BUFFER_1:
1224 return 512 + 4096;
1225 case AMDGPUAS::CONSTANT_BUFFER_2:
1226 return 512 + 4096 * 2;
1227 case AMDGPUAS::CONSTANT_BUFFER_3:
1228 return 512 + 4096 * 3;
1229 case AMDGPUAS::CONSTANT_BUFFER_4:
1230 return 512 + 4096 * 4;
1231 case AMDGPUAS::CONSTANT_BUFFER_5:
1232 return 512 + 4096 * 5;
1233 case AMDGPUAS::CONSTANT_BUFFER_6:
1234 return 512 + 4096 * 6;
1235 case AMDGPUAS::CONSTANT_BUFFER_7:
1236 return 512 + 4096 * 7;
1237 case AMDGPUAS::CONSTANT_BUFFER_8:
1238 return 512 + 4096 * 8;
1239 case AMDGPUAS::CONSTANT_BUFFER_9:
1240 return 512 + 4096 * 9;
1241 case AMDGPUAS::CONSTANT_BUFFER_10:
1242 return 512 + 4096 * 10;
1243 case AMDGPUAS::CONSTANT_BUFFER_11:
1244 return 512 + 4096 * 11;
1245 case AMDGPUAS::CONSTANT_BUFFER_12:
1246 return 512 + 4096 * 12;
1247 case AMDGPUAS::CONSTANT_BUFFER_13:
1248 return 512 + 4096 * 13;
1249 case AMDGPUAS::CONSTANT_BUFFER_14:
1250 return 512 + 4096 * 14;
1251 case AMDGPUAS::CONSTANT_BUFFER_15:
1252 return 512 + 4096 * 15;
1253 default:
1254 return -1;
1255 }
1256}
1257
1258SDValue R600TargetLowering::lowerPrivateExtLoad(SDValue Op,
1259 SelectionDAG &DAG) const {
1260 SDLoc DL(Op);
1261 LoadSDNode *Load = cast<LoadSDNode>(Val&: Op);
1262 ISD::LoadExtType ExtType = Load->getExtensionType();
1263 EVT MemVT = Load->getMemoryVT();
1264 assert(Load->getAlign() >= MemVT.getStoreSize());
1265
1266 SDValue BasePtr = Load->getBasePtr();
1267 SDValue Chain = Load->getChain();
1268 SDValue Offset = Load->getOffset();
1269
1270 SDValue LoadPtr = BasePtr;
1271 if (!Offset.isUndef()) {
1272 LoadPtr = DAG.getNode(Opcode: ISD::ADD, DL, VT: MVT::i32, N1: BasePtr, N2: Offset);
1273 }
1274
1275 // Get dword location
1276 // NOTE: this should be eliminated by the future SHR ptr, 2
1277 SDValue Ptr = DAG.getNode(Opcode: ISD::AND, DL, VT: MVT::i32, N1: LoadPtr,
1278 N2: DAG.getConstant(Val: 0xfffffffc, DL, VT: MVT::i32));
1279
1280 // Load dword
1281 // TODO: can we be smarter about machine pointer info?
1282 MachinePointerInfo PtrInfo(AMDGPUAS::PRIVATE_ADDRESS);
1283 SDValue Read = DAG.getLoad(VT: MVT::i32, dl: DL, Chain, Ptr, PtrInfo);
1284
1285 // Get offset within the register.
1286 SDValue ByteIdx = DAG.getNode(Opcode: ISD::AND, DL, VT: MVT::i32,
1287 N1: LoadPtr, N2: DAG.getConstant(Val: 0x3, DL, VT: MVT::i32));
1288
1289 // Bit offset of target byte (byteIdx * 8).
1290 SDValue ShiftAmt = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i32, N1: ByteIdx,
1291 N2: DAG.getConstant(Val: 3, DL, VT: MVT::i32));
1292
1293 // Shift to the right.
1294 SDValue Ret = DAG.getNode(Opcode: ISD::SRL, DL, VT: MVT::i32, N1: Read, N2: ShiftAmt);
1295
1296 // Eliminate the upper bits by setting them to ...
1297 EVT MemEltVT = MemVT.getScalarType();
1298
1299 if (ExtType == ISD::SEXTLOAD) { // ... ones.
1300 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1301 Ret = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL, VT: MVT::i32, N1: Ret, N2: MemEltVTNode);
1302 } else { // ... or zeros.
1303 Ret = DAG.getZeroExtendInReg(Op: Ret, DL, VT: MemEltVT);
1304 }
1305
1306 SDValue Ops[] = {
1307 Ret,
1308 Read.getValue(R: 1) // This should be our output chain
1309 };
1310
1311 return DAG.getMergeValues(Ops, dl: DL);
1312}
1313
1314SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1315 LoadSDNode *LoadNode = cast<LoadSDNode>(Val&: Op);
1316 unsigned AS = LoadNode->getAddressSpace();
1317 EVT MemVT = LoadNode->getMemoryVT();
1318 ISD::LoadExtType ExtType = LoadNode->getExtensionType();
1319
1320 if (AS == AMDGPUAS::PRIVATE_ADDRESS &&
1321 ExtType != ISD::NON_EXTLOAD && MemVT.bitsLT(VT: MVT::i32)) {
1322 return lowerPrivateExtLoad(Op, DAG);
1323 }
1324
1325 SDLoc DL(Op);
1326 EVT VT = Op.getValueType();
1327 SDValue Chain = LoadNode->getChain();
1328 SDValue Ptr = LoadNode->getBasePtr();
1329
1330 if ((LoadNode->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1331 LoadNode->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1332 VT.isVector()) {
1333 SDValue Ops[2];
1334 std::tie(args&: Ops[0], args&: Ops[1]) = scalarizeVectorLoad(LD: LoadNode, DAG);
1335 return DAG.getMergeValues(Ops, dl: DL);
1336 }
1337
1338 // This is still used for explicit load from addrspace(8)
1339 int ConstantBlock = ConstantAddressBlock(AddressSpace: LoadNode->getAddressSpace());
1340 if (ConstantBlock > -1 &&
1341 ((LoadNode->getExtensionType() == ISD::NON_EXTLOAD) ||
1342 (LoadNode->getExtensionType() == ISD::ZEXTLOAD))) {
1343 SDValue Result;
1344 if (isa<Constant>(Val: LoadNode->getMemOperand()->getValue()) ||
1345 isa<ConstantSDNode>(Val: Ptr)) {
1346 return constBufferLoad(LoadNode, Block: LoadNode->getAddressSpace(), DAG);
1347 }
1348 // TODO: Does this even work?
1349 // non-constant ptr can't be folded, keeps it as a v4f32 load
1350 Result = DAG.getNode(Opcode: AMDGPUISD::CONST_ADDRESS, DL, VT: MVT::v4i32,
1351 N1: DAG.getNode(Opcode: ISD::SRL, DL, VT: MVT::i32, N1: Ptr,
1352 N2: DAG.getConstant(Val: 4, DL, VT: MVT::i32)),
1353 N2: DAG.getConstant(Val: LoadNode->getAddressSpace() -
1354 AMDGPUAS::CONSTANT_BUFFER_0,
1355 DL, VT: MVT::i32));
1356
1357 if (!VT.isVector()) {
1358 Result = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: MVT::i32, N1: Result,
1359 N2: DAG.getConstant(Val: 0, DL, VT: MVT::i32));
1360 }
1361
1362 SDValue MergedValues[2] = {
1363 Result,
1364 Chain
1365 };
1366 return DAG.getMergeValues(Ops: MergedValues, dl: DL);
1367 }
1368
1369 // For most operations returning SDValue() will result in the node being
1370 // expanded by the DAG Legalizer. This is not the case for ISD::LOAD, so we
1371 // need to manually expand loads that may be legal in some address spaces and
1372 // illegal in others. SEXT loads from CONSTANT_BUFFER_0 are supported for
1373 // compute shaders, since the data is sign extended when it is uploaded to the
1374 // buffer. However SEXT loads from other address spaces are not supported, so
1375 // we need to expand them here.
1376 if (LoadNode->getExtensionType() == ISD::SEXTLOAD) {
1377 assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8));
1378 SDValue NewLoad = DAG.getExtLoad(
1379 ExtType: ISD::EXTLOAD, dl: DL, VT, Chain, Ptr, PtrInfo: LoadNode->getPointerInfo(), MemVT,
1380 Alignment: LoadNode->getAlign(), MMOFlags: LoadNode->getMemOperand()->getFlags());
1381 SDValue Res = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL, VT, N1: NewLoad,
1382 N2: DAG.getValueType(MemVT));
1383
1384 SDValue MergedValues[2] = { Res, Chain };
1385 return DAG.getMergeValues(Ops: MergedValues, dl: DL);
1386 }
1387
1388 if (LoadNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1389 return SDValue();
1390 }
1391
1392 // DWORDADDR ISD marks already shifted address
1393 if (Ptr.getOpcode() != AMDGPUISD::DWORDADDR) {
1394 assert(VT == MVT::i32);
1395 Ptr = DAG.getNode(Opcode: ISD::SRL, DL, VT: MVT::i32, N1: Ptr, N2: DAG.getConstant(Val: 2, DL, VT: MVT::i32));
1396 Ptr = DAG.getNode(Opcode: AMDGPUISD::DWORDADDR, DL, VT: MVT::i32, Operand: Ptr);
1397 return DAG.getLoad(VT: MVT::i32, dl: DL, Chain, Ptr, MMO: LoadNode->getMemOperand());
1398 }
1399 return SDValue();
1400}
1401
1402SDValue R600TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1403 SDValue Chain = Op.getOperand(i: 0);
1404 SDValue Cond = Op.getOperand(i: 1);
1405 SDValue Jump = Op.getOperand(i: 2);
1406
1407 return DAG.getNode(Opcode: AMDGPUISD::BRANCH_COND, DL: SDLoc(Op), VT: Op.getValueType(),
1408 N1: Chain, N2: Jump, N3: Cond);
1409}
1410
1411SDValue R600TargetLowering::lowerFrameIndex(SDValue Op,
1412 SelectionDAG &DAG) const {
1413 MachineFunction &MF = DAG.getMachineFunction();
1414 const R600FrameLowering *TFL = Subtarget->getFrameLowering();
1415
1416 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Val&: Op);
1417
1418 unsigned FrameIndex = FIN->getIndex();
1419 Register IgnoredFrameReg;
1420 StackOffset Offset =
1421 TFL->getFrameIndexReference(MF, FI: FrameIndex, FrameReg&: IgnoredFrameReg);
1422 return DAG.getConstant(Val: Offset.getFixed() * 4 * TFL->getStackWidth(MF),
1423 DL: SDLoc(Op), VT: Op.getValueType());
1424}
1425
1426CCAssignFn *R600TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1427 bool IsVarArg) const {
1428 switch (CC) {
1429 case CallingConv::AMDGPU_KERNEL:
1430 case CallingConv::SPIR_KERNEL:
1431 case CallingConv::C:
1432 case CallingConv::Fast:
1433 case CallingConv::Cold:
1434 llvm_unreachable("kernels should not be handled here");
1435 case CallingConv::AMDGPU_VS:
1436 case CallingConv::AMDGPU_GS:
1437 case CallingConv::AMDGPU_PS:
1438 case CallingConv::AMDGPU_CS:
1439 case CallingConv::AMDGPU_HS:
1440 case CallingConv::AMDGPU_ES:
1441 case CallingConv::AMDGPU_LS:
1442 return CC_R600;
1443 default:
1444 reportFatalUsageError(reason: "unsupported calling convention");
1445 }
1446}
1447
1448/// XXX Only kernel functions are supported, so we can assume for now that
1449/// every function is a kernel function, but in the future we should use
1450/// separate calling conventions for kernel and non-kernel functions.
1451SDValue R600TargetLowering::LowerFormalArguments(
1452 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1453 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
1454 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1455 SmallVector<CCValAssign, 16> ArgLocs;
1456 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1457 *DAG.getContext());
1458 MachineFunction &MF = DAG.getMachineFunction();
1459
1460 if (AMDGPU::isShader(CC: CallConv)) {
1461 CCInfo.AnalyzeFormalArguments(Ins, Fn: CCAssignFnForCall(CC: CallConv, IsVarArg: isVarArg));
1462 } else {
1463 analyzeFormalArgumentsCompute(State&: CCInfo, Ins);
1464 }
1465
1466 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
1467 CCValAssign &VA = ArgLocs[i];
1468 const ISD::InputArg &In = Ins[i];
1469 EVT VT = In.VT;
1470 EVT MemVT = VA.getLocVT();
1471 if (!VT.isVector() && MemVT.isVector()) {
1472 // Get load source type if scalarized.
1473 MemVT = MemVT.getVectorElementType();
1474 }
1475
1476 if (VT.isInteger() && !MemVT.isInteger())
1477 MemVT = MemVT.changeTypeToInteger();
1478
1479 if (AMDGPU::isShader(CC: CallConv)) {
1480 Register Reg = MF.addLiveIn(PReg: VA.getLocReg(), RC: &R600::R600_Reg128RegClass);
1481 SDValue Register = DAG.getCopyFromReg(Chain, dl: DL, Reg, VT);
1482 InVals.push_back(Elt: Register);
1483 continue;
1484 }
1485
1486 // i64 isn't a legal type, so the register type used ends up as i32, which
1487 // isn't expected here. It attempts to create this sextload, but it ends up
1488 // being invalid. Somehow this seems to work with i64 arguments, but breaks
1489 // for <1 x i64>.
1490
1491 // The first 36 bytes of the input buffer contains information about
1492 // thread group and global sizes.
1493 ISD::LoadExtType Ext = ISD::NON_EXTLOAD;
1494 if (MemVT.getScalarSizeInBits() != VT.getScalarSizeInBits()) {
1495 if (VT.isFloatingPoint()) {
1496 Ext = ISD::EXTLOAD;
1497 } else {
1498 // FIXME: This should really check the extload type, but the handling of
1499 // extload vector parameters seems to be broken.
1500
1501 // Ext = In.Flags.isSExt() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
1502 Ext = ISD::SEXTLOAD;
1503 }
1504 }
1505
1506 // Compute the offset from the value.
1507 // XXX - I think PartOffset should give you this, but it seems to give the
1508 // size of the register which isn't useful.
1509
1510 unsigned PartOffset = VA.getLocMemOffset();
1511 Align Alignment = commonAlignment(A: Align(VT.getStoreSize()), Offset: PartOffset);
1512
1513 MachinePointerInfo PtrInfo(AMDGPUAS::PARAM_I_ADDRESS);
1514 SDValue Arg = DAG.getLoad(
1515 AM: ISD::UNINDEXED, ExtType: Ext, VT, dl: DL, Chain,
1516 Ptr: DAG.getConstant(Val: PartOffset, DL, VT: MVT::i32), Offset: DAG.getUNDEF(VT: MVT::i32),
1517 PtrInfo,
1518 MemVT, Alignment, MMOFlags: MachineMemOperand::MONonTemporal |
1519 MachineMemOperand::MODereferenceable |
1520 MachineMemOperand::MOInvariant);
1521
1522 InVals.push_back(Elt: Arg);
1523 }
1524 return Chain;
1525}
1526
1527EVT R600TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1528 EVT VT) const {
1529 if (!VT.isVector())
1530 return MVT::i32;
1531 return VT.changeVectorElementTypeToInteger();
1532}
1533
1534bool R600TargetLowering::canMergeStoresTo(unsigned AS, EVT MemVT,
1535 const MachineFunction &MF) const {
1536 // Local and Private addresses do not handle vectors. Limit to i32
1537 if ((AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::PRIVATE_ADDRESS)) {
1538 return (MemVT.getSizeInBits() <= 32);
1539 }
1540 return true;
1541}
1542
1543bool R600TargetLowering::allowsMisalignedMemoryAccesses(
1544 EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags,
1545 unsigned *IsFast) const {
1546 if (IsFast)
1547 *IsFast = 0;
1548
1549 if (!VT.isSimple() || VT == MVT::Other)
1550 return false;
1551
1552 if (VT.bitsLT(VT: MVT::i32))
1553 return false;
1554
1555 // TODO: This is a rough estimate.
1556 if (IsFast)
1557 *IsFast = 1;
1558
1559 return VT.bitsGT(VT: MVT::i32) && Alignment >= Align(4);
1560}
1561
1562static SDValue CompactSwizzlableVector(
1563 SelectionDAG &DAG, SDValue VectorEntry,
1564 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1565 assert(RemapSwizzle.empty());
1566
1567 SDLoc DL(VectorEntry);
1568 EVT EltTy = VectorEntry.getValueType().getVectorElementType();
1569
1570 SDValue NewBldVec[4];
1571 for (unsigned i = 0; i < 4; i++)
1572 NewBldVec[i] = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: EltTy, N1: VectorEntry,
1573 N2: DAG.getIntPtrConstant(Val: i, DL));
1574
1575 for (unsigned i = 0; i < 4; i++) {
1576 if (NewBldVec[i].isUndef())
1577 // We mask write here to teach later passes that the ith element of this
1578 // vector is undef. Thus we can use it to reduce 128 bits reg usage,
1579 // break false dependencies and additionally make assembly easier to read.
1580 RemapSwizzle[i] = 7; // SEL_MASK_WRITE
1581 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val&: NewBldVec[i])) {
1582 if (C->isZero()) {
1583 RemapSwizzle[i] = 4; // SEL_0
1584 NewBldVec[i] = DAG.getUNDEF(VT: MVT::f32);
1585 } else if (C->isOne()) {
1586 RemapSwizzle[i] = 5; // SEL_1
1587 NewBldVec[i] = DAG.getUNDEF(VT: MVT::f32);
1588 }
1589 }
1590
1591 if (NewBldVec[i].isUndef())
1592 continue;
1593
1594 for (unsigned j = 0; j < i; j++) {
1595 if (NewBldVec[i] == NewBldVec[j]) {
1596 NewBldVec[i] = DAG.getUNDEF(VT: NewBldVec[i].getValueType());
1597 RemapSwizzle[i] = j;
1598 break;
1599 }
1600 }
1601 }
1602
1603 return DAG.getBuildVector(VT: VectorEntry.getValueType(), DL: SDLoc(VectorEntry),
1604 Ops: NewBldVec);
1605}
1606
1607static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry,
1608 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1609 assert(RemapSwizzle.empty());
1610
1611 SDLoc DL(VectorEntry);
1612 EVT EltTy = VectorEntry.getValueType().getVectorElementType();
1613
1614 SDValue NewBldVec[4];
1615 bool isUnmovable[4] = {false, false, false, false};
1616 for (unsigned i = 0; i < 4; i++)
1617 NewBldVec[i] = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: EltTy, N1: VectorEntry,
1618 N2: DAG.getIntPtrConstant(Val: i, DL));
1619
1620 for (unsigned i = 0; i < 4; i++) {
1621 RemapSwizzle[i] = i;
1622 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1623 unsigned Idx = NewBldVec[i].getConstantOperandVal(i: 1);
1624 if (i == Idx)
1625 isUnmovable[Idx] = true;
1626 }
1627 }
1628
1629 for (unsigned i = 0; i < 4; i++) {
1630 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1631 unsigned Idx = NewBldVec[i].getConstantOperandVal(i: 1);
1632 if (isUnmovable[Idx])
1633 continue;
1634 // Swap i and Idx
1635 std::swap(a&: NewBldVec[Idx], b&: NewBldVec[i]);
1636 std::swap(a&: RemapSwizzle[i], b&: RemapSwizzle[Idx]);
1637 break;
1638 }
1639 }
1640
1641 return DAG.getBuildVector(VT: VectorEntry.getValueType(), DL: SDLoc(VectorEntry),
1642 Ops: NewBldVec);
1643}
1644
1645SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector, SDValue Swz[],
1646 SelectionDAG &DAG,
1647 const SDLoc &DL) const {
1648 // Old -> New swizzle values
1649 DenseMap<unsigned, unsigned> SwizzleRemap;
1650
1651 BuildVector = CompactSwizzlableVector(DAG, VectorEntry: BuildVector, RemapSwizzle&: SwizzleRemap);
1652 for (unsigned i = 0; i < 4; i++) {
1653 unsigned Idx = Swz[i]->getAsZExtVal();
1654 auto It = SwizzleRemap.find(Val: Idx);
1655 if (It != SwizzleRemap.end())
1656 Swz[i] = DAG.getConstant(Val: It->second, DL, VT: MVT::i32);
1657 }
1658
1659 SwizzleRemap.clear();
1660 BuildVector = ReorganizeVector(DAG, VectorEntry: BuildVector, RemapSwizzle&: SwizzleRemap);
1661 for (unsigned i = 0; i < 4; i++) {
1662 unsigned Idx = Swz[i]->getAsZExtVal();
1663 auto It = SwizzleRemap.find(Val: Idx);
1664 if (It != SwizzleRemap.end())
1665 Swz[i] = DAG.getConstant(Val: It->second, DL, VT: MVT::i32);
1666 }
1667
1668 return BuildVector;
1669}
1670
1671SDValue R600TargetLowering::constBufferLoad(LoadSDNode *LoadNode, int Block,
1672 SelectionDAG &DAG) const {
1673 SDLoc DL(LoadNode);
1674 EVT VT = LoadNode->getValueType(ResNo: 0);
1675 SDValue Chain = LoadNode->getChain();
1676 SDValue Ptr = LoadNode->getBasePtr();
1677 assert (isa<ConstantSDNode>(Ptr));
1678
1679 //TODO: Support smaller loads
1680 if (LoadNode->getMemoryVT().getScalarType() != MVT::i32 || !ISD::isNON_EXTLoad(N: LoadNode))
1681 return SDValue();
1682
1683 if (LoadNode->getAlign() < Align(4))
1684 return SDValue();
1685
1686 int ConstantBlock = ConstantAddressBlock(AddressSpace: Block);
1687
1688 SDValue Slots[4];
1689 for (unsigned i = 0; i < 4; i++) {
1690 // We want Const position encoded with the following formula :
1691 // (((512 + (kc_bank << 12) + const_index) << 2) + chan)
1692 // const_index is Ptr computed by llvm using an alignment of 16.
1693 // Thus we add (((512 + (kc_bank << 12)) + chan ) * 4 here and
1694 // then div by 4 at the ISel step
1695 SDValue NewPtr = DAG.getNode(Opcode: ISD::ADD, DL, VT: Ptr.getValueType(), N1: Ptr,
1696 N2: DAG.getConstant(Val: 4 * i + ConstantBlock * 16, DL, VT: MVT::i32));
1697 Slots[i] = DAG.getNode(Opcode: AMDGPUISD::CONST_ADDRESS, DL, VT: MVT::i32, Operand: NewPtr);
1698 }
1699 EVT NewVT = MVT::v4i32;
1700 unsigned NumElements = 4;
1701 if (VT.isVector()) {
1702 NewVT = VT;
1703 NumElements = VT.getVectorNumElements();
1704 }
1705 SDValue Result = DAG.getBuildVector(VT: NewVT, DL, Ops: ArrayRef(Slots, NumElements));
1706 if (!VT.isVector()) {
1707 Result = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: MVT::i32, N1: Result,
1708 N2: DAG.getConstant(Val: 0, DL, VT: MVT::i32));
1709 }
1710 SDValue MergedValues[2] = {
1711 Result,
1712 Chain
1713 };
1714 return DAG.getMergeValues(Ops: MergedValues, dl: DL);
1715}
1716
1717//===----------------------------------------------------------------------===//
1718// Custom DAG Optimizations
1719//===----------------------------------------------------------------------===//
1720
1721SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
1722 DAGCombinerInfo &DCI) const {
1723 SelectionDAG &DAG = DCI.DAG;
1724 SDLoc DL(N);
1725
1726 switch (N->getOpcode()) {
1727 // (f32 fp_round (f64 uint_to_fp a)) -> (f32 uint_to_fp a)
1728 case ISD::FP_ROUND: {
1729 SDValue Arg = N->getOperand(Num: 0);
1730 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) {
1731 return DAG.getNode(Opcode: ISD::UINT_TO_FP, DL, VT: N->getValueType(ResNo: 0),
1732 Operand: Arg.getOperand(i: 0));
1733 }
1734 break;
1735 }
1736
1737 // (i32 fp_to_sint (fneg (select_cc f32, f32, 1.0, 0.0 cc))) ->
1738 // (i32 select_cc f32, f32, -1, 0 cc)
1739 //
1740 // Mesa's GLSL frontend generates the above pattern a lot and we can lower
1741 // this to one of the SET*_DX10 instructions.
1742 case ISD::FP_TO_SINT: {
1743 SDValue FNeg = N->getOperand(Num: 0);
1744 if (FNeg.getOpcode() != ISD::FNEG) {
1745 return SDValue();
1746 }
1747 SDValue SelectCC = FNeg.getOperand(i: 0);
1748 if (SelectCC.getOpcode() != ISD::SELECT_CC ||
1749 SelectCC.getOperand(i: 0).getValueType() != MVT::f32 || // LHS
1750 SelectCC.getOperand(i: 2).getValueType() != MVT::f32 || // True
1751 !isHWTrueValue(Op: SelectCC.getOperand(i: 2)) ||
1752 !isHWFalseValue(Op: SelectCC.getOperand(i: 3))) {
1753 return SDValue();
1754 }
1755
1756 return DAG.getNode(Opcode: ISD::SELECT_CC, DL, VT: N->getValueType(ResNo: 0),
1757 N1: SelectCC.getOperand(i: 0), // LHS
1758 N2: SelectCC.getOperand(i: 1), // RHS
1759 N3: DAG.getAllOnesConstant(DL, VT: MVT::i32), // True
1760 N4: DAG.getConstant(Val: 0, DL, VT: MVT::i32), // False
1761 N5: SelectCC.getOperand(i: 4)); // CC
1762 }
1763
1764 // insert_vector_elt (build_vector elt0, ... , eltN), NewEltIdx, idx
1765 // => build_vector elt0, ... , NewEltIdx, ... , eltN
1766 case ISD::INSERT_VECTOR_ELT: {
1767 SDValue InVec = N->getOperand(Num: 0);
1768 SDValue InVal = N->getOperand(Num: 1);
1769 SDValue EltNo = N->getOperand(Num: 2);
1770
1771 // If the inserted element is an UNDEF, just use the input vector.
1772 if (InVal.isUndef())
1773 return InVec;
1774
1775 EVT VT = InVec.getValueType();
1776
1777 // If we can't generate a legal BUILD_VECTOR, exit
1778 if (!isOperationLegal(Op: ISD::BUILD_VECTOR, VT))
1779 return SDValue();
1780
1781 // Check that we know which element is being inserted
1782 if (!isa<ConstantSDNode>(Val: EltNo))
1783 return SDValue();
1784 unsigned Elt = EltNo->getAsZExtVal();
1785
1786 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
1787 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
1788 // vector elements.
1789 SmallVector<SDValue, 8> Ops;
1790 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
1791 Ops.append(in_start: InVec.getNode()->op_begin(),
1792 in_end: InVec.getNode()->op_end());
1793 } else if (InVec.isUndef()) {
1794 unsigned NElts = VT.getVectorNumElements();
1795 Ops.append(NumInputs: NElts, Elt: DAG.getUNDEF(VT: InVal.getValueType()));
1796 } else {
1797 return SDValue();
1798 }
1799
1800 // Insert the element
1801 if (Elt < Ops.size()) {
1802 // All the operands of BUILD_VECTOR must have the same type;
1803 // we enforce that here.
1804 EVT OpVT = Ops[0].getValueType();
1805 if (InVal.getValueType() != OpVT)
1806 InVal = OpVT.bitsGT(VT: InVal.getValueType()) ?
1807 DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: OpVT, Operand: InVal) :
1808 DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: OpVT, Operand: InVal);
1809 Ops[Elt] = InVal;
1810 }
1811
1812 // Return the new vector
1813 return DAG.getBuildVector(VT, DL, Ops);
1814 }
1815
1816 // Extract_vec (Build_vector) generated by custom lowering
1817 // also needs to be customly combined
1818 case ISD::EXTRACT_VECTOR_ELT: {
1819 SDValue Arg = N->getOperand(Num: 0);
1820 if (Arg.getOpcode() == ISD::BUILD_VECTOR) {
1821 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Val: N->getOperand(Num: 1))) {
1822 unsigned Element = Const->getZExtValue();
1823 return Arg->getOperand(Num: Element);
1824 }
1825 }
1826 if (Arg.getOpcode() == ISD::BITCAST &&
1827 Arg.getOperand(i: 0).getOpcode() == ISD::BUILD_VECTOR &&
1828 (Arg.getOperand(i: 0).getValueType().getVectorNumElements() ==
1829 Arg.getValueType().getVectorNumElements())) {
1830 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Val: N->getOperand(Num: 1))) {
1831 unsigned Element = Const->getZExtValue();
1832 return DAG.getNode(Opcode: ISD::BITCAST, DL, VTList: N->getVTList(),
1833 N: Arg->getOperand(Num: 0).getOperand(i: Element));
1834 }
1835 }
1836 break;
1837 }
1838
1839 case ISD::SELECT_CC: {
1840 // Try common optimizations
1841 if (SDValue Ret = AMDGPUTargetLowering::PerformDAGCombine(N, DCI))
1842 return Ret;
1843
1844 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, seteq ->
1845 // selectcc x, y, a, b, inv(cc)
1846 //
1847 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne ->
1848 // selectcc x, y, a, b, cc
1849 SDValue LHS = N->getOperand(Num: 0);
1850 if (LHS.getOpcode() != ISD::SELECT_CC) {
1851 return SDValue();
1852 }
1853
1854 SDValue RHS = N->getOperand(Num: 1);
1855 SDValue True = N->getOperand(Num: 2);
1856 SDValue False = N->getOperand(Num: 3);
1857 ISD::CondCode NCC = cast<CondCodeSDNode>(Val: N->getOperand(Num: 4))->get();
1858
1859 if (LHS.getOperand(i: 2).getNode() != True.getNode() ||
1860 LHS.getOperand(i: 3).getNode() != False.getNode() ||
1861 RHS.getNode() != False.getNode()) {
1862 return SDValue();
1863 }
1864
1865 switch (NCC) {
1866 default: return SDValue();
1867 case ISD::SETNE: return LHS;
1868 case ISD::SETEQ: {
1869 ISD::CondCode LHSCC = cast<CondCodeSDNode>(Val: LHS.getOperand(i: 4))->get();
1870 LHSCC = ISD::getSetCCInverse(Operation: LHSCC, Type: LHS.getOperand(i: 0).getValueType());
1871 if (DCI.isBeforeLegalizeOps() ||
1872 isCondCodeLegal(CC: LHSCC, VT: LHS.getOperand(i: 0).getSimpleValueType()))
1873 return DAG.getSelectCC(DL,
1874 LHS: LHS.getOperand(i: 0),
1875 RHS: LHS.getOperand(i: 1),
1876 True: LHS.getOperand(i: 2),
1877 False: LHS.getOperand(i: 3),
1878 Cond: LHSCC);
1879 break;
1880 }
1881 }
1882 return SDValue();
1883 }
1884
1885 case AMDGPUISD::R600_EXPORT: {
1886 SDValue Arg = N->getOperand(Num: 1);
1887 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
1888 break;
1889
1890 SDValue NewArgs[8] = {
1891 N->getOperand(Num: 0), // Chain
1892 SDValue(),
1893 N->getOperand(Num: 2), // ArrayBase
1894 N->getOperand(Num: 3), // Type
1895 N->getOperand(Num: 4), // SWZ_X
1896 N->getOperand(Num: 5), // SWZ_Y
1897 N->getOperand(Num: 6), // SWZ_Z
1898 N->getOperand(Num: 7) // SWZ_W
1899 };
1900 NewArgs[1] = OptimizeSwizzle(BuildVector: N->getOperand(Num: 1), Swz: &NewArgs[4], DAG, DL);
1901 return DAG.getNode(Opcode: AMDGPUISD::R600_EXPORT, DL, VTList: N->getVTList(), Ops: NewArgs);
1902 }
1903 case AMDGPUISD::TEXTURE_FETCH: {
1904 SDValue Arg = N->getOperand(Num: 1);
1905 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
1906 break;
1907
1908 SDValue NewArgs[19] = {
1909 N->getOperand(Num: 0),
1910 N->getOperand(Num: 1),
1911 N->getOperand(Num: 2),
1912 N->getOperand(Num: 3),
1913 N->getOperand(Num: 4),
1914 N->getOperand(Num: 5),
1915 N->getOperand(Num: 6),
1916 N->getOperand(Num: 7),
1917 N->getOperand(Num: 8),
1918 N->getOperand(Num: 9),
1919 N->getOperand(Num: 10),
1920 N->getOperand(Num: 11),
1921 N->getOperand(Num: 12),
1922 N->getOperand(Num: 13),
1923 N->getOperand(Num: 14),
1924 N->getOperand(Num: 15),
1925 N->getOperand(Num: 16),
1926 N->getOperand(Num: 17),
1927 N->getOperand(Num: 18),
1928 };
1929 NewArgs[1] = OptimizeSwizzle(BuildVector: N->getOperand(Num: 1), Swz: &NewArgs[2], DAG, DL);
1930 return DAG.getNode(Opcode: AMDGPUISD::TEXTURE_FETCH, DL, VTList: N->getVTList(), Ops: NewArgs);
1931 }
1932
1933 case ISD::LOAD: {
1934 LoadSDNode *LoadNode = cast<LoadSDNode>(Val: N);
1935 SDValue Ptr = LoadNode->getBasePtr();
1936 if (LoadNode->getAddressSpace() == AMDGPUAS::PARAM_I_ADDRESS &&
1937 isa<ConstantSDNode>(Val: Ptr))
1938 return constBufferLoad(LoadNode, Block: AMDGPUAS::CONSTANT_BUFFER_0, DAG);
1939 break;
1940 }
1941
1942 default: break;
1943 }
1944
1945 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1946}
1947
1948bool R600TargetLowering::FoldOperand(SDNode *ParentNode, unsigned SrcIdx,
1949 SDValue &Src, SDValue &Neg, SDValue &Abs,
1950 SDValue &Sel, SDValue &Imm,
1951 SelectionDAG &DAG) const {
1952 const R600InstrInfo *TII = Subtarget->getInstrInfo();
1953 if (!Src.isMachineOpcode())
1954 return false;
1955
1956 switch (Src.getMachineOpcode()) {
1957 case R600::FNEG_R600:
1958 if (!Neg.getNode())
1959 return false;
1960 Src = Src.getOperand(i: 0);
1961 Neg = DAG.getTargetConstant(Val: 1, DL: SDLoc(ParentNode), VT: MVT::i32);
1962 return true;
1963 case R600::FABS_R600:
1964 if (!Abs.getNode())
1965 return false;
1966 Src = Src.getOperand(i: 0);
1967 Abs = DAG.getTargetConstant(Val: 1, DL: SDLoc(ParentNode), VT: MVT::i32);
1968 return true;
1969 case R600::CONST_COPY: {
1970 unsigned Opcode = ParentNode->getMachineOpcode();
1971 bool HasDst = TII->getOperandIdx(Opcode, Op: R600::OpName::dst) > -1;
1972
1973 if (!Sel.getNode())
1974 return false;
1975
1976 SDValue CstOffset = Src.getOperand(i: 0);
1977 if (ParentNode->getValueType(ResNo: 0).isVector())
1978 return false;
1979
1980 // Gather constants values
1981 int SrcIndices[] = {
1982 TII->getOperandIdx(Opcode, Op: R600::OpName::src0),
1983 TII->getOperandIdx(Opcode, Op: R600::OpName::src1),
1984 TII->getOperandIdx(Opcode, Op: R600::OpName::src2),
1985 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_X),
1986 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_Y),
1987 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_Z),
1988 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_W),
1989 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_X),
1990 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_Y),
1991 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_Z),
1992 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_W)
1993 };
1994 std::vector<unsigned> Consts;
1995 for (int OtherSrcIdx : SrcIndices) {
1996 int OtherSelIdx = TII->getSelIdx(Opcode, SrcIdx: OtherSrcIdx);
1997 if (OtherSrcIdx < 0 || OtherSelIdx < 0)
1998 continue;
1999 if (HasDst) {
2000 OtherSrcIdx--;
2001 OtherSelIdx--;
2002 }
2003 if (RegisterSDNode *Reg =
2004 dyn_cast<RegisterSDNode>(Val: ParentNode->getOperand(Num: OtherSrcIdx))) {
2005 if (Reg->getReg() == R600::ALU_CONST) {
2006 Consts.push_back(x: ParentNode->getConstantOperandVal(Num: OtherSelIdx));
2007 }
2008 }
2009 }
2010
2011 ConstantSDNode *Cst = cast<ConstantSDNode>(Val&: CstOffset);
2012 Consts.push_back(x: Cst->getZExtValue());
2013 if (!TII->fitsConstReadLimitations(Consts)) {
2014 return false;
2015 }
2016
2017 Sel = CstOffset;
2018 Src = DAG.getRegister(Reg: R600::ALU_CONST, VT: MVT::f32);
2019 return true;
2020 }
2021 case R600::MOV_IMM_GLOBAL_ADDR:
2022 // Check if the Imm slot is used. Taken from below.
2023 if (Imm->getAsZExtVal())
2024 return false;
2025 Imm = Src.getOperand(i: 0);
2026 Src = DAG.getRegister(Reg: R600::ALU_LITERAL_X, VT: MVT::i32);
2027 return true;
2028 case R600::MOV_IMM_I32:
2029 case R600::MOV_IMM_F32: {
2030 unsigned ImmReg = R600::ALU_LITERAL_X;
2031 uint64_t ImmValue = 0;
2032
2033 if (Src.getMachineOpcode() == R600::MOV_IMM_F32) {
2034 ConstantFPSDNode *FPC = cast<ConstantFPSDNode>(Val: Src.getOperand(i: 0));
2035 float FloatValue = FPC->getValueAPF().convertToFloat();
2036 if (FloatValue == 0.0) {
2037 ImmReg = R600::ZERO;
2038 } else if (FloatValue == 0.5) {
2039 ImmReg = R600::HALF;
2040 } else if (FloatValue == 1.0) {
2041 ImmReg = R600::ONE;
2042 } else {
2043 ImmValue = FPC->getValueAPF().bitcastToAPInt().getZExtValue();
2044 }
2045 } else {
2046 uint64_t Value = Src.getConstantOperandVal(i: 0);
2047 if (Value == 0) {
2048 ImmReg = R600::ZERO;
2049 } else if (Value == 1) {
2050 ImmReg = R600::ONE_INT;
2051 } else {
2052 ImmValue = Value;
2053 }
2054 }
2055
2056 // Check that we aren't already using an immediate.
2057 // XXX: It's possible for an instruction to have more than one
2058 // immediate operand, but this is not supported yet.
2059 if (ImmReg == R600::ALU_LITERAL_X) {
2060 if (!Imm.getNode())
2061 return false;
2062 ConstantSDNode *C = cast<ConstantSDNode>(Val&: Imm);
2063 if (C->getZExtValue())
2064 return false;
2065 Imm = DAG.getTargetConstant(Val: ImmValue, DL: SDLoc(ParentNode), VT: MVT::i32);
2066 }
2067 Src = DAG.getRegister(Reg: ImmReg, VT: MVT::i32);
2068 return true;
2069 }
2070 default:
2071 return false;
2072 }
2073}
2074
2075/// Fold the instructions after selecting them
2076SDNode *R600TargetLowering::PostISelFolding(MachineSDNode *Node,
2077 SelectionDAG &DAG) const {
2078 const R600InstrInfo *TII = Subtarget->getInstrInfo();
2079 if (!Node->isMachineOpcode())
2080 return Node;
2081
2082 unsigned Opcode = Node->getMachineOpcode();
2083 SDValue FakeOp;
2084
2085 std::vector<SDValue> Ops(Node->op_begin(), Node->op_end());
2086
2087 if (Opcode == R600::DOT_4) {
2088 int OperandIdx[] = {
2089 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_X),
2090 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_Y),
2091 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_Z),
2092 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_W),
2093 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_X),
2094 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_Y),
2095 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_Z),
2096 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_W)
2097 };
2098 int NegIdx[] = {
2099 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_neg_X),
2100 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_neg_Y),
2101 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_neg_Z),
2102 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_neg_W),
2103 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_neg_X),
2104 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_neg_Y),
2105 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_neg_Z),
2106 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_neg_W)
2107 };
2108 int AbsIdx[] = {
2109 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_abs_X),
2110 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_abs_Y),
2111 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_abs_Z),
2112 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_abs_W),
2113 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_abs_X),
2114 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_abs_Y),
2115 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_abs_Z),
2116 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_abs_W)
2117 };
2118 for (unsigned i = 0; i < 8; i++) {
2119 if (OperandIdx[i] < 0)
2120 return Node;
2121 SDValue &Src = Ops[OperandIdx[i] - 1];
2122 SDValue &Neg = Ops[NegIdx[i] - 1];
2123 SDValue &Abs = Ops[AbsIdx[i] - 1];
2124 bool HasDst = TII->getOperandIdx(Opcode, Op: R600::OpName::dst) > -1;
2125 int SelIdx = TII->getSelIdx(Opcode, SrcIdx: OperandIdx[i]);
2126 if (HasDst)
2127 SelIdx--;
2128 SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
2129 if (FoldOperand(ParentNode: Node, SrcIdx: i, Src, Neg, Abs, Sel, Imm&: FakeOp, DAG))
2130 return DAG.getMachineNode(Opcode, dl: SDLoc(Node), VTs: Node->getVTList(), Ops);
2131 }
2132 } else if (Opcode == R600::REG_SEQUENCE) {
2133 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) {
2134 SDValue &Src = Ops[i];
2135 if (FoldOperand(ParentNode: Node, SrcIdx: i, Src, Neg&: FakeOp, Abs&: FakeOp, Sel&: FakeOp, Imm&: FakeOp, DAG))
2136 return DAG.getMachineNode(Opcode, dl: SDLoc(Node), VTs: Node->getVTList(), Ops);
2137 }
2138 } else {
2139 if (!TII->hasInstrModifiers(Opcode))
2140 return Node;
2141 int OperandIdx[] = {
2142 TII->getOperandIdx(Opcode, Op: R600::OpName::src0),
2143 TII->getOperandIdx(Opcode, Op: R600::OpName::src1),
2144 TII->getOperandIdx(Opcode, Op: R600::OpName::src2)
2145 };
2146 int NegIdx[] = {
2147 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_neg),
2148 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_neg),
2149 TII->getOperandIdx(Opcode, Op: R600::OpName::src2_neg)
2150 };
2151 int AbsIdx[] = {
2152 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_abs),
2153 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_abs),
2154 -1
2155 };
2156 for (unsigned i = 0; i < 3; i++) {
2157 if (OperandIdx[i] < 0)
2158 return Node;
2159 SDValue &Src = Ops[OperandIdx[i] - 1];
2160 SDValue &Neg = Ops[NegIdx[i] - 1];
2161 SDValue FakeAbs;
2162 SDValue &Abs = (AbsIdx[i] > -1) ? Ops[AbsIdx[i] - 1] : FakeAbs;
2163 bool HasDst = TII->getOperandIdx(Opcode, Op: R600::OpName::dst) > -1;
2164 int SelIdx = TII->getSelIdx(Opcode, SrcIdx: OperandIdx[i]);
2165 int ImmIdx = TII->getOperandIdx(Opcode, Op: R600::OpName::literal);
2166 if (HasDst) {
2167 SelIdx--;
2168 ImmIdx--;
2169 }
2170 SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
2171 SDValue &Imm = Ops[ImmIdx];
2172 if (FoldOperand(ParentNode: Node, SrcIdx: i, Src, Neg, Abs, Sel, Imm, DAG))
2173 return DAG.getMachineNode(Opcode, dl: SDLoc(Node), VTs: Node->getVTList(), Ops);
2174 }
2175 }
2176
2177 return Node;
2178}
2179
2180TargetLowering::AtomicExpansionKind
2181R600TargetLowering::shouldExpandAtomicRMWInIR(const AtomicRMWInst *RMW) const {
2182 switch (RMW->getOperation()) {
2183 case AtomicRMWInst::Nand:
2184 case AtomicRMWInst::FAdd:
2185 case AtomicRMWInst::FSub:
2186 case AtomicRMWInst::FMax:
2187 case AtomicRMWInst::FMin:
2188 case AtomicRMWInst::USubCond:
2189 case AtomicRMWInst::USubSat:
2190 return AtomicExpansionKind::CmpXChg;
2191 case AtomicRMWInst::UIncWrap:
2192 case AtomicRMWInst::UDecWrap:
2193 // FIXME: Cayman at least appears to have instructions for this, but the
2194 // instruction definitions appear to be missing.
2195 return AtomicExpansionKind::CmpXChg;
2196 case AtomicRMWInst::Xchg: {
2197 const DataLayout &DL = RMW->getFunction()->getDataLayout();
2198 unsigned ValSize = DL.getTypeSizeInBits(Ty: RMW->getType());
2199 if (ValSize == 32 || ValSize == 64)
2200 return AtomicExpansionKind::None;
2201 return AtomicExpansionKind::CmpXChg;
2202 }
2203 default:
2204 if (auto *IntTy = dyn_cast<IntegerType>(Val: RMW->getType())) {
2205 unsigned Size = IntTy->getBitWidth();
2206 if (Size == 32 || Size == 64)
2207 return AtomicExpansionKind::None;
2208 }
2209
2210 return AtomicExpansionKind::CmpXChg;
2211 }
2212
2213 llvm_unreachable("covered atomicrmw op switch");
2214}
2215