1//===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// Custom DAG lowering for R600
11//
12//===----------------------------------------------------------------------===//
13
14#include "R600ISelLowering.h"
15#include "AMDGPU.h"
16#include "AMDGPUSelectionDAGInfo.h"
17#include "MCTargetDesc/R600MCTargetDesc.h"
18#include "R600Defines.h"
19#include "R600MachineFunctionInfo.h"
20#include "R600Subtarget.h"
21#include "llvm/CodeGen/MachineFunction.h"
22#include "llvm/IR/IntrinsicsAMDGPU.h"
23#include "llvm/IR/IntrinsicsR600.h"
24
25using namespace llvm;
26
27#define GET_CALLING_CONV_IMPL
28#include "R600GenCallingConv.inc"
29
30R600TargetLowering::R600TargetLowering(const TargetMachine &TM,
31 const R600Subtarget &STI)
32 : AMDGPUTargetLowering(TM, STI, STI), Subtarget(&STI),
33 Gen(STI.getGeneration()) {
34 addRegisterClass(VT: MVT::f32, RC: &R600::R600_Reg32RegClass);
35 addRegisterClass(VT: MVT::i32, RC: &R600::R600_Reg32RegClass);
36 addRegisterClass(VT: MVT::v2f32, RC: &R600::R600_Reg64RegClass);
37 addRegisterClass(VT: MVT::v2i32, RC: &R600::R600_Reg64RegClass);
38 addRegisterClass(VT: MVT::v4f32, RC: &R600::R600_Reg128RegClass);
39 addRegisterClass(VT: MVT::v4i32, RC: &R600::R600_Reg128RegClass);
40
41 setBooleanContents(ZeroOrNegativeOneBooleanContent);
42 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
43
44 computeRegisterProperties(TRI: Subtarget->getRegisterInfo());
45
46 // Legalize loads and stores to the private address space.
47 setOperationAction(Ops: ISD::LOAD, VTs: {MVT::i32, MVT::v2i32, MVT::v4i32}, Action: Custom);
48
49 // EXTLOAD should be the same as ZEXTLOAD. It is legal for some address
50 // spaces, so it is custom lowered to handle those where it isn't.
51 for (auto Op : {ISD::SEXTLOAD, ISD::ZEXTLOAD, ISD::EXTLOAD})
52 for (MVT VT : MVT::integer_valuetypes()) {
53 setLoadExtAction(ExtType: Op, ValVT: VT, MemVT: MVT::i1, Action: Promote);
54 setLoadExtAction(ExtType: Op, ValVT: VT, MemVT: MVT::i8, Action: Custom);
55 setLoadExtAction(ExtType: Op, ValVT: VT, MemVT: MVT::i16, Action: Custom);
56 }
57
58 // Workaround for LegalizeDAG asserting on expansion of i1 vector loads.
59 setLoadExtAction(ExtTypes: {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, ValVT: MVT::v2i32,
60 MemVT: MVT::v2i1, Action: Expand);
61
62 setLoadExtAction(ExtTypes: {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}, ValVT: MVT::v4i32,
63 MemVT: MVT::v4i1, Action: Expand);
64
65 setOperationAction(Ops: ISD::STORE, VTs: {MVT::i8, MVT::i32, MVT::v2i32, MVT::v4i32},
66 Action: Custom);
67
68 setTruncStoreAction(ValVT: MVT::i32, MemVT: MVT::i8, Action: Custom);
69 setTruncStoreAction(ValVT: MVT::i32, MemVT: MVT::i16, Action: Custom);
70 // We need to include these since trunc STORES to PRIVATE need
71 // special handling to accommodate RMW
72 setTruncStoreAction(ValVT: MVT::v2i32, MemVT: MVT::v2i16, Action: Custom);
73 setTruncStoreAction(ValVT: MVT::v4i32, MemVT: MVT::v4i16, Action: Custom);
74 setTruncStoreAction(ValVT: MVT::v8i32, MemVT: MVT::v8i16, Action: Custom);
75 setTruncStoreAction(ValVT: MVT::v16i32, MemVT: MVT::v16i16, Action: Custom);
76 setTruncStoreAction(ValVT: MVT::v32i32, MemVT: MVT::v32i16, Action: Custom);
77 setTruncStoreAction(ValVT: MVT::v2i32, MemVT: MVT::v2i8, Action: Custom);
78 setTruncStoreAction(ValVT: MVT::v4i32, MemVT: MVT::v4i8, Action: Custom);
79 setTruncStoreAction(ValVT: MVT::v8i32, MemVT: MVT::v8i8, Action: Custom);
80 setTruncStoreAction(ValVT: MVT::v16i32, MemVT: MVT::v16i8, Action: Custom);
81 setTruncStoreAction(ValVT: MVT::v32i32, MemVT: MVT::v32i8, Action: Custom);
82
83 // Workaround for LegalizeDAG asserting on expansion of i1 vector stores.
84 setTruncStoreAction(ValVT: MVT::v2i32, MemVT: MVT::v2i1, Action: Expand);
85 setTruncStoreAction(ValVT: MVT::v4i32, MemVT: MVT::v4i1, Action: Expand);
86
87 // Set condition code actions
88 setCondCodeAction(CCs: {ISD::SETO, ISD::SETUO, ISD::SETLT, ISD::SETLE, ISD::SETOLT,
89 ISD::SETOLE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGE,
90 ISD::SETUGT, ISD::SETULT, ISD::SETULE},
91 VT: MVT::f32, Action: Expand);
92
93 setCondCodeAction(CCs: {ISD::SETLE, ISD::SETLT, ISD::SETULE, ISD::SETULT},
94 VT: MVT::i32, Action: Expand);
95
96 setOperationAction(Ops: {ISD::FCOS, ISD::FSIN}, VT: MVT::f32, Action: Custom);
97
98 setOperationAction(Ops: ISD::SETCC, VTs: {MVT::v4i32, MVT::v2i32}, Action: Expand);
99
100 setOperationAction(Ops: ISD::BR_CC, VTs: {MVT::i32, MVT::f32}, Action: Expand);
101 setOperationAction(Op: ISD::BRCOND, VT: MVT::Other, Action: Custom);
102
103 setOperationAction(Op: ISD::FSUB, VT: MVT::f32, Action: Expand);
104
105 setOperationAction(Ops: ISD::IS_FPCLASS,
106 VTs: {MVT::f32, MVT::v2f32, MVT::v3f32, MVT::v4f32, MVT::v5f32,
107 MVT::v6f32, MVT::v7f32, MVT::v8f32, MVT::v16f32},
108 Action: Expand);
109
110 setOperationAction(Ops: {ISD::FCEIL, ISD::FTRUNC, ISD::FROUNDEVEN, ISD::FFLOOR},
111 VT: MVT::f64, Action: Custom);
112
113 setOperationAction(Op: ISD::FPOW, VT: MVT::f32, Action: Legal);
114
115 setOperationAction(Ops: ISD::SELECT_CC, VTs: {MVT::f32, MVT::i32}, Action: Custom);
116
117 setOperationAction(Ops: ISD::SETCC, VTs: {MVT::i32, MVT::f32}, Action: Expand);
118 setOperationAction(Ops: {ISD::FP_TO_UINT, ISD::FP_TO_SINT}, VTs: {MVT::i1, MVT::i64},
119 Action: Custom);
120
121 setOperationAction(Ops: ISD::SELECT, VTs: {MVT::i32, MVT::f32, MVT::v2i32, MVT::v4i32},
122 Action: Expand);
123
124 // ADD, SUB overflow.
125 // TODO: turn these into Legal?
126 if (Subtarget->hasCARRY())
127 setOperationAction(Op: ISD::UADDO, VT: MVT::i32, Action: Custom);
128
129 if (Subtarget->hasBORROW())
130 setOperationAction(Op: ISD::USUBO, VT: MVT::i32, Action: Custom);
131
132 // Expand sign extension of vectors
133 if (!Subtarget->hasBFE())
134 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: MVT::i1, Action: Expand);
135
136 setOperationAction(Ops: ISD::SIGN_EXTEND_INREG, VTs: {MVT::v2i1, MVT::v4i1}, Action: Expand);
137
138 if (!Subtarget->hasBFE())
139 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: MVT::i8, Action: Expand);
140 setOperationAction(Ops: ISD::SIGN_EXTEND_INREG, VTs: {MVT::v2i8, MVT::v4i8}, Action: Expand);
141
142 if (!Subtarget->hasBFE())
143 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: MVT::i16, Action: Expand);
144 setOperationAction(Ops: ISD::SIGN_EXTEND_INREG, VTs: {MVT::v2i16, MVT::v4i16}, Action: Expand);
145
146 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: MVT::i32, Action: Legal);
147 setOperationAction(Ops: ISD::SIGN_EXTEND_INREG, VTs: {MVT::v2i32, MVT::v4i32}, Action: Expand);
148
149 setOperationAction(Op: ISD::SIGN_EXTEND_INREG, VT: MVT::Other, Action: Expand);
150
151 setOperationAction(Op: ISD::FrameIndex, VT: MVT::i32, Action: Custom);
152
153 setOperationAction(Ops: ISD::EXTRACT_VECTOR_ELT,
154 VTs: {MVT::v2i32, MVT::v2f32, MVT::v4i32, MVT::v4f32}, Action: Custom);
155
156 setOperationAction(Ops: ISD::INSERT_VECTOR_ELT,
157 VTs: {MVT::v2i32, MVT::v2f32, MVT::v4i32, MVT::v4f32}, Action: Custom);
158
159 // We don't have 64-bit shifts. Thus we need either SHX i64 or SHX_PARTS i32
160 // to be Legal/Custom in order to avoid library calls.
161 setOperationAction(Ops: {ISD::SHL_PARTS, ISD::SRL_PARTS, ISD::SRA_PARTS}, VT: MVT::i32,
162 Action: Custom);
163
164 if (!Subtarget->hasFMA())
165 setOperationAction(Ops: ISD::FMA, VTs: {MVT::f32, MVT::f64}, Action: Expand);
166
167 // FIXME: May need no denormals check
168 setOperationAction(Op: ISD::FMAD, VT: MVT::f32, Action: Legal);
169
170 if (!Subtarget->hasBFI())
171 // fcopysign can be done in a single instruction with BFI.
172 setOperationAction(Ops: ISD::FCOPYSIGN, VTs: {MVT::f32, MVT::f64}, Action: Expand);
173
174 if (!Subtarget->hasBCNT(Size: 32))
175 setOperationAction(Op: ISD::CTPOP, VT: MVT::i32, Action: Expand);
176
177 if (!Subtarget->hasBCNT(Size: 64))
178 setOperationAction(Op: ISD::CTPOP, VT: MVT::i64, Action: Expand);
179
180 if (Subtarget->hasFFBH())
181 setOperationAction(Op: ISD::CTLZ_ZERO_POISON, VT: MVT::i32, Action: Custom);
182
183 if (Subtarget->hasFFBL())
184 setOperationAction(Op: ISD::CTTZ_ZERO_POISON, VT: MVT::i32, Action: Custom);
185
186 // FIXME: This was moved from AMDGPUTargetLowering, I'm not sure if we
187 // need it for R600.
188 if (Subtarget->hasBFE())
189 setHasExtractBitsInsn(true);
190
191 setOperationAction(Op: ISD::GlobalAddress, VT: MVT::i32, Action: Custom);
192 setOperationAction(Op: ISD::ADDRSPACECAST, VT: MVT::i32, Action: Custom);
193
194 // LLVM will expand these to atomic_cmp_swap(0)
195 // and atomic_swap, respectively.
196 setOperationAction(Ops: {ISD::ATOMIC_LOAD, ISD::ATOMIC_STORE}, VT: MVT::i32, Action: Expand);
197
198 // We need to custom lower some of the intrinsics
199 setOperationAction(Ops: {ISD::INTRINSIC_VOID, ISD::INTRINSIC_WO_CHAIN}, VT: MVT::Other,
200 Action: Custom);
201
202 setSchedulingPreference(Sched::Source);
203
204 setTargetDAGCombine({ISD::FP_ROUND, ISD::FP_TO_SINT, ISD::EXTRACT_VECTOR_ELT,
205 ISD::SELECT_CC, ISD::INSERT_VECTOR_ELT, ISD::LOAD});
206}
207
208static inline bool isEOP(MachineBasicBlock::iterator I) {
209 if (std::next(x: I) == I->getParent()->end())
210 return false;
211 return std::next(x: I)->getOpcode() == R600::RETURN;
212}
213
214MachineBasicBlock *
215R600TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
216 MachineBasicBlock *BB) const {
217 MachineFunction *MF = BB->getParent();
218 MachineRegisterInfo &MRI = MF->getRegInfo();
219 MachineBasicBlock::iterator I = MI;
220 const R600InstrInfo *TII = Subtarget->getInstrInfo();
221
222 switch (MI.getOpcode()) {
223 default:
224 // Replace LDS_*_RET instruction that don't have any uses with the
225 // equivalent LDS_*_NORET instruction.
226 if (TII->isLDSRetInstr(Opcode: MI.getOpcode())) {
227 int DstIdx = TII->getOperandIdx(Opcode: MI.getOpcode(), Op: R600::OpName::dst);
228 assert(DstIdx != -1);
229 MachineInstrBuilder NewMI;
230 // FIXME: getLDSNoRetOp method only handles LDS_1A1D LDS ops. Add
231 // LDS_1A2D support and remove this special case.
232 if (!MRI.use_empty(RegNo: MI.getOperand(i: DstIdx).getReg()) ||
233 MI.getOpcode() == R600::LDS_CMPST_RET)
234 return BB;
235
236 NewMI = BuildMI(BB&: *BB, I, MIMD: BB->findDebugLoc(MBBI: I),
237 MCID: TII->get(Opcode: R600::getLDSNoRetOp(Opcode: MI.getOpcode())));
238 for (const MachineOperand &MO : llvm::drop_begin(RangeOrContainer: MI.operands()))
239 NewMI.add(MO);
240 } else {
241 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, MBB: BB);
242 }
243 break;
244
245 case R600::FABS_R600: {
246 MachineInstr *NewMI = TII->buildDefaultInstruction(
247 MBB&: *BB, I, Opcode: R600::MOV, DstReg: MI.getOperand(i: 0).getReg(),
248 Src0Reg: MI.getOperand(i: 1).getReg());
249 TII->addFlag(MI&: *NewMI, SrcIdx: 0, MO_FLAG_ABS);
250 break;
251 }
252
253 case R600::FNEG_R600: {
254 MachineInstr *NewMI = TII->buildDefaultInstruction(
255 MBB&: *BB, I, Opcode: R600::MOV, DstReg: MI.getOperand(i: 0).getReg(),
256 Src0Reg: MI.getOperand(i: 1).getReg());
257 TII->addFlag(MI&: *NewMI, SrcIdx: 0, MO_FLAG_NEG);
258 break;
259 }
260
261 case R600::MASK_WRITE: {
262 Register maskedRegister = MI.getOperand(i: 0).getReg();
263 assert(maskedRegister.isVirtual());
264 MachineInstr * defInstr = MRI.getVRegDef(Reg: maskedRegister);
265 TII->addFlag(MI&: *defInstr, SrcIdx: 0, MO_FLAG_MASK);
266 break;
267 }
268
269 case R600::MOV_IMM_F32:
270 TII->buildMovImm(BB&: *BB, I, DstReg: MI.getOperand(i: 0).getReg(), Imm: MI.getOperand(i: 1)
271 .getFPImm()
272 ->getValueAPF()
273 .bitcastToAPInt()
274 .getZExtValue());
275 break;
276
277 case R600::MOV_IMM_I32:
278 TII->buildMovImm(BB&: *BB, I, DstReg: MI.getOperand(i: 0).getReg(),
279 Imm: MI.getOperand(i: 1).getImm());
280 break;
281
282 case R600::MOV_IMM_GLOBAL_ADDR: {
283 //TODO: Perhaps combine this instruction with the next if possible
284 auto MIB = TII->buildDefaultInstruction(
285 MBB&: *BB, I: MI, Opcode: R600::MOV, DstReg: MI.getOperand(i: 0).getReg(), Src0Reg: R600::ALU_LITERAL_X);
286 int Idx = TII->getOperandIdx(MI: *MIB, Op: R600::OpName::literal);
287 //TODO: Ugh this is rather ugly
288 const MachineOperand &MO = MI.getOperand(i: 1);
289 MIB->getOperand(i: Idx).ChangeToGA(GV: MO.getGlobal(), Offset: MO.getOffset(),
290 TargetFlags: MO.getTargetFlags());
291 break;
292 }
293
294 case R600::CONST_COPY: {
295 MachineInstr *NewMI = TII->buildDefaultInstruction(
296 MBB&: *BB, I: MI, Opcode: R600::MOV, DstReg: MI.getOperand(i: 0).getReg(), Src0Reg: R600::ALU_CONST);
297 TII->setImmOperand(MI&: *NewMI, Op: R600::OpName::src0_sel,
298 Imm: MI.getOperand(i: 1).getImm());
299 break;
300 }
301
302 case R600::RAT_WRITE_CACHELESS_32_eg:
303 case R600::RAT_WRITE_CACHELESS_64_eg:
304 case R600::RAT_WRITE_CACHELESS_128_eg:
305 BuildMI(BB&: *BB, I, MIMD: BB->findDebugLoc(MBBI: I), MCID: TII->get(Opcode: MI.getOpcode()))
306 .add(MO: MI.getOperand(i: 0))
307 .add(MO: MI.getOperand(i: 1))
308 .addImm(Val: isEOP(I)); // Set End of program bit
309 break;
310
311 case R600::RAT_STORE_TYPED_eg:
312 BuildMI(BB&: *BB, I, MIMD: BB->findDebugLoc(MBBI: I), MCID: TII->get(Opcode: MI.getOpcode()))
313 .add(MO: MI.getOperand(i: 0))
314 .add(MO: MI.getOperand(i: 1))
315 .add(MO: MI.getOperand(i: 2))
316 .addImm(Val: isEOP(I)); // Set End of program bit
317 break;
318
319 case R600::BRANCH:
320 BuildMI(BB&: *BB, I, MIMD: BB->findDebugLoc(MBBI: I), MCID: TII->get(Opcode: R600::JUMP))
321 .add(MO: MI.getOperand(i: 0));
322 break;
323
324 case R600::BRANCH_COND_f32: {
325 MachineInstr *NewMI =
326 BuildMI(BB&: *BB, I, MIMD: BB->findDebugLoc(MBBI: I), MCID: TII->get(Opcode: R600::PRED_X),
327 DestReg: R600::PREDICATE_BIT)
328 .add(MO: MI.getOperand(i: 1))
329 .addImm(Val: R600::PRED_SETNE)
330 .addImm(Val: 0); // Flags
331 TII->addFlag(MI&: *NewMI, SrcIdx: 0, MO_FLAG_PUSH);
332 BuildMI(BB&: *BB, I, MIMD: BB->findDebugLoc(MBBI: I), MCID: TII->get(Opcode: R600::JUMP_COND))
333 .add(MO: MI.getOperand(i: 0))
334 .addReg(RegNo: R600::PREDICATE_BIT, Flags: RegState::Kill);
335 break;
336 }
337
338 case R600::BRANCH_COND_i32: {
339 MachineInstr *NewMI =
340 BuildMI(BB&: *BB, I, MIMD: BB->findDebugLoc(MBBI: I), MCID: TII->get(Opcode: R600::PRED_X),
341 DestReg: R600::PREDICATE_BIT)
342 .add(MO: MI.getOperand(i: 1))
343 .addImm(Val: R600::PRED_SETNE_INT)
344 .addImm(Val: 0); // Flags
345 TII->addFlag(MI&: *NewMI, SrcIdx: 0, MO_FLAG_PUSH);
346 BuildMI(BB&: *BB, I, MIMD: BB->findDebugLoc(MBBI: I), MCID: TII->get(Opcode: R600::JUMP_COND))
347 .add(MO: MI.getOperand(i: 0))
348 .addReg(RegNo: R600::PREDICATE_BIT, Flags: RegState::Kill);
349 break;
350 }
351
352 case R600::EG_ExportSwz:
353 case R600::R600_ExportSwz: {
354 // Instruction is left unmodified if its not the last one of its type
355 bool isLastInstructionOfItsType = true;
356 unsigned InstExportType = MI.getOperand(i: 1).getImm();
357 for (MachineBasicBlock::iterator NextExportInst = std::next(x: I),
358 EndBlock = BB->end(); NextExportInst != EndBlock;
359 NextExportInst = std::next(x: NextExportInst)) {
360 if (NextExportInst->getOpcode() == R600::EG_ExportSwz ||
361 NextExportInst->getOpcode() == R600::R600_ExportSwz) {
362 unsigned CurrentInstExportType = NextExportInst->getOperand(i: 1)
363 .getImm();
364 if (CurrentInstExportType == InstExportType) {
365 isLastInstructionOfItsType = false;
366 break;
367 }
368 }
369 }
370 bool EOP = isEOP(I);
371 if (!EOP && !isLastInstructionOfItsType)
372 return BB;
373 unsigned CfInst = (MI.getOpcode() == R600::EG_ExportSwz) ? 84 : 40;
374 BuildMI(BB&: *BB, I, MIMD: BB->findDebugLoc(MBBI: I), MCID: TII->get(Opcode: MI.getOpcode()))
375 .add(MO: MI.getOperand(i: 0))
376 .add(MO: MI.getOperand(i: 1))
377 .add(MO: MI.getOperand(i: 2))
378 .add(MO: MI.getOperand(i: 3))
379 .add(MO: MI.getOperand(i: 4))
380 .add(MO: MI.getOperand(i: 5))
381 .add(MO: MI.getOperand(i: 6))
382 .addImm(Val: CfInst)
383 .addImm(Val: EOP);
384 break;
385 }
386 case R600::RETURN: {
387 return BB;
388 }
389 }
390
391 MI.eraseFromParent();
392 return BB;
393}
394
395//===----------------------------------------------------------------------===//
396// Custom DAG Lowering Operations
397//===----------------------------------------------------------------------===//
398
399SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
400 MachineFunction &MF = DAG.getMachineFunction();
401 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
402 switch (Op.getOpcode()) {
403 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
404 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
405 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
406 case ISD::SHL_PARTS:
407 case ISD::SRA_PARTS:
408 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
409 case ISD::UADDO: return LowerUADDSUBO(Op, DAG, mainop: ISD::ADD, ovf: AMDGPUISD::CARRY);
410 case ISD::USUBO: return LowerUADDSUBO(Op, DAG, mainop: ISD::SUB, ovf: AMDGPUISD::BORROW);
411 case ISD::FCOS:
412 case ISD::FSIN: return LowerTrig(Op, DAG);
413 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
414 case ISD::STORE: return LowerSTORE(Op, DAG);
415 case ISD::LOAD: {
416 SDValue Result = LowerLOAD(Op, DAG);
417 assert((!Result.getNode() ||
418 Result.getNode()->getNumValues() == 2) &&
419 "Load should return a value and a chain");
420 return Result;
421 }
422
423 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
424 case ISD::GlobalAddress: return LowerGlobalAddress(MFI, Op, DAG);
425 case ISD::FrameIndex: return lowerFrameIndex(Op, DAG);
426 case ISD::ADDRSPACECAST:
427 return lowerADDRSPACECAST(Op, DAG);
428 case ISD::INTRINSIC_VOID: {
429 SDValue Chain = Op.getOperand(i: 0);
430 unsigned IntrinsicID = Op.getConstantOperandVal(i: 1);
431 switch (IntrinsicID) {
432 case Intrinsic::r600_store_swizzle: {
433 SDLoc DL(Op);
434 const SDValue Args[8] = {
435 Chain,
436 Op.getOperand(i: 2), // Export Value
437 Op.getOperand(i: 3), // ArrayBase
438 Op.getOperand(i: 4), // Type
439 DAG.getConstant(Val: 0, DL, VT: MVT::i32), // SWZ_X
440 DAG.getConstant(Val: 1, DL, VT: MVT::i32), // SWZ_Y
441 DAG.getConstant(Val: 2, DL, VT: MVT::i32), // SWZ_Z
442 DAG.getConstant(Val: 3, DL, VT: MVT::i32) // SWZ_W
443 };
444 return DAG.getNode(Opcode: AMDGPUISD::R600_EXPORT, DL, VT: Op.getValueType(), Ops: Args);
445 }
446
447 // default for switch(IntrinsicID)
448 default: break;
449 }
450 // break out of case ISD::INTRINSIC_VOID in switch(Op.getOpcode())
451 break;
452 }
453 case ISD::INTRINSIC_WO_CHAIN: {
454 unsigned IntrinsicID = Op.getConstantOperandVal(i: 0);
455 EVT VT = Op.getValueType();
456 SDLoc DL(Op);
457 switch (IntrinsicID) {
458 case Intrinsic::r600_tex:
459 case Intrinsic::r600_texc: {
460 unsigned TextureOp;
461 switch (IntrinsicID) {
462 case Intrinsic::r600_tex:
463 TextureOp = 0;
464 break;
465 case Intrinsic::r600_texc:
466 TextureOp = 1;
467 break;
468 default:
469 llvm_unreachable("unhandled texture operation");
470 }
471
472 SDValue TexArgs[19] = {
473 DAG.getConstant(Val: TextureOp, DL, VT: MVT::i32),
474 Op.getOperand(i: 1),
475 DAG.getConstant(Val: 0, DL, VT: MVT::i32),
476 DAG.getConstant(Val: 1, DL, VT: MVT::i32),
477 DAG.getConstant(Val: 2, DL, VT: MVT::i32),
478 DAG.getConstant(Val: 3, DL, VT: MVT::i32),
479 Op.getOperand(i: 2),
480 Op.getOperand(i: 3),
481 Op.getOperand(i: 4),
482 DAG.getConstant(Val: 0, DL, VT: MVT::i32),
483 DAG.getConstant(Val: 1, DL, VT: MVT::i32),
484 DAG.getConstant(Val: 2, DL, VT: MVT::i32),
485 DAG.getConstant(Val: 3, DL, VT: MVT::i32),
486 Op.getOperand(i: 5),
487 Op.getOperand(i: 6),
488 Op.getOperand(i: 7),
489 Op.getOperand(i: 8),
490 Op.getOperand(i: 9),
491 Op.getOperand(i: 10)
492 };
493 return DAG.getNode(Opcode: AMDGPUISD::TEXTURE_FETCH, DL, VT: MVT::v4f32, Ops: TexArgs);
494 }
495 case Intrinsic::r600_dot4: {
496 SDValue Args[8] = {
497 DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: MVT::f32, N1: Op.getOperand(i: 1),
498 N2: DAG.getConstant(Val: 0, DL, VT: MVT::i32)),
499 DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: MVT::f32, N1: Op.getOperand(i: 2),
500 N2: DAG.getConstant(Val: 0, DL, VT: MVT::i32)),
501 DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: MVT::f32, N1: Op.getOperand(i: 1),
502 N2: DAG.getConstant(Val: 1, DL, VT: MVT::i32)),
503 DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: MVT::f32, N1: Op.getOperand(i: 2),
504 N2: DAG.getConstant(Val: 1, DL, VT: MVT::i32)),
505 DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: MVT::f32, N1: Op.getOperand(i: 1),
506 N2: DAG.getConstant(Val: 2, DL, VT: MVT::i32)),
507 DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: MVT::f32, N1: Op.getOperand(i: 2),
508 N2: DAG.getConstant(Val: 2, DL, VT: MVT::i32)),
509 DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: MVT::f32, N1: Op.getOperand(i: 1),
510 N2: DAG.getConstant(Val: 3, DL, VT: MVT::i32)),
511 DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: MVT::f32, N1: Op.getOperand(i: 2),
512 N2: DAG.getConstant(Val: 3, DL, VT: MVT::i32))
513 };
514 return DAG.getNode(Opcode: AMDGPUISD::DOT4, DL, VT: MVT::f32, Ops: Args);
515 }
516
517 case Intrinsic::r600_implicitarg_ptr: {
518 MVT PtrVT = getPointerTy(DL: DAG.getDataLayout(), AS: AMDGPUAS::PARAM_I_ADDRESS);
519 uint32_t ByteOffset = getImplicitParameterOffset(MF, Param: FIRST_IMPLICIT);
520 return DAG.getConstant(Val: ByteOffset, DL, VT: PtrVT);
521 }
522 case Intrinsic::r600_read_ngroups_x:
523 return LowerImplicitParameter(DAG, VT, DL, DwordOffset: 0);
524 case Intrinsic::r600_read_ngroups_y:
525 return LowerImplicitParameter(DAG, VT, DL, DwordOffset: 1);
526 case Intrinsic::r600_read_ngroups_z:
527 return LowerImplicitParameter(DAG, VT, DL, DwordOffset: 2);
528 case Intrinsic::r600_read_global_size_x:
529 return LowerImplicitParameter(DAG, VT, DL, DwordOffset: 3);
530 case Intrinsic::r600_read_global_size_y:
531 return LowerImplicitParameter(DAG, VT, DL, DwordOffset: 4);
532 case Intrinsic::r600_read_global_size_z:
533 return LowerImplicitParameter(DAG, VT, DL, DwordOffset: 5);
534 case Intrinsic::r600_read_local_size_x:
535 return LowerImplicitParameter(DAG, VT, DL, DwordOffset: 6);
536 case Intrinsic::r600_read_local_size_y:
537 return LowerImplicitParameter(DAG, VT, DL, DwordOffset: 7);
538 case Intrinsic::r600_read_local_size_z:
539 return LowerImplicitParameter(DAG, VT, DL, DwordOffset: 8);
540
541 case Intrinsic::r600_read_tgid_x:
542 case Intrinsic::amdgcn_workgroup_id_x:
543 return CreateLiveInRegisterRaw(DAG, RC: &R600::R600_TReg32RegClass,
544 Reg: R600::T1_X, VT);
545 case Intrinsic::r600_read_tgid_y:
546 case Intrinsic::amdgcn_workgroup_id_y:
547 return CreateLiveInRegisterRaw(DAG, RC: &R600::R600_TReg32RegClass,
548 Reg: R600::T1_Y, VT);
549 case Intrinsic::r600_read_tgid_z:
550 case Intrinsic::amdgcn_workgroup_id_z:
551 return CreateLiveInRegisterRaw(DAG, RC: &R600::R600_TReg32RegClass,
552 Reg: R600::T1_Z, VT);
553 case Intrinsic::r600_read_tidig_x:
554 case Intrinsic::amdgcn_workitem_id_x:
555 return CreateLiveInRegisterRaw(DAG, RC: &R600::R600_TReg32RegClass,
556 Reg: R600::T0_X, VT);
557 case Intrinsic::r600_read_tidig_y:
558 case Intrinsic::amdgcn_workitem_id_y:
559 return CreateLiveInRegisterRaw(DAG, RC: &R600::R600_TReg32RegClass,
560 Reg: R600::T0_Y, VT);
561 case Intrinsic::r600_read_tidig_z:
562 case Intrinsic::amdgcn_workitem_id_z:
563 return CreateLiveInRegisterRaw(DAG, RC: &R600::R600_TReg32RegClass,
564 Reg: R600::T0_Z, VT);
565
566 case Intrinsic::r600_recipsqrt_ieee:
567 return DAG.getNode(Opcode: AMDGPUISD::RSQ, DL, VT, Operand: Op.getOperand(i: 1));
568
569 case Intrinsic::r600_recipsqrt_clamped:
570 return DAG.getNode(Opcode: AMDGPUISD::RSQ_CLAMP, DL, VT, Operand: Op.getOperand(i: 1));
571 default:
572 return Op;
573 }
574
575 // break out of case ISD::INTRINSIC_WO_CHAIN in switch(Op.getOpcode())
576 break;
577 }
578 } // end switch(Op.getOpcode())
579 return SDValue();
580}
581
582void R600TargetLowering::ReplaceNodeResults(SDNode *N,
583 SmallVectorImpl<SDValue> &Results,
584 SelectionDAG &DAG) const {
585 switch (N->getOpcode()) {
586 default:
587 AMDGPUTargetLowering::ReplaceNodeResults(N, Results, DAG);
588 return;
589 case ISD::FP_TO_UINT:
590 if (N->getValueType(ResNo: 0) == MVT::i1) {
591 Results.push_back(Elt: lowerFP_TO_UINT(Op: N->getOperand(Num: 0), DAG));
592 return;
593 }
594 // Since we don't care about out of bounds values we can use FP_TO_SINT for
595 // uints too. The DAGLegalizer code for uint considers some extra cases
596 // which are not necessary here.
597 [[fallthrough]];
598 case ISD::FP_TO_SINT: {
599 if (N->getValueType(ResNo: 0) == MVT::i1) {
600 Results.push_back(Elt: lowerFP_TO_SINT(Op: N->getOperand(Num: 0), DAG));
601 return;
602 }
603
604 SDValue Result;
605 if (expandFP_TO_SINT(N, Result, DAG))
606 Results.push_back(Elt: Result);
607 return;
608 }
609 case ISD::SDIVREM: {
610 SDValue Op = SDValue(N, 1);
611 SDValue RES = LowerSDIVREM(Op, DAG);
612 Results.push_back(Elt: RES);
613 Results.push_back(Elt: RES.getValue(R: 1));
614 break;
615 }
616 case ISD::UDIVREM: {
617 SDValue Op = SDValue(N, 0);
618 LowerUDIVREM64(Op, DAG, Results);
619 break;
620 }
621 }
622}
623
624SDValue R600TargetLowering::vectorToVerticalVector(SelectionDAG &DAG,
625 SDValue Vector) const {
626 SDLoc DL(Vector);
627 EVT VecVT = Vector.getValueType();
628 EVT EltVT = VecVT.getVectorElementType();
629 SmallVector<SDValue, 8> Args;
630
631 for (unsigned i = 0, e = VecVT.getVectorNumElements(); i != e; ++i) {
632 Args.push_back(Elt: DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: EltVT, N1: Vector,
633 N2: DAG.getVectorIdxConstant(Val: i, DL)));
634 }
635
636 return DAG.getNode(Opcode: AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VT: VecVT, Ops: Args);
637}
638
639SDValue R600TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
640 SelectionDAG &DAG) const {
641 SDLoc DL(Op);
642 SDValue Vector = Op.getOperand(i: 0);
643 SDValue Index = Op.getOperand(i: 1);
644
645 if (isa<ConstantSDNode>(Val: Index) ||
646 Vector.getOpcode() == AMDGPUISD::BUILD_VERTICAL_VECTOR)
647 return Op;
648
649 Vector = vectorToVerticalVector(DAG, Vector);
650 return DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: Op.getValueType(),
651 N1: Vector, N2: Index);
652}
653
654SDValue R600TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
655 SelectionDAG &DAG) const {
656 SDLoc DL(Op);
657 SDValue Vector = Op.getOperand(i: 0);
658 SDValue Value = Op.getOperand(i: 1);
659 SDValue Index = Op.getOperand(i: 2);
660
661 if (isa<ConstantSDNode>(Val: Index) ||
662 Vector.getOpcode() == AMDGPUISD::BUILD_VERTICAL_VECTOR)
663 return Op;
664
665 Vector = vectorToVerticalVector(DAG, Vector);
666 SDValue Insert = DAG.getNode(Opcode: ISD::INSERT_VECTOR_ELT, DL, VT: Op.getValueType(),
667 N1: Vector, N2: Value, N3: Index);
668 return vectorToVerticalVector(DAG, Vector: Insert);
669}
670
671SDValue R600TargetLowering::LowerGlobalAddress(AMDGPUMachineFunctionInfo *MFI,
672 SDValue Op,
673 SelectionDAG &DAG) const {
674 GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Val&: Op);
675 if (GSD->getAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS)
676 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
677
678 const DataLayout &DL = DAG.getDataLayout();
679 const GlobalValue *GV = GSD->getGlobal();
680 MVT ConstPtrVT = getPointerTy(DL, AS: AMDGPUAS::CONSTANT_ADDRESS);
681
682 SDValue GA = DAG.getTargetGlobalAddress(GV, DL: SDLoc(GSD), VT: ConstPtrVT);
683 return DAG.getNode(Opcode: AMDGPUISD::CONST_DATA_PTR, DL: SDLoc(GSD), VT: ConstPtrVT, Operand: GA);
684}
685
686SDValue R600TargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
687 // On hw >= R700, COS/SIN input must be between -1. and 1.
688 // Thus we lower them to TRIG ( FRACT ( x / 2Pi + 0.5) - 0.5)
689 EVT VT = Op.getValueType();
690 SDValue Arg = Op.getOperand(i: 0);
691 SDLoc DL(Op);
692
693 // TODO: Should this propagate fast-math-flags?
694 SDValue FractPart = DAG.getNode(Opcode: AMDGPUISD::FRACT, DL, VT,
695 Operand: DAG.getNode(Opcode: ISD::FADD, DL, VT,
696 N1: DAG.getNode(Opcode: ISD::FMUL, DL, VT, N1: Arg,
697 N2: DAG.getConstantFP(Val: 0.15915494309, DL, VT: MVT::f32)),
698 N2: DAG.getConstantFP(Val: 0.5, DL, VT: MVT::f32)));
699 unsigned TrigNode;
700 switch (Op.getOpcode()) {
701 case ISD::FCOS:
702 TrigNode = AMDGPUISD::COS_HW;
703 break;
704 case ISD::FSIN:
705 TrigNode = AMDGPUISD::SIN_HW;
706 break;
707 default:
708 llvm_unreachable("Wrong trig opcode");
709 }
710 SDValue TrigVal = DAG.getNode(Opcode: TrigNode, DL, VT,
711 Operand: DAG.getNode(Opcode: ISD::FADD, DL, VT, N1: FractPart,
712 N2: DAG.getConstantFP(Val: -0.5, DL, VT: MVT::f32)));
713 if (Gen >= AMDGPUSubtarget::R700)
714 return TrigVal;
715 // On R600 hw, COS/SIN input must be between -Pi and Pi.
716 return DAG.getNode(Opcode: ISD::FMUL, DL, VT, N1: TrigVal,
717 N2: DAG.getConstantFP(Val: numbers::pif, DL, VT: MVT::f32));
718}
719
720SDValue R600TargetLowering::LowerShiftParts(SDValue Op,
721 SelectionDAG &DAG) const {
722 SDValue Lo, Hi;
723 expandShiftParts(N: Op.getNode(), Lo, Hi, DAG);
724 return DAG.getMergeValues(Ops: {Lo, Hi}, dl: SDLoc(Op));
725}
726
727SDValue R600TargetLowering::LowerUADDSUBO(SDValue Op, SelectionDAG &DAG,
728 unsigned mainop, unsigned ovf) const {
729 SDLoc DL(Op);
730 EVT VT = Op.getValueType();
731
732 SDValue Lo = Op.getOperand(i: 0);
733 SDValue Hi = Op.getOperand(i: 1);
734
735 SDValue OVF = DAG.getNode(Opcode: ovf, DL, VT, N1: Lo, N2: Hi);
736 // Extend sign.
737 OVF = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL, VT, N1: OVF,
738 N2: DAG.getValueType(MVT::i1));
739
740 SDValue Res = DAG.getNode(Opcode: mainop, DL, VT, N1: Lo, N2: Hi);
741
742 return DAG.getNode(Opcode: ISD::MERGE_VALUES, DL, VTList: DAG.getVTList(VT1: VT, VT2: VT), N1: Res, N2: OVF);
743}
744
745SDValue R600TargetLowering::lowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const {
746 SDLoc DL(Op);
747 return DAG.getNode(
748 Opcode: ISD::SETCC,
749 DL,
750 VT: MVT::i1,
751 N1: Op, N2: DAG.getConstantFP(Val: 1.0f, DL, VT: MVT::f32),
752 N3: DAG.getCondCode(Cond: ISD::SETEQ));
753}
754
755SDValue R600TargetLowering::lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const {
756 SDLoc DL(Op);
757 return DAG.getNode(
758 Opcode: ISD::SETCC,
759 DL,
760 VT: MVT::i1,
761 N1: Op, N2: DAG.getConstantFP(Val: -1.0f, DL, VT: MVT::f32),
762 N3: DAG.getCondCode(Cond: ISD::SETEQ));
763}
764
765SDValue R600TargetLowering::LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
766 const SDLoc &DL,
767 unsigned DwordOffset) const {
768 unsigned ByteOffset = DwordOffset * 4;
769 PointerType *PtrType =
770 PointerType::get(C&: *DAG.getContext(), AddressSpace: AMDGPUAS::PARAM_I_ADDRESS);
771
772 // We shouldn't be using an offset wider than 16-bits for implicit parameters.
773 assert(isInt<16>(ByteOffset));
774
775 return DAG.getLoad(VT, dl: DL, Chain: DAG.getEntryNode(),
776 Ptr: DAG.getConstant(Val: ByteOffset, DL, VT: MVT::i32), // PTR
777 PtrInfo: MachinePointerInfo(ConstantPointerNull::get(T: PtrType)));
778}
779
780bool R600TargetLowering::isZero(SDValue Op) const {
781 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Val&: Op))
782 return Cst->isZero();
783 if (ConstantFPSDNode *CstFP = dyn_cast<ConstantFPSDNode>(Val&: Op))
784 return CstFP->isZero();
785 return false;
786}
787
788bool R600TargetLowering::isHWTrueValue(SDValue Op) const {
789 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Val&: Op)) {
790 return CFP->isOne();
791 }
792 return isAllOnesConstant(V: Op);
793}
794
795bool R600TargetLowering::isHWFalseValue(SDValue Op) const {
796 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Val&: Op)) {
797 return CFP->getValueAPF().isZero();
798 }
799 return isNullConstant(V: Op);
800}
801
802SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
803 SDLoc DL(Op);
804 EVT VT = Op.getValueType();
805
806 SDValue LHS = Op.getOperand(i: 0);
807 SDValue RHS = Op.getOperand(i: 1);
808 SDValue True = Op.getOperand(i: 2);
809 SDValue False = Op.getOperand(i: 3);
810 SDValue CC = Op.getOperand(i: 4);
811 SDValue Temp;
812
813 if (VT == MVT::f32) {
814 DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr);
815 SDValue MinMax = combineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC,
816 Flags: SDNodeFlags(), DCI);
817 if (MinMax)
818 return MinMax;
819 }
820
821 // LHS and RHS are guaranteed to be the same value type
822 EVT CompareVT = LHS.getValueType();
823
824 // Check if we can lower this to a native operation.
825
826 // Try to lower to a SET* instruction:
827 //
828 // SET* can match the following patterns:
829 //
830 // select_cc f32, f32, -1, 0, cc_supported
831 // select_cc f32, f32, 1.0f, 0.0f, cc_supported
832 // select_cc i32, i32, -1, 0, cc_supported
833 //
834
835 // Move hardware True/False values to the correct operand.
836 if (isHWTrueValue(Op: False) && isHWFalseValue(Op: True)) {
837 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(Val&: CC)->get();
838 ISD::CondCode InverseCC = ISD::getSetCCInverse(Operation: CCOpcode, Type: CompareVT);
839 if (isCondCodeLegal(CC: InverseCC, VT: CompareVT.getSimpleVT())) {
840 std::swap(a&: False, b&: True);
841 CC = DAG.getCondCode(Cond: InverseCC);
842 } else {
843 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(Operation: InverseCC);
844 if (isCondCodeLegal(CC: SwapInvCC, VT: CompareVT.getSimpleVT())) {
845 std::swap(a&: False, b&: True);
846 std::swap(a&: LHS, b&: RHS);
847 CC = DAG.getCondCode(Cond: SwapInvCC);
848 }
849 }
850 }
851
852 if (isHWTrueValue(Op: True) && isHWFalseValue(Op: False) &&
853 (CompareVT == VT || VT == MVT::i32)) {
854 // This can be matched by a SET* instruction.
855 return DAG.getNode(Opcode: ISD::SELECT_CC, DL, VT, N1: LHS, N2: RHS, N3: True, N4: False, N5: CC);
856 }
857
858 // Try to lower to a CND* instruction:
859 //
860 // CND* can match the following patterns:
861 //
862 // select_cc f32, 0.0, f32, f32, cc_supported
863 // select_cc f32, 0.0, i32, i32, cc_supported
864 // select_cc i32, 0, f32, f32, cc_supported
865 // select_cc i32, 0, i32, i32, cc_supported
866 //
867
868 // Try to move the zero value to the RHS
869 if (isZero(Op: LHS)) {
870 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(Val&: CC)->get();
871 // Try swapping the operands
872 ISD::CondCode CCSwapped = ISD::getSetCCSwappedOperands(Operation: CCOpcode);
873 if (isCondCodeLegal(CC: CCSwapped, VT: CompareVT.getSimpleVT())) {
874 std::swap(a&: LHS, b&: RHS);
875 CC = DAG.getCondCode(Cond: CCSwapped);
876 } else {
877 // Try inverting the condition and then swapping the operands
878 ISD::CondCode CCInv = ISD::getSetCCInverse(Operation: CCOpcode, Type: CompareVT);
879 CCSwapped = ISD::getSetCCSwappedOperands(Operation: CCInv);
880 if (isCondCodeLegal(CC: CCSwapped, VT: CompareVT.getSimpleVT())) {
881 std::swap(a&: True, b&: False);
882 std::swap(a&: LHS, b&: RHS);
883 CC = DAG.getCondCode(Cond: CCSwapped);
884 }
885 }
886 }
887 if (isZero(Op: RHS)) {
888 SDValue Cond = LHS;
889 SDValue Zero = RHS;
890 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(Val&: CC)->get();
891 if (CompareVT != VT) {
892 // Bitcast True / False to the correct types. This will end up being
893 // a nop, but it allows us to define only a single pattern in the
894 // .TD files for each CND* instruction rather than having to have
895 // one pattern for integer True/False and one for fp True/False
896 True = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: CompareVT, Operand: True);
897 False = DAG.getNode(Opcode: ISD::BITCAST, DL, VT: CompareVT, Operand: False);
898 }
899
900 switch (CCOpcode) {
901 case ISD::SETONE:
902 case ISD::SETUNE:
903 case ISD::SETNE:
904 CCOpcode = ISD::getSetCCInverse(Operation: CCOpcode, Type: CompareVT);
905 Temp = True;
906 True = False;
907 False = Temp;
908 break;
909 default:
910 break;
911 }
912 SDValue SelectNode = DAG.getNode(Opcode: ISD::SELECT_CC, DL, VT: CompareVT,
913 N1: Cond, N2: Zero,
914 N3: True, N4: False,
915 N5: DAG.getCondCode(Cond: CCOpcode));
916 return DAG.getNode(Opcode: ISD::BITCAST, DL, VT, Operand: SelectNode);
917 }
918
919 // If we make it this for it means we have no native instructions to handle
920 // this SELECT_CC, so we must lower it.
921 SDValue HWTrue, HWFalse;
922
923 if (CompareVT == MVT::f32) {
924 HWTrue = DAG.getConstantFP(Val: 1.0f, DL, VT: CompareVT);
925 HWFalse = DAG.getConstantFP(Val: 0.0f, DL, VT: CompareVT);
926 } else if (CompareVT == MVT::i32) {
927 HWTrue = DAG.getAllOnesConstant(DL, VT: CompareVT);
928 HWFalse = DAG.getConstant(Val: 0, DL, VT: CompareVT);
929 }
930 else {
931 llvm_unreachable("Unhandled value type in LowerSELECT_CC");
932 }
933
934 // Lower this unsupported SELECT_CC into a combination of two supported
935 // SELECT_CC operations.
936 SDValue Cond = DAG.getNode(Opcode: ISD::SELECT_CC, DL, VT: CompareVT, N1: LHS, N2: RHS, N3: HWTrue, N4: HWFalse, N5: CC);
937
938 return DAG.getNode(Opcode: ISD::SELECT_CC, DL, VT,
939 N1: Cond, N2: HWFalse,
940 N3: True, N4: False,
941 N5: DAG.getCondCode(Cond: ISD::SETNE));
942}
943
944SDValue R600TargetLowering::lowerADDRSPACECAST(SDValue Op,
945 SelectionDAG &DAG) const {
946 SDLoc SL(Op);
947 EVT VT = Op.getValueType();
948
949 const AddrSpaceCastSDNode *ASC = cast<AddrSpaceCastSDNode>(Val&: Op);
950 unsigned SrcAS = ASC->getSrcAddressSpace();
951 unsigned DestAS = ASC->getDestAddressSpace();
952
953 if (isNullConstant(V: Op.getOperand(i: 0)) && SrcAS == AMDGPUAS::FLAT_ADDRESS)
954 return DAG.getSignedConstant(Val: AMDGPU::getNullPointerValue(AS: DestAS), DL: SL, VT);
955
956 return Op;
957}
958
959void R600TargetLowering::getStackAddress(unsigned StackWidth,
960 unsigned ElemIdx,
961 unsigned &Channel,
962 unsigned &PtrIncr) const {
963 switch (StackWidth) {
964 default:
965 case 1:
966 Channel = 0;
967 if (ElemIdx > 0) {
968 PtrIncr = 1;
969 } else {
970 PtrIncr = 0;
971 }
972 break;
973 case 2:
974 Channel = ElemIdx % 2;
975 if (ElemIdx == 2) {
976 PtrIncr = 1;
977 } else {
978 PtrIncr = 0;
979 }
980 break;
981 case 4:
982 Channel = ElemIdx;
983 PtrIncr = 0;
984 break;
985 }
986}
987
988SDValue R600TargetLowering::lowerPrivateTruncStore(StoreSDNode *Store,
989 SelectionDAG &DAG) const {
990 SDLoc DL(Store);
991 //TODO: Who creates the i8 stores?
992 assert(Store->isTruncatingStore()
993 || Store->getValue().getValueType() == MVT::i8);
994 assert(Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS);
995
996 SDValue Mask;
997 if (Store->getMemoryVT() == MVT::i8) {
998 assert(Store->getAlign() >= 1);
999 Mask = DAG.getConstant(Val: 0xff, DL, VT: MVT::i32);
1000 } else if (Store->getMemoryVT() == MVT::i16) {
1001 assert(Store->getAlign() >= 2);
1002 Mask = DAG.getConstant(Val: 0xffff, DL, VT: MVT::i32);
1003 } else {
1004 llvm_unreachable("Unsupported private trunc store");
1005 }
1006
1007 SDValue OldChain = Store->getChain();
1008 bool VectorTrunc = (OldChain.getOpcode() == AMDGPUISD::DUMMY_CHAIN);
1009 // Skip dummy
1010 SDValue Chain = VectorTrunc ? OldChain->getOperand(Num: 0) : OldChain;
1011 SDValue BasePtr = Store->getBasePtr();
1012 SDValue Offset = Store->getOffset();
1013 EVT MemVT = Store->getMemoryVT();
1014
1015 SDValue LoadPtr = BasePtr;
1016 if (!Offset.isUndef()) {
1017 LoadPtr = DAG.getNode(Opcode: ISD::ADD, DL, VT: MVT::i32, N1: BasePtr, N2: Offset);
1018 }
1019
1020 // Get dword location
1021 // TODO: this should be eliminated by the future SHR ptr, 2
1022 SDValue Ptr = DAG.getNode(Opcode: ISD::AND, DL, VT: MVT::i32, N1: LoadPtr,
1023 N2: DAG.getConstant(Val: 0xfffffffc, DL, VT: MVT::i32));
1024
1025 // Load dword
1026 // TODO: can we be smarter about machine pointer info?
1027 MachinePointerInfo PtrInfo(AMDGPUAS::PRIVATE_ADDRESS);
1028 SDValue Dst = DAG.getLoad(VT: MVT::i32, dl: DL, Chain, Ptr, PtrInfo);
1029
1030 Chain = Dst.getValue(R: 1);
1031
1032 // Get offset in dword
1033 SDValue ByteIdx = DAG.getNode(Opcode: ISD::AND, DL, VT: MVT::i32, N1: LoadPtr,
1034 N2: DAG.getConstant(Val: 0x3, DL, VT: MVT::i32));
1035
1036 // Convert byte offset to bit shift
1037 SDValue ShiftAmt = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i32, N1: ByteIdx,
1038 N2: DAG.getConstant(Val: 3, DL, VT: MVT::i32));
1039
1040 // TODO: Contrary to the name of the function,
1041 // it also handles sub i32 non-truncating stores (like i1)
1042 SDValue SExtValue = DAG.getNode(Opcode: ISD::SIGN_EXTEND, DL, VT: MVT::i32,
1043 Operand: Store->getValue());
1044
1045 // Mask the value to the right type
1046 SDValue MaskedValue = DAG.getZeroExtendInReg(Op: SExtValue, DL, VT: MemVT);
1047
1048 // Shift the value in place
1049 SDValue ShiftedValue = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i32,
1050 N1: MaskedValue, N2: ShiftAmt);
1051
1052 // Shift the mask in place
1053 SDValue DstMask = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i32, N1: Mask, N2: ShiftAmt);
1054
1055 // Invert the mask. NOTE: if we had native ROL instructions we could
1056 // use inverted mask
1057 DstMask = DAG.getNOT(DL, Val: DstMask, VT: MVT::i32);
1058
1059 // Cleanup the target bits
1060 Dst = DAG.getNode(Opcode: ISD::AND, DL, VT: MVT::i32, N1: Dst, N2: DstMask);
1061
1062 // Add the new bits
1063 SDValue Value = DAG.getNode(Opcode: ISD::OR, DL, VT: MVT::i32, N1: Dst, N2: ShiftedValue);
1064
1065 // Store dword
1066 // TODO: Can we be smarter about MachinePointerInfo?
1067 SDValue NewStore = DAG.getStore(Chain, dl: DL, Val: Value, Ptr, PtrInfo);
1068
1069 // If we are part of expanded vector, make our neighbors depend on this store
1070 if (VectorTrunc) {
1071 // Make all other vector elements depend on this store
1072 Chain = DAG.getNode(Opcode: AMDGPUISD::DUMMY_CHAIN, DL, VT: MVT::Other, Operand: NewStore);
1073 DAG.ReplaceAllUsesOfValueWith(From: OldChain, To: Chain);
1074 }
1075 return NewStore;
1076}
1077
1078SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1079 StoreSDNode *StoreNode = cast<StoreSDNode>(Val&: Op);
1080 unsigned AS = StoreNode->getAddressSpace();
1081
1082 SDValue Chain = StoreNode->getChain();
1083 SDValue Ptr = StoreNode->getBasePtr();
1084 SDValue Value = StoreNode->getValue();
1085
1086 EVT VT = Value.getValueType();
1087 EVT MemVT = StoreNode->getMemoryVT();
1088 EVT PtrVT = Ptr.getValueType();
1089
1090 SDLoc DL(Op);
1091
1092 const bool TruncatingStore = StoreNode->isTruncatingStore();
1093
1094 // Neither LOCAL nor PRIVATE can do vectors at the moment
1095 if ((AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::PRIVATE_ADDRESS ||
1096 TruncatingStore) &&
1097 VT.isVector()) {
1098 if ((AS == AMDGPUAS::PRIVATE_ADDRESS) && TruncatingStore) {
1099 // Add an extra level of chain to isolate this vector
1100 SDValue NewChain = DAG.getNode(Opcode: AMDGPUISD::DUMMY_CHAIN, DL, VT: MVT::Other, Operand: Chain);
1101 SmallVector<SDValue, 4> NewOps(StoreNode->ops());
1102 NewOps[0] = NewChain;
1103 StoreNode = cast<StoreSDNode>(Val: DAG.UpdateNodeOperands(N: StoreNode, Ops: NewOps));
1104 }
1105
1106 return scalarizeVectorStore(ST: StoreNode, DAG);
1107 }
1108
1109 Align Alignment = StoreNode->getAlign();
1110 if (Alignment < MemVT.getStoreSize() &&
1111 !allowsMisalignedMemoryAccesses(VT: MemVT, AS, Alignment,
1112 Flags: StoreNode->getMemOperand()->getFlags(),
1113 IsFast: nullptr)) {
1114 return expandUnalignedStore(ST: StoreNode, DAG);
1115 }
1116
1117 SDValue DWordAddr = DAG.getNode(Opcode: ISD::SRL, DL, VT: PtrVT, N1: Ptr,
1118 N2: DAG.getConstant(Val: 2, DL, VT: PtrVT));
1119
1120 if (AS == AMDGPUAS::GLOBAL_ADDRESS) {
1121 // It is beneficial to create MSKOR here instead of combiner to avoid
1122 // artificial dependencies introduced by RMW
1123 if (TruncatingStore) {
1124 assert(VT.bitsLE(MVT::i32));
1125 SDValue MaskConstant;
1126 if (MemVT == MVT::i8) {
1127 MaskConstant = DAG.getConstant(Val: 0xFF, DL, VT: MVT::i32);
1128 } else {
1129 assert(MemVT == MVT::i16);
1130 assert(StoreNode->getAlign() >= 2);
1131 MaskConstant = DAG.getConstant(Val: 0xFFFF, DL, VT: MVT::i32);
1132 }
1133
1134 SDValue ByteIndex = DAG.getNode(Opcode: ISD::AND, DL, VT: PtrVT, N1: Ptr,
1135 N2: DAG.getConstant(Val: 0x00000003, DL, VT: PtrVT));
1136 SDValue BitShift = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: ByteIndex,
1137 N2: DAG.getConstant(Val: 3, DL, VT));
1138
1139 // Put the mask in correct place
1140 SDValue Mask = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: MaskConstant, N2: BitShift);
1141
1142 // Put the value bits in correct place
1143 SDValue TruncValue = DAG.getNode(Opcode: ISD::AND, DL, VT, N1: Value, N2: MaskConstant);
1144 SDValue ShiftedValue = DAG.getNode(Opcode: ISD::SHL, DL, VT, N1: TruncValue, N2: BitShift);
1145
1146 // XXX: If we add a 64-bit ZW register class, then we could use a 2 x i32
1147 // vector instead.
1148 SDValue Src[4] = {
1149 ShiftedValue,
1150 DAG.getConstant(Val: 0, DL, VT: MVT::i32),
1151 DAG.getConstant(Val: 0, DL, VT: MVT::i32),
1152 Mask
1153 };
1154 SDValue Input = DAG.getBuildVector(VT: MVT::v4i32, DL, Ops: Src);
1155 SDValue Args[3] = { Chain, Input, DWordAddr };
1156 return DAG.getMemIntrinsicNode(Opcode: AMDGPUISD::STORE_MSKOR, dl: DL,
1157 VTList: Op->getVTList(), Ops: Args, MemVT,
1158 MMO: StoreNode->getMemOperand());
1159 }
1160 if (Ptr->getOpcode() != AMDGPUISD::DWORDADDR && VT.bitsGE(VT: MVT::i32)) {
1161 // Convert pointer from byte address to dword address.
1162 Ptr = DAG.getNode(Opcode: AMDGPUISD::DWORDADDR, DL, VT: PtrVT, Operand: DWordAddr);
1163
1164 if (StoreNode->isIndexed()) {
1165 llvm_unreachable("Indexed stores not supported yet");
1166 } else {
1167 Chain = DAG.getStore(Chain, dl: DL, Val: Value, Ptr, MMO: StoreNode->getMemOperand());
1168 }
1169 return Chain;
1170 }
1171 }
1172
1173 // GLOBAL_ADDRESS has been handled above, LOCAL_ADDRESS allows all sizes
1174 if (AS != AMDGPUAS::PRIVATE_ADDRESS)
1175 return SDValue();
1176
1177 if (MemVT.bitsLT(VT: MVT::i32))
1178 return lowerPrivateTruncStore(Store: StoreNode, DAG);
1179
1180 // Standard i32+ store, tag it with DWORDADDR to note that the address
1181 // has been shifted
1182 if (Ptr.getOpcode() != AMDGPUISD::DWORDADDR) {
1183 Ptr = DAG.getNode(Opcode: AMDGPUISD::DWORDADDR, DL, VT: PtrVT, Operand: DWordAddr);
1184 return DAG.getStore(Chain, dl: DL, Val: Value, Ptr, MMO: StoreNode->getMemOperand());
1185 }
1186
1187 // Tagged i32+ stores will be matched by patterns
1188 return SDValue();
1189}
1190
1191// return (512 + (kc_bank << 12)
1192static int
1193ConstantAddressBlock(unsigned AddressSpace) {
1194 switch (AddressSpace) {
1195 case AMDGPUAS::CONSTANT_BUFFER_0:
1196 return 512;
1197 case AMDGPUAS::CONSTANT_BUFFER_1:
1198 return 512 + 4096;
1199 case AMDGPUAS::CONSTANT_BUFFER_2:
1200 return 512 + 4096 * 2;
1201 case AMDGPUAS::CONSTANT_BUFFER_3:
1202 return 512 + 4096 * 3;
1203 case AMDGPUAS::CONSTANT_BUFFER_4:
1204 return 512 + 4096 * 4;
1205 case AMDGPUAS::CONSTANT_BUFFER_5:
1206 return 512 + 4096 * 5;
1207 case AMDGPUAS::CONSTANT_BUFFER_6:
1208 return 512 + 4096 * 6;
1209 case AMDGPUAS::CONSTANT_BUFFER_7:
1210 return 512 + 4096 * 7;
1211 case AMDGPUAS::CONSTANT_BUFFER_8:
1212 return 512 + 4096 * 8;
1213 case AMDGPUAS::CONSTANT_BUFFER_9:
1214 return 512 + 4096 * 9;
1215 case AMDGPUAS::CONSTANT_BUFFER_10:
1216 return 512 + 4096 * 10;
1217 case AMDGPUAS::CONSTANT_BUFFER_11:
1218 return 512 + 4096 * 11;
1219 case AMDGPUAS::CONSTANT_BUFFER_12:
1220 return 512 + 4096 * 12;
1221 case AMDGPUAS::CONSTANT_BUFFER_13:
1222 return 512 + 4096 * 13;
1223 case AMDGPUAS::CONSTANT_BUFFER_14:
1224 return 512 + 4096 * 14;
1225 case AMDGPUAS::CONSTANT_BUFFER_15:
1226 return 512 + 4096 * 15;
1227 default:
1228 return -1;
1229 }
1230}
1231
1232SDValue R600TargetLowering::lowerPrivateExtLoad(SDValue Op,
1233 SelectionDAG &DAG) const {
1234 SDLoc DL(Op);
1235 LoadSDNode *Load = cast<LoadSDNode>(Val&: Op);
1236 ISD::LoadExtType ExtType = Load->getExtensionType();
1237 EVT MemVT = Load->getMemoryVT();
1238 assert(Load->getAlign() >= MemVT.getStoreSize());
1239
1240 SDValue BasePtr = Load->getBasePtr();
1241 SDValue Chain = Load->getChain();
1242 SDValue Offset = Load->getOffset();
1243
1244 SDValue LoadPtr = BasePtr;
1245 if (!Offset.isUndef()) {
1246 LoadPtr = DAG.getNode(Opcode: ISD::ADD, DL, VT: MVT::i32, N1: BasePtr, N2: Offset);
1247 }
1248
1249 // Get dword location
1250 // NOTE: this should be eliminated by the future SHR ptr, 2
1251 SDValue Ptr = DAG.getNode(Opcode: ISD::AND, DL, VT: MVT::i32, N1: LoadPtr,
1252 N2: DAG.getConstant(Val: 0xfffffffc, DL, VT: MVT::i32));
1253
1254 // Load dword
1255 // TODO: can we be smarter about machine pointer info?
1256 MachinePointerInfo PtrInfo(AMDGPUAS::PRIVATE_ADDRESS);
1257 SDValue Read = DAG.getLoad(VT: MVT::i32, dl: DL, Chain, Ptr, PtrInfo);
1258
1259 // Get offset within the register.
1260 SDValue ByteIdx = DAG.getNode(Opcode: ISD::AND, DL, VT: MVT::i32,
1261 N1: LoadPtr, N2: DAG.getConstant(Val: 0x3, DL, VT: MVT::i32));
1262
1263 // Bit offset of target byte (byteIdx * 8).
1264 SDValue ShiftAmt = DAG.getNode(Opcode: ISD::SHL, DL, VT: MVT::i32, N1: ByteIdx,
1265 N2: DAG.getConstant(Val: 3, DL, VT: MVT::i32));
1266
1267 // Shift to the right.
1268 SDValue Ret = DAG.getNode(Opcode: ISD::SRL, DL, VT: MVT::i32, N1: Read, N2: ShiftAmt);
1269
1270 // Eliminate the upper bits by setting them to ...
1271 EVT MemEltVT = MemVT.getScalarType();
1272
1273 if (ExtType == ISD::SEXTLOAD) { // ... ones.
1274 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1275 Ret = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL, VT: MVT::i32, N1: Ret, N2: MemEltVTNode);
1276 } else { // ... or zeros.
1277 Ret = DAG.getZeroExtendInReg(Op: Ret, DL, VT: MemEltVT);
1278 }
1279
1280 SDValue Ops[] = {
1281 Ret,
1282 Read.getValue(R: 1) // This should be our output chain
1283 };
1284
1285 return DAG.getMergeValues(Ops, dl: DL);
1286}
1287
1288SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1289 LoadSDNode *LoadNode = cast<LoadSDNode>(Val&: Op);
1290 unsigned AS = LoadNode->getAddressSpace();
1291 EVT MemVT = LoadNode->getMemoryVT();
1292 ISD::LoadExtType ExtType = LoadNode->getExtensionType();
1293
1294 if (AS == AMDGPUAS::PRIVATE_ADDRESS &&
1295 ExtType != ISD::NON_EXTLOAD && MemVT.bitsLT(VT: MVT::i32)) {
1296 return lowerPrivateExtLoad(Op, DAG);
1297 }
1298
1299 SDLoc DL(Op);
1300 EVT VT = Op.getValueType();
1301 SDValue Chain = LoadNode->getChain();
1302 SDValue Ptr = LoadNode->getBasePtr();
1303
1304 if ((LoadNode->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1305 LoadNode->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1306 VT.isVector()) {
1307 SDValue Ops[2];
1308 std::tie(args&: Ops[0], args&: Ops[1]) = scalarizeVectorLoad(LD: LoadNode, DAG);
1309 return DAG.getMergeValues(Ops, dl: DL);
1310 }
1311
1312 // This is still used for explicit load from addrspace(8)
1313 int ConstantBlock = ConstantAddressBlock(AddressSpace: LoadNode->getAddressSpace());
1314 if (ConstantBlock > -1 &&
1315 ((LoadNode->getExtensionType() == ISD::NON_EXTLOAD) ||
1316 (LoadNode->getExtensionType() == ISD::ZEXTLOAD))) {
1317 SDValue Result;
1318 if (isa<Constant>(Val: LoadNode->getMemOperand()->getValue()) ||
1319 isa<ConstantSDNode>(Val: Ptr)) {
1320 return constBufferLoad(LoadNode, Block: LoadNode->getAddressSpace(), DAG);
1321 }
1322 // TODO: Does this even work?
1323 // non-constant ptr can't be folded, keeps it as a v4f32 load
1324 Result = DAG.getNode(Opcode: AMDGPUISD::CONST_ADDRESS, DL, VT: MVT::v4i32,
1325 N1: DAG.getNode(Opcode: ISD::SRL, DL, VT: MVT::i32, N1: Ptr,
1326 N2: DAG.getConstant(Val: 4, DL, VT: MVT::i32)),
1327 N2: DAG.getConstant(Val: LoadNode->getAddressSpace() -
1328 AMDGPUAS::CONSTANT_BUFFER_0,
1329 DL, VT: MVT::i32));
1330
1331 if (!VT.isVector()) {
1332 Result = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: MVT::i32, N1: Result,
1333 N2: DAG.getConstant(Val: 0, DL, VT: MVT::i32));
1334 }
1335
1336 SDValue MergedValues[2] = {
1337 Result,
1338 Chain
1339 };
1340 return DAG.getMergeValues(Ops: MergedValues, dl: DL);
1341 }
1342
1343 // For most operations returning SDValue() will result in the node being
1344 // expanded by the DAG Legalizer. This is not the case for ISD::LOAD, so we
1345 // need to manually expand loads that may be legal in some address spaces and
1346 // illegal in others. SEXT loads from CONSTANT_BUFFER_0 are supported for
1347 // compute shaders, since the data is sign extended when it is uploaded to the
1348 // buffer. However SEXT loads from other address spaces are not supported, so
1349 // we need to expand them here.
1350 if (LoadNode->getExtensionType() == ISD::SEXTLOAD) {
1351 assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8));
1352 SDValue NewLoad = DAG.getExtLoad(
1353 ExtType: ISD::EXTLOAD, dl: DL, VT, Chain, Ptr, PtrInfo: LoadNode->getPointerInfo(), MemVT,
1354 Alignment: LoadNode->getAlign(), MMOFlags: LoadNode->getMemOperand()->getFlags());
1355 SDValue Res = DAG.getNode(Opcode: ISD::SIGN_EXTEND_INREG, DL, VT, N1: NewLoad,
1356 N2: DAG.getValueType(MemVT));
1357
1358 SDValue MergedValues[2] = { Res, Chain };
1359 return DAG.getMergeValues(Ops: MergedValues, dl: DL);
1360 }
1361
1362 if (LoadNode->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS) {
1363 return SDValue();
1364 }
1365
1366 // DWORDADDR ISD marks already shifted address
1367 if (Ptr.getOpcode() != AMDGPUISD::DWORDADDR) {
1368 assert(VT == MVT::i32);
1369 Ptr = DAG.getNode(Opcode: ISD::SRL, DL, VT: MVT::i32, N1: Ptr, N2: DAG.getConstant(Val: 2, DL, VT: MVT::i32));
1370 Ptr = DAG.getNode(Opcode: AMDGPUISD::DWORDADDR, DL, VT: MVT::i32, Operand: Ptr);
1371 return DAG.getLoad(VT: MVT::i32, dl: DL, Chain, Ptr, MMO: LoadNode->getMemOperand());
1372 }
1373 return SDValue();
1374}
1375
1376SDValue R600TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1377 SDValue Chain = Op.getOperand(i: 0);
1378 SDValue Cond = Op.getOperand(i: 1);
1379 SDValue Jump = Op.getOperand(i: 2);
1380
1381 return DAG.getNode(Opcode: AMDGPUISD::BRANCH_COND, DL: SDLoc(Op), VT: Op.getValueType(),
1382 N1: Chain, N2: Jump, N3: Cond);
1383}
1384
1385SDValue R600TargetLowering::lowerFrameIndex(SDValue Op,
1386 SelectionDAG &DAG) const {
1387 MachineFunction &MF = DAG.getMachineFunction();
1388 const R600FrameLowering *TFL = Subtarget->getFrameLowering();
1389
1390 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Val&: Op);
1391
1392 unsigned FrameIndex = FIN->getIndex();
1393 Register IgnoredFrameReg;
1394 StackOffset Offset =
1395 TFL->getFrameIndexReference(MF, FI: FrameIndex, FrameReg&: IgnoredFrameReg);
1396 return DAG.getConstant(Val: Offset.getFixed() * 4 * TFL->getStackWidth(MF),
1397 DL: SDLoc(Op), VT: Op.getValueType());
1398}
1399
1400CCAssignFn *R600TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1401 bool IsVarArg) const {
1402 switch (CC) {
1403 case CallingConv::AMDGPU_KERNEL:
1404 case CallingConv::SPIR_KERNEL:
1405 case CallingConv::C:
1406 case CallingConv::Fast:
1407 case CallingConv::Cold:
1408 llvm_unreachable("kernels should not be handled here");
1409 case CallingConv::AMDGPU_VS:
1410 case CallingConv::AMDGPU_GS:
1411 case CallingConv::AMDGPU_PS:
1412 case CallingConv::AMDGPU_CS:
1413 case CallingConv::AMDGPU_HS:
1414 case CallingConv::AMDGPU_ES:
1415 case CallingConv::AMDGPU_LS:
1416 return CC_R600;
1417 default:
1418 reportFatalUsageError(reason: "unsupported calling convention");
1419 }
1420}
1421
1422/// XXX Only kernel functions are supported, so we can assume for now that
1423/// every function is a kernel function, but in the future we should use
1424/// separate calling conventions for kernel and non-kernel functions.
1425SDValue R600TargetLowering::LowerFormalArguments(
1426 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1427 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
1428 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1429 SmallVector<CCValAssign, 16> ArgLocs;
1430 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1431 *DAG.getContext());
1432 MachineFunction &MF = DAG.getMachineFunction();
1433
1434 if (AMDGPU::isShader(CC: CallConv)) {
1435 CCInfo.AnalyzeFormalArguments(Ins, Fn: CCAssignFnForCall(CC: CallConv, IsVarArg: isVarArg));
1436 } else {
1437 analyzeFormalArgumentsCompute(State&: CCInfo, Ins);
1438 }
1439
1440 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
1441 CCValAssign &VA = ArgLocs[i];
1442 const ISD::InputArg &In = Ins[i];
1443 EVT VT = In.VT;
1444 EVT MemVT = VA.getLocVT();
1445 if (!VT.isVector() && MemVT.isVector()) {
1446 // Get load source type if scalarized.
1447 MemVT = MemVT.getVectorElementType();
1448 }
1449
1450 if (VT.isInteger() && !MemVT.isInteger())
1451 MemVT = MemVT.changeTypeToInteger();
1452
1453 if (AMDGPU::isShader(CC: CallConv)) {
1454 Register Reg = MF.addLiveIn(PReg: VA.getLocReg(), RC: &R600::R600_Reg128RegClass);
1455 SDValue Register = DAG.getCopyFromReg(Chain, dl: DL, Reg, VT);
1456 InVals.push_back(Elt: Register);
1457 continue;
1458 }
1459
1460 // i64 isn't a legal type, so the register type used ends up as i32, which
1461 // isn't expected here. It attempts to create this sextload, but it ends up
1462 // being invalid. Somehow this seems to work with i64 arguments, but breaks
1463 // for <1 x i64>.
1464
1465 // The first 36 bytes of the input buffer contains information about
1466 // thread group and global sizes.
1467 ISD::LoadExtType Ext = ISD::NON_EXTLOAD;
1468 if (MemVT.getScalarSizeInBits() != VT.getScalarSizeInBits()) {
1469 if (VT.isFloatingPoint()) {
1470 Ext = ISD::EXTLOAD;
1471 } else {
1472 // FIXME: This should really check the extload type, but the handling of
1473 // extload vector parameters seems to be broken.
1474
1475 // Ext = In.Flags.isSExt() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
1476 Ext = ISD::SEXTLOAD;
1477 }
1478 }
1479
1480 // Compute the offset from the value.
1481 // XXX - I think PartOffset should give you this, but it seems to give the
1482 // size of the register which isn't useful.
1483
1484 unsigned PartOffset = VA.getLocMemOffset();
1485 Align Alignment = commonAlignment(A: Align(VT.getStoreSize()), Offset: PartOffset);
1486
1487 MachinePointerInfo PtrInfo(AMDGPUAS::PARAM_I_ADDRESS);
1488 SDValue Arg =
1489 DAG.getLoad(AM: ISD::UNINDEXED, ExtType: Ext, VT, dl: DL, Chain,
1490 Ptr: DAG.getConstant(Val: PartOffset, DL, VT: MVT::i32),
1491 Offset: DAG.getPOISON(VT: MVT::i32), PtrInfo, MemVT, Alignment,
1492 MMOFlags: MachineMemOperand::MONonTemporal |
1493 MachineMemOperand::MODereferenceable |
1494 MachineMemOperand::MOInvariant);
1495
1496 InVals.push_back(Elt: Arg);
1497 }
1498 return Chain;
1499}
1500
1501EVT R600TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1502 EVT VT) const {
1503 if (!VT.isVector())
1504 return MVT::i32;
1505 return VT.changeVectorElementTypeToInteger();
1506}
1507
1508bool R600TargetLowering::canMergeStoresTo(unsigned AS, EVT MemVT,
1509 const MachineFunction &MF) const {
1510 // Local and Private addresses do not handle vectors. Limit to i32
1511 if ((AS == AMDGPUAS::LOCAL_ADDRESS || AS == AMDGPUAS::PRIVATE_ADDRESS)) {
1512 return (MemVT.getSizeInBits() <= 32);
1513 }
1514 return true;
1515}
1516
1517bool R600TargetLowering::allowsMisalignedMemoryAccesses(
1518 EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags,
1519 unsigned *IsFast) const {
1520 if (IsFast)
1521 *IsFast = 0;
1522
1523 if (!VT.isSimple() || VT == MVT::Other)
1524 return false;
1525
1526 if (VT.bitsLT(VT: MVT::i32))
1527 return false;
1528
1529 // TODO: This is a rough estimate.
1530 if (IsFast)
1531 *IsFast = 1;
1532
1533 return VT.bitsGT(VT: MVT::i32) && Alignment >= Align(4);
1534}
1535
1536static SDValue CompactSwizzlableVector(
1537 SelectionDAG &DAG, SDValue VectorEntry,
1538 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1539 assert(RemapSwizzle.empty());
1540
1541 SDLoc DL(VectorEntry);
1542 EVT EltTy = VectorEntry.getValueType().getVectorElementType();
1543
1544 SDValue NewBldVec[4];
1545 for (unsigned i = 0; i < 4; i++)
1546 NewBldVec[i] = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: EltTy, N1: VectorEntry,
1547 N2: DAG.getIntPtrConstant(Val: i, DL));
1548
1549 for (unsigned i = 0; i < 4; i++) {
1550 if (NewBldVec[i].isUndef())
1551 // We mask write here to teach later passes that the ith element of this
1552 // vector is undef. Thus we can use it to reduce 128 bits reg usage,
1553 // break false dependencies and additionally make assembly easier to read.
1554 RemapSwizzle[i] = 7; // SEL_MASK_WRITE
1555 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val&: NewBldVec[i])) {
1556 if (C->isZero()) {
1557 RemapSwizzle[i] = 4; // SEL_0
1558 NewBldVec[i] = DAG.getUNDEF(VT: MVT::f32);
1559 } else if (C->isOne()) {
1560 RemapSwizzle[i] = 5; // SEL_1
1561 NewBldVec[i] = DAG.getUNDEF(VT: MVT::f32);
1562 }
1563 }
1564
1565 if (NewBldVec[i].isUndef())
1566 continue;
1567
1568 for (unsigned j = 0; j < i; j++) {
1569 if (NewBldVec[i] == NewBldVec[j]) {
1570 NewBldVec[i] = DAG.getUNDEF(VT: NewBldVec[i].getValueType());
1571 RemapSwizzle[i] = j;
1572 break;
1573 }
1574 }
1575 }
1576
1577 return DAG.getBuildVector(VT: VectorEntry.getValueType(), DL: SDLoc(VectorEntry),
1578 Ops: NewBldVec);
1579}
1580
1581static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry,
1582 DenseMap<unsigned, unsigned> &RemapSwizzle) {
1583 assert(RemapSwizzle.empty());
1584
1585 SDLoc DL(VectorEntry);
1586 EVT EltTy = VectorEntry.getValueType().getVectorElementType();
1587
1588 SDValue NewBldVec[4];
1589 bool isUnmovable[4] = {false, false, false, false};
1590 for (unsigned i = 0; i < 4; i++)
1591 NewBldVec[i] = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: EltTy, N1: VectorEntry,
1592 N2: DAG.getIntPtrConstant(Val: i, DL));
1593
1594 for (unsigned i = 0; i < 4; i++) {
1595 RemapSwizzle[i] = i;
1596 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1597 unsigned Idx = NewBldVec[i].getConstantOperandVal(i: 1);
1598 if (i == Idx)
1599 isUnmovable[Idx] = true;
1600 }
1601 }
1602
1603 for (unsigned i = 0; i < 4; i++) {
1604 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
1605 unsigned Idx = NewBldVec[i].getConstantOperandVal(i: 1);
1606 if (isUnmovable[Idx])
1607 continue;
1608 // Swap i and Idx
1609 std::swap(a&: NewBldVec[Idx], b&: NewBldVec[i]);
1610 std::swap(a&: RemapSwizzle[i], b&: RemapSwizzle[Idx]);
1611 break;
1612 }
1613 }
1614
1615 return DAG.getBuildVector(VT: VectorEntry.getValueType(), DL: SDLoc(VectorEntry),
1616 Ops: NewBldVec);
1617}
1618
1619SDValue R600TargetLowering::OptimizeSwizzle(SDValue BuildVector, SDValue Swz[],
1620 SelectionDAG &DAG,
1621 const SDLoc &DL) const {
1622 // Old -> New swizzle values
1623 DenseMap<unsigned, unsigned> SwizzleRemap;
1624
1625 BuildVector = CompactSwizzlableVector(DAG, VectorEntry: BuildVector, RemapSwizzle&: SwizzleRemap);
1626 for (unsigned i = 0; i < 4; i++) {
1627 unsigned Idx = Swz[i]->getAsZExtVal();
1628 auto It = SwizzleRemap.find(Val: Idx);
1629 if (It != SwizzleRemap.end())
1630 Swz[i] = DAG.getConstant(Val: It->second, DL, VT: MVT::i32);
1631 }
1632
1633 SwizzleRemap.clear();
1634 BuildVector = ReorganizeVector(DAG, VectorEntry: BuildVector, RemapSwizzle&: SwizzleRemap);
1635 for (unsigned i = 0; i < 4; i++) {
1636 unsigned Idx = Swz[i]->getAsZExtVal();
1637 auto It = SwizzleRemap.find(Val: Idx);
1638 if (It != SwizzleRemap.end())
1639 Swz[i] = DAG.getConstant(Val: It->second, DL, VT: MVT::i32);
1640 }
1641
1642 return BuildVector;
1643}
1644
1645SDValue R600TargetLowering::constBufferLoad(LoadSDNode *LoadNode, int Block,
1646 SelectionDAG &DAG) const {
1647 SDLoc DL(LoadNode);
1648 EVT VT = LoadNode->getValueType(ResNo: 0);
1649 SDValue Chain = LoadNode->getChain();
1650 SDValue Ptr = LoadNode->getBasePtr();
1651 assert (isa<ConstantSDNode>(Ptr));
1652
1653 //TODO: Support smaller loads
1654 if (LoadNode->getMemoryVT().getScalarType() != MVT::i32 || !ISD::isNON_EXTLoad(N: LoadNode))
1655 return SDValue();
1656
1657 if (LoadNode->getAlign() < Align(4))
1658 return SDValue();
1659
1660 int ConstantBlock = ConstantAddressBlock(AddressSpace: Block);
1661
1662 SDValue Slots[4];
1663 for (unsigned i = 0; i < 4; i++) {
1664 // We want Const position encoded with the following formula :
1665 // (((512 + (kc_bank << 12) + const_index) << 2) + chan)
1666 // const_index is Ptr computed by llvm using an alignment of 16.
1667 // Thus we add (((512 + (kc_bank << 12)) + chan ) * 4 here and
1668 // then div by 4 at the ISel step
1669 SDValue NewPtr = DAG.getNode(Opcode: ISD::ADD, DL, VT: Ptr.getValueType(), N1: Ptr,
1670 N2: DAG.getConstant(Val: 4 * i + ConstantBlock * 16, DL, VT: MVT::i32));
1671 Slots[i] = DAG.getNode(Opcode: AMDGPUISD::CONST_ADDRESS, DL, VT: MVT::i32, Operand: NewPtr);
1672 }
1673 EVT NewVT = MVT::v4i32;
1674 unsigned NumElements = 4;
1675 if (VT.isVector()) {
1676 NewVT = VT;
1677 NumElements = VT.getVectorNumElements();
1678 }
1679 SDValue Result = DAG.getBuildVector(VT: NewVT, DL, Ops: ArrayRef(Slots, NumElements));
1680 if (!VT.isVector()) {
1681 Result = DAG.getNode(Opcode: ISD::EXTRACT_VECTOR_ELT, DL, VT: MVT::i32, N1: Result,
1682 N2: DAG.getConstant(Val: 0, DL, VT: MVT::i32));
1683 }
1684 SDValue MergedValues[2] = {
1685 Result,
1686 Chain
1687 };
1688 return DAG.getMergeValues(Ops: MergedValues, dl: DL);
1689}
1690
1691//===----------------------------------------------------------------------===//
1692// Custom DAG Optimizations
1693//===----------------------------------------------------------------------===//
1694
1695SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
1696 DAGCombinerInfo &DCI) const {
1697 SelectionDAG &DAG = DCI.DAG;
1698 SDLoc DL(N);
1699
1700 switch (N->getOpcode()) {
1701 // (f32 fp_round (f64 uint_to_fp a)) -> (f32 uint_to_fp a)
1702 case ISD::FP_ROUND: {
1703 SDValue Arg = N->getOperand(Num: 0);
1704 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) {
1705 return DAG.getNode(Opcode: ISD::UINT_TO_FP, DL, VT: N->getValueType(ResNo: 0),
1706 Operand: Arg.getOperand(i: 0));
1707 }
1708 break;
1709 }
1710
1711 // (i32 fp_to_sint (fneg (select_cc f32, f32, 1.0, 0.0 cc))) ->
1712 // (i32 select_cc f32, f32, -1, 0 cc)
1713 //
1714 // Mesa's GLSL frontend generates the above pattern a lot and we can lower
1715 // this to one of the SET*_DX10 instructions.
1716 case ISD::FP_TO_SINT: {
1717 SDValue FNeg = N->getOperand(Num: 0);
1718 if (FNeg.getOpcode() != ISD::FNEG) {
1719 return SDValue();
1720 }
1721 SDValue SelectCC = FNeg.getOperand(i: 0);
1722 if (SelectCC.getOpcode() != ISD::SELECT_CC ||
1723 SelectCC.getOperand(i: 0).getValueType() != MVT::f32 || // LHS
1724 SelectCC.getOperand(i: 2).getValueType() != MVT::f32 || // True
1725 !isHWTrueValue(Op: SelectCC.getOperand(i: 2)) ||
1726 !isHWFalseValue(Op: SelectCC.getOperand(i: 3))) {
1727 return SDValue();
1728 }
1729
1730 return DAG.getNode(Opcode: ISD::SELECT_CC, DL, VT: N->getValueType(ResNo: 0),
1731 N1: SelectCC.getOperand(i: 0), // LHS
1732 N2: SelectCC.getOperand(i: 1), // RHS
1733 N3: DAG.getAllOnesConstant(DL, VT: MVT::i32), // True
1734 N4: DAG.getConstant(Val: 0, DL, VT: MVT::i32), // False
1735 N5: SelectCC.getOperand(i: 4)); // CC
1736 }
1737
1738 // insert_vector_elt (build_vector elt0, ... , eltN), NewEltIdx, idx
1739 // => build_vector elt0, ... , NewEltIdx, ... , eltN
1740 case ISD::INSERT_VECTOR_ELT: {
1741 SDValue InVec = N->getOperand(Num: 0);
1742 SDValue InVal = N->getOperand(Num: 1);
1743 SDValue EltNo = N->getOperand(Num: 2);
1744
1745 // If the inserted element is an UNDEF, just use the input vector.
1746 if (InVal.isUndef())
1747 return InVec;
1748
1749 EVT VT = InVec.getValueType();
1750
1751 // If we can't generate a legal BUILD_VECTOR, exit
1752 if (!isOperationLegal(Op: ISD::BUILD_VECTOR, VT))
1753 return SDValue();
1754
1755 // Check that we know which element is being inserted
1756 if (!isa<ConstantSDNode>(Val: EltNo))
1757 return SDValue();
1758 unsigned Elt = EltNo->getAsZExtVal();
1759
1760 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
1761 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
1762 // vector elements.
1763 SmallVector<SDValue, 8> Ops;
1764 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
1765 Ops.append(in_start: InVec.getNode()->op_begin(),
1766 in_end: InVec.getNode()->op_end());
1767 } else if (InVec.isUndef()) {
1768 unsigned NElts = VT.getVectorNumElements();
1769 Ops.append(NumInputs: NElts, Elt: DAG.getUNDEF(VT: InVal.getValueType()));
1770 } else {
1771 return SDValue();
1772 }
1773
1774 // Insert the element
1775 if (Elt < Ops.size()) {
1776 // All the operands of BUILD_VECTOR must have the same type;
1777 // we enforce that here.
1778 EVT OpVT = Ops[0].getValueType();
1779 if (InVal.getValueType() != OpVT)
1780 InVal = OpVT.bitsGT(VT: InVal.getValueType()) ?
1781 DAG.getNode(Opcode: ISD::ANY_EXTEND, DL, VT: OpVT, Operand: InVal) :
1782 DAG.getNode(Opcode: ISD::TRUNCATE, DL, VT: OpVT, Operand: InVal);
1783 Ops[Elt] = InVal;
1784 }
1785
1786 // Return the new vector
1787 return DAG.getBuildVector(VT, DL, Ops);
1788 }
1789
1790 // Extract_vec (Build_vector) generated by custom lowering
1791 // also needs to be customly combined
1792 case ISD::EXTRACT_VECTOR_ELT: {
1793 SDValue Arg = N->getOperand(Num: 0);
1794 if (Arg.getOpcode() == ISD::BUILD_VECTOR) {
1795 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Val: N->getOperand(Num: 1))) {
1796 unsigned Element = Const->getZExtValue();
1797 return Arg->getOperand(Num: Element);
1798 }
1799 }
1800 if (Arg.getOpcode() == ISD::BITCAST &&
1801 Arg.getOperand(i: 0).getOpcode() == ISD::BUILD_VECTOR &&
1802 (Arg.getOperand(i: 0).getValueType().getVectorNumElements() ==
1803 Arg.getValueType().getVectorNumElements())) {
1804 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Val: N->getOperand(Num: 1))) {
1805 unsigned Element = Const->getZExtValue();
1806 return DAG.getNode(Opcode: ISD::BITCAST, DL, VTList: N->getVTList(),
1807 N: Arg->getOperand(Num: 0).getOperand(i: Element));
1808 }
1809 }
1810 break;
1811 }
1812
1813 case ISD::SELECT_CC: {
1814 // Try common optimizations
1815 if (SDValue Ret = AMDGPUTargetLowering::PerformDAGCombine(N, DCI))
1816 return Ret;
1817
1818 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, seteq ->
1819 // selectcc x, y, a, b, inv(cc)
1820 //
1821 // fold selectcc (selectcc x, y, a, b, cc), b, a, b, setne ->
1822 // selectcc x, y, a, b, cc
1823 SDValue LHS = N->getOperand(Num: 0);
1824 if (LHS.getOpcode() != ISD::SELECT_CC) {
1825 return SDValue();
1826 }
1827
1828 SDValue RHS = N->getOperand(Num: 1);
1829 SDValue True = N->getOperand(Num: 2);
1830 SDValue False = N->getOperand(Num: 3);
1831 ISD::CondCode NCC = cast<CondCodeSDNode>(Val: N->getOperand(Num: 4))->get();
1832
1833 if (LHS.getOperand(i: 2).getNode() != True.getNode() ||
1834 LHS.getOperand(i: 3).getNode() != False.getNode() ||
1835 RHS.getNode() != False.getNode()) {
1836 return SDValue();
1837 }
1838
1839 switch (NCC) {
1840 default: return SDValue();
1841 case ISD::SETNE: return LHS;
1842 case ISD::SETEQ: {
1843 ISD::CondCode LHSCC = cast<CondCodeSDNode>(Val: LHS.getOperand(i: 4))->get();
1844 LHSCC = ISD::getSetCCInverse(Operation: LHSCC, Type: LHS.getOperand(i: 0).getValueType());
1845 if (DCI.isBeforeLegalizeOps() ||
1846 isCondCodeLegal(CC: LHSCC, VT: LHS.getOperand(i: 0).getSimpleValueType()))
1847 return DAG.getSelectCC(DL,
1848 LHS: LHS.getOperand(i: 0),
1849 RHS: LHS.getOperand(i: 1),
1850 True: LHS.getOperand(i: 2),
1851 False: LHS.getOperand(i: 3),
1852 Cond: LHSCC);
1853 break;
1854 }
1855 }
1856 return SDValue();
1857 }
1858
1859 case AMDGPUISD::R600_EXPORT: {
1860 SDValue Arg = N->getOperand(Num: 1);
1861 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
1862 break;
1863
1864 SDValue NewArgs[8] = {
1865 N->getOperand(Num: 0), // Chain
1866 SDValue(),
1867 N->getOperand(Num: 2), // ArrayBase
1868 N->getOperand(Num: 3), // Type
1869 N->getOperand(Num: 4), // SWZ_X
1870 N->getOperand(Num: 5), // SWZ_Y
1871 N->getOperand(Num: 6), // SWZ_Z
1872 N->getOperand(Num: 7) // SWZ_W
1873 };
1874 NewArgs[1] = OptimizeSwizzle(BuildVector: N->getOperand(Num: 1), Swz: &NewArgs[4], DAG, DL);
1875 return DAG.getNode(Opcode: AMDGPUISD::R600_EXPORT, DL, VTList: N->getVTList(), Ops: NewArgs);
1876 }
1877 case AMDGPUISD::TEXTURE_FETCH: {
1878 SDValue Arg = N->getOperand(Num: 1);
1879 if (Arg.getOpcode() != ISD::BUILD_VECTOR)
1880 break;
1881
1882 SDValue NewArgs[19] = {
1883 N->getOperand(Num: 0),
1884 N->getOperand(Num: 1),
1885 N->getOperand(Num: 2),
1886 N->getOperand(Num: 3),
1887 N->getOperand(Num: 4),
1888 N->getOperand(Num: 5),
1889 N->getOperand(Num: 6),
1890 N->getOperand(Num: 7),
1891 N->getOperand(Num: 8),
1892 N->getOperand(Num: 9),
1893 N->getOperand(Num: 10),
1894 N->getOperand(Num: 11),
1895 N->getOperand(Num: 12),
1896 N->getOperand(Num: 13),
1897 N->getOperand(Num: 14),
1898 N->getOperand(Num: 15),
1899 N->getOperand(Num: 16),
1900 N->getOperand(Num: 17),
1901 N->getOperand(Num: 18),
1902 };
1903 NewArgs[1] = OptimizeSwizzle(BuildVector: N->getOperand(Num: 1), Swz: &NewArgs[2], DAG, DL);
1904 return DAG.getNode(Opcode: AMDGPUISD::TEXTURE_FETCH, DL, VTList: N->getVTList(), Ops: NewArgs);
1905 }
1906
1907 case ISD::LOAD: {
1908 LoadSDNode *LoadNode = cast<LoadSDNode>(Val: N);
1909 SDValue Ptr = LoadNode->getBasePtr();
1910 if (LoadNode->getAddressSpace() == AMDGPUAS::PARAM_I_ADDRESS &&
1911 isa<ConstantSDNode>(Val: Ptr))
1912 return constBufferLoad(LoadNode, Block: AMDGPUAS::CONSTANT_BUFFER_0, DAG);
1913 break;
1914 }
1915
1916 default: break;
1917 }
1918
1919 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
1920}
1921
1922bool R600TargetLowering::FoldOperand(SDNode *ParentNode, unsigned SrcIdx,
1923 SDValue &Src, SDValue &Neg, SDValue &Abs,
1924 SDValue &Sel, SDValue &Imm,
1925 SelectionDAG &DAG) const {
1926 const R600InstrInfo *TII = Subtarget->getInstrInfo();
1927 if (!Src.isMachineOpcode())
1928 return false;
1929
1930 switch (Src.getMachineOpcode()) {
1931 case R600::FNEG_R600:
1932 if (!Neg.getNode())
1933 return false;
1934 Src = Src.getOperand(i: 0);
1935 Neg = DAG.getTargetConstant(Val: 1, DL: SDLoc(ParentNode), VT: MVT::i32);
1936 return true;
1937 case R600::FABS_R600:
1938 if (!Abs.getNode())
1939 return false;
1940 Src = Src.getOperand(i: 0);
1941 Abs = DAG.getTargetConstant(Val: 1, DL: SDLoc(ParentNode), VT: MVT::i32);
1942 return true;
1943 case R600::CONST_COPY: {
1944 unsigned Opcode = ParentNode->getMachineOpcode();
1945 bool HasDst = TII->getOperandIdx(Opcode, Op: R600::OpName::dst) > -1;
1946
1947 if (!Sel.getNode())
1948 return false;
1949
1950 SDValue CstOffset = Src.getOperand(i: 0);
1951 if (ParentNode->getValueType(ResNo: 0).isVector())
1952 return false;
1953
1954 // Gather constants values
1955 int SrcIndices[] = {
1956 TII->getOperandIdx(Opcode, Op: R600::OpName::src0),
1957 TII->getOperandIdx(Opcode, Op: R600::OpName::src1),
1958 TII->getOperandIdx(Opcode, Op: R600::OpName::src2),
1959 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_X),
1960 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_Y),
1961 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_Z),
1962 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_W),
1963 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_X),
1964 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_Y),
1965 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_Z),
1966 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_W)
1967 };
1968 std::vector<unsigned> Consts;
1969 for (int OtherSrcIdx : SrcIndices) {
1970 int OtherSelIdx = TII->getSelIdx(Opcode, SrcIdx: OtherSrcIdx);
1971 if (OtherSrcIdx < 0 || OtherSelIdx < 0)
1972 continue;
1973 if (HasDst) {
1974 OtherSrcIdx--;
1975 OtherSelIdx--;
1976 }
1977 if (RegisterSDNode *Reg =
1978 dyn_cast<RegisterSDNode>(Val: ParentNode->getOperand(Num: OtherSrcIdx))) {
1979 if (Reg->getReg() == R600::ALU_CONST) {
1980 Consts.push_back(x: ParentNode->getConstantOperandVal(Num: OtherSelIdx));
1981 }
1982 }
1983 }
1984
1985 ConstantSDNode *Cst = cast<ConstantSDNode>(Val&: CstOffset);
1986 Consts.push_back(x: Cst->getZExtValue());
1987 if (!TII->fitsConstReadLimitations(Consts)) {
1988 return false;
1989 }
1990
1991 Sel = CstOffset;
1992 Src = DAG.getRegister(Reg: R600::ALU_CONST, VT: MVT::f32);
1993 return true;
1994 }
1995 case R600::MOV_IMM_GLOBAL_ADDR:
1996 // Check if the Imm slot is used. Taken from below.
1997 if (Imm->getAsZExtVal())
1998 return false;
1999 Imm = Src.getOperand(i: 0);
2000 Src = DAG.getRegister(Reg: R600::ALU_LITERAL_X, VT: MVT::i32);
2001 return true;
2002 case R600::MOV_IMM_I32:
2003 case R600::MOV_IMM_F32: {
2004 unsigned ImmReg = R600::ALU_LITERAL_X;
2005 uint64_t ImmValue = 0;
2006
2007 if (Src.getMachineOpcode() == R600::MOV_IMM_F32) {
2008 ConstantFPSDNode *FPC = cast<ConstantFPSDNode>(Val: Src.getOperand(i: 0));
2009 float FloatValue = FPC->getValueAPF().convertToFloat();
2010 if (FloatValue == 0.0) {
2011 ImmReg = R600::ZERO;
2012 } else if (FloatValue == 0.5) {
2013 ImmReg = R600::HALF;
2014 } else if (FloatValue == 1.0) {
2015 ImmReg = R600::ONE;
2016 } else {
2017 ImmValue = FPC->getValueAPF().bitcastToAPInt().getZExtValue();
2018 }
2019 } else {
2020 uint64_t Value = Src.getConstantOperandVal(i: 0);
2021 if (Value == 0) {
2022 ImmReg = R600::ZERO;
2023 } else if (Value == 1) {
2024 ImmReg = R600::ONE_INT;
2025 } else {
2026 ImmValue = Value;
2027 }
2028 }
2029
2030 // Check that we aren't already using an immediate.
2031 // XXX: It's possible for an instruction to have more than one
2032 // immediate operand, but this is not supported yet.
2033 if (ImmReg == R600::ALU_LITERAL_X) {
2034 if (!Imm.getNode())
2035 return false;
2036 ConstantSDNode *C = cast<ConstantSDNode>(Val&: Imm);
2037 if (C->getZExtValue())
2038 return false;
2039 Imm = DAG.getTargetConstant(Val: ImmValue, DL: SDLoc(ParentNode), VT: MVT::i32);
2040 }
2041 Src = DAG.getRegister(Reg: ImmReg, VT: MVT::i32);
2042 return true;
2043 }
2044 default:
2045 return false;
2046 }
2047}
2048
2049/// Fold the instructions after selecting them
2050SDNode *R600TargetLowering::PostISelFolding(MachineSDNode *Node,
2051 SelectionDAG &DAG) const {
2052 const R600InstrInfo *TII = Subtarget->getInstrInfo();
2053 if (!Node->isMachineOpcode())
2054 return Node;
2055
2056 unsigned Opcode = Node->getMachineOpcode();
2057 SDValue FakeOp;
2058
2059 std::vector<SDValue> Ops(Node->op_begin(), Node->op_end());
2060
2061 if (Opcode == R600::DOT_4) {
2062 int OperandIdx[] = {
2063 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_X),
2064 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_Y),
2065 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_Z),
2066 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_W),
2067 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_X),
2068 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_Y),
2069 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_Z),
2070 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_W)
2071 };
2072 int NegIdx[] = {
2073 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_neg_X),
2074 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_neg_Y),
2075 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_neg_Z),
2076 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_neg_W),
2077 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_neg_X),
2078 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_neg_Y),
2079 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_neg_Z),
2080 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_neg_W)
2081 };
2082 int AbsIdx[] = {
2083 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_abs_X),
2084 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_abs_Y),
2085 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_abs_Z),
2086 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_abs_W),
2087 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_abs_X),
2088 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_abs_Y),
2089 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_abs_Z),
2090 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_abs_W)
2091 };
2092 for (unsigned i = 0; i < 8; i++) {
2093 if (OperandIdx[i] < 0)
2094 return Node;
2095 SDValue &Src = Ops[OperandIdx[i] - 1];
2096 SDValue &Neg = Ops[NegIdx[i] - 1];
2097 SDValue &Abs = Ops[AbsIdx[i] - 1];
2098 bool HasDst = TII->getOperandIdx(Opcode, Op: R600::OpName::dst) > -1;
2099 int SelIdx = TII->getSelIdx(Opcode, SrcIdx: OperandIdx[i]);
2100 if (HasDst)
2101 SelIdx--;
2102 SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
2103 if (FoldOperand(ParentNode: Node, SrcIdx: i, Src, Neg, Abs, Sel, Imm&: FakeOp, DAG))
2104 return DAG.getMachineNode(Opcode, dl: SDLoc(Node), VTs: Node->getVTList(), Ops);
2105 }
2106 } else if (Opcode == R600::REG_SEQUENCE) {
2107 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2) {
2108 SDValue &Src = Ops[i];
2109 if (FoldOperand(ParentNode: Node, SrcIdx: i, Src, Neg&: FakeOp, Abs&: FakeOp, Sel&: FakeOp, Imm&: FakeOp, DAG))
2110 return DAG.getMachineNode(Opcode, dl: SDLoc(Node), VTs: Node->getVTList(), Ops);
2111 }
2112 } else {
2113 if (!TII->hasInstrModifiers(Opcode))
2114 return Node;
2115 int OperandIdx[] = {
2116 TII->getOperandIdx(Opcode, Op: R600::OpName::src0),
2117 TII->getOperandIdx(Opcode, Op: R600::OpName::src1),
2118 TII->getOperandIdx(Opcode, Op: R600::OpName::src2)
2119 };
2120 int NegIdx[] = {
2121 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_neg),
2122 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_neg),
2123 TII->getOperandIdx(Opcode, Op: R600::OpName::src2_neg)
2124 };
2125 int AbsIdx[] = {
2126 TII->getOperandIdx(Opcode, Op: R600::OpName::src0_abs),
2127 TII->getOperandIdx(Opcode, Op: R600::OpName::src1_abs),
2128 -1
2129 };
2130 for (unsigned i = 0; i < 3; i++) {
2131 if (OperandIdx[i] < 0)
2132 return Node;
2133 SDValue &Src = Ops[OperandIdx[i] - 1];
2134 SDValue &Neg = Ops[NegIdx[i] - 1];
2135 SDValue FakeAbs;
2136 SDValue &Abs = (AbsIdx[i] > -1) ? Ops[AbsIdx[i] - 1] : FakeAbs;
2137 bool HasDst = TII->getOperandIdx(Opcode, Op: R600::OpName::dst) > -1;
2138 int SelIdx = TII->getSelIdx(Opcode, SrcIdx: OperandIdx[i]);
2139 int ImmIdx = TII->getOperandIdx(Opcode, Op: R600::OpName::literal);
2140 if (HasDst) {
2141 SelIdx--;
2142 ImmIdx--;
2143 }
2144 SDValue &Sel = (SelIdx > -1) ? Ops[SelIdx] : FakeOp;
2145 SDValue &Imm = Ops[ImmIdx];
2146 if (FoldOperand(ParentNode: Node, SrcIdx: i, Src, Neg, Abs, Sel, Imm, DAG))
2147 return DAG.getMachineNode(Opcode, dl: SDLoc(Node), VTs: Node->getVTList(), Ops);
2148 }
2149 }
2150
2151 return Node;
2152}
2153
2154TargetLowering::AtomicExpansionKind
2155R600TargetLowering::shouldExpandAtomicRMWInIR(const AtomicRMWInst *RMW) const {
2156 switch (RMW->getOperation()) {
2157 case AtomicRMWInst::Nand:
2158 case AtomicRMWInst::FAdd:
2159 case AtomicRMWInst::FSub:
2160 case AtomicRMWInst::FMax:
2161 case AtomicRMWInst::FMin:
2162 case AtomicRMWInst::USubCond:
2163 case AtomicRMWInst::USubSat:
2164 return AtomicExpansionKind::CmpXChg;
2165 case AtomicRMWInst::UIncWrap:
2166 case AtomicRMWInst::UDecWrap:
2167 // FIXME: Cayman at least appears to have instructions for this, but the
2168 // instruction definitions appear to be missing.
2169 return AtomicExpansionKind::CmpXChg;
2170 case AtomicRMWInst::Xchg: {
2171 const DataLayout &DL = RMW->getFunction()->getDataLayout();
2172 unsigned ValSize = DL.getTypeSizeInBits(Ty: RMW->getType());
2173 if (ValSize == 32 || ValSize == 64)
2174 return AtomicExpansionKind::None;
2175 return AtomicExpansionKind::CmpXChg;
2176 }
2177 default:
2178 if (auto *IntTy = dyn_cast<IntegerType>(Val: RMW->getType())) {
2179 unsigned Size = IntTy->getBitWidth();
2180 if (Size == 32 || Size == 64)
2181 return AtomicExpansionKind::None;
2182 }
2183
2184 return AtomicExpansionKind::CmpXChg;
2185 }
2186
2187 llvm_unreachable("covered atomicrmw op switch");
2188}
2189