1//===-- Mips16ISelLowering.h - Mips16 DAG Lowering Interface ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// Subclass of MipsTargetLowering specialized for mips16.
10//
11//===----------------------------------------------------------------------===//
12#include "Mips16ISelLowering.h"
13#include "MCTargetDesc/MipsBaseInfo.h"
14#include "Mips16HardFloatInfo.h"
15#include "MipsMachineFunction.h"
16#include "MipsRegisterInfo.h"
17#include "MipsTargetMachine.h"
18#include "llvm/CodeGen/MachineInstrBuilder.h"
19#include "llvm/CodeGen/TargetInstrInfo.h"
20#include "llvm/Support/CommandLine.h"
21
22using namespace llvm;
23
24#define DEBUG_TYPE "mips-lower"
25
26static cl::opt<bool> DontExpandCondPseudos16(
27 "mips16-dont-expand-cond-pseudo",
28 cl::init(Val: false),
29 cl::desc("Don't expand conditional move related "
30 "pseudos for Mips 16"),
31 cl::Hidden);
32
33namespace {
34struct Mips16IntrinsicHelperType{
35 const char* Name;
36 const char* Helper;
37
38 bool operator<(const Mips16IntrinsicHelperType &RHS) const {
39 return std::strcmp(s1: Name, s2: RHS.Name) < 0;
40 }
41 bool operator==(const Mips16IntrinsicHelperType &RHS) const {
42 return std::strcmp(s1: Name, s2: RHS.Name) == 0;
43 }
44};
45} // namespace
46
47static const Mips16IntrinsicHelperType Mips16IntrinsicHelper[] = {
48 {.Name: "__fixunsdfsi", .Helper: "__mips16_call_stub_2" },
49 {.Name: "ceil", .Helper: "__mips16_call_stub_df_2"},
50 {.Name: "ceilf", .Helper: "__mips16_call_stub_sf_1"},
51 {.Name: "copysign", .Helper: "__mips16_call_stub_df_10"},
52 {.Name: "copysignf", .Helper: "__mips16_call_stub_sf_5"},
53 {.Name: "cos", .Helper: "__mips16_call_stub_df_2"},
54 {.Name: "cosf", .Helper: "__mips16_call_stub_sf_1"},
55 {.Name: "exp2", .Helper: "__mips16_call_stub_df_2"},
56 {.Name: "exp2f", .Helper: "__mips16_call_stub_sf_1"},
57 {.Name: "floor", .Helper: "__mips16_call_stub_df_2"},
58 {.Name: "floorf", .Helper: "__mips16_call_stub_sf_1"},
59 {.Name: "log2", .Helper: "__mips16_call_stub_df_2"},
60 {.Name: "log2f", .Helper: "__mips16_call_stub_sf_1"},
61 {.Name: "nearbyint", .Helper: "__mips16_call_stub_df_2"},
62 {.Name: "nearbyintf", .Helper: "__mips16_call_stub_sf_1"},
63 {.Name: "rint", .Helper: "__mips16_call_stub_df_2"},
64 {.Name: "rintf", .Helper: "__mips16_call_stub_sf_1"},
65 {.Name: "sin", .Helper: "__mips16_call_stub_df_2"},
66 {.Name: "sinf", .Helper: "__mips16_call_stub_sf_1"},
67 {.Name: "sqrt", .Helper: "__mips16_call_stub_df_2"},
68 {.Name: "sqrtf", .Helper: "__mips16_call_stub_sf_1"},
69 {.Name: "trunc", .Helper: "__mips16_call_stub_df_2"},
70 {.Name: "truncf", .Helper: "__mips16_call_stub_sf_1"},
71};
72
73Mips16TargetLowering::Mips16TargetLowering(const MipsTargetMachine &TM,
74 const MipsSubtarget &STI)
75 : MipsTargetLowering(TM, STI) {
76
77 // Set up the register classes
78 addRegisterClass(VT: MVT::i32, RC: &Mips::CPU16RegsRegClass);
79
80 setOperationAction(Op: ISD::ATOMIC_FENCE, VT: MVT::Other, Action: LibCall);
81 setOperationAction(Op: ISD::ATOMIC_CMP_SWAP, VT: MVT::i32, Action: LibCall);
82 setOperationAction(Op: ISD::ATOMIC_SWAP, VT: MVT::i32, Action: LibCall);
83 setOperationAction(Op: ISD::ATOMIC_LOAD_ADD, VT: MVT::i32, Action: LibCall);
84 setOperationAction(Op: ISD::ATOMIC_LOAD_SUB, VT: MVT::i32, Action: LibCall);
85 setOperationAction(Op: ISD::ATOMIC_LOAD_AND, VT: MVT::i32, Action: LibCall);
86 setOperationAction(Op: ISD::ATOMIC_LOAD_OR, VT: MVT::i32, Action: LibCall);
87 setOperationAction(Op: ISD::ATOMIC_LOAD_XOR, VT: MVT::i32, Action: LibCall);
88 setOperationAction(Op: ISD::ATOMIC_LOAD_NAND, VT: MVT::i32, Action: LibCall);
89 setOperationAction(Op: ISD::ATOMIC_LOAD_MIN, VT: MVT::i32, Action: LibCall);
90 setOperationAction(Op: ISD::ATOMIC_LOAD_MAX, VT: MVT::i32, Action: LibCall);
91 setOperationAction(Op: ISD::ATOMIC_LOAD_UMIN, VT: MVT::i32, Action: LibCall);
92 setOperationAction(Op: ISD::ATOMIC_LOAD_UMAX, VT: MVT::i32, Action: LibCall);
93
94 setOperationAction(Op: ISD::ROTR, VT: MVT::i32, Action: Expand);
95 setOperationAction(Op: ISD::ROTR, VT: MVT::i64, Action: Expand);
96 setOperationAction(Op: ISD::BSWAP, VT: MVT::i32, Action: Expand);
97 setOperationAction(Op: ISD::BSWAP, VT: MVT::i64, Action: Expand);
98
99 computeRegisterProperties(TRI: STI.getRegisterInfo());
100}
101
102const MipsTargetLowering *
103llvm::createMips16TargetLowering(const MipsTargetMachine &TM,
104 const MipsSubtarget &STI) {
105 return new Mips16TargetLowering(TM, STI);
106}
107
108bool Mips16TargetLowering::allowsMisalignedMemoryAccesses(
109 EVT VT, unsigned, Align, MachineMemOperand::Flags, unsigned *Fast) const {
110 return false;
111}
112
113MachineBasicBlock *
114Mips16TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
115 MachineBasicBlock *BB) const {
116 switch (MI.getOpcode()) {
117 default:
118 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, MBB: BB);
119 case Mips::SelBeqZ:
120 return emitSel16(Opc: Mips::BeqzRxImm16, MI, BB);
121 case Mips::SelBneZ:
122 return emitSel16(Opc: Mips::BnezRxImm16, MI, BB);
123 case Mips::SelTBteqZCmpi:
124 return emitSeliT16(Opc1: Mips::Bteqz16, Opc2: Mips::CmpiRxImmX16, MI, BB);
125 case Mips::SelTBteqZSlti:
126 return emitSeliT16(Opc1: Mips::Bteqz16, Opc2: Mips::SltiRxImmX16, MI, BB);
127 case Mips::SelTBteqZSltiu:
128 return emitSeliT16(Opc1: Mips::Bteqz16, Opc2: Mips::SltiuRxImmX16, MI, BB);
129 case Mips::SelTBtneZCmpi:
130 return emitSeliT16(Opc1: Mips::Btnez16, Opc2: Mips::CmpiRxImmX16, MI, BB);
131 case Mips::SelTBtneZSlti:
132 return emitSeliT16(Opc1: Mips::Btnez16, Opc2: Mips::SltiRxImmX16, MI, BB);
133 case Mips::SelTBtneZSltiu:
134 return emitSeliT16(Opc1: Mips::Btnez16, Opc2: Mips::SltiuRxImmX16, MI, BB);
135 case Mips::SelTBteqZCmp:
136 return emitSelT16(Opc1: Mips::Bteqz16, Opc2: Mips::CmpRxRy16, MI, BB);
137 case Mips::SelTBteqZSlt:
138 return emitSelT16(Opc1: Mips::Bteqz16, Opc2: Mips::SltRxRy16, MI, BB);
139 case Mips::SelTBteqZSltu:
140 return emitSelT16(Opc1: Mips::Bteqz16, Opc2: Mips::SltuRxRy16, MI, BB);
141 case Mips::SelTBtneZCmp:
142 return emitSelT16(Opc1: Mips::Btnez16, Opc2: Mips::CmpRxRy16, MI, BB);
143 case Mips::SelTBtneZSlt:
144 return emitSelT16(Opc1: Mips::Btnez16, Opc2: Mips::SltRxRy16, MI, BB);
145 case Mips::SelTBtneZSltu:
146 return emitSelT16(Opc1: Mips::Btnez16, Opc2: Mips::SltuRxRy16, MI, BB);
147 case Mips::BteqzT8CmpX16:
148 return emitFEXT_T8I816_ins(BtOpc: Mips::Bteqz16, CmpOpc: Mips::CmpRxRy16, MI, BB);
149 case Mips::BteqzT8SltX16:
150 return emitFEXT_T8I816_ins(BtOpc: Mips::Bteqz16, CmpOpc: Mips::SltRxRy16, MI, BB);
151 case Mips::BteqzT8SltuX16:
152 // TBD: figure out a way to get this or remove the instruction
153 // altogether.
154 return emitFEXT_T8I816_ins(BtOpc: Mips::Bteqz16, CmpOpc: Mips::SltuRxRy16, MI, BB);
155 case Mips::BtnezT8CmpX16:
156 return emitFEXT_T8I816_ins(BtOpc: Mips::Btnez16, CmpOpc: Mips::CmpRxRy16, MI, BB);
157 case Mips::BtnezT8SltX16:
158 return emitFEXT_T8I816_ins(BtOpc: Mips::Btnez16, CmpOpc: Mips::SltRxRy16, MI, BB);
159 case Mips::BtnezT8SltuX16:
160 // TBD: figure out a way to get this or remove the instruction
161 // altogether.
162 return emitFEXT_T8I816_ins(BtOpc: Mips::Btnez16, CmpOpc: Mips::SltuRxRy16, MI, BB);
163 case Mips::BteqzT8CmpiX16: return emitFEXT_T8I8I16_ins(
164 BtOpc: Mips::Bteqz16, CmpiOpc: Mips::CmpiRxImm16, CmpiXOpc: Mips::CmpiRxImmX16, ImmSigned: false, MI, BB);
165 case Mips::BteqzT8SltiX16: return emitFEXT_T8I8I16_ins(
166 BtOpc: Mips::Bteqz16, CmpiOpc: Mips::SltiRxImm16, CmpiXOpc: Mips::SltiRxImmX16, ImmSigned: true, MI, BB);
167 case Mips::BteqzT8SltiuX16: return emitFEXT_T8I8I16_ins(
168 BtOpc: Mips::Bteqz16, CmpiOpc: Mips::SltiuRxImm16, CmpiXOpc: Mips::SltiuRxImmX16, ImmSigned: false, MI, BB);
169 case Mips::BtnezT8CmpiX16: return emitFEXT_T8I8I16_ins(
170 BtOpc: Mips::Btnez16, CmpiOpc: Mips::CmpiRxImm16, CmpiXOpc: Mips::CmpiRxImmX16, ImmSigned: false, MI, BB);
171 case Mips::BtnezT8SltiX16: return emitFEXT_T8I8I16_ins(
172 BtOpc: Mips::Btnez16, CmpiOpc: Mips::SltiRxImm16, CmpiXOpc: Mips::SltiRxImmX16, ImmSigned: true, MI, BB);
173 case Mips::BtnezT8SltiuX16: return emitFEXT_T8I8I16_ins(
174 BtOpc: Mips::Btnez16, CmpiOpc: Mips::SltiuRxImm16, CmpiXOpc: Mips::SltiuRxImmX16, ImmSigned: false, MI, BB);
175 break;
176 case Mips::SltCCRxRy16:
177 return emitFEXT_CCRX16_ins(SltOpc: Mips::SltRxRy16, MI, BB);
178 break;
179 case Mips::SltiCCRxImmX16:
180 return emitFEXT_CCRXI16_ins
181 (SltiOpc: Mips::SltiRxImm16, SltiXOpc: Mips::SltiRxImmX16, MI, BB);
182 case Mips::SltiuCCRxImmX16:
183 return emitFEXT_CCRXI16_ins
184 (SltiOpc: Mips::SltiuRxImm16, SltiXOpc: Mips::SltiuRxImmX16, MI, BB);
185 case Mips::SltuCCRxRy16:
186 return emitFEXT_CCRX16_ins
187 (SltOpc: Mips::SltuRxRy16, MI, BB);
188 }
189}
190
191bool Mips16TargetLowering::isEligibleForTailCallOptimization(
192 const CCState &CCInfo, unsigned NextStackOffset,
193 const MipsFunctionInfo &FI) const {
194 // No tail call optimization for mips16.
195 return false;
196}
197
198//
199// The Mips16 hard float is a crazy quilt inherited from gcc. I have a much
200// cleaner way to do all of this but it will have to wait until the traditional
201// gcc mechanism is completed.
202//
203// For Pic, in order for Mips16 code to call Mips32 code which according the abi
204// have either arguments or returned values placed in floating point registers,
205// we use a set of helper functions. (This includes functions which return type
206// complex which on Mips are returned in a pair of floating point registers).
207//
208// This is an encoding that we inherited from gcc.
209// In Mips traditional O32, N32 ABI, floating point numbers are passed in
210// floating point argument registers 1,2 only when the first and optionally
211// the second arguments are float (sf) or double (df).
212// For Mips16 we are only concerned with the situations where floating point
213// arguments are being passed in floating point registers by the ABI, because
214// Mips16 mode code cannot execute floating point instructions to load those
215// values and hence helper functions are needed.
216// The possibilities are (), (sf), (sf, sf), (sf, df), (df), (df, sf), (df, df)
217// the helper function suffixs for these are:
218// 0, 1, 5, 9, 2, 6, 10
219// this suffix can then be calculated as follows:
220// for a given argument Arg:
221// Arg1x, Arg2x = 1 : Arg is sf
222// 2 : Arg is df
223// 0: Arg is neither sf or df
224// So this stub is the string for number Arg1x + Arg2x*4.
225// However not all numbers between 0 and 10 are possible, we check anyway and
226// assert if the impossible exists.
227//
228
229unsigned int Mips16TargetLowering::getMips16HelperFunctionStubNumber
230 (ArgListTy &Args) const {
231 unsigned int resultNum = 0;
232 if (Args.size() >= 1) {
233 Type *t = Args[0].Ty;
234 if (t->isFloatTy()) {
235 resultNum = 1;
236 }
237 else if (t->isDoubleTy()) {
238 resultNum = 2;
239 }
240 }
241 if (resultNum) {
242 if (Args.size() >=2) {
243 Type *t = Args[1].Ty;
244 if (t->isFloatTy()) {
245 resultNum += 4;
246 }
247 else if (t->isDoubleTy()) {
248 resultNum += 8;
249 }
250 }
251 }
252 return resultNum;
253}
254
255//
256// Prefixes are attached to stub numbers depending on the return type.
257// return type: float sf_
258// double df_
259// single complex sc_
260// double complext dc_
261// others NO PREFIX
262//
263//
264// The full name of a helper function is__mips16_call_stub +
265// return type dependent prefix + stub number
266//
267// FIXME: This is something that probably should be in a different source file
268// and perhaps done differently but my main purpose is to not waste runtime
269// on something that we can enumerate in the source. Another possibility is
270// to have a python script to generate these mapping tables. This will do
271// for now. There are a whole series of helper function mapping arrays, one
272// for each return type class as outlined above. There there are 11 possible
273// entries. Ones with 0 are ones which should never be selected.
274//
275// All the arrays are similar except for ones which return neither
276// sf, df, sc, dc, in which we only care about ones which have sf or df as a
277// first parameter.
278//
279#define P_ "__mips16_call_stub_"
280#define MAX_STUB_NUMBER 10
281#define T1 P "1", P "2", 0, 0, P "5", P "6", 0, 0, P "9", P "10"
282#define T P "0" , T1
283#define P P_
284static char const * vMips16Helper[MAX_STUB_NUMBER+1] =
285 {nullptr, T1 };
286#undef P
287#define P P_ "sf_"
288static char const * sfMips16Helper[MAX_STUB_NUMBER+1] =
289 { T };
290#undef P
291#define P P_ "df_"
292static char const * dfMips16Helper[MAX_STUB_NUMBER+1] =
293 { T };
294#undef P
295#define P P_ "sc_"
296static char const * scMips16Helper[MAX_STUB_NUMBER+1] =
297 { T };
298#undef P
299#define P P_ "dc_"
300static char const * dcMips16Helper[MAX_STUB_NUMBER+1] =
301 { T };
302#undef P
303#undef P_
304
305
306const char* Mips16TargetLowering::
307 getMips16HelperFunction
308 (Type* RetTy, ArgListTy &Args, bool &needHelper) const {
309 const unsigned int stubNum = getMips16HelperFunctionStubNumber(Args);
310#ifndef NDEBUG
311 const unsigned int maxStubNum = 10;
312 assert(stubNum <= maxStubNum);
313 const bool validStubNum[maxStubNum+1] =
314 {true, true, true, false, false, true, true, false, false, true, true};
315 assert(validStubNum[stubNum]);
316#endif
317 const char *result;
318 if (RetTy->isFloatTy()) {
319 result = sfMips16Helper[stubNum];
320 }
321 else if (RetTy ->isDoubleTy()) {
322 result = dfMips16Helper[stubNum];
323 } else if (StructType *SRetTy = dyn_cast<StructType>(Val: RetTy)) {
324 // check if it's complex
325 if (SRetTy->getNumElements() == 2) {
326 if ((SRetTy->getElementType(N: 0)->isFloatTy()) &&
327 (SRetTy->getElementType(N: 1)->isFloatTy())) {
328 result = scMips16Helper[stubNum];
329 } else if ((SRetTy->getElementType(N: 0)->isDoubleTy()) &&
330 (SRetTy->getElementType(N: 1)->isDoubleTy())) {
331 result = dcMips16Helper[stubNum];
332 } else {
333 llvm_unreachable("Uncovered condition");
334 }
335 } else {
336 llvm_unreachable("Uncovered condition");
337 }
338 } else {
339 if (stubNum == 0) {
340 needHelper = false;
341 return "";
342 }
343 result = vMips16Helper[stubNum];
344 }
345 needHelper = true;
346 return result;
347}
348
349static bool isMips16HardFloatLibcall(StringRef Name) {
350 // FIXME: Use getSupportedLibcallImpl instead of blindly parsing the name.
351 iota_range<RTLIB::LibcallImpl> ParsedLibcalls =
352 RTLIB::RuntimeLibcallsInfo::lookupLibcallImplName(Name);
353 return !ParsedLibcalls.empty() &&
354 binary_search(Range: MipsSubtarget::HardFloatLibCalls,
355 Value: *ParsedLibcalls.begin());
356}
357
358void Mips16TargetLowering::getOpndList(
359 SmallVectorImpl<SDValue> &Ops,
360 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, bool IsPICCall,
361 bool GlobalOrExternal, bool LocalLinkage, bool IsCallReloc,
362 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const {
363 SelectionDAG &DAG = CLI.DAG;
364 MachineFunction &MF = DAG.getMachineFunction();
365 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
366 const char* Mips16HelperFunction = nullptr;
367 bool NeedMips16Helper = false;
368
369 if (Subtarget.inMips16HardFloat()) {
370 //
371 // currently we don't have symbols tagged with the mips16 or mips32
372 // qualifier so we will assume that we don't know what kind it is.
373 // and generate the helper
374 //
375 bool LookupHelper = true;
376 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Val&: CLI.Callee)) {
377 if (isMips16HardFloatLibcall(Name: S->getSymbol()))
378 LookupHelper = false;
379 else {
380 const char *Symbol = S->getSymbol();
381 Mips16IntrinsicHelperType IntrinsicFind = { .Name: Symbol, .Helper: "" };
382 const Mips16HardFloatInfo::FuncSignature *Signature =
383 Mips16HardFloatInfo::findFuncSignature(name: Symbol);
384 if (!IsPICCall && Signature &&
385 FuncInfo->StubsNeeded.try_emplace(k: Symbol, args&: Signature).second) {
386 //
387 // S2 is normally saved if the stub is for a function which
388 // returns a float or double value and is not otherwise. This is
389 // because more work is required after the function the stub
390 // is calling completes, and so the stub cannot directly return
391 // and the stub has no stack space to store the return address so
392 // S2 is used for that purpose.
393 // In order to take advantage of not saving S2, we need to also
394 // optimize the call in the stub and this requires some further
395 // functionality in MipsAsmPrinter which we don't have yet.
396 // So for now we always save S2. The optimization will be done
397 // in a follow-on patch.
398 //
399 if (true || (Signature->RetSig != Mips16HardFloatInfo::NoFPRet))
400 FuncInfo->setSaveS2();
401 }
402 // one more look at list of intrinsics
403 const Mips16IntrinsicHelperType *Helper =
404 llvm::lower_bound(Range: Mips16IntrinsicHelper, Value&: IntrinsicFind);
405 if (Helper != std::end(arr: Mips16IntrinsicHelper) &&
406 *Helper == IntrinsicFind) {
407 Mips16HelperFunction = Helper->Helper;
408 NeedMips16Helper = true;
409 LookupHelper = false;
410 }
411
412 }
413 } else if (GlobalAddressSDNode *G =
414 dyn_cast<GlobalAddressSDNode>(Val&: CLI.Callee)) {
415
416 if (isMips16HardFloatLibcall(Name: G->getGlobal()->getName()))
417 LookupHelper = false;
418 }
419 if (LookupHelper)
420 Mips16HelperFunction =
421 getMips16HelperFunction(RetTy: CLI.RetTy, Args&: CLI.getArgs(), needHelper&: NeedMips16Helper);
422 }
423
424 SDValue JumpTarget = Callee;
425
426 // T9 should contain the address of the callee function if
427 // -relocation-model=pic or it is an indirect call.
428 if (IsPICCall || !GlobalOrExternal) {
429 unsigned V0Reg = Mips::V0;
430 if (NeedMips16Helper) {
431 RegsToPass.push_front(x: std::make_pair(x&: V0Reg, y&: Callee));
432 JumpTarget = DAG.getExternalSymbol(Sym: Mips16HelperFunction,
433 VT: getPointerTy(DL: DAG.getDataLayout()));
434 ExternalSymbolSDNode *S = cast<ExternalSymbolSDNode>(Val&: JumpTarget);
435 JumpTarget = getAddrGlobal(N: S, DL: CLI.DL, Ty: JumpTarget.getValueType(), DAG,
436 Flag: MipsII::MO_GOT, Chain,
437 PtrInfo: FuncInfo->callPtrInfo(MF, ES: S->getSymbol()));
438 } else
439 RegsToPass.push_front(x: std::make_pair(x: (unsigned)Mips::T9, y&: Callee));
440 }
441
442 Ops.push_back(Elt: JumpTarget);
443
444 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
445 LocalLinkage, IsCallReloc, CLI, Callee,
446 Chain);
447}
448
449MachineBasicBlock *
450Mips16TargetLowering::emitSel16(unsigned Opc, MachineInstr &MI,
451 MachineBasicBlock *BB) const {
452 if (DontExpandCondPseudos16)
453 return BB;
454 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
455 DebugLoc DL = MI.getDebugLoc();
456 // To "insert" a SELECT_CC instruction, we actually have to insert the
457 // diamond control-flow pattern. The incoming instruction knows the
458 // destination vreg to set, the condition code register to branch on, the
459 // true/false values to select between, and a branch opcode to use.
460 const BasicBlock *LLVM_BB = BB->getBasicBlock();
461 MachineFunction::iterator It = ++BB->getIterator();
462
463 // thisMBB:
464 // ...
465 // TrueVal = ...
466 // setcc r1, r2, r3
467 // bNE r1, r0, copy1MBB
468 // fallthrough --> copy0MBB
469 MachineBasicBlock *thisMBB = BB;
470 MachineFunction *F = BB->getParent();
471 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(BB: LLVM_BB);
472 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(BB: LLVM_BB);
473 F->insert(MBBI: It, MBB: copy0MBB);
474 F->insert(MBBI: It, MBB: sinkMBB);
475
476 // Transfer the remainder of BB and its successor edges to sinkMBB.
477 sinkMBB->splice(Where: sinkMBB->begin(), Other: BB,
478 From: std::next(x: MachineBasicBlock::iterator(MI)), To: BB->end());
479 sinkMBB->transferSuccessorsAndUpdatePHIs(FromMBB: BB);
480
481 // Next, add the true and fallthrough blocks as its successors.
482 BB->addSuccessor(Succ: copy0MBB);
483 BB->addSuccessor(Succ: sinkMBB);
484
485 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: Opc))
486 .addReg(RegNo: MI.getOperand(i: 3).getReg())
487 .addMBB(MBB: sinkMBB);
488
489 // copy0MBB:
490 // %FalseValue = ...
491 // # fallthrough to sinkMBB
492 BB = copy0MBB;
493
494 // Update machine-CFG edges
495 BB->addSuccessor(Succ: sinkMBB);
496
497 // sinkMBB:
498 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
499 // ...
500 BB = sinkMBB;
501
502 BuildMI(BB&: *BB, I: BB->begin(), MIMD: DL, MCID: TII->get(Opcode: Mips::PHI), DestReg: MI.getOperand(i: 0).getReg())
503 .addReg(RegNo: MI.getOperand(i: 1).getReg())
504 .addMBB(MBB: thisMBB)
505 .addReg(RegNo: MI.getOperand(i: 2).getReg())
506 .addMBB(MBB: copy0MBB);
507
508 MI.eraseFromParent(); // The pseudo instruction is gone now.
509 return BB;
510}
511
512MachineBasicBlock *
513Mips16TargetLowering::emitSelT16(unsigned Opc1, unsigned Opc2, MachineInstr &MI,
514 MachineBasicBlock *BB) const {
515 if (DontExpandCondPseudos16)
516 return BB;
517 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
518 DebugLoc DL = MI.getDebugLoc();
519 // To "insert" a SELECT_CC instruction, we actually have to insert the
520 // diamond control-flow pattern. The incoming instruction knows the
521 // destination vreg to set, the condition code register to branch on, the
522 // true/false values to select between, and a branch opcode to use.
523 const BasicBlock *LLVM_BB = BB->getBasicBlock();
524 MachineFunction::iterator It = ++BB->getIterator();
525
526 // thisMBB:
527 // ...
528 // TrueVal = ...
529 // setcc r1, r2, r3
530 // bNE r1, r0, copy1MBB
531 // fallthrough --> copy0MBB
532 MachineBasicBlock *thisMBB = BB;
533 MachineFunction *F = BB->getParent();
534 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(BB: LLVM_BB);
535 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(BB: LLVM_BB);
536 F->insert(MBBI: It, MBB: copy0MBB);
537 F->insert(MBBI: It, MBB: sinkMBB);
538
539 // Transfer the remainder of BB and its successor edges to sinkMBB.
540 sinkMBB->splice(Where: sinkMBB->begin(), Other: BB,
541 From: std::next(x: MachineBasicBlock::iterator(MI)), To: BB->end());
542 sinkMBB->transferSuccessorsAndUpdatePHIs(FromMBB: BB);
543
544 // Next, add the true and fallthrough blocks as its successors.
545 BB->addSuccessor(Succ: copy0MBB);
546 BB->addSuccessor(Succ: sinkMBB);
547
548 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: Opc2))
549 .addReg(RegNo: MI.getOperand(i: 3).getReg())
550 .addReg(RegNo: MI.getOperand(i: 4).getReg());
551 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: Opc1)).addMBB(MBB: sinkMBB);
552
553 // copy0MBB:
554 // %FalseValue = ...
555 // # fallthrough to sinkMBB
556 BB = copy0MBB;
557
558 // Update machine-CFG edges
559 BB->addSuccessor(Succ: sinkMBB);
560
561 // sinkMBB:
562 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
563 // ...
564 BB = sinkMBB;
565
566 BuildMI(BB&: *BB, I: BB->begin(), MIMD: DL, MCID: TII->get(Opcode: Mips::PHI), DestReg: MI.getOperand(i: 0).getReg())
567 .addReg(RegNo: MI.getOperand(i: 1).getReg())
568 .addMBB(MBB: thisMBB)
569 .addReg(RegNo: MI.getOperand(i: 2).getReg())
570 .addMBB(MBB: copy0MBB);
571
572 MI.eraseFromParent(); // The pseudo instruction is gone now.
573 return BB;
574
575}
576
577MachineBasicBlock *
578Mips16TargetLowering::emitSeliT16(unsigned Opc1, unsigned Opc2,
579 MachineInstr &MI,
580 MachineBasicBlock *BB) const {
581 if (DontExpandCondPseudos16)
582 return BB;
583 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
584 DebugLoc DL = MI.getDebugLoc();
585 // To "insert" a SELECT_CC instruction, we actually have to insert the
586 // diamond control-flow pattern. The incoming instruction knows the
587 // destination vreg to set, the condition code register to branch on, the
588 // true/false values to select between, and a branch opcode to use.
589 const BasicBlock *LLVM_BB = BB->getBasicBlock();
590 MachineFunction::iterator It = ++BB->getIterator();
591
592 // thisMBB:
593 // ...
594 // TrueVal = ...
595 // setcc r1, r2, r3
596 // bNE r1, r0, copy1MBB
597 // fallthrough --> copy0MBB
598 MachineBasicBlock *thisMBB = BB;
599 MachineFunction *F = BB->getParent();
600 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(BB: LLVM_BB);
601 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(BB: LLVM_BB);
602 F->insert(MBBI: It, MBB: copy0MBB);
603 F->insert(MBBI: It, MBB: sinkMBB);
604
605 // Transfer the remainder of BB and its successor edges to sinkMBB.
606 sinkMBB->splice(Where: sinkMBB->begin(), Other: BB,
607 From: std::next(x: MachineBasicBlock::iterator(MI)), To: BB->end());
608 sinkMBB->transferSuccessorsAndUpdatePHIs(FromMBB: BB);
609
610 // Next, add the true and fallthrough blocks as its successors.
611 BB->addSuccessor(Succ: copy0MBB);
612 BB->addSuccessor(Succ: sinkMBB);
613
614 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: Opc2))
615 .addReg(RegNo: MI.getOperand(i: 3).getReg())
616 .addImm(Val: MI.getOperand(i: 4).getImm());
617 BuildMI(BB, MIMD: DL, MCID: TII->get(Opcode: Opc1)).addMBB(MBB: sinkMBB);
618
619 // copy0MBB:
620 // %FalseValue = ...
621 // # fallthrough to sinkMBB
622 BB = copy0MBB;
623
624 // Update machine-CFG edges
625 BB->addSuccessor(Succ: sinkMBB);
626
627 // sinkMBB:
628 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
629 // ...
630 BB = sinkMBB;
631
632 BuildMI(BB&: *BB, I: BB->begin(), MIMD: DL, MCID: TII->get(Opcode: Mips::PHI), DestReg: MI.getOperand(i: 0).getReg())
633 .addReg(RegNo: MI.getOperand(i: 1).getReg())
634 .addMBB(MBB: thisMBB)
635 .addReg(RegNo: MI.getOperand(i: 2).getReg())
636 .addMBB(MBB: copy0MBB);
637
638 MI.eraseFromParent(); // The pseudo instruction is gone now.
639 return BB;
640
641}
642
643MachineBasicBlock *
644Mips16TargetLowering::emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
645 MachineInstr &MI,
646 MachineBasicBlock *BB) const {
647 if (DontExpandCondPseudos16)
648 return BB;
649 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
650 Register regX = MI.getOperand(i: 0).getReg();
651 Register regY = MI.getOperand(i: 1).getReg();
652 MachineBasicBlock *target = MI.getOperand(i: 2).getMBB();
653 BuildMI(BB&: *BB, I&: MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: CmpOpc))
654 .addReg(RegNo: regX)
655 .addReg(RegNo: regY);
656 BuildMI(BB&: *BB, I&: MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: BtOpc)).addMBB(MBB: target);
657 MI.eraseFromParent(); // The pseudo instruction is gone now.
658 return BB;
659}
660
661MachineBasicBlock *Mips16TargetLowering::emitFEXT_T8I8I16_ins(
662 unsigned BtOpc, unsigned CmpiOpc, unsigned CmpiXOpc, bool ImmSigned,
663 MachineInstr &MI, MachineBasicBlock *BB) const {
664 if (DontExpandCondPseudos16)
665 return BB;
666 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
667 Register regX = MI.getOperand(i: 0).getReg();
668 int64_t imm = MI.getOperand(i: 1).getImm();
669 MachineBasicBlock *target = MI.getOperand(i: 2).getMBB();
670 unsigned CmpOpc;
671 if (isUInt<8>(x: imm))
672 CmpOpc = CmpiOpc;
673 else if ((!ImmSigned && isUInt<16>(x: imm)) ||
674 (ImmSigned && isInt<16>(x: imm)))
675 CmpOpc = CmpiXOpc;
676 else
677 llvm_unreachable("immediate field not usable");
678 BuildMI(BB&: *BB, I&: MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: CmpOpc)).addReg(RegNo: regX).addImm(Val: imm);
679 BuildMI(BB&: *BB, I&: MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: BtOpc)).addMBB(MBB: target);
680 MI.eraseFromParent(); // The pseudo instruction is gone now.
681 return BB;
682}
683
684static unsigned Mips16WhichOp8uOr16simm
685 (unsigned shortOp, unsigned longOp, int64_t Imm) {
686 if (isUInt<8>(x: Imm))
687 return shortOp;
688 else if (isInt<16>(x: Imm))
689 return longOp;
690 else
691 llvm_unreachable("immediate field not usable");
692}
693
694MachineBasicBlock *
695Mips16TargetLowering::emitFEXT_CCRX16_ins(unsigned SltOpc, MachineInstr &MI,
696 MachineBasicBlock *BB) const {
697 if (DontExpandCondPseudos16)
698 return BB;
699 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
700 Register CC = MI.getOperand(i: 0).getReg();
701 Register regX = MI.getOperand(i: 1).getReg();
702 Register regY = MI.getOperand(i: 2).getReg();
703 BuildMI(BB&: *BB, I&: MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: SltOpc))
704 .addReg(RegNo: regX)
705 .addReg(RegNo: regY);
706 BuildMI(BB&: *BB, I&: MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: Mips::MoveR3216), DestReg: CC)
707 .addReg(RegNo: Mips::T8);
708 MI.eraseFromParent(); // The pseudo instruction is gone now.
709 return BB;
710}
711
712MachineBasicBlock *
713Mips16TargetLowering::emitFEXT_CCRXI16_ins(unsigned SltiOpc, unsigned SltiXOpc,
714 MachineInstr &MI,
715 MachineBasicBlock *BB) const {
716 if (DontExpandCondPseudos16)
717 return BB;
718 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
719 Register CC = MI.getOperand(i: 0).getReg();
720 Register regX = MI.getOperand(i: 1).getReg();
721 int64_t Imm = MI.getOperand(i: 2).getImm();
722 unsigned SltOpc = Mips16WhichOp8uOr16simm(shortOp: SltiOpc, longOp: SltiXOpc, Imm);
723 BuildMI(BB&: *BB, I&: MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: SltOpc)).addReg(RegNo: regX).addImm(Val: Imm);
724 BuildMI(BB&: *BB, I&: MI, MIMD: MI.getDebugLoc(), MCID: TII->get(Opcode: Mips::MoveR3216), DestReg: CC)
725 .addReg(RegNo: Mips::T8);
726 MI.eraseFromParent(); // The pseudo instruction is gone now.
727 return BB;
728
729}
730