1//===-- RISCVSubtarget.cpp - RISC-V Subtarget Information -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the RISC-V specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVSubtarget.h"
14#include "GISel/RISCVCallLowering.h"
15#include "GISel/RISCVInlineAsmLowering.h"
16#include "GISel/RISCVLegalizerInfo.h"
17#include "RISCV.h"
18#include "RISCVFrameLowering.h"
19#include "RISCVSelectionDAGInfo.h"
20#include "RISCVTargetMachine.h"
21#include "llvm/ADT/Statistic.h"
22#include "llvm/CodeGen/MachineFrameInfo.h"
23#include "llvm/CodeGen/MachineTraceMetrics.h"
24#include "llvm/MC/MCSchedule.h"
25#include "llvm/MC/TargetRegistry.h"
26#include "llvm/Option/LibraryOptions.h"
27#include "llvm/Support/ErrorHandling.h"
28#include "llvm/Support/raw_ostream.h"
29
30using namespace llvm;
31
32#define DEBUG_TYPE "riscv-macro-fusion"
33
34#define GET_RISCV_MACRO_FUSION_PRED_IMPL
35#include "RISCVGenMacroFusion.inc"
36
37#undef DEBUG_TYPE
38#define DEBUG_TYPE "riscv-subtarget"
39
40#define GET_SUBTARGETINFO_TARGET_DESC
41#define GET_SUBTARGETINFO_CTOR
42#include "RISCVGenSubtargetInfo.inc"
43
44#define OPTIONS_STRUCT_DEFS
45#include "RISCVOptions.inc"
46
47namespace llvm::RISCVTuneInfoTable {
48
49#define GET_RISCVTuneInfoTable_IMPL
50#include "RISCVGenSearchableTables.inc"
51} // namespace llvm::RISCVTuneInfoTable
52
53void RISCVSubtarget::anchor() {}
54
55RISCVSubtarget &
56RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU,
57 StringRef TuneCPU, StringRef FS,
58 StringRef ABIName) {
59 // Determine default and user-specified characteristics
60 bool Is64Bit = TT.isArch64Bit();
61 if (CPU.empty() || CPU == "generic")
62 CPU = Is64Bit ? "generic-rv64" : "generic-rv32";
63
64 if (TuneCPU.empty())
65 TuneCPU = CPU;
66 if (TuneCPU == "generic")
67 TuneCPU = Is64Bit ? "generic-rv64" : "generic-rv32";
68
69 TuneInfo = RISCVTuneInfoTable::getRISCVTuneInfo(Name: TuneCPU);
70 // If there is no TuneInfo for this CPU, we fail back to generic.
71 if (!TuneInfo)
72 TuneInfo = RISCVTuneInfoTable::getRISCVTuneInfo(Name: "generic");
73 assert(TuneInfo && "TuneInfo shouldn't be nullptr!");
74
75 ParseSubtargetFeatures(CPU, TuneCPU, FS);
76
77 RISCV::updateCZceFeatureImplications(STI&: *this);
78
79 // Re-sync the flags.
80 HasStdExtZcd = hasFeature(Feature: RISCV::FeatureStdExtZcd);
81 HasStdExtZcf = hasFeature(Feature: RISCV::FeatureStdExtZcf);
82 HasStdExtC = hasFeature(Feature: RISCV::FeatureStdExtC);
83 HasStdExtZce = hasFeature(Feature: RISCV::FeatureStdExtZce);
84
85 // Can't be fatal: per-function subtargets mean this one may just be the
86 // module-level default with no matching function, e.g. -target-abi ilp32f
87 // with no global -mattr=+f but all functions have their own "+f" attribute.
88 if (auto ABIOrErr = RISCVABI::computeTargetABI(STI: *this, ABIName)) {
89 TargetABI = *ABIOrErr;
90 } else {
91 errs() << "note: " << toString(E: ABIOrErr.takeError())
92 << " (ignoring target-abi)\n";
93 TargetABI = cantFail(ValOrErr: RISCVABI::computeTargetABI(STI: *this, ABIName: ""));
94 }
95 RISCVFeatures::validate(TT, FeatureBits: getFeatureBits());
96 return *this;
97}
98
99RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU,
100 StringRef TuneCPU, StringRef FS,
101 StringRef ABIName, unsigned RVVVectorBitsMin,
102 unsigned RVVVectorBitsMax,
103 const TargetMachine &TM)
104 : RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS),
105 CLOpts(static_cast<const RISCVTargetMachine &>(TM).getCLOpts()),
106 IsLittleEndian(TT.isLittleEndian()), RVVVectorBitsMin(RVVVectorBitsMin),
107 RVVVectorBitsMax(RVVVectorBitsMax),
108 FrameLowering(
109 initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
110 InstrInfo(*this), TLInfo(TM, *this) {
111 TSInfo = std::make_unique<RISCVSelectionDAGInfo>();
112}
113
114RISCVSubtarget::~RISCVSubtarget() = default;
115
116const SelectionDAGTargetInfo *RISCVSubtarget::getSelectionDAGInfo() const {
117 return TSInfo.get();
118}
119
120const InlineAsmLowering *RISCVSubtarget::getInlineAsmLowering() const {
121 if (!InlineAsmLoweringInfo)
122 InlineAsmLoweringInfo.reset(
123 p: new RISCVInlineAsmLowering(getTargetLowering()));
124 return InlineAsmLoweringInfo.get();
125}
126
127const CallLowering *RISCVSubtarget::getCallLowering() const {
128 if (!CallLoweringInfo)
129 CallLoweringInfo.reset(p: new RISCVCallLowering(*getTargetLowering()));
130 return CallLoweringInfo.get();
131}
132
133InstructionSelector *RISCVSubtarget::getInstructionSelector() const {
134 if (!InstSelector) {
135 InstSelector.reset(p: createRISCVInstructionSelector(
136 *static_cast<const RISCVTargetMachine *>(&TLInfo.getTargetMachine()),
137 *this, *getRegBankInfo()));
138 }
139 return InstSelector.get();
140}
141
142const LegalizerInfo *RISCVSubtarget::getLegalizerInfo() const {
143 if (!Legalizer)
144 Legalizer.reset(p: new RISCVLegalizerInfo(*this));
145 return Legalizer.get();
146}
147
148const RISCVRegisterBankInfo *RISCVSubtarget::getRegBankInfo() const {
149 if (!RegBankInfo)
150 RegBankInfo.reset(p: new RISCVRegisterBankInfo(getHwMode()));
151 return RegBankInfo.get();
152}
153
154bool RISCVSubtarget::useConstantPoolForLargeInts() const {
155 return CLOpts.constant_pool_for_large_ints;
156}
157
158// Returns true if VT is a P extension packed SIMD type.
159bool RISCVSubtarget::isPExtPackedType(MVT VT) const {
160 if (!HasStdExtP)
161 return false;
162
163 // RV32 supports 32-bit and 64-bit vectors. RV64 only support 64-bit vectors.
164 if (!is64Bit() && (VT == MVT::v4i8 || VT == MVT::v2i16))
165 return true;
166
167 return VT == MVT::v8i8 || VT == MVT::v4i16 || VT == MVT::v2i32;
168}
169
170// Returns true if VT is a P extension packed double-wide SIMD type.
171bool RISCVSubtarget::isPExtPackedDoubleType(MVT VT) const {
172 if (!HasStdExtP || is64Bit())
173 return false;
174
175 return VT == MVT::v8i8 || VT == MVT::v4i16 || VT == MVT::v2i32;
176}
177
178unsigned RISCVSubtarget::getMaxBuildIntsCost() const {
179 // Loading integer from constant pool needs two instructions (the reason why
180 // the minimum cost is 2): an address calculation instruction and a load
181 // instruction. Usually, address calculation and instructions used for
182 // building integers (addi, slli, etc.) can be done in one cycle, so here we
183 // set the default cost to (LoadLatency + 1) if no threshold is provided.
184 return CLOpts.max_build_ints_cost == 0
185 ? getLoadLatency() + 1
186 : std::max<unsigned>(a: 2, b: CLOpts.max_build_ints_cost);
187}
188
189unsigned RISCVSubtarget::getMispredictionPenalty() const {
190 return CLOpts.sched_mispredict_penalty.value_or(
191 u: getSchedModel().MispredictPenalty);
192}
193
194unsigned RISCVSubtarget::getLoadLatency() const {
195 return CLOpts.sched_load_latency.value_or(u: getSchedModel().LoadLatency);
196}
197
198unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits() const {
199 assert(hasVInstructions() &&
200 "Tried to get vector length without Zve or V extension support!");
201
202 // ZvlLen specifies the minimum required vlen. The upper bound provided by
203 // riscv-v-vector-bits-max should be no less than it.
204 if (RVVVectorBitsMax != 0 && RVVVectorBitsMax < ZvlLen)
205 report_fatal_error(reason: "riscv-v-vector-bits-max specified is lower "
206 "than the Zvl*b limitation");
207
208 return RVVVectorBitsMax;
209}
210
211unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const {
212 assert(hasVInstructions() &&
213 "Tried to get vector length without Zve or V extension support!");
214
215 if (RVVVectorBitsMin == -1U)
216 return ZvlLen;
217
218 // ZvlLen specifies the minimum required vlen. The lower bound provided by
219 // riscv-v-vector-bits-min should be no less than it.
220 if (RVVVectorBitsMin != 0 && RVVVectorBitsMin < ZvlLen)
221 report_fatal_error(reason: "riscv-v-vector-bits-min specified is lower "
222 "than the Zvl*b limitation");
223
224 return RVVVectorBitsMin;
225}
226
227bool RISCVSubtarget::useRVVForFixedLengthVectors() const {
228 return hasVInstructions() &&
229 getMinRVVVectorSizeInBits() >= RISCV::RVVBitsPerBlock;
230}
231
232bool RISCVSubtarget::enableSubRegLiveness() const { return true; }
233
234bool RISCVSubtarget::enableMachinePipeliner() const {
235 return getSchedModel().hasInstrSchedModel();
236}
237
238void RISCVSubtarget::mirFileLoaded(MachineFunction &MF) const {
239 // We usually compute max call frame size after ISel. Do the computation now
240 // if the .mir file didn't specify it. Note that this will probably give you
241 // bogus values after PEI has eliminated the callframe setup/destroy pseudo
242 // instructions, specify explicitly if you need it to be correct.
243 MachineFrameInfo &MFI = MF.getFrameInfo();
244 if (!MFI.isMaxCallFrameSizeComputed())
245 MFI.computeMaxCallFrameSize(MF);
246}
247
248 /// Enable use of alias analysis during code generation (during MI
249 /// scheduling, DAGCombine, etc.).
250bool RISCVSubtarget::useAA() const { return CLOpts.use_aa; }
251
252unsigned RISCVSubtarget::getMinimumJumpTableEntries() const {
253 return CLOpts.min_jump_table_entries.value_or(
254 u: TuneInfo->MinimumJumpTableEntries);
255}
256
257void RISCVSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
258 const SchedRegion &Region) const {
259 // Do bidirectional scheduling since it provides a more balanced scheduling
260 // leading to better performance. This will increase compile time.
261 Policy.OnlyTopDown = false;
262 Policy.OnlyBottomUp = false;
263
264 // Disabling the latency heuristic can reduce the number of spills/reloads but
265 // will cause some regressions on some cores.
266 Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
267
268 // Spilling is generally expensive on all RISC-V cores, so always enable
269 // register-pressure tracking. This will increase compile time.
270 Policy.ShouldTrackPressure = true;
271}
272
273void RISCVSubtarget::overridePostRASchedPolicy(
274 MachineSchedPolicy &Policy, const SchedRegion &Region) const {
275 MISched::Direction PostRASchedDirection = getPostRASchedDirection();
276 if (PostRASchedDirection == MISched::TopDown) {
277 Policy.OnlyTopDown = true;
278 Policy.OnlyBottomUp = false;
279 } else if (PostRASchedDirection == MISched::BottomUp) {
280 Policy.OnlyTopDown = false;
281 Policy.OnlyBottomUp = true;
282 } else if (PostRASchedDirection == MISched::Bidirectional) {
283 Policy.OnlyTopDown = false;
284 Policy.OnlyBottomUp = false;
285 }
286}
287
288bool RISCVSubtarget::useMIPSLoadStorePairs() const {
289 return CLOpts.mips_load_store_pairs && HasVendorXMIPSLSP;
290}
291
292bool RISCVSubtarget::useMIPSCCMovInsn() const {
293 return CLOpts.mips_ccmov && HasVendorXMIPSCMov;
294}
295