1//===-- RISCVSubtarget.cpp - RISC-V Subtarget Information -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the RISC-V specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVSubtarget.h"
14#include "GISel/RISCVCallLowering.h"
15#include "GISel/RISCVLegalizerInfo.h"
16#include "RISCV.h"
17#include "RISCVFrameLowering.h"
18#include "RISCVSelectionDAGInfo.h"
19#include "RISCVTargetMachine.h"
20#include "llvm/MC/TargetRegistry.h"
21#include "llvm/Support/ErrorHandling.h"
22
23using namespace llvm;
24
25#define DEBUG_TYPE "riscv-subtarget"
26
27#define GET_SUBTARGETINFO_TARGET_DESC
28#define GET_SUBTARGETINFO_CTOR
29#include "RISCVGenSubtargetInfo.inc"
30
31#define GET_RISCV_MACRO_FUSION_PRED_IMPL
32#include "RISCVGenMacroFusion.inc"
33
34namespace llvm::RISCVTuneInfoTable {
35
36#define GET_RISCVTuneInfoTable_IMPL
37#include "RISCVGenSearchableTables.inc"
38} // namespace llvm::RISCVTuneInfoTable
39
40static cl::opt<unsigned> RVVVectorLMULMax(
41 "riscv-v-fixed-length-vector-lmul-max",
42 cl::desc("The maximum LMUL value to use for fixed length vectors. "
43 "Fractional LMUL values are not supported."),
44 cl::init(Val: 8), cl::Hidden);
45
46static cl::opt<bool> RISCVDisableUsingConstantPoolForLargeInts(
47 "riscv-disable-using-constant-pool-for-large-ints",
48 cl::desc("Disable using constant pool for large integers."),
49 cl::init(Val: false), cl::Hidden);
50
51static cl::opt<unsigned> RISCVMaxBuildIntsCost(
52 "riscv-max-build-ints-cost",
53 cl::desc("The maximum cost used for building integers."), cl::init(Val: 0),
54 cl::Hidden);
55
56static cl::opt<bool> UseAA("riscv-use-aa", cl::init(Val: true),
57 cl::desc("Enable the use of AA during codegen."));
58
59static cl::opt<unsigned> RISCVMinimumJumpTableEntries(
60 "riscv-min-jump-table-entries", cl::Hidden,
61 cl::desc("Set minimum number of entries to use a jump table on RISCV"));
62
63static cl::opt<bool> UseMIPSLoadStorePairsOpt(
64 "use-riscv-mips-load-store-pairs",
65 cl::desc("Enable the load/store pair optimization pass"), cl::init(Val: false),
66 cl::Hidden);
67
68static cl::opt<bool> UseMIPSCCMovInsn("use-riscv-mips-ccmov",
69 cl::desc("Use 'mips.ccmov' instruction"),
70 cl::init(Val: true), cl::Hidden);
71
72static cl::opt<bool> EnablePExtSIMDCodeGen(
73 "riscv-enable-p-ext-simd-codegen",
74 cl::desc("Turn on P Extension SIMD codegen(This is a temporary switch "
75 "where only partial codegen is currently supported)"),
76 cl::init(Val: false), cl::Hidden);
77
78void RISCVSubtarget::anchor() {}
79
80RISCVSubtarget &
81RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU,
82 StringRef TuneCPU, StringRef FS,
83 StringRef ABIName) {
84 // Determine default and user-specified characteristics
85 bool Is64Bit = TT.isArch64Bit();
86 if (CPU.empty() || CPU == "generic")
87 CPU = Is64Bit ? "generic-rv64" : "generic-rv32";
88
89 if (TuneCPU.empty())
90 TuneCPU = CPU;
91 if (TuneCPU == "generic")
92 TuneCPU = Is64Bit ? "generic-rv64" : "generic-rv32";
93
94 TuneInfo = RISCVTuneInfoTable::getRISCVTuneInfo(Name: TuneCPU);
95 // If there is no TuneInfo for this CPU, we fail back to generic.
96 if (!TuneInfo)
97 TuneInfo = RISCVTuneInfoTable::getRISCVTuneInfo(Name: "generic");
98 assert(TuneInfo && "TuneInfo shouldn't be nullptr!");
99
100 ParseSubtargetFeatures(CPU, TuneCPU, FS);
101 TargetABI = RISCVABI::computeTargetABI(TT, FeatureBits: getFeatureBits(), ABIName);
102 RISCVFeatures::validate(TT, FeatureBits: getFeatureBits());
103 return *this;
104}
105
106RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU,
107 StringRef TuneCPU, StringRef FS,
108 StringRef ABIName, unsigned RVVVectorBitsMin,
109 unsigned RVVVectorBitsMax,
110 const TargetMachine &TM)
111 : RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS),
112 IsLittleEndian(TT.isLittleEndian()), RVVVectorBitsMin(RVVVectorBitsMin),
113 RVVVectorBitsMax(RVVVectorBitsMax),
114 FrameLowering(
115 initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
116 InstrInfo(*this), TLInfo(TM, *this) {
117 TSInfo = std::make_unique<RISCVSelectionDAGInfo>();
118}
119
120RISCVSubtarget::~RISCVSubtarget() = default;
121
122const SelectionDAGTargetInfo *RISCVSubtarget::getSelectionDAGInfo() const {
123 return TSInfo.get();
124}
125
126const CallLowering *RISCVSubtarget::getCallLowering() const {
127 if (!CallLoweringInfo)
128 CallLoweringInfo.reset(p: new RISCVCallLowering(*getTargetLowering()));
129 return CallLoweringInfo.get();
130}
131
132InstructionSelector *RISCVSubtarget::getInstructionSelector() const {
133 if (!InstSelector) {
134 InstSelector.reset(p: createRISCVInstructionSelector(
135 *static_cast<const RISCVTargetMachine *>(&TLInfo.getTargetMachine()),
136 *this, *getRegBankInfo()));
137 }
138 return InstSelector.get();
139}
140
141const LegalizerInfo *RISCVSubtarget::getLegalizerInfo() const {
142 if (!Legalizer)
143 Legalizer.reset(p: new RISCVLegalizerInfo(*this));
144 return Legalizer.get();
145}
146
147const RISCVRegisterBankInfo *RISCVSubtarget::getRegBankInfo() const {
148 if (!RegBankInfo)
149 RegBankInfo.reset(p: new RISCVRegisterBankInfo(getHwMode()));
150 return RegBankInfo.get();
151}
152
153bool RISCVSubtarget::useConstantPoolForLargeInts() const {
154 return !RISCVDisableUsingConstantPoolForLargeInts;
155}
156
157bool RISCVSubtarget::enablePExtSIMDCodeGen() const {
158 return HasStdExtP && EnablePExtSIMDCodeGen;
159}
160
161// Returns true if VT is a P extension packed SIMD type that fits in XLen.
162bool RISCVSubtarget::isPExtPackedType(MVT VT) const {
163 if (!enablePExtSIMDCodeGen())
164 return false;
165
166 if (is64Bit())
167 return VT == MVT::v8i8 || VT == MVT::v4i16 || VT == MVT::v2i32;
168 return VT == MVT::v4i8 || VT == MVT::v2i16;
169}
170
171unsigned RISCVSubtarget::getMaxBuildIntsCost() const {
172 // Loading integer from constant pool needs two instructions (the reason why
173 // the minimum cost is 2): an address calculation instruction and a load
174 // instruction. Usually, address calculation and instructions used for
175 // building integers (addi, slli, etc.) can be done in one cycle, so here we
176 // set the default cost to (LoadLatency + 1) if no threshold is provided.
177 return RISCVMaxBuildIntsCost == 0
178 ? getSchedModel().LoadLatency + 1
179 : std::max<unsigned>(a: 2, b: RISCVMaxBuildIntsCost);
180}
181
182unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits() const {
183 assert(hasVInstructions() &&
184 "Tried to get vector length without Zve or V extension support!");
185
186 // ZvlLen specifies the minimum required vlen. The upper bound provided by
187 // riscv-v-vector-bits-max should be no less than it.
188 if (RVVVectorBitsMax != 0 && RVVVectorBitsMax < ZvlLen)
189 report_fatal_error(reason: "riscv-v-vector-bits-max specified is lower "
190 "than the Zvl*b limitation");
191
192 return RVVVectorBitsMax;
193}
194
195unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const {
196 assert(hasVInstructions() &&
197 "Tried to get vector length without Zve or V extension support!");
198
199 if (RVVVectorBitsMin == -1U)
200 return ZvlLen;
201
202 // ZvlLen specifies the minimum required vlen. The lower bound provided by
203 // riscv-v-vector-bits-min should be no less than it.
204 if (RVVVectorBitsMin != 0 && RVVVectorBitsMin < ZvlLen)
205 report_fatal_error(reason: "riscv-v-vector-bits-min specified is lower "
206 "than the Zvl*b limitation");
207
208 return RVVVectorBitsMin;
209}
210
211unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors() const {
212 assert(hasVInstructions() &&
213 "Tried to get vector length without Zve or V extension support!");
214 assert(RVVVectorLMULMax <= 8 &&
215 llvm::has_single_bit<uint32_t>(RVVVectorLMULMax) &&
216 "V extension requires a LMUL to be at most 8 and a power of 2!");
217 return llvm::bit_floor(Value: std::clamp<unsigned>(val: RVVVectorLMULMax, lo: 1, hi: 8));
218}
219
220bool RISCVSubtarget::useRVVForFixedLengthVectors() const {
221 return hasVInstructions() &&
222 getMinRVVVectorSizeInBits() >= RISCV::RVVBitsPerBlock;
223}
224
225bool RISCVSubtarget::enableSubRegLiveness() const { return true; }
226
227bool RISCVSubtarget::enableMachinePipeliner() const {
228 return getSchedModel().hasInstrSchedModel();
229}
230
231 /// Enable use of alias analysis during code generation (during MI
232 /// scheduling, DAGCombine, etc.).
233bool RISCVSubtarget::useAA() const { return UseAA; }
234
235unsigned RISCVSubtarget::getMinimumJumpTableEntries() const {
236 return RISCVMinimumJumpTableEntries.getNumOccurrences() > 0
237 ? RISCVMinimumJumpTableEntries
238 : TuneInfo->MinimumJumpTableEntries;
239}
240
241void RISCVSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
242 const SchedRegion &Region) const {
243 // Do bidirectional scheduling since it provides a more balanced scheduling
244 // leading to better performance. This will increase compile time.
245 Policy.OnlyTopDown = false;
246 Policy.OnlyBottomUp = false;
247
248 // Disabling the latency heuristic can reduce the number of spills/reloads but
249 // will cause some regressions on some cores.
250 Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
251
252 // Spilling is generally expensive on all RISC-V cores, so always enable
253 // register-pressure tracking. This will increase compile time.
254 Policy.ShouldTrackPressure = true;
255}
256
257void RISCVSubtarget::overridePostRASchedPolicy(
258 MachineSchedPolicy &Policy, const SchedRegion &Region) const {
259 MISched::Direction PostRASchedDirection = getPostRASchedDirection();
260 if (PostRASchedDirection == MISched::TopDown) {
261 Policy.OnlyTopDown = true;
262 Policy.OnlyBottomUp = false;
263 } else if (PostRASchedDirection == MISched::BottomUp) {
264 Policy.OnlyTopDown = false;
265 Policy.OnlyBottomUp = true;
266 } else if (PostRASchedDirection == MISched::Bidirectional) {
267 Policy.OnlyTopDown = false;
268 Policy.OnlyBottomUp = false;
269 }
270}
271
272bool RISCVSubtarget::useMIPSLoadStorePairs() const {
273 return UseMIPSLoadStorePairsOpt && HasVendorXMIPSLSP;
274}
275
276bool RISCVSubtarget::useMIPSCCMovInsn() const {
277 return UseMIPSCCMovInsn && HasVendorXMIPSCMov;
278}
279