1//===-- RISCVSubtarget.cpp - RISC-V Subtarget Information -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the RISC-V specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#include "RISCVSubtarget.h"
14#include "GISel/RISCVCallLowering.h"
15#include "GISel/RISCVInlineAsmLowering.h"
16#include "GISel/RISCVLegalizerInfo.h"
17#include "RISCV.h"
18#include "RISCVFrameLowering.h"
19#include "RISCVSelectionDAGInfo.h"
20#include "RISCVTargetMachine.h"
21#include "llvm/ADT/Statistic.h"
22#include "llvm/CodeGen/MachineFrameInfo.h"
23#include "llvm/MC/MCSchedule.h"
24#include "llvm/MC/TargetRegistry.h"
25#include "llvm/Support/CommandLine.h"
26#include "llvm/Support/ErrorHandling.h"
27#include "llvm/Support/raw_ostream.h"
28
29using namespace llvm;
30
31static cl::opt<unsigned> SchedMispredictPenalty(
32 "riscv-sched-mispredict-penalty", cl::Hidden,
33 cl::init(Val: MCSchedModel::DefaultMispredictPenalty),
34 cl::cat(MCScheduleOptions),
35 cl::desc("Override the mispredict penalty (in cycles) in the scheduler "
36 "model. A non-negative value overrides the target default."));
37
38static cl::opt<unsigned> SchedLoadLatency(
39 "riscv-sched-load-latency", cl::Hidden,
40 cl::init(Val: MCSchedModel::DefaultLoadLatency), cl::cat(MCScheduleOptions),
41 cl::desc("Override the load latency (in cycles) in the scheduler model. "
42 "A non-negative value overrides the target default."));
43
44#define DEBUG_TYPE "riscv-macro-fusion"
45
46#define GET_RISCV_MACRO_FUSION_PRED_IMPL
47#include "RISCVGenMacroFusion.inc"
48
49#undef DEBUG_TYPE
50#define DEBUG_TYPE "riscv-subtarget"
51
52#define GET_SUBTARGETINFO_TARGET_DESC
53#define GET_SUBTARGETINFO_CTOR
54#include "RISCVGenSubtargetInfo.inc"
55
56namespace llvm::RISCVTuneInfoTable {
57
58#define GET_RISCVTuneInfoTable_IMPL
59#include "RISCVGenSearchableTables.inc"
60} // namespace llvm::RISCVTuneInfoTable
61
62static cl::opt<bool> RISCVDisableUsingConstantPoolForLargeInts(
63 "riscv-disable-using-constant-pool-for-large-ints",
64 cl::desc("Disable using constant pool for large integers."),
65 cl::init(Val: false), cl::Hidden);
66
67static cl::opt<unsigned> RISCVMaxBuildIntsCost(
68 "riscv-max-build-ints-cost",
69 cl::desc("The maximum cost used for building integers."), cl::init(Val: 0),
70 cl::Hidden);
71
72static cl::opt<bool> UseAA("riscv-use-aa", cl::init(Val: true),
73 cl::desc("Enable the use of AA during codegen."));
74
75static cl::opt<unsigned> RISCVMinimumJumpTableEntries(
76 "riscv-min-jump-table-entries", cl::Hidden,
77 cl::desc("Set minimum number of entries to use a jump table on RISCV"));
78
79static cl::opt<bool> UseMIPSLoadStorePairsOpt(
80 "use-riscv-mips-load-store-pairs",
81 cl::desc("Enable the load/store pair optimization pass"), cl::init(Val: false),
82 cl::Hidden);
83
84static cl::opt<bool> UseMIPSCCMovInsn("use-riscv-mips-ccmov",
85 cl::desc("Use 'mips.ccmov' instruction"),
86 cl::init(Val: true), cl::Hidden);
87
88void RISCVSubtarget::anchor() {}
89
90RISCVSubtarget &
91RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU,
92 StringRef TuneCPU, StringRef FS,
93 StringRef ABIName) {
94 // Determine default and user-specified characteristics
95 bool Is64Bit = TT.isArch64Bit();
96 if (CPU.empty() || CPU == "generic")
97 CPU = Is64Bit ? "generic-rv64" : "generic-rv32";
98
99 if (TuneCPU.empty())
100 TuneCPU = CPU;
101 if (TuneCPU == "generic")
102 TuneCPU = Is64Bit ? "generic-rv64" : "generic-rv32";
103
104 TuneInfo = RISCVTuneInfoTable::getRISCVTuneInfo(Name: TuneCPU);
105 // If there is no TuneInfo for this CPU, we fail back to generic.
106 if (!TuneInfo)
107 TuneInfo = RISCVTuneInfoTable::getRISCVTuneInfo(Name: "generic");
108 assert(TuneInfo && "TuneInfo shouldn't be nullptr!");
109
110 ParseSubtargetFeatures(CPU, TuneCPU, FS);
111
112 RISCV::updateCZceFeatureImplications(STI&: *this);
113
114 // Re-sync the flags.
115 HasStdExtZcd = hasFeature(Feature: RISCV::FeatureStdExtZcd);
116 HasStdExtZcf = hasFeature(Feature: RISCV::FeatureStdExtZcf);
117 HasStdExtC = hasFeature(Feature: RISCV::FeatureStdExtC);
118 HasStdExtZce = hasFeature(Feature: RISCV::FeatureStdExtZce);
119
120 // Can't be fatal: per-function subtargets mean this one may just be the
121 // module-level default with no matching function, e.g. -target-abi ilp32f
122 // with no global -mattr=+f but all functions have their own "+f" attribute.
123 if (auto ABIOrErr = RISCVABI::computeTargetABI(STI: *this, ABIName)) {
124 TargetABI = *ABIOrErr;
125 } else {
126 errs() << "note: " << toString(E: ABIOrErr.takeError())
127 << " (ignoring target-abi)\n";
128 TargetABI = cantFail(ValOrErr: RISCVABI::computeTargetABI(STI: *this, ABIName: ""));
129 }
130 RISCVFeatures::validate(TT, FeatureBits: getFeatureBits());
131 return *this;
132}
133
134RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU,
135 StringRef TuneCPU, StringRef FS,
136 StringRef ABIName, unsigned RVVVectorBitsMin,
137 unsigned RVVVectorBitsMax,
138 const TargetMachine &TM)
139 : RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS),
140 IsLittleEndian(TT.isLittleEndian()), RVVVectorBitsMin(RVVVectorBitsMin),
141 RVVVectorBitsMax(RVVVectorBitsMax),
142 FrameLowering(
143 initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
144 InstrInfo(*this), TLInfo(TM, *this) {
145 TSInfo = std::make_unique<RISCVSelectionDAGInfo>();
146}
147
148RISCVSubtarget::~RISCVSubtarget() = default;
149
150const SelectionDAGTargetInfo *RISCVSubtarget::getSelectionDAGInfo() const {
151 return TSInfo.get();
152}
153
154const InlineAsmLowering *RISCVSubtarget::getInlineAsmLowering() const {
155 if (!InlineAsmLoweringInfo)
156 InlineAsmLoweringInfo.reset(
157 p: new RISCVInlineAsmLowering(getTargetLowering()));
158 return InlineAsmLoweringInfo.get();
159}
160
161const CallLowering *RISCVSubtarget::getCallLowering() const {
162 if (!CallLoweringInfo)
163 CallLoweringInfo.reset(p: new RISCVCallLowering(*getTargetLowering()));
164 return CallLoweringInfo.get();
165}
166
167InstructionSelector *RISCVSubtarget::getInstructionSelector() const {
168 if (!InstSelector) {
169 InstSelector.reset(p: createRISCVInstructionSelector(
170 *static_cast<const RISCVTargetMachine *>(&TLInfo.getTargetMachine()),
171 *this, *getRegBankInfo()));
172 }
173 return InstSelector.get();
174}
175
176const LegalizerInfo *RISCVSubtarget::getLegalizerInfo() const {
177 if (!Legalizer)
178 Legalizer.reset(p: new RISCVLegalizerInfo(*this));
179 return Legalizer.get();
180}
181
182const RISCVRegisterBankInfo *RISCVSubtarget::getRegBankInfo() const {
183 if (!RegBankInfo)
184 RegBankInfo.reset(p: new RISCVRegisterBankInfo(getHwMode()));
185 return RegBankInfo.get();
186}
187
188bool RISCVSubtarget::useConstantPoolForLargeInts() const {
189 return !RISCVDisableUsingConstantPoolForLargeInts;
190}
191
192// Returns true if VT is a P extension packed SIMD type.
193bool RISCVSubtarget::isPExtPackedType(MVT VT) const {
194 if (!HasStdExtP)
195 return false;
196
197 // RV32 supports 32-bit and 64-bit vectors. RV64 only support 64-bit vectors.
198 if (!is64Bit() && (VT == MVT::v4i8 || VT == MVT::v2i16))
199 return true;
200
201 return VT == MVT::v8i8 || VT == MVT::v4i16 || VT == MVT::v2i32;
202}
203
204// Returns true if VT is a P extension packed double-wide SIMD type.
205bool RISCVSubtarget::isPExtPackedDoubleType(MVT VT) const {
206 if (!HasStdExtP || is64Bit())
207 return false;
208
209 return VT == MVT::v8i8 || VT == MVT::v4i16 || VT == MVT::v2i32;
210}
211
212unsigned RISCVSubtarget::getMaxBuildIntsCost() const {
213 // Loading integer from constant pool needs two instructions (the reason why
214 // the minimum cost is 2): an address calculation instruction and a load
215 // instruction. Usually, address calculation and instructions used for
216 // building integers (addi, slli, etc.) can be done in one cycle, so here we
217 // set the default cost to (LoadLatency + 1) if no threshold is provided.
218 return RISCVMaxBuildIntsCost == 0
219 ? getLoadLatency() + 1
220 : std::max<unsigned>(a: 2, b: RISCVMaxBuildIntsCost);
221}
222
223unsigned RISCVSubtarget::getMispredictionPenalty() const {
224 if (SchedMispredictPenalty.getNumOccurrences() > 0)
225 return SchedMispredictPenalty;
226 return getSchedModel().MispredictPenalty;
227}
228
229unsigned RISCVSubtarget::getLoadLatency() const {
230 if (SchedLoadLatency.getNumOccurrences() > 0)
231 return SchedLoadLatency;
232 return getSchedModel().LoadLatency;
233}
234
235unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits() const {
236 assert(hasVInstructions() &&
237 "Tried to get vector length without Zve or V extension support!");
238
239 // ZvlLen specifies the minimum required vlen. The upper bound provided by
240 // riscv-v-vector-bits-max should be no less than it.
241 if (RVVVectorBitsMax != 0 && RVVVectorBitsMax < ZvlLen)
242 report_fatal_error(reason: "riscv-v-vector-bits-max specified is lower "
243 "than the Zvl*b limitation");
244
245 return RVVVectorBitsMax;
246}
247
248unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const {
249 assert(hasVInstructions() &&
250 "Tried to get vector length without Zve or V extension support!");
251
252 if (RVVVectorBitsMin == -1U)
253 return ZvlLen;
254
255 // ZvlLen specifies the minimum required vlen. The lower bound provided by
256 // riscv-v-vector-bits-min should be no less than it.
257 if (RVVVectorBitsMin != 0 && RVVVectorBitsMin < ZvlLen)
258 report_fatal_error(reason: "riscv-v-vector-bits-min specified is lower "
259 "than the Zvl*b limitation");
260
261 return RVVVectorBitsMin;
262}
263
264unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors() const {
265 assert(hasVInstructions() &&
266 "Tried to get vector length without Zve or V extension support!");
267 return 8;
268}
269
270bool RISCVSubtarget::useRVVForFixedLengthVectors() const {
271 return hasVInstructions() &&
272 getMinRVVVectorSizeInBits() >= RISCV::RVVBitsPerBlock;
273}
274
275bool RISCVSubtarget::enableSubRegLiveness() const { return true; }
276
277bool RISCVSubtarget::enableMachinePipeliner() const {
278 return getSchedModel().hasInstrSchedModel();
279}
280
281void RISCVSubtarget::mirFileLoaded(MachineFunction &MF) const {
282 // We usually compute max call frame size after ISel. Do the computation now
283 // if the .mir file didn't specify it. Note that this will probably give you
284 // bogus values after PEI has eliminated the callframe setup/destroy pseudo
285 // instructions, specify explicitly if you need it to be correct.
286 MachineFrameInfo &MFI = MF.getFrameInfo();
287 if (!MFI.isMaxCallFrameSizeComputed())
288 MFI.computeMaxCallFrameSize(MF);
289}
290
291 /// Enable use of alias analysis during code generation (during MI
292 /// scheduling, DAGCombine, etc.).
293bool RISCVSubtarget::useAA() const { return UseAA; }
294
295unsigned RISCVSubtarget::getMinimumJumpTableEntries() const {
296 return RISCVMinimumJumpTableEntries.getNumOccurrences() > 0
297 ? RISCVMinimumJumpTableEntries
298 : TuneInfo->MinimumJumpTableEntries;
299}
300
301void RISCVSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
302 const SchedRegion &Region) const {
303 // Do bidirectional scheduling since it provides a more balanced scheduling
304 // leading to better performance. This will increase compile time.
305 Policy.OnlyTopDown = false;
306 Policy.OnlyBottomUp = false;
307
308 // Disabling the latency heuristic can reduce the number of spills/reloads but
309 // will cause some regressions on some cores.
310 Policy.DisableLatencyHeuristic = DisableLatencySchedHeuristic;
311
312 // Spilling is generally expensive on all RISC-V cores, so always enable
313 // register-pressure tracking. This will increase compile time.
314 Policy.ShouldTrackPressure = true;
315}
316
317void RISCVSubtarget::overridePostRASchedPolicy(
318 MachineSchedPolicy &Policy, const SchedRegion &Region) const {
319 MISched::Direction PostRASchedDirection = getPostRASchedDirection();
320 if (PostRASchedDirection == MISched::TopDown) {
321 Policy.OnlyTopDown = true;
322 Policy.OnlyBottomUp = false;
323 } else if (PostRASchedDirection == MISched::BottomUp) {
324 Policy.OnlyTopDown = false;
325 Policy.OnlyBottomUp = true;
326 } else if (PostRASchedDirection == MISched::Bidirectional) {
327 Policy.OnlyTopDown = false;
328 Policy.OnlyBottomUp = false;
329 }
330}
331
332bool RISCVSubtarget::useMIPSLoadStorePairs() const {
333 return UseMIPSLoadStorePairsOpt && HasVendorXMIPSLSP;
334}
335
336bool RISCVSubtarget::useMIPSCCMovInsn() const {
337 return UseMIPSCCMovInsn && HasVendorXMIPSCMov;
338}
339